1 #ifndef SPARC_CPU_H 2 #define SPARC_CPU_H 3 4 #include "qemu/bswap.h" 5 #include "cpu-qom.h" 6 #include "exec/cpu-defs.h" 7 #include "qemu/cpu-float.h" 8 9 /* 10 * From Oracle SPARC Architecture 2015: 11 * 12 * Compatibility notes: The PSO memory model described in SPARC V8 and 13 * SPARC V9 compatibility architecture specifications was never implemented 14 * in a SPARC V9 implementation and is not included in the Oracle SPARC 15 * Architecture specification. 16 * 17 * The RMO memory model described in the SPARC V9 specification was 18 * implemented in some non-Sun SPARC V9 implementations, but is not 19 * directly supported in Oracle SPARC Architecture 2015 implementations. 20 * 21 * Therefore always use TSO in QEMU. 22 * 23 * D.5 Specification of Partial Store Order (PSO) 24 * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. 25 * 26 * D.6 Specification of Total Store Order (TSO) 27 * ... PSO with the additional requirement that all [stores] are followed 28 * by an implied MEMBAR #StoreStore. 29 */ 30 #define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST) 31 32 #if !defined(TARGET_SPARC64) 33 #define TARGET_DPREGS 16 34 #else 35 #define TARGET_DPREGS 32 36 #endif 37 38 /*#define EXCP_INTERRUPT 0x100*/ 39 40 /* Windowed register indexes. */ 41 enum { 42 WREG_O0, 43 WREG_O1, 44 WREG_O2, 45 WREG_O3, 46 WREG_O4, 47 WREG_O5, 48 WREG_O6, 49 WREG_O7, 50 51 WREG_L0, 52 WREG_L1, 53 WREG_L2, 54 WREG_L3, 55 WREG_L4, 56 WREG_L5, 57 WREG_L6, 58 WREG_L7, 59 60 WREG_I0, 61 WREG_I1, 62 WREG_I2, 63 WREG_I3, 64 WREG_I4, 65 WREG_I5, 66 WREG_I6, 67 WREG_I7, 68 69 WREG_SP = WREG_O6, 70 WREG_FP = WREG_I6, 71 }; 72 73 /* trap definitions */ 74 #ifndef TARGET_SPARC64 75 #define TT_TFAULT 0x01 76 #define TT_ILL_INSN 0x02 77 #define TT_PRIV_INSN 0x03 78 #define TT_NFPU_INSN 0x04 79 #define TT_WIN_OVF 0x05 80 #define TT_WIN_UNF 0x06 81 #define TT_UNALIGNED 0x07 82 #define TT_FP_EXCP 0x08 83 #define TT_DFAULT 0x09 84 #define TT_TOVF 0x0a 85 #define TT_EXTINT 0x10 86 #define TT_CODE_ACCESS 0x21 87 #define TT_UNIMP_FLUSH 0x25 88 #define TT_DATA_ACCESS 0x29 89 #define TT_DIV_ZERO 0x2a 90 #define TT_NCP_INSN 0x24 91 #define TT_TRAP 0x80 92 #else 93 #define TT_POWER_ON_RESET 0x01 94 #define TT_TFAULT 0x08 95 #define TT_CODE_ACCESS 0x0a 96 #define TT_ILL_INSN 0x10 97 #define TT_UNIMP_FLUSH TT_ILL_INSN 98 #define TT_PRIV_INSN 0x11 99 #define TT_NFPU_INSN 0x20 100 #define TT_FP_EXCP 0x21 101 #define TT_TOVF 0x23 102 #define TT_CLRWIN 0x24 103 #define TT_DIV_ZERO 0x28 104 #define TT_DFAULT 0x30 105 #define TT_DATA_ACCESS 0x32 106 #define TT_UNALIGNED 0x34 107 #define TT_PRIV_ACT 0x37 108 #define TT_INSN_REAL_TRANSLATION_MISS 0x3e 109 #define TT_DATA_REAL_TRANSLATION_MISS 0x3f 110 #define TT_EXTINT 0x40 111 #define TT_IVEC 0x60 112 #define TT_TMISS 0x64 113 #define TT_DMISS 0x68 114 #define TT_DPROT 0x6c 115 #define TT_SPILL 0x80 116 #define TT_FILL 0xc0 117 #define TT_WOTHER (1 << 5) 118 #define TT_TRAP 0x100 119 #define TT_HTRAP 0x180 120 #endif 121 122 #define PSR_NEG_SHIFT 23 123 #define PSR_NEG (1 << PSR_NEG_SHIFT) 124 #define PSR_ZERO_SHIFT 22 125 #define PSR_ZERO (1 << PSR_ZERO_SHIFT) 126 #define PSR_OVF_SHIFT 21 127 #define PSR_OVF (1 << PSR_OVF_SHIFT) 128 #define PSR_CARRY_SHIFT 20 129 #define PSR_CARRY (1 << PSR_CARRY_SHIFT) 130 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) 131 #if !defined(TARGET_SPARC64) 132 #define PSR_EF (1<<12) 133 #define PSR_PIL 0xf00 134 #define PSR_S (1<<7) 135 #define PSR_PS (1<<6) 136 #define PSR_ET (1<<5) 137 #define PSR_CWP 0x1f 138 #endif 139 140 /* Trap base register */ 141 #define TBR_BASE_MASK 0xfffff000 142 143 #if defined(TARGET_SPARC64) 144 #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */ 145 #define PS_IG (1<<11) /* v9, zero on UA2007 */ 146 #define PS_MG (1<<10) /* v9, zero on UA2007 */ 147 #define PS_CLE (1<<9) /* UA2007 */ 148 #define PS_TLE (1<<8) /* UA2007 */ 149 #define PS_RMO (1<<7) 150 #define PS_RED (1<<5) /* v9, zero on UA2007 */ 151 #define PS_PEF (1<<4) /* enable fpu */ 152 #define PS_AM (1<<3) /* address mask */ 153 #define PS_PRIV (1<<2) 154 #define PS_IE (1<<1) 155 #define PS_AG (1<<0) /* v9, zero on UA2007 */ 156 157 #define FPRS_DL (1 << 0) 158 #define FPRS_DU (1 << 1) 159 #define FPRS_FEF (1 << 2) 160 161 #define HS_PRIV (1<<2) 162 #endif 163 164 /* Fcc */ 165 #define FSR_RD1 (1ULL << 31) 166 #define FSR_RD0 (1ULL << 30) 167 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0) 168 #define FSR_RD_NEAREST 0 169 #define FSR_RD_ZERO FSR_RD0 170 #define FSR_RD_POS FSR_RD1 171 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0) 172 173 #define FSR_NVM (1ULL << 27) 174 #define FSR_OFM (1ULL << 26) 175 #define FSR_UFM (1ULL << 25) 176 #define FSR_DZM (1ULL << 24) 177 #define FSR_NXM (1ULL << 23) 178 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) 179 #define FSR_TEM_SHIFT 23 180 181 #define FSR_NVA (1ULL << 9) 182 #define FSR_OFA (1ULL << 8) 183 #define FSR_UFA (1ULL << 7) 184 #define FSR_DZA (1ULL << 6) 185 #define FSR_NXA (1ULL << 5) 186 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) 187 #define FSR_AEXC_SHIFT 5 188 189 #define FSR_NVC (1ULL << 4) 190 #define FSR_OFC (1ULL << 3) 191 #define FSR_UFC (1ULL << 2) 192 #define FSR_DZC (1ULL << 1) 193 #define FSR_NXC (1ULL << 0) 194 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) 195 196 #define FSR_VER_SHIFT 17 197 #define FSR_VER_MASK (7 << FSR_VER_SHIFT) 198 199 #define FSR_FTT2 (1ULL << 16) 200 #define FSR_FTT1 (1ULL << 15) 201 #define FSR_FTT0 (1ULL << 14) 202 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) 203 #ifdef TARGET_SPARC64 204 #define FSR_FTT_NMASK 0xfffffffffffe3fffULL 205 #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL 206 #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL 207 #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL 208 #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL 209 #else 210 #define FSR_FTT_NMASK 0xfffe3fffULL 211 #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL 212 #define FSR_LDFSR_OLDMASK 0x000fc000ULL 213 #endif 214 #define FSR_LDFSR_MASK 0xcfc00fffULL 215 #define FSR_FTT_IEEE_EXCP (1ULL << 14) 216 #define FSR_FTT_UNIMPFPOP (3ULL << 14) 217 #define FSR_FTT_SEQ_ERROR (4ULL << 14) 218 #define FSR_FTT_INVAL_FPR (6ULL << 14) 219 220 #define FSR_FCC1_SHIFT 11 221 #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT) 222 #define FSR_FCC0_SHIFT 10 223 #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT) 224 225 /* MMU */ 226 #define MMU_E (1<<0) 227 #define MMU_NF (1<<1) 228 229 #define PTE_ENTRYTYPE_MASK 3 230 #define PTE_ACCESS_MASK 0x1c 231 #define PTE_ACCESS_SHIFT 2 232 #define PTE_PPN_SHIFT 7 233 #define PTE_ADDR_MASK 0xffffff00 234 235 #define PG_ACCESSED_BIT 5 236 #define PG_MODIFIED_BIT 6 237 #define PG_CACHE_BIT 7 238 239 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 240 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) 241 #define PG_CACHE_MASK (1 << PG_CACHE_BIT) 242 243 /* 3 <= NWINDOWS <= 32. */ 244 #define MIN_NWINDOWS 3 245 #define MAX_NWINDOWS 32 246 247 #ifdef TARGET_SPARC64 248 typedef struct trap_state { 249 uint64_t tpc; 250 uint64_t tnpc; 251 uint64_t tstate; 252 uint32_t tt; 253 } trap_state; 254 #endif 255 #define TARGET_INSN_START_EXTRA_WORDS 1 256 257 typedef struct sparc_def_t { 258 const char *name; 259 target_ulong iu_version; 260 uint32_t fpu_version; 261 uint32_t mmu_version; 262 uint32_t mmu_bm; 263 uint32_t mmu_ctpr_mask; 264 uint32_t mmu_cxr_mask; 265 uint32_t mmu_sfsr_mask; 266 uint32_t mmu_trcr_mask; 267 uint32_t mxcc_version; 268 uint32_t features; 269 uint32_t nwindows; 270 uint32_t maxtl; 271 } sparc_def_t; 272 273 #define FEATURE(X) CPU_FEATURE_BIT_##X, 274 enum { 275 #include "cpu-feature.h.inc" 276 }; 277 278 #undef FEATURE 279 #define FEATURE(X) CPU_FEATURE_##X = 1u << CPU_FEATURE_BIT_##X, 280 281 enum { 282 #include "cpu-feature.h.inc" 283 }; 284 285 #undef FEATURE 286 287 #ifndef TARGET_SPARC64 288 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 289 CPU_FEATURE_FSMULD) 290 #else 291 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 292 CPU_FEATURE_FSMULD | CPU_FEATURE_CASA | \ 293 CPU_FEATURE_VIS1 | CPU_FEATURE_VIS2) 294 enum { 295 mmu_us_12, // Ultrasparc < III (64 entry TLB) 296 mmu_us_3, // Ultrasparc III (512 entry TLB) 297 mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages) 298 mmu_sun4v, // T1, T2 299 }; 300 #endif 301 302 #define TTE_VALID_BIT (1ULL << 63) 303 #define TTE_NFO_BIT (1ULL << 60) 304 #define TTE_IE_BIT (1ULL << 59) 305 #define TTE_USED_BIT (1ULL << 41) 306 #define TTE_LOCKED_BIT (1ULL << 6) 307 #define TTE_SIDEEFFECT_BIT (1ULL << 3) 308 #define TTE_PRIV_BIT (1ULL << 2) 309 #define TTE_W_OK_BIT (1ULL << 1) 310 #define TTE_GLOBAL_BIT (1ULL << 0) 311 312 #define TTE_NFO_BIT_UA2005 (1ULL << 62) 313 #define TTE_USED_BIT_UA2005 (1ULL << 47) 314 #define TTE_LOCKED_BIT_UA2005 (1ULL << 61) 315 #define TTE_SIDEEFFECT_BIT_UA2005 (1ULL << 11) 316 #define TTE_PRIV_BIT_UA2005 (1ULL << 8) 317 #define TTE_W_OK_BIT_UA2005 (1ULL << 6) 318 319 #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) 320 #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT) 321 #define TTE_IS_IE(tte) ((tte) & TTE_IE_BIT) 322 #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) 323 #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) 324 #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) 325 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 326 #define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT) 327 #define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT) 328 329 #define TTE_IS_NFO_UA2005(tte) ((tte) & TTE_NFO_BIT_UA2005) 330 #define TTE_IS_USED_UA2005(tte) ((tte) & TTE_USED_BIT_UA2005) 331 #define TTE_IS_LOCKED_UA2005(tte) ((tte) & TTE_LOCKED_BIT_UA2005) 332 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 333 #define TTE_IS_PRIV_UA2005(tte) ((tte) & TTE_PRIV_BIT_UA2005) 334 #define TTE_IS_W_OK_UA2005(tte) ((tte) & TTE_W_OK_BIT_UA2005) 335 336 #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT) 337 338 #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT) 339 #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT) 340 341 #define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL) 342 #define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL) 343 #define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL) 344 345 /* UltraSPARC T1 specific */ 346 #define TLB_UST1_IS_REAL_BIT (1ULL << 9) /* Real translation entry */ 347 #define TLB_UST1_IS_SUN4V_BIT (1ULL << 10) /* sun4u/sun4v TTE format switch */ 348 349 #define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */ 350 #define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */ 351 #define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */ 352 #define SFSR_FT_VA_DMMU_BIT (1ULL << 12) /* USIIi VA out of range (DMMU) */ 353 #define SFSR_FT_NFO_BIT (1ULL << 11) /* NFO page access */ 354 #define SFSR_FT_ILL_BIT (1ULL << 10) /* illegal LDA/STA ASI */ 355 #define SFSR_FT_ATOMIC_BIT (1ULL << 9) /* atomic op on noncacheable area */ 356 #define SFSR_FT_NF_E_BIT (1ULL << 8) /* NF access on side effect area */ 357 #define SFSR_FT_PRIV_BIT (1ULL << 7) /* privilege violation */ 358 #define SFSR_PR_BIT (1ULL << 3) /* privilege mode */ 359 #define SFSR_WRITE_BIT (1ULL << 2) /* write access mode */ 360 #define SFSR_OW_BIT (1ULL << 1) /* status overwritten */ 361 #define SFSR_VALID_BIT (1ULL << 0) /* status valid */ 362 363 #define SFSR_ASI_SHIFT 16 /* 23:16 ASI value */ 364 #define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT) 365 #define SFSR_CT_PRIMARY (0ULL << 4) /* 5:4 context type */ 366 #define SFSR_CT_SECONDARY (1ULL << 4) 367 #define SFSR_CT_NUCLEUS (2ULL << 4) 368 #define SFSR_CT_NOTRANS (3ULL << 4) 369 #define SFSR_CT_MASK (3ULL << 4) 370 371 /* Leon3 cache control */ 372 373 /* Cache control: emulate the behavior of cache control registers but without 374 any effect on the emulated */ 375 376 #define CACHE_STATE_MASK 0x3 377 #define CACHE_DISABLED 0x0 378 #define CACHE_FROZEN 0x1 379 #define CACHE_ENABLED 0x3 380 381 /* Cache Control register fields */ 382 383 #define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */ 384 #define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */ 385 #define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */ 386 #define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */ 387 #define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */ 388 #define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */ 389 #define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */ 390 #define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */ 391 392 #define CONVERT_BIT(X, SRC, DST) \ 393 (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC)) 394 395 typedef struct SparcTLBEntry { 396 uint64_t tag; 397 uint64_t tte; 398 } SparcTLBEntry; 399 400 struct CPUTimer 401 { 402 const char *name; 403 uint32_t frequency; 404 uint32_t disabled; 405 uint64_t disabled_mask; 406 uint32_t npt; 407 uint64_t npt_mask; 408 int64_t clock_offset; 409 QEMUTimer *qtimer; 410 }; 411 412 typedef struct CPUTimer CPUTimer; 413 414 typedef struct CPUArchState CPUSPARCState; 415 #if defined(TARGET_SPARC64) 416 typedef union { 417 uint64_t mmuregs[16]; 418 struct { 419 uint64_t tsb_tag_target; 420 uint64_t mmu_primary_context; 421 uint64_t mmu_secondary_context; 422 uint64_t sfsr; 423 uint64_t sfar; 424 uint64_t tsb; 425 uint64_t tag_access; 426 uint64_t virtual_watchpoint; 427 uint64_t physical_watchpoint; 428 uint64_t sun4v_ctx_config[2]; 429 uint64_t sun4v_tsb_pointers[4]; 430 }; 431 } SparcV9MMU; 432 #endif 433 struct CPUArchState { 434 target_ulong gregs[8]; /* general registers */ 435 target_ulong *regwptr; /* pointer to current register window */ 436 target_ulong pc; /* program counter */ 437 target_ulong npc; /* next program counter */ 438 target_ulong y; /* multiply/divide register */ 439 440 /* 441 * Bit 31 is for icc, bit 63 for xcc. 442 * Other bits are garbage. 443 */ 444 target_long cc_N; 445 target_long cc_V; 446 447 /* 448 * Z is represented as == 0; any non-zero value is !Z. 449 * For sparc64, the high 32-bits of icc.Z are garbage. 450 */ 451 target_ulong icc_Z; 452 #ifdef TARGET_SPARC64 453 target_ulong xcc_Z; 454 #endif 455 456 /* 457 * For sparc32, icc.C is boolean. 458 * For sparc64, xcc.C is boolean; 459 * icc.C is bit 32 with other bits garbage. 460 */ 461 target_ulong icc_C; 462 #ifdef TARGET_SPARC64 463 target_ulong xcc_C; 464 #endif 465 466 target_ulong cond; /* conditional branch result (XXX: save it in a 467 temporary register when possible) */ 468 469 /* FPU State Register, in parts */ 470 target_ulong fsr; /* rm, tem, aexc, fcc* */ 471 uint32_t fsr_cexc_ftt; /* cexc, ftt */ 472 473 CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ 474 uint32_t cwp; /* index of current register window (extracted 475 from PSR) */ 476 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32) 477 uint32_t wim; /* window invalid mask */ 478 #endif 479 target_ulong tbr; /* trap base register */ 480 #if !defined(TARGET_SPARC64) 481 int psrs; /* supervisor mode (extracted from PSR) */ 482 int psrps; /* previous supervisor mode */ 483 int psret; /* enable traps */ 484 #endif 485 uint32_t psrpil; /* interrupt blocking level */ 486 uint32_t pil_in; /* incoming interrupt level bitmap */ 487 #if !defined(TARGET_SPARC64) 488 int psref; /* enable fpu */ 489 #endif 490 int interrupt_index; 491 /* NOTE: we allow 8 more registers to handle wrapping */ 492 target_ulong regbase[MAX_NWINDOWS * 16 + 8]; 493 494 /* Fields up to this point are cleared by a CPU reset */ 495 struct {} end_reset_fields; 496 497 /* Fields from here on are preserved across CPU reset. */ 498 target_ulong version; 499 uint32_t nwindows; 500 501 /* MMU regs */ 502 #if defined(TARGET_SPARC64) 503 uint64_t lsu; 504 #define DMMU_E 0x8 505 #define IMMU_E 0x4 506 SparcV9MMU immu; 507 SparcV9MMU dmmu; 508 SparcTLBEntry itlb[64]; 509 SparcTLBEntry dtlb[64]; 510 uint32_t mmu_version; 511 #else 512 uint32_t mmuregs[32]; 513 uint64_t mxccdata[4]; 514 uint64_t mxccregs[8]; 515 uint32_t mmubpctrv, mmubpctrc, mmubpctrs; 516 uint64_t mmubpaction; 517 uint64_t mmubpregs[4]; 518 uint64_t prom_addr; 519 #endif 520 float_status fp_status; 521 #if defined(TARGET_SPARC64) 522 #define MAXTL_MAX 8 523 #define MAXTL_MASK (MAXTL_MAX - 1) 524 trap_state ts[MAXTL_MAX]; 525 uint32_t asi; 526 uint32_t pstate; 527 uint32_t tl; 528 uint32_t maxtl; 529 uint32_t cansave, canrestore, otherwin, wstate, cleanwin; 530 uint64_t agregs[8]; /* alternate general registers */ 531 uint64_t bgregs[8]; /* backup for normal global registers */ 532 uint64_t igregs[8]; /* interrupt general registers */ 533 uint64_t mgregs[8]; /* mmu general registers */ 534 uint64_t glregs[8 * MAXTL_MAX]; 535 uint32_t fprs; 536 uint64_t tick_cmpr, stick_cmpr; 537 CPUTimer *tick, *stick; 538 #define TICK_NPT_MASK 0x8000000000000000ULL 539 #define TICK_INT_DIS 0x8000000000000000ULL 540 uint64_t gsr; 541 uint32_t gl; // UA2005 542 /* UA 2005 hyperprivileged registers */ 543 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; 544 uint64_t scratch[8]; 545 CPUTimer *hstick; // UA 2005 546 /* Interrupt vector registers */ 547 uint64_t ivec_status; 548 uint64_t ivec_data[3]; 549 uint32_t softint; 550 #define SOFTINT_TIMER 1 551 #define SOFTINT_STIMER (1 << 16) 552 #define SOFTINT_INTRMASK (0xFFFE) 553 #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER) 554 #endif 555 sparc_def_t def; 556 557 void *irq_manager; 558 void (*qemu_irq_ack)(CPUSPARCState *env, int intno); 559 560 /* Leon3 cache control */ 561 uint32_t cache_control; 562 }; 563 564 /** 565 * SPARCCPU: 566 * @env: #CPUSPARCState 567 * 568 * A SPARC CPU. 569 */ 570 struct ArchCPU { 571 CPUState parent_obj; 572 573 CPUSPARCState env; 574 }; 575 576 /** 577 * SPARCCPUClass: 578 * @parent_realize: The parent class' realize handler. 579 * @parent_phases: The parent class' reset phase handlers. 580 * 581 * A SPARC CPU model. 582 */ 583 struct SPARCCPUClass { 584 CPUClass parent_class; 585 586 DeviceRealize parent_realize; 587 ResettablePhases parent_phases; 588 sparc_def_t *cpu_def; 589 }; 590 591 #ifndef CONFIG_USER_ONLY 592 extern const VMStateDescription vmstate_sparc_cpu; 593 594 hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 595 #endif 596 597 void sparc_cpu_do_interrupt(CPUState *cpu); 598 int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 599 int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 600 G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 601 MMUAccessType access_type, 602 int mmu_idx, 603 uintptr_t retaddr); 604 G_NORETURN void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t); 605 606 /* cpu_init.c */ 607 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); 608 void sparc_cpu_list(void); 609 /* mmu_helper.c */ 610 bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 611 MMUAccessType access_type, int mmu_idx, 612 bool probe, uintptr_t retaddr); 613 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); 614 void dump_mmu(CPUSPARCState *env); 615 616 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 617 int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 618 uint8_t *buf, int len, bool is_write); 619 #endif 620 621 622 /* translate.c */ 623 void sparc_tcg_init(void); 624 void sparc_restore_state_to_opc(CPUState *cs, 625 const TranslationBlock *tb, 626 const uint64_t *data); 627 628 /* fop_helper.c */ 629 target_ulong cpu_get_fsr(CPUSPARCState *); 630 void cpu_put_fsr(CPUSPARCState *, target_ulong); 631 632 /* win_helper.c */ 633 target_ulong cpu_get_psr(CPUSPARCState *env1); 634 void cpu_put_psr(CPUSPARCState *env1, target_ulong val); 635 void cpu_put_psr_icc(CPUSPARCState *env1, target_ulong val); 636 void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val); 637 #ifdef TARGET_SPARC64 638 void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate); 639 void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl); 640 #endif 641 int cpu_cwp_inc(CPUSPARCState *env1, int cwp); 642 int cpu_cwp_dec(CPUSPARCState *env1, int cwp); 643 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); 644 645 /* sun4m.c, sun4u.c */ 646 void cpu_check_irqs(CPUSPARCState *env); 647 648 #if defined (TARGET_SPARC64) 649 650 static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) 651 { 652 return (x & mask) == (y & mask); 653 } 654 655 #define MMU_CONTEXT_BITS 13 656 #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1) 657 658 static inline int tlb_compare_context(const SparcTLBEntry *tlb, 659 uint64_t context) 660 { 661 return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK); 662 } 663 664 #endif 665 666 /* cpu-exec.c */ 667 #if !defined(CONFIG_USER_ONLY) 668 void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 669 vaddr addr, unsigned size, 670 MMUAccessType access_type, 671 int mmu_idx, MemTxAttrs attrs, 672 MemTxResult response, uintptr_t retaddr); 673 #if defined(TARGET_SPARC64) 674 hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, 675 int mmu_idx); 676 #endif 677 #endif 678 679 #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU 680 681 #define cpu_list sparc_cpu_list 682 683 /* MMU modes definitions */ 684 #if defined (TARGET_SPARC64) 685 #define MMU_USER_IDX 0 686 #define MMU_USER_SECONDARY_IDX 1 687 #define MMU_KERNEL_IDX 2 688 #define MMU_KERNEL_SECONDARY_IDX 3 689 #define MMU_NUCLEUS_IDX 4 690 #define MMU_PHYS_IDX 5 691 #else 692 #define MMU_USER_IDX 0 693 #define MMU_KERNEL_IDX 1 694 #define MMU_PHYS_IDX 2 695 #endif 696 697 #if defined (TARGET_SPARC64) 698 static inline int cpu_has_hypervisor(CPUSPARCState *env1) 699 { 700 return env1->def.features & CPU_FEATURE_HYPV; 701 } 702 703 static inline int cpu_hypervisor_mode(CPUSPARCState *env1) 704 { 705 return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV); 706 } 707 708 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 709 { 710 return env1->pstate & PS_PRIV; 711 } 712 #else 713 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 714 { 715 return env1->psrs; 716 } 717 #endif 718 719 static inline int cpu_interrupts_enabled(CPUSPARCState *env1) 720 { 721 #if !defined (TARGET_SPARC64) 722 if (env1->psret != 0) 723 return 1; 724 #else 725 if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) { 726 return 1; 727 } 728 #endif 729 730 return 0; 731 } 732 733 static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) 734 { 735 #if !defined(TARGET_SPARC64) 736 /* level 15 is non-maskable on sparc v8 */ 737 return pil == 15 || pil > env1->psrpil; 738 #else 739 return pil > env1->psrpil; 740 #endif 741 } 742 743 #include "exec/cpu-all.h" 744 745 #ifdef TARGET_SPARC64 746 /* sun4u.c */ 747 void cpu_tick_set_count(CPUTimer *timer, uint64_t count); 748 uint64_t cpu_tick_get_count(CPUTimer *timer); 749 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit); 750 trap_state* cpu_tsptr(CPUSPARCState* env); 751 #endif 752 753 #define TB_FLAG_MMU_MASK 7 754 #define TB_FLAG_FPU_ENABLED (1 << 4) 755 #define TB_FLAG_AM_ENABLED (1 << 5) 756 #define TB_FLAG_SUPER (1 << 6) 757 #define TB_FLAG_HYPER (1 << 7) 758 #define TB_FLAG_ASI_SHIFT 24 759 760 static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, 761 uint64_t *cs_base, uint32_t *pflags) 762 { 763 uint32_t flags; 764 *pc = env->pc; 765 *cs_base = env->npc; 766 flags = cpu_mmu_index(env_cpu(env), false); 767 #ifndef CONFIG_USER_ONLY 768 if (cpu_supervisor_mode(env)) { 769 flags |= TB_FLAG_SUPER; 770 } 771 #endif 772 #ifdef TARGET_SPARC64 773 #ifndef CONFIG_USER_ONLY 774 if (cpu_hypervisor_mode(env)) { 775 flags |= TB_FLAG_HYPER; 776 } 777 #endif 778 if (env->pstate & PS_AM) { 779 flags |= TB_FLAG_AM_ENABLED; 780 } 781 if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) { 782 flags |= TB_FLAG_FPU_ENABLED; 783 } 784 flags |= env->asi << TB_FLAG_ASI_SHIFT; 785 #else 786 if (env->psref) { 787 flags |= TB_FLAG_FPU_ENABLED; 788 } 789 #endif 790 *pflags = flags; 791 } 792 793 static inline bool tb_fpu_enabled(int tb_flags) 794 { 795 #if defined(CONFIG_USER_ONLY) 796 return true; 797 #else 798 return tb_flags & TB_FLAG_FPU_ENABLED; 799 #endif 800 } 801 802 static inline bool tb_am_enabled(int tb_flags) 803 { 804 #ifndef TARGET_SPARC64 805 return false; 806 #else 807 return tb_flags & TB_FLAG_AM_ENABLED; 808 #endif 809 } 810 811 #ifdef TARGET_SPARC64 812 /* win_helper.c */ 813 target_ulong cpu_get_ccr(CPUSPARCState *env1); 814 void cpu_put_ccr(CPUSPARCState *env1, target_ulong val); 815 target_ulong cpu_get_cwp64(CPUSPARCState *env1); 816 void cpu_put_cwp64(CPUSPARCState *env1, int cwp); 817 818 static inline uint64_t sparc64_tstate(CPUSPARCState *env) 819 { 820 uint64_t tstate = (cpu_get_ccr(env) << 32) | 821 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | 822 cpu_get_cwp64(env); 823 824 if (env->def.features & CPU_FEATURE_GL) { 825 tstate |= (env->gl & 7ULL) << 40; 826 } 827 return tstate; 828 } 829 #endif 830 831 #endif 832