1 /* 2 * S390x MMU related functions 3 * 4 * Copyright (c) 2011 Alexander Graf 5 * Copyright (c) 2015 Thomas Huth, IBM Corporation 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/error-report.h" 20 #include "exec/address-spaces.h" 21 #include "cpu.h" 22 #include "internal.h" 23 #include "kvm_s390x.h" 24 #include "sysemu/kvm.h" 25 #include "sysemu/tcg.h" 26 #include "exec/exec-all.h" 27 #include "trace.h" 28 #include "hw/hw.h" 29 #include "hw/s390x/storage-keys.h" 30 31 /* Fetch/store bits in the translation exception code: */ 32 #define FS_READ 0x800 33 #define FS_WRITE 0x400 34 35 static void trigger_access_exception(CPUS390XState *env, uint32_t type, 36 uint32_t ilen, uint64_t tec) 37 { 38 S390CPU *cpu = env_archcpu(env); 39 40 if (kvm_enabled()) { 41 kvm_s390_access_exception(cpu, type, tec); 42 } else { 43 CPUState *cs = env_cpu(env); 44 if (type != PGM_ADDRESSING) { 45 stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec); 46 } 47 trigger_pgm_exception(env, type, ilen); 48 } 49 } 50 51 /* check whether the address would be proteted by Low-Address Protection */ 52 static bool is_low_address(uint64_t addr) 53 { 54 return addr <= 511 || (addr >= 4096 && addr <= 4607); 55 } 56 57 /* check whether Low-Address Protection is enabled for mmu_translate() */ 58 static bool lowprot_enabled(const CPUS390XState *env, uint64_t asc) 59 { 60 if (!(env->cregs[0] & CR0_LOWPROT)) { 61 return false; 62 } 63 if (!(env->psw.mask & PSW_MASK_DAT)) { 64 return true; 65 } 66 67 /* Check the private-space control bit */ 68 switch (asc) { 69 case PSW_ASC_PRIMARY: 70 return !(env->cregs[1] & ASCE_PRIVATE_SPACE); 71 case PSW_ASC_SECONDARY: 72 return !(env->cregs[7] & ASCE_PRIVATE_SPACE); 73 case PSW_ASC_HOME: 74 return !(env->cregs[13] & ASCE_PRIVATE_SPACE); 75 default: 76 /* We don't support access register mode */ 77 error_report("unsupported addressing mode"); 78 exit(1); 79 } 80 } 81 82 /** 83 * Translate real address to absolute (= physical) 84 * address by taking care of the prefix mapping. 85 */ 86 target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr) 87 { 88 if (raddr < 0x2000) { 89 return raddr + env->psa; /* Map the lowcore. */ 90 } else if (raddr >= env->psa && raddr < env->psa + 0x2000) { 91 return raddr - env->psa; /* Map the 0 page. */ 92 } 93 return raddr; 94 } 95 96 static inline bool read_table_entry(CPUS390XState *env, hwaddr gaddr, 97 uint64_t *entry) 98 { 99 CPUState *cs = env_cpu(env); 100 101 /* 102 * According to the PoP, these table addresses are "unpredictably real 103 * or absolute". Also, "it is unpredictable whether the address wraps 104 * or an addressing exception is recognized". 105 * 106 * We treat them as absolute addresses and don't wrap them. 107 */ 108 if (unlikely(address_space_read(cs->as, gaddr, MEMTXATTRS_UNSPECIFIED, 109 (uint8_t *)entry, sizeof(*entry)) != 110 MEMTX_OK)) { 111 return false; 112 } 113 *entry = be64_to_cpu(*entry); 114 return true; 115 } 116 117 static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, 118 uint64_t asc, uint64_t asce, target_ulong *raddr, 119 int *flags, int rw, bool exc) 120 { 121 const bool edat1 = (env->cregs[0] & CR0_EDAT) && 122 s390_has_feat(S390_FEAT_EDAT); 123 const bool edat2 = edat1 && s390_has_feat(S390_FEAT_EDAT_2); 124 const int asce_tl = asce & ASCE_TABLE_LENGTH; 125 const int asce_p = asce & ASCE_PRIVATE_SPACE; 126 hwaddr gaddr = asce & ASCE_ORIGIN; 127 uint64_t entry; 128 129 if (asce & ASCE_REAL_SPACE) { 130 /* direct mapping */ 131 *raddr = vaddr; 132 return 0; 133 } 134 135 switch (asce & ASCE_TYPE_MASK) { 136 case ASCE_TYPE_REGION1: 137 if (VADDR_REGION1_TL(vaddr) > asce_tl) { 138 return PGM_REG_FIRST_TRANS; 139 } 140 gaddr += VADDR_REGION1_TX(vaddr) * 8; 141 break; 142 case ASCE_TYPE_REGION2: 143 if (VADDR_REGION1_TX(vaddr)) { 144 return PGM_ASCE_TYPE; 145 } 146 if (VADDR_REGION2_TL(vaddr) > asce_tl) { 147 return PGM_REG_SEC_TRANS; 148 } 149 gaddr += VADDR_REGION2_TX(vaddr) * 8; 150 break; 151 case ASCE_TYPE_REGION3: 152 if (VADDR_REGION1_TX(vaddr) || VADDR_REGION2_TX(vaddr)) { 153 return PGM_ASCE_TYPE; 154 } 155 if (VADDR_REGION3_TL(vaddr) > asce_tl) { 156 return PGM_REG_THIRD_TRANS; 157 } 158 gaddr += VADDR_REGION3_TX(vaddr) * 8; 159 break; 160 case ASCE_TYPE_SEGMENT: 161 if (VADDR_REGION1_TX(vaddr) || VADDR_REGION2_TX(vaddr) || 162 VADDR_REGION3_TX(vaddr)) { 163 return PGM_ASCE_TYPE; 164 } 165 if (VADDR_SEGMENT_TL(vaddr) > asce_tl) { 166 return PGM_SEGMENT_TRANS; 167 } 168 gaddr += VADDR_SEGMENT_TX(vaddr) * 8; 169 break; 170 } 171 172 switch (asce & ASCE_TYPE_MASK) { 173 case ASCE_TYPE_REGION1: 174 if (!read_table_entry(env, gaddr, &entry)) { 175 return PGM_ADDRESSING; 176 } 177 if (entry & REGION_ENTRY_I) { 178 return PGM_REG_FIRST_TRANS; 179 } 180 if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION1) { 181 return PGM_TRANS_SPEC; 182 } 183 if (VADDR_REGION2_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 || 184 VADDR_REGION2_TL(vaddr) > (entry & REGION_ENTRY_TL)) { 185 return PGM_REG_SEC_TRANS; 186 } 187 if (edat1 && (entry & REGION_ENTRY_P)) { 188 *flags &= ~PAGE_WRITE; 189 } 190 gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION2_TX(vaddr) * 8; 191 /* fall through */ 192 case ASCE_TYPE_REGION2: 193 if (!read_table_entry(env, gaddr, &entry)) { 194 return PGM_ADDRESSING; 195 } 196 if (entry & REGION_ENTRY_I) { 197 return PGM_REG_SEC_TRANS; 198 } 199 if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION2) { 200 return PGM_TRANS_SPEC; 201 } 202 if (VADDR_REGION3_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 || 203 VADDR_REGION3_TL(vaddr) > (entry & REGION_ENTRY_TL)) { 204 return PGM_REG_THIRD_TRANS; 205 } 206 if (edat1 && (entry & REGION_ENTRY_P)) { 207 *flags &= ~PAGE_WRITE; 208 } 209 gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION3_TX(vaddr) * 8; 210 /* fall through */ 211 case ASCE_TYPE_REGION3: 212 if (!read_table_entry(env, gaddr, &entry)) { 213 return PGM_ADDRESSING; 214 } 215 if (entry & REGION_ENTRY_I) { 216 return PGM_REG_THIRD_TRANS; 217 } 218 if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION3) { 219 return PGM_TRANS_SPEC; 220 } 221 if (edat2 && (entry & REGION3_ENTRY_CR) && asce_p) { 222 return PGM_TRANS_SPEC; 223 } 224 if (edat1 && (entry & REGION_ENTRY_P)) { 225 *flags &= ~PAGE_WRITE; 226 } 227 if (edat2 && (entry & REGION3_ENTRY_FC)) { 228 *raddr = (entry & REGION3_ENTRY_RFAA) | 229 (vaddr & ~REGION3_ENTRY_RFAA); 230 return 0; 231 } 232 if (VADDR_SEGMENT_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 || 233 VADDR_SEGMENT_TL(vaddr) > (entry & REGION_ENTRY_TL)) { 234 return PGM_SEGMENT_TRANS; 235 } 236 gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_SEGMENT_TX(vaddr) * 8; 237 /* fall through */ 238 case ASCE_TYPE_SEGMENT: 239 if (!read_table_entry(env, gaddr, &entry)) { 240 return PGM_ADDRESSING; 241 } 242 if (entry & SEGMENT_ENTRY_I) { 243 return PGM_SEGMENT_TRANS; 244 } 245 if ((entry & SEGMENT_ENTRY_TT) != SEGMENT_ENTRY_TT_SEGMENT) { 246 return PGM_TRANS_SPEC; 247 } 248 if ((entry & SEGMENT_ENTRY_CS) && asce_p) { 249 return PGM_TRANS_SPEC; 250 } 251 if (entry & SEGMENT_ENTRY_P) { 252 *flags &= ~PAGE_WRITE; 253 } 254 if (edat1 && (entry & SEGMENT_ENTRY_FC)) { 255 *raddr = (entry & SEGMENT_ENTRY_SFAA) | 256 (vaddr & ~SEGMENT_ENTRY_SFAA); 257 return 0; 258 } 259 gaddr = (entry & SEGMENT_ENTRY_ORIGIN) + VADDR_PAGE_TX(vaddr) * 8; 260 break; 261 } 262 263 if (!read_table_entry(env, gaddr, &entry)) { 264 return PGM_ADDRESSING; 265 } 266 if (entry & PAGE_ENTRY_I) { 267 return PGM_PAGE_TRANS; 268 } 269 if (entry & PAGE_ENTRY_0) { 270 return PGM_TRANS_SPEC; 271 } 272 if (entry & PAGE_ENTRY_P) { 273 *flags &= ~PAGE_WRITE; 274 } 275 276 *raddr = entry & TARGET_PAGE_MASK; 277 return 0; 278 } 279 280 static void mmu_handle_skey(target_ulong addr, int rw, int *flags) 281 { 282 static S390SKeysClass *skeyclass; 283 static S390SKeysState *ss; 284 uint8_t key; 285 int rc; 286 287 if (unlikely(addr >= ram_size)) { 288 return; 289 } 290 291 if (unlikely(!ss)) { 292 ss = s390_get_skeys_device(); 293 skeyclass = S390_SKEYS_GET_CLASS(ss); 294 } 295 296 /* 297 * Whenever we create a new TLB entry, we set the storage key reference 298 * bit. In case we allow write accesses, we set the storage key change 299 * bit. Whenever the guest changes the storage key, we have to flush the 300 * TLBs of all CPUs (the whole TLB or all affected entries), so that the 301 * next reference/change will result in an MMU fault and make us properly 302 * update the storage key here. 303 * 304 * Note 1: "record of references ... is not necessarily accurate", 305 * "change bit may be set in case no storing has occurred". 306 * -> We can set reference/change bits even on exceptions. 307 * Note 2: certain accesses seem to ignore storage keys. For example, 308 * DAT translation does not set reference bits for table accesses. 309 * 310 * TODO: key-controlled protection. Only CPU accesses make use of the 311 * PSW key. CSS accesses are different - we have to pass in the key. 312 * 313 * TODO: we have races between getting and setting the key. 314 */ 315 rc = skeyclass->get_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key); 316 if (rc) { 317 trace_get_skeys_nonzero(rc); 318 return; 319 } 320 321 switch (rw) { 322 case MMU_DATA_LOAD: 323 case MMU_INST_FETCH: 324 /* 325 * The TLB entry has to remain write-protected on read-faults if 326 * the storage key does not indicate a change already. Otherwise 327 * we might miss setting the change bit on write accesses. 328 */ 329 if (!(key & SK_C)) { 330 *flags &= ~PAGE_WRITE; 331 } 332 break; 333 case MMU_DATA_STORE: 334 key |= SK_C; 335 break; 336 default: 337 g_assert_not_reached(); 338 } 339 340 /* Any store/fetch sets the reference bit */ 341 key |= SK_R; 342 343 rc = skeyclass->set_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key); 344 if (rc) { 345 trace_set_skeys_nonzero(rc); 346 } 347 } 348 349 /** 350 * Translate a virtual (logical) address into a physical (absolute) address. 351 * @param vaddr the virtual address 352 * @param rw 0 = read, 1 = write, 2 = code fetch 353 * @param asc address space control (one of the PSW_ASC_* modes) 354 * @param raddr the translated address is stored to this pointer 355 * @param flags the PAGE_READ/WRITE/EXEC flags are stored to this pointer 356 * @param exc true = inject a program check if a fault occurred 357 * @return 0 if the translation was successful, -1 if a fault occurred 358 */ 359 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc, 360 target_ulong *raddr, int *flags, bool exc) 361 { 362 /* Code accesses have an undefined ilc, let's use 2 bytes. */ 363 const int ilen = (rw == MMU_INST_FETCH) ? 2 : ILEN_AUTO; 364 uint64_t tec = (vaddr & TARGET_PAGE_MASK) | (asc >> 46) | 365 (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ); 366 uint64_t asce; 367 int r; 368 369 370 *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 371 if (is_low_address(vaddr & TARGET_PAGE_MASK) && lowprot_enabled(env, asc)) { 372 /* 373 * If any part of this page is currently protected, make sure the 374 * TLB entry will not be reused. 375 * 376 * As the protected range is always the first 512 bytes of the 377 * two first pages, we are able to catch all writes to these areas 378 * just by looking at the start address (triggering the tlb miss). 379 */ 380 *flags |= PAGE_WRITE_INV; 381 if (is_low_address(vaddr) && rw == MMU_DATA_STORE) { 382 if (exc) { 383 /* LAP sets bit 56 */ 384 tec |= 0x80; 385 trigger_access_exception(env, PGM_PROTECTION, ilen, tec); 386 } 387 return -EACCES; 388 } 389 } 390 391 vaddr &= TARGET_PAGE_MASK; 392 393 if (!(env->psw.mask & PSW_MASK_DAT)) { 394 *raddr = vaddr; 395 goto nodat; 396 } 397 398 switch (asc) { 399 case PSW_ASC_PRIMARY: 400 asce = env->cregs[1]; 401 break; 402 case PSW_ASC_HOME: 403 asce = env->cregs[13]; 404 break; 405 case PSW_ASC_SECONDARY: 406 asce = env->cregs[7]; 407 break; 408 case PSW_ASC_ACCREG: 409 default: 410 hw_error("guest switched to unknown asc mode\n"); 411 break; 412 } 413 414 /* perform the DAT translation */ 415 r = mmu_translate_asce(env, vaddr, asc, asce, raddr, flags, rw, exc); 416 if (unlikely(r)) { 417 if (exc) { 418 trigger_access_exception(env, r, ilen, tec); 419 } 420 return -1; 421 } 422 423 /* check for DAT protection */ 424 if (unlikely(rw == MMU_DATA_STORE && !(*flags & PAGE_WRITE))) { 425 if (exc) { 426 /* DAT sets bit 61 only */ 427 tec |= 0x4; 428 trigger_access_exception(env, PGM_PROTECTION, ilen, tec); 429 } 430 return -1; 431 } 432 433 nodat: 434 /* Convert real address -> absolute address */ 435 *raddr = mmu_real2abs(env, *raddr); 436 437 mmu_handle_skey(*raddr, rw, flags); 438 return 0; 439 } 440 441 /** 442 * translate_pages: Translate a set of consecutive logical page addresses 443 * to absolute addresses. This function is used for TCG and old KVM without 444 * the MEMOP interface. 445 */ 446 static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages, 447 target_ulong *pages, bool is_write) 448 { 449 uint64_t asc = cpu->env.psw.mask & PSW_MASK_ASC; 450 CPUS390XState *env = &cpu->env; 451 int ret, i, pflags; 452 453 for (i = 0; i < nr_pages; i++) { 454 ret = mmu_translate(env, addr, is_write, asc, &pages[i], &pflags, true); 455 if (ret) { 456 return ret; 457 } 458 if (!address_space_access_valid(&address_space_memory, pages[i], 459 TARGET_PAGE_SIZE, is_write, 460 MEMTXATTRS_UNSPECIFIED)) { 461 trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0); 462 return -EFAULT; 463 } 464 addr += TARGET_PAGE_SIZE; 465 } 466 467 return 0; 468 } 469 470 /** 471 * s390_cpu_virt_mem_rw: 472 * @laddr: the logical start address 473 * @ar: the access register number 474 * @hostbuf: buffer in host memory. NULL = do only checks w/o copying 475 * @len: length that should be transferred 476 * @is_write: true = write, false = read 477 * Returns: 0 on success, non-zero if an exception occurred 478 * 479 * Copy from/to guest memory using logical addresses. Note that we inject a 480 * program interrupt in case there is an error while accessing the memory. 481 * 482 * This function will always return (also for TCG), make sure to call 483 * s390_cpu_virt_mem_handle_exc() to properly exit the CPU loop. 484 */ 485 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf, 486 int len, bool is_write) 487 { 488 int currlen, nr_pages, i; 489 target_ulong *pages; 490 int ret; 491 492 if (kvm_enabled()) { 493 ret = kvm_s390_mem_op(cpu, laddr, ar, hostbuf, len, is_write); 494 if (ret >= 0) { 495 return ret; 496 } 497 } 498 499 nr_pages = (((laddr & ~TARGET_PAGE_MASK) + len - 1) >> TARGET_PAGE_BITS) 500 + 1; 501 pages = g_malloc(nr_pages * sizeof(*pages)); 502 503 ret = translate_pages(cpu, laddr, nr_pages, pages, is_write); 504 if (ret == 0 && hostbuf != NULL) { 505 /* Copy data by stepping through the area page by page */ 506 for (i = 0; i < nr_pages; i++) { 507 currlen = MIN(len, TARGET_PAGE_SIZE - (laddr % TARGET_PAGE_SIZE)); 508 cpu_physical_memory_rw(pages[i] | (laddr & ~TARGET_PAGE_MASK), 509 hostbuf, currlen, is_write); 510 laddr += currlen; 511 hostbuf += currlen; 512 len -= currlen; 513 } 514 } 515 516 g_free(pages); 517 return ret; 518 } 519 520 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra) 521 { 522 /* KVM will handle the interrupt automatically, TCG has to exit the TB */ 523 #ifdef CONFIG_TCG 524 if (tcg_enabled()) { 525 cpu_loop_exit_restore(CPU(cpu), ra); 526 } 527 #endif 528 } 529 530 /** 531 * Translate a real address into a physical (absolute) address. 532 * @param raddr the real address 533 * @param rw 0 = read, 1 = write, 2 = code fetch 534 * @param addr the translated address is stored to this pointer 535 * @param flags the PAGE_READ/WRITE/EXEC flags are stored to this pointer 536 * @return 0 if the translation was successful, < 0 if a fault occurred 537 */ 538 int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw, 539 target_ulong *addr, int *flags) 540 { 541 /* Code accesses have an undefined ilc, let's use 2 bytes. */ 542 uint64_t tec = (raddr & TARGET_PAGE_MASK) | 543 (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ); 544 const bool lowprot_enabled = env->cregs[0] & CR0_LOWPROT; 545 546 *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 547 if (is_low_address(raddr & TARGET_PAGE_MASK) && lowprot_enabled) { 548 /* see comment in mmu_translate() how this works */ 549 *flags |= PAGE_WRITE_INV; 550 if (is_low_address(raddr) && rw == MMU_DATA_STORE) { 551 /* LAP sets bit 56 */ 552 tec |= 0x80; 553 trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, tec); 554 return -EACCES; 555 } 556 } 557 558 *addr = mmu_real2abs(env, raddr & TARGET_PAGE_MASK); 559 560 mmu_handle_skey(*addr, rw, flags); 561 return 0; 562 } 563