1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * S/390 virtual CPU header 3fcf5ef2aSThomas Huth * 43fd0e85fSDavid Hildenbrand * For details on the s390x architecture and used definitions (e.g., 53fd0e85fSDavid Hildenbrand * PSW, PER and DAT (Dynamic Address Translation)), please refer to 63fd0e85fSDavid Hildenbrand * the "z/Architecture Principles of Operations" - a.k.a. PoP. 73fd0e85fSDavid Hildenbrand * 8fcf5ef2aSThomas Huth * Copyright (c) 2009 Ulrich Hecht 927e84d4eSChristian Borntraeger * Copyright IBM Corp. 2012, 2018 10fcf5ef2aSThomas Huth * 1144699e1cSThomas Huth * This program is free software; you can redistribute it and/or modify 1244699e1cSThomas Huth * it under the terms of the GNU General Public License as published by 1344699e1cSThomas Huth * the Free Software Foundation; either version 2 of the License, or 1444699e1cSThomas Huth * (at your option) any later version. 15fcf5ef2aSThomas Huth * 1644699e1cSThomas Huth * This program is distributed in the hope that it will be useful, 17fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 18fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1944699e1cSThomas Huth * General Public License for more details. 20fcf5ef2aSThomas Huth * 2144699e1cSThomas Huth * You should have received a copy of the GNU General Public License 2244699e1cSThomas Huth * along with this program; if not, see <http://www.gnu.org/licenses/>. 23fcf5ef2aSThomas Huth */ 24fcf5ef2aSThomas Huth 25fcf5ef2aSThomas Huth #ifndef S390X_CPU_H 26fcf5ef2aSThomas Huth #define S390X_CPU_H 27fcf5ef2aSThomas Huth 28fcf5ef2aSThomas Huth #include "cpu-qom.h" 29ef2974ccSDavid Hildenbrand #include "cpu_models.h" 3074433bf0SRichard Henderson #include "exec/cpu-defs.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #define ELF_MACHINE_UNAME "S390X" 33fcf5ef2aSThomas Huth 34843caef2SAlex Bennée /* The z/Architecture has a strong memory model with some store-after-load re-ordering */ 35843caef2SAlex Bennée #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 36843caef2SAlex Bennée 37c87ff4d1SRichard Henderson #define TARGET_INSN_START_EXTRA_WORDS 2 38fcf5ef2aSThomas Huth 39fcf5ef2aSThomas Huth #define MMU_USER_IDX 0 40fcf5ef2aSThomas Huth 41f42dc44aSDavid Hildenbrand #define S390_MAX_CPUS 248 42f42dc44aSDavid Hildenbrand 43fcf5ef2aSThomas Huth typedef struct PSW { 44fcf5ef2aSThomas Huth uint64_t mask; 45fcf5ef2aSThomas Huth uint64_t addr; 46fcf5ef2aSThomas Huth } PSW; 47fcf5ef2aSThomas Huth 48ef2974ccSDavid Hildenbrand struct CPUS390XState { 49fcf5ef2aSThomas Huth uint64_t regs[16]; /* GP registers */ 50fcf5ef2aSThomas Huth /* 51fcf5ef2aSThomas Huth * The floating point registers are part of the vector registers. 52fcf5ef2aSThomas Huth * vregs[0][0] -> vregs[15][0] are 16 floating point registers 53fcf5ef2aSThomas Huth */ 544f83d7d2SDavid Hildenbrand uint64_t vregs[32][2] QEMU_ALIGNED(16); /* vector registers */ 55fcf5ef2aSThomas Huth uint32_t aregs[16]; /* access registers */ 5662deb62dSFan Zhang uint64_t gscb[4]; /* guarded storage control */ 5727e84d4eSChristian Borntraeger uint64_t etoken; /* etoken */ 5827e84d4eSChristian Borntraeger uint64_t etoken_extension; /* etoken extension */ 59cb4f4bc3SChristian Borntraeger 60cb4f4bc3SChristian Borntraeger /* Fields up to this point are not cleared by initial CPU reset */ 61cb4f4bc3SChristian Borntraeger struct {} start_initial_reset_fields; 62fcf5ef2aSThomas Huth 63fcf5ef2aSThomas Huth uint32_t fpc; /* floating-point control register */ 64fcf5ef2aSThomas Huth uint32_t cc_op; 65b073c875SChristian Borntraeger bool bpbc; /* branch prediction blocking */ 66fcf5ef2aSThomas Huth 67fcf5ef2aSThomas Huth float_status fpu_status; /* passed to softfloat lib */ 68fcf5ef2aSThomas Huth 69fcf5ef2aSThomas Huth /* The low part of a 128-bit return, or remainder of a divide. */ 70fcf5ef2aSThomas Huth uint64_t retxl; 71fcf5ef2aSThomas Huth 72fcf5ef2aSThomas Huth PSW psw; 73fcf5ef2aSThomas Huth 744ada99adSChristian Borntraeger S390CrashReason crash_reason; 754ada99adSChristian Borntraeger 76fcf5ef2aSThomas Huth uint64_t cc_src; 77fcf5ef2aSThomas Huth uint64_t cc_dst; 78fcf5ef2aSThomas Huth uint64_t cc_vr; 79fcf5ef2aSThomas Huth 80303c681aSRichard Henderson uint64_t ex_value; 81303c681aSRichard Henderson 82fcf5ef2aSThomas Huth uint64_t __excp_addr; 83fcf5ef2aSThomas Huth uint64_t psa; 84fcf5ef2aSThomas Huth 85fcf5ef2aSThomas Huth uint32_t int_pgm_code; 86fcf5ef2aSThomas Huth uint32_t int_pgm_ilen; 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth uint32_t int_svc_code; 89fcf5ef2aSThomas Huth uint32_t int_svc_ilen; 90fcf5ef2aSThomas Huth 91fcf5ef2aSThomas Huth uint64_t per_address; 92fcf5ef2aSThomas Huth uint16_t per_perc_atmid; 93fcf5ef2aSThomas Huth 94fcf5ef2aSThomas Huth uint64_t cregs[16]; /* control registers */ 95fcf5ef2aSThomas Huth 96fcf5ef2aSThomas Huth uint64_t ckc; 97fcf5ef2aSThomas Huth uint64_t cputm; 98fcf5ef2aSThomas Huth uint32_t todpr; 99fcf5ef2aSThomas Huth 100fcf5ef2aSThomas Huth uint64_t pfault_token; 101fcf5ef2aSThomas Huth uint64_t pfault_compare; 102fcf5ef2aSThomas Huth uint64_t pfault_select; 103fcf5ef2aSThomas Huth 104fcf5ef2aSThomas Huth uint64_t gbea; 105fcf5ef2aSThomas Huth uint64_t pp; 106fcf5ef2aSThomas Huth 107e893baeeSJanosch Frank /* Fields up to this point are not cleared by normal CPU reset */ 108e893baeeSJanosch Frank struct {} start_normal_reset_fields; 109e893baeeSJanosch Frank uint8_t riccb[64]; /* runtime instrumentation control */ 110e893baeeSJanosch Frank 111bcf88d56SCornelia Huck int pending_int; 112bcf88d56SCornelia Huck uint16_t external_call_addr; 113bcf88d56SCornelia Huck DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS); 114bcf88d56SCornelia Huck 115fabdada9SCollin Walling uint64_t diag318_info; 116fabdada9SCollin Walling 117*e56552cfSRichard Henderson #if !defined(CONFIG_USER_ONLY) 118*e56552cfSRichard Henderson uint64_t tlb_fill_tec; /* translation exception code during tlb_fill */ 119*e56552cfSRichard Henderson int tlb_fill_exc; /* exception number seen during tlb_fill */ 120*e56552cfSRichard Henderson #endif 121*e56552cfSRichard Henderson 1221f5c00cfSAlex Bennée /* Fields up to this point are cleared by a CPU reset */ 1231f5c00cfSAlex Bennée struct {} end_reset_fields; 124fcf5ef2aSThomas Huth 1251e70ba24SDavid Hildenbrand #if !defined(CONFIG_USER_ONLY) 126ca5c1457SDavid Hildenbrand uint32_t core_id; /* PoP "CPU address", same as cpu_index */ 127076d4d39SDavid Hildenbrand uint64_t cpuid; 1281e70ba24SDavid Hildenbrand #endif 129fcf5ef2aSThomas Huth 130fcf5ef2aSThomas Huth QEMUTimer *tod_timer; 131fcf5ef2aSThomas Huth 132fcf5ef2aSThomas Huth QEMUTimer *cpu_timer; 133fcf5ef2aSThomas Huth 134fcf5ef2aSThomas Huth /* 135fcf5ef2aSThomas Huth * The cpu state represents the logical state of a cpu. In contrast to other 136fcf5ef2aSThomas Huth * architectures, there is a difference between a halt and a stop on s390. 137fcf5ef2aSThomas Huth * If all cpus are either stopped (including check stop) or in the disabled 138fcf5ef2aSThomas Huth * wait state, the vm can be shut down. 1399d0306dfSViktor Mihajlovski * The acceptable cpu_state values are defined in the CpuInfoS390State 1409d0306dfSViktor Mihajlovski * enum. 141fcf5ef2aSThomas Huth */ 142fcf5ef2aSThomas Huth uint8_t cpu_state; 143fcf5ef2aSThomas Huth 144fcf5ef2aSThomas Huth /* currently processed sigp order */ 145fcf5ef2aSThomas Huth uint8_t sigp_order; 146fcf5ef2aSThomas Huth 147ef2974ccSDavid Hildenbrand }; 148fcf5ef2aSThomas Huth 1494f83d7d2SDavid Hildenbrand static inline uint64_t *get_freg(CPUS390XState *cs, int nr) 150fcf5ef2aSThomas Huth { 151fcf5ef2aSThomas Huth return &cs->vregs[nr][0]; 152fcf5ef2aSThomas Huth } 153fcf5ef2aSThomas Huth 154fcf5ef2aSThomas Huth /** 155fcf5ef2aSThomas Huth * S390CPU: 156fcf5ef2aSThomas Huth * @env: #CPUS390XState. 157fcf5ef2aSThomas Huth * 158fcf5ef2aSThomas Huth * An S/390 CPU. 159fcf5ef2aSThomas Huth */ 160fcf5ef2aSThomas Huth struct S390CPU { 161fcf5ef2aSThomas Huth /*< private >*/ 162fcf5ef2aSThomas Huth CPUState parent_obj; 163fcf5ef2aSThomas Huth /*< public >*/ 164fcf5ef2aSThomas Huth 1655b146dc7SRichard Henderson CPUNegativeOffsetState neg; 166fcf5ef2aSThomas Huth CPUS390XState env; 167fcf5ef2aSThomas Huth S390CPUModel *model; 168fcf5ef2aSThomas Huth /* needed for live migration */ 169fcf5ef2aSThomas Huth void *irqstate; 170fcf5ef2aSThomas Huth uint32_t irqstate_saved_size; 171fcf5ef2aSThomas Huth }; 172fcf5ef2aSThomas Huth 173fcf5ef2aSThomas Huth 174fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 1758a9358ccSMarkus Armbruster extern const VMStateDescription vmstate_s390_cpu; 176fcf5ef2aSThomas Huth #endif 177fcf5ef2aSThomas Huth 178fcf5ef2aSThomas Huth /* distinguish between 24 bit and 31 bit addressing */ 179fcf5ef2aSThomas Huth #define HIGH_ORDER_BIT 0x80000000 180fcf5ef2aSThomas Huth 181fcf5ef2aSThomas Huth /* Interrupt Codes */ 182fcf5ef2aSThomas Huth /* Program Interrupts */ 183fcf5ef2aSThomas Huth #define PGM_OPERATION 0x0001 184fcf5ef2aSThomas Huth #define PGM_PRIVILEGED 0x0002 185fcf5ef2aSThomas Huth #define PGM_EXECUTE 0x0003 186fcf5ef2aSThomas Huth #define PGM_PROTECTION 0x0004 187fcf5ef2aSThomas Huth #define PGM_ADDRESSING 0x0005 188fcf5ef2aSThomas Huth #define PGM_SPECIFICATION 0x0006 189fcf5ef2aSThomas Huth #define PGM_DATA 0x0007 190fcf5ef2aSThomas Huth #define PGM_FIXPT_OVERFLOW 0x0008 191fcf5ef2aSThomas Huth #define PGM_FIXPT_DIVIDE 0x0009 192fcf5ef2aSThomas Huth #define PGM_DEC_OVERFLOW 0x000a 193fcf5ef2aSThomas Huth #define PGM_DEC_DIVIDE 0x000b 194fcf5ef2aSThomas Huth #define PGM_HFP_EXP_OVERFLOW 0x000c 195fcf5ef2aSThomas Huth #define PGM_HFP_EXP_UNDERFLOW 0x000d 196fcf5ef2aSThomas Huth #define PGM_HFP_SIGNIFICANCE 0x000e 197fcf5ef2aSThomas Huth #define PGM_HFP_DIVIDE 0x000f 198fcf5ef2aSThomas Huth #define PGM_SEGMENT_TRANS 0x0010 199fcf5ef2aSThomas Huth #define PGM_PAGE_TRANS 0x0011 200fcf5ef2aSThomas Huth #define PGM_TRANS_SPEC 0x0012 201fcf5ef2aSThomas Huth #define PGM_SPECIAL_OP 0x0013 202fcf5ef2aSThomas Huth #define PGM_OPERAND 0x0015 203fcf5ef2aSThomas Huth #define PGM_TRACE_TABLE 0x0016 2049be6fa99SDavid Hildenbrand #define PGM_VECTOR_PROCESSING 0x001b 205fcf5ef2aSThomas Huth #define PGM_SPACE_SWITCH 0x001c 206fcf5ef2aSThomas Huth #define PGM_HFP_SQRT 0x001d 207fcf5ef2aSThomas Huth #define PGM_PC_TRANS_SPEC 0x001f 208fcf5ef2aSThomas Huth #define PGM_AFX_TRANS 0x0020 209fcf5ef2aSThomas Huth #define PGM_ASX_TRANS 0x0021 210fcf5ef2aSThomas Huth #define PGM_LX_TRANS 0x0022 211fcf5ef2aSThomas Huth #define PGM_EX_TRANS 0x0023 212fcf5ef2aSThomas Huth #define PGM_PRIM_AUTH 0x0024 213fcf5ef2aSThomas Huth #define PGM_SEC_AUTH 0x0025 214fcf5ef2aSThomas Huth #define PGM_ALET_SPEC 0x0028 215fcf5ef2aSThomas Huth #define PGM_ALEN_SPEC 0x0029 216fcf5ef2aSThomas Huth #define PGM_ALE_SEQ 0x002a 217fcf5ef2aSThomas Huth #define PGM_ASTE_VALID 0x002b 218fcf5ef2aSThomas Huth #define PGM_ASTE_SEQ 0x002c 219fcf5ef2aSThomas Huth #define PGM_EXT_AUTH 0x002d 220fcf5ef2aSThomas Huth #define PGM_STACK_FULL 0x0030 221fcf5ef2aSThomas Huth #define PGM_STACK_EMPTY 0x0031 222fcf5ef2aSThomas Huth #define PGM_STACK_SPEC 0x0032 223fcf5ef2aSThomas Huth #define PGM_STACK_TYPE 0x0033 224fcf5ef2aSThomas Huth #define PGM_STACK_OP 0x0034 225fcf5ef2aSThomas Huth #define PGM_ASCE_TYPE 0x0038 226fcf5ef2aSThomas Huth #define PGM_REG_FIRST_TRANS 0x0039 227fcf5ef2aSThomas Huth #define PGM_REG_SEC_TRANS 0x003a 228fcf5ef2aSThomas Huth #define PGM_REG_THIRD_TRANS 0x003b 229fcf5ef2aSThomas Huth #define PGM_MONITOR 0x0040 230fcf5ef2aSThomas Huth #define PGM_PER 0x0080 231fcf5ef2aSThomas Huth #define PGM_CRYPTO 0x0119 232fcf5ef2aSThomas Huth 233fcf5ef2aSThomas Huth /* External Interrupts */ 234fcf5ef2aSThomas Huth #define EXT_INTERRUPT_KEY 0x0040 235fcf5ef2aSThomas Huth #define EXT_CLOCK_COMP 0x1004 236fcf5ef2aSThomas Huth #define EXT_CPU_TIMER 0x1005 237fcf5ef2aSThomas Huth #define EXT_MALFUNCTION 0x1200 238fcf5ef2aSThomas Huth #define EXT_EMERGENCY 0x1201 239fcf5ef2aSThomas Huth #define EXT_EXTERNAL_CALL 0x1202 240fcf5ef2aSThomas Huth #define EXT_ETR 0x1406 241fcf5ef2aSThomas Huth #define EXT_SERVICE 0x2401 242fcf5ef2aSThomas Huth #define EXT_VIRTIO 0x2603 243fcf5ef2aSThomas Huth 244fcf5ef2aSThomas Huth /* PSW defines */ 245fcf5ef2aSThomas Huth #undef PSW_MASK_PER 24613054739SDavid Hildenbrand #undef PSW_MASK_UNUSED_2 247b971a2fdSDavid Hildenbrand #undef PSW_MASK_UNUSED_3 248fcf5ef2aSThomas Huth #undef PSW_MASK_DAT 249fcf5ef2aSThomas Huth #undef PSW_MASK_IO 250fcf5ef2aSThomas Huth #undef PSW_MASK_EXT 251fcf5ef2aSThomas Huth #undef PSW_MASK_KEY 252fcf5ef2aSThomas Huth #undef PSW_SHIFT_KEY 253fcf5ef2aSThomas Huth #undef PSW_MASK_MCHECK 254fcf5ef2aSThomas Huth #undef PSW_MASK_WAIT 255fcf5ef2aSThomas Huth #undef PSW_MASK_PSTATE 256fcf5ef2aSThomas Huth #undef PSW_MASK_ASC 2573e7e5e0bSDavid Hildenbrand #undef PSW_SHIFT_ASC 258fcf5ef2aSThomas Huth #undef PSW_MASK_CC 259fcf5ef2aSThomas Huth #undef PSW_MASK_PM 260e893baeeSJanosch Frank #undef PSW_MASK_RI 2616b257354SDavid Hildenbrand #undef PSW_SHIFT_MASK_PM 262fcf5ef2aSThomas Huth #undef PSW_MASK_64 263fcf5ef2aSThomas Huth #undef PSW_MASK_32 264fcf5ef2aSThomas Huth #undef PSW_MASK_ESA_ADDR 265fcf5ef2aSThomas Huth 266fcf5ef2aSThomas Huth #define PSW_MASK_PER 0x4000000000000000ULL 26713054739SDavid Hildenbrand #define PSW_MASK_UNUSED_2 0x2000000000000000ULL 268b971a2fdSDavid Hildenbrand #define PSW_MASK_UNUSED_3 0x1000000000000000ULL 269fcf5ef2aSThomas Huth #define PSW_MASK_DAT 0x0400000000000000ULL 270fcf5ef2aSThomas Huth #define PSW_MASK_IO 0x0200000000000000ULL 271fcf5ef2aSThomas Huth #define PSW_MASK_EXT 0x0100000000000000ULL 272fcf5ef2aSThomas Huth #define PSW_MASK_KEY 0x00F0000000000000ULL 273c8bd9537SDavid Hildenbrand #define PSW_SHIFT_KEY 52 274104130cbSJanosch Frank #define PSW_MASK_SHORTPSW 0x0008000000000000ULL 275fcf5ef2aSThomas Huth #define PSW_MASK_MCHECK 0x0004000000000000ULL 276fcf5ef2aSThomas Huth #define PSW_MASK_WAIT 0x0002000000000000ULL 277fcf5ef2aSThomas Huth #define PSW_MASK_PSTATE 0x0001000000000000ULL 278fcf5ef2aSThomas Huth #define PSW_MASK_ASC 0x0000C00000000000ULL 2793e7e5e0bSDavid Hildenbrand #define PSW_SHIFT_ASC 46 280fcf5ef2aSThomas Huth #define PSW_MASK_CC 0x0000300000000000ULL 281fcf5ef2aSThomas Huth #define PSW_MASK_PM 0x00000F0000000000ULL 2826b257354SDavid Hildenbrand #define PSW_SHIFT_MASK_PM 40 283e893baeeSJanosch Frank #define PSW_MASK_RI 0x0000008000000000ULL 284fcf5ef2aSThomas Huth #define PSW_MASK_64 0x0000000100000000ULL 285fcf5ef2aSThomas Huth #define PSW_MASK_32 0x0000000080000000ULL 286b6c2dbd7SJanosch Frank #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL 287b6c2dbd7SJanosch Frank #define PSW_MASK_SHORT_CTRL 0xffffffff80000000ULL 288fcf5ef2aSThomas Huth 289fcf5ef2aSThomas Huth #undef PSW_ASC_PRIMARY 290fcf5ef2aSThomas Huth #undef PSW_ASC_ACCREG 291fcf5ef2aSThomas Huth #undef PSW_ASC_SECONDARY 292fcf5ef2aSThomas Huth #undef PSW_ASC_HOME 293fcf5ef2aSThomas Huth 294fcf5ef2aSThomas Huth #define PSW_ASC_PRIMARY 0x0000000000000000ULL 295fcf5ef2aSThomas Huth #define PSW_ASC_ACCREG 0x0000400000000000ULL 296fcf5ef2aSThomas Huth #define PSW_ASC_SECONDARY 0x0000800000000000ULL 297fcf5ef2aSThomas Huth #define PSW_ASC_HOME 0x0000C00000000000ULL 298fcf5ef2aSThomas Huth 2993e7e5e0bSDavid Hildenbrand /* the address space values shifted */ 3003e7e5e0bSDavid Hildenbrand #define AS_PRIMARY 0 3013e7e5e0bSDavid Hildenbrand #define AS_ACCREG 1 3023e7e5e0bSDavid Hildenbrand #define AS_SECONDARY 2 3033e7e5e0bSDavid Hildenbrand #define AS_HOME 3 3043e7e5e0bSDavid Hildenbrand 305fcf5ef2aSThomas Huth /* tb flags */ 306fcf5ef2aSThomas Huth 307159fed45SRichard Henderson #define FLAG_MASK_PSW_SHIFT 31 308159fed45SRichard Henderson #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT) 309f26852aaSDavid Hildenbrand #define FLAG_MASK_DAT (PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT) 310159fed45SRichard Henderson #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT) 311159fed45SRichard Henderson #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT) 312159fed45SRichard Henderson #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT) 313159fed45SRichard Henderson #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT) 314f26852aaSDavid Hildenbrand #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \ 315159fed45SRichard Henderson | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32) 316fcf5ef2aSThomas Huth 31713054739SDavid Hildenbrand /* we'll use some unused PSW positions to store CR flags in tb flags */ 31813054739SDavid Hildenbrand #define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT) 319b971a2fdSDavid Hildenbrand #define FLAG_MASK_VECTOR (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT) 32013054739SDavid Hildenbrand 321fcf5ef2aSThomas Huth /* Control register 0 bits */ 322fcf5ef2aSThomas Huth #define CR0_LOWPROT 0x0000000010000000ULL 3233e7e5e0bSDavid Hildenbrand #define CR0_SECONDARY 0x0000000004000000ULL 324fcf5ef2aSThomas Huth #define CR0_EDAT 0x0000000000800000ULL 325bbf6ea3bSDavid Hildenbrand #define CR0_AFP 0x0000000000040000ULL 326b971a2fdSDavid Hildenbrand #define CR0_VECTOR 0x0000000000020000ULL 3273a06f981SDavid Hildenbrand #define CR0_IEP 0x0000000000100000ULL 3289dec2388SDavid Hildenbrand #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL 3299dec2388SDavid Hildenbrand #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL 3309dec2388SDavid Hildenbrand #define CR0_CKC_SC 0x0000000000000800ULL 3319dec2388SDavid Hildenbrand #define CR0_CPU_TIMER_SC 0x0000000000000400ULL 3329dec2388SDavid Hildenbrand #define CR0_SERVICE_SC 0x0000000000000200ULL 333fcf5ef2aSThomas Huth 334b700d75eSDavid Hildenbrand /* Control register 14 bits */ 335b700d75eSDavid Hildenbrand #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL 336b700d75eSDavid Hildenbrand 337fcf5ef2aSThomas Huth /* MMU */ 338fcf5ef2aSThomas Huth #define MMU_PRIMARY_IDX 0 339fcf5ef2aSThomas Huth #define MMU_SECONDARY_IDX 1 340fcf5ef2aSThomas Huth #define MMU_HOME_IDX 2 341fb66944dSDavid Hildenbrand #define MMU_REAL_IDX 3 342fcf5ef2aSThomas Huth 343fcf5ef2aSThomas Huth static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) 344fcf5ef2aSThomas Huth { 345817791e8SDavid Hildenbrand #ifdef CONFIG_USER_ONLY 346817791e8SDavid Hildenbrand return MMU_USER_IDX; 347817791e8SDavid Hildenbrand #else 348f26852aaSDavid Hildenbrand if (!(env->psw.mask & PSW_MASK_DAT)) { 349f26852aaSDavid Hildenbrand return MMU_REAL_IDX; 350f26852aaSDavid Hildenbrand } 351f26852aaSDavid Hildenbrand 3523096ffd3SDavid Hildenbrand if (ifetch) { 3533096ffd3SDavid Hildenbrand if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) { 3543096ffd3SDavid Hildenbrand return MMU_HOME_IDX; 3553096ffd3SDavid Hildenbrand } 3563096ffd3SDavid Hildenbrand return MMU_PRIMARY_IDX; 3573096ffd3SDavid Hildenbrand } 3583096ffd3SDavid Hildenbrand 359fcf5ef2aSThomas Huth switch (env->psw.mask & PSW_MASK_ASC) { 360fcf5ef2aSThomas Huth case PSW_ASC_PRIMARY: 361fcf5ef2aSThomas Huth return MMU_PRIMARY_IDX; 362fcf5ef2aSThomas Huth case PSW_ASC_SECONDARY: 363fcf5ef2aSThomas Huth return MMU_SECONDARY_IDX; 364fcf5ef2aSThomas Huth case PSW_ASC_HOME: 365fcf5ef2aSThomas Huth return MMU_HOME_IDX; 366fcf5ef2aSThomas Huth case PSW_ASC_ACCREG: 367fcf5ef2aSThomas Huth /* Fallthrough: access register mode is not yet supported */ 368fcf5ef2aSThomas Huth default: 369fcf5ef2aSThomas Huth abort(); 370fcf5ef2aSThomas Huth } 371817791e8SDavid Hildenbrand #endif 372fcf5ef2aSThomas Huth } 373fcf5ef2aSThomas Huth 374fcf5ef2aSThomas Huth static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, 375fcf5ef2aSThomas Huth target_ulong *cs_base, uint32_t *flags) 376fcf5ef2aSThomas Huth { 377fcf5ef2aSThomas Huth *pc = env->psw.addr; 378303c681aSRichard Henderson *cs_base = env->ex_value; 379159fed45SRichard Henderson *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; 38013054739SDavid Hildenbrand if (env->cregs[0] & CR0_AFP) { 38113054739SDavid Hildenbrand *flags |= FLAG_MASK_AFP; 38213054739SDavid Hildenbrand } 383b971a2fdSDavid Hildenbrand if (env->cregs[0] & CR0_VECTOR) { 384b971a2fdSDavid Hildenbrand *flags |= FLAG_MASK_VECTOR; 385b971a2fdSDavid Hildenbrand } 386fcf5ef2aSThomas Huth } 387fcf5ef2aSThomas Huth 388fcf5ef2aSThomas Huth /* PER bits from control register 9 */ 389fcf5ef2aSThomas Huth #define PER_CR9_EVENT_BRANCH 0x80000000 390fcf5ef2aSThomas Huth #define PER_CR9_EVENT_IFETCH 0x40000000 391fcf5ef2aSThomas Huth #define PER_CR9_EVENT_STORE 0x20000000 392fcf5ef2aSThomas Huth #define PER_CR9_EVENT_STORE_REAL 0x08000000 393fcf5ef2aSThomas Huth #define PER_CR9_EVENT_NULLIFICATION 0x01000000 394fcf5ef2aSThomas Huth #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000 395fcf5ef2aSThomas Huth #define PER_CR9_CONTROL_ALTERATION 0x00200000 396fcf5ef2aSThomas Huth 397fcf5ef2aSThomas Huth /* PER bits from the PER CODE/ATMID/AI in lowcore */ 398fcf5ef2aSThomas Huth #define PER_CODE_EVENT_BRANCH 0x8000 399fcf5ef2aSThomas Huth #define PER_CODE_EVENT_IFETCH 0x4000 400fcf5ef2aSThomas Huth #define PER_CODE_EVENT_STORE 0x2000 401fcf5ef2aSThomas Huth #define PER_CODE_EVENT_STORE_REAL 0x0800 402fcf5ef2aSThomas Huth #define PER_CODE_EVENT_NULLIFICATION 0x0100 403fcf5ef2aSThomas Huth 404fcf5ef2aSThomas Huth #define EXCP_EXT 1 /* external interrupt */ 405fcf5ef2aSThomas Huth #define EXCP_SVC 2 /* supervisor call (syscall) */ 406fcf5ef2aSThomas Huth #define EXCP_PGM 3 /* program interruption */ 407b1ab5f60SDavid Hildenbrand #define EXCP_RESTART 4 /* restart interrupt */ 408b1ab5f60SDavid Hildenbrand #define EXCP_STOP 5 /* stop interrupt */ 409fcf5ef2aSThomas Huth #define EXCP_IO 7 /* I/O interrupt */ 410fcf5ef2aSThomas Huth #define EXCP_MCHK 8 /* machine check */ 411fcf5ef2aSThomas Huth 4126482b0ffSDavid Hildenbrand #define INTERRUPT_EXT_CPU_TIMER (1 << 3) 4136482b0ffSDavid Hildenbrand #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4) 41414ca122eSDavid Hildenbrand #define INTERRUPT_EXTERNAL_CALL (1 << 5) 41514ca122eSDavid Hildenbrand #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6) 416b1ab5f60SDavid Hildenbrand #define INTERRUPT_RESTART (1 << 7) 417b1ab5f60SDavid Hildenbrand #define INTERRUPT_STOP (1 << 8) 418fcf5ef2aSThomas Huth 419fcf5ef2aSThomas Huth /* Program Status Word. */ 420fcf5ef2aSThomas Huth #define S390_PSWM_REGNUM 0 421fcf5ef2aSThomas Huth #define S390_PSWA_REGNUM 1 422fcf5ef2aSThomas Huth /* General Purpose Registers. */ 423fcf5ef2aSThomas Huth #define S390_R0_REGNUM 2 424fcf5ef2aSThomas Huth #define S390_R1_REGNUM 3 425fcf5ef2aSThomas Huth #define S390_R2_REGNUM 4 426fcf5ef2aSThomas Huth #define S390_R3_REGNUM 5 427fcf5ef2aSThomas Huth #define S390_R4_REGNUM 6 428fcf5ef2aSThomas Huth #define S390_R5_REGNUM 7 429fcf5ef2aSThomas Huth #define S390_R6_REGNUM 8 430fcf5ef2aSThomas Huth #define S390_R7_REGNUM 9 431fcf5ef2aSThomas Huth #define S390_R8_REGNUM 10 432fcf5ef2aSThomas Huth #define S390_R9_REGNUM 11 433fcf5ef2aSThomas Huth #define S390_R10_REGNUM 12 434fcf5ef2aSThomas Huth #define S390_R11_REGNUM 13 435fcf5ef2aSThomas Huth #define S390_R12_REGNUM 14 436fcf5ef2aSThomas Huth #define S390_R13_REGNUM 15 437fcf5ef2aSThomas Huth #define S390_R14_REGNUM 16 438fcf5ef2aSThomas Huth #define S390_R15_REGNUM 17 439fcf5ef2aSThomas Huth /* Total Core Registers. */ 440fcf5ef2aSThomas Huth #define S390_NUM_CORE_REGS 18 441fcf5ef2aSThomas Huth 442fcf5ef2aSThomas Huth static inline void setcc(S390CPU *cpu, uint64_t cc) 443fcf5ef2aSThomas Huth { 444fcf5ef2aSThomas Huth CPUS390XState *env = &cpu->env; 445fcf5ef2aSThomas Huth 446fcf5ef2aSThomas Huth env->psw.mask &= ~(3ull << 44); 447fcf5ef2aSThomas Huth env->psw.mask |= (cc & 3) << 44; 448fcf5ef2aSThomas Huth env->cc_op = cc; 449fcf5ef2aSThomas Huth } 450fcf5ef2aSThomas Huth 451fcf5ef2aSThomas Huth /* STSI */ 45279947862SDavid Hildenbrand #define STSI_R0_FC_MASK 0x00000000f0000000ULL 45379947862SDavid Hildenbrand #define STSI_R0_FC_CURRENT 0x0000000000000000ULL 45479947862SDavid Hildenbrand #define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL 45579947862SDavid Hildenbrand #define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL 45679947862SDavid Hildenbrand #define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL 457fcf5ef2aSThomas Huth #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL 458fcf5ef2aSThomas Huth #define STSI_R0_SEL1_MASK 0x00000000000000ffULL 459fcf5ef2aSThomas Huth #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL 460fcf5ef2aSThomas Huth #define STSI_R1_SEL2_MASK 0x000000000000ffffULL 461fcf5ef2aSThomas Huth 462fcf5ef2aSThomas Huth /* Basic Machine Configuration */ 4634d1369efSDavid Hildenbrand typedef struct SysIB_111 { 4644d1369efSDavid Hildenbrand uint8_t res1[32]; 465fcf5ef2aSThomas Huth uint8_t manuf[16]; 466fcf5ef2aSThomas Huth uint8_t type[4]; 467fcf5ef2aSThomas Huth uint8_t res2[12]; 468fcf5ef2aSThomas Huth uint8_t model[16]; 469fcf5ef2aSThomas Huth uint8_t sequence[16]; 470fcf5ef2aSThomas Huth uint8_t plant[4]; 4714d1369efSDavid Hildenbrand uint8_t res3[3996]; 4724d1369efSDavid Hildenbrand } SysIB_111; 4734d1369efSDavid Hildenbrand QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096); 474fcf5ef2aSThomas Huth 475fcf5ef2aSThomas Huth /* Basic Machine CPU */ 4764d1369efSDavid Hildenbrand typedef struct SysIB_121 { 4774d1369efSDavid Hildenbrand uint8_t res1[80]; 478fcf5ef2aSThomas Huth uint8_t sequence[16]; 479fcf5ef2aSThomas Huth uint8_t plant[4]; 480fcf5ef2aSThomas Huth uint8_t res2[2]; 481fcf5ef2aSThomas Huth uint16_t cpu_addr; 4824d1369efSDavid Hildenbrand uint8_t res3[3992]; 4834d1369efSDavid Hildenbrand } SysIB_121; 4844d1369efSDavid Hildenbrand QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096); 485fcf5ef2aSThomas Huth 486fcf5ef2aSThomas Huth /* Basic Machine CPUs */ 4874d1369efSDavid Hildenbrand typedef struct SysIB_122 { 488fcf5ef2aSThomas Huth uint8_t res1[32]; 489fcf5ef2aSThomas Huth uint32_t capability; 490fcf5ef2aSThomas Huth uint16_t total_cpus; 49179947862SDavid Hildenbrand uint16_t conf_cpus; 492fcf5ef2aSThomas Huth uint16_t standby_cpus; 493fcf5ef2aSThomas Huth uint16_t reserved_cpus; 494fcf5ef2aSThomas Huth uint16_t adjustments[2026]; 4954d1369efSDavid Hildenbrand } SysIB_122; 4964d1369efSDavid Hildenbrand QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096); 497fcf5ef2aSThomas Huth 498fcf5ef2aSThomas Huth /* LPAR CPU */ 4994d1369efSDavid Hildenbrand typedef struct SysIB_221 { 5004d1369efSDavid Hildenbrand uint8_t res1[80]; 501fcf5ef2aSThomas Huth uint8_t sequence[16]; 502fcf5ef2aSThomas Huth uint8_t plant[4]; 503fcf5ef2aSThomas Huth uint16_t cpu_id; 504fcf5ef2aSThomas Huth uint16_t cpu_addr; 5054d1369efSDavid Hildenbrand uint8_t res3[3992]; 5064d1369efSDavid Hildenbrand } SysIB_221; 5074d1369efSDavid Hildenbrand QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096); 508fcf5ef2aSThomas Huth 509fcf5ef2aSThomas Huth /* LPAR CPUs */ 5104d1369efSDavid Hildenbrand typedef struct SysIB_222 { 5114d1369efSDavid Hildenbrand uint8_t res1[32]; 512fcf5ef2aSThomas Huth uint16_t lpar_num; 513fcf5ef2aSThomas Huth uint8_t res2; 514fcf5ef2aSThomas Huth uint8_t lcpuc; 515fcf5ef2aSThomas Huth uint16_t total_cpus; 516fcf5ef2aSThomas Huth uint16_t conf_cpus; 517fcf5ef2aSThomas Huth uint16_t standby_cpus; 518fcf5ef2aSThomas Huth uint16_t reserved_cpus; 519fcf5ef2aSThomas Huth uint8_t name[8]; 520fcf5ef2aSThomas Huth uint32_t caf; 521fcf5ef2aSThomas Huth uint8_t res3[16]; 522fcf5ef2aSThomas Huth uint16_t dedicated_cpus; 523fcf5ef2aSThomas Huth uint16_t shared_cpus; 5244d1369efSDavid Hildenbrand uint8_t res4[4020]; 5254d1369efSDavid Hildenbrand } SysIB_222; 5264d1369efSDavid Hildenbrand QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096); 527fcf5ef2aSThomas Huth 528fcf5ef2aSThomas Huth /* VM CPUs */ 5294d1369efSDavid Hildenbrand typedef struct SysIB_322 { 530fcf5ef2aSThomas Huth uint8_t res1[31]; 531fcf5ef2aSThomas Huth uint8_t count; 532fcf5ef2aSThomas Huth struct { 533fcf5ef2aSThomas Huth uint8_t res2[4]; 534fcf5ef2aSThomas Huth uint16_t total_cpus; 535fcf5ef2aSThomas Huth uint16_t conf_cpus; 536fcf5ef2aSThomas Huth uint16_t standby_cpus; 537fcf5ef2aSThomas Huth uint16_t reserved_cpus; 538fcf5ef2aSThomas Huth uint8_t name[8]; 539fcf5ef2aSThomas Huth uint32_t caf; 540fcf5ef2aSThomas Huth uint8_t cpi[16]; 541fcf5ef2aSThomas Huth uint8_t res5[3]; 542fcf5ef2aSThomas Huth uint8_t ext_name_encoding; 543fcf5ef2aSThomas Huth uint32_t res3; 544fcf5ef2aSThomas Huth uint8_t uuid[16]; 545fcf5ef2aSThomas Huth } vm[8]; 546fcf5ef2aSThomas Huth uint8_t res4[1504]; 547fcf5ef2aSThomas Huth uint8_t ext_names[8][256]; 5484d1369efSDavid Hildenbrand } SysIB_322; 5494d1369efSDavid Hildenbrand QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096); 550fcf5ef2aSThomas Huth 55179947862SDavid Hildenbrand typedef union SysIB { 55279947862SDavid Hildenbrand SysIB_111 sysib_111; 55379947862SDavid Hildenbrand SysIB_121 sysib_121; 55479947862SDavid Hildenbrand SysIB_122 sysib_122; 55579947862SDavid Hildenbrand SysIB_221 sysib_221; 55679947862SDavid Hildenbrand SysIB_222 sysib_222; 55779947862SDavid Hildenbrand SysIB_322 sysib_322; 55879947862SDavid Hildenbrand } SysIB; 55979947862SDavid Hildenbrand QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096); 56079947862SDavid Hildenbrand 561fcf5ef2aSThomas Huth /* MMU defines */ 562adab99beSThomas Huth #define ASCE_ORIGIN (~0xfffULL) /* segment table origin */ 563adab99beSThomas Huth #define ASCE_SUBSPACE 0x200 /* subspace group control */ 564adab99beSThomas Huth #define ASCE_PRIVATE_SPACE 0x100 /* private space control */ 565adab99beSThomas Huth #define ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 566adab99beSThomas Huth #define ASCE_SPACE_SWITCH 0x40 /* space switch event */ 567adab99beSThomas Huth #define ASCE_REAL_SPACE 0x20 /* real space control */ 568adab99beSThomas Huth #define ASCE_TYPE_MASK 0x0c /* asce table type mask */ 569adab99beSThomas Huth #define ASCE_TYPE_REGION1 0x0c /* region first table type */ 570adab99beSThomas Huth #define ASCE_TYPE_REGION2 0x08 /* region second table type */ 571adab99beSThomas Huth #define ASCE_TYPE_REGION3 0x04 /* region third table type */ 572adab99beSThomas Huth #define ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 573adab99beSThomas Huth #define ASCE_TABLE_LENGTH 0x03 /* region table length */ 574fcf5ef2aSThomas Huth 5753fd0e85fSDavid Hildenbrand #define REGION_ENTRY_ORIGIN 0xfffffffffffff000ULL 5763fd0e85fSDavid Hildenbrand #define REGION_ENTRY_P 0x0000000000000200ULL 5773fd0e85fSDavid Hildenbrand #define REGION_ENTRY_TF 0x00000000000000c0ULL 5783fd0e85fSDavid Hildenbrand #define REGION_ENTRY_I 0x0000000000000020ULL 5793fd0e85fSDavid Hildenbrand #define REGION_ENTRY_TT 0x000000000000000cULL 5803fd0e85fSDavid Hildenbrand #define REGION_ENTRY_TL 0x0000000000000003ULL 581fcf5ef2aSThomas Huth 5823fd0e85fSDavid Hildenbrand #define REGION_ENTRY_TT_REGION1 0x000000000000000cULL 5833fd0e85fSDavid Hildenbrand #define REGION_ENTRY_TT_REGION2 0x0000000000000008ULL 5843fd0e85fSDavid Hildenbrand #define REGION_ENTRY_TT_REGION3 0x0000000000000004ULL 585fcf5ef2aSThomas Huth 5863fd0e85fSDavid Hildenbrand #define REGION3_ENTRY_RFAA 0xffffffff80000000ULL 5873fd0e85fSDavid Hildenbrand #define REGION3_ENTRY_AV 0x0000000000010000ULL 5883fd0e85fSDavid Hildenbrand #define REGION3_ENTRY_ACC 0x000000000000f000ULL 5893fd0e85fSDavid Hildenbrand #define REGION3_ENTRY_F 0x0000000000000800ULL 5903fd0e85fSDavid Hildenbrand #define REGION3_ENTRY_FC 0x0000000000000400ULL 5913fd0e85fSDavid Hildenbrand #define REGION3_ENTRY_IEP 0x0000000000000100ULL 5923fd0e85fSDavid Hildenbrand #define REGION3_ENTRY_CR 0x0000000000000010ULL 5938a4719f5SAurelien Jarno 5943fd0e85fSDavid Hildenbrand #define SEGMENT_ENTRY_ORIGIN 0xfffffffffffff800ULL 5953fd0e85fSDavid Hildenbrand #define SEGMENT_ENTRY_SFAA 0xfffffffffff00000ULL 5963fd0e85fSDavid Hildenbrand #define SEGMENT_ENTRY_AV 0x0000000000010000ULL 5973fd0e85fSDavid Hildenbrand #define SEGMENT_ENTRY_ACC 0x000000000000f000ULL 5983fd0e85fSDavid Hildenbrand #define SEGMENT_ENTRY_F 0x0000000000000800ULL 5993fd0e85fSDavid Hildenbrand #define SEGMENT_ENTRY_FC 0x0000000000000400ULL 6003fd0e85fSDavid Hildenbrand #define SEGMENT_ENTRY_P 0x0000000000000200ULL 6013fd0e85fSDavid Hildenbrand #define SEGMENT_ENTRY_IEP 0x0000000000000100ULL 6023fd0e85fSDavid Hildenbrand #define SEGMENT_ENTRY_I 0x0000000000000020ULL 6033fd0e85fSDavid Hildenbrand #define SEGMENT_ENTRY_CS 0x0000000000000010ULL 6043fd0e85fSDavid Hildenbrand #define SEGMENT_ENTRY_TT 0x000000000000000cULL 6053fd0e85fSDavid Hildenbrand 6063fd0e85fSDavid Hildenbrand #define SEGMENT_ENTRY_TT_SEGMENT 0x0000000000000000ULL 6073fd0e85fSDavid Hildenbrand 6083fd0e85fSDavid Hildenbrand #define PAGE_ENTRY_0 0x0000000000000800ULL 6093fd0e85fSDavid Hildenbrand #define PAGE_ENTRY_I 0x0000000000000400ULL 6103fd0e85fSDavid Hildenbrand #define PAGE_ENTRY_P 0x0000000000000200ULL 6113fd0e85fSDavid Hildenbrand #define PAGE_ENTRY_IEP 0x0000000000000100ULL 6123fd0e85fSDavid Hildenbrand 6133fd0e85fSDavid Hildenbrand #define VADDR_REGION1_TX_MASK 0xffe0000000000000ULL 6143fd0e85fSDavid Hildenbrand #define VADDR_REGION2_TX_MASK 0x001ffc0000000000ULL 6153fd0e85fSDavid Hildenbrand #define VADDR_REGION3_TX_MASK 0x000003ff80000000ULL 6163fd0e85fSDavid Hildenbrand #define VADDR_SEGMENT_TX_MASK 0x000000007ff00000ULL 6173fd0e85fSDavid Hildenbrand #define VADDR_PAGE_TX_MASK 0x00000000000ff000ULL 6183fd0e85fSDavid Hildenbrand 6193fd0e85fSDavid Hildenbrand #define VADDR_REGION1_TX(vaddr) (((vaddr) & VADDR_REGION1_TX_MASK) >> 53) 6203fd0e85fSDavid Hildenbrand #define VADDR_REGION2_TX(vaddr) (((vaddr) & VADDR_REGION2_TX_MASK) >> 42) 6213fd0e85fSDavid Hildenbrand #define VADDR_REGION3_TX(vaddr) (((vaddr) & VADDR_REGION3_TX_MASK) >> 31) 6223fd0e85fSDavid Hildenbrand #define VADDR_SEGMENT_TX(vaddr) (((vaddr) & VADDR_SEGMENT_TX_MASK) >> 20) 6233fd0e85fSDavid Hildenbrand #define VADDR_PAGE_TX(vaddr) (((vaddr) & VADDR_PAGE_TX_MASK) >> 12) 6243fd0e85fSDavid Hildenbrand 6253fd0e85fSDavid Hildenbrand #define VADDR_REGION1_TL(vaddr) (((vaddr) & 0xc000000000000000ULL) >> 62) 6263fd0e85fSDavid Hildenbrand #define VADDR_REGION2_TL(vaddr) (((vaddr) & 0x0018000000000000ULL) >> 51) 6273fd0e85fSDavid Hildenbrand #define VADDR_REGION3_TL(vaddr) (((vaddr) & 0x0000030000000000ULL) >> 40) 6283fd0e85fSDavid Hildenbrand #define VADDR_SEGMENT_TL(vaddr) (((vaddr) & 0x0000000060000000ULL) >> 29) 629fcf5ef2aSThomas Huth 630fcf5ef2aSThomas Huth #define SK_C (0x1 << 1) 631fcf5ef2aSThomas Huth #define SK_R (0x1 << 2) 632fcf5ef2aSThomas Huth #define SK_F (0x1 << 3) 633fcf5ef2aSThomas Huth #define SK_ACC_MASK (0xf << 4) 634fcf5ef2aSThomas Huth 635fcf5ef2aSThomas Huth /* SIGP order codes */ 636fcf5ef2aSThomas Huth #define SIGP_SENSE 0x01 637fcf5ef2aSThomas Huth #define SIGP_EXTERNAL_CALL 0x02 638fcf5ef2aSThomas Huth #define SIGP_EMERGENCY 0x03 639fcf5ef2aSThomas Huth #define SIGP_START 0x04 640fcf5ef2aSThomas Huth #define SIGP_STOP 0x05 641fcf5ef2aSThomas Huth #define SIGP_RESTART 0x06 642fcf5ef2aSThomas Huth #define SIGP_STOP_STORE_STATUS 0x09 643fcf5ef2aSThomas Huth #define SIGP_INITIAL_CPU_RESET 0x0b 644fcf5ef2aSThomas Huth #define SIGP_CPU_RESET 0x0c 645fcf5ef2aSThomas Huth #define SIGP_SET_PREFIX 0x0d 646fcf5ef2aSThomas Huth #define SIGP_STORE_STATUS_ADDR 0x0e 647fcf5ef2aSThomas Huth #define SIGP_SET_ARCH 0x12 648a6880d21SDavid Hildenbrand #define SIGP_COND_EMERGENCY 0x13 649d1b468bcSDavid Hildenbrand #define SIGP_SENSE_RUNNING 0x15 650fcf5ef2aSThomas Huth #define SIGP_STORE_ADTL_STATUS 0x17 651fcf5ef2aSThomas Huth 652fcf5ef2aSThomas Huth /* SIGP condition codes */ 653fcf5ef2aSThomas Huth #define SIGP_CC_ORDER_CODE_ACCEPTED 0 654fcf5ef2aSThomas Huth #define SIGP_CC_STATUS_STORED 1 655fcf5ef2aSThomas Huth #define SIGP_CC_BUSY 2 656fcf5ef2aSThomas Huth #define SIGP_CC_NOT_OPERATIONAL 3 657fcf5ef2aSThomas Huth 658fcf5ef2aSThomas Huth /* SIGP status bits */ 659fcf5ef2aSThomas Huth #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL 660d1b468bcSDavid Hildenbrand #define SIGP_STAT_NOT_RUNNING 0x00000400UL 661fcf5ef2aSThomas Huth #define SIGP_STAT_INCORRECT_STATE 0x00000200UL 662fcf5ef2aSThomas Huth #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL 663fcf5ef2aSThomas Huth #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL 664fcf5ef2aSThomas Huth #define SIGP_STAT_STOPPED 0x00000040UL 665fcf5ef2aSThomas Huth #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL 666fcf5ef2aSThomas Huth #define SIGP_STAT_CHECK_STOP 0x00000010UL 667fcf5ef2aSThomas Huth #define SIGP_STAT_INOPERATIVE 0x00000004UL 668fcf5ef2aSThomas Huth #define SIGP_STAT_INVALID_ORDER 0x00000002UL 669fcf5ef2aSThomas Huth #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL 670fcf5ef2aSThomas Huth 671fcf5ef2aSThomas Huth /* SIGP SET ARCHITECTURE modes */ 672fcf5ef2aSThomas Huth #define SIGP_MODE_ESA_S390 0 673fcf5ef2aSThomas Huth #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1 674fcf5ef2aSThomas Huth #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2 675fcf5ef2aSThomas Huth 676a7c1fadfSAurelien Jarno /* SIGP order code mask corresponding to bit positions 56-63 */ 677a7c1fadfSAurelien Jarno #define SIGP_ORDER_MASK 0x000000ff 678a7c1fadfSAurelien Jarno 679fcf5ef2aSThomas Huth /* machine check interruption code */ 680fcf5ef2aSThomas Huth 681fcf5ef2aSThomas Huth /* subclasses */ 682fcf5ef2aSThomas Huth #define MCIC_SC_SD 0x8000000000000000ULL 683fcf5ef2aSThomas Huth #define MCIC_SC_PD 0x4000000000000000ULL 684fcf5ef2aSThomas Huth #define MCIC_SC_SR 0x2000000000000000ULL 685fcf5ef2aSThomas Huth #define MCIC_SC_CD 0x0800000000000000ULL 686fcf5ef2aSThomas Huth #define MCIC_SC_ED 0x0400000000000000ULL 687fcf5ef2aSThomas Huth #define MCIC_SC_DG 0x0100000000000000ULL 688fcf5ef2aSThomas Huth #define MCIC_SC_W 0x0080000000000000ULL 689fcf5ef2aSThomas Huth #define MCIC_SC_CP 0x0040000000000000ULL 690fcf5ef2aSThomas Huth #define MCIC_SC_SP 0x0020000000000000ULL 691fcf5ef2aSThomas Huth #define MCIC_SC_CK 0x0010000000000000ULL 692fcf5ef2aSThomas Huth 693fcf5ef2aSThomas Huth /* subclass modifiers */ 694fcf5ef2aSThomas Huth #define MCIC_SCM_B 0x0002000000000000ULL 695fcf5ef2aSThomas Huth #define MCIC_SCM_DA 0x0000000020000000ULL 696fcf5ef2aSThomas Huth #define MCIC_SCM_AP 0x0000000000080000ULL 697fcf5ef2aSThomas Huth 698fcf5ef2aSThomas Huth /* storage errors */ 699fcf5ef2aSThomas Huth #define MCIC_SE_SE 0x0000800000000000ULL 700fcf5ef2aSThomas Huth #define MCIC_SE_SC 0x0000400000000000ULL 701fcf5ef2aSThomas Huth #define MCIC_SE_KE 0x0000200000000000ULL 702fcf5ef2aSThomas Huth #define MCIC_SE_DS 0x0000100000000000ULL 703fcf5ef2aSThomas Huth #define MCIC_SE_IE 0x0000000080000000ULL 704fcf5ef2aSThomas Huth 705fcf5ef2aSThomas Huth /* validity bits */ 706fcf5ef2aSThomas Huth #define MCIC_VB_WP 0x0000080000000000ULL 707fcf5ef2aSThomas Huth #define MCIC_VB_MS 0x0000040000000000ULL 708fcf5ef2aSThomas Huth #define MCIC_VB_PM 0x0000020000000000ULL 709fcf5ef2aSThomas Huth #define MCIC_VB_IA 0x0000010000000000ULL 710fcf5ef2aSThomas Huth #define MCIC_VB_FA 0x0000008000000000ULL 711fcf5ef2aSThomas Huth #define MCIC_VB_VR 0x0000004000000000ULL 712fcf5ef2aSThomas Huth #define MCIC_VB_EC 0x0000002000000000ULL 713fcf5ef2aSThomas Huth #define MCIC_VB_FP 0x0000001000000000ULL 714fcf5ef2aSThomas Huth #define MCIC_VB_GR 0x0000000800000000ULL 715fcf5ef2aSThomas Huth #define MCIC_VB_CR 0x0000000400000000ULL 716fcf5ef2aSThomas Huth #define MCIC_VB_ST 0x0000000100000000ULL 717fcf5ef2aSThomas Huth #define MCIC_VB_AR 0x0000000040000000ULL 71862deb62dSFan Zhang #define MCIC_VB_GS 0x0000000008000000ULL 719fcf5ef2aSThomas Huth #define MCIC_VB_PR 0x0000000000200000ULL 720fcf5ef2aSThomas Huth #define MCIC_VB_FC 0x0000000000100000ULL 721fcf5ef2aSThomas Huth #define MCIC_VB_CT 0x0000000000020000ULL 722fcf5ef2aSThomas Huth #define MCIC_VB_CC 0x0000000000010000ULL 723fcf5ef2aSThomas Huth 724b700d75eSDavid Hildenbrand static inline uint64_t s390_build_validity_mcic(void) 725b700d75eSDavid Hildenbrand { 726b700d75eSDavid Hildenbrand uint64_t mcic; 727b700d75eSDavid Hildenbrand 728b700d75eSDavid Hildenbrand /* 729b700d75eSDavid Hildenbrand * Indicate all validity bits (no damage) only. Other bits have to be 730b700d75eSDavid Hildenbrand * added by the caller. (storage errors, subclasses and subclass modifiers) 731b700d75eSDavid Hildenbrand */ 732b700d75eSDavid Hildenbrand mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP | 733b700d75eSDavid Hildenbrand MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR | 734b700d75eSDavid Hildenbrand MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC; 735b700d75eSDavid Hildenbrand if (s390_has_feat(S390_FEAT_VECTOR)) { 736b700d75eSDavid Hildenbrand mcic |= MCIC_VB_VR; 737b700d75eSDavid Hildenbrand } 738b700d75eSDavid Hildenbrand if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) { 739b700d75eSDavid Hildenbrand mcic |= MCIC_VB_GS; 740b700d75eSDavid Hildenbrand } 741b700d75eSDavid Hildenbrand return mcic; 742b700d75eSDavid Hildenbrand } 743b700d75eSDavid Hildenbrand 744a30fb811SDavid Hildenbrand static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg) 745a30fb811SDavid Hildenbrand { 746a30fb811SDavid Hildenbrand cpu_reset(cs); 747a30fb811SDavid Hildenbrand } 748a30fb811SDavid Hildenbrand 749a30fb811SDavid Hildenbrand static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg) 750a30fb811SDavid Hildenbrand { 751a30fb811SDavid Hildenbrand S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 752a30fb811SDavid Hildenbrand 753eac4f827SJanosch Frank scc->reset(cs, S390_CPU_RESET_NORMAL); 754a30fb811SDavid Hildenbrand } 755a30fb811SDavid Hildenbrand 756a30fb811SDavid Hildenbrand static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg) 757a30fb811SDavid Hildenbrand { 758a30fb811SDavid Hildenbrand S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 759a30fb811SDavid Hildenbrand 76081b92223SJanosch Frank scc->reset(cs, S390_CPU_RESET_INITIAL); 761a30fb811SDavid Hildenbrand } 762a30fb811SDavid Hildenbrand 763a30fb811SDavid Hildenbrand static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg) 764a30fb811SDavid Hildenbrand { 765a30fb811SDavid Hildenbrand S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 766a30fb811SDavid Hildenbrand 767a30fb811SDavid Hildenbrand scc->load_normal(cs); 768a30fb811SDavid Hildenbrand } 769a30fb811SDavid Hildenbrand 770c862bddbSDavid Hildenbrand 771c862bddbSDavid Hildenbrand /* cpu.c */ 772c862bddbSDavid Hildenbrand void s390_crypto_reset(void); 773c862bddbSDavid Hildenbrand int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit); 7749138977bSDavid Hildenbrand void s390_set_max_pagesize(uint64_t pagesize, Error **errp); 775c862bddbSDavid Hildenbrand void s390_cmma_reset(void); 776c862bddbSDavid Hildenbrand void s390_enable_css_support(S390CPU *cpu); 777e2c6cd56SCollin Walling void s390_do_cpu_set_diag318(CPUState *cs, run_on_cpu_data arg); 778c862bddbSDavid Hildenbrand int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id, 779c862bddbSDavid Hildenbrand int vq, bool assign); 780c862bddbSDavid Hildenbrand #ifndef CONFIG_USER_ONLY 781c862bddbSDavid Hildenbrand unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu); 782c862bddbSDavid Hildenbrand #else 783c862bddbSDavid Hildenbrand static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) 784c862bddbSDavid Hildenbrand { 785c862bddbSDavid Hildenbrand return 0; 786c862bddbSDavid Hildenbrand } 787c862bddbSDavid Hildenbrand #endif /* CONFIG_USER_ONLY */ 788631b5966SDavid Hildenbrand static inline uint8_t s390_cpu_get_state(S390CPU *cpu) 789631b5966SDavid Hildenbrand { 790631b5966SDavid Hildenbrand return cpu->env.cpu_state; 791631b5966SDavid Hildenbrand } 792c862bddbSDavid Hildenbrand 793c862bddbSDavid Hildenbrand 794c862bddbSDavid Hildenbrand /* cpu_models.c */ 7950442428aSMarkus Armbruster void s390_cpu_list(void); 796c862bddbSDavid Hildenbrand #define cpu_list s390_cpu_list 79735b4df64SDavid Hildenbrand void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, 79835b4df64SDavid Hildenbrand const S390FeatInit feat_init); 79935b4df64SDavid Hildenbrand 800c862bddbSDavid Hildenbrand 801c862bddbSDavid Hildenbrand /* helper.c */ 802b6805e12SIgor Mammedov #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU 803b6805e12SIgor Mammedov #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) 8040dacec87SIgor Mammedov #define CPU_RESOLVING_TYPE TYPE_S390_CPU 805b6805e12SIgor Mammedov 806c862bddbSDavid Hildenbrand /* you can call this signal handler from your SIGBUS and SIGSEGV 807c862bddbSDavid Hildenbrand signal handlers to inform the virtual CPU of exceptions. non zero 808c862bddbSDavid Hildenbrand is returned if the signal was handled by the virtual CPU. */ 809c862bddbSDavid Hildenbrand int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc); 810c862bddbSDavid Hildenbrand #define cpu_signal_handler cpu_s390x_signal_handler 811c862bddbSDavid Hildenbrand 812c862bddbSDavid Hildenbrand 813c862bddbSDavid Hildenbrand /* interrupt.c */ 814c862bddbSDavid Hildenbrand void s390_crw_mchk(void); 815c862bddbSDavid Hildenbrand void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr, 816c862bddbSDavid Hildenbrand uint32_t io_int_parm, uint32_t io_int_word); 8171b98fb99SDavid Hildenbrand #define RA_IGNORED 0 81877b703f8SRichard Henderson void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra); 819c862bddbSDavid Hildenbrand /* service interrupts are floating therefore we must not pass an cpustate */ 820c862bddbSDavid Hildenbrand void s390_sclp_extint(uint32_t parm); 821c862bddbSDavid Hildenbrand 822c862bddbSDavid Hildenbrand /* mmu_helper.c */ 823c862bddbSDavid Hildenbrand int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf, 824c862bddbSDavid Hildenbrand int len, bool is_write); 825c862bddbSDavid Hildenbrand #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \ 826c862bddbSDavid Hildenbrand s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false) 827c862bddbSDavid Hildenbrand #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \ 828c862bddbSDavid Hildenbrand s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true) 829b5e85329SDavid Hildenbrand #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \ 830b5e85329SDavid Hildenbrand s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false) 831c862bddbSDavid Hildenbrand #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \ 832c862bddbSDavid Hildenbrand s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true) 83398ee9bedSDavid Hildenbrand void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra); 8341cca8265SJanosch Frank int s390_cpu_pv_mem_rw(S390CPU *cpu, unsigned int offset, void *hostbuf, 8351cca8265SJanosch Frank int len, bool is_write); 8361cca8265SJanosch Frank #define s390_cpu_pv_mem_read(cpu, offset, dest, len) \ 8371cca8265SJanosch Frank s390_cpu_pv_mem_rw(cpu, offset, dest, len, false) 8381cca8265SJanosch Frank #define s390_cpu_pv_mem_write(cpu, offset, dest, len) \ 8391cca8265SJanosch Frank s390_cpu_pv_mem_rw(cpu, offset, dest, len, true) 840c862bddbSDavid Hildenbrand 84174b4c74dSDavid Hildenbrand /* sigp.c */ 84274b4c74dSDavid Hildenbrand int s390_cpu_restart(S390CPU *cpu); 84374b4c74dSDavid Hildenbrand void s390_init_sigp(void); 84474b4c74dSDavid Hildenbrand 84574b4c74dSDavid Hildenbrand 846c862bddbSDavid Hildenbrand /* outside of target/s390x/ */ 847c862bddbSDavid Hildenbrand S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); 848c862bddbSDavid Hildenbrand 8494f7c64b3SRichard Henderson typedef CPUS390XState CPUArchState; 8502161a612SRichard Henderson typedef S390CPU ArchCPU; 8514f7c64b3SRichard Henderson 8524f7c64b3SRichard Henderson #include "exec/cpu-all.h" 8534f7c64b3SRichard Henderson 854fcf5ef2aSThomas Huth #endif 855