xref: /openbmc/qemu/target/s390x/cpu.h (revision 6b257354c4912d536b999ef32968b1cbb8add4f2)
1fcf5ef2aSThomas Huth /*
2fcf5ef2aSThomas Huth  * S/390 virtual CPU header
3fcf5ef2aSThomas Huth  *
4fcf5ef2aSThomas Huth  *  Copyright (c) 2009 Ulrich Hecht
5fcf5ef2aSThomas Huth  *
6fcf5ef2aSThomas Huth  * This library is free software; you can redistribute it and/or
7fcf5ef2aSThomas Huth  * modify it under the terms of the GNU Lesser General Public
8fcf5ef2aSThomas Huth  * License as published by the Free Software Foundation; either
9fcf5ef2aSThomas Huth  * version 2 of the License, or (at your option) any later version.
10fcf5ef2aSThomas Huth  *
11fcf5ef2aSThomas Huth  * This library is distributed in the hope that it will be useful,
12fcf5ef2aSThomas Huth  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13fcf5ef2aSThomas Huth  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14fcf5ef2aSThomas Huth  * Lesser General Public License for more details.
15fcf5ef2aSThomas Huth  *
16fcf5ef2aSThomas Huth  * Contributions after 2012-10-29 are licensed under the terms of the
17fcf5ef2aSThomas Huth  * GNU GPL, version 2 or (at your option) any later version.
18fcf5ef2aSThomas Huth  *
19fcf5ef2aSThomas Huth  * You should have received a copy of the GNU (Lesser) General Public
20fcf5ef2aSThomas Huth  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21fcf5ef2aSThomas Huth  */
22fcf5ef2aSThomas Huth 
23fcf5ef2aSThomas Huth #ifndef S390X_CPU_H
24fcf5ef2aSThomas Huth #define S390X_CPU_H
25fcf5ef2aSThomas Huth 
26fcf5ef2aSThomas Huth #include "qemu-common.h"
27fcf5ef2aSThomas Huth #include "cpu-qom.h"
28ef2974ccSDavid Hildenbrand #include "cpu_models.h"
29fcf5ef2aSThomas Huth 
30fcf5ef2aSThomas Huth #define TARGET_LONG_BITS 64
31fcf5ef2aSThomas Huth 
32fcf5ef2aSThomas Huth #define ELF_MACHINE_UNAME "S390X"
33fcf5ef2aSThomas Huth 
34fcf5ef2aSThomas Huth #define CPUArchState struct CPUS390XState
35fcf5ef2aSThomas Huth 
36fcf5ef2aSThomas Huth #include "exec/cpu-defs.h"
37fcf5ef2aSThomas Huth #define TARGET_PAGE_BITS 12
38fcf5ef2aSThomas Huth 
39fcf5ef2aSThomas Huth #define TARGET_PHYS_ADDR_SPACE_BITS 64
40fcf5ef2aSThomas Huth #define TARGET_VIRT_ADDR_SPACE_BITS 64
41fcf5ef2aSThomas Huth 
42fcf5ef2aSThomas Huth #include "exec/cpu-all.h"
43fcf5ef2aSThomas Huth 
44fcf5ef2aSThomas Huth #include "fpu/softfloat.h"
45fcf5ef2aSThomas Huth 
46fcf5ef2aSThomas Huth #define NB_MMU_MODES 3
47fcf5ef2aSThomas Huth #define TARGET_INSN_START_EXTRA_WORDS 1
48fcf5ef2aSThomas Huth 
49fcf5ef2aSThomas Huth #define MMU_MODE0_SUFFIX _primary
50fcf5ef2aSThomas Huth #define MMU_MODE1_SUFFIX _secondary
51fcf5ef2aSThomas Huth #define MMU_MODE2_SUFFIX _home
52fcf5ef2aSThomas Huth 
53fcf5ef2aSThomas Huth #define MMU_USER_IDX 0
54fcf5ef2aSThomas Huth 
55fcf5ef2aSThomas Huth #define MAX_EXT_QUEUE 16
56fcf5ef2aSThomas Huth #define MAX_IO_QUEUE 16
57fcf5ef2aSThomas Huth #define MAX_MCHK_QUEUE 16
58fcf5ef2aSThomas Huth 
59fcf5ef2aSThomas Huth #define PSW_MCHK_MASK 0x0004000000000000
60fcf5ef2aSThomas Huth #define PSW_IO_MASK 0x0200000000000000
61fcf5ef2aSThomas Huth 
62fcf5ef2aSThomas Huth typedef struct PSW {
63fcf5ef2aSThomas Huth     uint64_t mask;
64fcf5ef2aSThomas Huth     uint64_t addr;
65fcf5ef2aSThomas Huth } PSW;
66fcf5ef2aSThomas Huth 
67fcf5ef2aSThomas Huth typedef struct ExtQueue {
68fcf5ef2aSThomas Huth     uint32_t code;
69fcf5ef2aSThomas Huth     uint32_t param;
70fcf5ef2aSThomas Huth     uint32_t param64;
71fcf5ef2aSThomas Huth } ExtQueue;
72fcf5ef2aSThomas Huth 
73fcf5ef2aSThomas Huth typedef struct IOIntQueue {
74fcf5ef2aSThomas Huth     uint16_t id;
75fcf5ef2aSThomas Huth     uint16_t nr;
76fcf5ef2aSThomas Huth     uint32_t parm;
77fcf5ef2aSThomas Huth     uint32_t word;
78fcf5ef2aSThomas Huth } IOIntQueue;
79fcf5ef2aSThomas Huth 
80fcf5ef2aSThomas Huth typedef struct MchkQueue {
81fcf5ef2aSThomas Huth     uint16_t type;
82fcf5ef2aSThomas Huth } MchkQueue;
83fcf5ef2aSThomas Huth 
84ef2974ccSDavid Hildenbrand struct CPUS390XState {
85fcf5ef2aSThomas Huth     uint64_t regs[16];     /* GP registers */
86fcf5ef2aSThomas Huth     /*
87fcf5ef2aSThomas Huth      * The floating point registers are part of the vector registers.
88fcf5ef2aSThomas Huth      * vregs[0][0] -> vregs[15][0] are 16 floating point registers
89fcf5ef2aSThomas Huth      */
90fcf5ef2aSThomas Huth     CPU_DoubleU vregs[32][2];  /* vector registers */
91fcf5ef2aSThomas Huth     uint32_t aregs[16];    /* access registers */
92cb4f4bc3SChristian Borntraeger     uint8_t riccb[64];     /* runtime instrumentation control */
9362deb62dSFan Zhang     uint64_t gscb[4];      /* guarded storage control */
94cb4f4bc3SChristian Borntraeger 
95cb4f4bc3SChristian Borntraeger     /* Fields up to this point are not cleared by initial CPU reset */
96cb4f4bc3SChristian Borntraeger     struct {} start_initial_reset_fields;
97fcf5ef2aSThomas Huth 
98fcf5ef2aSThomas Huth     uint32_t fpc;          /* floating-point control register */
99fcf5ef2aSThomas Huth     uint32_t cc_op;
100fcf5ef2aSThomas Huth 
101fcf5ef2aSThomas Huth     float_status fpu_status; /* passed to softfloat lib */
102fcf5ef2aSThomas Huth 
103fcf5ef2aSThomas Huth     /* The low part of a 128-bit return, or remainder of a divide.  */
104fcf5ef2aSThomas Huth     uint64_t retxl;
105fcf5ef2aSThomas Huth 
106fcf5ef2aSThomas Huth     PSW psw;
107fcf5ef2aSThomas Huth 
108fcf5ef2aSThomas Huth     uint64_t cc_src;
109fcf5ef2aSThomas Huth     uint64_t cc_dst;
110fcf5ef2aSThomas Huth     uint64_t cc_vr;
111fcf5ef2aSThomas Huth 
112303c681aSRichard Henderson     uint64_t ex_value;
113303c681aSRichard Henderson 
114fcf5ef2aSThomas Huth     uint64_t __excp_addr;
115fcf5ef2aSThomas Huth     uint64_t psa;
116fcf5ef2aSThomas Huth 
117fcf5ef2aSThomas Huth     uint32_t int_pgm_code;
118fcf5ef2aSThomas Huth     uint32_t int_pgm_ilen;
119fcf5ef2aSThomas Huth 
120fcf5ef2aSThomas Huth     uint32_t int_svc_code;
121fcf5ef2aSThomas Huth     uint32_t int_svc_ilen;
122fcf5ef2aSThomas Huth 
123fcf5ef2aSThomas Huth     uint64_t per_address;
124fcf5ef2aSThomas Huth     uint16_t per_perc_atmid;
125fcf5ef2aSThomas Huth 
126fcf5ef2aSThomas Huth     uint64_t cregs[16]; /* control registers */
127fcf5ef2aSThomas Huth 
128fcf5ef2aSThomas Huth     ExtQueue ext_queue[MAX_EXT_QUEUE];
129fcf5ef2aSThomas Huth     IOIntQueue io_queue[MAX_IO_QUEUE][8];
130fcf5ef2aSThomas Huth     MchkQueue mchk_queue[MAX_MCHK_QUEUE];
131fcf5ef2aSThomas Huth 
132fcf5ef2aSThomas Huth     int pending_int;
133fcf5ef2aSThomas Huth     int ext_index;
134fcf5ef2aSThomas Huth     int io_index[8];
135fcf5ef2aSThomas Huth     int mchk_index;
136fcf5ef2aSThomas Huth 
137fcf5ef2aSThomas Huth     uint64_t ckc;
138fcf5ef2aSThomas Huth     uint64_t cputm;
139fcf5ef2aSThomas Huth     uint32_t todpr;
140fcf5ef2aSThomas Huth 
141fcf5ef2aSThomas Huth     uint64_t pfault_token;
142fcf5ef2aSThomas Huth     uint64_t pfault_compare;
143fcf5ef2aSThomas Huth     uint64_t pfault_select;
144fcf5ef2aSThomas Huth 
145fcf5ef2aSThomas Huth     uint64_t gbea;
146fcf5ef2aSThomas Huth     uint64_t pp;
147fcf5ef2aSThomas Huth 
1481f5c00cfSAlex Bennée     /* Fields up to this point are cleared by a CPU reset */
1491f5c00cfSAlex Bennée     struct {} end_reset_fields;
150fcf5ef2aSThomas Huth 
1511f5c00cfSAlex Bennée     CPU_COMMON
152fcf5ef2aSThomas Huth 
153ca5c1457SDavid Hildenbrand     uint32_t core_id; /* PoP "CPU address", same as cpu_index */
154076d4d39SDavid Hildenbrand     uint64_t cpuid;
155fcf5ef2aSThomas Huth 
156fcf5ef2aSThomas Huth     uint64_t tod_offset;
157fcf5ef2aSThomas Huth     uint64_t tod_basetime;
158fcf5ef2aSThomas Huth     QEMUTimer *tod_timer;
159fcf5ef2aSThomas Huth 
160fcf5ef2aSThomas Huth     QEMUTimer *cpu_timer;
161fcf5ef2aSThomas Huth 
162fcf5ef2aSThomas Huth     /*
163fcf5ef2aSThomas Huth      * The cpu state represents the logical state of a cpu. In contrast to other
164fcf5ef2aSThomas Huth      * architectures, there is a difference between a halt and a stop on s390.
165fcf5ef2aSThomas Huth      * If all cpus are either stopped (including check stop) or in the disabled
166fcf5ef2aSThomas Huth      * wait state, the vm can be shut down.
167fcf5ef2aSThomas Huth      */
168fcf5ef2aSThomas Huth #define CPU_STATE_UNINITIALIZED        0x00
169fcf5ef2aSThomas Huth #define CPU_STATE_STOPPED              0x01
170fcf5ef2aSThomas Huth #define CPU_STATE_CHECK_STOP           0x02
171fcf5ef2aSThomas Huth #define CPU_STATE_OPERATING            0x03
172fcf5ef2aSThomas Huth #define CPU_STATE_LOAD                 0x04
173fcf5ef2aSThomas Huth     uint8_t cpu_state;
174fcf5ef2aSThomas Huth 
175fcf5ef2aSThomas Huth     /* currently processed sigp order */
176fcf5ef2aSThomas Huth     uint8_t sigp_order;
177fcf5ef2aSThomas Huth 
178ef2974ccSDavid Hildenbrand };
179fcf5ef2aSThomas Huth 
180fcf5ef2aSThomas Huth static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
181fcf5ef2aSThomas Huth {
182fcf5ef2aSThomas Huth     return &cs->vregs[nr][0];
183fcf5ef2aSThomas Huth }
184fcf5ef2aSThomas Huth 
185fcf5ef2aSThomas Huth /**
186fcf5ef2aSThomas Huth  * S390CPU:
187fcf5ef2aSThomas Huth  * @env: #CPUS390XState.
188fcf5ef2aSThomas Huth  *
189fcf5ef2aSThomas Huth  * An S/390 CPU.
190fcf5ef2aSThomas Huth  */
191fcf5ef2aSThomas Huth struct S390CPU {
192fcf5ef2aSThomas Huth     /*< private >*/
193fcf5ef2aSThomas Huth     CPUState parent_obj;
194fcf5ef2aSThomas Huth     /*< public >*/
195fcf5ef2aSThomas Huth 
196fcf5ef2aSThomas Huth     CPUS390XState env;
197fcf5ef2aSThomas Huth     S390CPUModel *model;
198fcf5ef2aSThomas Huth     /* needed for live migration */
199fcf5ef2aSThomas Huth     void *irqstate;
200fcf5ef2aSThomas Huth     uint32_t irqstate_saved_size;
201fcf5ef2aSThomas Huth };
202fcf5ef2aSThomas Huth 
203fcf5ef2aSThomas Huth static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
204fcf5ef2aSThomas Huth {
205fcf5ef2aSThomas Huth     return container_of(env, S390CPU, env);
206fcf5ef2aSThomas Huth }
207fcf5ef2aSThomas Huth 
208fcf5ef2aSThomas Huth #define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
209fcf5ef2aSThomas Huth 
210fcf5ef2aSThomas Huth #define ENV_OFFSET offsetof(S390CPU, env)
211fcf5ef2aSThomas Huth 
212fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY
213fcf5ef2aSThomas Huth extern const struct VMStateDescription vmstate_s390_cpu;
214fcf5ef2aSThomas Huth #endif
215fcf5ef2aSThomas Huth 
216fcf5ef2aSThomas Huth /* distinguish between 24 bit and 31 bit addressing */
217fcf5ef2aSThomas Huth #define HIGH_ORDER_BIT 0x80000000
218fcf5ef2aSThomas Huth 
219fcf5ef2aSThomas Huth /* Interrupt Codes */
220fcf5ef2aSThomas Huth /* Program Interrupts */
221fcf5ef2aSThomas Huth #define PGM_OPERATION                   0x0001
222fcf5ef2aSThomas Huth #define PGM_PRIVILEGED                  0x0002
223fcf5ef2aSThomas Huth #define PGM_EXECUTE                     0x0003
224fcf5ef2aSThomas Huth #define PGM_PROTECTION                  0x0004
225fcf5ef2aSThomas Huth #define PGM_ADDRESSING                  0x0005
226fcf5ef2aSThomas Huth #define PGM_SPECIFICATION               0x0006
227fcf5ef2aSThomas Huth #define PGM_DATA                        0x0007
228fcf5ef2aSThomas Huth #define PGM_FIXPT_OVERFLOW              0x0008
229fcf5ef2aSThomas Huth #define PGM_FIXPT_DIVIDE                0x0009
230fcf5ef2aSThomas Huth #define PGM_DEC_OVERFLOW                0x000a
231fcf5ef2aSThomas Huth #define PGM_DEC_DIVIDE                  0x000b
232fcf5ef2aSThomas Huth #define PGM_HFP_EXP_OVERFLOW            0x000c
233fcf5ef2aSThomas Huth #define PGM_HFP_EXP_UNDERFLOW           0x000d
234fcf5ef2aSThomas Huth #define PGM_HFP_SIGNIFICANCE            0x000e
235fcf5ef2aSThomas Huth #define PGM_HFP_DIVIDE                  0x000f
236fcf5ef2aSThomas Huth #define PGM_SEGMENT_TRANS               0x0010
237fcf5ef2aSThomas Huth #define PGM_PAGE_TRANS                  0x0011
238fcf5ef2aSThomas Huth #define PGM_TRANS_SPEC                  0x0012
239fcf5ef2aSThomas Huth #define PGM_SPECIAL_OP                  0x0013
240fcf5ef2aSThomas Huth #define PGM_OPERAND                     0x0015
241fcf5ef2aSThomas Huth #define PGM_TRACE_TABLE                 0x0016
242fcf5ef2aSThomas Huth #define PGM_SPACE_SWITCH                0x001c
243fcf5ef2aSThomas Huth #define PGM_HFP_SQRT                    0x001d
244fcf5ef2aSThomas Huth #define PGM_PC_TRANS_SPEC               0x001f
245fcf5ef2aSThomas Huth #define PGM_AFX_TRANS                   0x0020
246fcf5ef2aSThomas Huth #define PGM_ASX_TRANS                   0x0021
247fcf5ef2aSThomas Huth #define PGM_LX_TRANS                    0x0022
248fcf5ef2aSThomas Huth #define PGM_EX_TRANS                    0x0023
249fcf5ef2aSThomas Huth #define PGM_PRIM_AUTH                   0x0024
250fcf5ef2aSThomas Huth #define PGM_SEC_AUTH                    0x0025
251fcf5ef2aSThomas Huth #define PGM_ALET_SPEC                   0x0028
252fcf5ef2aSThomas Huth #define PGM_ALEN_SPEC                   0x0029
253fcf5ef2aSThomas Huth #define PGM_ALE_SEQ                     0x002a
254fcf5ef2aSThomas Huth #define PGM_ASTE_VALID                  0x002b
255fcf5ef2aSThomas Huth #define PGM_ASTE_SEQ                    0x002c
256fcf5ef2aSThomas Huth #define PGM_EXT_AUTH                    0x002d
257fcf5ef2aSThomas Huth #define PGM_STACK_FULL                  0x0030
258fcf5ef2aSThomas Huth #define PGM_STACK_EMPTY                 0x0031
259fcf5ef2aSThomas Huth #define PGM_STACK_SPEC                  0x0032
260fcf5ef2aSThomas Huth #define PGM_STACK_TYPE                  0x0033
261fcf5ef2aSThomas Huth #define PGM_STACK_OP                    0x0034
262fcf5ef2aSThomas Huth #define PGM_ASCE_TYPE                   0x0038
263fcf5ef2aSThomas Huth #define PGM_REG_FIRST_TRANS             0x0039
264fcf5ef2aSThomas Huth #define PGM_REG_SEC_TRANS               0x003a
265fcf5ef2aSThomas Huth #define PGM_REG_THIRD_TRANS             0x003b
266fcf5ef2aSThomas Huth #define PGM_MONITOR                     0x0040
267fcf5ef2aSThomas Huth #define PGM_PER                         0x0080
268fcf5ef2aSThomas Huth #define PGM_CRYPTO                      0x0119
269fcf5ef2aSThomas Huth 
270fcf5ef2aSThomas Huth /* External Interrupts */
271fcf5ef2aSThomas Huth #define EXT_INTERRUPT_KEY               0x0040
272fcf5ef2aSThomas Huth #define EXT_CLOCK_COMP                  0x1004
273fcf5ef2aSThomas Huth #define EXT_CPU_TIMER                   0x1005
274fcf5ef2aSThomas Huth #define EXT_MALFUNCTION                 0x1200
275fcf5ef2aSThomas Huth #define EXT_EMERGENCY                   0x1201
276fcf5ef2aSThomas Huth #define EXT_EXTERNAL_CALL               0x1202
277fcf5ef2aSThomas Huth #define EXT_ETR                         0x1406
278fcf5ef2aSThomas Huth #define EXT_SERVICE                     0x2401
279fcf5ef2aSThomas Huth #define EXT_VIRTIO                      0x2603
280fcf5ef2aSThomas Huth 
281fcf5ef2aSThomas Huth /* PSW defines */
282fcf5ef2aSThomas Huth #undef PSW_MASK_PER
283fcf5ef2aSThomas Huth #undef PSW_MASK_DAT
284fcf5ef2aSThomas Huth #undef PSW_MASK_IO
285fcf5ef2aSThomas Huth #undef PSW_MASK_EXT
286fcf5ef2aSThomas Huth #undef PSW_MASK_KEY
287fcf5ef2aSThomas Huth #undef PSW_SHIFT_KEY
288fcf5ef2aSThomas Huth #undef PSW_MASK_MCHECK
289fcf5ef2aSThomas Huth #undef PSW_MASK_WAIT
290fcf5ef2aSThomas Huth #undef PSW_MASK_PSTATE
291fcf5ef2aSThomas Huth #undef PSW_MASK_ASC
2923e7e5e0bSDavid Hildenbrand #undef PSW_SHIFT_ASC
293fcf5ef2aSThomas Huth #undef PSW_MASK_CC
294fcf5ef2aSThomas Huth #undef PSW_MASK_PM
295*6b257354SDavid Hildenbrand #undef PSW_SHIFT_MASK_PM
296fcf5ef2aSThomas Huth #undef PSW_MASK_64
297fcf5ef2aSThomas Huth #undef PSW_MASK_32
298fcf5ef2aSThomas Huth #undef PSW_MASK_ESA_ADDR
299fcf5ef2aSThomas Huth 
300fcf5ef2aSThomas Huth #define PSW_MASK_PER            0x4000000000000000ULL
301fcf5ef2aSThomas Huth #define PSW_MASK_DAT            0x0400000000000000ULL
302fcf5ef2aSThomas Huth #define PSW_MASK_IO             0x0200000000000000ULL
303fcf5ef2aSThomas Huth #define PSW_MASK_EXT            0x0100000000000000ULL
304fcf5ef2aSThomas Huth #define PSW_MASK_KEY            0x00F0000000000000ULL
305c8bd9537SDavid Hildenbrand #define PSW_SHIFT_KEY           52
306fcf5ef2aSThomas Huth #define PSW_MASK_MCHECK         0x0004000000000000ULL
307fcf5ef2aSThomas Huth #define PSW_MASK_WAIT           0x0002000000000000ULL
308fcf5ef2aSThomas Huth #define PSW_MASK_PSTATE         0x0001000000000000ULL
309fcf5ef2aSThomas Huth #define PSW_MASK_ASC            0x0000C00000000000ULL
3103e7e5e0bSDavid Hildenbrand #define PSW_SHIFT_ASC           46
311fcf5ef2aSThomas Huth #define PSW_MASK_CC             0x0000300000000000ULL
312fcf5ef2aSThomas Huth #define PSW_MASK_PM             0x00000F0000000000ULL
313*6b257354SDavid Hildenbrand #define PSW_SHIFT_MASK_PM       40
314fcf5ef2aSThomas Huth #define PSW_MASK_64             0x0000000100000000ULL
315fcf5ef2aSThomas Huth #define PSW_MASK_32             0x0000000080000000ULL
316fcf5ef2aSThomas Huth #define PSW_MASK_ESA_ADDR       0x000000007fffffffULL
317fcf5ef2aSThomas Huth 
318fcf5ef2aSThomas Huth #undef PSW_ASC_PRIMARY
319fcf5ef2aSThomas Huth #undef PSW_ASC_ACCREG
320fcf5ef2aSThomas Huth #undef PSW_ASC_SECONDARY
321fcf5ef2aSThomas Huth #undef PSW_ASC_HOME
322fcf5ef2aSThomas Huth 
323fcf5ef2aSThomas Huth #define PSW_ASC_PRIMARY         0x0000000000000000ULL
324fcf5ef2aSThomas Huth #define PSW_ASC_ACCREG          0x0000400000000000ULL
325fcf5ef2aSThomas Huth #define PSW_ASC_SECONDARY       0x0000800000000000ULL
326fcf5ef2aSThomas Huth #define PSW_ASC_HOME            0x0000C00000000000ULL
327fcf5ef2aSThomas Huth 
3283e7e5e0bSDavid Hildenbrand /* the address space values shifted */
3293e7e5e0bSDavid Hildenbrand #define AS_PRIMARY              0
3303e7e5e0bSDavid Hildenbrand #define AS_ACCREG               1
3313e7e5e0bSDavid Hildenbrand #define AS_SECONDARY            2
3323e7e5e0bSDavid Hildenbrand #define AS_HOME                 3
3333e7e5e0bSDavid Hildenbrand 
334fcf5ef2aSThomas Huth /* tb flags */
335fcf5ef2aSThomas Huth 
336159fed45SRichard Henderson #define FLAG_MASK_PSW_SHIFT     31
337159fed45SRichard Henderson #define FLAG_MASK_PER           (PSW_MASK_PER    >> FLAG_MASK_PSW_SHIFT)
338159fed45SRichard Henderson #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
339159fed45SRichard Henderson #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> FLAG_MASK_PSW_SHIFT)
340159fed45SRichard Henderson #define FLAG_MASK_64            (PSW_MASK_64     >> FLAG_MASK_PSW_SHIFT)
341159fed45SRichard Henderson #define FLAG_MASK_32            (PSW_MASK_32     >> FLAG_MASK_PSW_SHIFT)
342159fed45SRichard Henderson #define FLAG_MASK_PSW		(FLAG_MASK_PER | FLAG_MASK_PSTATE \
343159fed45SRichard Henderson                                 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
344fcf5ef2aSThomas Huth 
345fcf5ef2aSThomas Huth /* Control register 0 bits */
346fcf5ef2aSThomas Huth #define CR0_LOWPROT             0x0000000010000000ULL
3473e7e5e0bSDavid Hildenbrand #define CR0_SECONDARY           0x0000000004000000ULL
348fcf5ef2aSThomas Huth #define CR0_EDAT                0x0000000000800000ULL
349fcf5ef2aSThomas Huth 
350fcf5ef2aSThomas Huth /* MMU */
351fcf5ef2aSThomas Huth #define MMU_PRIMARY_IDX         0
352fcf5ef2aSThomas Huth #define MMU_SECONDARY_IDX       1
353fcf5ef2aSThomas Huth #define MMU_HOME_IDX            2
354fcf5ef2aSThomas Huth 
355fcf5ef2aSThomas Huth static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
356fcf5ef2aSThomas Huth {
357fcf5ef2aSThomas Huth     switch (env->psw.mask & PSW_MASK_ASC) {
358fcf5ef2aSThomas Huth     case PSW_ASC_PRIMARY:
359fcf5ef2aSThomas Huth         return MMU_PRIMARY_IDX;
360fcf5ef2aSThomas Huth     case PSW_ASC_SECONDARY:
361fcf5ef2aSThomas Huth         return MMU_SECONDARY_IDX;
362fcf5ef2aSThomas Huth     case PSW_ASC_HOME:
363fcf5ef2aSThomas Huth         return MMU_HOME_IDX;
364fcf5ef2aSThomas Huth     case PSW_ASC_ACCREG:
365fcf5ef2aSThomas Huth         /* Fallthrough: access register mode is not yet supported */
366fcf5ef2aSThomas Huth     default:
367fcf5ef2aSThomas Huth         abort();
368fcf5ef2aSThomas Huth     }
369fcf5ef2aSThomas Huth }
370fcf5ef2aSThomas Huth 
371fcf5ef2aSThomas Huth static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
372fcf5ef2aSThomas Huth                                         target_ulong *cs_base, uint32_t *flags)
373fcf5ef2aSThomas Huth {
374fcf5ef2aSThomas Huth     *pc = env->psw.addr;
375303c681aSRichard Henderson     *cs_base = env->ex_value;
376159fed45SRichard Henderson     *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
377fcf5ef2aSThomas Huth }
378fcf5ef2aSThomas Huth 
379fcf5ef2aSThomas Huth /* PER bits from control register 9 */
380fcf5ef2aSThomas Huth #define PER_CR9_EVENT_BRANCH           0x80000000
381fcf5ef2aSThomas Huth #define PER_CR9_EVENT_IFETCH           0x40000000
382fcf5ef2aSThomas Huth #define PER_CR9_EVENT_STORE            0x20000000
383fcf5ef2aSThomas Huth #define PER_CR9_EVENT_STORE_REAL       0x08000000
384fcf5ef2aSThomas Huth #define PER_CR9_EVENT_NULLIFICATION    0x01000000
385fcf5ef2aSThomas Huth #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
386fcf5ef2aSThomas Huth #define PER_CR9_CONTROL_ALTERATION     0x00200000
387fcf5ef2aSThomas Huth 
388fcf5ef2aSThomas Huth /* PER bits from the PER CODE/ATMID/AI in lowcore */
389fcf5ef2aSThomas Huth #define PER_CODE_EVENT_BRANCH          0x8000
390fcf5ef2aSThomas Huth #define PER_CODE_EVENT_IFETCH          0x4000
391fcf5ef2aSThomas Huth #define PER_CODE_EVENT_STORE           0x2000
392fcf5ef2aSThomas Huth #define PER_CODE_EVENT_STORE_REAL      0x0800
393fcf5ef2aSThomas Huth #define PER_CODE_EVENT_NULLIFICATION   0x0100
394fcf5ef2aSThomas Huth 
395fcf5ef2aSThomas Huth #define EXCP_EXT 1 /* external interrupt */
396fcf5ef2aSThomas Huth #define EXCP_SVC 2 /* supervisor call (syscall) */
397fcf5ef2aSThomas Huth #define EXCP_PGM 3 /* program interruption */
398fcf5ef2aSThomas Huth #define EXCP_IO  7 /* I/O interrupt */
399fcf5ef2aSThomas Huth #define EXCP_MCHK 8 /* machine check */
400fcf5ef2aSThomas Huth 
401fcf5ef2aSThomas Huth #define INTERRUPT_EXT        (1 << 0)
402fcf5ef2aSThomas Huth #define INTERRUPT_TOD        (1 << 1)
403fcf5ef2aSThomas Huth #define INTERRUPT_CPUTIMER   (1 << 2)
404fcf5ef2aSThomas Huth #define INTERRUPT_IO         (1 << 3)
405fcf5ef2aSThomas Huth #define INTERRUPT_MCHK       (1 << 4)
406fcf5ef2aSThomas Huth 
407fcf5ef2aSThomas Huth /* Program Status Word.  */
408fcf5ef2aSThomas Huth #define S390_PSWM_REGNUM 0
409fcf5ef2aSThomas Huth #define S390_PSWA_REGNUM 1
410fcf5ef2aSThomas Huth /* General Purpose Registers.  */
411fcf5ef2aSThomas Huth #define S390_R0_REGNUM 2
412fcf5ef2aSThomas Huth #define S390_R1_REGNUM 3
413fcf5ef2aSThomas Huth #define S390_R2_REGNUM 4
414fcf5ef2aSThomas Huth #define S390_R3_REGNUM 5
415fcf5ef2aSThomas Huth #define S390_R4_REGNUM 6
416fcf5ef2aSThomas Huth #define S390_R5_REGNUM 7
417fcf5ef2aSThomas Huth #define S390_R6_REGNUM 8
418fcf5ef2aSThomas Huth #define S390_R7_REGNUM 9
419fcf5ef2aSThomas Huth #define S390_R8_REGNUM 10
420fcf5ef2aSThomas Huth #define S390_R9_REGNUM 11
421fcf5ef2aSThomas Huth #define S390_R10_REGNUM 12
422fcf5ef2aSThomas Huth #define S390_R11_REGNUM 13
423fcf5ef2aSThomas Huth #define S390_R12_REGNUM 14
424fcf5ef2aSThomas Huth #define S390_R13_REGNUM 15
425fcf5ef2aSThomas Huth #define S390_R14_REGNUM 16
426fcf5ef2aSThomas Huth #define S390_R15_REGNUM 17
427fcf5ef2aSThomas Huth /* Total Core Registers. */
428fcf5ef2aSThomas Huth #define S390_NUM_CORE_REGS 18
429fcf5ef2aSThomas Huth 
430fcf5ef2aSThomas Huth static inline void setcc(S390CPU *cpu, uint64_t cc)
431fcf5ef2aSThomas Huth {
432fcf5ef2aSThomas Huth     CPUS390XState *env = &cpu->env;
433fcf5ef2aSThomas Huth 
434fcf5ef2aSThomas Huth     env->psw.mask &= ~(3ull << 44);
435fcf5ef2aSThomas Huth     env->psw.mask |= (cc & 3) << 44;
436fcf5ef2aSThomas Huth     env->cc_op = cc;
437fcf5ef2aSThomas Huth }
438fcf5ef2aSThomas Huth 
439fcf5ef2aSThomas Huth /* STSI */
440fcf5ef2aSThomas Huth #define STSI_LEVEL_MASK         0x00000000f0000000ULL
441fcf5ef2aSThomas Huth #define STSI_LEVEL_CURRENT      0x0000000000000000ULL
442fcf5ef2aSThomas Huth #define STSI_LEVEL_1            0x0000000010000000ULL
443fcf5ef2aSThomas Huth #define STSI_LEVEL_2            0x0000000020000000ULL
444fcf5ef2aSThomas Huth #define STSI_LEVEL_3            0x0000000030000000ULL
445fcf5ef2aSThomas Huth #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
446fcf5ef2aSThomas Huth #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
447fcf5ef2aSThomas Huth #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
448fcf5ef2aSThomas Huth #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
449fcf5ef2aSThomas Huth 
450fcf5ef2aSThomas Huth /* Basic Machine Configuration */
451fcf5ef2aSThomas Huth struct sysib_111 {
452fcf5ef2aSThomas Huth     uint32_t res1[8];
453fcf5ef2aSThomas Huth     uint8_t  manuf[16];
454fcf5ef2aSThomas Huth     uint8_t  type[4];
455fcf5ef2aSThomas Huth     uint8_t  res2[12];
456fcf5ef2aSThomas Huth     uint8_t  model[16];
457fcf5ef2aSThomas Huth     uint8_t  sequence[16];
458fcf5ef2aSThomas Huth     uint8_t  plant[4];
459fcf5ef2aSThomas Huth     uint8_t  res3[156];
460fcf5ef2aSThomas Huth };
461fcf5ef2aSThomas Huth 
462fcf5ef2aSThomas Huth /* Basic Machine CPU */
463fcf5ef2aSThomas Huth struct sysib_121 {
464fcf5ef2aSThomas Huth     uint32_t res1[80];
465fcf5ef2aSThomas Huth     uint8_t  sequence[16];
466fcf5ef2aSThomas Huth     uint8_t  plant[4];
467fcf5ef2aSThomas Huth     uint8_t  res2[2];
468fcf5ef2aSThomas Huth     uint16_t cpu_addr;
469fcf5ef2aSThomas Huth     uint8_t  res3[152];
470fcf5ef2aSThomas Huth };
471fcf5ef2aSThomas Huth 
472fcf5ef2aSThomas Huth /* Basic Machine CPUs */
473fcf5ef2aSThomas Huth struct sysib_122 {
474fcf5ef2aSThomas Huth     uint8_t res1[32];
475fcf5ef2aSThomas Huth     uint32_t capability;
476fcf5ef2aSThomas Huth     uint16_t total_cpus;
477fcf5ef2aSThomas Huth     uint16_t active_cpus;
478fcf5ef2aSThomas Huth     uint16_t standby_cpus;
479fcf5ef2aSThomas Huth     uint16_t reserved_cpus;
480fcf5ef2aSThomas Huth     uint16_t adjustments[2026];
481fcf5ef2aSThomas Huth };
482fcf5ef2aSThomas Huth 
483fcf5ef2aSThomas Huth /* LPAR CPU */
484fcf5ef2aSThomas Huth struct sysib_221 {
485fcf5ef2aSThomas Huth     uint32_t res1[80];
486fcf5ef2aSThomas Huth     uint8_t  sequence[16];
487fcf5ef2aSThomas Huth     uint8_t  plant[4];
488fcf5ef2aSThomas Huth     uint16_t cpu_id;
489fcf5ef2aSThomas Huth     uint16_t cpu_addr;
490fcf5ef2aSThomas Huth     uint8_t  res3[152];
491fcf5ef2aSThomas Huth };
492fcf5ef2aSThomas Huth 
493fcf5ef2aSThomas Huth /* LPAR CPUs */
494fcf5ef2aSThomas Huth struct sysib_222 {
495fcf5ef2aSThomas Huth     uint32_t res1[32];
496fcf5ef2aSThomas Huth     uint16_t lpar_num;
497fcf5ef2aSThomas Huth     uint8_t  res2;
498fcf5ef2aSThomas Huth     uint8_t  lcpuc;
499fcf5ef2aSThomas Huth     uint16_t total_cpus;
500fcf5ef2aSThomas Huth     uint16_t conf_cpus;
501fcf5ef2aSThomas Huth     uint16_t standby_cpus;
502fcf5ef2aSThomas Huth     uint16_t reserved_cpus;
503fcf5ef2aSThomas Huth     uint8_t  name[8];
504fcf5ef2aSThomas Huth     uint32_t caf;
505fcf5ef2aSThomas Huth     uint8_t  res3[16];
506fcf5ef2aSThomas Huth     uint16_t dedicated_cpus;
507fcf5ef2aSThomas Huth     uint16_t shared_cpus;
508fcf5ef2aSThomas Huth     uint8_t  res4[180];
509fcf5ef2aSThomas Huth };
510fcf5ef2aSThomas Huth 
511fcf5ef2aSThomas Huth /* VM CPUs */
512fcf5ef2aSThomas Huth struct sysib_322 {
513fcf5ef2aSThomas Huth     uint8_t  res1[31];
514fcf5ef2aSThomas Huth     uint8_t  count;
515fcf5ef2aSThomas Huth     struct {
516fcf5ef2aSThomas Huth         uint8_t  res2[4];
517fcf5ef2aSThomas Huth         uint16_t total_cpus;
518fcf5ef2aSThomas Huth         uint16_t conf_cpus;
519fcf5ef2aSThomas Huth         uint16_t standby_cpus;
520fcf5ef2aSThomas Huth         uint16_t reserved_cpus;
521fcf5ef2aSThomas Huth         uint8_t  name[8];
522fcf5ef2aSThomas Huth         uint32_t caf;
523fcf5ef2aSThomas Huth         uint8_t  cpi[16];
524fcf5ef2aSThomas Huth         uint8_t res5[3];
525fcf5ef2aSThomas Huth         uint8_t ext_name_encoding;
526fcf5ef2aSThomas Huth         uint32_t res3;
527fcf5ef2aSThomas Huth         uint8_t uuid[16];
528fcf5ef2aSThomas Huth     } vm[8];
529fcf5ef2aSThomas Huth     uint8_t res4[1504];
530fcf5ef2aSThomas Huth     uint8_t ext_names[8][256];
531fcf5ef2aSThomas Huth };
532fcf5ef2aSThomas Huth 
533fcf5ef2aSThomas Huth /* MMU defines */
534fcf5ef2aSThomas Huth #define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
535fcf5ef2aSThomas Huth #define _ASCE_SUBSPACE          0x200     /* subspace group control           */
536fcf5ef2aSThomas Huth #define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
537fcf5ef2aSThomas Huth #define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
538fcf5ef2aSThomas Huth #define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
539fcf5ef2aSThomas Huth #define _ASCE_REAL_SPACE        0x20      /* real space control               */
540fcf5ef2aSThomas Huth #define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
541fcf5ef2aSThomas Huth #define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
542fcf5ef2aSThomas Huth #define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
543fcf5ef2aSThomas Huth #define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
544fcf5ef2aSThomas Huth #define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
545fcf5ef2aSThomas Huth #define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
546fcf5ef2aSThomas Huth 
547fcf5ef2aSThomas Huth #define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
548fcf5ef2aSThomas Huth #define _REGION_ENTRY_RO        0x200     /* region/segment protection bit    */
549fcf5ef2aSThomas Huth #define _REGION_ENTRY_TF        0xc0      /* region/segment table offset      */
550fcf5ef2aSThomas Huth #define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
551fcf5ef2aSThomas Huth #define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
552fcf5ef2aSThomas Huth #define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
553fcf5ef2aSThomas Huth #define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
554fcf5ef2aSThomas Huth #define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
555fcf5ef2aSThomas Huth #define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
556fcf5ef2aSThomas Huth 
557fcf5ef2aSThomas Huth #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
558fcf5ef2aSThomas Huth #define _SEGMENT_ENTRY_FC       0x400     /* format control                   */
559fcf5ef2aSThomas Huth #define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
560fcf5ef2aSThomas Huth #define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
561fcf5ef2aSThomas Huth 
5628a4719f5SAurelien Jarno #define VADDR_PX                0xff000   /* page index bits                  */
5638a4719f5SAurelien Jarno 
564fcf5ef2aSThomas Huth #define _PAGE_RO        0x200            /* HW read-only bit  */
565fcf5ef2aSThomas Huth #define _PAGE_INVALID   0x400            /* HW invalid bit    */
566fcf5ef2aSThomas Huth #define _PAGE_RES0      0x800            /* bit must be zero  */
567fcf5ef2aSThomas Huth 
568fcf5ef2aSThomas Huth #define SK_C                    (0x1 << 1)
569fcf5ef2aSThomas Huth #define SK_R                    (0x1 << 2)
570fcf5ef2aSThomas Huth #define SK_F                    (0x1 << 3)
571fcf5ef2aSThomas Huth #define SK_ACC_MASK             (0xf << 4)
572fcf5ef2aSThomas Huth 
573fcf5ef2aSThomas Huth /* SIGP order codes */
574fcf5ef2aSThomas Huth #define SIGP_SENSE             0x01
575fcf5ef2aSThomas Huth #define SIGP_EXTERNAL_CALL     0x02
576fcf5ef2aSThomas Huth #define SIGP_EMERGENCY         0x03
577fcf5ef2aSThomas Huth #define SIGP_START             0x04
578fcf5ef2aSThomas Huth #define SIGP_STOP              0x05
579fcf5ef2aSThomas Huth #define SIGP_RESTART           0x06
580fcf5ef2aSThomas Huth #define SIGP_STOP_STORE_STATUS 0x09
581fcf5ef2aSThomas Huth #define SIGP_INITIAL_CPU_RESET 0x0b
582fcf5ef2aSThomas Huth #define SIGP_CPU_RESET         0x0c
583fcf5ef2aSThomas Huth #define SIGP_SET_PREFIX        0x0d
584fcf5ef2aSThomas Huth #define SIGP_STORE_STATUS_ADDR 0x0e
585fcf5ef2aSThomas Huth #define SIGP_SET_ARCH          0x12
586fcf5ef2aSThomas Huth #define SIGP_STORE_ADTL_STATUS 0x17
587fcf5ef2aSThomas Huth 
588fcf5ef2aSThomas Huth /* SIGP condition codes */
589fcf5ef2aSThomas Huth #define SIGP_CC_ORDER_CODE_ACCEPTED 0
590fcf5ef2aSThomas Huth #define SIGP_CC_STATUS_STORED       1
591fcf5ef2aSThomas Huth #define SIGP_CC_BUSY                2
592fcf5ef2aSThomas Huth #define SIGP_CC_NOT_OPERATIONAL     3
593fcf5ef2aSThomas Huth 
594fcf5ef2aSThomas Huth /* SIGP status bits */
595fcf5ef2aSThomas Huth #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
596fcf5ef2aSThomas Huth #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
597fcf5ef2aSThomas Huth #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
598fcf5ef2aSThomas Huth #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
599fcf5ef2aSThomas Huth #define SIGP_STAT_STOPPED           0x00000040UL
600fcf5ef2aSThomas Huth #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
601fcf5ef2aSThomas Huth #define SIGP_STAT_CHECK_STOP        0x00000010UL
602fcf5ef2aSThomas Huth #define SIGP_STAT_INOPERATIVE       0x00000004UL
603fcf5ef2aSThomas Huth #define SIGP_STAT_INVALID_ORDER     0x00000002UL
604fcf5ef2aSThomas Huth #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
605fcf5ef2aSThomas Huth 
606fcf5ef2aSThomas Huth /* SIGP SET ARCHITECTURE modes */
607fcf5ef2aSThomas Huth #define SIGP_MODE_ESA_S390 0
608fcf5ef2aSThomas Huth #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
609fcf5ef2aSThomas Huth #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
610fcf5ef2aSThomas Huth 
611a7c1fadfSAurelien Jarno /* SIGP order code mask corresponding to bit positions 56-63 */
612a7c1fadfSAurelien Jarno #define SIGP_ORDER_MASK 0x000000ff
613a7c1fadfSAurelien Jarno 
614fcf5ef2aSThomas Huth /* from s390-virtio-ccw */
615fcf5ef2aSThomas Huth #define MEM_SECTION_SIZE             0x10000000UL
616fcf5ef2aSThomas Huth #define MAX_AVAIL_SLOTS              32
617fcf5ef2aSThomas Huth 
618fcf5ef2aSThomas Huth /* machine check interruption code */
619fcf5ef2aSThomas Huth 
620fcf5ef2aSThomas Huth /* subclasses */
621fcf5ef2aSThomas Huth #define MCIC_SC_SD 0x8000000000000000ULL
622fcf5ef2aSThomas Huth #define MCIC_SC_PD 0x4000000000000000ULL
623fcf5ef2aSThomas Huth #define MCIC_SC_SR 0x2000000000000000ULL
624fcf5ef2aSThomas Huth #define MCIC_SC_CD 0x0800000000000000ULL
625fcf5ef2aSThomas Huth #define MCIC_SC_ED 0x0400000000000000ULL
626fcf5ef2aSThomas Huth #define MCIC_SC_DG 0x0100000000000000ULL
627fcf5ef2aSThomas Huth #define MCIC_SC_W  0x0080000000000000ULL
628fcf5ef2aSThomas Huth #define MCIC_SC_CP 0x0040000000000000ULL
629fcf5ef2aSThomas Huth #define MCIC_SC_SP 0x0020000000000000ULL
630fcf5ef2aSThomas Huth #define MCIC_SC_CK 0x0010000000000000ULL
631fcf5ef2aSThomas Huth 
632fcf5ef2aSThomas Huth /* subclass modifiers */
633fcf5ef2aSThomas Huth #define MCIC_SCM_B  0x0002000000000000ULL
634fcf5ef2aSThomas Huth #define MCIC_SCM_DA 0x0000000020000000ULL
635fcf5ef2aSThomas Huth #define MCIC_SCM_AP 0x0000000000080000ULL
636fcf5ef2aSThomas Huth 
637fcf5ef2aSThomas Huth /* storage errors */
638fcf5ef2aSThomas Huth #define MCIC_SE_SE 0x0000800000000000ULL
639fcf5ef2aSThomas Huth #define MCIC_SE_SC 0x0000400000000000ULL
640fcf5ef2aSThomas Huth #define MCIC_SE_KE 0x0000200000000000ULL
641fcf5ef2aSThomas Huth #define MCIC_SE_DS 0x0000100000000000ULL
642fcf5ef2aSThomas Huth #define MCIC_SE_IE 0x0000000080000000ULL
643fcf5ef2aSThomas Huth 
644fcf5ef2aSThomas Huth /* validity bits */
645fcf5ef2aSThomas Huth #define MCIC_VB_WP 0x0000080000000000ULL
646fcf5ef2aSThomas Huth #define MCIC_VB_MS 0x0000040000000000ULL
647fcf5ef2aSThomas Huth #define MCIC_VB_PM 0x0000020000000000ULL
648fcf5ef2aSThomas Huth #define MCIC_VB_IA 0x0000010000000000ULL
649fcf5ef2aSThomas Huth #define MCIC_VB_FA 0x0000008000000000ULL
650fcf5ef2aSThomas Huth #define MCIC_VB_VR 0x0000004000000000ULL
651fcf5ef2aSThomas Huth #define MCIC_VB_EC 0x0000002000000000ULL
652fcf5ef2aSThomas Huth #define MCIC_VB_FP 0x0000001000000000ULL
653fcf5ef2aSThomas Huth #define MCIC_VB_GR 0x0000000800000000ULL
654fcf5ef2aSThomas Huth #define MCIC_VB_CR 0x0000000400000000ULL
655fcf5ef2aSThomas Huth #define MCIC_VB_ST 0x0000000100000000ULL
656fcf5ef2aSThomas Huth #define MCIC_VB_AR 0x0000000040000000ULL
65762deb62dSFan Zhang #define MCIC_VB_GS 0x0000000008000000ULL
658fcf5ef2aSThomas Huth #define MCIC_VB_PR 0x0000000000200000ULL
659fcf5ef2aSThomas Huth #define MCIC_VB_FC 0x0000000000100000ULL
660fcf5ef2aSThomas Huth #define MCIC_VB_CT 0x0000000000020000ULL
661fcf5ef2aSThomas Huth #define MCIC_VB_CC 0x0000000000010000ULL
662fcf5ef2aSThomas Huth 
663c862bddbSDavid Hildenbrand 
664c862bddbSDavid Hildenbrand /* cpu.c */
665c862bddbSDavid Hildenbrand int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low);
666c862bddbSDavid Hildenbrand int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low);
667c862bddbSDavid Hildenbrand void s390_crypto_reset(void);
668c862bddbSDavid Hildenbrand bool s390_get_squash_mcss(void);
669c862bddbSDavid Hildenbrand int s390_get_memslot_count(void);
670c862bddbSDavid Hildenbrand int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit);
671c862bddbSDavid Hildenbrand void s390_cmma_reset(void);
672c862bddbSDavid Hildenbrand int s390_cpu_restart(S390CPU *cpu);
673c862bddbSDavid Hildenbrand void s390_enable_css_support(S390CPU *cpu);
674c862bddbSDavid Hildenbrand int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id,
675c862bddbSDavid Hildenbrand                                 int vq, bool assign);
676c862bddbSDavid Hildenbrand #ifndef CONFIG_USER_ONLY
677c862bddbSDavid Hildenbrand unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
678c862bddbSDavid Hildenbrand #else
679c862bddbSDavid Hildenbrand static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
680c862bddbSDavid Hildenbrand {
681c862bddbSDavid Hildenbrand     return 0;
682c862bddbSDavid Hildenbrand }
683c862bddbSDavid Hildenbrand #endif /* CONFIG_USER_ONLY */
684c862bddbSDavid Hildenbrand 
685c862bddbSDavid Hildenbrand 
686c862bddbSDavid Hildenbrand /* cpu_models.c */
687c862bddbSDavid Hildenbrand void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
688c862bddbSDavid Hildenbrand #define cpu_list s390_cpu_list
689c862bddbSDavid Hildenbrand const char *s390_default_cpu_model_name(void);
690c862bddbSDavid Hildenbrand 
691c862bddbSDavid Hildenbrand 
692c862bddbSDavid Hildenbrand /* helper.c */
6936ad76dfdSIgor Mammedov #define cpu_init(cpu_model) cpu_generic_init(TYPE_S390_CPU, cpu_model)
694524d18d8SDavid Hildenbrand S390CPU *s390x_new_cpu(const char *typename, uint32_t core_id, Error **errp);
695c862bddbSDavid Hildenbrand /* you can call this signal handler from your SIGBUS and SIGSEGV
696c862bddbSDavid Hildenbrand    signal handlers to inform the virtual CPU of exceptions. non zero
697c862bddbSDavid Hildenbrand    is returned if the signal was handled by the virtual CPU.  */
698c862bddbSDavid Hildenbrand int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc);
699c862bddbSDavid Hildenbrand #define cpu_signal_handler cpu_s390x_signal_handler
700c862bddbSDavid Hildenbrand 
701c862bddbSDavid Hildenbrand 
702c862bddbSDavid Hildenbrand /* interrupt.c */
703c862bddbSDavid Hildenbrand void s390_crw_mchk(void);
704c862bddbSDavid Hildenbrand void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
705c862bddbSDavid Hildenbrand                        uint32_t io_int_parm, uint32_t io_int_word);
706c862bddbSDavid Hildenbrand /* automatically detect the instruction length */
707c862bddbSDavid Hildenbrand #define ILEN_AUTO                   0xff
708c862bddbSDavid Hildenbrand void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
709c862bddbSDavid Hildenbrand /* service interrupts are floating therefore we must not pass an cpustate */
710c862bddbSDavid Hildenbrand void s390_sclp_extint(uint32_t parm);
711c862bddbSDavid Hildenbrand 
712c862bddbSDavid Hildenbrand 
713c862bddbSDavid Hildenbrand /* mmu_helper.c */
714c862bddbSDavid Hildenbrand int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
715c862bddbSDavid Hildenbrand                          int len, bool is_write);
716c862bddbSDavid Hildenbrand #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len)    \
717c862bddbSDavid Hildenbrand         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
718c862bddbSDavid Hildenbrand #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len)       \
719c862bddbSDavid Hildenbrand         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
720c862bddbSDavid Hildenbrand #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len)   \
721c862bddbSDavid Hildenbrand         s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
722c862bddbSDavid Hildenbrand 
723c862bddbSDavid Hildenbrand 
724c862bddbSDavid Hildenbrand /* outside of target/s390x/ */
725c862bddbSDavid Hildenbrand S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
726c862bddbSDavid Hildenbrand 
727fcf5ef2aSThomas Huth #endif
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