1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "cpu_vendorid.h" 26 #include "pmu.h" 27 #include "internals.h" 28 #include "time_helper.h" 29 #include "exec/exec-all.h" 30 #include "qapi/error.h" 31 #include "qemu/error-report.h" 32 #include "hw/qdev-properties.h" 33 #include "migration/vmstate.h" 34 #include "fpu/softfloat-helpers.h" 35 #include "sysemu/kvm.h" 36 #include "kvm_riscv.h" 37 #include "tcg/tcg.h" 38 39 /* RISC-V CPU definitions */ 40 41 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 42 (QEMU_VERSION_MINOR << 8) | \ 43 (QEMU_VERSION_MICRO)) 44 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 45 46 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 47 48 struct isa_ext_data { 49 const char *name; 50 bool multi_letter; 51 int min_version; 52 int ext_enable_offset; 53 }; 54 55 #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ 56 {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 57 58 /** 59 * Here are the ordering rules of extension naming defined by RISC-V 60 * specification : 61 * 1. All extensions should be separated from other multi-letter extensions 62 * by an underscore. 63 * 2. The first letter following the 'Z' conventionally indicates the most 64 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 65 * If multiple 'Z' extensions are named, they should be ordered first 66 * by category, then alphabetically within a category. 67 * 3. Standard supervisor-level extensions (starts with 'S') should be 68 * listed after standard unprivileged extensions. If multiple 69 * supervisor-level extensions are listed, they should be ordered 70 * alphabetically. 71 * 4. Non-standard extensions (starts with 'X') must be listed after all 72 * standard extensions. They must be separated from other multi-letter 73 * extensions by an underscore. 74 */ 75 static const struct isa_ext_data isa_edata_arr[] = { 76 ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), 77 ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v), 78 ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), 79 ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), 80 ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), 81 ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), 82 ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh), 83 ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), 84 ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), 85 ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), 86 ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), 87 ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), 88 ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), 89 ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), 90 ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), 91 ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), 92 ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), 93 ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), 94 ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), 95 ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), 96 ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), 97 ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), 98 ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), 99 ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), 100 ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), 101 ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), 102 ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), 103 ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), 104 ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), 105 ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), 106 ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), 107 ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), 108 ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), 109 ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), 110 ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), 111 ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), 112 ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), 113 ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), 114 ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), 115 ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), 116 ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), 117 ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), 118 ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), 119 ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), 120 ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv), 121 ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), 122 ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx), 123 ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), 124 ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), 125 ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 126 }; 127 128 static bool isa_ext_is_enabled(RISCVCPU *cpu, 129 const struct isa_ext_data *edata) 130 { 131 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 132 133 return *ext_enabled; 134 } 135 136 static void isa_ext_update_enabled(RISCVCPU *cpu, 137 const struct isa_ext_data *edata, bool en) 138 { 139 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 140 141 *ext_enabled = en; 142 } 143 144 const char * const riscv_int_regnames[] = { 145 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 146 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 147 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 148 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 149 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 150 }; 151 152 const char * const riscv_int_regnamesh[] = { 153 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 154 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 155 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 156 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 157 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 158 "x30h/t5h", "x31h/t6h" 159 }; 160 161 const char * const riscv_fpr_regnames[] = { 162 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 163 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 164 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 165 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 166 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 167 "f30/ft10", "f31/ft11" 168 }; 169 170 static const char * const riscv_excp_names[] = { 171 "misaligned_fetch", 172 "fault_fetch", 173 "illegal_instruction", 174 "breakpoint", 175 "misaligned_load", 176 "fault_load", 177 "misaligned_store", 178 "fault_store", 179 "user_ecall", 180 "supervisor_ecall", 181 "hypervisor_ecall", 182 "machine_ecall", 183 "exec_page_fault", 184 "load_page_fault", 185 "reserved", 186 "store_page_fault", 187 "reserved", 188 "reserved", 189 "reserved", 190 "reserved", 191 "guest_exec_page_fault", 192 "guest_load_page_fault", 193 "reserved", 194 "guest_store_page_fault", 195 }; 196 197 static const char * const riscv_intr_names[] = { 198 "u_software", 199 "s_software", 200 "vs_software", 201 "m_software", 202 "u_timer", 203 "s_timer", 204 "vs_timer", 205 "m_timer", 206 "u_external", 207 "s_external", 208 "vs_external", 209 "m_external", 210 "reserved", 211 "reserved", 212 "reserved", 213 "reserved" 214 }; 215 216 static void register_cpu_props(DeviceState *dev); 217 218 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 219 { 220 if (async) { 221 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 222 riscv_intr_names[cause] : "(unknown)"; 223 } else { 224 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 225 riscv_excp_names[cause] : "(unknown)"; 226 } 227 } 228 229 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 230 { 231 env->misa_mxl_max = env->misa_mxl = mxl; 232 env->misa_ext_mask = env->misa_ext = ext; 233 } 234 235 static void set_priv_version(CPURISCVState *env, int priv_ver) 236 { 237 env->priv_ver = priv_ver; 238 } 239 240 static void set_vext_version(CPURISCVState *env, int vext_ver) 241 { 242 env->vext_ver = vext_ver; 243 } 244 245 static void riscv_any_cpu_init(Object *obj) 246 { 247 CPURISCVState *env = &RISCV_CPU(obj)->env; 248 #if defined(TARGET_RISCV32) 249 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 250 #elif defined(TARGET_RISCV64) 251 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 252 #endif 253 set_priv_version(env, PRIV_VERSION_1_12_0); 254 register_cpu_props(DEVICE(obj)); 255 } 256 257 #if defined(TARGET_RISCV64) 258 static void rv64_base_cpu_init(Object *obj) 259 { 260 CPURISCVState *env = &RISCV_CPU(obj)->env; 261 /* We set this in the realise function */ 262 set_misa(env, MXL_RV64, 0); 263 register_cpu_props(DEVICE(obj)); 264 /* Set latest version of privileged specification */ 265 set_priv_version(env, PRIV_VERSION_1_12_0); 266 } 267 268 static void rv64_sifive_u_cpu_init(Object *obj) 269 { 270 CPURISCVState *env = &RISCV_CPU(obj)->env; 271 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 272 register_cpu_props(DEVICE(obj)); 273 set_priv_version(env, PRIV_VERSION_1_10_0); 274 } 275 276 static void rv64_sifive_e_cpu_init(Object *obj) 277 { 278 CPURISCVState *env = &RISCV_CPU(obj)->env; 279 RISCVCPU *cpu = RISCV_CPU(obj); 280 281 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 282 register_cpu_props(DEVICE(obj)); 283 set_priv_version(env, PRIV_VERSION_1_10_0); 284 cpu->cfg.mmu = false; 285 } 286 287 static void rv64_thead_c906_cpu_init(Object *obj) 288 { 289 CPURISCVState *env = &RISCV_CPU(obj)->env; 290 RISCVCPU *cpu = RISCV_CPU(obj); 291 292 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 293 set_priv_version(env, PRIV_VERSION_1_11_0); 294 295 cpu->cfg.ext_g = true; 296 cpu->cfg.ext_c = true; 297 cpu->cfg.ext_u = true; 298 cpu->cfg.ext_s = true; 299 cpu->cfg.ext_icsr = true; 300 cpu->cfg.ext_zfh = true; 301 cpu->cfg.mmu = true; 302 cpu->cfg.ext_xtheadba = true; 303 cpu->cfg.ext_xtheadbb = true; 304 cpu->cfg.ext_xtheadbs = true; 305 cpu->cfg.ext_xtheadcmo = true; 306 cpu->cfg.ext_xtheadcondmov = true; 307 cpu->cfg.ext_xtheadfmemidx = true; 308 cpu->cfg.ext_xtheadmac = true; 309 cpu->cfg.ext_xtheadmemidx = true; 310 cpu->cfg.ext_xtheadmempair = true; 311 cpu->cfg.ext_xtheadsync = true; 312 313 cpu->cfg.mvendorid = THEAD_VENDOR_ID; 314 } 315 316 static void rv128_base_cpu_init(Object *obj) 317 { 318 if (qemu_tcg_mttcg_enabled()) { 319 /* Missing 128-bit aligned atomics */ 320 error_report("128-bit RISC-V currently does not work with Multi " 321 "Threaded TCG. Please use: -accel tcg,thread=single"); 322 exit(EXIT_FAILURE); 323 } 324 CPURISCVState *env = &RISCV_CPU(obj)->env; 325 /* We set this in the realise function */ 326 set_misa(env, MXL_RV128, 0); 327 register_cpu_props(DEVICE(obj)); 328 /* Set latest version of privileged specification */ 329 set_priv_version(env, PRIV_VERSION_1_12_0); 330 } 331 #else 332 static void rv32_base_cpu_init(Object *obj) 333 { 334 CPURISCVState *env = &RISCV_CPU(obj)->env; 335 /* We set this in the realise function */ 336 set_misa(env, MXL_RV32, 0); 337 register_cpu_props(DEVICE(obj)); 338 /* Set latest version of privileged specification */ 339 set_priv_version(env, PRIV_VERSION_1_12_0); 340 } 341 342 static void rv32_sifive_u_cpu_init(Object *obj) 343 { 344 CPURISCVState *env = &RISCV_CPU(obj)->env; 345 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 346 register_cpu_props(DEVICE(obj)); 347 set_priv_version(env, PRIV_VERSION_1_10_0); 348 } 349 350 static void rv32_sifive_e_cpu_init(Object *obj) 351 { 352 CPURISCVState *env = &RISCV_CPU(obj)->env; 353 RISCVCPU *cpu = RISCV_CPU(obj); 354 355 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 356 register_cpu_props(DEVICE(obj)); 357 set_priv_version(env, PRIV_VERSION_1_10_0); 358 cpu->cfg.mmu = false; 359 } 360 361 static void rv32_ibex_cpu_init(Object *obj) 362 { 363 CPURISCVState *env = &RISCV_CPU(obj)->env; 364 RISCVCPU *cpu = RISCV_CPU(obj); 365 366 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 367 register_cpu_props(DEVICE(obj)); 368 set_priv_version(env, PRIV_VERSION_1_11_0); 369 cpu->cfg.mmu = false; 370 cpu->cfg.epmp = true; 371 } 372 373 static void rv32_imafcu_nommu_cpu_init(Object *obj) 374 { 375 CPURISCVState *env = &RISCV_CPU(obj)->env; 376 RISCVCPU *cpu = RISCV_CPU(obj); 377 378 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 379 register_cpu_props(DEVICE(obj)); 380 set_priv_version(env, PRIV_VERSION_1_10_0); 381 cpu->cfg.mmu = false; 382 } 383 #endif 384 385 #if defined(CONFIG_KVM) 386 static void riscv_host_cpu_init(Object *obj) 387 { 388 CPURISCVState *env = &RISCV_CPU(obj)->env; 389 #if defined(TARGET_RISCV32) 390 set_misa(env, MXL_RV32, 0); 391 #elif defined(TARGET_RISCV64) 392 set_misa(env, MXL_RV64, 0); 393 #endif 394 register_cpu_props(DEVICE(obj)); 395 } 396 #endif 397 398 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 399 { 400 ObjectClass *oc; 401 char *typename; 402 char **cpuname; 403 404 cpuname = g_strsplit(cpu_model, ",", 1); 405 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 406 oc = object_class_by_name(typename); 407 g_strfreev(cpuname); 408 g_free(typename); 409 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 410 object_class_is_abstract(oc)) { 411 return NULL; 412 } 413 return oc; 414 } 415 416 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 417 { 418 RISCVCPU *cpu = RISCV_CPU(cs); 419 CPURISCVState *env = &cpu->env; 420 int i; 421 422 #if !defined(CONFIG_USER_ONLY) 423 if (riscv_has_ext(env, RVH)) { 424 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 425 } 426 #endif 427 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 428 #ifndef CONFIG_USER_ONLY 429 { 430 static const int dump_csrs[] = { 431 CSR_MHARTID, 432 CSR_MSTATUS, 433 CSR_MSTATUSH, 434 /* 435 * CSR_SSTATUS is intentionally omitted here as its value 436 * can be figured out by looking at CSR_MSTATUS 437 */ 438 CSR_HSTATUS, 439 CSR_VSSTATUS, 440 CSR_MIP, 441 CSR_MIE, 442 CSR_MIDELEG, 443 CSR_HIDELEG, 444 CSR_MEDELEG, 445 CSR_HEDELEG, 446 CSR_MTVEC, 447 CSR_STVEC, 448 CSR_VSTVEC, 449 CSR_MEPC, 450 CSR_SEPC, 451 CSR_VSEPC, 452 CSR_MCAUSE, 453 CSR_SCAUSE, 454 CSR_VSCAUSE, 455 CSR_MTVAL, 456 CSR_STVAL, 457 CSR_HTVAL, 458 CSR_MTVAL2, 459 CSR_MSCRATCH, 460 CSR_SSCRATCH, 461 CSR_SATP, 462 CSR_MMTE, 463 CSR_UPMBASE, 464 CSR_UPMMASK, 465 CSR_SPMBASE, 466 CSR_SPMMASK, 467 CSR_MPMBASE, 468 CSR_MPMMASK, 469 }; 470 471 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 472 int csrno = dump_csrs[i]; 473 target_ulong val = 0; 474 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 475 476 /* 477 * Rely on the smode, hmode, etc, predicates within csr.c 478 * to do the filtering of the registers that are present. 479 */ 480 if (res == RISCV_EXCP_NONE) { 481 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 482 csr_ops[csrno].name, val); 483 } 484 } 485 } 486 #endif 487 488 for (i = 0; i < 32; i++) { 489 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 490 riscv_int_regnames[i], env->gpr[i]); 491 if ((i & 3) == 3) { 492 qemu_fprintf(f, "\n"); 493 } 494 } 495 if (flags & CPU_DUMP_FPU) { 496 for (i = 0; i < 32; i++) { 497 qemu_fprintf(f, " %-8s %016" PRIx64, 498 riscv_fpr_regnames[i], env->fpr[i]); 499 if ((i & 3) == 3) { 500 qemu_fprintf(f, "\n"); 501 } 502 } 503 } 504 } 505 506 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 507 { 508 RISCVCPU *cpu = RISCV_CPU(cs); 509 CPURISCVState *env = &cpu->env; 510 511 if (env->xl == MXL_RV32) { 512 env->pc = (int32_t)value; 513 } else { 514 env->pc = value; 515 } 516 } 517 518 static vaddr riscv_cpu_get_pc(CPUState *cs) 519 { 520 RISCVCPU *cpu = RISCV_CPU(cs); 521 CPURISCVState *env = &cpu->env; 522 523 /* Match cpu_get_tb_cpu_state. */ 524 if (env->xl == MXL_RV32) { 525 return env->pc & UINT32_MAX; 526 } 527 return env->pc; 528 } 529 530 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 531 const TranslationBlock *tb) 532 { 533 RISCVCPU *cpu = RISCV_CPU(cs); 534 CPURISCVState *env = &cpu->env; 535 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 536 537 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 538 539 if (xl == MXL_RV32) { 540 env->pc = (int32_t) tb->pc; 541 } else { 542 env->pc = tb->pc; 543 } 544 } 545 546 static bool riscv_cpu_has_work(CPUState *cs) 547 { 548 #ifndef CONFIG_USER_ONLY 549 RISCVCPU *cpu = RISCV_CPU(cs); 550 CPURISCVState *env = &cpu->env; 551 /* 552 * Definition of the WFI instruction requires it to ignore the privilege 553 * mode and delegation registers, but respect individual enables 554 */ 555 return riscv_cpu_all_pending(env) != 0; 556 #else 557 return true; 558 #endif 559 } 560 561 static void riscv_restore_state_to_opc(CPUState *cs, 562 const TranslationBlock *tb, 563 const uint64_t *data) 564 { 565 RISCVCPU *cpu = RISCV_CPU(cs); 566 CPURISCVState *env = &cpu->env; 567 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 568 569 if (xl == MXL_RV32) { 570 env->pc = (int32_t)data[0]; 571 } else { 572 env->pc = data[0]; 573 } 574 env->bins = data[1]; 575 } 576 577 static void riscv_cpu_reset_hold(Object *obj) 578 { 579 #ifndef CONFIG_USER_ONLY 580 uint8_t iprio; 581 int i, irq, rdzero; 582 #endif 583 CPUState *cs = CPU(obj); 584 RISCVCPU *cpu = RISCV_CPU(cs); 585 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 586 CPURISCVState *env = &cpu->env; 587 588 if (mcc->parent_phases.hold) { 589 mcc->parent_phases.hold(obj); 590 } 591 #ifndef CONFIG_USER_ONLY 592 env->misa_mxl = env->misa_mxl_max; 593 env->priv = PRV_M; 594 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 595 if (env->misa_mxl > MXL_RV32) { 596 /* 597 * The reset status of SXL/UXL is undefined, but mstatus is WARL 598 * and we must ensure that the value after init is valid for read. 599 */ 600 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 601 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 602 if (riscv_has_ext(env, RVH)) { 603 env->vsstatus = set_field(env->vsstatus, 604 MSTATUS64_SXL, env->misa_mxl); 605 env->vsstatus = set_field(env->vsstatus, 606 MSTATUS64_UXL, env->misa_mxl); 607 env->mstatus_hs = set_field(env->mstatus_hs, 608 MSTATUS64_SXL, env->misa_mxl); 609 env->mstatus_hs = set_field(env->mstatus_hs, 610 MSTATUS64_UXL, env->misa_mxl); 611 } 612 } 613 env->mcause = 0; 614 env->miclaim = MIP_SGEIP; 615 env->pc = env->resetvec; 616 env->bins = 0; 617 env->two_stage_lookup = false; 618 619 /* Initialized default priorities of local interrupts. */ 620 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 621 iprio = riscv_cpu_default_priority(i); 622 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 623 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 624 env->hviprio[i] = 0; 625 } 626 i = 0; 627 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 628 if (!rdzero) { 629 env->hviprio[irq] = env->miprio[irq]; 630 } 631 i++; 632 } 633 /* mmte is supposed to have pm.current hardwired to 1 */ 634 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 635 #endif 636 env->xl = riscv_cpu_mxl(env); 637 riscv_cpu_update_mask(env); 638 cs->exception_index = RISCV_EXCP_NONE; 639 env->load_res = -1; 640 set_default_nan_mode(1, &env->fp_status); 641 642 #ifndef CONFIG_USER_ONLY 643 if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { 644 riscv_trigger_init(env); 645 } 646 647 if (kvm_enabled()) { 648 kvm_riscv_reset_vcpu(cpu); 649 } 650 #endif 651 } 652 653 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 654 { 655 RISCVCPU *cpu = RISCV_CPU(s); 656 657 switch (riscv_cpu_mxl(&cpu->env)) { 658 case MXL_RV32: 659 info->print_insn = print_insn_riscv32; 660 break; 661 case MXL_RV64: 662 info->print_insn = print_insn_riscv64; 663 break; 664 case MXL_RV128: 665 info->print_insn = print_insn_riscv128; 666 break; 667 default: 668 g_assert_not_reached(); 669 } 670 } 671 672 /* 673 * Check consistency between chosen extensions while setting 674 * cpu->cfg accordingly, doing a set_misa() in the end. 675 */ 676 static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 677 { 678 CPURISCVState *env = &cpu->env; 679 uint32_t ext = 0; 680 681 /* Do some ISA extension error checking */ 682 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && 683 cpu->cfg.ext_a && cpu->cfg.ext_f && 684 cpu->cfg.ext_d && 685 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 686 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 687 cpu->cfg.ext_i = true; 688 cpu->cfg.ext_m = true; 689 cpu->cfg.ext_a = true; 690 cpu->cfg.ext_f = true; 691 cpu->cfg.ext_d = true; 692 cpu->cfg.ext_icsr = true; 693 cpu->cfg.ext_ifencei = true; 694 } 695 696 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 697 error_setg(errp, 698 "I and E extensions are incompatible"); 699 return; 700 } 701 702 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 703 error_setg(errp, 704 "Either I or E extension must be set"); 705 return; 706 } 707 708 if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { 709 error_setg(errp, 710 "Setting S extension without U extension is illegal"); 711 return; 712 } 713 714 if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { 715 error_setg(errp, 716 "H depends on an I base integer ISA with 32 x registers"); 717 return; 718 } 719 720 if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { 721 error_setg(errp, "H extension implicitly requires S-mode"); 722 return; 723 } 724 725 if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { 726 error_setg(errp, "F extension requires Zicsr"); 727 return; 728 } 729 730 if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { 731 error_setg(errp, "Zawrs extension requires A extension"); 732 return; 733 } 734 735 if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { 736 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 737 return; 738 } 739 740 if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { 741 error_setg(errp, "D extension requires F extension"); 742 return; 743 } 744 745 if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { 746 error_setg(errp, "V extension requires D extension"); 747 return; 748 } 749 750 if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { 751 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 752 return; 753 } 754 755 /* Set the ISA extensions, checks should have happened above */ 756 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || 757 cpu->cfg.ext_zhinxmin) { 758 cpu->cfg.ext_zfinx = true; 759 } 760 761 if (cpu->cfg.ext_zfinx) { 762 if (!cpu->cfg.ext_icsr) { 763 error_setg(errp, "Zfinx extension requires Zicsr"); 764 return; 765 } 766 if (cpu->cfg.ext_f) { 767 error_setg(errp, 768 "Zfinx cannot be supported together with F extension"); 769 return; 770 } 771 } 772 773 if (cpu->cfg.ext_zk) { 774 cpu->cfg.ext_zkn = true; 775 cpu->cfg.ext_zkr = true; 776 cpu->cfg.ext_zkt = true; 777 } 778 779 if (cpu->cfg.ext_zkn) { 780 cpu->cfg.ext_zbkb = true; 781 cpu->cfg.ext_zbkc = true; 782 cpu->cfg.ext_zbkx = true; 783 cpu->cfg.ext_zkne = true; 784 cpu->cfg.ext_zknd = true; 785 cpu->cfg.ext_zknh = true; 786 } 787 788 if (cpu->cfg.ext_zks) { 789 cpu->cfg.ext_zbkb = true; 790 cpu->cfg.ext_zbkc = true; 791 cpu->cfg.ext_zbkx = true; 792 cpu->cfg.ext_zksed = true; 793 cpu->cfg.ext_zksh = true; 794 } 795 796 if (cpu->cfg.ext_i) { 797 ext |= RVI; 798 } 799 if (cpu->cfg.ext_e) { 800 ext |= RVE; 801 } 802 if (cpu->cfg.ext_m) { 803 ext |= RVM; 804 } 805 if (cpu->cfg.ext_a) { 806 ext |= RVA; 807 } 808 if (cpu->cfg.ext_f) { 809 ext |= RVF; 810 } 811 if (cpu->cfg.ext_d) { 812 ext |= RVD; 813 } 814 if (cpu->cfg.ext_c) { 815 ext |= RVC; 816 } 817 if (cpu->cfg.ext_s) { 818 ext |= RVS; 819 } 820 if (cpu->cfg.ext_u) { 821 ext |= RVU; 822 } 823 if (cpu->cfg.ext_h) { 824 ext |= RVH; 825 } 826 if (cpu->cfg.ext_v) { 827 int vext_version = VEXT_VERSION_1_00_0; 828 ext |= RVV; 829 if (!is_power_of_2(cpu->cfg.vlen)) { 830 error_setg(errp, 831 "Vector extension VLEN must be power of 2"); 832 return; 833 } 834 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 835 error_setg(errp, 836 "Vector extension implementation only supports VLEN " 837 "in the range [128, %d]", RV_VLEN_MAX); 838 return; 839 } 840 if (!is_power_of_2(cpu->cfg.elen)) { 841 error_setg(errp, 842 "Vector extension ELEN must be power of 2"); 843 return; 844 } 845 if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { 846 error_setg(errp, 847 "Vector extension implementation only supports ELEN " 848 "in the range [8, 64]"); 849 return; 850 } 851 if (cpu->cfg.vext_spec) { 852 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 853 vext_version = VEXT_VERSION_1_00_0; 854 } else { 855 error_setg(errp, 856 "Unsupported vector spec version '%s'", 857 cpu->cfg.vext_spec); 858 return; 859 } 860 } else { 861 qemu_log("vector version is not specified, " 862 "use the default value v1.0\n"); 863 } 864 set_vext_version(env, vext_version); 865 } 866 if (cpu->cfg.ext_j) { 867 ext |= RVJ; 868 } 869 870 set_misa(env, env->misa_mxl, ext); 871 } 872 873 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 874 { 875 CPUState *cs = CPU(dev); 876 RISCVCPU *cpu = RISCV_CPU(dev); 877 CPURISCVState *env = &cpu->env; 878 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 879 CPUClass *cc = CPU_CLASS(mcc); 880 int i, priv_version = -1; 881 Error *local_err = NULL; 882 883 cpu_exec_realizefn(cs, &local_err); 884 if (local_err != NULL) { 885 error_propagate(errp, local_err); 886 return; 887 } 888 889 if (cpu->cfg.priv_spec) { 890 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 891 priv_version = PRIV_VERSION_1_12_0; 892 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 893 priv_version = PRIV_VERSION_1_11_0; 894 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 895 priv_version = PRIV_VERSION_1_10_0; 896 } else { 897 error_setg(errp, 898 "Unsupported privilege spec version '%s'", 899 cpu->cfg.priv_spec); 900 return; 901 } 902 } 903 904 if (priv_version >= PRIV_VERSION_1_10_0) { 905 set_priv_version(env, priv_version); 906 } 907 908 /* Force disable extensions if priv spec version does not match */ 909 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 910 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 911 (env->priv_ver < isa_edata_arr[i].min_version)) { 912 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 913 #ifndef CONFIG_USER_ONLY 914 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 915 " because privilege spec version does not match", 916 isa_edata_arr[i].name, env->mhartid); 917 #else 918 warn_report("disabling %s extension because " 919 "privilege spec version does not match", 920 isa_edata_arr[i].name); 921 #endif 922 } 923 } 924 925 if (cpu->cfg.mmu) { 926 riscv_set_feature(env, RISCV_FEATURE_MMU); 927 } 928 929 if (cpu->cfg.pmp) { 930 riscv_set_feature(env, RISCV_FEATURE_PMP); 931 932 /* 933 * Enhanced PMP should only be available 934 * on harts with PMP support 935 */ 936 if (cpu->cfg.epmp) { 937 riscv_set_feature(env, RISCV_FEATURE_EPMP); 938 } 939 } 940 941 if (cpu->cfg.debug) { 942 riscv_set_feature(env, RISCV_FEATURE_DEBUG); 943 } 944 945 946 #ifndef CONFIG_USER_ONLY 947 if (cpu->cfg.ext_sstc) { 948 riscv_timer_init(cpu); 949 } 950 #endif /* CONFIG_USER_ONLY */ 951 952 /* Validate that MISA_MXL is set properly. */ 953 switch (env->misa_mxl_max) { 954 #ifdef TARGET_RISCV64 955 case MXL_RV64: 956 case MXL_RV128: 957 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 958 break; 959 #endif 960 case MXL_RV32: 961 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 962 break; 963 default: 964 g_assert_not_reached(); 965 } 966 assert(env->misa_mxl_max == env->misa_mxl); 967 968 riscv_cpu_validate_set_extensions(cpu, &local_err); 969 if (local_err != NULL) { 970 error_propagate(errp, local_err); 971 return; 972 } 973 974 #ifndef CONFIG_USER_ONLY 975 if (cpu->cfg.pmu_num) { 976 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 977 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 978 riscv_pmu_timer_cb, cpu); 979 } 980 } 981 #endif 982 983 riscv_cpu_register_gdb_regs_for_features(cs); 984 985 qemu_init_vcpu(cs); 986 cpu_reset(cs); 987 988 mcc->parent_realize(dev, errp); 989 } 990 991 #ifndef CONFIG_USER_ONLY 992 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 993 { 994 RISCVCPU *cpu = RISCV_CPU(opaque); 995 CPURISCVState *env = &cpu->env; 996 997 if (irq < IRQ_LOCAL_MAX) { 998 switch (irq) { 999 case IRQ_U_SOFT: 1000 case IRQ_S_SOFT: 1001 case IRQ_VS_SOFT: 1002 case IRQ_M_SOFT: 1003 case IRQ_U_TIMER: 1004 case IRQ_S_TIMER: 1005 case IRQ_VS_TIMER: 1006 case IRQ_M_TIMER: 1007 case IRQ_U_EXT: 1008 case IRQ_VS_EXT: 1009 case IRQ_M_EXT: 1010 if (kvm_enabled()) { 1011 kvm_riscv_set_irq(cpu, irq, level); 1012 } else { 1013 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); 1014 } 1015 break; 1016 case IRQ_S_EXT: 1017 if (kvm_enabled()) { 1018 kvm_riscv_set_irq(cpu, irq, level); 1019 } else { 1020 env->external_seip = level; 1021 riscv_cpu_update_mip(cpu, 1 << irq, 1022 BOOL_TO_MASK(level | env->software_seip)); 1023 } 1024 break; 1025 default: 1026 g_assert_not_reached(); 1027 } 1028 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 1029 /* Require H-extension for handling guest local interrupts */ 1030 if (!riscv_has_ext(env, RVH)) { 1031 g_assert_not_reached(); 1032 } 1033 1034 /* Compute bit position in HGEIP CSR */ 1035 irq = irq - IRQ_LOCAL_MAX + 1; 1036 if (env->geilen < irq) { 1037 g_assert_not_reached(); 1038 } 1039 1040 /* Update HGEIP CSR */ 1041 env->hgeip &= ~((target_ulong)1 << irq); 1042 if (level) { 1043 env->hgeip |= (target_ulong)1 << irq; 1044 } 1045 1046 /* Update mip.SGEIP bit */ 1047 riscv_cpu_update_mip(cpu, MIP_SGEIP, 1048 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1049 } else { 1050 g_assert_not_reached(); 1051 } 1052 } 1053 #endif /* CONFIG_USER_ONLY */ 1054 1055 static void riscv_cpu_init(Object *obj) 1056 { 1057 RISCVCPU *cpu = RISCV_CPU(obj); 1058 1059 cpu->cfg.ext_ifencei = true; 1060 cpu->cfg.ext_icsr = true; 1061 cpu->cfg.mmu = true; 1062 cpu->cfg.pmp = true; 1063 1064 cpu_set_cpustate_pointers(cpu); 1065 1066 #ifndef CONFIG_USER_ONLY 1067 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 1068 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1069 #endif /* CONFIG_USER_ONLY */ 1070 } 1071 1072 static Property riscv_cpu_extensions[] = { 1073 /* Defaults for standard extensions */ 1074 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 1075 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 1076 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), 1077 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 1078 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 1079 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 1080 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 1081 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 1082 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 1083 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 1084 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 1085 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 1086 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1087 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1088 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1089 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1090 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1091 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), 1092 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1093 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1094 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1095 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1096 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1097 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1098 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1099 1100 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1101 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1102 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1103 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1104 1105 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1106 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1107 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1108 1109 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1110 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1111 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1112 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1113 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1114 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1115 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1116 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1117 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1118 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1119 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1120 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1121 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1122 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1123 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1124 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1125 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1126 1127 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1128 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1129 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1130 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1131 1132 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1133 1134 /* Vendor-specific custom extensions */ 1135 DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), 1136 DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), 1137 DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), 1138 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), 1139 DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), 1140 DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), 1141 DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), 1142 DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), 1143 DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), 1144 DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), 1145 DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), 1146 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1147 1148 /* These are experimental so mark with 'x-' */ 1149 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 1150 /* ePMP 0.9.3 */ 1151 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1152 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1153 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1154 1155 DEFINE_PROP_END_OF_LIST(), 1156 }; 1157 1158 /* 1159 * Register CPU props based on env.misa_ext. If a non-zero 1160 * value was set, register only the required cpu->cfg.ext_* 1161 * properties and leave. env.misa_ext = 0 means that we want 1162 * all the default properties to be registered. 1163 */ 1164 static void register_cpu_props(DeviceState *dev) 1165 { 1166 RISCVCPU *cpu = RISCV_CPU(OBJECT(dev)); 1167 uint32_t misa_ext = cpu->env.misa_ext; 1168 Property *prop; 1169 1170 /* 1171 * If misa_ext is not zero, set cfg properties now to 1172 * allow them to be read during riscv_cpu_realize() 1173 * later on. 1174 */ 1175 if (cpu->env.misa_ext != 0) { 1176 cpu->cfg.ext_i = misa_ext & RVI; 1177 cpu->cfg.ext_e = misa_ext & RVE; 1178 cpu->cfg.ext_m = misa_ext & RVM; 1179 cpu->cfg.ext_a = misa_ext & RVA; 1180 cpu->cfg.ext_f = misa_ext & RVF; 1181 cpu->cfg.ext_d = misa_ext & RVD; 1182 cpu->cfg.ext_v = misa_ext & RVV; 1183 cpu->cfg.ext_c = misa_ext & RVC; 1184 cpu->cfg.ext_s = misa_ext & RVS; 1185 cpu->cfg.ext_u = misa_ext & RVU; 1186 cpu->cfg.ext_h = misa_ext & RVH; 1187 cpu->cfg.ext_j = misa_ext & RVJ; 1188 1189 /* 1190 * We don't want to set the default riscv_cpu_extensions 1191 * in this case. 1192 */ 1193 return; 1194 } 1195 1196 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1197 qdev_property_add_static(dev, prop); 1198 } 1199 } 1200 1201 static Property riscv_cpu_properties[] = { 1202 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1203 1204 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1205 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1206 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1207 1208 #ifndef CONFIG_USER_ONLY 1209 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1210 #endif 1211 1212 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1213 1214 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1215 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1216 DEFINE_PROP_END_OF_LIST(), 1217 }; 1218 1219 static gchar *riscv_gdb_arch_name(CPUState *cs) 1220 { 1221 RISCVCPU *cpu = RISCV_CPU(cs); 1222 CPURISCVState *env = &cpu->env; 1223 1224 switch (riscv_cpu_mxl(env)) { 1225 case MXL_RV32: 1226 return g_strdup("riscv:rv32"); 1227 case MXL_RV64: 1228 case MXL_RV128: 1229 return g_strdup("riscv:rv64"); 1230 default: 1231 g_assert_not_reached(); 1232 } 1233 } 1234 1235 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1236 { 1237 RISCVCPU *cpu = RISCV_CPU(cs); 1238 1239 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1240 return cpu->dyn_csr_xml; 1241 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1242 return cpu->dyn_vreg_xml; 1243 } 1244 1245 return NULL; 1246 } 1247 1248 #ifndef CONFIG_USER_ONLY 1249 #include "hw/core/sysemu-cpu-ops.h" 1250 1251 static const struct SysemuCPUOps riscv_sysemu_ops = { 1252 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1253 .write_elf64_note = riscv_cpu_write_elf64_note, 1254 .write_elf32_note = riscv_cpu_write_elf32_note, 1255 .legacy_vmsd = &vmstate_riscv_cpu, 1256 }; 1257 #endif 1258 1259 #include "hw/core/tcg-cpu-ops.h" 1260 1261 static const struct TCGCPUOps riscv_tcg_ops = { 1262 .initialize = riscv_translate_init, 1263 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1264 .restore_state_to_opc = riscv_restore_state_to_opc, 1265 1266 #ifndef CONFIG_USER_ONLY 1267 .tlb_fill = riscv_cpu_tlb_fill, 1268 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1269 .do_interrupt = riscv_cpu_do_interrupt, 1270 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1271 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1272 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1273 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1274 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1275 #endif /* !CONFIG_USER_ONLY */ 1276 }; 1277 1278 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1279 { 1280 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1281 CPUClass *cc = CPU_CLASS(c); 1282 DeviceClass *dc = DEVICE_CLASS(c); 1283 ResettableClass *rc = RESETTABLE_CLASS(c); 1284 1285 device_class_set_parent_realize(dc, riscv_cpu_realize, 1286 &mcc->parent_realize); 1287 1288 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1289 &mcc->parent_phases); 1290 1291 cc->class_by_name = riscv_cpu_class_by_name; 1292 cc->has_work = riscv_cpu_has_work; 1293 cc->dump_state = riscv_cpu_dump_state; 1294 cc->set_pc = riscv_cpu_set_pc; 1295 cc->get_pc = riscv_cpu_get_pc; 1296 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1297 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1298 cc->gdb_num_core_regs = 33; 1299 cc->gdb_stop_before_watchpoint = true; 1300 cc->disas_set_info = riscv_cpu_disas_set_info; 1301 #ifndef CONFIG_USER_ONLY 1302 cc->sysemu_ops = &riscv_sysemu_ops; 1303 #endif 1304 cc->gdb_arch_name = riscv_gdb_arch_name; 1305 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1306 cc->tcg_ops = &riscv_tcg_ops; 1307 1308 device_class_set_props(dc, riscv_cpu_properties); 1309 } 1310 1311 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) 1312 { 1313 char *old = *isa_str; 1314 char *new = *isa_str; 1315 int i; 1316 1317 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1318 if (isa_edata_arr[i].multi_letter && 1319 isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1320 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1321 g_free(old); 1322 old = new; 1323 } 1324 } 1325 1326 *isa_str = new; 1327 } 1328 1329 char *riscv_isa_string(RISCVCPU *cpu) 1330 { 1331 int i; 1332 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1333 char *isa_str = g_new(char, maxlen); 1334 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1335 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1336 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1337 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1338 } 1339 } 1340 *p = '\0'; 1341 if (!cpu->cfg.short_isa_string) { 1342 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1343 } 1344 return isa_str; 1345 } 1346 1347 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1348 { 1349 ObjectClass *class_a = (ObjectClass *)a; 1350 ObjectClass *class_b = (ObjectClass *)b; 1351 const char *name_a, *name_b; 1352 1353 name_a = object_class_get_name(class_a); 1354 name_b = object_class_get_name(class_b); 1355 return strcmp(name_a, name_b); 1356 } 1357 1358 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1359 { 1360 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1361 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1362 1363 qemu_printf("%.*s\n", len, typename); 1364 } 1365 1366 void riscv_cpu_list(void) 1367 { 1368 GSList *list; 1369 1370 list = object_class_get_list(TYPE_RISCV_CPU, false); 1371 list = g_slist_sort(list, riscv_cpu_list_compare); 1372 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1373 g_slist_free(list); 1374 } 1375 1376 #define DEFINE_CPU(type_name, initfn) \ 1377 { \ 1378 .name = type_name, \ 1379 .parent = TYPE_RISCV_CPU, \ 1380 .instance_init = initfn \ 1381 } 1382 1383 static const TypeInfo riscv_cpu_type_infos[] = { 1384 { 1385 .name = TYPE_RISCV_CPU, 1386 .parent = TYPE_CPU, 1387 .instance_size = sizeof(RISCVCPU), 1388 .instance_align = __alignof__(RISCVCPU), 1389 .instance_init = riscv_cpu_init, 1390 .abstract = true, 1391 .class_size = sizeof(RISCVCPUClass), 1392 .class_init = riscv_cpu_class_init, 1393 }, 1394 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1395 #if defined(CONFIG_KVM) 1396 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1397 #endif 1398 #if defined(TARGET_RISCV32) 1399 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1400 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1401 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1402 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1403 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1404 #elif defined(TARGET_RISCV64) 1405 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1406 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1407 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1408 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1409 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), 1410 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1411 #endif 1412 }; 1413 1414 DEFINE_TYPES(riscv_cpu_type_infos) 1415