174433bf0SRichard Henderson /* 274433bf0SRichard Henderson * RISC-V cpu parameters for qemu. 374433bf0SRichard Henderson * 474433bf0SRichard Henderson * Copyright (c) 2017-2018 SiFive, Inc. 5*97d348ccSPhilippe Mathieu-Daudé * SPDX-License-Identifier: GPL-2.0-or-later 674433bf0SRichard Henderson */ 774433bf0SRichard Henderson 874433bf0SRichard Henderson #ifndef RISCV_CPU_PARAM_H 94f31b54bSMarkus Armbruster #define RISCV_CPU_PARAM_H 1074433bf0SRichard Henderson 1174433bf0SRichard Henderson #if defined(TARGET_RISCV64) 1274433bf0SRichard Henderson # define TARGET_LONG_BITS 64 1374433bf0SRichard Henderson # define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ 1474433bf0SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ 1574433bf0SRichard Henderson #elif defined(TARGET_RISCV32) 1674433bf0SRichard Henderson # define TARGET_LONG_BITS 32 1774433bf0SRichard Henderson # define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ 1874433bf0SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ 1974433bf0SRichard Henderson #endif 2074433bf0SRichard Henderson #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ 21c445593dSAlistair Francis /* 22c445593dSAlistair Francis * The current MMU Modes are: 23c445593dSAlistair Francis * - U mode 0b000 24c445593dSAlistair Francis * - S mode 0b001 25c445593dSAlistair Francis * - M mode 0b011 26c445593dSAlistair Francis * - U mode HLV/HLVX/HSV 0b100 27c445593dSAlistair Francis * - S mode HLV/HLVX/HSV 0b101 28c445593dSAlistair Francis * - M mode HLV/HLVX/HSV 0b111 29c445593dSAlistair Francis */ 3074433bf0SRichard Henderson 31e92dd332SPhilippe Mathieu-Daudé #define TCG_GUEST_DEFAULT_MO 0 32e92dd332SPhilippe Mathieu-Daudé 3374433bf0SRichard Henderson #endif 34