1/* 2 * translate-fp.c 3 * 4 * Standard FPU translation 5 */ 6 7static inline void gen_reset_fpstatus(void) 8{ 9 gen_helper_reset_fpstatus(cpu_env); 10} 11 12static inline void gen_compute_fprf_float64(TCGv_i64 arg) 13{ 14 gen_helper_compute_fprf_float64(cpu_env, arg); 15 gen_helper_float_check_status(cpu_env); 16} 17 18#if defined(TARGET_PPC64) 19static void gen_set_cr1_from_fpscr(DisasContext *ctx) 20{ 21 TCGv_i32 tmp = tcg_temp_new_i32(); 22 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr); 23 tcg_gen_shri_i32(cpu_crf[1], tmp, 28); 24 tcg_temp_free_i32(tmp); 25} 26#else 27static void gen_set_cr1_from_fpscr(DisasContext *ctx) 28{ 29 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28); 30} 31#endif 32 33/*** Floating-Point arithmetic ***/ 34#define _GEN_FLOAT_ACB(name, op1, op2, set_fprf, type) \ 35static void gen_f##name(DisasContext *ctx) \ 36{ \ 37 TCGv_i64 t0; \ 38 TCGv_i64 t1; \ 39 TCGv_i64 t2; \ 40 TCGv_i64 t3; \ 41 if (unlikely(!ctx->fpu_enabled)) { \ 42 gen_exception(ctx, POWERPC_EXCP_FPU); \ 43 return; \ 44 } \ 45 t0 = tcg_temp_new_i64(); \ 46 t1 = tcg_temp_new_i64(); \ 47 t2 = tcg_temp_new_i64(); \ 48 t3 = tcg_temp_new_i64(); \ 49 gen_reset_fpstatus(); \ 50 get_fpr(t0, rA(ctx->opcode)); \ 51 get_fpr(t1, rC(ctx->opcode)); \ 52 get_fpr(t2, rB(ctx->opcode)); \ 53 gen_helper_f##name(t3, cpu_env, t0, t1, t2); \ 54 set_fpr(rD(ctx->opcode), t3); \ 55 if (set_fprf) { \ 56 gen_compute_fprf_float64(t3); \ 57 } \ 58 if (unlikely(Rc(ctx->opcode) != 0)) { \ 59 gen_set_cr1_from_fpscr(ctx); \ 60 } \ 61 tcg_temp_free_i64(t0); \ 62 tcg_temp_free_i64(t1); \ 63 tcg_temp_free_i64(t2); \ 64 tcg_temp_free_i64(t3); \ 65} 66 67#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ 68_GEN_FLOAT_ACB(name, 0x3F, op2, set_fprf, type); \ 69_GEN_FLOAT_ACB(name##s, 0x3B, op2, set_fprf, type); 70 71#define _GEN_FLOAT_AB(name, op1, op2, inval, set_fprf, type) \ 72static void gen_f##name(DisasContext *ctx) \ 73{ \ 74 TCGv_i64 t0; \ 75 TCGv_i64 t1; \ 76 TCGv_i64 t2; \ 77 if (unlikely(!ctx->fpu_enabled)) { \ 78 gen_exception(ctx, POWERPC_EXCP_FPU); \ 79 return; \ 80 } \ 81 t0 = tcg_temp_new_i64(); \ 82 t1 = tcg_temp_new_i64(); \ 83 t2 = tcg_temp_new_i64(); \ 84 gen_reset_fpstatus(); \ 85 get_fpr(t0, rA(ctx->opcode)); \ 86 get_fpr(t1, rB(ctx->opcode)); \ 87 gen_helper_f##name(t2, cpu_env, t0, t1); \ 88 set_fpr(rD(ctx->opcode), t2); \ 89 if (set_fprf) { \ 90 gen_compute_fprf_float64(t2); \ 91 } \ 92 if (unlikely(Rc(ctx->opcode) != 0)) { \ 93 gen_set_cr1_from_fpscr(ctx); \ 94 } \ 95 tcg_temp_free_i64(t0); \ 96 tcg_temp_free_i64(t1); \ 97 tcg_temp_free_i64(t2); \ 98} 99#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ 100_GEN_FLOAT_AB(name, 0x3F, op2, inval, set_fprf, type); \ 101_GEN_FLOAT_AB(name##s, 0x3B, op2, inval, set_fprf, type); 102 103#define _GEN_FLOAT_AC(name, op1, op2, inval, set_fprf, type) \ 104static void gen_f##name(DisasContext *ctx) \ 105{ \ 106 TCGv_i64 t0; \ 107 TCGv_i64 t1; \ 108 TCGv_i64 t2; \ 109 if (unlikely(!ctx->fpu_enabled)) { \ 110 gen_exception(ctx, POWERPC_EXCP_FPU); \ 111 return; \ 112 } \ 113 t0 = tcg_temp_new_i64(); \ 114 t1 = tcg_temp_new_i64(); \ 115 t2 = tcg_temp_new_i64(); \ 116 gen_reset_fpstatus(); \ 117 get_fpr(t0, rA(ctx->opcode)); \ 118 get_fpr(t1, rC(ctx->opcode)); \ 119 gen_helper_f##name(t2, cpu_env, t0, t1); \ 120 set_fpr(rD(ctx->opcode), t2); \ 121 if (set_fprf) { \ 122 gen_compute_fprf_float64(t2); \ 123 } \ 124 if (unlikely(Rc(ctx->opcode) != 0)) { \ 125 gen_set_cr1_from_fpscr(ctx); \ 126 } \ 127 tcg_temp_free_i64(t0); \ 128 tcg_temp_free_i64(t1); \ 129 tcg_temp_free_i64(t2); \ 130} 131#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ 132_GEN_FLOAT_AC(name, 0x3F, op2, inval, set_fprf, type); \ 133_GEN_FLOAT_AC(name##s, 0x3B, op2, inval, set_fprf, type); 134 135#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ 136static void gen_f##name(DisasContext *ctx) \ 137{ \ 138 TCGv_i64 t0; \ 139 TCGv_i64 t1; \ 140 if (unlikely(!ctx->fpu_enabled)) { \ 141 gen_exception(ctx, POWERPC_EXCP_FPU); \ 142 return; \ 143 } \ 144 t0 = tcg_temp_new_i64(); \ 145 t1 = tcg_temp_new_i64(); \ 146 gen_reset_fpstatus(); \ 147 get_fpr(t0, rB(ctx->opcode)); \ 148 gen_helper_f##name(t1, cpu_env, t0); \ 149 set_fpr(rD(ctx->opcode), t1); \ 150 if (set_fprf) { \ 151 gen_helper_compute_fprf_float64(cpu_env, t1); \ 152 } \ 153 gen_helper_float_check_status(cpu_env); \ 154 if (unlikely(Rc(ctx->opcode) != 0)) { \ 155 gen_set_cr1_from_fpscr(ctx); \ 156 } \ 157 tcg_temp_free_i64(t0); \ 158 tcg_temp_free_i64(t1); \ 159} 160 161#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ 162static void gen_f##name(DisasContext *ctx) \ 163{ \ 164 TCGv_i64 t0; \ 165 TCGv_i64 t1; \ 166 if (unlikely(!ctx->fpu_enabled)) { \ 167 gen_exception(ctx, POWERPC_EXCP_FPU); \ 168 return; \ 169 } \ 170 t0 = tcg_temp_new_i64(); \ 171 t1 = tcg_temp_new_i64(); \ 172 gen_reset_fpstatus(); \ 173 get_fpr(t0, rB(ctx->opcode)); \ 174 gen_helper_f##name(t1, cpu_env, t0); \ 175 set_fpr(rD(ctx->opcode), t1); \ 176 if (set_fprf) { \ 177 gen_compute_fprf_float64(t1); \ 178 } \ 179 if (unlikely(Rc(ctx->opcode) != 0)) { \ 180 gen_set_cr1_from_fpscr(ctx); \ 181 } \ 182 tcg_temp_free_i64(t0); \ 183 tcg_temp_free_i64(t1); \ 184} 185 186/* fadd - fadds */ 187GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); 188/* fdiv - fdivs */ 189GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); 190/* fmul - fmuls */ 191GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); 192 193/* fre */ 194GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); 195 196/* fres */ 197GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); 198 199/* frsqrte */ 200GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); 201 202/* frsqrtes */ 203static void gen_frsqrtes(DisasContext *ctx) 204{ 205 TCGv_i64 t0; 206 TCGv_i64 t1; 207 if (unlikely(!ctx->fpu_enabled)) { 208 gen_exception(ctx, POWERPC_EXCP_FPU); 209 return; 210 } 211 t0 = tcg_temp_new_i64(); 212 t1 = tcg_temp_new_i64(); 213 gen_reset_fpstatus(); 214 get_fpr(t0, rB(ctx->opcode)); 215 gen_helper_frsqrtes(t1, cpu_env, t0); 216 set_fpr(rD(ctx->opcode), t1); 217 gen_compute_fprf_float64(t1); 218 if (unlikely(Rc(ctx->opcode) != 0)) { 219 gen_set_cr1_from_fpscr(ctx); 220 } 221 tcg_temp_free_i64(t0); 222 tcg_temp_free_i64(t1); 223} 224 225static bool trans_FSEL(DisasContext *ctx, arg_A *a) 226{ 227 TCGv_i64 t0, t1, t2; 228 229 REQUIRE_INSNS_FLAGS(ctx, FLOAT_FSEL); 230 REQUIRE_FPU(ctx); 231 232 t0 = tcg_temp_new_i64(); 233 t1 = tcg_temp_new_i64(); 234 t2 = tcg_temp_new_i64(); 235 236 get_fpr(t0, a->fra); 237 get_fpr(t1, a->frb); 238 get_fpr(t2, a->frc); 239 240 gen_helper_FSEL(t0, t0, t1, t2); 241 set_fpr(a->frt, t0); 242 if (a->rc) { 243 gen_set_cr1_from_fpscr(ctx); 244 } 245 246 tcg_temp_free_i64(t0); 247 tcg_temp_free_i64(t1); 248 tcg_temp_free_i64(t2); 249 250 return true; 251} 252 253/* fsub - fsubs */ 254GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); 255/* Optional: */ 256 257/* fsqrt */ 258static void gen_fsqrt(DisasContext *ctx) 259{ 260 TCGv_i64 t0; 261 TCGv_i64 t1; 262 if (unlikely(!ctx->fpu_enabled)) { 263 gen_exception(ctx, POWERPC_EXCP_FPU); 264 return; 265 } 266 t0 = tcg_temp_new_i64(); 267 t1 = tcg_temp_new_i64(); 268 gen_reset_fpstatus(); 269 get_fpr(t0, rB(ctx->opcode)); 270 gen_helper_fsqrt(t1, cpu_env, t0); 271 set_fpr(rD(ctx->opcode), t1); 272 gen_compute_fprf_float64(t1); 273 if (unlikely(Rc(ctx->opcode) != 0)) { 274 gen_set_cr1_from_fpscr(ctx); 275 } 276 tcg_temp_free_i64(t0); 277 tcg_temp_free_i64(t1); 278} 279 280static void gen_fsqrts(DisasContext *ctx) 281{ 282 TCGv_i64 t0; 283 TCGv_i64 t1; 284 if (unlikely(!ctx->fpu_enabled)) { 285 gen_exception(ctx, POWERPC_EXCP_FPU); 286 return; 287 } 288 t0 = tcg_temp_new_i64(); 289 t1 = tcg_temp_new_i64(); 290 gen_reset_fpstatus(); 291 get_fpr(t0, rB(ctx->opcode)); 292 gen_helper_fsqrts(t1, cpu_env, t0); 293 set_fpr(rD(ctx->opcode), t1); 294 gen_compute_fprf_float64(t1); 295 if (unlikely(Rc(ctx->opcode) != 0)) { 296 gen_set_cr1_from_fpscr(ctx); 297 } 298 tcg_temp_free_i64(t0); 299 tcg_temp_free_i64(t1); 300} 301 302/*** Floating-Point multiply-and-add ***/ 303/* fmadd - fmadds */ 304GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); 305/* fmsub - fmsubs */ 306GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); 307/* fnmadd - fnmadds */ 308GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); 309/* fnmsub - fnmsubs */ 310GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); 311 312/*** Floating-Point round & convert ***/ 313/* fctiw */ 314GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); 315/* fctiwu */ 316GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206); 317/* fctiwz */ 318GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); 319/* fctiwuz */ 320GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206); 321/* frsp */ 322GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); 323/* fcfid */ 324GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64); 325/* fcfids */ 326GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206); 327/* fcfidu */ 328GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206); 329/* fcfidus */ 330GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206); 331/* fctid */ 332GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64); 333/* fctidu */ 334GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206); 335/* fctidz */ 336GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64); 337/* fctidu */ 338GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206); 339 340/* frin */ 341GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); 342/* friz */ 343GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); 344/* frip */ 345GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); 346/* frim */ 347GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); 348 349static void gen_ftdiv(DisasContext *ctx) 350{ 351 TCGv_i64 t0; 352 TCGv_i64 t1; 353 if (unlikely(!ctx->fpu_enabled)) { 354 gen_exception(ctx, POWERPC_EXCP_FPU); 355 return; 356 } 357 t0 = tcg_temp_new_i64(); 358 t1 = tcg_temp_new_i64(); 359 get_fpr(t0, rA(ctx->opcode)); 360 get_fpr(t1, rB(ctx->opcode)); 361 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], t0, t1); 362 tcg_temp_free_i64(t0); 363 tcg_temp_free_i64(t1); 364} 365 366static void gen_ftsqrt(DisasContext *ctx) 367{ 368 TCGv_i64 t0; 369 if (unlikely(!ctx->fpu_enabled)) { 370 gen_exception(ctx, POWERPC_EXCP_FPU); 371 return; 372 } 373 t0 = tcg_temp_new_i64(); 374 get_fpr(t0, rB(ctx->opcode)); 375 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], t0); 376 tcg_temp_free_i64(t0); 377} 378 379 380 381/*** Floating-Point compare ***/ 382 383/* fcmpo */ 384static void gen_fcmpo(DisasContext *ctx) 385{ 386 TCGv_i32 crf; 387 TCGv_i64 t0; 388 TCGv_i64 t1; 389 if (unlikely(!ctx->fpu_enabled)) { 390 gen_exception(ctx, POWERPC_EXCP_FPU); 391 return; 392 } 393 t0 = tcg_temp_new_i64(); 394 t1 = tcg_temp_new_i64(); 395 gen_reset_fpstatus(); 396 crf = tcg_const_i32(crfD(ctx->opcode)); 397 get_fpr(t0, rA(ctx->opcode)); 398 get_fpr(t1, rB(ctx->opcode)); 399 gen_helper_fcmpo(cpu_env, t0, t1, crf); 400 tcg_temp_free_i32(crf); 401 gen_helper_float_check_status(cpu_env); 402 tcg_temp_free_i64(t0); 403 tcg_temp_free_i64(t1); 404} 405 406/* fcmpu */ 407static void gen_fcmpu(DisasContext *ctx) 408{ 409 TCGv_i32 crf; 410 TCGv_i64 t0; 411 TCGv_i64 t1; 412 if (unlikely(!ctx->fpu_enabled)) { 413 gen_exception(ctx, POWERPC_EXCP_FPU); 414 return; 415 } 416 t0 = tcg_temp_new_i64(); 417 t1 = tcg_temp_new_i64(); 418 gen_reset_fpstatus(); 419 crf = tcg_const_i32(crfD(ctx->opcode)); 420 get_fpr(t0, rA(ctx->opcode)); 421 get_fpr(t1, rB(ctx->opcode)); 422 gen_helper_fcmpu(cpu_env, t0, t1, crf); 423 tcg_temp_free_i32(crf); 424 gen_helper_float_check_status(cpu_env); 425 tcg_temp_free_i64(t0); 426 tcg_temp_free_i64(t1); 427} 428 429/*** Floating-point move ***/ 430/* fabs */ 431/* XXX: beware that fabs never checks for NaNs nor update FPSCR */ 432static void gen_fabs(DisasContext *ctx) 433{ 434 TCGv_i64 t0; 435 TCGv_i64 t1; 436 if (unlikely(!ctx->fpu_enabled)) { 437 gen_exception(ctx, POWERPC_EXCP_FPU); 438 return; 439 } 440 t0 = tcg_temp_new_i64(); 441 t1 = tcg_temp_new_i64(); 442 get_fpr(t0, rB(ctx->opcode)); 443 tcg_gen_andi_i64(t1, t0, ~(1ULL << 63)); 444 set_fpr(rD(ctx->opcode), t1); 445 if (unlikely(Rc(ctx->opcode))) { 446 gen_set_cr1_from_fpscr(ctx); 447 } 448 tcg_temp_free_i64(t0); 449 tcg_temp_free_i64(t1); 450} 451 452/* fmr - fmr. */ 453/* XXX: beware that fmr never checks for NaNs nor update FPSCR */ 454static void gen_fmr(DisasContext *ctx) 455{ 456 TCGv_i64 t0; 457 if (unlikely(!ctx->fpu_enabled)) { 458 gen_exception(ctx, POWERPC_EXCP_FPU); 459 return; 460 } 461 t0 = tcg_temp_new_i64(); 462 get_fpr(t0, rB(ctx->opcode)); 463 set_fpr(rD(ctx->opcode), t0); 464 if (unlikely(Rc(ctx->opcode))) { 465 gen_set_cr1_from_fpscr(ctx); 466 } 467 tcg_temp_free_i64(t0); 468} 469 470/* fnabs */ 471/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */ 472static void gen_fnabs(DisasContext *ctx) 473{ 474 TCGv_i64 t0; 475 TCGv_i64 t1; 476 if (unlikely(!ctx->fpu_enabled)) { 477 gen_exception(ctx, POWERPC_EXCP_FPU); 478 return; 479 } 480 t0 = tcg_temp_new_i64(); 481 t1 = tcg_temp_new_i64(); 482 get_fpr(t0, rB(ctx->opcode)); 483 tcg_gen_ori_i64(t1, t0, 1ULL << 63); 484 set_fpr(rD(ctx->opcode), t1); 485 if (unlikely(Rc(ctx->opcode))) { 486 gen_set_cr1_from_fpscr(ctx); 487 } 488 tcg_temp_free_i64(t0); 489 tcg_temp_free_i64(t1); 490} 491 492/* fneg */ 493/* XXX: beware that fneg never checks for NaNs nor update FPSCR */ 494static void gen_fneg(DisasContext *ctx) 495{ 496 TCGv_i64 t0; 497 TCGv_i64 t1; 498 if (unlikely(!ctx->fpu_enabled)) { 499 gen_exception(ctx, POWERPC_EXCP_FPU); 500 return; 501 } 502 t0 = tcg_temp_new_i64(); 503 t1 = tcg_temp_new_i64(); 504 get_fpr(t0, rB(ctx->opcode)); 505 tcg_gen_xori_i64(t1, t0, 1ULL << 63); 506 set_fpr(rD(ctx->opcode), t1); 507 if (unlikely(Rc(ctx->opcode))) { 508 gen_set_cr1_from_fpscr(ctx); 509 } 510 tcg_temp_free_i64(t0); 511 tcg_temp_free_i64(t1); 512} 513 514/* fcpsgn: PowerPC 2.05 specification */ 515/* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */ 516static void gen_fcpsgn(DisasContext *ctx) 517{ 518 TCGv_i64 t0; 519 TCGv_i64 t1; 520 TCGv_i64 t2; 521 if (unlikely(!ctx->fpu_enabled)) { 522 gen_exception(ctx, POWERPC_EXCP_FPU); 523 return; 524 } 525 t0 = tcg_temp_new_i64(); 526 t1 = tcg_temp_new_i64(); 527 t2 = tcg_temp_new_i64(); 528 get_fpr(t0, rA(ctx->opcode)); 529 get_fpr(t1, rB(ctx->opcode)); 530 tcg_gen_deposit_i64(t2, t0, t1, 0, 63); 531 set_fpr(rD(ctx->opcode), t2); 532 if (unlikely(Rc(ctx->opcode))) { 533 gen_set_cr1_from_fpscr(ctx); 534 } 535 tcg_temp_free_i64(t0); 536 tcg_temp_free_i64(t1); 537 tcg_temp_free_i64(t2); 538} 539 540static void gen_fmrgew(DisasContext *ctx) 541{ 542 TCGv_i64 b0; 543 TCGv_i64 t0; 544 TCGv_i64 t1; 545 if (unlikely(!ctx->fpu_enabled)) { 546 gen_exception(ctx, POWERPC_EXCP_FPU); 547 return; 548 } 549 b0 = tcg_temp_new_i64(); 550 t0 = tcg_temp_new_i64(); 551 t1 = tcg_temp_new_i64(); 552 get_fpr(t0, rB(ctx->opcode)); 553 tcg_gen_shri_i64(b0, t0, 32); 554 get_fpr(t0, rA(ctx->opcode)); 555 tcg_gen_deposit_i64(t1, t0, b0, 0, 32); 556 set_fpr(rD(ctx->opcode), t1); 557 tcg_temp_free_i64(b0); 558 tcg_temp_free_i64(t0); 559 tcg_temp_free_i64(t1); 560} 561 562static void gen_fmrgow(DisasContext *ctx) 563{ 564 TCGv_i64 t0; 565 TCGv_i64 t1; 566 TCGv_i64 t2; 567 if (unlikely(!ctx->fpu_enabled)) { 568 gen_exception(ctx, POWERPC_EXCP_FPU); 569 return; 570 } 571 t0 = tcg_temp_new_i64(); 572 t1 = tcg_temp_new_i64(); 573 t2 = tcg_temp_new_i64(); 574 get_fpr(t0, rB(ctx->opcode)); 575 get_fpr(t1, rA(ctx->opcode)); 576 tcg_gen_deposit_i64(t2, t0, t1, 32, 32); 577 set_fpr(rD(ctx->opcode), t2); 578 tcg_temp_free_i64(t0); 579 tcg_temp_free_i64(t1); 580 tcg_temp_free_i64(t2); 581} 582 583/*** Floating-Point status & ctrl register ***/ 584 585/* mcrfs */ 586static void gen_mcrfs(DisasContext *ctx) 587{ 588 TCGv tmp = tcg_temp_new(); 589 TCGv_i32 tmask; 590 TCGv_i64 tnew_fpscr = tcg_temp_new_i64(); 591 int bfa; 592 int nibble; 593 int shift; 594 595 if (unlikely(!ctx->fpu_enabled)) { 596 gen_exception(ctx, POWERPC_EXCP_FPU); 597 return; 598 } 599 bfa = crfS(ctx->opcode); 600 nibble = 7 - bfa; 601 shift = 4 * nibble; 602 tcg_gen_shri_tl(tmp, cpu_fpscr, shift); 603 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp); 604 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 605 0xf); 606 tcg_temp_free(tmp); 607 tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr); 608 /* Only the exception bits (including FX) should be cleared if read */ 609 tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, 610 ~((0xF << shift) & FP_EX_CLEAR_BITS)); 611 /* FEX and VX need to be updated, so don't set fpscr directly */ 612 tmask = tcg_const_i32(1 << nibble); 613 gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask); 614 tcg_temp_free_i32(tmask); 615 tcg_temp_free_i64(tnew_fpscr); 616} 617 618static TCGv_i64 place_from_fpscr(int rt, uint64_t mask) 619{ 620 TCGv_i64 fpscr = tcg_temp_new_i64(); 621 TCGv_i64 fpscr_masked = tcg_temp_new_i64(); 622 623 tcg_gen_extu_tl_i64(fpscr, cpu_fpscr); 624 tcg_gen_andi_i64(fpscr_masked, fpscr, mask); 625 set_fpr(rt, fpscr_masked); 626 627 tcg_temp_free_i64(fpscr_masked); 628 629 return fpscr; 630} 631 632static void store_fpscr_masked(TCGv_i64 fpscr, uint64_t clear_mask, 633 TCGv_i64 set_mask, uint32_t store_mask) 634{ 635 TCGv_i64 fpscr_masked = tcg_temp_new_i64(); 636 TCGv_i32 st_mask = tcg_constant_i32(store_mask); 637 638 tcg_gen_andi_i64(fpscr_masked, fpscr, ~clear_mask); 639 tcg_gen_or_i64(fpscr_masked, fpscr_masked, set_mask); 640 gen_helper_store_fpscr(cpu_env, fpscr_masked, st_mask); 641 642 tcg_temp_free_i64(fpscr_masked); 643} 644 645static bool trans_MFFS(DisasContext *ctx, arg_X_t_rc *a) 646{ 647 TCGv_i64 fpscr; 648 649 REQUIRE_FPU(ctx); 650 651 gen_reset_fpstatus(); 652 fpscr = place_from_fpscr(a->rt, UINT64_MAX); 653 if (a->rc) { 654 gen_set_cr1_from_fpscr(ctx); 655 } 656 657 tcg_temp_free_i64(fpscr); 658 659 return true; 660} 661 662static bool trans_MFFSCE(DisasContext *ctx, arg_X_t *a) 663{ 664 TCGv_i64 fpscr; 665 666 REQUIRE_INSNS_FLAGS2(ctx, ISA300); 667 REQUIRE_FPU(ctx); 668 669 gen_reset_fpstatus(); 670 fpscr = place_from_fpscr(a->rt, UINT64_MAX); 671 store_fpscr_masked(fpscr, FP_ENABLES, tcg_constant_i64(0), 0x0003); 672 673 tcg_temp_free_i64(fpscr); 674 675 return true; 676} 677 678static bool trans_MFFSCRN(DisasContext *ctx, arg_X_tb *a) 679{ 680 TCGv_i64 t1, fpscr; 681 682 REQUIRE_INSNS_FLAGS2(ctx, ISA300); 683 REQUIRE_FPU(ctx); 684 685 t1 = tcg_temp_new_i64(); 686 get_fpr(t1, a->rb); 687 tcg_gen_andi_i64(t1, t1, FP_RN); 688 689 gen_reset_fpstatus(); 690 fpscr = place_from_fpscr(a->rt, FP_DRN | FP_ENABLES | FP_NI | FP_RN); 691 store_fpscr_masked(fpscr, FP_RN, t1, 0x0001); 692 693 tcg_temp_free_i64(t1); 694 tcg_temp_free_i64(fpscr); 695 696 return true; 697} 698 699static bool trans_MFFSCRNI(DisasContext *ctx, arg_X_imm2 *a) 700{ 701 TCGv_i64 t1, fpscr; 702 703 REQUIRE_INSNS_FLAGS2(ctx, ISA300); 704 REQUIRE_FPU(ctx); 705 706 t1 = tcg_temp_new_i64(); 707 tcg_gen_movi_i64(t1, a->imm); 708 709 gen_reset_fpstatus(); 710 fpscr = place_from_fpscr(a->rt, FP_DRN | FP_ENABLES | FP_NI | FP_RN); 711 store_fpscr_masked(fpscr, FP_RN, t1, 0x0001); 712 713 tcg_temp_free_i64(t1); 714 tcg_temp_free_i64(fpscr); 715 716 return true; 717} 718 719static bool trans_MFFSL(DisasContext *ctx, arg_X_t *a) 720{ 721 TCGv_i64 fpscr; 722 723 REQUIRE_INSNS_FLAGS2(ctx, ISA300); 724 REQUIRE_FPU(ctx); 725 726 gen_reset_fpstatus(); 727 fpscr = place_from_fpscr(a->rt, 728 FP_DRN | FP_STATUS | FP_ENABLES | FP_NI | FP_RN); 729 730 tcg_temp_free_i64(fpscr); 731 732 return true; 733} 734 735/* mtfsb0 */ 736static void gen_mtfsb0(DisasContext *ctx) 737{ 738 uint8_t crb; 739 740 if (unlikely(!ctx->fpu_enabled)) { 741 gen_exception(ctx, POWERPC_EXCP_FPU); 742 return; 743 } 744 crb = 31 - crbD(ctx->opcode); 745 gen_reset_fpstatus(); 746 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) { 747 TCGv_i32 t0; 748 t0 = tcg_const_i32(crb); 749 gen_helper_fpscr_clrbit(cpu_env, t0); 750 tcg_temp_free_i32(t0); 751 } 752 if (unlikely(Rc(ctx->opcode) != 0)) { 753 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); 754 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); 755 } 756} 757 758/* mtfsb1 */ 759static void gen_mtfsb1(DisasContext *ctx) 760{ 761 uint8_t crb; 762 763 if (unlikely(!ctx->fpu_enabled)) { 764 gen_exception(ctx, POWERPC_EXCP_FPU); 765 return; 766 } 767 crb = 31 - crbD(ctx->opcode); 768 /* XXX: we pretend we can only do IEEE floating-point computations */ 769 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { 770 TCGv_i32 t0; 771 t0 = tcg_const_i32(crb); 772 gen_helper_fpscr_setbit(cpu_env, t0); 773 tcg_temp_free_i32(t0); 774 } 775 if (unlikely(Rc(ctx->opcode) != 0)) { 776 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); 777 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); 778 } 779 /* We can raise a deferred exception */ 780 gen_helper_fpscr_check_status(cpu_env); 781} 782 783/* mtfsf */ 784static void gen_mtfsf(DisasContext *ctx) 785{ 786 TCGv_i32 t0; 787 TCGv_i64 t1; 788 int flm, l, w; 789 790 if (unlikely(!ctx->fpu_enabled)) { 791 gen_exception(ctx, POWERPC_EXCP_FPU); 792 return; 793 } 794 flm = FPFLM(ctx->opcode); 795 l = FPL(ctx->opcode); 796 w = FPW(ctx->opcode); 797 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) { 798 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 799 return; 800 } 801 if (l) { 802 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff); 803 } else { 804 t0 = tcg_const_i32(flm << (w * 8)); 805 } 806 t1 = tcg_temp_new_i64(); 807 get_fpr(t1, rB(ctx->opcode)); 808 gen_helper_store_fpscr(cpu_env, t1, t0); 809 tcg_temp_free_i32(t0); 810 if (unlikely(Rc(ctx->opcode) != 0)) { 811 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); 812 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); 813 } 814 /* We can raise a deferred exception */ 815 gen_helper_fpscr_check_status(cpu_env); 816 tcg_temp_free_i64(t1); 817} 818 819/* mtfsfi */ 820static void gen_mtfsfi(DisasContext *ctx) 821{ 822 int bf, sh, w; 823 TCGv_i64 t0; 824 TCGv_i32 t1; 825 826 if (unlikely(!ctx->fpu_enabled)) { 827 gen_exception(ctx, POWERPC_EXCP_FPU); 828 return; 829 } 830 w = FPW(ctx->opcode); 831 bf = FPBF(ctx->opcode); 832 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) { 833 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 834 return; 835 } 836 sh = (8 * w) + 7 - bf; 837 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh)); 838 t1 = tcg_const_i32(1 << sh); 839 gen_helper_store_fpscr(cpu_env, t0, t1); 840 tcg_temp_free_i64(t0); 841 tcg_temp_free_i32(t1); 842 if (unlikely(Rc(ctx->opcode) != 0)) { 843 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); 844 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); 845 } 846 /* We can raise a deferred exception */ 847 gen_helper_fpscr_check_status(cpu_env); 848} 849 850static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr) 851{ 852 TCGv_i32 tmp = tcg_temp_new_i32(); 853 tcg_gen_qemu_ld_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL)); 854 gen_helper_todouble(dest, tmp); 855 tcg_temp_free_i32(tmp); 856} 857 858/* lfdepx (external PID lfdx) */ 859static void gen_lfdepx(DisasContext *ctx) 860{ 861 TCGv EA; 862 TCGv_i64 t0; 863 CHK_SV; 864 if (unlikely(!ctx->fpu_enabled)) { 865 gen_exception(ctx, POWERPC_EXCP_FPU); 866 return; 867 } 868 gen_set_access_type(ctx, ACCESS_FLOAT); 869 EA = tcg_temp_new(); 870 t0 = tcg_temp_new_i64(); 871 gen_addr_reg_index(ctx, EA); 872 tcg_gen_qemu_ld_i64(t0, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UQ)); 873 set_fpr(rD(ctx->opcode), t0); 874 tcg_temp_free(EA); 875 tcg_temp_free_i64(t0); 876} 877 878/* lfdp */ 879static void gen_lfdp(DisasContext *ctx) 880{ 881 TCGv EA; 882 TCGv_i64 t0; 883 if (unlikely(!ctx->fpu_enabled)) { 884 gen_exception(ctx, POWERPC_EXCP_FPU); 885 return; 886 } 887 gen_set_access_type(ctx, ACCESS_FLOAT); 888 EA = tcg_temp_new(); 889 gen_addr_imm_index(ctx, EA, 0); 890 t0 = tcg_temp_new_i64(); 891 /* 892 * We only need to swap high and low halves. gen_qemu_ld64_i64 893 * does necessary 64-bit byteswap already. 894 */ 895 if (unlikely(ctx->le_mode)) { 896 gen_qemu_ld64_i64(ctx, t0, EA); 897 set_fpr(rD(ctx->opcode) + 1, t0); 898 tcg_gen_addi_tl(EA, EA, 8); 899 gen_qemu_ld64_i64(ctx, t0, EA); 900 set_fpr(rD(ctx->opcode), t0); 901 } else { 902 gen_qemu_ld64_i64(ctx, t0, EA); 903 set_fpr(rD(ctx->opcode), t0); 904 tcg_gen_addi_tl(EA, EA, 8); 905 gen_qemu_ld64_i64(ctx, t0, EA); 906 set_fpr(rD(ctx->opcode) + 1, t0); 907 } 908 tcg_temp_free(EA); 909 tcg_temp_free_i64(t0); 910} 911 912/* lfdpx */ 913static void gen_lfdpx(DisasContext *ctx) 914{ 915 TCGv EA; 916 TCGv_i64 t0; 917 if (unlikely(!ctx->fpu_enabled)) { 918 gen_exception(ctx, POWERPC_EXCP_FPU); 919 return; 920 } 921 gen_set_access_type(ctx, ACCESS_FLOAT); 922 EA = tcg_temp_new(); 923 gen_addr_reg_index(ctx, EA); 924 t0 = tcg_temp_new_i64(); 925 /* 926 * We only need to swap high and low halves. gen_qemu_ld64_i64 927 * does necessary 64-bit byteswap already. 928 */ 929 if (unlikely(ctx->le_mode)) { 930 gen_qemu_ld64_i64(ctx, t0, EA); 931 set_fpr(rD(ctx->opcode) + 1, t0); 932 tcg_gen_addi_tl(EA, EA, 8); 933 gen_qemu_ld64_i64(ctx, t0, EA); 934 set_fpr(rD(ctx->opcode), t0); 935 } else { 936 gen_qemu_ld64_i64(ctx, t0, EA); 937 set_fpr(rD(ctx->opcode), t0); 938 tcg_gen_addi_tl(EA, EA, 8); 939 gen_qemu_ld64_i64(ctx, t0, EA); 940 set_fpr(rD(ctx->opcode) + 1, t0); 941 } 942 tcg_temp_free(EA); 943 tcg_temp_free_i64(t0); 944} 945 946/* lfiwax */ 947static void gen_lfiwax(DisasContext *ctx) 948{ 949 TCGv EA; 950 TCGv t0; 951 TCGv_i64 t1; 952 if (unlikely(!ctx->fpu_enabled)) { 953 gen_exception(ctx, POWERPC_EXCP_FPU); 954 return; 955 } 956 gen_set_access_type(ctx, ACCESS_FLOAT); 957 EA = tcg_temp_new(); 958 t0 = tcg_temp_new(); 959 t1 = tcg_temp_new_i64(); 960 gen_addr_reg_index(ctx, EA); 961 gen_qemu_ld32s(ctx, t0, EA); 962 tcg_gen_ext_tl_i64(t1, t0); 963 set_fpr(rD(ctx->opcode), t1); 964 tcg_temp_free(EA); 965 tcg_temp_free(t0); 966 tcg_temp_free_i64(t1); 967} 968 969/* lfiwzx */ 970static void gen_lfiwzx(DisasContext *ctx) 971{ 972 TCGv EA; 973 TCGv_i64 t0; 974 if (unlikely(!ctx->fpu_enabled)) { 975 gen_exception(ctx, POWERPC_EXCP_FPU); 976 return; 977 } 978 gen_set_access_type(ctx, ACCESS_FLOAT); 979 EA = tcg_temp_new(); 980 t0 = tcg_temp_new_i64(); 981 gen_addr_reg_index(ctx, EA); 982 gen_qemu_ld32u_i64(ctx, t0, EA); 983 set_fpr(rD(ctx->opcode), t0); 984 tcg_temp_free(EA); 985 tcg_temp_free_i64(t0); 986} 987 988#define GEN_STXF(name, stop, opc2, opc3, type) \ 989static void glue(gen_, name##x)(DisasContext *ctx) \ 990{ \ 991 TCGv EA; \ 992 TCGv_i64 t0; \ 993 if (unlikely(!ctx->fpu_enabled)) { \ 994 gen_exception(ctx, POWERPC_EXCP_FPU); \ 995 return; \ 996 } \ 997 gen_set_access_type(ctx, ACCESS_FLOAT); \ 998 EA = tcg_temp_new(); \ 999 t0 = tcg_temp_new_i64(); \ 1000 gen_addr_reg_index(ctx, EA); \ 1001 get_fpr(t0, rS(ctx->opcode)); \ 1002 gen_qemu_##stop(ctx, t0, EA); \ 1003 tcg_temp_free(EA); \ 1004 tcg_temp_free_i64(t0); \ 1005} 1006 1007static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr) 1008{ 1009 TCGv_i32 tmp = tcg_temp_new_i32(); 1010 gen_helper_tosingle(tmp, src); 1011 tcg_gen_qemu_st_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL)); 1012 tcg_temp_free_i32(tmp); 1013} 1014 1015/* stfdepx (external PID lfdx) */ 1016static void gen_stfdepx(DisasContext *ctx) 1017{ 1018 TCGv EA; 1019 TCGv_i64 t0; 1020 CHK_SV; 1021 if (unlikely(!ctx->fpu_enabled)) { 1022 gen_exception(ctx, POWERPC_EXCP_FPU); 1023 return; 1024 } 1025 gen_set_access_type(ctx, ACCESS_FLOAT); 1026 EA = tcg_temp_new(); 1027 t0 = tcg_temp_new_i64(); 1028 gen_addr_reg_index(ctx, EA); 1029 get_fpr(t0, rD(ctx->opcode)); 1030 tcg_gen_qemu_st_i64(t0, EA, PPC_TLB_EPID_STORE, DEF_MEMOP(MO_UQ)); 1031 tcg_temp_free(EA); 1032 tcg_temp_free_i64(t0); 1033} 1034 1035/* stfdp */ 1036static void gen_stfdp(DisasContext *ctx) 1037{ 1038 TCGv EA; 1039 TCGv_i64 t0; 1040 if (unlikely(!ctx->fpu_enabled)) { 1041 gen_exception(ctx, POWERPC_EXCP_FPU); 1042 return; 1043 } 1044 gen_set_access_type(ctx, ACCESS_FLOAT); 1045 EA = tcg_temp_new(); 1046 t0 = tcg_temp_new_i64(); 1047 gen_addr_imm_index(ctx, EA, 0); 1048 /* 1049 * We only need to swap high and low halves. gen_qemu_st64_i64 1050 * does necessary 64-bit byteswap already. 1051 */ 1052 if (unlikely(ctx->le_mode)) { 1053 get_fpr(t0, rD(ctx->opcode) + 1); 1054 gen_qemu_st64_i64(ctx, t0, EA); 1055 tcg_gen_addi_tl(EA, EA, 8); 1056 get_fpr(t0, rD(ctx->opcode)); 1057 gen_qemu_st64_i64(ctx, t0, EA); 1058 } else { 1059 get_fpr(t0, rD(ctx->opcode)); 1060 gen_qemu_st64_i64(ctx, t0, EA); 1061 tcg_gen_addi_tl(EA, EA, 8); 1062 get_fpr(t0, rD(ctx->opcode) + 1); 1063 gen_qemu_st64_i64(ctx, t0, EA); 1064 } 1065 tcg_temp_free(EA); 1066 tcg_temp_free_i64(t0); 1067} 1068 1069/* stfdpx */ 1070static void gen_stfdpx(DisasContext *ctx) 1071{ 1072 TCGv EA; 1073 TCGv_i64 t0; 1074 if (unlikely(!ctx->fpu_enabled)) { 1075 gen_exception(ctx, POWERPC_EXCP_FPU); 1076 return; 1077 } 1078 gen_set_access_type(ctx, ACCESS_FLOAT); 1079 EA = tcg_temp_new(); 1080 t0 = tcg_temp_new_i64(); 1081 gen_addr_reg_index(ctx, EA); 1082 /* 1083 * We only need to swap high and low halves. gen_qemu_st64_i64 1084 * does necessary 64-bit byteswap already. 1085 */ 1086 if (unlikely(ctx->le_mode)) { 1087 get_fpr(t0, rD(ctx->opcode) + 1); 1088 gen_qemu_st64_i64(ctx, t0, EA); 1089 tcg_gen_addi_tl(EA, EA, 8); 1090 get_fpr(t0, rD(ctx->opcode)); 1091 gen_qemu_st64_i64(ctx, t0, EA); 1092 } else { 1093 get_fpr(t0, rD(ctx->opcode)); 1094 gen_qemu_st64_i64(ctx, t0, EA); 1095 tcg_gen_addi_tl(EA, EA, 8); 1096 get_fpr(t0, rD(ctx->opcode) + 1); 1097 gen_qemu_st64_i64(ctx, t0, EA); 1098 } 1099 tcg_temp_free(EA); 1100 tcg_temp_free_i64(t0); 1101} 1102 1103/* Optional: */ 1104static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) 1105{ 1106 TCGv t0 = tcg_temp_new(); 1107 tcg_gen_trunc_i64_tl(t0, arg1), 1108 gen_qemu_st32(ctx, t0, arg2); 1109 tcg_temp_free(t0); 1110} 1111/* stfiwx */ 1112GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); 1113 1114/* Floating-point Load/Store Instructions */ 1115static bool do_lsfpsd(DisasContext *ctx, int rt, int ra, TCGv displ, 1116 bool update, bool store, bool single) 1117{ 1118 TCGv ea; 1119 TCGv_i64 t0; 1120 REQUIRE_INSNS_FLAGS(ctx, FLOAT); 1121 REQUIRE_FPU(ctx); 1122 if (update && ra == 0) { 1123 gen_invalid(ctx); 1124 return true; 1125 } 1126 gen_set_access_type(ctx, ACCESS_FLOAT); 1127 t0 = tcg_temp_new_i64(); 1128 ea = do_ea_calc(ctx, ra, displ); 1129 if (store) { 1130 get_fpr(t0, rt); 1131 if (single) { 1132 gen_qemu_st32fs(ctx, t0, ea); 1133 } else { 1134 gen_qemu_st64_i64(ctx, t0, ea); 1135 } 1136 } else { 1137 if (single) { 1138 gen_qemu_ld32fs(ctx, t0, ea); 1139 } else { 1140 gen_qemu_ld64_i64(ctx, t0, ea); 1141 } 1142 set_fpr(rt, t0); 1143 } 1144 if (update) { 1145 tcg_gen_mov_tl(cpu_gpr[ra], ea); 1146 } 1147 tcg_temp_free_i64(t0); 1148 tcg_temp_free(ea); 1149 return true; 1150} 1151 1152static bool do_lsfp_D(DisasContext *ctx, arg_D *a, bool update, bool store, 1153 bool single) 1154{ 1155 return do_lsfpsd(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store, 1156 single); 1157} 1158 1159static bool do_lsfp_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool update, 1160 bool store, bool single) 1161{ 1162 arg_D d; 1163 if (!resolve_PLS_D(ctx, &d, a)) { 1164 return true; 1165 } 1166 return do_lsfp_D(ctx, &d, update, store, single); 1167} 1168 1169static bool do_lsfp_X(DisasContext *ctx, arg_X *a, bool update, 1170 bool store, bool single) 1171{ 1172 return do_lsfpsd(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, single); 1173} 1174 1175TRANS(LFS, do_lsfp_D, false, false, true) 1176TRANS(LFSU, do_lsfp_D, true, false, true) 1177TRANS(LFSX, do_lsfp_X, false, false, true) 1178TRANS(LFSUX, do_lsfp_X, true, false, true) 1179TRANS(PLFS, do_lsfp_PLS_D, false, false, true) 1180 1181TRANS(LFD, do_lsfp_D, false, false, false) 1182TRANS(LFDU, do_lsfp_D, true, false, false) 1183TRANS(LFDX, do_lsfp_X, false, false, false) 1184TRANS(LFDUX, do_lsfp_X, true, false, false) 1185TRANS(PLFD, do_lsfp_PLS_D, false, false, false) 1186 1187TRANS(STFS, do_lsfp_D, false, true, true) 1188TRANS(STFSU, do_lsfp_D, true, true, true) 1189TRANS(STFSX, do_lsfp_X, false, true, true) 1190TRANS(STFSUX, do_lsfp_X, true, true, true) 1191TRANS(PSTFS, do_lsfp_PLS_D, false, true, true) 1192 1193TRANS(STFD, do_lsfp_D, false, true, false) 1194TRANS(STFDU, do_lsfp_D, true, true, false) 1195TRANS(STFDX, do_lsfp_X, false, true, false) 1196TRANS(STFDUX, do_lsfp_X, true, true, false) 1197TRANS(PSTFD, do_lsfp_PLS_D, false, true, false) 1198 1199#undef _GEN_FLOAT_ACB 1200#undef GEN_FLOAT_ACB 1201#undef _GEN_FLOAT_AB 1202#undef GEN_FLOAT_AB 1203#undef _GEN_FLOAT_AC 1204#undef GEN_FLOAT_AC 1205#undef GEN_FLOAT_B 1206#undef GEN_FLOAT_BS 1207 1208#undef GEN_LDF 1209#undef GEN_LDUF 1210#undef GEN_LDUXF 1211#undef GEN_LDXF 1212#undef GEN_LDFS 1213 1214#undef GEN_STF 1215#undef GEN_STUF 1216#undef GEN_STUXF 1217#undef GEN_STXF 1218#undef GEN_STFS 1219