1 #include "qemu/osdep.h" 2 #include "qemu-common.h" 3 #include "cpu.h" 4 #include "exec/exec-all.h" 5 #include "hw/hw.h" 6 #include "hw/boards.h" 7 #include "sysemu/kvm.h" 8 #include "helper_regs.h" 9 #include "mmu-hash64.h" 10 #include "migration/cpu.h" 11 12 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) 13 { 14 PowerPCCPU *cpu = opaque; 15 CPUPPCState *env = &cpu->env; 16 unsigned int i, j; 17 target_ulong sdr1; 18 uint32_t fpscr; 19 target_ulong xer; 20 21 for (i = 0; i < 32; i++) 22 qemu_get_betls(f, &env->gpr[i]); 23 #if !defined(TARGET_PPC64) 24 for (i = 0; i < 32; i++) 25 qemu_get_betls(f, &env->gprh[i]); 26 #endif 27 qemu_get_betls(f, &env->lr); 28 qemu_get_betls(f, &env->ctr); 29 for (i = 0; i < 8; i++) 30 qemu_get_be32s(f, &env->crf[i]); 31 qemu_get_betls(f, &xer); 32 cpu_write_xer(env, xer); 33 qemu_get_betls(f, &env->reserve_addr); 34 qemu_get_betls(f, &env->msr); 35 for (i = 0; i < 4; i++) 36 qemu_get_betls(f, &env->tgpr[i]); 37 for (i = 0; i < 32; i++) { 38 union { 39 float64 d; 40 uint64_t l; 41 } u; 42 u.l = qemu_get_be64(f); 43 env->fpr[i] = u.d; 44 } 45 qemu_get_be32s(f, &fpscr); 46 env->fpscr = fpscr; 47 qemu_get_sbe32s(f, &env->access_type); 48 #if defined(TARGET_PPC64) 49 qemu_get_betls(f, &env->spr[SPR_ASR]); 50 qemu_get_sbe32s(f, &env->slb_nr); 51 #endif 52 qemu_get_betls(f, &sdr1); 53 for (i = 0; i < 32; i++) 54 qemu_get_betls(f, &env->sr[i]); 55 for (i = 0; i < 2; i++) 56 for (j = 0; j < 8; j++) 57 qemu_get_betls(f, &env->DBAT[i][j]); 58 for (i = 0; i < 2; i++) 59 for (j = 0; j < 8; j++) 60 qemu_get_betls(f, &env->IBAT[i][j]); 61 qemu_get_sbe32s(f, &env->nb_tlb); 62 qemu_get_sbe32s(f, &env->tlb_per_way); 63 qemu_get_sbe32s(f, &env->nb_ways); 64 qemu_get_sbe32s(f, &env->last_way); 65 qemu_get_sbe32s(f, &env->id_tlbs); 66 qemu_get_sbe32s(f, &env->nb_pids); 67 if (env->tlb.tlb6) { 68 // XXX assumes 6xx 69 for (i = 0; i < env->nb_tlb; i++) { 70 qemu_get_betls(f, &env->tlb.tlb6[i].pte0); 71 qemu_get_betls(f, &env->tlb.tlb6[i].pte1); 72 qemu_get_betls(f, &env->tlb.tlb6[i].EPN); 73 } 74 } 75 for (i = 0; i < 4; i++) 76 qemu_get_betls(f, &env->pb[i]); 77 for (i = 0; i < 1024; i++) 78 qemu_get_betls(f, &env->spr[i]); 79 if (!cpu->vhyp) { 80 ppc_store_sdr1(env, sdr1); 81 } 82 qemu_get_be32s(f, &env->vscr); 83 qemu_get_be64s(f, &env->spe_acc); 84 qemu_get_be32s(f, &env->spe_fscr); 85 qemu_get_betls(f, &env->msr_mask); 86 qemu_get_be32s(f, &env->flags); 87 qemu_get_sbe32s(f, &env->error_code); 88 qemu_get_be32s(f, &env->pending_interrupts); 89 qemu_get_be32s(f, &env->irq_input_state); 90 for (i = 0; i < POWERPC_EXCP_NB; i++) 91 qemu_get_betls(f, &env->excp_vectors[i]); 92 qemu_get_betls(f, &env->excp_prefix); 93 qemu_get_betls(f, &env->ivor_mask); 94 qemu_get_betls(f, &env->ivpr_mask); 95 qemu_get_betls(f, &env->hreset_vector); 96 qemu_get_betls(f, &env->nip); 97 qemu_get_betls(f, &env->hflags); 98 qemu_get_betls(f, &env->hflags_nmsr); 99 qemu_get_sbe32(f); /* Discard unused mmu_idx */ 100 qemu_get_sbe32(f); /* Discard unused power_mode */ 101 102 /* Recompute mmu indices */ 103 hreg_compute_mem_idx(env); 104 105 return 0; 106 } 107 108 static int get_avr(QEMUFile *f, void *pv, size_t size, VMStateField *field) 109 { 110 ppc_avr_t *v = pv; 111 112 v->u64[0] = qemu_get_be64(f); 113 v->u64[1] = qemu_get_be64(f); 114 115 return 0; 116 } 117 118 static int put_avr(QEMUFile *f, void *pv, size_t size, VMStateField *field, 119 QJSON *vmdesc) 120 { 121 ppc_avr_t *v = pv; 122 123 qemu_put_be64(f, v->u64[0]); 124 qemu_put_be64(f, v->u64[1]); 125 return 0; 126 } 127 128 static const VMStateInfo vmstate_info_avr = { 129 .name = "avr", 130 .get = get_avr, 131 .put = put_avr, 132 }; 133 134 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \ 135 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t) 136 137 #define VMSTATE_AVR_ARRAY(_f, _s, _n) \ 138 VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0) 139 140 static bool cpu_pre_2_8_migration(void *opaque, int version_id) 141 { 142 PowerPCCPU *cpu = opaque; 143 144 return cpu->pre_2_8_migration; 145 } 146 147 static void cpu_pre_save(void *opaque) 148 { 149 PowerPCCPU *cpu = opaque; 150 CPUPPCState *env = &cpu->env; 151 int i; 152 uint64_t insns_compat_mask = 153 PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB 154 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES 155 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES 156 | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT 157 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ 158 | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC 159 | PPC_64B | PPC_64BX | PPC_ALTIVEC 160 | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; 161 uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX 162 | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 163 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 164 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 165 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 166 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM; 167 168 env->spr[SPR_LR] = env->lr; 169 env->spr[SPR_CTR] = env->ctr; 170 env->spr[SPR_XER] = cpu_read_xer(env); 171 #if defined(TARGET_PPC64) 172 env->spr[SPR_CFAR] = env->cfar; 173 #endif 174 env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr; 175 176 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 177 env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i]; 178 env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i]; 179 env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i]; 180 env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i]; 181 } 182 for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { 183 env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4]; 184 env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4]; 185 env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4]; 186 env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4]; 187 } 188 189 /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */ 190 if (cpu->pre_2_8_migration) { 191 cpu->mig_msr_mask = env->msr_mask; 192 cpu->mig_insns_flags = env->insns_flags & insns_compat_mask; 193 cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2; 194 cpu->mig_nb_BATs = env->nb_BATs; 195 } 196 } 197 198 static int cpu_post_load(void *opaque, int version_id) 199 { 200 PowerPCCPU *cpu = opaque; 201 CPUPPCState *env = &cpu->env; 202 int i; 203 target_ulong msr; 204 205 /* 206 * We always ignore the source PVR. The user or management 207 * software has to take care of running QEMU in a compatible mode. 208 */ 209 env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value; 210 env->lr = env->spr[SPR_LR]; 211 env->ctr = env->spr[SPR_CTR]; 212 cpu_write_xer(env, env->spr[SPR_XER]); 213 #if defined(TARGET_PPC64) 214 env->cfar = env->spr[SPR_CFAR]; 215 #endif 216 env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR]; 217 218 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 219 env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i]; 220 env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1]; 221 env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i]; 222 env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1]; 223 } 224 for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { 225 env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i]; 226 env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1]; 227 env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i]; 228 env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1]; 229 } 230 231 if (!cpu->vhyp) { 232 ppc_store_sdr1(env, env->spr[SPR_SDR1]); 233 } 234 235 /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */ 236 msr = env->msr; 237 env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB); 238 ppc_store_msr(env, msr); 239 240 hreg_compute_mem_idx(env); 241 242 return 0; 243 } 244 245 static bool fpu_needed(void *opaque) 246 { 247 PowerPCCPU *cpu = opaque; 248 249 return (cpu->env.insns_flags & PPC_FLOAT); 250 } 251 252 static const VMStateDescription vmstate_fpu = { 253 .name = "cpu/fpu", 254 .version_id = 1, 255 .minimum_version_id = 1, 256 .needed = fpu_needed, 257 .fields = (VMStateField[]) { 258 VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32), 259 VMSTATE_UINTTL(env.fpscr, PowerPCCPU), 260 VMSTATE_END_OF_LIST() 261 }, 262 }; 263 264 static bool altivec_needed(void *opaque) 265 { 266 PowerPCCPU *cpu = opaque; 267 268 return (cpu->env.insns_flags & PPC_ALTIVEC); 269 } 270 271 static const VMStateDescription vmstate_altivec = { 272 .name = "cpu/altivec", 273 .version_id = 1, 274 .minimum_version_id = 1, 275 .needed = altivec_needed, 276 .fields = (VMStateField[]) { 277 VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32), 278 VMSTATE_UINT32(env.vscr, PowerPCCPU), 279 VMSTATE_END_OF_LIST() 280 }, 281 }; 282 283 static bool vsx_needed(void *opaque) 284 { 285 PowerPCCPU *cpu = opaque; 286 287 return (cpu->env.insns_flags2 & PPC2_VSX); 288 } 289 290 static const VMStateDescription vmstate_vsx = { 291 .name = "cpu/vsx", 292 .version_id = 1, 293 .minimum_version_id = 1, 294 .needed = vsx_needed, 295 .fields = (VMStateField[]) { 296 VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32), 297 VMSTATE_END_OF_LIST() 298 }, 299 }; 300 301 #ifdef TARGET_PPC64 302 /* Transactional memory state */ 303 static bool tm_needed(void *opaque) 304 { 305 PowerPCCPU *cpu = opaque; 306 CPUPPCState *env = &cpu->env; 307 return msr_ts; 308 } 309 310 static const VMStateDescription vmstate_tm = { 311 .name = "cpu/tm", 312 .version_id = 1, 313 .minimum_version_id = 1, 314 .minimum_version_id_old = 1, 315 .needed = tm_needed, 316 .fields = (VMStateField []) { 317 VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32), 318 VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64), 319 VMSTATE_UINT64(env.tm_cr, PowerPCCPU), 320 VMSTATE_UINT64(env.tm_lr, PowerPCCPU), 321 VMSTATE_UINT64(env.tm_ctr, PowerPCCPU), 322 VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU), 323 VMSTATE_UINT64(env.tm_amr, PowerPCCPU), 324 VMSTATE_UINT64(env.tm_ppr, PowerPCCPU), 325 VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU), 326 VMSTATE_UINT32(env.tm_vscr, PowerPCCPU), 327 VMSTATE_UINT64(env.tm_dscr, PowerPCCPU), 328 VMSTATE_UINT64(env.tm_tar, PowerPCCPU), 329 VMSTATE_END_OF_LIST() 330 }, 331 }; 332 #endif 333 334 static bool sr_needed(void *opaque) 335 { 336 #ifdef TARGET_PPC64 337 PowerPCCPU *cpu = opaque; 338 339 return !(cpu->env.mmu_model & POWERPC_MMU_64); 340 #else 341 return true; 342 #endif 343 } 344 345 static const VMStateDescription vmstate_sr = { 346 .name = "cpu/sr", 347 .version_id = 1, 348 .minimum_version_id = 1, 349 .needed = sr_needed, 350 .fields = (VMStateField[]) { 351 VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32), 352 VMSTATE_END_OF_LIST() 353 }, 354 }; 355 356 #ifdef TARGET_PPC64 357 static int get_slbe(QEMUFile *f, void *pv, size_t size, VMStateField *field) 358 { 359 ppc_slb_t *v = pv; 360 361 v->esid = qemu_get_be64(f); 362 v->vsid = qemu_get_be64(f); 363 364 return 0; 365 } 366 367 static int put_slbe(QEMUFile *f, void *pv, size_t size, VMStateField *field, 368 QJSON *vmdesc) 369 { 370 ppc_slb_t *v = pv; 371 372 qemu_put_be64(f, v->esid); 373 qemu_put_be64(f, v->vsid); 374 return 0; 375 } 376 377 static const VMStateInfo vmstate_info_slbe = { 378 .name = "slbe", 379 .get = get_slbe, 380 .put = put_slbe, 381 }; 382 383 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \ 384 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t) 385 386 #define VMSTATE_SLB_ARRAY(_f, _s, _n) \ 387 VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0) 388 389 static bool slb_needed(void *opaque) 390 { 391 PowerPCCPU *cpu = opaque; 392 393 /* We don't support any of the old segment table based 64-bit CPUs */ 394 return (cpu->env.mmu_model & POWERPC_MMU_64); 395 } 396 397 static int slb_post_load(void *opaque, int version_id) 398 { 399 PowerPCCPU *cpu = opaque; 400 CPUPPCState *env = &cpu->env; 401 int i; 402 403 /* We've pulled in the raw esid and vsid values from the migration 404 * stream, but we need to recompute the page size pointers */ 405 for (i = 0; i < env->slb_nr; i++) { 406 if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) { 407 /* Migration source had bad values in its SLB */ 408 return -1; 409 } 410 } 411 412 return 0; 413 } 414 415 static const VMStateDescription vmstate_slb = { 416 .name = "cpu/slb", 417 .version_id = 1, 418 .minimum_version_id = 1, 419 .needed = slb_needed, 420 .post_load = slb_post_load, 421 .fields = (VMStateField[]) { 422 VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU), 423 VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES), 424 VMSTATE_END_OF_LIST() 425 } 426 }; 427 #endif /* TARGET_PPC64 */ 428 429 static const VMStateDescription vmstate_tlb6xx_entry = { 430 .name = "cpu/tlb6xx_entry", 431 .version_id = 1, 432 .minimum_version_id = 1, 433 .fields = (VMStateField[]) { 434 VMSTATE_UINTTL(pte0, ppc6xx_tlb_t), 435 VMSTATE_UINTTL(pte1, ppc6xx_tlb_t), 436 VMSTATE_UINTTL(EPN, ppc6xx_tlb_t), 437 VMSTATE_END_OF_LIST() 438 }, 439 }; 440 441 static bool tlb6xx_needed(void *opaque) 442 { 443 PowerPCCPU *cpu = opaque; 444 CPUPPCState *env = &cpu->env; 445 446 return env->nb_tlb && (env->tlb_type == TLB_6XX); 447 } 448 449 static const VMStateDescription vmstate_tlb6xx = { 450 .name = "cpu/tlb6xx", 451 .version_id = 1, 452 .minimum_version_id = 1, 453 .needed = tlb6xx_needed, 454 .fields = (VMStateField[]) { 455 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU), 456 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU, 457 env.nb_tlb, 458 vmstate_tlb6xx_entry, 459 ppc6xx_tlb_t), 460 VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4), 461 VMSTATE_END_OF_LIST() 462 } 463 }; 464 465 static const VMStateDescription vmstate_tlbemb_entry = { 466 .name = "cpu/tlbemb_entry", 467 .version_id = 1, 468 .minimum_version_id = 1, 469 .fields = (VMStateField[]) { 470 VMSTATE_UINT64(RPN, ppcemb_tlb_t), 471 VMSTATE_UINTTL(EPN, ppcemb_tlb_t), 472 VMSTATE_UINTTL(PID, ppcemb_tlb_t), 473 VMSTATE_UINTTL(size, ppcemb_tlb_t), 474 VMSTATE_UINT32(prot, ppcemb_tlb_t), 475 VMSTATE_UINT32(attr, ppcemb_tlb_t), 476 VMSTATE_END_OF_LIST() 477 }, 478 }; 479 480 static bool tlbemb_needed(void *opaque) 481 { 482 PowerPCCPU *cpu = opaque; 483 CPUPPCState *env = &cpu->env; 484 485 return env->nb_tlb && (env->tlb_type == TLB_EMB); 486 } 487 488 static bool pbr403_needed(void *opaque) 489 { 490 PowerPCCPU *cpu = opaque; 491 uint32_t pvr = cpu->env.spr[SPR_PVR]; 492 493 return (pvr & 0xffff0000) == 0x00200000; 494 } 495 496 static const VMStateDescription vmstate_pbr403 = { 497 .name = "cpu/pbr403", 498 .version_id = 1, 499 .minimum_version_id = 1, 500 .needed = pbr403_needed, 501 .fields = (VMStateField[]) { 502 VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4), 503 VMSTATE_END_OF_LIST() 504 }, 505 }; 506 507 static const VMStateDescription vmstate_tlbemb = { 508 .name = "cpu/tlb6xx", 509 .version_id = 1, 510 .minimum_version_id = 1, 511 .needed = tlbemb_needed, 512 .fields = (VMStateField[]) { 513 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU), 514 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU, 515 env.nb_tlb, 516 vmstate_tlbemb_entry, 517 ppcemb_tlb_t), 518 /* 403 protection registers */ 519 VMSTATE_END_OF_LIST() 520 }, 521 .subsections = (const VMStateDescription*[]) { 522 &vmstate_pbr403, 523 NULL 524 } 525 }; 526 527 static const VMStateDescription vmstate_tlbmas_entry = { 528 .name = "cpu/tlbmas_entry", 529 .version_id = 1, 530 .minimum_version_id = 1, 531 .fields = (VMStateField[]) { 532 VMSTATE_UINT32(mas8, ppcmas_tlb_t), 533 VMSTATE_UINT32(mas1, ppcmas_tlb_t), 534 VMSTATE_UINT64(mas2, ppcmas_tlb_t), 535 VMSTATE_UINT64(mas7_3, ppcmas_tlb_t), 536 VMSTATE_END_OF_LIST() 537 }, 538 }; 539 540 static bool tlbmas_needed(void *opaque) 541 { 542 PowerPCCPU *cpu = opaque; 543 CPUPPCState *env = &cpu->env; 544 545 return env->nb_tlb && (env->tlb_type == TLB_MAS); 546 } 547 548 static const VMStateDescription vmstate_tlbmas = { 549 .name = "cpu/tlbmas", 550 .version_id = 1, 551 .minimum_version_id = 1, 552 .needed = tlbmas_needed, 553 .fields = (VMStateField[]) { 554 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU), 555 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU, 556 env.nb_tlb, 557 vmstate_tlbmas_entry, 558 ppcmas_tlb_t), 559 VMSTATE_END_OF_LIST() 560 } 561 }; 562 563 const VMStateDescription vmstate_ppc_cpu = { 564 .name = "cpu", 565 .version_id = 5, 566 .minimum_version_id = 5, 567 .minimum_version_id_old = 4, 568 .load_state_old = cpu_load_old, 569 .pre_save = cpu_pre_save, 570 .post_load = cpu_post_load, 571 .fields = (VMStateField[]) { 572 VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */ 573 574 /* User mode architected state */ 575 VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32), 576 #if !defined(TARGET_PPC64) 577 VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32), 578 #endif 579 VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8), 580 VMSTATE_UINTTL(env.nip, PowerPCCPU), 581 582 /* SPRs */ 583 VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024), 584 VMSTATE_UINT64(env.spe_acc, PowerPCCPU), 585 586 /* Reservation */ 587 VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU), 588 589 /* Supervisor mode architected state */ 590 VMSTATE_UINTTL(env.msr, PowerPCCPU), 591 592 /* Internal state */ 593 VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU), 594 /* FIXME: access_type? */ 595 596 /* Sanity checking */ 597 VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration), 598 VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration), 599 VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU, 600 cpu_pre_2_8_migration), 601 VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration), 602 VMSTATE_END_OF_LIST() 603 }, 604 .subsections = (const VMStateDescription*[]) { 605 &vmstate_fpu, 606 &vmstate_altivec, 607 &vmstate_vsx, 608 &vmstate_sr, 609 #ifdef TARGET_PPC64 610 &vmstate_tm, 611 &vmstate_slb, 612 #endif /* TARGET_PPC64 */ 613 &vmstate_tlb6xx, 614 &vmstate_tlbemb, 615 &vmstate_tlbmas, 616 NULL 617 } 618 }; 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