1 /* 2 * PowerPC CPU routines for qemu. 3 * 4 * Copyright (c) 2017 Nikunj A Dadhania, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "cpu-models.h" 23 #include "cpu-qom.h" 24 #include "exec/log.h" 25 #include "fpu/softfloat-helpers.h" 26 #include "mmu-hash64.h" 27 #include "helper_regs.h" 28 #include "sysemu/tcg.h" 29 30 target_ulong cpu_read_xer(const CPUPPCState *env) 31 { 32 if (is_isa300(env)) { 33 return env->xer | (env->so << XER_SO) | 34 (env->ov << XER_OV) | (env->ca << XER_CA) | 35 (env->ov32 << XER_OV32) | (env->ca32 << XER_CA32); 36 } 37 38 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | 39 (env->ca << XER_CA); 40 } 41 42 void cpu_write_xer(CPUPPCState *env, target_ulong xer) 43 { 44 env->so = (xer >> XER_SO) & 1; 45 env->ov = (xer >> XER_OV) & 1; 46 env->ca = (xer >> XER_CA) & 1; 47 /* write all the flags, while reading back check of isa300 */ 48 env->ov32 = (xer >> XER_OV32) & 1; 49 env->ca32 = (xer >> XER_CA32) & 1; 50 env->xer = xer & ~((1ul << XER_SO) | 51 (1ul << XER_OV) | (1ul << XER_CA) | 52 (1ul << XER_OV32) | (1ul << XER_CA32)); 53 } 54 55 void ppc_store_vscr(CPUPPCState *env, uint32_t vscr) 56 { 57 env->vscr = vscr & ~(1u << VSCR_SAT); 58 /* Which bit we set is completely arbitrary, but clear the rest. */ 59 env->vscr_sat.u64[0] = vscr & (1u << VSCR_SAT); 60 env->vscr_sat.u64[1] = 0; 61 set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status); 62 } 63 64 uint32_t ppc_get_vscr(CPUPPCState *env) 65 { 66 uint32_t sat = (env->vscr_sat.u64[0] | env->vscr_sat.u64[1]) != 0; 67 return env->vscr | (sat << VSCR_SAT); 68 } 69 70 void ppc_set_cr(CPUPPCState *env, uint64_t cr) 71 { 72 for (int i = 7; i >= 0; i--) { 73 env->crf[i] = cr & 0xf; 74 cr >>= 4; 75 } 76 } 77 78 uint64_t ppc_get_cr(const CPUPPCState *env) 79 { 80 uint64_t cr = 0; 81 for (int i = 0; i < 8; i++) { 82 cr |= (env->crf[i] & 0xf) << (4 * (7 - i)); 83 } 84 return cr; 85 } 86 87 /* GDBstub can read and write MSR... */ 88 void ppc_store_msr(CPUPPCState *env, target_ulong value) 89 { 90 hreg_store_msr(env, value, 0); 91 } 92 93 #if !defined(CONFIG_USER_ONLY) 94 void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) 95 { 96 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 97 CPUPPCState *env = &cpu->env; 98 99 env->spr[SPR_LPCR] = val & pcc->lpcr_mask; 100 /* The gtse bit affects hflags */ 101 hreg_compute_hflags(env); 102 103 ppc_maybe_interrupt(env); 104 } 105 106 #if defined(TARGET_PPC64) 107 void ppc_update_ciabr(CPUPPCState *env) 108 { 109 CPUState *cs = env_cpu(env); 110 target_ulong ciabr = env->spr[SPR_CIABR]; 111 target_ulong ciea, priv; 112 113 ciea = ciabr & PPC_BITMASK(0, 61); 114 priv = ciabr & PPC_BITMASK(62, 63); 115 116 if (env->ciabr_breakpoint) { 117 cpu_breakpoint_remove_by_ref(cs, env->ciabr_breakpoint); 118 env->ciabr_breakpoint = NULL; 119 } 120 121 if (priv) { 122 cpu_breakpoint_insert(cs, ciea, BP_CPU, &env->ciabr_breakpoint); 123 } 124 } 125 126 void ppc_store_ciabr(CPUPPCState *env, target_ulong val) 127 { 128 env->spr[SPR_CIABR] = val; 129 ppc_update_ciabr(env); 130 } 131 132 void ppc_update_daw0(CPUPPCState *env) 133 { 134 CPUState *cs = env_cpu(env); 135 target_ulong deaw = env->spr[SPR_DAWR0] & PPC_BITMASK(0, 60); 136 uint32_t dawrx = env->spr[SPR_DAWRX0]; 137 int mrd = extract32(dawrx, PPC_BIT_NR(48), 54 - 48); 138 bool dw = extract32(dawrx, PPC_BIT_NR(57), 1); 139 bool dr = extract32(dawrx, PPC_BIT_NR(58), 1); 140 bool hv = extract32(dawrx, PPC_BIT_NR(61), 1); 141 bool sv = extract32(dawrx, PPC_BIT_NR(62), 1); 142 bool pr = extract32(dawrx, PPC_BIT_NR(62), 1); 143 vaddr len; 144 int flags; 145 146 if (env->dawr0_watchpoint) { 147 cpu_watchpoint_remove_by_ref(cs, env->dawr0_watchpoint); 148 env->dawr0_watchpoint = NULL; 149 } 150 151 if (!dr && !dw) { 152 return; 153 } 154 155 if (!hv && !sv && !pr) { 156 return; 157 } 158 159 len = (mrd + 1) * 8; 160 flags = BP_CPU | BP_STOP_BEFORE_ACCESS; 161 if (dr) { 162 flags |= BP_MEM_READ; 163 } 164 if (dw) { 165 flags |= BP_MEM_WRITE; 166 } 167 168 cpu_watchpoint_insert(cs, deaw, len, flags, &env->dawr0_watchpoint); 169 } 170 171 void ppc_store_dawr0(CPUPPCState *env, target_ulong val) 172 { 173 env->spr[SPR_DAWR0] = val; 174 ppc_update_daw0(env); 175 } 176 177 void ppc_store_dawrx0(CPUPPCState *env, uint32_t val) 178 { 179 int hrammc = extract32(val, PPC_BIT_NR(56), 1); 180 181 if (hrammc) { 182 /* This might be done with a second watchpoint at the xor of DEAW[0] */ 183 qemu_log_mask(LOG_UNIMP, "%s: DAWRX0[HRAMMC] is unimplemented\n", 184 __func__); 185 } 186 187 env->spr[SPR_DAWRX0] = val; 188 ppc_update_daw0(env); 189 } 190 #endif 191 #endif 192 193 static inline void fpscr_set_rounding_mode(CPUPPCState *env) 194 { 195 int rnd_type; 196 197 /* Set rounding mode */ 198 switch (env->fpscr & FP_RN) { 199 case 0: 200 /* Best approximation (round to nearest) */ 201 rnd_type = float_round_nearest_even; 202 break; 203 case 1: 204 /* Smaller magnitude (round toward zero) */ 205 rnd_type = float_round_to_zero; 206 break; 207 case 2: 208 /* Round toward +infinite */ 209 rnd_type = float_round_up; 210 break; 211 default: 212 case 3: 213 /* Round toward -infinite */ 214 rnd_type = float_round_down; 215 break; 216 } 217 set_float_rounding_mode(rnd_type, &env->fp_status); 218 } 219 220 void ppc_store_fpscr(CPUPPCState *env, target_ulong val) 221 { 222 val &= FPSCR_MTFS_MASK; 223 if (val & FPSCR_IX) { 224 val |= FP_VX; 225 } 226 if ((val >> FPSCR_XX) & (val >> FPSCR_XE) & 0x1f) { 227 val |= FP_FEX; 228 } 229 env->fpscr = val; 230 env->fp_status.rebias_overflow = (FP_OE & env->fpscr) ? true : false; 231 env->fp_status.rebias_underflow = (FP_UE & env->fpscr) ? true : false; 232 if (tcg_enabled()) { 233 fpscr_set_rounding_mode(env); 234 } 235 } 236