1 /* 2 * OpenRISC system instructions helper routines 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * Zhizhou Zhang <etouzh@gmail.com> 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "exec/exec-all.h" 24 #include "exec/helper-proto.h" 25 #include "exception.h" 26 #include "sysemu/sysemu.h" 27 #ifndef CONFIG_USER_ONLY 28 #include "hw/boards.h" 29 #endif 30 31 #define TO_SPR(group, number) (((group) << 11) + (number)) 32 33 void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) 34 { 35 #ifndef CONFIG_USER_ONLY 36 OpenRISCCPU *cpu = env_archcpu(env); 37 CPUState *cs = env_cpu(env); 38 target_ulong mr; 39 int idx; 40 41 switch (spr) { 42 case TO_SPR(0, 11): /* EVBAR */ 43 env->evbar = rb; 44 break; 45 46 case TO_SPR(0, 16): /* NPC */ 47 cpu_restore_state(cs, GETPC(), true); 48 /* ??? Mirror or1ksim in not trashing delayed branch state 49 when "jumping" to the current instruction. */ 50 if (env->pc != rb) { 51 env->pc = rb; 52 env->dflag = 0; 53 cpu_loop_exit(cs); 54 } 55 break; 56 57 case TO_SPR(0, 17): /* SR */ 58 cpu_set_sr(env, rb); 59 break; 60 61 case TO_SPR(0, 32): /* EPCR */ 62 env->epcr = rb; 63 break; 64 65 case TO_SPR(0, 48): /* EEAR */ 66 env->eear = rb; 67 break; 68 69 case TO_SPR(0, 64): /* ESR */ 70 env->esr = rb; 71 break; 72 73 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ 74 idx = (spr - 1024); 75 env->shadow_gpr[idx / 32][idx % 32] = rb; 76 break; 77 78 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ 79 idx = spr - TO_SPR(1, 512); 80 mr = env->tlb.dtlb[idx].mr; 81 if (mr & 1) { 82 tlb_flush_page(cs, mr & TARGET_PAGE_MASK); 83 } 84 if (rb & 1) { 85 tlb_flush_page(cs, rb & TARGET_PAGE_MASK); 86 } 87 env->tlb.dtlb[idx].mr = rb; 88 break; 89 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ 90 idx = spr - TO_SPR(1, 640); 91 env->tlb.dtlb[idx].tr = rb; 92 break; 93 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ 94 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ 95 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */ 96 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */ 97 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ 98 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ 99 break; 100 101 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ 102 idx = spr - TO_SPR(2, 512); 103 mr = env->tlb.itlb[idx].mr; 104 if (mr & 1) { 105 tlb_flush_page(cs, mr & TARGET_PAGE_MASK); 106 } 107 if (rb & 1) { 108 tlb_flush_page(cs, rb & TARGET_PAGE_MASK); 109 } 110 env->tlb.itlb[idx].mr = rb; 111 break; 112 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ 113 idx = spr - TO_SPR(2, 640); 114 env->tlb.itlb[idx].tr = rb; 115 break; 116 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ 117 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ 118 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */ 119 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */ 120 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ 121 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ 122 break; 123 124 case TO_SPR(5, 1): /* MACLO */ 125 env->mac = deposit64(env->mac, 0, 32, rb); 126 break; 127 case TO_SPR(5, 2): /* MACHI */ 128 env->mac = deposit64(env->mac, 32, 32, rb); 129 break; 130 case TO_SPR(8, 0): /* PMR */ 131 env->pmr = rb; 132 if (env->pmr & PMR_DME || env->pmr & PMR_SME) { 133 cpu_restore_state(cs, GETPC(), true); 134 env->pc += 4; 135 cs->halted = 1; 136 raise_exception(cpu, EXCP_HALTED); 137 } 138 break; 139 case TO_SPR(9, 0): /* PICMR */ 140 env->picmr = rb; 141 break; 142 case TO_SPR(9, 2): /* PICSR */ 143 env->picsr &= ~rb; 144 break; 145 case TO_SPR(10, 0): /* TTMR */ 146 { 147 if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) { 148 switch (rb & TTMR_M) { 149 case TIMER_NONE: 150 cpu_openrisc_count_stop(cpu); 151 break; 152 case TIMER_INTR: 153 case TIMER_SHOT: 154 case TIMER_CONT: 155 cpu_openrisc_count_start(cpu); 156 break; 157 default: 158 break; 159 } 160 } 161 162 int ip = env->ttmr & TTMR_IP; 163 164 if (rb & TTMR_IP) { /* Keep IP bit. */ 165 env->ttmr = (rb & ~TTMR_IP) | ip; 166 } else { /* Clear IP bit. */ 167 env->ttmr = rb & ~TTMR_IP; 168 cs->interrupt_request &= ~CPU_INTERRUPT_TIMER; 169 } 170 171 cpu_openrisc_timer_update(cpu); 172 } 173 break; 174 175 case TO_SPR(10, 1): /* TTCR */ 176 cpu_openrisc_count_set(cpu, rb); 177 if (env->ttmr & TIMER_NONE) { 178 return; 179 } 180 cpu_openrisc_timer_update(cpu); 181 break; 182 default: 183 break; 184 } 185 #endif 186 } 187 188 target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, 189 target_ulong spr) 190 { 191 #ifndef CONFIG_USER_ONLY 192 MachineState *ms = MACHINE(qdev_get_machine()); 193 OpenRISCCPU *cpu = env_archcpu(env); 194 CPUState *cs = env_cpu(env); 195 int idx; 196 197 switch (spr) { 198 case TO_SPR(0, 0): /* VR */ 199 return env->vr; 200 201 case TO_SPR(0, 1): /* UPR */ 202 return env->upr; /* TT, DM, IM, UP present */ 203 204 case TO_SPR(0, 2): /* CPUCFGR */ 205 return env->cpucfgr; 206 207 case TO_SPR(0, 3): /* DMMUCFGR */ 208 return env->dmmucfgr; /* 1Way, 64 entries */ 209 210 case TO_SPR(0, 4): /* IMMUCFGR */ 211 return env->immucfgr; 212 213 case TO_SPR(0, 11): /* EVBAR */ 214 return env->evbar; 215 216 case TO_SPR(0, 16): /* NPC (equals PC) */ 217 cpu_restore_state(cs, GETPC(), false); 218 return env->pc; 219 220 case TO_SPR(0, 17): /* SR */ 221 return cpu_get_sr(env); 222 223 case TO_SPR(0, 18): /* PPC */ 224 cpu_restore_state(cs, GETPC(), false); 225 return env->ppc; 226 227 case TO_SPR(0, 32): /* EPCR */ 228 return env->epcr; 229 230 case TO_SPR(0, 48): /* EEAR */ 231 return env->eear; 232 233 case TO_SPR(0, 64): /* ESR */ 234 return env->esr; 235 236 case TO_SPR(0, 128): /* COREID */ 237 return cpu->parent_obj.cpu_index; 238 239 case TO_SPR(0, 129): /* NUMCORES */ 240 return ms->smp.max_cpus; 241 242 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ 243 idx = (spr - 1024); 244 return env->shadow_gpr[idx / 32][idx % 32]; 245 246 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ 247 idx = spr - TO_SPR(1, 512); 248 return env->tlb.dtlb[idx].mr; 249 250 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ 251 idx = spr - TO_SPR(1, 640); 252 return env->tlb.dtlb[idx].tr; 253 254 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ 255 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ 256 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */ 257 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */ 258 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ 259 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ 260 break; 261 262 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ 263 idx = spr - TO_SPR(2, 512); 264 return env->tlb.itlb[idx].mr; 265 266 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ 267 idx = spr - TO_SPR(2, 640); 268 return env->tlb.itlb[idx].tr; 269 270 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ 271 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ 272 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */ 273 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */ 274 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ 275 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ 276 break; 277 278 case TO_SPR(5, 1): /* MACLO */ 279 return (uint32_t)env->mac; 280 break; 281 case TO_SPR(5, 2): /* MACHI */ 282 return env->mac >> 32; 283 break; 284 285 case TO_SPR(8, 0): /* PMR */ 286 return env->pmr; 287 288 case TO_SPR(9, 0): /* PICMR */ 289 return env->picmr; 290 291 case TO_SPR(9, 2): /* PICSR */ 292 return env->picsr; 293 294 case TO_SPR(10, 0): /* TTMR */ 295 return env->ttmr; 296 297 case TO_SPR(10, 1): /* TTCR */ 298 cpu_openrisc_count_update(cpu); 299 return cpu_openrisc_count_get(cpu); 300 301 default: 302 break; 303 } 304 #endif 305 306 /* for rd is passed in, if rd unchanged, just keep it back. */ 307 return rd; 308 } 309