1 /* 2 * OpenRISC system instructions helper routines 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * Zhizhou Zhang <etouzh@gmail.com> 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "exec/exec-all.h" 24 #include "exec/helper-proto.h" 25 #include "exception.h" 26 #ifndef CONFIG_USER_ONLY 27 #include "hw/boards.h" 28 #endif 29 30 #define TO_SPR(group, number) (((group) << 11) + (number)) 31 32 void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) 33 { 34 #ifndef CONFIG_USER_ONLY 35 OpenRISCCPU *cpu = env_archcpu(env); 36 CPUState *cs = env_cpu(env); 37 target_ulong mr; 38 int idx; 39 #endif 40 41 switch (spr) { 42 #ifndef CONFIG_USER_ONLY 43 case TO_SPR(0, 11): /* EVBAR */ 44 env->evbar = rb; 45 break; 46 47 case TO_SPR(0, 16): /* NPC */ 48 cpu_restore_state(cs, GETPC(), true); 49 /* ??? Mirror or1ksim in not trashing delayed branch state 50 when "jumping" to the current instruction. */ 51 if (env->pc != rb) { 52 env->pc = rb; 53 env->dflag = 0; 54 cpu_loop_exit(cs); 55 } 56 break; 57 58 case TO_SPR(0, 17): /* SR */ 59 cpu_set_sr(env, rb); 60 break; 61 62 case TO_SPR(0, 32): /* EPCR */ 63 env->epcr = rb; 64 break; 65 66 case TO_SPR(0, 48): /* EEAR */ 67 env->eear = rb; 68 break; 69 70 case TO_SPR(0, 64): /* ESR */ 71 env->esr = rb; 72 break; 73 74 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ 75 idx = (spr - 1024); 76 env->shadow_gpr[idx / 32][idx % 32] = rb; 77 break; 78 79 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ 80 idx = spr - TO_SPR(1, 512); 81 mr = env->tlb.dtlb[idx].mr; 82 if (mr & 1) { 83 tlb_flush_page(cs, mr & TARGET_PAGE_MASK); 84 } 85 if (rb & 1) { 86 tlb_flush_page(cs, rb & TARGET_PAGE_MASK); 87 } 88 env->tlb.dtlb[idx].mr = rb; 89 break; 90 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ 91 idx = spr - TO_SPR(1, 640); 92 env->tlb.dtlb[idx].tr = rb; 93 break; 94 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ 95 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ 96 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */ 97 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */ 98 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ 99 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ 100 break; 101 102 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ 103 idx = spr - TO_SPR(2, 512); 104 mr = env->tlb.itlb[idx].mr; 105 if (mr & 1) { 106 tlb_flush_page(cs, mr & TARGET_PAGE_MASK); 107 } 108 if (rb & 1) { 109 tlb_flush_page(cs, rb & TARGET_PAGE_MASK); 110 } 111 env->tlb.itlb[idx].mr = rb; 112 break; 113 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ 114 idx = spr - TO_SPR(2, 640); 115 env->tlb.itlb[idx].tr = rb; 116 break; 117 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ 118 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ 119 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */ 120 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */ 121 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ 122 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ 123 break; 124 125 case TO_SPR(5, 1): /* MACLO */ 126 env->mac = deposit64(env->mac, 0, 32, rb); 127 break; 128 case TO_SPR(5, 2): /* MACHI */ 129 env->mac = deposit64(env->mac, 32, 32, rb); 130 break; 131 case TO_SPR(8, 0): /* PMR */ 132 env->pmr = rb; 133 if (env->pmr & PMR_DME || env->pmr & PMR_SME) { 134 cpu_restore_state(cs, GETPC(), true); 135 env->pc += 4; 136 cs->halted = 1; 137 raise_exception(cpu, EXCP_HALTED); 138 } 139 break; 140 case TO_SPR(9, 0): /* PICMR */ 141 env->picmr = rb; 142 break; 143 case TO_SPR(9, 2): /* PICSR */ 144 env->picsr &= ~rb; 145 break; 146 case TO_SPR(10, 0): /* TTMR */ 147 { 148 qemu_mutex_lock_iothread(); 149 if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) { 150 switch (rb & TTMR_M) { 151 case TIMER_NONE: 152 cpu_openrisc_count_stop(cpu); 153 break; 154 case TIMER_INTR: 155 case TIMER_SHOT: 156 case TIMER_CONT: 157 cpu_openrisc_count_start(cpu); 158 break; 159 default: 160 break; 161 } 162 } 163 164 int ip = env->ttmr & TTMR_IP; 165 166 if (rb & TTMR_IP) { /* Keep IP bit. */ 167 env->ttmr = (rb & ~TTMR_IP) | ip; 168 } else { /* Clear IP bit. */ 169 env->ttmr = rb & ~TTMR_IP; 170 cs->interrupt_request &= ~CPU_INTERRUPT_TIMER; 171 } 172 cpu_openrisc_timer_update(cpu); 173 qemu_mutex_unlock_iothread(); 174 } 175 break; 176 177 case TO_SPR(10, 1): /* TTCR */ 178 qemu_mutex_lock_iothread(); 179 cpu_openrisc_count_set(cpu, rb); 180 cpu_openrisc_timer_update(cpu); 181 qemu_mutex_unlock_iothread(); 182 break; 183 #endif 184 185 case TO_SPR(0, 20): /* FPCSR */ 186 cpu_set_fpcsr(env, rb); 187 break; 188 } 189 } 190 191 target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, 192 target_ulong spr) 193 { 194 #ifndef CONFIG_USER_ONLY 195 MachineState *ms = MACHINE(qdev_get_machine()); 196 OpenRISCCPU *cpu = env_archcpu(env); 197 CPUState *cs = env_cpu(env); 198 int idx; 199 #endif 200 201 switch (spr) { 202 #ifndef CONFIG_USER_ONLY 203 case TO_SPR(0, 0): /* VR */ 204 return env->vr; 205 206 case TO_SPR(0, 1): /* UPR */ 207 return env->upr; 208 209 case TO_SPR(0, 2): /* CPUCFGR */ 210 return env->cpucfgr; 211 212 case TO_SPR(0, 3): /* DMMUCFGR */ 213 return env->dmmucfgr; 214 215 case TO_SPR(0, 4): /* IMMUCFGR */ 216 return env->immucfgr; 217 218 case TO_SPR(0, 9): /* VR2 */ 219 return env->vr2; 220 221 case TO_SPR(0, 10): /* AVR */ 222 return env->avr; 223 224 case TO_SPR(0, 11): /* EVBAR */ 225 return env->evbar; 226 227 case TO_SPR(0, 16): /* NPC (equals PC) */ 228 cpu_restore_state(cs, GETPC(), false); 229 return env->pc; 230 231 case TO_SPR(0, 17): /* SR */ 232 return cpu_get_sr(env); 233 234 case TO_SPR(0, 18): /* PPC */ 235 cpu_restore_state(cs, GETPC(), false); 236 return env->ppc; 237 238 case TO_SPR(0, 32): /* EPCR */ 239 return env->epcr; 240 241 case TO_SPR(0, 48): /* EEAR */ 242 return env->eear; 243 244 case TO_SPR(0, 64): /* ESR */ 245 return env->esr; 246 247 case TO_SPR(0, 128): /* COREID */ 248 return cpu->parent_obj.cpu_index; 249 250 case TO_SPR(0, 129): /* NUMCORES */ 251 return ms->smp.max_cpus; 252 253 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ 254 idx = (spr - 1024); 255 return env->shadow_gpr[idx / 32][idx % 32]; 256 257 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ 258 idx = spr - TO_SPR(1, 512); 259 return env->tlb.dtlb[idx].mr; 260 261 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ 262 idx = spr - TO_SPR(1, 640); 263 return env->tlb.dtlb[idx].tr; 264 265 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ 266 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ 267 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */ 268 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */ 269 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ 270 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ 271 break; 272 273 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ 274 idx = spr - TO_SPR(2, 512); 275 return env->tlb.itlb[idx].mr; 276 277 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ 278 idx = spr - TO_SPR(2, 640); 279 return env->tlb.itlb[idx].tr; 280 281 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ 282 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ 283 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */ 284 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */ 285 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ 286 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ 287 break; 288 289 case TO_SPR(5, 1): /* MACLO */ 290 return (uint32_t)env->mac; 291 break; 292 case TO_SPR(5, 2): /* MACHI */ 293 return env->mac >> 32; 294 break; 295 296 case TO_SPR(8, 0): /* PMR */ 297 return env->pmr; 298 299 case TO_SPR(9, 0): /* PICMR */ 300 return env->picmr; 301 302 case TO_SPR(9, 2): /* PICSR */ 303 return env->picsr; 304 305 case TO_SPR(10, 0): /* TTMR */ 306 return env->ttmr; 307 308 case TO_SPR(10, 1): /* TTCR */ 309 qemu_mutex_lock_iothread(); 310 cpu_openrisc_count_update(cpu); 311 qemu_mutex_unlock_iothread(); 312 return cpu_openrisc_count_get(cpu); 313 #endif 314 315 case TO_SPR(0, 20): /* FPCSR */ 316 return env->fpcsr; 317 } 318 319 /* for rd is passed in, if rd unchanged, just keep it back. */ 320 return rd; 321 } 322