1 /* 2 * MIPS translation routines. 3 * 4 * Copyright (c) 2004-2005 Jocelyn Mayer 5 * 6 * SPDX-License-Identifier: LGPL-2.1-or-later 7 */ 8 #ifndef TARGET_MIPS_TRANSLATE_H 9 #define TARGET_MIPS_TRANSLATE_H 10 11 #include "qemu/log.h" 12 #include "exec/translator.h" 13 #include "tcg/tcg-op.h" 14 15 #define MIPS_DEBUG_DISAS 0 16 17 typedef struct DisasContext { 18 DisasContextBase base; 19 target_ulong saved_pc; 20 target_ulong page_start; 21 uint32_t opcode; 22 uint64_t insn_flags; 23 int32_t CP0_Config0; 24 int32_t CP0_Config1; 25 int32_t CP0_Config2; 26 int32_t CP0_Config3; 27 int32_t CP0_Config5; 28 /* Routine used to access memory */ 29 int mem_idx; 30 MemOp default_tcg_memop_mask; 31 uint32_t hflags, saved_hflags; 32 target_ulong btarget; 33 bool ulri; 34 int kscrexist; 35 bool rxi; 36 int ie; 37 bool bi; 38 bool bp; 39 uint64_t PAMask; 40 bool mvh; 41 bool eva; 42 bool sc; 43 int CP0_LLAddr_shift; 44 bool ps; 45 bool vp; 46 bool cmgcr; 47 bool mrp; 48 bool nan2008; 49 bool abs2008; 50 bool saar; 51 bool mi; 52 int gi; 53 } DisasContext; 54 55 #define DISAS_STOP DISAS_TARGET_0 56 #define DISAS_EXIT DISAS_TARGET_1 57 #define DISAS_SEMIHOST DISAS_TARGET_2 58 59 /* MIPS major opcodes */ 60 #define MASK_OP_MAJOR(op) (op & (0x3F << 26)) 61 62 #define OPC_CP1 (0x11 << 26) 63 64 /* Coprocessor 1 (rs field) */ 65 #define MASK_CP1(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21))) 66 67 /* Values for the fmt field in FP instructions */ 68 enum { 69 /* 0 - 15 are reserved */ 70 FMT_S = 16, /* single fp */ 71 FMT_D = 17, /* double fp */ 72 FMT_E = 18, /* extended fp */ 73 FMT_Q = 19, /* quad fp */ 74 FMT_W = 20, /* 32-bit fixed */ 75 FMT_L = 21, /* 64-bit fixed */ 76 FMT_PS = 22, /* paired single fp */ 77 /* 23 - 31 are reserved */ 78 }; 79 80 enum { 81 OPC_MFC1 = (0x00 << 21) | OPC_CP1, 82 OPC_DMFC1 = (0x01 << 21) | OPC_CP1, 83 OPC_CFC1 = (0x02 << 21) | OPC_CP1, 84 OPC_MFHC1 = (0x03 << 21) | OPC_CP1, 85 OPC_MTC1 = (0x04 << 21) | OPC_CP1, 86 OPC_DMTC1 = (0x05 << 21) | OPC_CP1, 87 OPC_CTC1 = (0x06 << 21) | OPC_CP1, 88 OPC_MTHC1 = (0x07 << 21) | OPC_CP1, 89 OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */ 90 OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1, 91 OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1, 92 OPC_S_FMT = (FMT_S << 21) | OPC_CP1, 93 OPC_D_FMT = (FMT_D << 21) | OPC_CP1, 94 OPC_E_FMT = (FMT_E << 21) | OPC_CP1, 95 OPC_Q_FMT = (FMT_Q << 21) | OPC_CP1, 96 OPC_W_FMT = (FMT_W << 21) | OPC_CP1, 97 OPC_L_FMT = (FMT_L << 21) | OPC_CP1, 98 OPC_PS_FMT = (FMT_PS << 21) | OPC_CP1, 99 OPC_BC1EQZ = (0x09 << 21) | OPC_CP1, 100 OPC_BC1NEZ = (0x0D << 21) | OPC_CP1, 101 }; 102 103 #define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F)) 104 #define MASK_BC1(op) (MASK_CP1(op) | (op & (0x3 << 16))) 105 106 enum { 107 OPC_BC1F = (0x00 << 16) | OPC_BC1, 108 OPC_BC1T = (0x01 << 16) | OPC_BC1, 109 OPC_BC1FL = (0x02 << 16) | OPC_BC1, 110 OPC_BC1TL = (0x03 << 16) | OPC_BC1, 111 }; 112 113 enum { 114 OPC_BC1FANY2 = (0x00 << 16) | OPC_BC1ANY2, 115 OPC_BC1TANY2 = (0x01 << 16) | OPC_BC1ANY2, 116 }; 117 118 enum { 119 OPC_BC1FANY4 = (0x00 << 16) | OPC_BC1ANY4, 120 OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4, 121 }; 122 123 #define gen_helper_0e1i(name, arg1, arg2) do { \ 124 gen_helper_##name(cpu_env, arg1, tcg_constant_i32(arg2)); \ 125 } while (0) 126 127 #define gen_helper_1e0i(name, ret, arg1) do { \ 128 gen_helper_##name(ret, cpu_env, tcg_constant_i32(arg1)); \ 129 } while (0) 130 131 #define gen_helper_0e2i(name, arg1, arg2, arg3) do { \ 132 gen_helper_##name(cpu_env, arg1, arg2, tcg_constant_i32(arg3));\ 133 } while (0) 134 135 void generate_exception(DisasContext *ctx, int excp); 136 void generate_exception_err(DisasContext *ctx, int excp, int err); 137 void generate_exception_end(DisasContext *ctx, int excp); 138 void generate_exception_break(DisasContext *ctx, int code); 139 void gen_reserved_instruction(DisasContext *ctx); 140 141 void check_insn(DisasContext *ctx, uint64_t flags); 142 void check_mips_64(DisasContext *ctx); 143 /** 144 * check_cp0_enabled: 145 * Return %true if CP0 is enabled, otherwise return %false 146 * and emit a 'coprocessor unusable' exception. 147 */ 148 bool check_cp0_enabled(DisasContext *ctx); 149 void check_cp1_enabled(DisasContext *ctx); 150 void check_cp1_64bitmode(DisasContext *ctx); 151 void check_cp1_registers(DisasContext *ctx, int regs); 152 void check_cop1x(DisasContext *ctx); 153 154 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset); 155 void gen_move_low32(TCGv ret, TCGv_i64 arg); 156 void gen_move_high32(TCGv ret, TCGv_i64 arg); 157 void gen_load_gpr(TCGv t, int reg); 158 void gen_store_gpr(TCGv t, int reg); 159 #if defined(TARGET_MIPS64) 160 void gen_load_gpr_hi(TCGv_i64 t, int reg); 161 void gen_store_gpr_hi(TCGv_i64 t, int reg); 162 #endif /* TARGET_MIPS64 */ 163 void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg); 164 void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg); 165 void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg); 166 void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg); 167 int get_fp_bit(int cc); 168 169 void gen_ldxs(DisasContext *ctx, int base, int index, int rd); 170 void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int bp); 171 void gen_addiupc(DisasContext *ctx, int rx, int imm, 172 int is_64_bit, int extended); 173 174 /* 175 * Address Computation and Large Constant Instructions 176 */ 177 void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1); 178 bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa); 179 bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa); 180 181 void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel); 182 183 extern TCGv cpu_gpr[32], cpu_PC; 184 #if defined(TARGET_MIPS64) 185 extern TCGv_i64 cpu_gpr_hi[32]; 186 #endif 187 extern TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; 188 extern TCGv_i32 fpu_fcr0, fpu_fcr31; 189 extern TCGv_i64 fpu_f64[32]; 190 extern TCGv bcond; 191 192 #define LOG_DISAS(...) \ 193 do { \ 194 if (MIPS_DEBUG_DISAS) { \ 195 qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \ 196 } \ 197 } while (0) 198 199 #define MIPS_INVAL(op) \ 200 do { \ 201 if (MIPS_DEBUG_DISAS) { \ 202 qemu_log_mask(CPU_LOG_TB_IN_ASM, \ 203 TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \ 204 ctx->base.pc_next, ctx->opcode, op, \ 205 ctx->opcode >> 26, ctx->opcode & 0x3F, \ 206 ((ctx->opcode >> 16) & 0x1F)); \ 207 } \ 208 } while (0) 209 210 /* MSA */ 211 void msa_translate_init(void); 212 213 /* MXU */ 214 void mxu_translate_init(void); 215 bool decode_ase_mxu(DisasContext *ctx, uint32_t insn); 216 217 /* decodetree generated */ 218 bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); 219 bool decode_ase_msa(DisasContext *ctx, uint32_t insn); 220 bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); 221 #if defined(TARGET_MIPS64) 222 bool decode_ext_tx79(DisasContext *ctx, uint32_t insn); 223 bool decode_ext_octeon(DisasContext *ctx, uint32_t insn); 224 #endif 225 bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn); 226 227 /* 228 * Helpers for implementing sets of trans_* functions. 229 * Defer the implementation of NAME to FUNC, with optional extra arguments. 230 */ 231 #define TRANS(NAME, FUNC, ...) \ 232 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 233 { return FUNC(ctx, a, __VA_ARGS__); } 234 235 static inline bool cpu_is_bigendian(DisasContext *ctx) 236 { 237 return extract32(ctx->CP0_Config0, CP0C0_BE, 1); 238 } 239 240 #endif 241