1 /* 2 * MIPS emulation for QEMU - main translation routines 3 * 4 * Copyright (c) 2004-2005 Jocelyn Mayer 5 * Copyright (c) 2006 Marius Groeger (FPU operations) 6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) 7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) 8 * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) 9 * Copyright (c) 2020 Philippe Mathieu-Daudé 10 * 11 * This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU Lesser General Public 13 * License as published by the Free Software Foundation; either 14 * version 2.1 of the License, or (at your option) any later version. 15 * 16 * This library is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * Lesser General Public License for more details. 20 * 21 * You should have received a copy of the GNU Lesser General Public 22 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "cpu.h" 27 #include "internal.h" 28 #include "tcg/tcg-op.h" 29 #include "exec/translator.h" 30 #include "exec/helper-proto.h" 31 #include "exec/helper-gen.h" 32 #include "semihosting/semihost.h" 33 34 #include "trace.h" 35 #include "exec/log.h" 36 #include "qemu/qemu-print.h" 37 #include "fpu_helper.h" 38 #include "translate.h" 39 40 #define HELPER_H "helper.h" 41 #include "exec/helper-info.c.inc" 42 #undef HELPER_H 43 44 45 /* 46 * Many sysemu-only helpers are not reachable for user-only. 47 * Define stub generators here, so that we need not either sprinkle 48 * ifdefs through the translator, nor provide the helper function. 49 */ 50 #define STUB_HELPER(NAME, ...) \ 51 static inline void gen_helper_##NAME(__VA_ARGS__) \ 52 { g_assert_not_reached(); } 53 54 #ifdef CONFIG_USER_ONLY 55 STUB_HELPER(cache, TCGv_env env, TCGv val, TCGv_i32 reg) 56 #endif 57 58 enum { 59 /* indirect opcode tables */ 60 OPC_SPECIAL = (0x00 << 26), 61 OPC_REGIMM = (0x01 << 26), 62 OPC_CP0 = (0x10 << 26), 63 OPC_CP2 = (0x12 << 26), 64 OPC_CP3 = (0x13 << 26), 65 OPC_SPECIAL2 = (0x1C << 26), 66 OPC_SPECIAL3 = (0x1F << 26), 67 /* arithmetic with immediate */ 68 OPC_ADDI = (0x08 << 26), 69 OPC_ADDIU = (0x09 << 26), 70 OPC_SLTI = (0x0A << 26), 71 OPC_SLTIU = (0x0B << 26), 72 /* logic with immediate */ 73 OPC_ANDI = (0x0C << 26), 74 OPC_ORI = (0x0D << 26), 75 OPC_XORI = (0x0E << 26), 76 OPC_LUI = (0x0F << 26), 77 /* arithmetic with immediate */ 78 OPC_DADDI = (0x18 << 26), 79 OPC_DADDIU = (0x19 << 26), 80 /* Jump and branches */ 81 OPC_J = (0x02 << 26), 82 OPC_JAL = (0x03 << 26), 83 OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */ 84 OPC_BEQL = (0x14 << 26), 85 OPC_BNE = (0x05 << 26), 86 OPC_BNEL = (0x15 << 26), 87 OPC_BLEZ = (0x06 << 26), 88 OPC_BLEZL = (0x16 << 26), 89 OPC_BGTZ = (0x07 << 26), 90 OPC_BGTZL = (0x17 << 26), 91 OPC_JALX = (0x1D << 26), 92 OPC_DAUI = (0x1D << 26), 93 /* Load and stores */ 94 OPC_LDL = (0x1A << 26), 95 OPC_LDR = (0x1B << 26), 96 OPC_LB = (0x20 << 26), 97 OPC_LH = (0x21 << 26), 98 OPC_LWL = (0x22 << 26), 99 OPC_LW = (0x23 << 26), 100 OPC_LWPC = OPC_LW | 0x5, 101 OPC_LBU = (0x24 << 26), 102 OPC_LHU = (0x25 << 26), 103 OPC_LWR = (0x26 << 26), 104 OPC_LWU = (0x27 << 26), 105 OPC_SB = (0x28 << 26), 106 OPC_SH = (0x29 << 26), 107 OPC_SWL = (0x2A << 26), 108 OPC_SW = (0x2B << 26), 109 OPC_SDL = (0x2C << 26), 110 OPC_SDR = (0x2D << 26), 111 OPC_SWR = (0x2E << 26), 112 OPC_LL = (0x30 << 26), 113 OPC_LLD = (0x34 << 26), 114 OPC_LD = (0x37 << 26), 115 OPC_LDPC = OPC_LD | 0x5, 116 OPC_SC = (0x38 << 26), 117 OPC_SCD = (0x3C << 26), 118 OPC_SD = (0x3F << 26), 119 /* Floating point load/store */ 120 OPC_LWC1 = (0x31 << 26), 121 OPC_LWC2 = (0x32 << 26), 122 OPC_LDC1 = (0x35 << 26), 123 OPC_LDC2 = (0x36 << 26), 124 OPC_SWC1 = (0x39 << 26), 125 OPC_SWC2 = (0x3A << 26), 126 OPC_SDC1 = (0x3D << 26), 127 OPC_SDC2 = (0x3E << 26), 128 /* Compact Branches */ 129 OPC_BLEZALC = (0x06 << 26), 130 OPC_BGEZALC = (0x06 << 26), 131 OPC_BGEUC = (0x06 << 26), 132 OPC_BGTZALC = (0x07 << 26), 133 OPC_BLTZALC = (0x07 << 26), 134 OPC_BLTUC = (0x07 << 26), 135 OPC_BOVC = (0x08 << 26), 136 OPC_BEQZALC = (0x08 << 26), 137 OPC_BEQC = (0x08 << 26), 138 OPC_BLEZC = (0x16 << 26), 139 OPC_BGEZC = (0x16 << 26), 140 OPC_BGEC = (0x16 << 26), 141 OPC_BGTZC = (0x17 << 26), 142 OPC_BLTZC = (0x17 << 26), 143 OPC_BLTC = (0x17 << 26), 144 OPC_BNVC = (0x18 << 26), 145 OPC_BNEZALC = (0x18 << 26), 146 OPC_BNEC = (0x18 << 26), 147 OPC_BC = (0x32 << 26), 148 OPC_BEQZC = (0x36 << 26), 149 OPC_JIC = (0x36 << 26), 150 OPC_BALC = (0x3A << 26), 151 OPC_BNEZC = (0x3E << 26), 152 OPC_JIALC = (0x3E << 26), 153 /* MDMX ASE specific */ 154 OPC_MDMX = (0x1E << 26), 155 /* Cache and prefetch */ 156 OPC_CACHE = (0x2F << 26), 157 OPC_PREF = (0x33 << 26), 158 /* PC-relative address computation / loads */ 159 OPC_PCREL = (0x3B << 26), 160 }; 161 162 /* PC-relative address computation / loads */ 163 #define MASK_OPC_PCREL_TOP2BITS(op) (MASK_OP_MAJOR(op) | (op & (3 << 19))) 164 #define MASK_OPC_PCREL_TOP5BITS(op) (MASK_OP_MAJOR(op) | (op & (0x1f << 16))) 165 enum { 166 /* Instructions determined by bits 19 and 20 */ 167 OPC_ADDIUPC = OPC_PCREL | (0 << 19), 168 R6_OPC_LWPC = OPC_PCREL | (1 << 19), 169 OPC_LWUPC = OPC_PCREL | (2 << 19), 170 171 /* Instructions determined by bits 16 ... 20 */ 172 OPC_AUIPC = OPC_PCREL | (0x1e << 16), 173 OPC_ALUIPC = OPC_PCREL | (0x1f << 16), 174 175 /* Other */ 176 R6_OPC_LDPC = OPC_PCREL | (6 << 18), 177 }; 178 179 /* MIPS special opcodes */ 180 #define MASK_SPECIAL(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) 181 182 enum { 183 /* Shifts */ 184 OPC_SLL = 0x00 | OPC_SPECIAL, 185 /* NOP is SLL r0, r0, 0 */ 186 /* SSNOP is SLL r0, r0, 1 */ 187 /* EHB is SLL r0, r0, 3 */ 188 OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */ 189 OPC_ROTR = OPC_SRL | (1 << 21), 190 OPC_SRA = 0x03 | OPC_SPECIAL, 191 OPC_SLLV = 0x04 | OPC_SPECIAL, 192 OPC_SRLV = 0x06 | OPC_SPECIAL, /* also ROTRV */ 193 OPC_ROTRV = OPC_SRLV | (1 << 6), 194 OPC_SRAV = 0x07 | OPC_SPECIAL, 195 OPC_DSLLV = 0x14 | OPC_SPECIAL, 196 OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */ 197 OPC_DROTRV = OPC_DSRLV | (1 << 6), 198 OPC_DSRAV = 0x17 | OPC_SPECIAL, 199 OPC_DSLL = 0x38 | OPC_SPECIAL, 200 OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */ 201 OPC_DROTR = OPC_DSRL | (1 << 21), 202 OPC_DSRA = 0x3B | OPC_SPECIAL, 203 OPC_DSLL32 = 0x3C | OPC_SPECIAL, 204 OPC_DSRL32 = 0x3E | OPC_SPECIAL, /* also DROTR32 */ 205 OPC_DROTR32 = OPC_DSRL32 | (1 << 21), 206 OPC_DSRA32 = 0x3F | OPC_SPECIAL, 207 /* Multiplication / division */ 208 OPC_MULT = 0x18 | OPC_SPECIAL, 209 OPC_MULTU = 0x19 | OPC_SPECIAL, 210 OPC_DIV = 0x1A | OPC_SPECIAL, 211 OPC_DIVU = 0x1B | OPC_SPECIAL, 212 OPC_DMULT = 0x1C | OPC_SPECIAL, 213 OPC_DMULTU = 0x1D | OPC_SPECIAL, 214 OPC_DDIV = 0x1E | OPC_SPECIAL, 215 OPC_DDIVU = 0x1F | OPC_SPECIAL, 216 217 /* 2 registers arithmetic / logic */ 218 OPC_ADD = 0x20 | OPC_SPECIAL, 219 OPC_ADDU = 0x21 | OPC_SPECIAL, 220 OPC_SUB = 0x22 | OPC_SPECIAL, 221 OPC_SUBU = 0x23 | OPC_SPECIAL, 222 OPC_AND = 0x24 | OPC_SPECIAL, 223 OPC_OR = 0x25 | OPC_SPECIAL, 224 OPC_XOR = 0x26 | OPC_SPECIAL, 225 OPC_NOR = 0x27 | OPC_SPECIAL, 226 OPC_SLT = 0x2A | OPC_SPECIAL, 227 OPC_SLTU = 0x2B | OPC_SPECIAL, 228 OPC_DADD = 0x2C | OPC_SPECIAL, 229 OPC_DADDU = 0x2D | OPC_SPECIAL, 230 OPC_DSUB = 0x2E | OPC_SPECIAL, 231 OPC_DSUBU = 0x2F | OPC_SPECIAL, 232 /* Jumps */ 233 OPC_JR = 0x08 | OPC_SPECIAL, /* Also JR.HB */ 234 OPC_JALR = 0x09 | OPC_SPECIAL, /* Also JALR.HB */ 235 /* Traps */ 236 OPC_TGE = 0x30 | OPC_SPECIAL, 237 OPC_TGEU = 0x31 | OPC_SPECIAL, 238 OPC_TLT = 0x32 | OPC_SPECIAL, 239 OPC_TLTU = 0x33 | OPC_SPECIAL, 240 OPC_TEQ = 0x34 | OPC_SPECIAL, 241 OPC_TNE = 0x36 | OPC_SPECIAL, 242 /* HI / LO registers load & stores */ 243 OPC_MFHI = 0x10 | OPC_SPECIAL, 244 OPC_MTHI = 0x11 | OPC_SPECIAL, 245 OPC_MFLO = 0x12 | OPC_SPECIAL, 246 OPC_MTLO = 0x13 | OPC_SPECIAL, 247 /* Conditional moves */ 248 OPC_MOVZ = 0x0A | OPC_SPECIAL, 249 OPC_MOVN = 0x0B | OPC_SPECIAL, 250 251 OPC_SELEQZ = 0x35 | OPC_SPECIAL, 252 OPC_SELNEZ = 0x37 | OPC_SPECIAL, 253 254 OPC_MOVCI = 0x01 | OPC_SPECIAL, 255 256 /* Special */ 257 OPC_PMON = 0x05 | OPC_SPECIAL, /* unofficial */ 258 OPC_SYSCALL = 0x0C | OPC_SPECIAL, 259 OPC_BREAK = 0x0D | OPC_SPECIAL, 260 OPC_SPIM = 0x0E | OPC_SPECIAL, /* unofficial */ 261 OPC_SYNC = 0x0F | OPC_SPECIAL, 262 263 OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL, 264 OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL, 265 OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL, 266 OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL, 267 }; 268 269 /* 270 * R6 Multiply and Divide instructions have the same opcode 271 * and function field as legacy OPC_MULT[U]/OPC_DIV[U] 272 */ 273 #define MASK_R6_MULDIV(op) (MASK_SPECIAL(op) | (op & (0x7ff))) 274 275 enum { 276 R6_OPC_MUL = OPC_MULT | (2 << 6), 277 R6_OPC_MUH = OPC_MULT | (3 << 6), 278 R6_OPC_MULU = OPC_MULTU | (2 << 6), 279 R6_OPC_MUHU = OPC_MULTU | (3 << 6), 280 R6_OPC_DIV = OPC_DIV | (2 << 6), 281 R6_OPC_MOD = OPC_DIV | (3 << 6), 282 R6_OPC_DIVU = OPC_DIVU | (2 << 6), 283 R6_OPC_MODU = OPC_DIVU | (3 << 6), 284 285 R6_OPC_DMUL = OPC_DMULT | (2 << 6), 286 R6_OPC_DMUH = OPC_DMULT | (3 << 6), 287 R6_OPC_DMULU = OPC_DMULTU | (2 << 6), 288 R6_OPC_DMUHU = OPC_DMULTU | (3 << 6), 289 R6_OPC_DDIV = OPC_DDIV | (2 << 6), 290 R6_OPC_DMOD = OPC_DDIV | (3 << 6), 291 R6_OPC_DDIVU = OPC_DDIVU | (2 << 6), 292 R6_OPC_DMODU = OPC_DDIVU | (3 << 6), 293 294 R6_OPC_CLZ = 0x10 | OPC_SPECIAL, 295 R6_OPC_CLO = 0x11 | OPC_SPECIAL, 296 R6_OPC_DCLZ = 0x12 | OPC_SPECIAL, 297 R6_OPC_DCLO = 0x13 | OPC_SPECIAL, 298 R6_OPC_SDBBP = 0x0e | OPC_SPECIAL, 299 }; 300 301 /* REGIMM (rt field) opcodes */ 302 #define MASK_REGIMM(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 16))) 303 304 enum { 305 OPC_BLTZ = (0x00 << 16) | OPC_REGIMM, 306 OPC_BLTZL = (0x02 << 16) | OPC_REGIMM, 307 OPC_BGEZ = (0x01 << 16) | OPC_REGIMM, 308 OPC_BGEZL = (0x03 << 16) | OPC_REGIMM, 309 OPC_BLTZAL = (0x10 << 16) | OPC_REGIMM, 310 OPC_BLTZALL = (0x12 << 16) | OPC_REGIMM, 311 OPC_BGEZAL = (0x11 << 16) | OPC_REGIMM, 312 OPC_BGEZALL = (0x13 << 16) | OPC_REGIMM, 313 OPC_TGEI = (0x08 << 16) | OPC_REGIMM, 314 OPC_TGEIU = (0x09 << 16) | OPC_REGIMM, 315 OPC_TLTI = (0x0A << 16) | OPC_REGIMM, 316 OPC_TLTIU = (0x0B << 16) | OPC_REGIMM, 317 OPC_TEQI = (0x0C << 16) | OPC_REGIMM, 318 OPC_TNEI = (0x0E << 16) | OPC_REGIMM, 319 OPC_SIGRIE = (0x17 << 16) | OPC_REGIMM, 320 OPC_SYNCI = (0x1F << 16) | OPC_REGIMM, 321 322 OPC_DAHI = (0x06 << 16) | OPC_REGIMM, 323 OPC_DATI = (0x1e << 16) | OPC_REGIMM, 324 }; 325 326 /* Special2 opcodes */ 327 #define MASK_SPECIAL2(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) 328 329 enum { 330 /* Multiply & xxx operations */ 331 OPC_MADD = 0x00 | OPC_SPECIAL2, 332 OPC_MADDU = 0x01 | OPC_SPECIAL2, 333 OPC_MUL = 0x02 | OPC_SPECIAL2, 334 OPC_MSUB = 0x04 | OPC_SPECIAL2, 335 OPC_MSUBU = 0x05 | OPC_SPECIAL2, 336 /* Loongson 2F */ 337 OPC_MULT_G_2F = 0x10 | OPC_SPECIAL2, 338 OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2, 339 OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2, 340 OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2, 341 OPC_DIV_G_2F = 0x14 | OPC_SPECIAL2, 342 OPC_DDIV_G_2F = 0x15 | OPC_SPECIAL2, 343 OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2, 344 OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2, 345 OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2, 346 OPC_DMOD_G_2F = 0x1d | OPC_SPECIAL2, 347 OPC_MODU_G_2F = 0x1e | OPC_SPECIAL2, 348 OPC_DMODU_G_2F = 0x1f | OPC_SPECIAL2, 349 /* Misc */ 350 OPC_CLZ = 0x20 | OPC_SPECIAL2, 351 OPC_CLO = 0x21 | OPC_SPECIAL2, 352 OPC_DCLZ = 0x24 | OPC_SPECIAL2, 353 OPC_DCLO = 0x25 | OPC_SPECIAL2, 354 /* Special */ 355 OPC_SDBBP = 0x3F | OPC_SPECIAL2, 356 }; 357 358 /* Special3 opcodes */ 359 #define MASK_SPECIAL3(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) 360 361 enum { 362 OPC_EXT = 0x00 | OPC_SPECIAL3, 363 OPC_DEXTM = 0x01 | OPC_SPECIAL3, 364 OPC_DEXTU = 0x02 | OPC_SPECIAL3, 365 OPC_DEXT = 0x03 | OPC_SPECIAL3, 366 OPC_INS = 0x04 | OPC_SPECIAL3, 367 OPC_DINSM = 0x05 | OPC_SPECIAL3, 368 OPC_DINSU = 0x06 | OPC_SPECIAL3, 369 OPC_DINS = 0x07 | OPC_SPECIAL3, 370 OPC_FORK = 0x08 | OPC_SPECIAL3, 371 OPC_YIELD = 0x09 | OPC_SPECIAL3, 372 OPC_BSHFL = 0x20 | OPC_SPECIAL3, 373 OPC_DBSHFL = 0x24 | OPC_SPECIAL3, 374 OPC_RDHWR = 0x3B | OPC_SPECIAL3, 375 OPC_GINV = 0x3D | OPC_SPECIAL3, 376 377 /* Loongson 2E */ 378 OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3, 379 OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3, 380 OPC_DIV_G_2E = 0x1A | OPC_SPECIAL3, 381 OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3, 382 OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3, 383 OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3, 384 OPC_DDIV_G_2E = 0x1E | OPC_SPECIAL3, 385 OPC_DDIVU_G_2E = 0x1F | OPC_SPECIAL3, 386 OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3, 387 OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3, 388 OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3, 389 OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3, 390 391 /* MIPS DSP Load */ 392 OPC_LX_DSP = 0x0A | OPC_SPECIAL3, 393 /* MIPS DSP Arithmetic */ 394 OPC_ADDU_QB_DSP = 0x10 | OPC_SPECIAL3, 395 OPC_ADDU_OB_DSP = 0x14 | OPC_SPECIAL3, 396 OPC_ABSQ_S_PH_DSP = 0x12 | OPC_SPECIAL3, 397 OPC_ABSQ_S_QH_DSP = 0x16 | OPC_SPECIAL3, 398 /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */ 399 /* OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, */ 400 OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3, 401 OPC_CMPU_EQ_OB_DSP = 0x15 | OPC_SPECIAL3, 402 /* MIPS DSP GPR-Based Shift Sub-class */ 403 OPC_SHLL_QB_DSP = 0x13 | OPC_SPECIAL3, 404 OPC_SHLL_OB_DSP = 0x17 | OPC_SPECIAL3, 405 /* MIPS DSP Multiply Sub-class insns */ 406 /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP. */ 407 /* OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, */ 408 OPC_DPA_W_PH_DSP = 0x30 | OPC_SPECIAL3, 409 OPC_DPAQ_W_QH_DSP = 0x34 | OPC_SPECIAL3, 410 /* DSP Bit/Manipulation Sub-class */ 411 OPC_INSV_DSP = 0x0C | OPC_SPECIAL3, 412 OPC_DINSV_DSP = 0x0D | OPC_SPECIAL3, 413 /* MIPS DSP Append Sub-class */ 414 OPC_APPEND_DSP = 0x31 | OPC_SPECIAL3, 415 OPC_DAPPEND_DSP = 0x35 | OPC_SPECIAL3, 416 /* MIPS DSP Accumulator and DSPControl Access Sub-class */ 417 OPC_EXTR_W_DSP = 0x38 | OPC_SPECIAL3, 418 OPC_DEXTR_W_DSP = 0x3C | OPC_SPECIAL3, 419 420 /* EVA */ 421 OPC_LWLE = 0x19 | OPC_SPECIAL3, 422 OPC_LWRE = 0x1A | OPC_SPECIAL3, 423 OPC_CACHEE = 0x1B | OPC_SPECIAL3, 424 OPC_SBE = 0x1C | OPC_SPECIAL3, 425 OPC_SHE = 0x1D | OPC_SPECIAL3, 426 OPC_SCE = 0x1E | OPC_SPECIAL3, 427 OPC_SWE = 0x1F | OPC_SPECIAL3, 428 OPC_SWLE = 0x21 | OPC_SPECIAL3, 429 OPC_SWRE = 0x22 | OPC_SPECIAL3, 430 OPC_PREFE = 0x23 | OPC_SPECIAL3, 431 OPC_LBUE = 0x28 | OPC_SPECIAL3, 432 OPC_LHUE = 0x29 | OPC_SPECIAL3, 433 OPC_LBE = 0x2C | OPC_SPECIAL3, 434 OPC_LHE = 0x2D | OPC_SPECIAL3, 435 OPC_LLE = 0x2E | OPC_SPECIAL3, 436 OPC_LWE = 0x2F | OPC_SPECIAL3, 437 438 /* R6 */ 439 R6_OPC_PREF = 0x35 | OPC_SPECIAL3, 440 R6_OPC_CACHE = 0x25 | OPC_SPECIAL3, 441 R6_OPC_LL = 0x36 | OPC_SPECIAL3, 442 R6_OPC_SC = 0x26 | OPC_SPECIAL3, 443 R6_OPC_LLD = 0x37 | OPC_SPECIAL3, 444 R6_OPC_SCD = 0x27 | OPC_SPECIAL3, 445 }; 446 447 /* Loongson EXT load/store quad word opcodes */ 448 #define MASK_LOONGSON_GSLSQ(op) (MASK_OP_MAJOR(op) | (op & 0x8020)) 449 enum { 450 OPC_GSLQ = 0x0020 | OPC_LWC2, 451 OPC_GSLQC1 = 0x8020 | OPC_LWC2, 452 OPC_GSSHFL = OPC_LWC2, 453 OPC_GSSQ = 0x0020 | OPC_SWC2, 454 OPC_GSSQC1 = 0x8020 | OPC_SWC2, 455 OPC_GSSHFS = OPC_SWC2, 456 }; 457 458 /* Loongson EXT shifted load/store opcodes */ 459 #define MASK_LOONGSON_GSSHFLS(op) (MASK_OP_MAJOR(op) | (op & 0xc03f)) 460 enum { 461 OPC_GSLWLC1 = 0x4 | OPC_GSSHFL, 462 OPC_GSLWRC1 = 0x5 | OPC_GSSHFL, 463 OPC_GSLDLC1 = 0x6 | OPC_GSSHFL, 464 OPC_GSLDRC1 = 0x7 | OPC_GSSHFL, 465 OPC_GSSWLC1 = 0x4 | OPC_GSSHFS, 466 OPC_GSSWRC1 = 0x5 | OPC_GSSHFS, 467 OPC_GSSDLC1 = 0x6 | OPC_GSSHFS, 468 OPC_GSSDRC1 = 0x7 | OPC_GSSHFS, 469 }; 470 471 /* Loongson EXT LDC2/SDC2 opcodes */ 472 #define MASK_LOONGSON_LSDC2(op) (MASK_OP_MAJOR(op) | (op & 0x7)) 473 474 enum { 475 OPC_GSLBX = 0x0 | OPC_LDC2, 476 OPC_GSLHX = 0x1 | OPC_LDC2, 477 OPC_GSLWX = 0x2 | OPC_LDC2, 478 OPC_GSLDX = 0x3 | OPC_LDC2, 479 OPC_GSLWXC1 = 0x6 | OPC_LDC2, 480 OPC_GSLDXC1 = 0x7 | OPC_LDC2, 481 OPC_GSSBX = 0x0 | OPC_SDC2, 482 OPC_GSSHX = 0x1 | OPC_SDC2, 483 OPC_GSSWX = 0x2 | OPC_SDC2, 484 OPC_GSSDX = 0x3 | OPC_SDC2, 485 OPC_GSSWXC1 = 0x6 | OPC_SDC2, 486 OPC_GSSDXC1 = 0x7 | OPC_SDC2, 487 }; 488 489 /* BSHFL opcodes */ 490 #define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 491 492 enum { 493 OPC_WSBH = (0x02 << 6) | OPC_BSHFL, 494 OPC_SEB = (0x10 << 6) | OPC_BSHFL, 495 OPC_SEH = (0x18 << 6) | OPC_BSHFL, 496 OPC_ALIGN = (0x08 << 6) | OPC_BSHFL, /* 010.bp (010.00 to 010.11) */ 497 OPC_ALIGN_1 = (0x09 << 6) | OPC_BSHFL, 498 OPC_ALIGN_2 = (0x0A << 6) | OPC_BSHFL, 499 OPC_ALIGN_3 = (0x0B << 6) | OPC_BSHFL, 500 OPC_BITSWAP = (0x00 << 6) | OPC_BSHFL /* 00000 */ 501 }; 502 503 /* DBSHFL opcodes */ 504 #define MASK_DBSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 505 506 enum { 507 OPC_DSBH = (0x02 << 6) | OPC_DBSHFL, 508 OPC_DSHD = (0x05 << 6) | OPC_DBSHFL, 509 OPC_DALIGN = (0x08 << 6) | OPC_DBSHFL, /* 01.bp (01.000 to 01.111) */ 510 OPC_DALIGN_1 = (0x09 << 6) | OPC_DBSHFL, 511 OPC_DALIGN_2 = (0x0A << 6) | OPC_DBSHFL, 512 OPC_DALIGN_3 = (0x0B << 6) | OPC_DBSHFL, 513 OPC_DALIGN_4 = (0x0C << 6) | OPC_DBSHFL, 514 OPC_DALIGN_5 = (0x0D << 6) | OPC_DBSHFL, 515 OPC_DALIGN_6 = (0x0E << 6) | OPC_DBSHFL, 516 OPC_DALIGN_7 = (0x0F << 6) | OPC_DBSHFL, 517 OPC_DBITSWAP = (0x00 << 6) | OPC_DBSHFL, /* 00000 */ 518 }; 519 520 /* MIPS DSP REGIMM opcodes */ 521 enum { 522 OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM, 523 OPC_BPOSGE64 = (0x1D << 16) | OPC_REGIMM, 524 }; 525 526 #define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 527 /* MIPS DSP Load */ 528 enum { 529 OPC_LBUX = (0x06 << 6) | OPC_LX_DSP, 530 OPC_LHX = (0x04 << 6) | OPC_LX_DSP, 531 OPC_LWX = (0x00 << 6) | OPC_LX_DSP, 532 OPC_LDX = (0x08 << 6) | OPC_LX_DSP, 533 }; 534 535 #define MASK_ADDU_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 536 enum { 537 /* MIPS DSP Arithmetic Sub-class */ 538 OPC_ADDQ_PH = (0x0A << 6) | OPC_ADDU_QB_DSP, 539 OPC_ADDQ_S_PH = (0x0E << 6) | OPC_ADDU_QB_DSP, 540 OPC_ADDQ_S_W = (0x16 << 6) | OPC_ADDU_QB_DSP, 541 OPC_ADDU_QB = (0x00 << 6) | OPC_ADDU_QB_DSP, 542 OPC_ADDU_S_QB = (0x04 << 6) | OPC_ADDU_QB_DSP, 543 OPC_ADDU_PH = (0x08 << 6) | OPC_ADDU_QB_DSP, 544 OPC_ADDU_S_PH = (0x0C << 6) | OPC_ADDU_QB_DSP, 545 OPC_SUBQ_PH = (0x0B << 6) | OPC_ADDU_QB_DSP, 546 OPC_SUBQ_S_PH = (0x0F << 6) | OPC_ADDU_QB_DSP, 547 OPC_SUBQ_S_W = (0x17 << 6) | OPC_ADDU_QB_DSP, 548 OPC_SUBU_QB = (0x01 << 6) | OPC_ADDU_QB_DSP, 549 OPC_SUBU_S_QB = (0x05 << 6) | OPC_ADDU_QB_DSP, 550 OPC_SUBU_PH = (0x09 << 6) | OPC_ADDU_QB_DSP, 551 OPC_SUBU_S_PH = (0x0D << 6) | OPC_ADDU_QB_DSP, 552 OPC_ADDSC = (0x10 << 6) | OPC_ADDU_QB_DSP, 553 OPC_ADDWC = (0x11 << 6) | OPC_ADDU_QB_DSP, 554 OPC_MODSUB = (0x12 << 6) | OPC_ADDU_QB_DSP, 555 OPC_RADDU_W_QB = (0x14 << 6) | OPC_ADDU_QB_DSP, 556 /* MIPS DSP Multiply Sub-class insns */ 557 OPC_MULEU_S_PH_QBL = (0x06 << 6) | OPC_ADDU_QB_DSP, 558 OPC_MULEU_S_PH_QBR = (0x07 << 6) | OPC_ADDU_QB_DSP, 559 OPC_MULQ_RS_PH = (0x1F << 6) | OPC_ADDU_QB_DSP, 560 OPC_MULEQ_S_W_PHL = (0x1C << 6) | OPC_ADDU_QB_DSP, 561 OPC_MULEQ_S_W_PHR = (0x1D << 6) | OPC_ADDU_QB_DSP, 562 OPC_MULQ_S_PH = (0x1E << 6) | OPC_ADDU_QB_DSP, 563 }; 564 565 #define OPC_ADDUH_QB_DSP OPC_MULT_G_2E 566 #define MASK_ADDUH_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 567 enum { 568 /* MIPS DSP Arithmetic Sub-class */ 569 OPC_ADDUH_QB = (0x00 << 6) | OPC_ADDUH_QB_DSP, 570 OPC_ADDUH_R_QB = (0x02 << 6) | OPC_ADDUH_QB_DSP, 571 OPC_ADDQH_PH = (0x08 << 6) | OPC_ADDUH_QB_DSP, 572 OPC_ADDQH_R_PH = (0x0A << 6) | OPC_ADDUH_QB_DSP, 573 OPC_ADDQH_W = (0x10 << 6) | OPC_ADDUH_QB_DSP, 574 OPC_ADDQH_R_W = (0x12 << 6) | OPC_ADDUH_QB_DSP, 575 OPC_SUBUH_QB = (0x01 << 6) | OPC_ADDUH_QB_DSP, 576 OPC_SUBUH_R_QB = (0x03 << 6) | OPC_ADDUH_QB_DSP, 577 OPC_SUBQH_PH = (0x09 << 6) | OPC_ADDUH_QB_DSP, 578 OPC_SUBQH_R_PH = (0x0B << 6) | OPC_ADDUH_QB_DSP, 579 OPC_SUBQH_W = (0x11 << 6) | OPC_ADDUH_QB_DSP, 580 OPC_SUBQH_R_W = (0x13 << 6) | OPC_ADDUH_QB_DSP, 581 /* MIPS DSP Multiply Sub-class insns */ 582 OPC_MUL_PH = (0x0C << 6) | OPC_ADDUH_QB_DSP, 583 OPC_MUL_S_PH = (0x0E << 6) | OPC_ADDUH_QB_DSP, 584 OPC_MULQ_S_W = (0x16 << 6) | OPC_ADDUH_QB_DSP, 585 OPC_MULQ_RS_W = (0x17 << 6) | OPC_ADDUH_QB_DSP, 586 }; 587 588 #define MASK_ABSQ_S_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 589 enum { 590 /* MIPS DSP Arithmetic Sub-class */ 591 OPC_ABSQ_S_QB = (0x01 << 6) | OPC_ABSQ_S_PH_DSP, 592 OPC_ABSQ_S_PH = (0x09 << 6) | OPC_ABSQ_S_PH_DSP, 593 OPC_ABSQ_S_W = (0x11 << 6) | OPC_ABSQ_S_PH_DSP, 594 OPC_PRECEQ_W_PHL = (0x0C << 6) | OPC_ABSQ_S_PH_DSP, 595 OPC_PRECEQ_W_PHR = (0x0D << 6) | OPC_ABSQ_S_PH_DSP, 596 OPC_PRECEQU_PH_QBL = (0x04 << 6) | OPC_ABSQ_S_PH_DSP, 597 OPC_PRECEQU_PH_QBR = (0x05 << 6) | OPC_ABSQ_S_PH_DSP, 598 OPC_PRECEQU_PH_QBLA = (0x06 << 6) | OPC_ABSQ_S_PH_DSP, 599 OPC_PRECEQU_PH_QBRA = (0x07 << 6) | OPC_ABSQ_S_PH_DSP, 600 OPC_PRECEU_PH_QBL = (0x1C << 6) | OPC_ABSQ_S_PH_DSP, 601 OPC_PRECEU_PH_QBR = (0x1D << 6) | OPC_ABSQ_S_PH_DSP, 602 OPC_PRECEU_PH_QBLA = (0x1E << 6) | OPC_ABSQ_S_PH_DSP, 603 OPC_PRECEU_PH_QBRA = (0x1F << 6) | OPC_ABSQ_S_PH_DSP, 604 /* DSP Bit/Manipulation Sub-class */ 605 OPC_BITREV = (0x1B << 6) | OPC_ABSQ_S_PH_DSP, 606 OPC_REPL_QB = (0x02 << 6) | OPC_ABSQ_S_PH_DSP, 607 OPC_REPLV_QB = (0x03 << 6) | OPC_ABSQ_S_PH_DSP, 608 OPC_REPL_PH = (0x0A << 6) | OPC_ABSQ_S_PH_DSP, 609 OPC_REPLV_PH = (0x0B << 6) | OPC_ABSQ_S_PH_DSP, 610 }; 611 612 #define MASK_CMPU_EQ_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 613 enum { 614 /* MIPS DSP Arithmetic Sub-class */ 615 OPC_PRECR_QB_PH = (0x0D << 6) | OPC_CMPU_EQ_QB_DSP, 616 OPC_PRECRQ_QB_PH = (0x0C << 6) | OPC_CMPU_EQ_QB_DSP, 617 OPC_PRECR_SRA_PH_W = (0x1E << 6) | OPC_CMPU_EQ_QB_DSP, 618 OPC_PRECR_SRA_R_PH_W = (0x1F << 6) | OPC_CMPU_EQ_QB_DSP, 619 OPC_PRECRQ_PH_W = (0x14 << 6) | OPC_CMPU_EQ_QB_DSP, 620 OPC_PRECRQ_RS_PH_W = (0x15 << 6) | OPC_CMPU_EQ_QB_DSP, 621 OPC_PRECRQU_S_QB_PH = (0x0F << 6) | OPC_CMPU_EQ_QB_DSP, 622 /* DSP Compare-Pick Sub-class */ 623 OPC_CMPU_EQ_QB = (0x00 << 6) | OPC_CMPU_EQ_QB_DSP, 624 OPC_CMPU_LT_QB = (0x01 << 6) | OPC_CMPU_EQ_QB_DSP, 625 OPC_CMPU_LE_QB = (0x02 << 6) | OPC_CMPU_EQ_QB_DSP, 626 OPC_CMPGU_EQ_QB = (0x04 << 6) | OPC_CMPU_EQ_QB_DSP, 627 OPC_CMPGU_LT_QB = (0x05 << 6) | OPC_CMPU_EQ_QB_DSP, 628 OPC_CMPGU_LE_QB = (0x06 << 6) | OPC_CMPU_EQ_QB_DSP, 629 OPC_CMPGDU_EQ_QB = (0x18 << 6) | OPC_CMPU_EQ_QB_DSP, 630 OPC_CMPGDU_LT_QB = (0x19 << 6) | OPC_CMPU_EQ_QB_DSP, 631 OPC_CMPGDU_LE_QB = (0x1A << 6) | OPC_CMPU_EQ_QB_DSP, 632 OPC_CMP_EQ_PH = (0x08 << 6) | OPC_CMPU_EQ_QB_DSP, 633 OPC_CMP_LT_PH = (0x09 << 6) | OPC_CMPU_EQ_QB_DSP, 634 OPC_CMP_LE_PH = (0x0A << 6) | OPC_CMPU_EQ_QB_DSP, 635 OPC_PICK_QB = (0x03 << 6) | OPC_CMPU_EQ_QB_DSP, 636 OPC_PICK_PH = (0x0B << 6) | OPC_CMPU_EQ_QB_DSP, 637 OPC_PACKRL_PH = (0x0E << 6) | OPC_CMPU_EQ_QB_DSP, 638 }; 639 640 #define MASK_SHLL_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 641 enum { 642 /* MIPS DSP GPR-Based Shift Sub-class */ 643 OPC_SHLL_QB = (0x00 << 6) | OPC_SHLL_QB_DSP, 644 OPC_SHLLV_QB = (0x02 << 6) | OPC_SHLL_QB_DSP, 645 OPC_SHLL_PH = (0x08 << 6) | OPC_SHLL_QB_DSP, 646 OPC_SHLLV_PH = (0x0A << 6) | OPC_SHLL_QB_DSP, 647 OPC_SHLL_S_PH = (0x0C << 6) | OPC_SHLL_QB_DSP, 648 OPC_SHLLV_S_PH = (0x0E << 6) | OPC_SHLL_QB_DSP, 649 OPC_SHLL_S_W = (0x14 << 6) | OPC_SHLL_QB_DSP, 650 OPC_SHLLV_S_W = (0x16 << 6) | OPC_SHLL_QB_DSP, 651 OPC_SHRL_QB = (0x01 << 6) | OPC_SHLL_QB_DSP, 652 OPC_SHRLV_QB = (0x03 << 6) | OPC_SHLL_QB_DSP, 653 OPC_SHRL_PH = (0x19 << 6) | OPC_SHLL_QB_DSP, 654 OPC_SHRLV_PH = (0x1B << 6) | OPC_SHLL_QB_DSP, 655 OPC_SHRA_QB = (0x04 << 6) | OPC_SHLL_QB_DSP, 656 OPC_SHRA_R_QB = (0x05 << 6) | OPC_SHLL_QB_DSP, 657 OPC_SHRAV_QB = (0x06 << 6) | OPC_SHLL_QB_DSP, 658 OPC_SHRAV_R_QB = (0x07 << 6) | OPC_SHLL_QB_DSP, 659 OPC_SHRA_PH = (0x09 << 6) | OPC_SHLL_QB_DSP, 660 OPC_SHRAV_PH = (0x0B << 6) | OPC_SHLL_QB_DSP, 661 OPC_SHRA_R_PH = (0x0D << 6) | OPC_SHLL_QB_DSP, 662 OPC_SHRAV_R_PH = (0x0F << 6) | OPC_SHLL_QB_DSP, 663 OPC_SHRA_R_W = (0x15 << 6) | OPC_SHLL_QB_DSP, 664 OPC_SHRAV_R_W = (0x17 << 6) | OPC_SHLL_QB_DSP, 665 }; 666 667 #define MASK_DPA_W_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 668 enum { 669 /* MIPS DSP Multiply Sub-class insns */ 670 OPC_DPAU_H_QBL = (0x03 << 6) | OPC_DPA_W_PH_DSP, 671 OPC_DPAU_H_QBR = (0x07 << 6) | OPC_DPA_W_PH_DSP, 672 OPC_DPSU_H_QBL = (0x0B << 6) | OPC_DPA_W_PH_DSP, 673 OPC_DPSU_H_QBR = (0x0F << 6) | OPC_DPA_W_PH_DSP, 674 OPC_DPA_W_PH = (0x00 << 6) | OPC_DPA_W_PH_DSP, 675 OPC_DPAX_W_PH = (0x08 << 6) | OPC_DPA_W_PH_DSP, 676 OPC_DPAQ_S_W_PH = (0x04 << 6) | OPC_DPA_W_PH_DSP, 677 OPC_DPAQX_S_W_PH = (0x18 << 6) | OPC_DPA_W_PH_DSP, 678 OPC_DPAQX_SA_W_PH = (0x1A << 6) | OPC_DPA_W_PH_DSP, 679 OPC_DPS_W_PH = (0x01 << 6) | OPC_DPA_W_PH_DSP, 680 OPC_DPSX_W_PH = (0x09 << 6) | OPC_DPA_W_PH_DSP, 681 OPC_DPSQ_S_W_PH = (0x05 << 6) | OPC_DPA_W_PH_DSP, 682 OPC_DPSQX_S_W_PH = (0x19 << 6) | OPC_DPA_W_PH_DSP, 683 OPC_DPSQX_SA_W_PH = (0x1B << 6) | OPC_DPA_W_PH_DSP, 684 OPC_MULSAQ_S_W_PH = (0x06 << 6) | OPC_DPA_W_PH_DSP, 685 OPC_DPAQ_SA_L_W = (0x0C << 6) | OPC_DPA_W_PH_DSP, 686 OPC_DPSQ_SA_L_W = (0x0D << 6) | OPC_DPA_W_PH_DSP, 687 OPC_MAQ_S_W_PHL = (0x14 << 6) | OPC_DPA_W_PH_DSP, 688 OPC_MAQ_S_W_PHR = (0x16 << 6) | OPC_DPA_W_PH_DSP, 689 OPC_MAQ_SA_W_PHL = (0x10 << 6) | OPC_DPA_W_PH_DSP, 690 OPC_MAQ_SA_W_PHR = (0x12 << 6) | OPC_DPA_W_PH_DSP, 691 OPC_MULSA_W_PH = (0x02 << 6) | OPC_DPA_W_PH_DSP, 692 }; 693 694 #define MASK_INSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 695 enum { 696 /* DSP Bit/Manipulation Sub-class */ 697 OPC_INSV = (0x00 << 6) | OPC_INSV_DSP, 698 }; 699 700 #define MASK_APPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 701 enum { 702 /* MIPS DSP Append Sub-class */ 703 OPC_APPEND = (0x00 << 6) | OPC_APPEND_DSP, 704 OPC_PREPEND = (0x01 << 6) | OPC_APPEND_DSP, 705 OPC_BALIGN = (0x10 << 6) | OPC_APPEND_DSP, 706 }; 707 708 #define MASK_EXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 709 enum { 710 /* MIPS DSP Accumulator and DSPControl Access Sub-class */ 711 OPC_EXTR_W = (0x00 << 6) | OPC_EXTR_W_DSP, 712 OPC_EXTR_R_W = (0x04 << 6) | OPC_EXTR_W_DSP, 713 OPC_EXTR_RS_W = (0x06 << 6) | OPC_EXTR_W_DSP, 714 OPC_EXTR_S_H = (0x0E << 6) | OPC_EXTR_W_DSP, 715 OPC_EXTRV_S_H = (0x0F << 6) | OPC_EXTR_W_DSP, 716 OPC_EXTRV_W = (0x01 << 6) | OPC_EXTR_W_DSP, 717 OPC_EXTRV_R_W = (0x05 << 6) | OPC_EXTR_W_DSP, 718 OPC_EXTRV_RS_W = (0x07 << 6) | OPC_EXTR_W_DSP, 719 OPC_EXTP = (0x02 << 6) | OPC_EXTR_W_DSP, 720 OPC_EXTPV = (0x03 << 6) | OPC_EXTR_W_DSP, 721 OPC_EXTPDP = (0x0A << 6) | OPC_EXTR_W_DSP, 722 OPC_EXTPDPV = (0x0B << 6) | OPC_EXTR_W_DSP, 723 OPC_SHILO = (0x1A << 6) | OPC_EXTR_W_DSP, 724 OPC_SHILOV = (0x1B << 6) | OPC_EXTR_W_DSP, 725 OPC_MTHLIP = (0x1F << 6) | OPC_EXTR_W_DSP, 726 OPC_WRDSP = (0x13 << 6) | OPC_EXTR_W_DSP, 727 OPC_RDDSP = (0x12 << 6) | OPC_EXTR_W_DSP, 728 }; 729 730 #define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 731 enum { 732 /* MIPS DSP Arithmetic Sub-class */ 733 OPC_PRECEQ_L_PWL = (0x14 << 6) | OPC_ABSQ_S_QH_DSP, 734 OPC_PRECEQ_L_PWR = (0x15 << 6) | OPC_ABSQ_S_QH_DSP, 735 OPC_PRECEQ_PW_QHL = (0x0C << 6) | OPC_ABSQ_S_QH_DSP, 736 OPC_PRECEQ_PW_QHR = (0x0D << 6) | OPC_ABSQ_S_QH_DSP, 737 OPC_PRECEQ_PW_QHLA = (0x0E << 6) | OPC_ABSQ_S_QH_DSP, 738 OPC_PRECEQ_PW_QHRA = (0x0F << 6) | OPC_ABSQ_S_QH_DSP, 739 OPC_PRECEQU_QH_OBL = (0x04 << 6) | OPC_ABSQ_S_QH_DSP, 740 OPC_PRECEQU_QH_OBR = (0x05 << 6) | OPC_ABSQ_S_QH_DSP, 741 OPC_PRECEQU_QH_OBLA = (0x06 << 6) | OPC_ABSQ_S_QH_DSP, 742 OPC_PRECEQU_QH_OBRA = (0x07 << 6) | OPC_ABSQ_S_QH_DSP, 743 OPC_PRECEU_QH_OBL = (0x1C << 6) | OPC_ABSQ_S_QH_DSP, 744 OPC_PRECEU_QH_OBR = (0x1D << 6) | OPC_ABSQ_S_QH_DSP, 745 OPC_PRECEU_QH_OBLA = (0x1E << 6) | OPC_ABSQ_S_QH_DSP, 746 OPC_PRECEU_QH_OBRA = (0x1F << 6) | OPC_ABSQ_S_QH_DSP, 747 OPC_ABSQ_S_OB = (0x01 << 6) | OPC_ABSQ_S_QH_DSP, 748 OPC_ABSQ_S_PW = (0x11 << 6) | OPC_ABSQ_S_QH_DSP, 749 OPC_ABSQ_S_QH = (0x09 << 6) | OPC_ABSQ_S_QH_DSP, 750 /* DSP Bit/Manipulation Sub-class */ 751 OPC_REPL_OB = (0x02 << 6) | OPC_ABSQ_S_QH_DSP, 752 OPC_REPL_PW = (0x12 << 6) | OPC_ABSQ_S_QH_DSP, 753 OPC_REPL_QH = (0x0A << 6) | OPC_ABSQ_S_QH_DSP, 754 OPC_REPLV_OB = (0x03 << 6) | OPC_ABSQ_S_QH_DSP, 755 OPC_REPLV_PW = (0x13 << 6) | OPC_ABSQ_S_QH_DSP, 756 OPC_REPLV_QH = (0x0B << 6) | OPC_ABSQ_S_QH_DSP, 757 }; 758 759 #define MASK_ADDU_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 760 enum { 761 /* MIPS DSP Multiply Sub-class insns */ 762 OPC_MULEQ_S_PW_QHL = (0x1C << 6) | OPC_ADDU_OB_DSP, 763 OPC_MULEQ_S_PW_QHR = (0x1D << 6) | OPC_ADDU_OB_DSP, 764 OPC_MULEU_S_QH_OBL = (0x06 << 6) | OPC_ADDU_OB_DSP, 765 OPC_MULEU_S_QH_OBR = (0x07 << 6) | OPC_ADDU_OB_DSP, 766 OPC_MULQ_RS_QH = (0x1F << 6) | OPC_ADDU_OB_DSP, 767 /* MIPS DSP Arithmetic Sub-class */ 768 OPC_RADDU_L_OB = (0x14 << 6) | OPC_ADDU_OB_DSP, 769 OPC_SUBQ_PW = (0x13 << 6) | OPC_ADDU_OB_DSP, 770 OPC_SUBQ_S_PW = (0x17 << 6) | OPC_ADDU_OB_DSP, 771 OPC_SUBQ_QH = (0x0B << 6) | OPC_ADDU_OB_DSP, 772 OPC_SUBQ_S_QH = (0x0F << 6) | OPC_ADDU_OB_DSP, 773 OPC_SUBU_OB = (0x01 << 6) | OPC_ADDU_OB_DSP, 774 OPC_SUBU_S_OB = (0x05 << 6) | OPC_ADDU_OB_DSP, 775 OPC_SUBU_QH = (0x09 << 6) | OPC_ADDU_OB_DSP, 776 OPC_SUBU_S_QH = (0x0D << 6) | OPC_ADDU_OB_DSP, 777 OPC_SUBUH_OB = (0x19 << 6) | OPC_ADDU_OB_DSP, 778 OPC_SUBUH_R_OB = (0x1B << 6) | OPC_ADDU_OB_DSP, 779 OPC_ADDQ_PW = (0x12 << 6) | OPC_ADDU_OB_DSP, 780 OPC_ADDQ_S_PW = (0x16 << 6) | OPC_ADDU_OB_DSP, 781 OPC_ADDQ_QH = (0x0A << 6) | OPC_ADDU_OB_DSP, 782 OPC_ADDQ_S_QH = (0x0E << 6) | OPC_ADDU_OB_DSP, 783 OPC_ADDU_OB = (0x00 << 6) | OPC_ADDU_OB_DSP, 784 OPC_ADDU_S_OB = (0x04 << 6) | OPC_ADDU_OB_DSP, 785 OPC_ADDU_QH = (0x08 << 6) | OPC_ADDU_OB_DSP, 786 OPC_ADDU_S_QH = (0x0C << 6) | OPC_ADDU_OB_DSP, 787 OPC_ADDUH_OB = (0x18 << 6) | OPC_ADDU_OB_DSP, 788 OPC_ADDUH_R_OB = (0x1A << 6) | OPC_ADDU_OB_DSP, 789 }; 790 791 #define MASK_CMPU_EQ_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 792 enum { 793 /* DSP Compare-Pick Sub-class */ 794 OPC_CMP_EQ_PW = (0x10 << 6) | OPC_CMPU_EQ_OB_DSP, 795 OPC_CMP_LT_PW = (0x11 << 6) | OPC_CMPU_EQ_OB_DSP, 796 OPC_CMP_LE_PW = (0x12 << 6) | OPC_CMPU_EQ_OB_DSP, 797 OPC_CMP_EQ_QH = (0x08 << 6) | OPC_CMPU_EQ_OB_DSP, 798 OPC_CMP_LT_QH = (0x09 << 6) | OPC_CMPU_EQ_OB_DSP, 799 OPC_CMP_LE_QH = (0x0A << 6) | OPC_CMPU_EQ_OB_DSP, 800 OPC_CMPGDU_EQ_OB = (0x18 << 6) | OPC_CMPU_EQ_OB_DSP, 801 OPC_CMPGDU_LT_OB = (0x19 << 6) | OPC_CMPU_EQ_OB_DSP, 802 OPC_CMPGDU_LE_OB = (0x1A << 6) | OPC_CMPU_EQ_OB_DSP, 803 OPC_CMPGU_EQ_OB = (0x04 << 6) | OPC_CMPU_EQ_OB_DSP, 804 OPC_CMPGU_LT_OB = (0x05 << 6) | OPC_CMPU_EQ_OB_DSP, 805 OPC_CMPGU_LE_OB = (0x06 << 6) | OPC_CMPU_EQ_OB_DSP, 806 OPC_CMPU_EQ_OB = (0x00 << 6) | OPC_CMPU_EQ_OB_DSP, 807 OPC_CMPU_LT_OB = (0x01 << 6) | OPC_CMPU_EQ_OB_DSP, 808 OPC_CMPU_LE_OB = (0x02 << 6) | OPC_CMPU_EQ_OB_DSP, 809 OPC_PACKRL_PW = (0x0E << 6) | OPC_CMPU_EQ_OB_DSP, 810 OPC_PICK_OB = (0x03 << 6) | OPC_CMPU_EQ_OB_DSP, 811 OPC_PICK_PW = (0x13 << 6) | OPC_CMPU_EQ_OB_DSP, 812 OPC_PICK_QH = (0x0B << 6) | OPC_CMPU_EQ_OB_DSP, 813 /* MIPS DSP Arithmetic Sub-class */ 814 OPC_PRECR_OB_QH = (0x0D << 6) | OPC_CMPU_EQ_OB_DSP, 815 OPC_PRECR_SRA_QH_PW = (0x1E << 6) | OPC_CMPU_EQ_OB_DSP, 816 OPC_PRECR_SRA_R_QH_PW = (0x1F << 6) | OPC_CMPU_EQ_OB_DSP, 817 OPC_PRECRQ_OB_QH = (0x0C << 6) | OPC_CMPU_EQ_OB_DSP, 818 OPC_PRECRQ_PW_L = (0x1C << 6) | OPC_CMPU_EQ_OB_DSP, 819 OPC_PRECRQ_QH_PW = (0x14 << 6) | OPC_CMPU_EQ_OB_DSP, 820 OPC_PRECRQ_RS_QH_PW = (0x15 << 6) | OPC_CMPU_EQ_OB_DSP, 821 OPC_PRECRQU_S_OB_QH = (0x0F << 6) | OPC_CMPU_EQ_OB_DSP, 822 }; 823 824 #define MASK_DAPPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 825 enum { 826 /* DSP Append Sub-class */ 827 OPC_DAPPEND = (0x00 << 6) | OPC_DAPPEND_DSP, 828 OPC_PREPENDD = (0x03 << 6) | OPC_DAPPEND_DSP, 829 OPC_PREPENDW = (0x01 << 6) | OPC_DAPPEND_DSP, 830 OPC_DBALIGN = (0x10 << 6) | OPC_DAPPEND_DSP, 831 }; 832 833 #define MASK_DEXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 834 enum { 835 /* MIPS DSP Accumulator and DSPControl Access Sub-class */ 836 OPC_DMTHLIP = (0x1F << 6) | OPC_DEXTR_W_DSP, 837 OPC_DSHILO = (0x1A << 6) | OPC_DEXTR_W_DSP, 838 OPC_DEXTP = (0x02 << 6) | OPC_DEXTR_W_DSP, 839 OPC_DEXTPDP = (0x0A << 6) | OPC_DEXTR_W_DSP, 840 OPC_DEXTPDPV = (0x0B << 6) | OPC_DEXTR_W_DSP, 841 OPC_DEXTPV = (0x03 << 6) | OPC_DEXTR_W_DSP, 842 OPC_DEXTR_L = (0x10 << 6) | OPC_DEXTR_W_DSP, 843 OPC_DEXTR_R_L = (0x14 << 6) | OPC_DEXTR_W_DSP, 844 OPC_DEXTR_RS_L = (0x16 << 6) | OPC_DEXTR_W_DSP, 845 OPC_DEXTR_W = (0x00 << 6) | OPC_DEXTR_W_DSP, 846 OPC_DEXTR_R_W = (0x04 << 6) | OPC_DEXTR_W_DSP, 847 OPC_DEXTR_RS_W = (0x06 << 6) | OPC_DEXTR_W_DSP, 848 OPC_DEXTR_S_H = (0x0E << 6) | OPC_DEXTR_W_DSP, 849 OPC_DEXTRV_L = (0x11 << 6) | OPC_DEXTR_W_DSP, 850 OPC_DEXTRV_R_L = (0x15 << 6) | OPC_DEXTR_W_DSP, 851 OPC_DEXTRV_RS_L = (0x17 << 6) | OPC_DEXTR_W_DSP, 852 OPC_DEXTRV_S_H = (0x0F << 6) | OPC_DEXTR_W_DSP, 853 OPC_DEXTRV_W = (0x01 << 6) | OPC_DEXTR_W_DSP, 854 OPC_DEXTRV_R_W = (0x05 << 6) | OPC_DEXTR_W_DSP, 855 OPC_DEXTRV_RS_W = (0x07 << 6) | OPC_DEXTR_W_DSP, 856 OPC_DSHILOV = (0x1B << 6) | OPC_DEXTR_W_DSP, 857 }; 858 859 #define MASK_DINSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 860 enum { 861 /* DSP Bit/Manipulation Sub-class */ 862 OPC_DINSV = (0x00 << 6) | OPC_DINSV_DSP, 863 }; 864 865 #define MASK_DPAQ_W_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 866 enum { 867 /* MIPS DSP Multiply Sub-class insns */ 868 OPC_DMADD = (0x19 << 6) | OPC_DPAQ_W_QH_DSP, 869 OPC_DMADDU = (0x1D << 6) | OPC_DPAQ_W_QH_DSP, 870 OPC_DMSUB = (0x1B << 6) | OPC_DPAQ_W_QH_DSP, 871 OPC_DMSUBU = (0x1F << 6) | OPC_DPAQ_W_QH_DSP, 872 OPC_DPA_W_QH = (0x00 << 6) | OPC_DPAQ_W_QH_DSP, 873 OPC_DPAQ_S_W_QH = (0x04 << 6) | OPC_DPAQ_W_QH_DSP, 874 OPC_DPAQ_SA_L_PW = (0x0C << 6) | OPC_DPAQ_W_QH_DSP, 875 OPC_DPAU_H_OBL = (0x03 << 6) | OPC_DPAQ_W_QH_DSP, 876 OPC_DPAU_H_OBR = (0x07 << 6) | OPC_DPAQ_W_QH_DSP, 877 OPC_DPS_W_QH = (0x01 << 6) | OPC_DPAQ_W_QH_DSP, 878 OPC_DPSQ_S_W_QH = (0x05 << 6) | OPC_DPAQ_W_QH_DSP, 879 OPC_DPSQ_SA_L_PW = (0x0D << 6) | OPC_DPAQ_W_QH_DSP, 880 OPC_DPSU_H_OBL = (0x0B << 6) | OPC_DPAQ_W_QH_DSP, 881 OPC_DPSU_H_OBR = (0x0F << 6) | OPC_DPAQ_W_QH_DSP, 882 OPC_MAQ_S_L_PWL = (0x1C << 6) | OPC_DPAQ_W_QH_DSP, 883 OPC_MAQ_S_L_PWR = (0x1E << 6) | OPC_DPAQ_W_QH_DSP, 884 OPC_MAQ_S_W_QHLL = (0x14 << 6) | OPC_DPAQ_W_QH_DSP, 885 OPC_MAQ_SA_W_QHLL = (0x10 << 6) | OPC_DPAQ_W_QH_DSP, 886 OPC_MAQ_S_W_QHLR = (0x15 << 6) | OPC_DPAQ_W_QH_DSP, 887 OPC_MAQ_SA_W_QHLR = (0x11 << 6) | OPC_DPAQ_W_QH_DSP, 888 OPC_MAQ_S_W_QHRL = (0x16 << 6) | OPC_DPAQ_W_QH_DSP, 889 OPC_MAQ_SA_W_QHRL = (0x12 << 6) | OPC_DPAQ_W_QH_DSP, 890 OPC_MAQ_S_W_QHRR = (0x17 << 6) | OPC_DPAQ_W_QH_DSP, 891 OPC_MAQ_SA_W_QHRR = (0x13 << 6) | OPC_DPAQ_W_QH_DSP, 892 OPC_MULSAQ_S_L_PW = (0x0E << 6) | OPC_DPAQ_W_QH_DSP, 893 OPC_MULSAQ_S_W_QH = (0x06 << 6) | OPC_DPAQ_W_QH_DSP, 894 }; 895 896 #define MASK_SHLL_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 897 enum { 898 /* MIPS DSP GPR-Based Shift Sub-class */ 899 OPC_SHLL_PW = (0x10 << 6) | OPC_SHLL_OB_DSP, 900 OPC_SHLL_S_PW = (0x14 << 6) | OPC_SHLL_OB_DSP, 901 OPC_SHLLV_OB = (0x02 << 6) | OPC_SHLL_OB_DSP, 902 OPC_SHLLV_PW = (0x12 << 6) | OPC_SHLL_OB_DSP, 903 OPC_SHLLV_S_PW = (0x16 << 6) | OPC_SHLL_OB_DSP, 904 OPC_SHLLV_QH = (0x0A << 6) | OPC_SHLL_OB_DSP, 905 OPC_SHLLV_S_QH = (0x0E << 6) | OPC_SHLL_OB_DSP, 906 OPC_SHRA_PW = (0x11 << 6) | OPC_SHLL_OB_DSP, 907 OPC_SHRA_R_PW = (0x15 << 6) | OPC_SHLL_OB_DSP, 908 OPC_SHRAV_OB = (0x06 << 6) | OPC_SHLL_OB_DSP, 909 OPC_SHRAV_R_OB = (0x07 << 6) | OPC_SHLL_OB_DSP, 910 OPC_SHRAV_PW = (0x13 << 6) | OPC_SHLL_OB_DSP, 911 OPC_SHRAV_R_PW = (0x17 << 6) | OPC_SHLL_OB_DSP, 912 OPC_SHRAV_QH = (0x0B << 6) | OPC_SHLL_OB_DSP, 913 OPC_SHRAV_R_QH = (0x0F << 6) | OPC_SHLL_OB_DSP, 914 OPC_SHRLV_OB = (0x03 << 6) | OPC_SHLL_OB_DSP, 915 OPC_SHRLV_QH = (0x1B << 6) | OPC_SHLL_OB_DSP, 916 OPC_SHLL_OB = (0x00 << 6) | OPC_SHLL_OB_DSP, 917 OPC_SHLL_QH = (0x08 << 6) | OPC_SHLL_OB_DSP, 918 OPC_SHLL_S_QH = (0x0C << 6) | OPC_SHLL_OB_DSP, 919 OPC_SHRA_OB = (0x04 << 6) | OPC_SHLL_OB_DSP, 920 OPC_SHRA_R_OB = (0x05 << 6) | OPC_SHLL_OB_DSP, 921 OPC_SHRA_QH = (0x09 << 6) | OPC_SHLL_OB_DSP, 922 OPC_SHRA_R_QH = (0x0D << 6) | OPC_SHLL_OB_DSP, 923 OPC_SHRL_OB = (0x01 << 6) | OPC_SHLL_OB_DSP, 924 OPC_SHRL_QH = (0x19 << 6) | OPC_SHLL_OB_DSP, 925 }; 926 927 /* Coprocessor 0 (rs field) */ 928 #define MASK_CP0(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21))) 929 930 enum { 931 OPC_MFC0 = (0x00 << 21) | OPC_CP0, 932 OPC_DMFC0 = (0x01 << 21) | OPC_CP0, 933 OPC_MFHC0 = (0x02 << 21) | OPC_CP0, 934 OPC_MTC0 = (0x04 << 21) | OPC_CP0, 935 OPC_DMTC0 = (0x05 << 21) | OPC_CP0, 936 OPC_MTHC0 = (0x06 << 21) | OPC_CP0, 937 OPC_MFTR = (0x08 << 21) | OPC_CP0, 938 OPC_RDPGPR = (0x0A << 21) | OPC_CP0, 939 OPC_MFMC0 = (0x0B << 21) | OPC_CP0, 940 OPC_MTTR = (0x0C << 21) | OPC_CP0, 941 OPC_WRPGPR = (0x0E << 21) | OPC_CP0, 942 OPC_C0 = (0x10 << 21) | OPC_CP0, 943 OPC_C0_1 = (0x11 << 21) | OPC_CP0, 944 OPC_C0_2 = (0x12 << 21) | OPC_CP0, 945 OPC_C0_3 = (0x13 << 21) | OPC_CP0, 946 OPC_C0_4 = (0x14 << 21) | OPC_CP0, 947 OPC_C0_5 = (0x15 << 21) | OPC_CP0, 948 OPC_C0_6 = (0x16 << 21) | OPC_CP0, 949 OPC_C0_7 = (0x17 << 21) | OPC_CP0, 950 OPC_C0_8 = (0x18 << 21) | OPC_CP0, 951 OPC_C0_9 = (0x19 << 21) | OPC_CP0, 952 OPC_C0_A = (0x1A << 21) | OPC_CP0, 953 OPC_C0_B = (0x1B << 21) | OPC_CP0, 954 OPC_C0_C = (0x1C << 21) | OPC_CP0, 955 OPC_C0_D = (0x1D << 21) | OPC_CP0, 956 OPC_C0_E = (0x1E << 21) | OPC_CP0, 957 OPC_C0_F = (0x1F << 21) | OPC_CP0, 958 }; 959 960 /* MFMC0 opcodes */ 961 #define MASK_MFMC0(op) (MASK_CP0(op) | (op & 0xFFFF)) 962 963 enum { 964 OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0, 965 OPC_EMT = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0, 966 OPC_DVPE = 0x01 | (0 << 5) | OPC_MFMC0, 967 OPC_EVPE = 0x01 | (1 << 5) | OPC_MFMC0, 968 OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0, 969 OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0, 970 OPC_DVP = 0x04 | (0 << 3) | (1 << 5) | (0 << 11) | OPC_MFMC0, 971 OPC_EVP = 0x04 | (0 << 3) | (0 << 5) | (0 << 11) | OPC_MFMC0, 972 }; 973 974 /* Coprocessor 0 (with rs == C0) */ 975 #define MASK_C0(op) (MASK_CP0(op) | (op & 0x3F)) 976 977 enum { 978 OPC_TLBR = 0x01 | OPC_C0, 979 OPC_TLBWI = 0x02 | OPC_C0, 980 OPC_TLBINV = 0x03 | OPC_C0, 981 OPC_TLBINVF = 0x04 | OPC_C0, 982 OPC_TLBWR = 0x06 | OPC_C0, 983 OPC_TLBP = 0x08 | OPC_C0, 984 OPC_RFE = 0x10 | OPC_C0, 985 OPC_ERET = 0x18 | OPC_C0, 986 OPC_DERET = 0x1F | OPC_C0, 987 OPC_WAIT = 0x20 | OPC_C0, 988 }; 989 990 #define MASK_CP2(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21))) 991 992 enum { 993 OPC_MFC2 = (0x00 << 21) | OPC_CP2, 994 OPC_DMFC2 = (0x01 << 21) | OPC_CP2, 995 OPC_CFC2 = (0x02 << 21) | OPC_CP2, 996 OPC_MFHC2 = (0x03 << 21) | OPC_CP2, 997 OPC_MTC2 = (0x04 << 21) | OPC_CP2, 998 OPC_DMTC2 = (0x05 << 21) | OPC_CP2, 999 OPC_CTC2 = (0x06 << 21) | OPC_CP2, 1000 OPC_MTHC2 = (0x07 << 21) | OPC_CP2, 1001 OPC_BC2 = (0x08 << 21) | OPC_CP2, 1002 OPC_BC2EQZ = (0x09 << 21) | OPC_CP2, 1003 OPC_BC2NEZ = (0x0D << 21) | OPC_CP2, 1004 }; 1005 1006 #define MASK_LMMI(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F)) 1007 1008 enum { 1009 OPC_PADDSH = (24 << 21) | (0x00) | OPC_CP2, 1010 OPC_PADDUSH = (25 << 21) | (0x00) | OPC_CP2, 1011 OPC_PADDH = (26 << 21) | (0x00) | OPC_CP2, 1012 OPC_PADDW = (27 << 21) | (0x00) | OPC_CP2, 1013 OPC_PADDSB = (28 << 21) | (0x00) | OPC_CP2, 1014 OPC_PADDUSB = (29 << 21) | (0x00) | OPC_CP2, 1015 OPC_PADDB = (30 << 21) | (0x00) | OPC_CP2, 1016 OPC_PADDD = (31 << 21) | (0x00) | OPC_CP2, 1017 1018 OPC_PSUBSH = (24 << 21) | (0x01) | OPC_CP2, 1019 OPC_PSUBUSH = (25 << 21) | (0x01) | OPC_CP2, 1020 OPC_PSUBH = (26 << 21) | (0x01) | OPC_CP2, 1021 OPC_PSUBW = (27 << 21) | (0x01) | OPC_CP2, 1022 OPC_PSUBSB = (28 << 21) | (0x01) | OPC_CP2, 1023 OPC_PSUBUSB = (29 << 21) | (0x01) | OPC_CP2, 1024 OPC_PSUBB = (30 << 21) | (0x01) | OPC_CP2, 1025 OPC_PSUBD = (31 << 21) | (0x01) | OPC_CP2, 1026 1027 OPC_PSHUFH = (24 << 21) | (0x02) | OPC_CP2, 1028 OPC_PACKSSWH = (25 << 21) | (0x02) | OPC_CP2, 1029 OPC_PACKSSHB = (26 << 21) | (0x02) | OPC_CP2, 1030 OPC_PACKUSHB = (27 << 21) | (0x02) | OPC_CP2, 1031 OPC_XOR_CP2 = (28 << 21) | (0x02) | OPC_CP2, 1032 OPC_NOR_CP2 = (29 << 21) | (0x02) | OPC_CP2, 1033 OPC_AND_CP2 = (30 << 21) | (0x02) | OPC_CP2, 1034 OPC_PANDN = (31 << 21) | (0x02) | OPC_CP2, 1035 1036 OPC_PUNPCKLHW = (24 << 21) | (0x03) | OPC_CP2, 1037 OPC_PUNPCKHHW = (25 << 21) | (0x03) | OPC_CP2, 1038 OPC_PUNPCKLBH = (26 << 21) | (0x03) | OPC_CP2, 1039 OPC_PUNPCKHBH = (27 << 21) | (0x03) | OPC_CP2, 1040 OPC_PINSRH_0 = (28 << 21) | (0x03) | OPC_CP2, 1041 OPC_PINSRH_1 = (29 << 21) | (0x03) | OPC_CP2, 1042 OPC_PINSRH_2 = (30 << 21) | (0x03) | OPC_CP2, 1043 OPC_PINSRH_3 = (31 << 21) | (0x03) | OPC_CP2, 1044 1045 OPC_PAVGH = (24 << 21) | (0x08) | OPC_CP2, 1046 OPC_PAVGB = (25 << 21) | (0x08) | OPC_CP2, 1047 OPC_PMAXSH = (26 << 21) | (0x08) | OPC_CP2, 1048 OPC_PMINSH = (27 << 21) | (0x08) | OPC_CP2, 1049 OPC_PMAXUB = (28 << 21) | (0x08) | OPC_CP2, 1050 OPC_PMINUB = (29 << 21) | (0x08) | OPC_CP2, 1051 1052 OPC_PCMPEQW = (24 << 21) | (0x09) | OPC_CP2, 1053 OPC_PCMPGTW = (25 << 21) | (0x09) | OPC_CP2, 1054 OPC_PCMPEQH = (26 << 21) | (0x09) | OPC_CP2, 1055 OPC_PCMPGTH = (27 << 21) | (0x09) | OPC_CP2, 1056 OPC_PCMPEQB = (28 << 21) | (0x09) | OPC_CP2, 1057 OPC_PCMPGTB = (29 << 21) | (0x09) | OPC_CP2, 1058 1059 OPC_PSLLW = (24 << 21) | (0x0A) | OPC_CP2, 1060 OPC_PSLLH = (25 << 21) | (0x0A) | OPC_CP2, 1061 OPC_PMULLH = (26 << 21) | (0x0A) | OPC_CP2, 1062 OPC_PMULHH = (27 << 21) | (0x0A) | OPC_CP2, 1063 OPC_PMULUW = (28 << 21) | (0x0A) | OPC_CP2, 1064 OPC_PMULHUH = (29 << 21) | (0x0A) | OPC_CP2, 1065 1066 OPC_PSRLW = (24 << 21) | (0x0B) | OPC_CP2, 1067 OPC_PSRLH = (25 << 21) | (0x0B) | OPC_CP2, 1068 OPC_PSRAW = (26 << 21) | (0x0B) | OPC_CP2, 1069 OPC_PSRAH = (27 << 21) | (0x0B) | OPC_CP2, 1070 OPC_PUNPCKLWD = (28 << 21) | (0x0B) | OPC_CP2, 1071 OPC_PUNPCKHWD = (29 << 21) | (0x0B) | OPC_CP2, 1072 1073 OPC_ADDU_CP2 = (24 << 21) | (0x0C) | OPC_CP2, 1074 OPC_OR_CP2 = (25 << 21) | (0x0C) | OPC_CP2, 1075 OPC_ADD_CP2 = (26 << 21) | (0x0C) | OPC_CP2, 1076 OPC_DADD_CP2 = (27 << 21) | (0x0C) | OPC_CP2, 1077 OPC_SEQU_CP2 = (28 << 21) | (0x0C) | OPC_CP2, 1078 OPC_SEQ_CP2 = (29 << 21) | (0x0C) | OPC_CP2, 1079 1080 OPC_SUBU_CP2 = (24 << 21) | (0x0D) | OPC_CP2, 1081 OPC_PASUBUB = (25 << 21) | (0x0D) | OPC_CP2, 1082 OPC_SUB_CP2 = (26 << 21) | (0x0D) | OPC_CP2, 1083 OPC_DSUB_CP2 = (27 << 21) | (0x0D) | OPC_CP2, 1084 OPC_SLTU_CP2 = (28 << 21) | (0x0D) | OPC_CP2, 1085 OPC_SLT_CP2 = (29 << 21) | (0x0D) | OPC_CP2, 1086 1087 OPC_SLL_CP2 = (24 << 21) | (0x0E) | OPC_CP2, 1088 OPC_DSLL_CP2 = (25 << 21) | (0x0E) | OPC_CP2, 1089 OPC_PEXTRH = (26 << 21) | (0x0E) | OPC_CP2, 1090 OPC_PMADDHW = (27 << 21) | (0x0E) | OPC_CP2, 1091 OPC_SLEU_CP2 = (28 << 21) | (0x0E) | OPC_CP2, 1092 OPC_SLE_CP2 = (29 << 21) | (0x0E) | OPC_CP2, 1093 1094 OPC_SRL_CP2 = (24 << 21) | (0x0F) | OPC_CP2, 1095 OPC_DSRL_CP2 = (25 << 21) | (0x0F) | OPC_CP2, 1096 OPC_SRA_CP2 = (26 << 21) | (0x0F) | OPC_CP2, 1097 OPC_DSRA_CP2 = (27 << 21) | (0x0F) | OPC_CP2, 1098 OPC_BIADD = (28 << 21) | (0x0F) | OPC_CP2, 1099 OPC_PMOVMSKB = (29 << 21) | (0x0F) | OPC_CP2, 1100 }; 1101 1102 1103 #define MASK_CP3(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) 1104 1105 enum { 1106 OPC_LWXC1 = 0x00 | OPC_CP3, 1107 OPC_LDXC1 = 0x01 | OPC_CP3, 1108 OPC_LUXC1 = 0x05 | OPC_CP3, 1109 OPC_SWXC1 = 0x08 | OPC_CP3, 1110 OPC_SDXC1 = 0x09 | OPC_CP3, 1111 OPC_SUXC1 = 0x0D | OPC_CP3, 1112 OPC_PREFX = 0x0F | OPC_CP3, 1113 OPC_ALNV_PS = 0x1E | OPC_CP3, 1114 OPC_MADD_S = 0x20 | OPC_CP3, 1115 OPC_MADD_D = 0x21 | OPC_CP3, 1116 OPC_MADD_PS = 0x26 | OPC_CP3, 1117 OPC_MSUB_S = 0x28 | OPC_CP3, 1118 OPC_MSUB_D = 0x29 | OPC_CP3, 1119 OPC_MSUB_PS = 0x2E | OPC_CP3, 1120 OPC_NMADD_S = 0x30 | OPC_CP3, 1121 OPC_NMADD_D = 0x31 | OPC_CP3, 1122 OPC_NMADD_PS = 0x36 | OPC_CP3, 1123 OPC_NMSUB_S = 0x38 | OPC_CP3, 1124 OPC_NMSUB_D = 0x39 | OPC_CP3, 1125 OPC_NMSUB_PS = 0x3E | OPC_CP3, 1126 }; 1127 1128 /* 1129 * MMI (MultiMedia Instruction) encodings 1130 * ====================================== 1131 * 1132 * MMI instructions encoding table keys: 1133 * 1134 * * This code is reserved for future use. An attempt to execute it 1135 * causes a Reserved Instruction exception. 1136 * % This code indicates an instruction class. The instruction word 1137 * must be further decoded by examining additional tables that show 1138 * the values for other instruction fields. 1139 * # This code is reserved for the unsupported instructions DMULT, 1140 * DMULTU, DDIV, DDIVU, LL, LLD, SC, SCD, LWC2 and SWC2. An attempt 1141 * to execute it causes a Reserved Instruction exception. 1142 * 1143 * MMI instructions encoded by opcode field (MMI, LQ, SQ): 1144 * 1145 * 31 26 0 1146 * +--------+----------------------------------------+ 1147 * | opcode | | 1148 * +--------+----------------------------------------+ 1149 * 1150 * opcode bits 28..26 1151 * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 1152 * 31..29 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 1153 * -------+-------+-------+-------+-------+-------+-------+-------+------- 1154 * 0 000 |SPECIAL| REGIMM| J | JAL | BEQ | BNE | BLEZ | BGTZ 1155 * 1 001 | ADDI | ADDIU | SLTI | SLTIU | ANDI | ORI | XORI | LUI 1156 * 2 010 | COP0 | COP1 | * | * | BEQL | BNEL | BLEZL | BGTZL 1157 * 3 011 | DADDI | DADDIU| LDL | LDR | MMI% | * | LQ | SQ 1158 * 4 100 | LB | LH | LWL | LW | LBU | LHU | LWR | LWU 1159 * 5 101 | SB | SH | SWL | SW | SDL | SDR | SWR | CACHE 1160 * 6 110 | # | LWC1 | # | PREF | # | LDC1 | # | LD 1161 * 7 111 | # | SWC1 | # | * | # | SDC1 | # | SD 1162 */ 1163 1164 enum { 1165 MMI_OPC_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */ 1166 MMI_OPC_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */ 1167 }; 1168 1169 /* 1170 * MMI instructions with opcode field = MMI: 1171 * 1172 * 31 26 5 0 1173 * +--------+-------------------------------+--------+ 1174 * | MMI | |function| 1175 * +--------+-------------------------------+--------+ 1176 * 1177 * function bits 2..0 1178 * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 1179 * 5..3 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 1180 * -------+-------+-------+-------+-------+-------+-------+-------+------- 1181 * 0 000 | MADD | MADDU | * | * | PLZCW | * | * | * 1182 * 1 001 | MMI0% | MMI2% | * | * | * | * | * | * 1183 * 2 010 | MFHI1 | MTHI1 | MFLO1 | MTLO1 | * | * | * | * 1184 * 3 011 | MULT1 | MULTU1| DIV1 | DIVU1 | * | * | * | * 1185 * 4 100 | MADD1 | MADDU1| * | * | * | * | * | * 1186 * 5 101 | MMI1% | MMI3% | * | * | * | * | * | * 1187 * 6 110 | PMFHL | PMTHL | * | * | PSLLH | * | PSRLH | PSRAH 1188 * 7 111 | * | * | * | * | PSLLW | * | PSRLW | PSRAW 1189 */ 1190 1191 #define MASK_MMI(op) (MASK_OP_MAJOR(op) | ((op) & 0x3F)) 1192 enum { 1193 MMI_OPC_MADD = 0x00 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADD */ 1194 MMI_OPC_MADDU = 0x01 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADDU */ 1195 MMI_OPC_MULT1 = 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MULT */ 1196 MMI_OPC_MULTU1 = 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_MULTU */ 1197 MMI_OPC_DIV1 = 0x1A | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIV */ 1198 MMI_OPC_DIVU1 = 0x1B | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIVU */ 1199 MMI_OPC_MADD1 = 0x20 | MMI_OPC_CLASS_MMI, 1200 MMI_OPC_MADDU1 = 0x21 | MMI_OPC_CLASS_MMI, 1201 }; 1202 1203 /* global register indices */ 1204 TCGv cpu_gpr[32], cpu_PC; 1205 /* 1206 * For CPUs using 128-bit GPR registers, we put the lower halves in cpu_gpr[]) 1207 * and the upper halves in cpu_gpr_hi[]. 1208 */ 1209 TCGv_i64 cpu_gpr_hi[32]; 1210 TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; 1211 static TCGv cpu_dspctrl, btarget; 1212 TCGv bcond; 1213 static TCGv cpu_lladdr, cpu_llval; 1214 static TCGv_i32 hflags; 1215 TCGv_i32 fpu_fcr0, fpu_fcr31; 1216 TCGv_i64 fpu_f64[32]; 1217 1218 #include "exec/gen-icount.h" 1219 1220 static const char regnames_HI[][4] = { 1221 "HI0", "HI1", "HI2", "HI3", 1222 }; 1223 1224 static const char regnames_LO[][4] = { 1225 "LO0", "LO1", "LO2", "LO3", 1226 }; 1227 1228 /* General purpose registers moves. */ 1229 void gen_load_gpr(TCGv t, int reg) 1230 { 1231 assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr)); 1232 if (reg == 0) { 1233 tcg_gen_movi_tl(t, 0); 1234 } else { 1235 tcg_gen_mov_tl(t, cpu_gpr[reg]); 1236 } 1237 } 1238 1239 void gen_store_gpr(TCGv t, int reg) 1240 { 1241 assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr)); 1242 if (reg != 0) { 1243 tcg_gen_mov_tl(cpu_gpr[reg], t); 1244 } 1245 } 1246 1247 #if defined(TARGET_MIPS64) 1248 void gen_load_gpr_hi(TCGv_i64 t, int reg) 1249 { 1250 assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr_hi)); 1251 if (reg == 0) { 1252 tcg_gen_movi_i64(t, 0); 1253 } else { 1254 tcg_gen_mov_i64(t, cpu_gpr_hi[reg]); 1255 } 1256 } 1257 1258 void gen_store_gpr_hi(TCGv_i64 t, int reg) 1259 { 1260 assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr_hi)); 1261 if (reg != 0) { 1262 tcg_gen_mov_i64(cpu_gpr_hi[reg], t); 1263 } 1264 } 1265 #endif /* TARGET_MIPS64 */ 1266 1267 /* Moves to/from shadow registers. */ 1268 static inline void gen_load_srsgpr(int from, int to) 1269 { 1270 TCGv t0 = tcg_temp_new(); 1271 1272 if (from == 0) { 1273 tcg_gen_movi_tl(t0, 0); 1274 } else { 1275 TCGv_i32 t2 = tcg_temp_new_i32(); 1276 TCGv_ptr addr = tcg_temp_new_ptr(); 1277 1278 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl)); 1279 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); 1280 tcg_gen_andi_i32(t2, t2, 0xf); 1281 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32); 1282 tcg_gen_ext_i32_ptr(addr, t2); 1283 tcg_gen_add_ptr(addr, cpu_env, addr); 1284 1285 tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from); 1286 } 1287 gen_store_gpr(t0, to); 1288 } 1289 1290 static inline void gen_store_srsgpr(int from, int to) 1291 { 1292 if (to != 0) { 1293 TCGv t0 = tcg_temp_new(); 1294 TCGv_i32 t2 = tcg_temp_new_i32(); 1295 TCGv_ptr addr = tcg_temp_new_ptr(); 1296 1297 gen_load_gpr(t0, from); 1298 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl)); 1299 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); 1300 tcg_gen_andi_i32(t2, t2, 0xf); 1301 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32); 1302 tcg_gen_ext_i32_ptr(addr, t2); 1303 tcg_gen_add_ptr(addr, cpu_env, addr); 1304 1305 tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to); 1306 } 1307 } 1308 1309 /* Tests */ 1310 static inline void gen_save_pc(target_ulong pc) 1311 { 1312 tcg_gen_movi_tl(cpu_PC, pc); 1313 } 1314 1315 static inline void save_cpu_state(DisasContext *ctx, int do_save_pc) 1316 { 1317 LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags); 1318 if (do_save_pc && ctx->base.pc_next != ctx->saved_pc) { 1319 gen_save_pc(ctx->base.pc_next); 1320 ctx->saved_pc = ctx->base.pc_next; 1321 } 1322 if (ctx->hflags != ctx->saved_hflags) { 1323 tcg_gen_movi_i32(hflags, ctx->hflags); 1324 ctx->saved_hflags = ctx->hflags; 1325 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) { 1326 case MIPS_HFLAG_BR: 1327 break; 1328 case MIPS_HFLAG_BC: 1329 case MIPS_HFLAG_BL: 1330 case MIPS_HFLAG_B: 1331 tcg_gen_movi_tl(btarget, ctx->btarget); 1332 break; 1333 } 1334 } 1335 } 1336 1337 static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx) 1338 { 1339 ctx->saved_hflags = ctx->hflags; 1340 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) { 1341 case MIPS_HFLAG_BR: 1342 break; 1343 case MIPS_HFLAG_BC: 1344 case MIPS_HFLAG_BL: 1345 case MIPS_HFLAG_B: 1346 ctx->btarget = env->btarget; 1347 break; 1348 } 1349 } 1350 1351 void generate_exception_err(DisasContext *ctx, int excp, int err) 1352 { 1353 save_cpu_state(ctx, 1); 1354 gen_helper_raise_exception_err(cpu_env, tcg_constant_i32(excp), 1355 tcg_constant_i32(err)); 1356 ctx->base.is_jmp = DISAS_NORETURN; 1357 } 1358 1359 void generate_exception(DisasContext *ctx, int excp) 1360 { 1361 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 1362 } 1363 1364 void generate_exception_end(DisasContext *ctx, int excp) 1365 { 1366 generate_exception_err(ctx, excp, 0); 1367 } 1368 1369 void generate_exception_break(DisasContext *ctx, int code) 1370 { 1371 #ifdef CONFIG_USER_ONLY 1372 /* Pass the break code along to cpu_loop. */ 1373 tcg_gen_st_i32(tcg_constant_i32(code), cpu_env, 1374 offsetof(CPUMIPSState, error_code)); 1375 #endif 1376 generate_exception_end(ctx, EXCP_BREAK); 1377 } 1378 1379 void gen_reserved_instruction(DisasContext *ctx) 1380 { 1381 generate_exception_end(ctx, EXCP_RI); 1382 } 1383 1384 /* Floating point register moves. */ 1385 void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) 1386 { 1387 if (ctx->hflags & MIPS_HFLAG_FRE) { 1388 generate_exception(ctx, EXCP_RI); 1389 } 1390 tcg_gen_extrl_i64_i32(t, fpu_f64[reg]); 1391 } 1392 1393 void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) 1394 { 1395 TCGv_i64 t64; 1396 if (ctx->hflags & MIPS_HFLAG_FRE) { 1397 generate_exception(ctx, EXCP_RI); 1398 } 1399 t64 = tcg_temp_new_i64(); 1400 tcg_gen_extu_i32_i64(t64, t); 1401 tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 0, 32); 1402 } 1403 1404 static void gen_load_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg) 1405 { 1406 if (ctx->hflags & MIPS_HFLAG_F64) { 1407 tcg_gen_extrh_i64_i32(t, fpu_f64[reg]); 1408 } else { 1409 gen_load_fpr32(ctx, t, reg | 1); 1410 } 1411 } 1412 1413 static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg) 1414 { 1415 if (ctx->hflags & MIPS_HFLAG_F64) { 1416 TCGv_i64 t64 = tcg_temp_new_i64(); 1417 tcg_gen_extu_i32_i64(t64, t); 1418 tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 32, 32); 1419 } else { 1420 gen_store_fpr32(ctx, t, reg | 1); 1421 } 1422 } 1423 1424 void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) 1425 { 1426 if (ctx->hflags & MIPS_HFLAG_F64) { 1427 tcg_gen_mov_i64(t, fpu_f64[reg]); 1428 } else { 1429 tcg_gen_concat32_i64(t, fpu_f64[reg & ~1], fpu_f64[reg | 1]); 1430 } 1431 } 1432 1433 void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) 1434 { 1435 if (ctx->hflags & MIPS_HFLAG_F64) { 1436 tcg_gen_mov_i64(fpu_f64[reg], t); 1437 } else { 1438 TCGv_i64 t0; 1439 tcg_gen_deposit_i64(fpu_f64[reg & ~1], fpu_f64[reg & ~1], t, 0, 32); 1440 t0 = tcg_temp_new_i64(); 1441 tcg_gen_shri_i64(t0, t, 32); 1442 tcg_gen_deposit_i64(fpu_f64[reg | 1], fpu_f64[reg | 1], t0, 0, 32); 1443 } 1444 } 1445 1446 int get_fp_bit(int cc) 1447 { 1448 if (cc) { 1449 return 24 + cc; 1450 } else { 1451 return 23; 1452 } 1453 } 1454 1455 /* Addresses computation */ 1456 void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1) 1457 { 1458 tcg_gen_add_tl(ret, arg0, arg1); 1459 1460 #if defined(TARGET_MIPS64) 1461 if (ctx->hflags & MIPS_HFLAG_AWRAP) { 1462 tcg_gen_ext32s_i64(ret, ret); 1463 } 1464 #endif 1465 } 1466 1467 static inline void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base, 1468 target_long ofs) 1469 { 1470 tcg_gen_addi_tl(ret, base, ofs); 1471 1472 #if defined(TARGET_MIPS64) 1473 if (ctx->hflags & MIPS_HFLAG_AWRAP) { 1474 tcg_gen_ext32s_i64(ret, ret); 1475 } 1476 #endif 1477 } 1478 1479 /* Addresses computation (translation time) */ 1480 static target_long addr_add(DisasContext *ctx, target_long base, 1481 target_long offset) 1482 { 1483 target_long sum = base + offset; 1484 1485 #if defined(TARGET_MIPS64) 1486 if (ctx->hflags & MIPS_HFLAG_AWRAP) { 1487 sum = (int32_t)sum; 1488 } 1489 #endif 1490 return sum; 1491 } 1492 1493 /* Sign-extract the low 32-bits to a target_long. */ 1494 void gen_move_low32(TCGv ret, TCGv_i64 arg) 1495 { 1496 #if defined(TARGET_MIPS64) 1497 tcg_gen_ext32s_i64(ret, arg); 1498 #else 1499 tcg_gen_extrl_i64_i32(ret, arg); 1500 #endif 1501 } 1502 1503 /* Sign-extract the high 32-bits to a target_long. */ 1504 void gen_move_high32(TCGv ret, TCGv_i64 arg) 1505 { 1506 #if defined(TARGET_MIPS64) 1507 tcg_gen_sari_i64(ret, arg, 32); 1508 #else 1509 tcg_gen_extrh_i64_i32(ret, arg); 1510 #endif 1511 } 1512 1513 bool check_cp0_enabled(DisasContext *ctx) 1514 { 1515 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { 1516 generate_exception_end(ctx, EXCP_CpU); 1517 return false; 1518 } 1519 return true; 1520 } 1521 1522 void check_cp1_enabled(DisasContext *ctx) 1523 { 1524 if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) { 1525 generate_exception_err(ctx, EXCP_CpU, 1); 1526 } 1527 } 1528 1529 /* 1530 * Verify that the processor is running with COP1X instructions enabled. 1531 * This is associated with the nabla symbol in the MIPS32 and MIPS64 1532 * opcode tables. 1533 */ 1534 void check_cop1x(DisasContext *ctx) 1535 { 1536 if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) { 1537 gen_reserved_instruction(ctx); 1538 } 1539 } 1540 1541 /* 1542 * Verify that the processor is running with 64-bit floating-point 1543 * operations enabled. 1544 */ 1545 void check_cp1_64bitmode(DisasContext *ctx) 1546 { 1547 if (unlikely(~ctx->hflags & MIPS_HFLAG_F64)) { 1548 gen_reserved_instruction(ctx); 1549 } 1550 } 1551 1552 /* 1553 * Verify if floating point register is valid; an operation is not defined 1554 * if bit 0 of any register specification is set and the FR bit in the 1555 * Status register equals zero, since the register numbers specify an 1556 * even-odd pair of adjacent coprocessor general registers. When the FR bit 1557 * in the Status register equals one, both even and odd register numbers 1558 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers. 1559 * 1560 * Multiple 64 bit wide registers can be checked by calling 1561 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN); 1562 */ 1563 void check_cp1_registers(DisasContext *ctx, int regs) 1564 { 1565 if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) { 1566 gen_reserved_instruction(ctx); 1567 } 1568 } 1569 1570 /* 1571 * Verify that the processor is running with DSP instructions enabled. 1572 * This is enabled by CP0 Status register MX(24) bit. 1573 */ 1574 static inline void check_dsp(DisasContext *ctx) 1575 { 1576 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) { 1577 if (ctx->insn_flags & ASE_DSP) { 1578 generate_exception_end(ctx, EXCP_DSPDIS); 1579 } else { 1580 gen_reserved_instruction(ctx); 1581 } 1582 } 1583 } 1584 1585 static inline void check_dsp_r2(DisasContext *ctx) 1586 { 1587 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R2))) { 1588 if (ctx->insn_flags & ASE_DSP) { 1589 generate_exception_end(ctx, EXCP_DSPDIS); 1590 } else { 1591 gen_reserved_instruction(ctx); 1592 } 1593 } 1594 } 1595 1596 static inline void check_dsp_r3(DisasContext *ctx) 1597 { 1598 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R3))) { 1599 if (ctx->insn_flags & ASE_DSP) { 1600 generate_exception_end(ctx, EXCP_DSPDIS); 1601 } else { 1602 gen_reserved_instruction(ctx); 1603 } 1604 } 1605 } 1606 1607 /* 1608 * This code generates a "reserved instruction" exception if the 1609 * CPU does not support the instruction set corresponding to flags. 1610 */ 1611 void check_insn(DisasContext *ctx, uint64_t flags) 1612 { 1613 if (unlikely(!(ctx->insn_flags & flags))) { 1614 gen_reserved_instruction(ctx); 1615 } 1616 } 1617 1618 /* 1619 * This code generates a "reserved instruction" exception if the 1620 * CPU has corresponding flag set which indicates that the instruction 1621 * has been removed. 1622 */ 1623 static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags) 1624 { 1625 if (unlikely(ctx->insn_flags & flags)) { 1626 gen_reserved_instruction(ctx); 1627 } 1628 } 1629 1630 /* 1631 * The Linux kernel traps certain reserved instruction exceptions to 1632 * emulate the corresponding instructions. QEMU is the kernel in user 1633 * mode, so those traps are emulated by accepting the instructions. 1634 * 1635 * A reserved instruction exception is generated for flagged CPUs if 1636 * QEMU runs in system mode. 1637 */ 1638 static inline void check_insn_opc_user_only(DisasContext *ctx, uint64_t flags) 1639 { 1640 #ifndef CONFIG_USER_ONLY 1641 check_insn_opc_removed(ctx, flags); 1642 #endif 1643 } 1644 1645 /* 1646 * This code generates a "reserved instruction" exception if the 1647 * CPU does not support 64-bit paired-single (PS) floating point data type. 1648 */ 1649 static inline void check_ps(DisasContext *ctx) 1650 { 1651 if (unlikely(!ctx->ps)) { 1652 generate_exception(ctx, EXCP_RI); 1653 } 1654 check_cp1_64bitmode(ctx); 1655 } 1656 1657 /* 1658 * This code generates a "reserved instruction" exception if cpu is not 1659 * 64-bit or 64-bit instructions are not enabled. 1660 */ 1661 void check_mips_64(DisasContext *ctx) 1662 { 1663 if (unlikely((TARGET_LONG_BITS != 64) || !(ctx->hflags & MIPS_HFLAG_64))) { 1664 gen_reserved_instruction(ctx); 1665 } 1666 } 1667 1668 #ifndef CONFIG_USER_ONLY 1669 static inline void check_mvh(DisasContext *ctx) 1670 { 1671 if (unlikely(!ctx->mvh)) { 1672 generate_exception(ctx, EXCP_RI); 1673 } 1674 } 1675 #endif 1676 1677 /* 1678 * This code generates a "reserved instruction" exception if the 1679 * Config5 XNP bit is set. 1680 */ 1681 static inline void check_xnp(DisasContext *ctx) 1682 { 1683 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) { 1684 gen_reserved_instruction(ctx); 1685 } 1686 } 1687 1688 #ifndef CONFIG_USER_ONLY 1689 /* 1690 * This code generates a "reserved instruction" exception if the 1691 * Config3 PW bit is NOT set. 1692 */ 1693 static inline void check_pw(DisasContext *ctx) 1694 { 1695 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_PW)))) { 1696 gen_reserved_instruction(ctx); 1697 } 1698 } 1699 #endif 1700 1701 /* 1702 * This code generates a "reserved instruction" exception if the 1703 * Config3 MT bit is NOT set. 1704 */ 1705 static inline void check_mt(DisasContext *ctx) 1706 { 1707 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { 1708 gen_reserved_instruction(ctx); 1709 } 1710 } 1711 1712 #ifndef CONFIG_USER_ONLY 1713 /* 1714 * This code generates a "coprocessor unusable" exception if CP0 is not 1715 * available, and, if that is not the case, generates a "reserved instruction" 1716 * exception if the Config5 MT bit is NOT set. This is needed for availability 1717 * control of some of MT ASE instructions. 1718 */ 1719 static inline void check_cp0_mt(DisasContext *ctx) 1720 { 1721 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { 1722 generate_exception_end(ctx, EXCP_CpU); 1723 } else { 1724 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { 1725 gen_reserved_instruction(ctx); 1726 } 1727 } 1728 } 1729 #endif 1730 1731 /* 1732 * This code generates a "reserved instruction" exception if the 1733 * Config5 NMS bit is set. 1734 */ 1735 static inline void check_nms(DisasContext *ctx) 1736 { 1737 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) { 1738 gen_reserved_instruction(ctx); 1739 } 1740 } 1741 1742 /* 1743 * This code generates a "reserved instruction" exception if the 1744 * Config5 NMS bit is set, and Config1 DL, Config1 IL, Config2 SL, 1745 * Config2 TL, and Config5 L2C are unset. 1746 */ 1747 static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx) 1748 { 1749 if (unlikely((ctx->CP0_Config5 & (1 << CP0C5_NMS)) && 1750 !(ctx->CP0_Config1 & (1 << CP0C1_DL)) && 1751 !(ctx->CP0_Config1 & (1 << CP0C1_IL)) && 1752 !(ctx->CP0_Config2 & (1 << CP0C2_SL)) && 1753 !(ctx->CP0_Config2 & (1 << CP0C2_TL)) && 1754 !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) { 1755 gen_reserved_instruction(ctx); 1756 } 1757 } 1758 1759 /* 1760 * This code generates a "reserved instruction" exception if the 1761 * Config5 EVA bit is NOT set. 1762 */ 1763 static inline void check_eva(DisasContext *ctx) 1764 { 1765 if (unlikely(!(ctx->CP0_Config5 & (1 << CP0C5_EVA)))) { 1766 gen_reserved_instruction(ctx); 1767 } 1768 } 1769 1770 1771 /* 1772 * Define small wrappers for gen_load_fpr* so that we have a uniform 1773 * calling interface for 32 and 64-bit FPRs. No sense in changing 1774 * all callers for gen_load_fpr32 when we need the CTX parameter for 1775 * this one use. 1776 */ 1777 #define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(ctx, x, y) 1778 #define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y) 1779 #define FOP_CONDS(type, abs, fmt, ifmt, bits) \ 1780 static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \ 1781 int ft, int fs, int cc) \ 1782 { \ 1783 TCGv_i##bits fp0 = tcg_temp_new_i##bits(); \ 1784 TCGv_i##bits fp1 = tcg_temp_new_i##bits(); \ 1785 switch (ifmt) { \ 1786 case FMT_PS: \ 1787 check_ps(ctx); \ 1788 break; \ 1789 case FMT_D: \ 1790 if (abs) { \ 1791 check_cop1x(ctx); \ 1792 } \ 1793 check_cp1_registers(ctx, fs | ft); \ 1794 break; \ 1795 case FMT_S: \ 1796 if (abs) { \ 1797 check_cop1x(ctx); \ 1798 } \ 1799 break; \ 1800 } \ 1801 gen_ldcmp_fpr##bits(ctx, fp0, fs); \ 1802 gen_ldcmp_fpr##bits(ctx, fp1, ft); \ 1803 switch (n) { \ 1804 case 0: \ 1805 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); \ 1806 break; \ 1807 case 1: \ 1808 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); \ 1809 break; \ 1810 case 2: \ 1811 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); \ 1812 break; \ 1813 case 3: \ 1814 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); \ 1815 break; \ 1816 case 4: \ 1817 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); \ 1818 break; \ 1819 case 5: \ 1820 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); \ 1821 break; \ 1822 case 6: \ 1823 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); \ 1824 break; \ 1825 case 7: \ 1826 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); \ 1827 break; \ 1828 case 8: \ 1829 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); \ 1830 break; \ 1831 case 9: \ 1832 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); \ 1833 break; \ 1834 case 10: \ 1835 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); \ 1836 break; \ 1837 case 11: \ 1838 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); \ 1839 break; \ 1840 case 12: \ 1841 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); \ 1842 break; \ 1843 case 13: \ 1844 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); \ 1845 break; \ 1846 case 14: \ 1847 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); \ 1848 break; \ 1849 case 15: \ 1850 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); \ 1851 break; \ 1852 default: \ 1853 abort(); \ 1854 } \ 1855 } 1856 1857 FOP_CONDS(, 0, d, FMT_D, 64) 1858 FOP_CONDS(abs, 1, d, FMT_D, 64) 1859 FOP_CONDS(, 0, s, FMT_S, 32) 1860 FOP_CONDS(abs, 1, s, FMT_S, 32) 1861 FOP_CONDS(, 0, ps, FMT_PS, 64) 1862 FOP_CONDS(abs, 1, ps, FMT_PS, 64) 1863 #undef FOP_CONDS 1864 1865 #define FOP_CONDNS(fmt, ifmt, bits, STORE) \ 1866 static inline void gen_r6_cmp_ ## fmt(DisasContext *ctx, int n, \ 1867 int ft, int fs, int fd) \ 1868 { \ 1869 TCGv_i ## bits fp0 = tcg_temp_new_i ## bits(); \ 1870 TCGv_i ## bits fp1 = tcg_temp_new_i ## bits(); \ 1871 if (ifmt == FMT_D) { \ 1872 check_cp1_registers(ctx, fs | ft | fd); \ 1873 } \ 1874 gen_ldcmp_fpr ## bits(ctx, fp0, fs); \ 1875 gen_ldcmp_fpr ## bits(ctx, fp1, ft); \ 1876 switch (n) { \ 1877 case 0: \ 1878 gen_helper_r6_cmp_ ## fmt ## _af(fp0, cpu_env, fp0, fp1); \ 1879 break; \ 1880 case 1: \ 1881 gen_helper_r6_cmp_ ## fmt ## _un(fp0, cpu_env, fp0, fp1); \ 1882 break; \ 1883 case 2: \ 1884 gen_helper_r6_cmp_ ## fmt ## _eq(fp0, cpu_env, fp0, fp1); \ 1885 break; \ 1886 case 3: \ 1887 gen_helper_r6_cmp_ ## fmt ## _ueq(fp0, cpu_env, fp0, fp1); \ 1888 break; \ 1889 case 4: \ 1890 gen_helper_r6_cmp_ ## fmt ## _lt(fp0, cpu_env, fp0, fp1); \ 1891 break; \ 1892 case 5: \ 1893 gen_helper_r6_cmp_ ## fmt ## _ult(fp0, cpu_env, fp0, fp1); \ 1894 break; \ 1895 case 6: \ 1896 gen_helper_r6_cmp_ ## fmt ## _le(fp0, cpu_env, fp0, fp1); \ 1897 break; \ 1898 case 7: \ 1899 gen_helper_r6_cmp_ ## fmt ## _ule(fp0, cpu_env, fp0, fp1); \ 1900 break; \ 1901 case 8: \ 1902 gen_helper_r6_cmp_ ## fmt ## _saf(fp0, cpu_env, fp0, fp1); \ 1903 break; \ 1904 case 9: \ 1905 gen_helper_r6_cmp_ ## fmt ## _sun(fp0, cpu_env, fp0, fp1); \ 1906 break; \ 1907 case 10: \ 1908 gen_helper_r6_cmp_ ## fmt ## _seq(fp0, cpu_env, fp0, fp1); \ 1909 break; \ 1910 case 11: \ 1911 gen_helper_r6_cmp_ ## fmt ## _sueq(fp0, cpu_env, fp0, fp1); \ 1912 break; \ 1913 case 12: \ 1914 gen_helper_r6_cmp_ ## fmt ## _slt(fp0, cpu_env, fp0, fp1); \ 1915 break; \ 1916 case 13: \ 1917 gen_helper_r6_cmp_ ## fmt ## _sult(fp0, cpu_env, fp0, fp1); \ 1918 break; \ 1919 case 14: \ 1920 gen_helper_r6_cmp_ ## fmt ## _sle(fp0, cpu_env, fp0, fp1); \ 1921 break; \ 1922 case 15: \ 1923 gen_helper_r6_cmp_ ## fmt ## _sule(fp0, cpu_env, fp0, fp1); \ 1924 break; \ 1925 case 17: \ 1926 gen_helper_r6_cmp_ ## fmt ## _or(fp0, cpu_env, fp0, fp1); \ 1927 break; \ 1928 case 18: \ 1929 gen_helper_r6_cmp_ ## fmt ## _une(fp0, cpu_env, fp0, fp1); \ 1930 break; \ 1931 case 19: \ 1932 gen_helper_r6_cmp_ ## fmt ## _ne(fp0, cpu_env, fp0, fp1); \ 1933 break; \ 1934 case 25: \ 1935 gen_helper_r6_cmp_ ## fmt ## _sor(fp0, cpu_env, fp0, fp1); \ 1936 break; \ 1937 case 26: \ 1938 gen_helper_r6_cmp_ ## fmt ## _sune(fp0, cpu_env, fp0, fp1); \ 1939 break; \ 1940 case 27: \ 1941 gen_helper_r6_cmp_ ## fmt ## _sne(fp0, cpu_env, fp0, fp1); \ 1942 break; \ 1943 default: \ 1944 abort(); \ 1945 } \ 1946 STORE; \ 1947 } 1948 1949 FOP_CONDNS(d, FMT_D, 64, gen_store_fpr64(ctx, fp0, fd)) 1950 FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, fd)) 1951 #undef FOP_CONDNS 1952 #undef gen_ldcmp_fpr32 1953 #undef gen_ldcmp_fpr64 1954 1955 /* load/store instructions. */ 1956 #ifdef CONFIG_USER_ONLY 1957 #define OP_LD_ATOMIC(insn, memop) \ 1958 static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \ 1959 DisasContext *ctx) \ 1960 { \ 1961 TCGv t0 = tcg_temp_new(); \ 1962 tcg_gen_mov_tl(t0, arg1); \ 1963 tcg_gen_qemu_ld_tl(ret, arg1, ctx->mem_idx, memop); \ 1964 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \ 1965 tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); \ 1966 } 1967 #else 1968 #define OP_LD_ATOMIC(insn, fname) \ 1969 static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \ 1970 DisasContext *ctx) \ 1971 { \ 1972 gen_helper_##insn(ret, cpu_env, arg1, tcg_constant_i32(mem_idx)); \ 1973 } 1974 #endif 1975 OP_LD_ATOMIC(ll, MO_TESL); 1976 #if defined(TARGET_MIPS64) 1977 OP_LD_ATOMIC(lld, MO_TEUQ); 1978 #endif 1979 #undef OP_LD_ATOMIC 1980 1981 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset) 1982 { 1983 if (base == 0) { 1984 tcg_gen_movi_tl(addr, offset); 1985 } else if (offset == 0) { 1986 gen_load_gpr(addr, base); 1987 } else { 1988 tcg_gen_movi_tl(addr, offset); 1989 gen_op_addr_add(ctx, addr, cpu_gpr[base], addr); 1990 } 1991 } 1992 1993 static target_ulong pc_relative_pc(DisasContext *ctx) 1994 { 1995 target_ulong pc = ctx->base.pc_next; 1996 1997 if (ctx->hflags & MIPS_HFLAG_BMASK) { 1998 int branch_bytes = ctx->hflags & MIPS_HFLAG_BDS16 ? 2 : 4; 1999 2000 pc -= branch_bytes; 2001 } 2002 2003 pc &= ~(target_ulong)3; 2004 return pc; 2005 } 2006 2007 /* LWL or LDL, depending on MemOp. */ 2008 static void gen_lxl(DisasContext *ctx, TCGv reg, TCGv addr, 2009 int mem_idx, MemOp mop) 2010 { 2011 int sizem1 = memop_size(mop) - 1; 2012 TCGv t0 = tcg_temp_new(); 2013 TCGv t1 = tcg_temp_new(); 2014 2015 /* 2016 * Do a byte access to possibly trigger a page 2017 * fault with the unaligned address. 2018 */ 2019 tcg_gen_qemu_ld_tl(t1, addr, mem_idx, MO_UB); 2020 tcg_gen_andi_tl(t1, addr, sizem1); 2021 if (!cpu_is_bigendian(ctx)) { 2022 tcg_gen_xori_tl(t1, t1, sizem1); 2023 } 2024 tcg_gen_shli_tl(t1, t1, 3); 2025 tcg_gen_andi_tl(t0, addr, ~sizem1); 2026 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mop); 2027 tcg_gen_shl_tl(t0, t0, t1); 2028 tcg_gen_shl_tl(t1, tcg_constant_tl(-1), t1); 2029 tcg_gen_andc_tl(t1, reg, t1); 2030 tcg_gen_or_tl(reg, t0, t1); 2031 } 2032 2033 /* LWR or LDR, depending on MemOp. */ 2034 static void gen_lxr(DisasContext *ctx, TCGv reg, TCGv addr, 2035 int mem_idx, MemOp mop) 2036 { 2037 int size = memop_size(mop); 2038 int sizem1 = size - 1; 2039 TCGv t0 = tcg_temp_new(); 2040 TCGv t1 = tcg_temp_new(); 2041 2042 /* 2043 * Do a byte access to possibly trigger a page 2044 * fault with the unaligned address. 2045 */ 2046 tcg_gen_qemu_ld_tl(t1, addr, mem_idx, MO_UB); 2047 tcg_gen_andi_tl(t1, addr, sizem1); 2048 if (cpu_is_bigendian(ctx)) { 2049 tcg_gen_xori_tl(t1, t1, sizem1); 2050 } 2051 tcg_gen_shli_tl(t1, t1, 3); 2052 tcg_gen_andi_tl(t0, addr, ~sizem1); 2053 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mop); 2054 tcg_gen_shr_tl(t0, t0, t1); 2055 tcg_gen_xori_tl(t1, t1, size * 8 - 1); 2056 tcg_gen_shl_tl(t1, tcg_constant_tl(~1), t1); 2057 tcg_gen_and_tl(t1, reg, t1); 2058 tcg_gen_or_tl(reg, t0, t1); 2059 } 2060 2061 /* Load */ 2062 static void gen_ld(DisasContext *ctx, uint32_t opc, 2063 int rt, int base, int offset) 2064 { 2065 TCGv t0, t1; 2066 int mem_idx = ctx->mem_idx; 2067 2068 if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F | 2069 INSN_LOONGSON3A)) { 2070 /* 2071 * Loongson CPU uses a load to zero register for prefetch. 2072 * We emulate it as a NOP. On other CPU we must perform the 2073 * actual memory access. 2074 */ 2075 return; 2076 } 2077 2078 t0 = tcg_temp_new(); 2079 gen_base_offset_addr(ctx, t0, base, offset); 2080 2081 switch (opc) { 2082 #if defined(TARGET_MIPS64) 2083 case OPC_LWU: 2084 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL | 2085 ctx->default_tcg_memop_mask); 2086 gen_store_gpr(t0, rt); 2087 break; 2088 case OPC_LD: 2089 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ | 2090 ctx->default_tcg_memop_mask); 2091 gen_store_gpr(t0, rt); 2092 break; 2093 case OPC_LLD: 2094 case R6_OPC_LLD: 2095 op_ld_lld(t0, t0, mem_idx, ctx); 2096 gen_store_gpr(t0, rt); 2097 break; 2098 case OPC_LDL: 2099 t1 = tcg_temp_new(); 2100 gen_load_gpr(t1, rt); 2101 gen_lxl(ctx, t1, t0, mem_idx, MO_TEUQ); 2102 gen_store_gpr(t1, rt); 2103 break; 2104 case OPC_LDR: 2105 t1 = tcg_temp_new(); 2106 gen_load_gpr(t1, rt); 2107 gen_lxr(ctx, t1, t0, mem_idx, MO_TEUQ); 2108 gen_store_gpr(t1, rt); 2109 break; 2110 case OPC_LDPC: 2111 t1 = tcg_constant_tl(pc_relative_pc(ctx)); 2112 gen_op_addr_add(ctx, t0, t0, t1); 2113 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ); 2114 gen_store_gpr(t0, rt); 2115 break; 2116 #endif 2117 case OPC_LWPC: 2118 t1 = tcg_constant_tl(pc_relative_pc(ctx)); 2119 gen_op_addr_add(ctx, t0, t0, t1); 2120 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL); 2121 gen_store_gpr(t0, rt); 2122 break; 2123 case OPC_LWE: 2124 mem_idx = MIPS_HFLAG_UM; 2125 /* fall through */ 2126 case OPC_LW: 2127 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL | 2128 ctx->default_tcg_memop_mask); 2129 gen_store_gpr(t0, rt); 2130 break; 2131 case OPC_LHE: 2132 mem_idx = MIPS_HFLAG_UM; 2133 /* fall through */ 2134 case OPC_LH: 2135 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESW | 2136 ctx->default_tcg_memop_mask); 2137 gen_store_gpr(t0, rt); 2138 break; 2139 case OPC_LHUE: 2140 mem_idx = MIPS_HFLAG_UM; 2141 /* fall through */ 2142 case OPC_LHU: 2143 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUW | 2144 ctx->default_tcg_memop_mask); 2145 gen_store_gpr(t0, rt); 2146 break; 2147 case OPC_LBE: 2148 mem_idx = MIPS_HFLAG_UM; 2149 /* fall through */ 2150 case OPC_LB: 2151 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_SB); 2152 gen_store_gpr(t0, rt); 2153 break; 2154 case OPC_LBUE: 2155 mem_idx = MIPS_HFLAG_UM; 2156 /* fall through */ 2157 case OPC_LBU: 2158 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_UB); 2159 gen_store_gpr(t0, rt); 2160 break; 2161 case OPC_LWLE: 2162 mem_idx = MIPS_HFLAG_UM; 2163 /* fall through */ 2164 case OPC_LWL: 2165 t1 = tcg_temp_new(); 2166 gen_load_gpr(t1, rt); 2167 gen_lxl(ctx, t1, t0, mem_idx, MO_TEUL); 2168 tcg_gen_ext32s_tl(t1, t1); 2169 gen_store_gpr(t1, rt); 2170 break; 2171 case OPC_LWRE: 2172 mem_idx = MIPS_HFLAG_UM; 2173 /* fall through */ 2174 case OPC_LWR: 2175 t1 = tcg_temp_new(); 2176 gen_load_gpr(t1, rt); 2177 gen_lxr(ctx, t1, t0, mem_idx, MO_TEUL); 2178 tcg_gen_ext32s_tl(t1, t1); 2179 gen_store_gpr(t1, rt); 2180 break; 2181 case OPC_LLE: 2182 mem_idx = MIPS_HFLAG_UM; 2183 /* fall through */ 2184 case OPC_LL: 2185 case R6_OPC_LL: 2186 op_ld_ll(t0, t0, mem_idx, ctx); 2187 gen_store_gpr(t0, rt); 2188 break; 2189 } 2190 } 2191 2192 /* Store */ 2193 static void gen_st(DisasContext *ctx, uint32_t opc, int rt, 2194 int base, int offset) 2195 { 2196 TCGv t0 = tcg_temp_new(); 2197 TCGv t1 = tcg_temp_new(); 2198 int mem_idx = ctx->mem_idx; 2199 2200 gen_base_offset_addr(ctx, t0, base, offset); 2201 gen_load_gpr(t1, rt); 2202 switch (opc) { 2203 #if defined(TARGET_MIPS64) 2204 case OPC_SD: 2205 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUQ | 2206 ctx->default_tcg_memop_mask); 2207 break; 2208 case OPC_SDL: 2209 gen_helper_0e2i(sdl, t1, t0, mem_idx); 2210 break; 2211 case OPC_SDR: 2212 gen_helper_0e2i(sdr, t1, t0, mem_idx); 2213 break; 2214 #endif 2215 case OPC_SWE: 2216 mem_idx = MIPS_HFLAG_UM; 2217 /* fall through */ 2218 case OPC_SW: 2219 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUL | 2220 ctx->default_tcg_memop_mask); 2221 break; 2222 case OPC_SHE: 2223 mem_idx = MIPS_HFLAG_UM; 2224 /* fall through */ 2225 case OPC_SH: 2226 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUW | 2227 ctx->default_tcg_memop_mask); 2228 break; 2229 case OPC_SBE: 2230 mem_idx = MIPS_HFLAG_UM; 2231 /* fall through */ 2232 case OPC_SB: 2233 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_8); 2234 break; 2235 case OPC_SWLE: 2236 mem_idx = MIPS_HFLAG_UM; 2237 /* fall through */ 2238 case OPC_SWL: 2239 gen_helper_0e2i(swl, t1, t0, mem_idx); 2240 break; 2241 case OPC_SWRE: 2242 mem_idx = MIPS_HFLAG_UM; 2243 /* fall through */ 2244 case OPC_SWR: 2245 gen_helper_0e2i(swr, t1, t0, mem_idx); 2246 break; 2247 } 2248 } 2249 2250 2251 /* Store conditional */ 2252 static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset, 2253 MemOp tcg_mo, bool eva) 2254 { 2255 TCGv addr, t0, val; 2256 TCGLabel *l1 = gen_new_label(); 2257 TCGLabel *done = gen_new_label(); 2258 2259 t0 = tcg_temp_new(); 2260 addr = tcg_temp_new(); 2261 /* compare the address against that of the preceding LL */ 2262 gen_base_offset_addr(ctx, addr, base, offset); 2263 tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1); 2264 tcg_gen_movi_tl(t0, 0); 2265 gen_store_gpr(t0, rt); 2266 tcg_gen_br(done); 2267 2268 gen_set_label(l1); 2269 /* generate cmpxchg */ 2270 val = tcg_temp_new(); 2271 gen_load_gpr(val, rt); 2272 tcg_gen_atomic_cmpxchg_tl(t0, cpu_lladdr, cpu_llval, val, 2273 eva ? MIPS_HFLAG_UM : ctx->mem_idx, tcg_mo); 2274 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_llval); 2275 gen_store_gpr(t0, rt); 2276 2277 gen_set_label(done); 2278 } 2279 2280 /* Load and store */ 2281 static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft, 2282 TCGv t0) 2283 { 2284 /* 2285 * Don't do NOP if destination is zero: we must perform the actual 2286 * memory access. 2287 */ 2288 switch (opc) { 2289 case OPC_LWC1: 2290 { 2291 TCGv_i32 fp0 = tcg_temp_new_i32(); 2292 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL | 2293 ctx->default_tcg_memop_mask); 2294 gen_store_fpr32(ctx, fp0, ft); 2295 } 2296 break; 2297 case OPC_SWC1: 2298 { 2299 TCGv_i32 fp0 = tcg_temp_new_i32(); 2300 gen_load_fpr32(ctx, fp0, ft); 2301 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL | 2302 ctx->default_tcg_memop_mask); 2303 } 2304 break; 2305 case OPC_LDC1: 2306 { 2307 TCGv_i64 fp0 = tcg_temp_new_i64(); 2308 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ | 2309 ctx->default_tcg_memop_mask); 2310 gen_store_fpr64(ctx, fp0, ft); 2311 } 2312 break; 2313 case OPC_SDC1: 2314 { 2315 TCGv_i64 fp0 = tcg_temp_new_i64(); 2316 gen_load_fpr64(ctx, fp0, ft); 2317 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ | 2318 ctx->default_tcg_memop_mask); 2319 } 2320 break; 2321 default: 2322 MIPS_INVAL("flt_ldst"); 2323 gen_reserved_instruction(ctx); 2324 break; 2325 } 2326 } 2327 2328 static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt, 2329 int rs, int16_t imm) 2330 { 2331 TCGv t0 = tcg_temp_new(); 2332 2333 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { 2334 check_cp1_enabled(ctx); 2335 switch (op) { 2336 case OPC_LDC1: 2337 case OPC_SDC1: 2338 check_insn(ctx, ISA_MIPS2); 2339 /* Fallthrough */ 2340 default: 2341 gen_base_offset_addr(ctx, t0, rs, imm); 2342 gen_flt_ldst(ctx, op, rt, t0); 2343 } 2344 } else { 2345 generate_exception_err(ctx, EXCP_CpU, 1); 2346 } 2347 } 2348 2349 /* Arithmetic with immediate operand */ 2350 static void gen_arith_imm(DisasContext *ctx, uint32_t opc, 2351 int rt, int rs, int imm) 2352 { 2353 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ 2354 2355 if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) { 2356 /* 2357 * If no destination, treat it as a NOP. 2358 * For addi, we must generate the overflow exception when needed. 2359 */ 2360 return; 2361 } 2362 switch (opc) { 2363 case OPC_ADDI: 2364 { 2365 TCGv t0 = tcg_temp_new(); 2366 TCGv t1 = tcg_temp_new(); 2367 TCGv t2 = tcg_temp_new(); 2368 TCGLabel *l1 = gen_new_label(); 2369 2370 gen_load_gpr(t1, rs); 2371 tcg_gen_addi_tl(t0, t1, uimm); 2372 tcg_gen_ext32s_tl(t0, t0); 2373 2374 tcg_gen_xori_tl(t1, t1, ~uimm); 2375 tcg_gen_xori_tl(t2, t0, uimm); 2376 tcg_gen_and_tl(t1, t1, t2); 2377 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2378 /* operands of same sign, result different sign */ 2379 generate_exception(ctx, EXCP_OVERFLOW); 2380 gen_set_label(l1); 2381 tcg_gen_ext32s_tl(t0, t0); 2382 gen_store_gpr(t0, rt); 2383 } 2384 break; 2385 case OPC_ADDIU: 2386 if (rs != 0) { 2387 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); 2388 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 2389 } else { 2390 tcg_gen_movi_tl(cpu_gpr[rt], uimm); 2391 } 2392 break; 2393 #if defined(TARGET_MIPS64) 2394 case OPC_DADDI: 2395 { 2396 TCGv t0 = tcg_temp_new(); 2397 TCGv t1 = tcg_temp_new(); 2398 TCGv t2 = tcg_temp_new(); 2399 TCGLabel *l1 = gen_new_label(); 2400 2401 gen_load_gpr(t1, rs); 2402 tcg_gen_addi_tl(t0, t1, uimm); 2403 2404 tcg_gen_xori_tl(t1, t1, ~uimm); 2405 tcg_gen_xori_tl(t2, t0, uimm); 2406 tcg_gen_and_tl(t1, t1, t2); 2407 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2408 /* operands of same sign, result different sign */ 2409 generate_exception(ctx, EXCP_OVERFLOW); 2410 gen_set_label(l1); 2411 gen_store_gpr(t0, rt); 2412 } 2413 break; 2414 case OPC_DADDIU: 2415 if (rs != 0) { 2416 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); 2417 } else { 2418 tcg_gen_movi_tl(cpu_gpr[rt], uimm); 2419 } 2420 break; 2421 #endif 2422 } 2423 } 2424 2425 /* Logic with immediate operand */ 2426 static void gen_logic_imm(DisasContext *ctx, uint32_t opc, 2427 int rt, int rs, int16_t imm) 2428 { 2429 target_ulong uimm; 2430 2431 if (rt == 0) { 2432 /* If no destination, treat it as a NOP. */ 2433 return; 2434 } 2435 uimm = (uint16_t)imm; 2436 switch (opc) { 2437 case OPC_ANDI: 2438 if (likely(rs != 0)) { 2439 tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); 2440 } else { 2441 tcg_gen_movi_tl(cpu_gpr[rt], 0); 2442 } 2443 break; 2444 case OPC_ORI: 2445 if (rs != 0) { 2446 tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); 2447 } else { 2448 tcg_gen_movi_tl(cpu_gpr[rt], uimm); 2449 } 2450 break; 2451 case OPC_XORI: 2452 if (likely(rs != 0)) { 2453 tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); 2454 } else { 2455 tcg_gen_movi_tl(cpu_gpr[rt], uimm); 2456 } 2457 break; 2458 case OPC_LUI: 2459 if (rs != 0 && (ctx->insn_flags & ISA_MIPS_R6)) { 2460 /* OPC_AUI */ 2461 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm << 16); 2462 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 2463 } else { 2464 tcg_gen_movi_tl(cpu_gpr[rt], imm << 16); 2465 } 2466 break; 2467 2468 default: 2469 break; 2470 } 2471 } 2472 2473 /* Set on less than with immediate operand */ 2474 static void gen_slt_imm(DisasContext *ctx, uint32_t opc, 2475 int rt, int rs, int16_t imm) 2476 { 2477 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ 2478 TCGv t0; 2479 2480 if (rt == 0) { 2481 /* If no destination, treat it as a NOP. */ 2482 return; 2483 } 2484 t0 = tcg_temp_new(); 2485 gen_load_gpr(t0, rs); 2486 switch (opc) { 2487 case OPC_SLTI: 2488 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr[rt], t0, uimm); 2489 break; 2490 case OPC_SLTIU: 2491 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rt], t0, uimm); 2492 break; 2493 } 2494 } 2495 2496 /* Shifts with immediate operand */ 2497 static void gen_shift_imm(DisasContext *ctx, uint32_t opc, 2498 int rt, int rs, int16_t imm) 2499 { 2500 target_ulong uimm = ((uint16_t)imm) & 0x1f; 2501 TCGv t0; 2502 2503 if (rt == 0) { 2504 /* If no destination, treat it as a NOP. */ 2505 return; 2506 } 2507 2508 t0 = tcg_temp_new(); 2509 gen_load_gpr(t0, rs); 2510 switch (opc) { 2511 case OPC_SLL: 2512 tcg_gen_shli_tl(t0, t0, uimm); 2513 tcg_gen_ext32s_tl(cpu_gpr[rt], t0); 2514 break; 2515 case OPC_SRA: 2516 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm); 2517 break; 2518 case OPC_SRL: 2519 if (uimm != 0) { 2520 tcg_gen_ext32u_tl(t0, t0); 2521 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm); 2522 } else { 2523 tcg_gen_ext32s_tl(cpu_gpr[rt], t0); 2524 } 2525 break; 2526 case OPC_ROTR: 2527 if (uimm != 0) { 2528 TCGv_i32 t1 = tcg_temp_new_i32(); 2529 2530 tcg_gen_trunc_tl_i32(t1, t0); 2531 tcg_gen_rotri_i32(t1, t1, uimm); 2532 tcg_gen_ext_i32_tl(cpu_gpr[rt], t1); 2533 } else { 2534 tcg_gen_ext32s_tl(cpu_gpr[rt], t0); 2535 } 2536 break; 2537 #if defined(TARGET_MIPS64) 2538 case OPC_DSLL: 2539 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm); 2540 break; 2541 case OPC_DSRA: 2542 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm); 2543 break; 2544 case OPC_DSRL: 2545 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm); 2546 break; 2547 case OPC_DROTR: 2548 if (uimm != 0) { 2549 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm); 2550 } else { 2551 tcg_gen_mov_tl(cpu_gpr[rt], t0); 2552 } 2553 break; 2554 case OPC_DSLL32: 2555 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm + 32); 2556 break; 2557 case OPC_DSRA32: 2558 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm + 32); 2559 break; 2560 case OPC_DSRL32: 2561 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32); 2562 break; 2563 case OPC_DROTR32: 2564 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm + 32); 2565 break; 2566 #endif 2567 } 2568 } 2569 2570 /* Arithmetic */ 2571 static void gen_arith(DisasContext *ctx, uint32_t opc, 2572 int rd, int rs, int rt) 2573 { 2574 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB 2575 && opc != OPC_DADD && opc != OPC_DSUB) { 2576 /* 2577 * If no destination, treat it as a NOP. 2578 * For add & sub, we must generate the overflow exception when needed. 2579 */ 2580 return; 2581 } 2582 2583 switch (opc) { 2584 case OPC_ADD: 2585 { 2586 TCGv t0 = tcg_temp_new(); 2587 TCGv t1 = tcg_temp_new(); 2588 TCGv t2 = tcg_temp_new(); 2589 TCGLabel *l1 = gen_new_label(); 2590 2591 gen_load_gpr(t1, rs); 2592 gen_load_gpr(t2, rt); 2593 tcg_gen_add_tl(t0, t1, t2); 2594 tcg_gen_ext32s_tl(t0, t0); 2595 tcg_gen_xor_tl(t1, t1, t2); 2596 tcg_gen_xor_tl(t2, t0, t2); 2597 tcg_gen_andc_tl(t1, t2, t1); 2598 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2599 /* operands of same sign, result different sign */ 2600 generate_exception(ctx, EXCP_OVERFLOW); 2601 gen_set_label(l1); 2602 gen_store_gpr(t0, rd); 2603 } 2604 break; 2605 case OPC_ADDU: 2606 if (rs != 0 && rt != 0) { 2607 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2608 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 2609 } else if (rs == 0 && rt != 0) { 2610 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); 2611 } else if (rs != 0 && rt == 0) { 2612 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2613 } else { 2614 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2615 } 2616 break; 2617 case OPC_SUB: 2618 { 2619 TCGv t0 = tcg_temp_new(); 2620 TCGv t1 = tcg_temp_new(); 2621 TCGv t2 = tcg_temp_new(); 2622 TCGLabel *l1 = gen_new_label(); 2623 2624 gen_load_gpr(t1, rs); 2625 gen_load_gpr(t2, rt); 2626 tcg_gen_sub_tl(t0, t1, t2); 2627 tcg_gen_ext32s_tl(t0, t0); 2628 tcg_gen_xor_tl(t2, t1, t2); 2629 tcg_gen_xor_tl(t1, t0, t1); 2630 tcg_gen_and_tl(t1, t1, t2); 2631 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2632 /* 2633 * operands of different sign, first operand and the result 2634 * of different sign 2635 */ 2636 generate_exception(ctx, EXCP_OVERFLOW); 2637 gen_set_label(l1); 2638 gen_store_gpr(t0, rd); 2639 } 2640 break; 2641 case OPC_SUBU: 2642 if (rs != 0 && rt != 0) { 2643 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2644 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 2645 } else if (rs == 0 && rt != 0) { 2646 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]); 2647 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 2648 } else if (rs != 0 && rt == 0) { 2649 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2650 } else { 2651 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2652 } 2653 break; 2654 #if defined(TARGET_MIPS64) 2655 case OPC_DADD: 2656 { 2657 TCGv t0 = tcg_temp_new(); 2658 TCGv t1 = tcg_temp_new(); 2659 TCGv t2 = tcg_temp_new(); 2660 TCGLabel *l1 = gen_new_label(); 2661 2662 gen_load_gpr(t1, rs); 2663 gen_load_gpr(t2, rt); 2664 tcg_gen_add_tl(t0, t1, t2); 2665 tcg_gen_xor_tl(t1, t1, t2); 2666 tcg_gen_xor_tl(t2, t0, t2); 2667 tcg_gen_andc_tl(t1, t2, t1); 2668 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2669 /* operands of same sign, result different sign */ 2670 generate_exception(ctx, EXCP_OVERFLOW); 2671 gen_set_label(l1); 2672 gen_store_gpr(t0, rd); 2673 } 2674 break; 2675 case OPC_DADDU: 2676 if (rs != 0 && rt != 0) { 2677 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2678 } else if (rs == 0 && rt != 0) { 2679 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); 2680 } else if (rs != 0 && rt == 0) { 2681 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2682 } else { 2683 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2684 } 2685 break; 2686 case OPC_DSUB: 2687 { 2688 TCGv t0 = tcg_temp_new(); 2689 TCGv t1 = tcg_temp_new(); 2690 TCGv t2 = tcg_temp_new(); 2691 TCGLabel *l1 = gen_new_label(); 2692 2693 gen_load_gpr(t1, rs); 2694 gen_load_gpr(t2, rt); 2695 tcg_gen_sub_tl(t0, t1, t2); 2696 tcg_gen_xor_tl(t2, t1, t2); 2697 tcg_gen_xor_tl(t1, t0, t1); 2698 tcg_gen_and_tl(t1, t1, t2); 2699 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2700 /* 2701 * Operands of different sign, first operand and result different 2702 * sign. 2703 */ 2704 generate_exception(ctx, EXCP_OVERFLOW); 2705 gen_set_label(l1); 2706 gen_store_gpr(t0, rd); 2707 } 2708 break; 2709 case OPC_DSUBU: 2710 if (rs != 0 && rt != 0) { 2711 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2712 } else if (rs == 0 && rt != 0) { 2713 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]); 2714 } else if (rs != 0 && rt == 0) { 2715 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2716 } else { 2717 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2718 } 2719 break; 2720 #endif 2721 case OPC_MUL: 2722 if (likely(rs != 0 && rt != 0)) { 2723 tcg_gen_mul_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2724 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 2725 } else { 2726 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2727 } 2728 break; 2729 } 2730 } 2731 2732 /* Conditional move */ 2733 static void gen_cond_move(DisasContext *ctx, uint32_t opc, 2734 int rd, int rs, int rt) 2735 { 2736 TCGv t0, t1, t2; 2737 2738 if (rd == 0) { 2739 /* If no destination, treat it as a NOP. */ 2740 return; 2741 } 2742 2743 t0 = tcg_temp_new(); 2744 gen_load_gpr(t0, rt); 2745 t1 = tcg_constant_tl(0); 2746 t2 = tcg_temp_new(); 2747 gen_load_gpr(t2, rs); 2748 switch (opc) { 2749 case OPC_MOVN: 2750 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]); 2751 break; 2752 case OPC_MOVZ: 2753 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]); 2754 break; 2755 case OPC_SELNEZ: 2756 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, t1); 2757 break; 2758 case OPC_SELEQZ: 2759 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, t1); 2760 break; 2761 } 2762 } 2763 2764 /* Logic */ 2765 static void gen_logic(DisasContext *ctx, uint32_t opc, 2766 int rd, int rs, int rt) 2767 { 2768 if (rd == 0) { 2769 /* If no destination, treat it as a NOP. */ 2770 return; 2771 } 2772 2773 switch (opc) { 2774 case OPC_AND: 2775 if (likely(rs != 0 && rt != 0)) { 2776 tcg_gen_and_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2777 } else { 2778 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2779 } 2780 break; 2781 case OPC_NOR: 2782 if (rs != 0 && rt != 0) { 2783 tcg_gen_nor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2784 } else if (rs == 0 && rt != 0) { 2785 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rt]); 2786 } else if (rs != 0 && rt == 0) { 2787 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rs]); 2788 } else { 2789 tcg_gen_movi_tl(cpu_gpr[rd], ~((target_ulong)0)); 2790 } 2791 break; 2792 case OPC_OR: 2793 if (likely(rs != 0 && rt != 0)) { 2794 tcg_gen_or_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2795 } else if (rs == 0 && rt != 0) { 2796 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); 2797 } else if (rs != 0 && rt == 0) { 2798 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2799 } else { 2800 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2801 } 2802 break; 2803 case OPC_XOR: 2804 if (likely(rs != 0 && rt != 0)) { 2805 tcg_gen_xor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2806 } else if (rs == 0 && rt != 0) { 2807 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); 2808 } else if (rs != 0 && rt == 0) { 2809 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2810 } else { 2811 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2812 } 2813 break; 2814 } 2815 } 2816 2817 /* Set on lower than */ 2818 static void gen_slt(DisasContext *ctx, uint32_t opc, 2819 int rd, int rs, int rt) 2820 { 2821 TCGv t0, t1; 2822 2823 if (rd == 0) { 2824 /* If no destination, treat it as a NOP. */ 2825 return; 2826 } 2827 2828 t0 = tcg_temp_new(); 2829 t1 = tcg_temp_new(); 2830 gen_load_gpr(t0, rs); 2831 gen_load_gpr(t1, rt); 2832 switch (opc) { 2833 case OPC_SLT: 2834 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr[rd], t0, t1); 2835 break; 2836 case OPC_SLTU: 2837 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr[rd], t0, t1); 2838 break; 2839 } 2840 } 2841 2842 /* Shifts */ 2843 static void gen_shift(DisasContext *ctx, uint32_t opc, 2844 int rd, int rs, int rt) 2845 { 2846 TCGv t0, t1; 2847 2848 if (rd == 0) { 2849 /* 2850 * If no destination, treat it as a NOP. 2851 * For add & sub, we must generate the overflow exception when needed. 2852 */ 2853 return; 2854 } 2855 2856 t0 = tcg_temp_new(); 2857 t1 = tcg_temp_new(); 2858 gen_load_gpr(t0, rs); 2859 gen_load_gpr(t1, rt); 2860 switch (opc) { 2861 case OPC_SLLV: 2862 tcg_gen_andi_tl(t0, t0, 0x1f); 2863 tcg_gen_shl_tl(t0, t1, t0); 2864 tcg_gen_ext32s_tl(cpu_gpr[rd], t0); 2865 break; 2866 case OPC_SRAV: 2867 tcg_gen_andi_tl(t0, t0, 0x1f); 2868 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0); 2869 break; 2870 case OPC_SRLV: 2871 tcg_gen_ext32u_tl(t1, t1); 2872 tcg_gen_andi_tl(t0, t0, 0x1f); 2873 tcg_gen_shr_tl(t0, t1, t0); 2874 tcg_gen_ext32s_tl(cpu_gpr[rd], t0); 2875 break; 2876 case OPC_ROTRV: 2877 { 2878 TCGv_i32 t2 = tcg_temp_new_i32(); 2879 TCGv_i32 t3 = tcg_temp_new_i32(); 2880 2881 tcg_gen_trunc_tl_i32(t2, t0); 2882 tcg_gen_trunc_tl_i32(t3, t1); 2883 tcg_gen_andi_i32(t2, t2, 0x1f); 2884 tcg_gen_rotr_i32(t2, t3, t2); 2885 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); 2886 } 2887 break; 2888 #if defined(TARGET_MIPS64) 2889 case OPC_DSLLV: 2890 tcg_gen_andi_tl(t0, t0, 0x3f); 2891 tcg_gen_shl_tl(cpu_gpr[rd], t1, t0); 2892 break; 2893 case OPC_DSRAV: 2894 tcg_gen_andi_tl(t0, t0, 0x3f); 2895 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0); 2896 break; 2897 case OPC_DSRLV: 2898 tcg_gen_andi_tl(t0, t0, 0x3f); 2899 tcg_gen_shr_tl(cpu_gpr[rd], t1, t0); 2900 break; 2901 case OPC_DROTRV: 2902 tcg_gen_andi_tl(t0, t0, 0x3f); 2903 tcg_gen_rotr_tl(cpu_gpr[rd], t1, t0); 2904 break; 2905 #endif 2906 } 2907 } 2908 2909 /* Arithmetic on HI/LO registers */ 2910 static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) 2911 { 2912 if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) { 2913 /* Treat as NOP. */ 2914 return; 2915 } 2916 2917 if (acc != 0) { 2918 check_dsp(ctx); 2919 } 2920 2921 switch (opc) { 2922 case OPC_MFHI: 2923 #if defined(TARGET_MIPS64) 2924 if (acc != 0) { 2925 tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]); 2926 } else 2927 #endif 2928 { 2929 tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[acc]); 2930 } 2931 break; 2932 case OPC_MFLO: 2933 #if defined(TARGET_MIPS64) 2934 if (acc != 0) { 2935 tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]); 2936 } else 2937 #endif 2938 { 2939 tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[acc]); 2940 } 2941 break; 2942 case OPC_MTHI: 2943 if (reg != 0) { 2944 #if defined(TARGET_MIPS64) 2945 if (acc != 0) { 2946 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_gpr[reg]); 2947 } else 2948 #endif 2949 { 2950 tcg_gen_mov_tl(cpu_HI[acc], cpu_gpr[reg]); 2951 } 2952 } else { 2953 tcg_gen_movi_tl(cpu_HI[acc], 0); 2954 } 2955 break; 2956 case OPC_MTLO: 2957 if (reg != 0) { 2958 #if defined(TARGET_MIPS64) 2959 if (acc != 0) { 2960 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_gpr[reg]); 2961 } else 2962 #endif 2963 { 2964 tcg_gen_mov_tl(cpu_LO[acc], cpu_gpr[reg]); 2965 } 2966 } else { 2967 tcg_gen_movi_tl(cpu_LO[acc], 0); 2968 } 2969 break; 2970 } 2971 } 2972 2973 static inline void gen_r6_ld(target_long addr, int reg, int memidx, 2974 MemOp memop) 2975 { 2976 TCGv t0 = tcg_temp_new(); 2977 tcg_gen_qemu_ld_tl(t0, tcg_constant_tl(addr), memidx, memop); 2978 gen_store_gpr(t0, reg); 2979 } 2980 2981 static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc, 2982 int rs) 2983 { 2984 target_long offset; 2985 target_long addr; 2986 2987 switch (MASK_OPC_PCREL_TOP2BITS(opc)) { 2988 case OPC_ADDIUPC: 2989 if (rs != 0) { 2990 offset = sextract32(ctx->opcode << 2, 0, 21); 2991 addr = addr_add(ctx, pc, offset); 2992 tcg_gen_movi_tl(cpu_gpr[rs], addr); 2993 } 2994 break; 2995 case R6_OPC_LWPC: 2996 offset = sextract32(ctx->opcode << 2, 0, 21); 2997 addr = addr_add(ctx, pc, offset); 2998 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TESL); 2999 break; 3000 #if defined(TARGET_MIPS64) 3001 case OPC_LWUPC: 3002 check_mips_64(ctx); 3003 offset = sextract32(ctx->opcode << 2, 0, 21); 3004 addr = addr_add(ctx, pc, offset); 3005 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUL); 3006 break; 3007 #endif 3008 default: 3009 switch (MASK_OPC_PCREL_TOP5BITS(opc)) { 3010 case OPC_AUIPC: 3011 if (rs != 0) { 3012 offset = sextract32(ctx->opcode, 0, 16) << 16; 3013 addr = addr_add(ctx, pc, offset); 3014 tcg_gen_movi_tl(cpu_gpr[rs], addr); 3015 } 3016 break; 3017 case OPC_ALUIPC: 3018 if (rs != 0) { 3019 offset = sextract32(ctx->opcode, 0, 16) << 16; 3020 addr = ~0xFFFF & addr_add(ctx, pc, offset); 3021 tcg_gen_movi_tl(cpu_gpr[rs], addr); 3022 } 3023 break; 3024 #if defined(TARGET_MIPS64) 3025 case R6_OPC_LDPC: /* bits 16 and 17 are part of immediate */ 3026 case R6_OPC_LDPC + (1 << 16): 3027 case R6_OPC_LDPC + (2 << 16): 3028 case R6_OPC_LDPC + (3 << 16): 3029 check_mips_64(ctx); 3030 offset = sextract32(ctx->opcode << 3, 0, 21); 3031 addr = addr_add(ctx, (pc & ~0x7), offset); 3032 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUQ); 3033 break; 3034 #endif 3035 default: 3036 MIPS_INVAL("OPC_PCREL"); 3037 gen_reserved_instruction(ctx); 3038 break; 3039 } 3040 break; 3041 } 3042 } 3043 3044 static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) 3045 { 3046 TCGv t0, t1; 3047 3048 if (rd == 0) { 3049 /* Treat as NOP. */ 3050 return; 3051 } 3052 3053 t0 = tcg_temp_new(); 3054 t1 = tcg_temp_new(); 3055 3056 gen_load_gpr(t0, rs); 3057 gen_load_gpr(t1, rt); 3058 3059 switch (opc) { 3060 case R6_OPC_DIV: 3061 { 3062 TCGv t2 = tcg_temp_new(); 3063 TCGv t3 = tcg_temp_new(); 3064 tcg_gen_ext32s_tl(t0, t0); 3065 tcg_gen_ext32s_tl(t1, t1); 3066 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); 3067 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); 3068 tcg_gen_and_tl(t2, t2, t3); 3069 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3070 tcg_gen_or_tl(t2, t2, t3); 3071 tcg_gen_movi_tl(t3, 0); 3072 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3073 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); 3074 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3075 } 3076 break; 3077 case R6_OPC_MOD: 3078 { 3079 TCGv t2 = tcg_temp_new(); 3080 TCGv t3 = tcg_temp_new(); 3081 tcg_gen_ext32s_tl(t0, t0); 3082 tcg_gen_ext32s_tl(t1, t1); 3083 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); 3084 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); 3085 tcg_gen_and_tl(t2, t2, t3); 3086 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3087 tcg_gen_or_tl(t2, t2, t3); 3088 tcg_gen_movi_tl(t3, 0); 3089 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3090 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); 3091 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3092 } 3093 break; 3094 case R6_OPC_DIVU: 3095 { 3096 TCGv t2 = tcg_constant_tl(0); 3097 TCGv t3 = tcg_constant_tl(1); 3098 tcg_gen_ext32u_tl(t0, t0); 3099 tcg_gen_ext32u_tl(t1, t1); 3100 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3101 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); 3102 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3103 } 3104 break; 3105 case R6_OPC_MODU: 3106 { 3107 TCGv t2 = tcg_constant_tl(0); 3108 TCGv t3 = tcg_constant_tl(1); 3109 tcg_gen_ext32u_tl(t0, t0); 3110 tcg_gen_ext32u_tl(t1, t1); 3111 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3112 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); 3113 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3114 } 3115 break; 3116 case R6_OPC_MUL: 3117 { 3118 TCGv_i32 t2 = tcg_temp_new_i32(); 3119 TCGv_i32 t3 = tcg_temp_new_i32(); 3120 tcg_gen_trunc_tl_i32(t2, t0); 3121 tcg_gen_trunc_tl_i32(t3, t1); 3122 tcg_gen_mul_i32(t2, t2, t3); 3123 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); 3124 } 3125 break; 3126 case R6_OPC_MUH: 3127 { 3128 TCGv_i32 t2 = tcg_temp_new_i32(); 3129 TCGv_i32 t3 = tcg_temp_new_i32(); 3130 tcg_gen_trunc_tl_i32(t2, t0); 3131 tcg_gen_trunc_tl_i32(t3, t1); 3132 tcg_gen_muls2_i32(t2, t3, t2, t3); 3133 tcg_gen_ext_i32_tl(cpu_gpr[rd], t3); 3134 } 3135 break; 3136 case R6_OPC_MULU: 3137 { 3138 TCGv_i32 t2 = tcg_temp_new_i32(); 3139 TCGv_i32 t3 = tcg_temp_new_i32(); 3140 tcg_gen_trunc_tl_i32(t2, t0); 3141 tcg_gen_trunc_tl_i32(t3, t1); 3142 tcg_gen_mul_i32(t2, t2, t3); 3143 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); 3144 } 3145 break; 3146 case R6_OPC_MUHU: 3147 { 3148 TCGv_i32 t2 = tcg_temp_new_i32(); 3149 TCGv_i32 t3 = tcg_temp_new_i32(); 3150 tcg_gen_trunc_tl_i32(t2, t0); 3151 tcg_gen_trunc_tl_i32(t3, t1); 3152 tcg_gen_mulu2_i32(t2, t3, t2, t3); 3153 tcg_gen_ext_i32_tl(cpu_gpr[rd], t3); 3154 } 3155 break; 3156 #if defined(TARGET_MIPS64) 3157 case R6_OPC_DDIV: 3158 { 3159 TCGv t2 = tcg_temp_new(); 3160 TCGv t3 = tcg_temp_new(); 3161 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); 3162 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); 3163 tcg_gen_and_tl(t2, t2, t3); 3164 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3165 tcg_gen_or_tl(t2, t2, t3); 3166 tcg_gen_movi_tl(t3, 0); 3167 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3168 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); 3169 } 3170 break; 3171 case R6_OPC_DMOD: 3172 { 3173 TCGv t2 = tcg_temp_new(); 3174 TCGv t3 = tcg_temp_new(); 3175 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); 3176 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); 3177 tcg_gen_and_tl(t2, t2, t3); 3178 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3179 tcg_gen_or_tl(t2, t2, t3); 3180 tcg_gen_movi_tl(t3, 0); 3181 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3182 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); 3183 } 3184 break; 3185 case R6_OPC_DDIVU: 3186 { 3187 TCGv t2 = tcg_constant_tl(0); 3188 TCGv t3 = tcg_constant_tl(1); 3189 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3190 tcg_gen_divu_i64(cpu_gpr[rd], t0, t1); 3191 } 3192 break; 3193 case R6_OPC_DMODU: 3194 { 3195 TCGv t2 = tcg_constant_tl(0); 3196 TCGv t3 = tcg_constant_tl(1); 3197 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3198 tcg_gen_remu_i64(cpu_gpr[rd], t0, t1); 3199 } 3200 break; 3201 case R6_OPC_DMUL: 3202 tcg_gen_mul_i64(cpu_gpr[rd], t0, t1); 3203 break; 3204 case R6_OPC_DMUH: 3205 { 3206 TCGv t2 = tcg_temp_new(); 3207 tcg_gen_muls2_i64(t2, cpu_gpr[rd], t0, t1); 3208 } 3209 break; 3210 case R6_OPC_DMULU: 3211 tcg_gen_mul_i64(cpu_gpr[rd], t0, t1); 3212 break; 3213 case R6_OPC_DMUHU: 3214 { 3215 TCGv t2 = tcg_temp_new(); 3216 tcg_gen_mulu2_i64(t2, cpu_gpr[rd], t0, t1); 3217 } 3218 break; 3219 #endif 3220 default: 3221 MIPS_INVAL("r6 mul/div"); 3222 gen_reserved_instruction(ctx); 3223 break; 3224 } 3225 } 3226 3227 #if defined(TARGET_MIPS64) 3228 static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt) 3229 { 3230 TCGv t0, t1; 3231 3232 t0 = tcg_temp_new(); 3233 t1 = tcg_temp_new(); 3234 3235 gen_load_gpr(t0, rs); 3236 gen_load_gpr(t1, rt); 3237 3238 switch (opc) { 3239 case MMI_OPC_DIV1: 3240 { 3241 TCGv t2 = tcg_temp_new(); 3242 TCGv t3 = tcg_temp_new(); 3243 tcg_gen_ext32s_tl(t0, t0); 3244 tcg_gen_ext32s_tl(t1, t1); 3245 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); 3246 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); 3247 tcg_gen_and_tl(t2, t2, t3); 3248 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3249 tcg_gen_or_tl(t2, t2, t3); 3250 tcg_gen_movi_tl(t3, 0); 3251 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3252 tcg_gen_div_tl(cpu_LO[1], t0, t1); 3253 tcg_gen_rem_tl(cpu_HI[1], t0, t1); 3254 tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]); 3255 tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]); 3256 } 3257 break; 3258 case MMI_OPC_DIVU1: 3259 { 3260 TCGv t2 = tcg_constant_tl(0); 3261 TCGv t3 = tcg_constant_tl(1); 3262 tcg_gen_ext32u_tl(t0, t0); 3263 tcg_gen_ext32u_tl(t1, t1); 3264 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3265 tcg_gen_divu_tl(cpu_LO[1], t0, t1); 3266 tcg_gen_remu_tl(cpu_HI[1], t0, t1); 3267 tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]); 3268 tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]); 3269 } 3270 break; 3271 default: 3272 MIPS_INVAL("div1 TX79"); 3273 gen_reserved_instruction(ctx); 3274 break; 3275 } 3276 } 3277 #endif 3278 3279 static void gen_muldiv(DisasContext *ctx, uint32_t opc, 3280 int acc, int rs, int rt) 3281 { 3282 TCGv t0, t1; 3283 3284 t0 = tcg_temp_new(); 3285 t1 = tcg_temp_new(); 3286 3287 gen_load_gpr(t0, rs); 3288 gen_load_gpr(t1, rt); 3289 3290 if (acc != 0) { 3291 check_dsp(ctx); 3292 } 3293 3294 switch (opc) { 3295 case OPC_DIV: 3296 { 3297 TCGv t2 = tcg_temp_new(); 3298 TCGv t3 = tcg_temp_new(); 3299 tcg_gen_ext32s_tl(t0, t0); 3300 tcg_gen_ext32s_tl(t1, t1); 3301 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); 3302 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); 3303 tcg_gen_and_tl(t2, t2, t3); 3304 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3305 tcg_gen_or_tl(t2, t2, t3); 3306 tcg_gen_movi_tl(t3, 0); 3307 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3308 tcg_gen_div_tl(cpu_LO[acc], t0, t1); 3309 tcg_gen_rem_tl(cpu_HI[acc], t0, t1); 3310 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]); 3311 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]); 3312 } 3313 break; 3314 case OPC_DIVU: 3315 { 3316 TCGv t2 = tcg_constant_tl(0); 3317 TCGv t3 = tcg_constant_tl(1); 3318 tcg_gen_ext32u_tl(t0, t0); 3319 tcg_gen_ext32u_tl(t1, t1); 3320 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3321 tcg_gen_divu_tl(cpu_LO[acc], t0, t1); 3322 tcg_gen_remu_tl(cpu_HI[acc], t0, t1); 3323 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]); 3324 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]); 3325 } 3326 break; 3327 case OPC_MULT: 3328 { 3329 TCGv_i32 t2 = tcg_temp_new_i32(); 3330 TCGv_i32 t3 = tcg_temp_new_i32(); 3331 tcg_gen_trunc_tl_i32(t2, t0); 3332 tcg_gen_trunc_tl_i32(t3, t1); 3333 tcg_gen_muls2_i32(t2, t3, t2, t3); 3334 tcg_gen_ext_i32_tl(cpu_LO[acc], t2); 3335 tcg_gen_ext_i32_tl(cpu_HI[acc], t3); 3336 } 3337 break; 3338 case OPC_MULTU: 3339 { 3340 TCGv_i32 t2 = tcg_temp_new_i32(); 3341 TCGv_i32 t3 = tcg_temp_new_i32(); 3342 tcg_gen_trunc_tl_i32(t2, t0); 3343 tcg_gen_trunc_tl_i32(t3, t1); 3344 tcg_gen_mulu2_i32(t2, t3, t2, t3); 3345 tcg_gen_ext_i32_tl(cpu_LO[acc], t2); 3346 tcg_gen_ext_i32_tl(cpu_HI[acc], t3); 3347 } 3348 break; 3349 #if defined(TARGET_MIPS64) 3350 case OPC_DDIV: 3351 { 3352 TCGv t2 = tcg_temp_new(); 3353 TCGv t3 = tcg_temp_new(); 3354 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); 3355 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); 3356 tcg_gen_and_tl(t2, t2, t3); 3357 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3358 tcg_gen_or_tl(t2, t2, t3); 3359 tcg_gen_movi_tl(t3, 0); 3360 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3361 tcg_gen_div_tl(cpu_LO[acc], t0, t1); 3362 tcg_gen_rem_tl(cpu_HI[acc], t0, t1); 3363 } 3364 break; 3365 case OPC_DDIVU: 3366 { 3367 TCGv t2 = tcg_constant_tl(0); 3368 TCGv t3 = tcg_constant_tl(1); 3369 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3370 tcg_gen_divu_i64(cpu_LO[acc], t0, t1); 3371 tcg_gen_remu_i64(cpu_HI[acc], t0, t1); 3372 } 3373 break; 3374 case OPC_DMULT: 3375 tcg_gen_muls2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1); 3376 break; 3377 case OPC_DMULTU: 3378 tcg_gen_mulu2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1); 3379 break; 3380 #endif 3381 case OPC_MADD: 3382 { 3383 TCGv_i64 t2 = tcg_temp_new_i64(); 3384 TCGv_i64 t3 = tcg_temp_new_i64(); 3385 3386 tcg_gen_ext_tl_i64(t2, t0); 3387 tcg_gen_ext_tl_i64(t3, t1); 3388 tcg_gen_mul_i64(t2, t2, t3); 3389 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3390 tcg_gen_add_i64(t2, t2, t3); 3391 gen_move_low32(cpu_LO[acc], t2); 3392 gen_move_high32(cpu_HI[acc], t2); 3393 } 3394 break; 3395 case OPC_MADDU: 3396 { 3397 TCGv_i64 t2 = tcg_temp_new_i64(); 3398 TCGv_i64 t3 = tcg_temp_new_i64(); 3399 3400 tcg_gen_ext32u_tl(t0, t0); 3401 tcg_gen_ext32u_tl(t1, t1); 3402 tcg_gen_extu_tl_i64(t2, t0); 3403 tcg_gen_extu_tl_i64(t3, t1); 3404 tcg_gen_mul_i64(t2, t2, t3); 3405 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3406 tcg_gen_add_i64(t2, t2, t3); 3407 gen_move_low32(cpu_LO[acc], t2); 3408 gen_move_high32(cpu_HI[acc], t2); 3409 } 3410 break; 3411 case OPC_MSUB: 3412 { 3413 TCGv_i64 t2 = tcg_temp_new_i64(); 3414 TCGv_i64 t3 = tcg_temp_new_i64(); 3415 3416 tcg_gen_ext_tl_i64(t2, t0); 3417 tcg_gen_ext_tl_i64(t3, t1); 3418 tcg_gen_mul_i64(t2, t2, t3); 3419 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3420 tcg_gen_sub_i64(t2, t3, t2); 3421 gen_move_low32(cpu_LO[acc], t2); 3422 gen_move_high32(cpu_HI[acc], t2); 3423 } 3424 break; 3425 case OPC_MSUBU: 3426 { 3427 TCGv_i64 t2 = tcg_temp_new_i64(); 3428 TCGv_i64 t3 = tcg_temp_new_i64(); 3429 3430 tcg_gen_ext32u_tl(t0, t0); 3431 tcg_gen_ext32u_tl(t1, t1); 3432 tcg_gen_extu_tl_i64(t2, t0); 3433 tcg_gen_extu_tl_i64(t3, t1); 3434 tcg_gen_mul_i64(t2, t2, t3); 3435 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3436 tcg_gen_sub_i64(t2, t3, t2); 3437 gen_move_low32(cpu_LO[acc], t2); 3438 gen_move_high32(cpu_HI[acc], t2); 3439 } 3440 break; 3441 default: 3442 MIPS_INVAL("mul/div"); 3443 gen_reserved_instruction(ctx); 3444 break; 3445 } 3446 } 3447 3448 /* 3449 * These MULT[U] and MADD[U] instructions implemented in for example 3450 * the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core 3451 * architectures are special three-operand variants with the syntax 3452 * 3453 * MULT[U][1] rd, rs, rt 3454 * 3455 * such that 3456 * 3457 * (rd, LO, HI) <- rs * rt 3458 * 3459 * and 3460 * 3461 * MADD[U][1] rd, rs, rt 3462 * 3463 * such that 3464 * 3465 * (rd, LO, HI) <- (LO, HI) + rs * rt 3466 * 3467 * where the low-order 32-bits of the result is placed into both the 3468 * GPR rd and the special register LO. The high-order 32-bits of the 3469 * result is placed into the special register HI. 3470 * 3471 * If the GPR rd is omitted in assembly language, it is taken to be 0, 3472 * which is the zero register that always reads as 0. 3473 */ 3474 static void gen_mul_txx9(DisasContext *ctx, uint32_t opc, 3475 int rd, int rs, int rt) 3476 { 3477 TCGv t0 = tcg_temp_new(); 3478 TCGv t1 = tcg_temp_new(); 3479 int acc = 0; 3480 3481 gen_load_gpr(t0, rs); 3482 gen_load_gpr(t1, rt); 3483 3484 switch (opc) { 3485 case MMI_OPC_MULT1: 3486 acc = 1; 3487 /* Fall through */ 3488 case OPC_MULT: 3489 { 3490 TCGv_i32 t2 = tcg_temp_new_i32(); 3491 TCGv_i32 t3 = tcg_temp_new_i32(); 3492 tcg_gen_trunc_tl_i32(t2, t0); 3493 tcg_gen_trunc_tl_i32(t3, t1); 3494 tcg_gen_muls2_i32(t2, t3, t2, t3); 3495 if (rd) { 3496 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); 3497 } 3498 tcg_gen_ext_i32_tl(cpu_LO[acc], t2); 3499 tcg_gen_ext_i32_tl(cpu_HI[acc], t3); 3500 } 3501 break; 3502 case MMI_OPC_MULTU1: 3503 acc = 1; 3504 /* Fall through */ 3505 case OPC_MULTU: 3506 { 3507 TCGv_i32 t2 = tcg_temp_new_i32(); 3508 TCGv_i32 t3 = tcg_temp_new_i32(); 3509 tcg_gen_trunc_tl_i32(t2, t0); 3510 tcg_gen_trunc_tl_i32(t3, t1); 3511 tcg_gen_mulu2_i32(t2, t3, t2, t3); 3512 if (rd) { 3513 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); 3514 } 3515 tcg_gen_ext_i32_tl(cpu_LO[acc], t2); 3516 tcg_gen_ext_i32_tl(cpu_HI[acc], t3); 3517 } 3518 break; 3519 case MMI_OPC_MADD1: 3520 acc = 1; 3521 /* Fall through */ 3522 case MMI_OPC_MADD: 3523 { 3524 TCGv_i64 t2 = tcg_temp_new_i64(); 3525 TCGv_i64 t3 = tcg_temp_new_i64(); 3526 3527 tcg_gen_ext_tl_i64(t2, t0); 3528 tcg_gen_ext_tl_i64(t3, t1); 3529 tcg_gen_mul_i64(t2, t2, t3); 3530 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3531 tcg_gen_add_i64(t2, t2, t3); 3532 gen_move_low32(cpu_LO[acc], t2); 3533 gen_move_high32(cpu_HI[acc], t2); 3534 if (rd) { 3535 gen_move_low32(cpu_gpr[rd], t2); 3536 } 3537 } 3538 break; 3539 case MMI_OPC_MADDU1: 3540 acc = 1; 3541 /* Fall through */ 3542 case MMI_OPC_MADDU: 3543 { 3544 TCGv_i64 t2 = tcg_temp_new_i64(); 3545 TCGv_i64 t3 = tcg_temp_new_i64(); 3546 3547 tcg_gen_ext32u_tl(t0, t0); 3548 tcg_gen_ext32u_tl(t1, t1); 3549 tcg_gen_extu_tl_i64(t2, t0); 3550 tcg_gen_extu_tl_i64(t3, t1); 3551 tcg_gen_mul_i64(t2, t2, t3); 3552 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3553 tcg_gen_add_i64(t2, t2, t3); 3554 gen_move_low32(cpu_LO[acc], t2); 3555 gen_move_high32(cpu_HI[acc], t2); 3556 if (rd) { 3557 gen_move_low32(cpu_gpr[rd], t2); 3558 } 3559 } 3560 break; 3561 default: 3562 MIPS_INVAL("mul/madd TXx9"); 3563 gen_reserved_instruction(ctx); 3564 break; 3565 } 3566 } 3567 3568 static void gen_cl(DisasContext *ctx, uint32_t opc, 3569 int rd, int rs) 3570 { 3571 TCGv t0; 3572 3573 if (rd == 0) { 3574 /* Treat as NOP. */ 3575 return; 3576 } 3577 t0 = cpu_gpr[rd]; 3578 gen_load_gpr(t0, rs); 3579 3580 switch (opc) { 3581 case OPC_CLO: 3582 case R6_OPC_CLO: 3583 #if defined(TARGET_MIPS64) 3584 case OPC_DCLO: 3585 case R6_OPC_DCLO: 3586 #endif 3587 tcg_gen_not_tl(t0, t0); 3588 break; 3589 } 3590 3591 switch (opc) { 3592 case OPC_CLO: 3593 case R6_OPC_CLO: 3594 case OPC_CLZ: 3595 case R6_OPC_CLZ: 3596 tcg_gen_ext32u_tl(t0, t0); 3597 tcg_gen_clzi_tl(t0, t0, TARGET_LONG_BITS); 3598 tcg_gen_subi_tl(t0, t0, TARGET_LONG_BITS - 32); 3599 break; 3600 #if defined(TARGET_MIPS64) 3601 case OPC_DCLO: 3602 case R6_OPC_DCLO: 3603 case OPC_DCLZ: 3604 case R6_OPC_DCLZ: 3605 tcg_gen_clzi_i64(t0, t0, 64); 3606 break; 3607 #endif 3608 } 3609 } 3610 3611 /* Godson integer instructions */ 3612 static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, 3613 int rd, int rs, int rt) 3614 { 3615 TCGv t0, t1; 3616 3617 if (rd == 0) { 3618 /* Treat as NOP. */ 3619 return; 3620 } 3621 3622 t0 = tcg_temp_new(); 3623 t1 = tcg_temp_new(); 3624 gen_load_gpr(t0, rs); 3625 gen_load_gpr(t1, rt); 3626 3627 switch (opc) { 3628 case OPC_MULT_G_2E: 3629 case OPC_MULT_G_2F: 3630 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); 3631 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3632 break; 3633 case OPC_MULTU_G_2E: 3634 case OPC_MULTU_G_2F: 3635 tcg_gen_ext32u_tl(t0, t0); 3636 tcg_gen_ext32u_tl(t1, t1); 3637 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); 3638 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3639 break; 3640 case OPC_DIV_G_2E: 3641 case OPC_DIV_G_2F: 3642 { 3643 TCGLabel *l1 = gen_new_label(); 3644 TCGLabel *l2 = gen_new_label(); 3645 TCGLabel *l3 = gen_new_label(); 3646 tcg_gen_ext32s_tl(t0, t0); 3647 tcg_gen_ext32s_tl(t1, t1); 3648 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3649 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3650 tcg_gen_br(l3); 3651 gen_set_label(l1); 3652 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2); 3653 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2); 3654 tcg_gen_mov_tl(cpu_gpr[rd], t0); 3655 tcg_gen_br(l3); 3656 gen_set_label(l2); 3657 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); 3658 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3659 gen_set_label(l3); 3660 } 3661 break; 3662 case OPC_DIVU_G_2E: 3663 case OPC_DIVU_G_2F: 3664 { 3665 TCGLabel *l1 = gen_new_label(); 3666 TCGLabel *l2 = gen_new_label(); 3667 tcg_gen_ext32u_tl(t0, t0); 3668 tcg_gen_ext32u_tl(t1, t1); 3669 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3670 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3671 tcg_gen_br(l2); 3672 gen_set_label(l1); 3673 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); 3674 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3675 gen_set_label(l2); 3676 } 3677 break; 3678 case OPC_MOD_G_2E: 3679 case OPC_MOD_G_2F: 3680 { 3681 TCGLabel *l1 = gen_new_label(); 3682 TCGLabel *l2 = gen_new_label(); 3683 TCGLabel *l3 = gen_new_label(); 3684 tcg_gen_ext32u_tl(t0, t0); 3685 tcg_gen_ext32u_tl(t1, t1); 3686 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 3687 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2); 3688 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2); 3689 gen_set_label(l1); 3690 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3691 tcg_gen_br(l3); 3692 gen_set_label(l2); 3693 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); 3694 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3695 gen_set_label(l3); 3696 } 3697 break; 3698 case OPC_MODU_G_2E: 3699 case OPC_MODU_G_2F: 3700 { 3701 TCGLabel *l1 = gen_new_label(); 3702 TCGLabel *l2 = gen_new_label(); 3703 tcg_gen_ext32u_tl(t0, t0); 3704 tcg_gen_ext32u_tl(t1, t1); 3705 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3706 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3707 tcg_gen_br(l2); 3708 gen_set_label(l1); 3709 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); 3710 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3711 gen_set_label(l2); 3712 } 3713 break; 3714 #if defined(TARGET_MIPS64) 3715 case OPC_DMULT_G_2E: 3716 case OPC_DMULT_G_2F: 3717 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); 3718 break; 3719 case OPC_DMULTU_G_2E: 3720 case OPC_DMULTU_G_2F: 3721 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); 3722 break; 3723 case OPC_DDIV_G_2E: 3724 case OPC_DDIV_G_2F: 3725 { 3726 TCGLabel *l1 = gen_new_label(); 3727 TCGLabel *l2 = gen_new_label(); 3728 TCGLabel *l3 = gen_new_label(); 3729 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3730 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3731 tcg_gen_br(l3); 3732 gen_set_label(l1); 3733 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); 3734 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); 3735 tcg_gen_mov_tl(cpu_gpr[rd], t0); 3736 tcg_gen_br(l3); 3737 gen_set_label(l2); 3738 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); 3739 gen_set_label(l3); 3740 } 3741 break; 3742 case OPC_DDIVU_G_2E: 3743 case OPC_DDIVU_G_2F: 3744 { 3745 TCGLabel *l1 = gen_new_label(); 3746 TCGLabel *l2 = gen_new_label(); 3747 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3748 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3749 tcg_gen_br(l2); 3750 gen_set_label(l1); 3751 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); 3752 gen_set_label(l2); 3753 } 3754 break; 3755 case OPC_DMOD_G_2E: 3756 case OPC_DMOD_G_2F: 3757 { 3758 TCGLabel *l1 = gen_new_label(); 3759 TCGLabel *l2 = gen_new_label(); 3760 TCGLabel *l3 = gen_new_label(); 3761 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 3762 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); 3763 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); 3764 gen_set_label(l1); 3765 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3766 tcg_gen_br(l3); 3767 gen_set_label(l2); 3768 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); 3769 gen_set_label(l3); 3770 } 3771 break; 3772 case OPC_DMODU_G_2E: 3773 case OPC_DMODU_G_2F: 3774 { 3775 TCGLabel *l1 = gen_new_label(); 3776 TCGLabel *l2 = gen_new_label(); 3777 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3778 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3779 tcg_gen_br(l2); 3780 gen_set_label(l1); 3781 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); 3782 gen_set_label(l2); 3783 } 3784 break; 3785 #endif 3786 } 3787 } 3788 3789 /* Loongson multimedia instructions */ 3790 static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) 3791 { 3792 uint32_t opc, shift_max; 3793 TCGv_i64 t0, t1; 3794 TCGCond cond; 3795 3796 opc = MASK_LMMI(ctx->opcode); 3797 check_cp1_enabled(ctx); 3798 3799 t0 = tcg_temp_new_i64(); 3800 t1 = tcg_temp_new_i64(); 3801 gen_load_fpr64(ctx, t0, rs); 3802 gen_load_fpr64(ctx, t1, rt); 3803 3804 switch (opc) { 3805 case OPC_PADDSH: 3806 gen_helper_paddsh(t0, t0, t1); 3807 break; 3808 case OPC_PADDUSH: 3809 gen_helper_paddush(t0, t0, t1); 3810 break; 3811 case OPC_PADDH: 3812 gen_helper_paddh(t0, t0, t1); 3813 break; 3814 case OPC_PADDW: 3815 gen_helper_paddw(t0, t0, t1); 3816 break; 3817 case OPC_PADDSB: 3818 gen_helper_paddsb(t0, t0, t1); 3819 break; 3820 case OPC_PADDUSB: 3821 gen_helper_paddusb(t0, t0, t1); 3822 break; 3823 case OPC_PADDB: 3824 gen_helper_paddb(t0, t0, t1); 3825 break; 3826 3827 case OPC_PSUBSH: 3828 gen_helper_psubsh(t0, t0, t1); 3829 break; 3830 case OPC_PSUBUSH: 3831 gen_helper_psubush(t0, t0, t1); 3832 break; 3833 case OPC_PSUBH: 3834 gen_helper_psubh(t0, t0, t1); 3835 break; 3836 case OPC_PSUBW: 3837 gen_helper_psubw(t0, t0, t1); 3838 break; 3839 case OPC_PSUBSB: 3840 gen_helper_psubsb(t0, t0, t1); 3841 break; 3842 case OPC_PSUBUSB: 3843 gen_helper_psubusb(t0, t0, t1); 3844 break; 3845 case OPC_PSUBB: 3846 gen_helper_psubb(t0, t0, t1); 3847 break; 3848 3849 case OPC_PSHUFH: 3850 gen_helper_pshufh(t0, t0, t1); 3851 break; 3852 case OPC_PACKSSWH: 3853 gen_helper_packsswh(t0, t0, t1); 3854 break; 3855 case OPC_PACKSSHB: 3856 gen_helper_packsshb(t0, t0, t1); 3857 break; 3858 case OPC_PACKUSHB: 3859 gen_helper_packushb(t0, t0, t1); 3860 break; 3861 3862 case OPC_PUNPCKLHW: 3863 gen_helper_punpcklhw(t0, t0, t1); 3864 break; 3865 case OPC_PUNPCKHHW: 3866 gen_helper_punpckhhw(t0, t0, t1); 3867 break; 3868 case OPC_PUNPCKLBH: 3869 gen_helper_punpcklbh(t0, t0, t1); 3870 break; 3871 case OPC_PUNPCKHBH: 3872 gen_helper_punpckhbh(t0, t0, t1); 3873 break; 3874 case OPC_PUNPCKLWD: 3875 gen_helper_punpcklwd(t0, t0, t1); 3876 break; 3877 case OPC_PUNPCKHWD: 3878 gen_helper_punpckhwd(t0, t0, t1); 3879 break; 3880 3881 case OPC_PAVGH: 3882 gen_helper_pavgh(t0, t0, t1); 3883 break; 3884 case OPC_PAVGB: 3885 gen_helper_pavgb(t0, t0, t1); 3886 break; 3887 case OPC_PMAXSH: 3888 gen_helper_pmaxsh(t0, t0, t1); 3889 break; 3890 case OPC_PMINSH: 3891 gen_helper_pminsh(t0, t0, t1); 3892 break; 3893 case OPC_PMAXUB: 3894 gen_helper_pmaxub(t0, t0, t1); 3895 break; 3896 case OPC_PMINUB: 3897 gen_helper_pminub(t0, t0, t1); 3898 break; 3899 3900 case OPC_PCMPEQW: 3901 gen_helper_pcmpeqw(t0, t0, t1); 3902 break; 3903 case OPC_PCMPGTW: 3904 gen_helper_pcmpgtw(t0, t0, t1); 3905 break; 3906 case OPC_PCMPEQH: 3907 gen_helper_pcmpeqh(t0, t0, t1); 3908 break; 3909 case OPC_PCMPGTH: 3910 gen_helper_pcmpgth(t0, t0, t1); 3911 break; 3912 case OPC_PCMPEQB: 3913 gen_helper_pcmpeqb(t0, t0, t1); 3914 break; 3915 case OPC_PCMPGTB: 3916 gen_helper_pcmpgtb(t0, t0, t1); 3917 break; 3918 3919 case OPC_PSLLW: 3920 gen_helper_psllw(t0, t0, t1); 3921 break; 3922 case OPC_PSLLH: 3923 gen_helper_psllh(t0, t0, t1); 3924 break; 3925 case OPC_PSRLW: 3926 gen_helper_psrlw(t0, t0, t1); 3927 break; 3928 case OPC_PSRLH: 3929 gen_helper_psrlh(t0, t0, t1); 3930 break; 3931 case OPC_PSRAW: 3932 gen_helper_psraw(t0, t0, t1); 3933 break; 3934 case OPC_PSRAH: 3935 gen_helper_psrah(t0, t0, t1); 3936 break; 3937 3938 case OPC_PMULLH: 3939 gen_helper_pmullh(t0, t0, t1); 3940 break; 3941 case OPC_PMULHH: 3942 gen_helper_pmulhh(t0, t0, t1); 3943 break; 3944 case OPC_PMULHUH: 3945 gen_helper_pmulhuh(t0, t0, t1); 3946 break; 3947 case OPC_PMADDHW: 3948 gen_helper_pmaddhw(t0, t0, t1); 3949 break; 3950 3951 case OPC_PASUBUB: 3952 gen_helper_pasubub(t0, t0, t1); 3953 break; 3954 case OPC_BIADD: 3955 gen_helper_biadd(t0, t0); 3956 break; 3957 case OPC_PMOVMSKB: 3958 gen_helper_pmovmskb(t0, t0); 3959 break; 3960 3961 case OPC_PADDD: 3962 tcg_gen_add_i64(t0, t0, t1); 3963 break; 3964 case OPC_PSUBD: 3965 tcg_gen_sub_i64(t0, t0, t1); 3966 break; 3967 case OPC_XOR_CP2: 3968 tcg_gen_xor_i64(t0, t0, t1); 3969 break; 3970 case OPC_NOR_CP2: 3971 tcg_gen_nor_i64(t0, t0, t1); 3972 break; 3973 case OPC_AND_CP2: 3974 tcg_gen_and_i64(t0, t0, t1); 3975 break; 3976 case OPC_OR_CP2: 3977 tcg_gen_or_i64(t0, t0, t1); 3978 break; 3979 3980 case OPC_PANDN: 3981 tcg_gen_andc_i64(t0, t1, t0); 3982 break; 3983 3984 case OPC_PINSRH_0: 3985 tcg_gen_deposit_i64(t0, t0, t1, 0, 16); 3986 break; 3987 case OPC_PINSRH_1: 3988 tcg_gen_deposit_i64(t0, t0, t1, 16, 16); 3989 break; 3990 case OPC_PINSRH_2: 3991 tcg_gen_deposit_i64(t0, t0, t1, 32, 16); 3992 break; 3993 case OPC_PINSRH_3: 3994 tcg_gen_deposit_i64(t0, t0, t1, 48, 16); 3995 break; 3996 3997 case OPC_PEXTRH: 3998 tcg_gen_andi_i64(t1, t1, 3); 3999 tcg_gen_shli_i64(t1, t1, 4); 4000 tcg_gen_shr_i64(t0, t0, t1); 4001 tcg_gen_ext16u_i64(t0, t0); 4002 break; 4003 4004 case OPC_ADDU_CP2: 4005 tcg_gen_add_i64(t0, t0, t1); 4006 tcg_gen_ext32s_i64(t0, t0); 4007 break; 4008 case OPC_SUBU_CP2: 4009 tcg_gen_sub_i64(t0, t0, t1); 4010 tcg_gen_ext32s_i64(t0, t0); 4011 break; 4012 4013 case OPC_SLL_CP2: 4014 shift_max = 32; 4015 goto do_shift; 4016 case OPC_SRL_CP2: 4017 shift_max = 32; 4018 goto do_shift; 4019 case OPC_SRA_CP2: 4020 shift_max = 32; 4021 goto do_shift; 4022 case OPC_DSLL_CP2: 4023 shift_max = 64; 4024 goto do_shift; 4025 case OPC_DSRL_CP2: 4026 shift_max = 64; 4027 goto do_shift; 4028 case OPC_DSRA_CP2: 4029 shift_max = 64; 4030 goto do_shift; 4031 do_shift: 4032 /* Make sure shift count isn't TCG undefined behaviour. */ 4033 tcg_gen_andi_i64(t1, t1, shift_max - 1); 4034 4035 switch (opc) { 4036 case OPC_SLL_CP2: 4037 case OPC_DSLL_CP2: 4038 tcg_gen_shl_i64(t0, t0, t1); 4039 break; 4040 case OPC_SRA_CP2: 4041 case OPC_DSRA_CP2: 4042 /* 4043 * Since SRA is UndefinedResult without sign-extended inputs, 4044 * we can treat SRA and DSRA the same. 4045 */ 4046 tcg_gen_sar_i64(t0, t0, t1); 4047 break; 4048 case OPC_SRL_CP2: 4049 /* We want to shift in zeros for SRL; zero-extend first. */ 4050 tcg_gen_ext32u_i64(t0, t0); 4051 /* FALLTHRU */ 4052 case OPC_DSRL_CP2: 4053 tcg_gen_shr_i64(t0, t0, t1); 4054 break; 4055 } 4056 4057 if (shift_max == 32) { 4058 tcg_gen_ext32s_i64(t0, t0); 4059 } 4060 4061 /* Shifts larger than MAX produce zero. */ 4062 tcg_gen_setcondi_i64(TCG_COND_LTU, t1, t1, shift_max); 4063 tcg_gen_neg_i64(t1, t1); 4064 tcg_gen_and_i64(t0, t0, t1); 4065 break; 4066 4067 case OPC_ADD_CP2: 4068 case OPC_DADD_CP2: 4069 { 4070 TCGv_i64 t2 = tcg_temp_new_i64(); 4071 TCGLabel *lab = gen_new_label(); 4072 4073 tcg_gen_mov_i64(t2, t0); 4074 tcg_gen_add_i64(t0, t1, t2); 4075 if (opc == OPC_ADD_CP2) { 4076 tcg_gen_ext32s_i64(t0, t0); 4077 } 4078 tcg_gen_xor_i64(t1, t1, t2); 4079 tcg_gen_xor_i64(t2, t2, t0); 4080 tcg_gen_andc_i64(t1, t2, t1); 4081 tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab); 4082 generate_exception(ctx, EXCP_OVERFLOW); 4083 gen_set_label(lab); 4084 break; 4085 } 4086 4087 case OPC_SUB_CP2: 4088 case OPC_DSUB_CP2: 4089 { 4090 TCGv_i64 t2 = tcg_temp_new_i64(); 4091 TCGLabel *lab = gen_new_label(); 4092 4093 tcg_gen_mov_i64(t2, t0); 4094 tcg_gen_sub_i64(t0, t1, t2); 4095 if (opc == OPC_SUB_CP2) { 4096 tcg_gen_ext32s_i64(t0, t0); 4097 } 4098 tcg_gen_xor_i64(t1, t1, t2); 4099 tcg_gen_xor_i64(t2, t2, t0); 4100 tcg_gen_and_i64(t1, t1, t2); 4101 tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab); 4102 generate_exception(ctx, EXCP_OVERFLOW); 4103 gen_set_label(lab); 4104 break; 4105 } 4106 4107 case OPC_PMULUW: 4108 tcg_gen_ext32u_i64(t0, t0); 4109 tcg_gen_ext32u_i64(t1, t1); 4110 tcg_gen_mul_i64(t0, t0, t1); 4111 break; 4112 4113 case OPC_SEQU_CP2: 4114 case OPC_SEQ_CP2: 4115 cond = TCG_COND_EQ; 4116 goto do_cc_cond; 4117 break; 4118 case OPC_SLTU_CP2: 4119 cond = TCG_COND_LTU; 4120 goto do_cc_cond; 4121 break; 4122 case OPC_SLT_CP2: 4123 cond = TCG_COND_LT; 4124 goto do_cc_cond; 4125 break; 4126 case OPC_SLEU_CP2: 4127 cond = TCG_COND_LEU; 4128 goto do_cc_cond; 4129 break; 4130 case OPC_SLE_CP2: 4131 cond = TCG_COND_LE; 4132 do_cc_cond: 4133 { 4134 int cc = (ctx->opcode >> 8) & 0x7; 4135 TCGv_i64 t64 = tcg_temp_new_i64(); 4136 TCGv_i32 t32 = tcg_temp_new_i32(); 4137 4138 tcg_gen_setcond_i64(cond, t64, t0, t1); 4139 tcg_gen_extrl_i64_i32(t32, t64); 4140 tcg_gen_deposit_i32(fpu_fcr31, fpu_fcr31, t32, 4141 get_fp_bit(cc), 1); 4142 } 4143 return; 4144 default: 4145 MIPS_INVAL("loongson_cp2"); 4146 gen_reserved_instruction(ctx); 4147 return; 4148 } 4149 4150 gen_store_fpr64(ctx, t0, rd); 4151 } 4152 4153 static void gen_loongson_lswc2(DisasContext *ctx, int rt, 4154 int rs, int rd) 4155 { 4156 TCGv t0, t1; 4157 TCGv_i32 fp0; 4158 #if defined(TARGET_MIPS64) 4159 int lsq_rt1 = ctx->opcode & 0x1f; 4160 int lsq_offset = sextract32(ctx->opcode, 6, 9) << 4; 4161 #endif 4162 int shf_offset = sextract32(ctx->opcode, 6, 8); 4163 4164 t0 = tcg_temp_new(); 4165 4166 switch (MASK_LOONGSON_GSLSQ(ctx->opcode)) { 4167 #if defined(TARGET_MIPS64) 4168 case OPC_GSLQ: 4169 t1 = tcg_temp_new(); 4170 gen_base_offset_addr(ctx, t0, rs, lsq_offset); 4171 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4172 ctx->default_tcg_memop_mask); 4173 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); 4174 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ | 4175 ctx->default_tcg_memop_mask); 4176 gen_store_gpr(t1, rt); 4177 gen_store_gpr(t0, lsq_rt1); 4178 break; 4179 case OPC_GSLQC1: 4180 check_cp1_enabled(ctx); 4181 t1 = tcg_temp_new(); 4182 gen_base_offset_addr(ctx, t0, rs, lsq_offset); 4183 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4184 ctx->default_tcg_memop_mask); 4185 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); 4186 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ | 4187 ctx->default_tcg_memop_mask); 4188 gen_store_fpr64(ctx, t1, rt); 4189 gen_store_fpr64(ctx, t0, lsq_rt1); 4190 break; 4191 case OPC_GSSQ: 4192 t1 = tcg_temp_new(); 4193 gen_base_offset_addr(ctx, t0, rs, lsq_offset); 4194 gen_load_gpr(t1, rt); 4195 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4196 ctx->default_tcg_memop_mask); 4197 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); 4198 gen_load_gpr(t1, lsq_rt1); 4199 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4200 ctx->default_tcg_memop_mask); 4201 break; 4202 case OPC_GSSQC1: 4203 check_cp1_enabled(ctx); 4204 t1 = tcg_temp_new(); 4205 gen_base_offset_addr(ctx, t0, rs, lsq_offset); 4206 gen_load_fpr64(ctx, t1, rt); 4207 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4208 ctx->default_tcg_memop_mask); 4209 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); 4210 gen_load_fpr64(ctx, t1, lsq_rt1); 4211 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4212 ctx->default_tcg_memop_mask); 4213 break; 4214 #endif 4215 case OPC_GSSHFL: 4216 switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) { 4217 case OPC_GSLWLC1: 4218 check_cp1_enabled(ctx); 4219 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4220 fp0 = tcg_temp_new_i32(); 4221 gen_load_fpr32(ctx, fp0, rt); 4222 t1 = tcg_temp_new(); 4223 tcg_gen_ext_i32_tl(t1, fp0); 4224 gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TEUL); 4225 tcg_gen_trunc_tl_i32(fp0, t1); 4226 gen_store_fpr32(ctx, fp0, rt); 4227 break; 4228 case OPC_GSLWRC1: 4229 check_cp1_enabled(ctx); 4230 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4231 fp0 = tcg_temp_new_i32(); 4232 gen_load_fpr32(ctx, fp0, rt); 4233 t1 = tcg_temp_new(); 4234 tcg_gen_ext_i32_tl(t1, fp0); 4235 gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TEUL); 4236 tcg_gen_trunc_tl_i32(fp0, t1); 4237 gen_store_fpr32(ctx, fp0, rt); 4238 break; 4239 #if defined(TARGET_MIPS64) 4240 case OPC_GSLDLC1: 4241 check_cp1_enabled(ctx); 4242 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4243 t1 = tcg_temp_new(); 4244 gen_load_fpr64(ctx, t1, rt); 4245 gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TEUQ); 4246 gen_store_fpr64(ctx, t1, rt); 4247 break; 4248 case OPC_GSLDRC1: 4249 check_cp1_enabled(ctx); 4250 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4251 t1 = tcg_temp_new(); 4252 gen_load_fpr64(ctx, t1, rt); 4253 gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TEUQ); 4254 gen_store_fpr64(ctx, t1, rt); 4255 break; 4256 #endif 4257 default: 4258 MIPS_INVAL("loongson_gsshfl"); 4259 gen_reserved_instruction(ctx); 4260 break; 4261 } 4262 break; 4263 case OPC_GSSHFS: 4264 switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) { 4265 case OPC_GSSWLC1: 4266 check_cp1_enabled(ctx); 4267 t1 = tcg_temp_new(); 4268 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4269 fp0 = tcg_temp_new_i32(); 4270 gen_load_fpr32(ctx, fp0, rt); 4271 tcg_gen_ext_i32_tl(t1, fp0); 4272 gen_helper_0e2i(swl, t1, t0, ctx->mem_idx); 4273 break; 4274 case OPC_GSSWRC1: 4275 check_cp1_enabled(ctx); 4276 t1 = tcg_temp_new(); 4277 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4278 fp0 = tcg_temp_new_i32(); 4279 gen_load_fpr32(ctx, fp0, rt); 4280 tcg_gen_ext_i32_tl(t1, fp0); 4281 gen_helper_0e2i(swr, t1, t0, ctx->mem_idx); 4282 break; 4283 #if defined(TARGET_MIPS64) 4284 case OPC_GSSDLC1: 4285 check_cp1_enabled(ctx); 4286 t1 = tcg_temp_new(); 4287 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4288 gen_load_fpr64(ctx, t1, rt); 4289 gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx); 4290 break; 4291 case OPC_GSSDRC1: 4292 check_cp1_enabled(ctx); 4293 t1 = tcg_temp_new(); 4294 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4295 gen_load_fpr64(ctx, t1, rt); 4296 gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx); 4297 break; 4298 #endif 4299 default: 4300 MIPS_INVAL("loongson_gsshfs"); 4301 gen_reserved_instruction(ctx); 4302 break; 4303 } 4304 break; 4305 default: 4306 MIPS_INVAL("loongson_gslsq"); 4307 gen_reserved_instruction(ctx); 4308 break; 4309 } 4310 } 4311 4312 /* Loongson EXT LDC2/SDC2 */ 4313 static void gen_loongson_lsdc2(DisasContext *ctx, int rt, 4314 int rs, int rd) 4315 { 4316 int offset = sextract32(ctx->opcode, 3, 8); 4317 uint32_t opc = MASK_LOONGSON_LSDC2(ctx->opcode); 4318 TCGv t0, t1; 4319 TCGv_i32 fp0; 4320 4321 /* Pre-conditions */ 4322 switch (opc) { 4323 case OPC_GSLBX: 4324 case OPC_GSLHX: 4325 case OPC_GSLWX: 4326 case OPC_GSLDX: 4327 /* prefetch, implement as NOP */ 4328 if (rt == 0) { 4329 return; 4330 } 4331 break; 4332 case OPC_GSSBX: 4333 case OPC_GSSHX: 4334 case OPC_GSSWX: 4335 case OPC_GSSDX: 4336 break; 4337 case OPC_GSLWXC1: 4338 #if defined(TARGET_MIPS64) 4339 case OPC_GSLDXC1: 4340 #endif 4341 check_cp1_enabled(ctx); 4342 /* prefetch, implement as NOP */ 4343 if (rt == 0) { 4344 return; 4345 } 4346 break; 4347 case OPC_GSSWXC1: 4348 #if defined(TARGET_MIPS64) 4349 case OPC_GSSDXC1: 4350 #endif 4351 check_cp1_enabled(ctx); 4352 break; 4353 default: 4354 MIPS_INVAL("loongson_lsdc2"); 4355 gen_reserved_instruction(ctx); 4356 return; 4357 break; 4358 } 4359 4360 t0 = tcg_temp_new(); 4361 4362 gen_base_offset_addr(ctx, t0, rs, offset); 4363 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); 4364 4365 switch (opc) { 4366 case OPC_GSLBX: 4367 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB); 4368 gen_store_gpr(t0, rt); 4369 break; 4370 case OPC_GSLHX: 4371 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW | 4372 ctx->default_tcg_memop_mask); 4373 gen_store_gpr(t0, rt); 4374 break; 4375 case OPC_GSLWX: 4376 gen_base_offset_addr(ctx, t0, rs, offset); 4377 if (rd) { 4378 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); 4379 } 4380 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL | 4381 ctx->default_tcg_memop_mask); 4382 gen_store_gpr(t0, rt); 4383 break; 4384 #if defined(TARGET_MIPS64) 4385 case OPC_GSLDX: 4386 gen_base_offset_addr(ctx, t0, rs, offset); 4387 if (rd) { 4388 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); 4389 } 4390 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ | 4391 ctx->default_tcg_memop_mask); 4392 gen_store_gpr(t0, rt); 4393 break; 4394 #endif 4395 case OPC_GSLWXC1: 4396 gen_base_offset_addr(ctx, t0, rs, offset); 4397 if (rd) { 4398 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); 4399 } 4400 fp0 = tcg_temp_new_i32(); 4401 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL | 4402 ctx->default_tcg_memop_mask); 4403 gen_store_fpr32(ctx, fp0, rt); 4404 break; 4405 #if defined(TARGET_MIPS64) 4406 case OPC_GSLDXC1: 4407 gen_base_offset_addr(ctx, t0, rs, offset); 4408 if (rd) { 4409 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); 4410 } 4411 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ | 4412 ctx->default_tcg_memop_mask); 4413 gen_store_fpr64(ctx, t0, rt); 4414 break; 4415 #endif 4416 case OPC_GSSBX: 4417 t1 = tcg_temp_new(); 4418 gen_load_gpr(t1, rt); 4419 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_SB); 4420 break; 4421 case OPC_GSSHX: 4422 t1 = tcg_temp_new(); 4423 gen_load_gpr(t1, rt); 4424 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW | 4425 ctx->default_tcg_memop_mask); 4426 break; 4427 case OPC_GSSWX: 4428 t1 = tcg_temp_new(); 4429 gen_load_gpr(t1, rt); 4430 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | 4431 ctx->default_tcg_memop_mask); 4432 break; 4433 #if defined(TARGET_MIPS64) 4434 case OPC_GSSDX: 4435 t1 = tcg_temp_new(); 4436 gen_load_gpr(t1, rt); 4437 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4438 ctx->default_tcg_memop_mask); 4439 break; 4440 #endif 4441 case OPC_GSSWXC1: 4442 fp0 = tcg_temp_new_i32(); 4443 gen_load_fpr32(ctx, fp0, rt); 4444 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL | 4445 ctx->default_tcg_memop_mask); 4446 break; 4447 #if defined(TARGET_MIPS64) 4448 case OPC_GSSDXC1: 4449 t1 = tcg_temp_new(); 4450 gen_load_fpr64(ctx, t1, rt); 4451 tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TEUQ | 4452 ctx->default_tcg_memop_mask); 4453 break; 4454 #endif 4455 default: 4456 break; 4457 } 4458 } 4459 4460 /* Traps */ 4461 static void gen_trap(DisasContext *ctx, uint32_t opc, 4462 int rs, int rt, int16_t imm, int code) 4463 { 4464 int cond; 4465 TCGv t0 = tcg_temp_new(); 4466 TCGv t1 = tcg_temp_new(); 4467 4468 cond = 0; 4469 /* Load needed operands */ 4470 switch (opc) { 4471 case OPC_TEQ: 4472 case OPC_TGE: 4473 case OPC_TGEU: 4474 case OPC_TLT: 4475 case OPC_TLTU: 4476 case OPC_TNE: 4477 /* Compare two registers */ 4478 if (rs != rt) { 4479 gen_load_gpr(t0, rs); 4480 gen_load_gpr(t1, rt); 4481 cond = 1; 4482 } 4483 break; 4484 case OPC_TEQI: 4485 case OPC_TGEI: 4486 case OPC_TGEIU: 4487 case OPC_TLTI: 4488 case OPC_TLTIU: 4489 case OPC_TNEI: 4490 /* Compare register to immediate */ 4491 if (rs != 0 || imm != 0) { 4492 gen_load_gpr(t0, rs); 4493 tcg_gen_movi_tl(t1, (int32_t)imm); 4494 cond = 1; 4495 } 4496 break; 4497 } 4498 if (cond == 0) { 4499 switch (opc) { 4500 case OPC_TEQ: /* rs == rs */ 4501 case OPC_TEQI: /* r0 == 0 */ 4502 case OPC_TGE: /* rs >= rs */ 4503 case OPC_TGEI: /* r0 >= 0 */ 4504 case OPC_TGEU: /* rs >= rs unsigned */ 4505 case OPC_TGEIU: /* r0 >= 0 unsigned */ 4506 /* Always trap */ 4507 #ifdef CONFIG_USER_ONLY 4508 /* Pass the break code along to cpu_loop. */ 4509 tcg_gen_st_i32(tcg_constant_i32(code), cpu_env, 4510 offsetof(CPUMIPSState, error_code)); 4511 #endif 4512 generate_exception_end(ctx, EXCP_TRAP); 4513 break; 4514 case OPC_TLT: /* rs < rs */ 4515 case OPC_TLTI: /* r0 < 0 */ 4516 case OPC_TLTU: /* rs < rs unsigned */ 4517 case OPC_TLTIU: /* r0 < 0 unsigned */ 4518 case OPC_TNE: /* rs != rs */ 4519 case OPC_TNEI: /* r0 != 0 */ 4520 /* Never trap: treat as NOP. */ 4521 break; 4522 } 4523 } else { 4524 TCGLabel *l1 = gen_new_label(); 4525 4526 switch (opc) { 4527 case OPC_TEQ: 4528 case OPC_TEQI: 4529 tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1); 4530 break; 4531 case OPC_TGE: 4532 case OPC_TGEI: 4533 tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1); 4534 break; 4535 case OPC_TGEU: 4536 case OPC_TGEIU: 4537 tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1); 4538 break; 4539 case OPC_TLT: 4540 case OPC_TLTI: 4541 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 4542 break; 4543 case OPC_TLTU: 4544 case OPC_TLTIU: 4545 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 4546 break; 4547 case OPC_TNE: 4548 case OPC_TNEI: 4549 tcg_gen_brcond_tl(TCG_COND_EQ, t0, t1, l1); 4550 break; 4551 } 4552 #ifdef CONFIG_USER_ONLY 4553 /* Pass the break code along to cpu_loop. */ 4554 tcg_gen_st_i32(tcg_constant_i32(code), cpu_env, 4555 offsetof(CPUMIPSState, error_code)); 4556 #endif 4557 /* Like save_cpu_state, only don't update saved values. */ 4558 if (ctx->base.pc_next != ctx->saved_pc) { 4559 gen_save_pc(ctx->base.pc_next); 4560 } 4561 if (ctx->hflags != ctx->saved_hflags) { 4562 tcg_gen_movi_i32(hflags, ctx->hflags); 4563 } 4564 generate_exception(ctx, EXCP_TRAP); 4565 gen_set_label(l1); 4566 } 4567 } 4568 4569 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4570 { 4571 if (translator_use_goto_tb(&ctx->base, dest)) { 4572 tcg_gen_goto_tb(n); 4573 gen_save_pc(dest); 4574 tcg_gen_exit_tb(ctx->base.tb, n); 4575 } else { 4576 gen_save_pc(dest); 4577 tcg_gen_lookup_and_goto_ptr(); 4578 } 4579 } 4580 4581 /* Branches (before delay slot) */ 4582 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, 4583 int insn_bytes, 4584 int rs, int rt, int32_t offset, 4585 int delayslot_size) 4586 { 4587 target_ulong btgt = -1; 4588 int blink = 0; 4589 int bcond_compute = 0; 4590 TCGv t0 = tcg_temp_new(); 4591 TCGv t1 = tcg_temp_new(); 4592 4593 if (ctx->hflags & MIPS_HFLAG_BMASK) { 4594 #ifdef MIPS_DEBUG_DISAS 4595 LOG_DISAS("Branch in delay / forbidden slot at PC 0x" 4596 TARGET_FMT_lx "\n", ctx->base.pc_next); 4597 #endif 4598 gen_reserved_instruction(ctx); 4599 goto out; 4600 } 4601 4602 /* Load needed operands */ 4603 switch (opc) { 4604 case OPC_BEQ: 4605 case OPC_BEQL: 4606 case OPC_BNE: 4607 case OPC_BNEL: 4608 /* Compare two registers */ 4609 if (rs != rt) { 4610 gen_load_gpr(t0, rs); 4611 gen_load_gpr(t1, rt); 4612 bcond_compute = 1; 4613 } 4614 btgt = ctx->base.pc_next + insn_bytes + offset; 4615 break; 4616 case OPC_BGEZ: 4617 case OPC_BGEZAL: 4618 case OPC_BGEZALL: 4619 case OPC_BGEZL: 4620 case OPC_BGTZ: 4621 case OPC_BGTZL: 4622 case OPC_BLEZ: 4623 case OPC_BLEZL: 4624 case OPC_BLTZ: 4625 case OPC_BLTZAL: 4626 case OPC_BLTZALL: 4627 case OPC_BLTZL: 4628 /* Compare to zero */ 4629 if (rs != 0) { 4630 gen_load_gpr(t0, rs); 4631 bcond_compute = 1; 4632 } 4633 btgt = ctx->base.pc_next + insn_bytes + offset; 4634 break; 4635 case OPC_BPOSGE32: 4636 #if defined(TARGET_MIPS64) 4637 case OPC_BPOSGE64: 4638 tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F); 4639 #else 4640 tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F); 4641 #endif 4642 bcond_compute = 1; 4643 btgt = ctx->base.pc_next + insn_bytes + offset; 4644 break; 4645 case OPC_J: 4646 case OPC_JAL: 4647 { 4648 /* Jump to immediate */ 4649 int jal_mask = ctx->hflags & MIPS_HFLAG_M16 ? 0xF8000000 4650 : 0xF0000000; 4651 btgt = ((ctx->base.pc_next + insn_bytes) & jal_mask) 4652 | (uint32_t)offset; 4653 break; 4654 } 4655 case OPC_JALX: 4656 /* Jump to immediate */ 4657 btgt = ((ctx->base.pc_next + insn_bytes) & (int32_t)0xF0000000) | 4658 (uint32_t)offset; 4659 break; 4660 case OPC_JR: 4661 case OPC_JALR: 4662 /* Jump to register */ 4663 if (offset != 0 && offset != 16) { 4664 /* 4665 * Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the 4666 * others are reserved. 4667 */ 4668 MIPS_INVAL("jump hint"); 4669 gen_reserved_instruction(ctx); 4670 goto out; 4671 } 4672 gen_load_gpr(btarget, rs); 4673 break; 4674 default: 4675 MIPS_INVAL("branch/jump"); 4676 gen_reserved_instruction(ctx); 4677 goto out; 4678 } 4679 if (bcond_compute == 0) { 4680 /* No condition to be computed */ 4681 switch (opc) { 4682 case OPC_BEQ: /* rx == rx */ 4683 case OPC_BEQL: /* rx == rx likely */ 4684 case OPC_BGEZ: /* 0 >= 0 */ 4685 case OPC_BGEZL: /* 0 >= 0 likely */ 4686 case OPC_BLEZ: /* 0 <= 0 */ 4687 case OPC_BLEZL: /* 0 <= 0 likely */ 4688 /* Always take */ 4689 ctx->hflags |= MIPS_HFLAG_B; 4690 break; 4691 case OPC_BGEZAL: /* 0 >= 0 */ 4692 case OPC_BGEZALL: /* 0 >= 0 likely */ 4693 /* Always take and link */ 4694 blink = 31; 4695 ctx->hflags |= MIPS_HFLAG_B; 4696 break; 4697 case OPC_BNE: /* rx != rx */ 4698 case OPC_BGTZ: /* 0 > 0 */ 4699 case OPC_BLTZ: /* 0 < 0 */ 4700 /* Treat as NOP. */ 4701 goto out; 4702 case OPC_BLTZAL: /* 0 < 0 */ 4703 /* 4704 * Handle as an unconditional branch to get correct delay 4705 * slot checking. 4706 */ 4707 blink = 31; 4708 btgt = ctx->base.pc_next + insn_bytes + delayslot_size; 4709 ctx->hflags |= MIPS_HFLAG_B; 4710 break; 4711 case OPC_BLTZALL: /* 0 < 0 likely */ 4712 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 8); 4713 /* Skip the instruction in the delay slot */ 4714 ctx->base.pc_next += 4; 4715 goto out; 4716 case OPC_BNEL: /* rx != rx likely */ 4717 case OPC_BGTZL: /* 0 > 0 likely */ 4718 case OPC_BLTZL: /* 0 < 0 likely */ 4719 /* Skip the instruction in the delay slot */ 4720 ctx->base.pc_next += 4; 4721 goto out; 4722 case OPC_J: 4723 ctx->hflags |= MIPS_HFLAG_B; 4724 break; 4725 case OPC_JALX: 4726 ctx->hflags |= MIPS_HFLAG_BX; 4727 /* Fallthrough */ 4728 case OPC_JAL: 4729 blink = 31; 4730 ctx->hflags |= MIPS_HFLAG_B; 4731 break; 4732 case OPC_JR: 4733 ctx->hflags |= MIPS_HFLAG_BR; 4734 break; 4735 case OPC_JALR: 4736 blink = rt; 4737 ctx->hflags |= MIPS_HFLAG_BR; 4738 break; 4739 default: 4740 MIPS_INVAL("branch/jump"); 4741 gen_reserved_instruction(ctx); 4742 goto out; 4743 } 4744 } else { 4745 switch (opc) { 4746 case OPC_BEQ: 4747 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1); 4748 goto not_likely; 4749 case OPC_BEQL: 4750 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1); 4751 goto likely; 4752 case OPC_BNE: 4753 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1); 4754 goto not_likely; 4755 case OPC_BNEL: 4756 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1); 4757 goto likely; 4758 case OPC_BGEZ: 4759 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); 4760 goto not_likely; 4761 case OPC_BGEZL: 4762 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); 4763 goto likely; 4764 case OPC_BGEZAL: 4765 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); 4766 blink = 31; 4767 goto not_likely; 4768 case OPC_BGEZALL: 4769 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); 4770 blink = 31; 4771 goto likely; 4772 case OPC_BGTZ: 4773 tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0); 4774 goto not_likely; 4775 case OPC_BGTZL: 4776 tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0); 4777 goto likely; 4778 case OPC_BLEZ: 4779 tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0); 4780 goto not_likely; 4781 case OPC_BLEZL: 4782 tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0); 4783 goto likely; 4784 case OPC_BLTZ: 4785 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); 4786 goto not_likely; 4787 case OPC_BLTZL: 4788 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); 4789 goto likely; 4790 case OPC_BPOSGE32: 4791 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32); 4792 goto not_likely; 4793 #if defined(TARGET_MIPS64) 4794 case OPC_BPOSGE64: 4795 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 64); 4796 goto not_likely; 4797 #endif 4798 case OPC_BLTZAL: 4799 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); 4800 blink = 31; 4801 not_likely: 4802 ctx->hflags |= MIPS_HFLAG_BC; 4803 break; 4804 case OPC_BLTZALL: 4805 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); 4806 blink = 31; 4807 likely: 4808 ctx->hflags |= MIPS_HFLAG_BL; 4809 break; 4810 default: 4811 MIPS_INVAL("conditional branch/jump"); 4812 gen_reserved_instruction(ctx); 4813 goto out; 4814 } 4815 } 4816 4817 ctx->btarget = btgt; 4818 4819 switch (delayslot_size) { 4820 case 2: 4821 ctx->hflags |= MIPS_HFLAG_BDS16; 4822 break; 4823 case 4: 4824 ctx->hflags |= MIPS_HFLAG_BDS32; 4825 break; 4826 } 4827 4828 if (blink > 0) { 4829 int post_delay = insn_bytes + delayslot_size; 4830 int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16); 4831 4832 tcg_gen_movi_tl(cpu_gpr[blink], 4833 ctx->base.pc_next + post_delay + lowbit); 4834 } 4835 4836 out: 4837 if (insn_bytes == 2) { 4838 ctx->hflags |= MIPS_HFLAG_B16; 4839 } 4840 } 4841 4842 4843 /* special3 bitfield operations */ 4844 static void gen_bitops(DisasContext *ctx, uint32_t opc, int rt, 4845 int rs, int lsb, int msb) 4846 { 4847 TCGv t0 = tcg_temp_new(); 4848 TCGv t1 = tcg_temp_new(); 4849 4850 gen_load_gpr(t1, rs); 4851 switch (opc) { 4852 case OPC_EXT: 4853 if (lsb + msb > 31) { 4854 goto fail; 4855 } 4856 if (msb != 31) { 4857 tcg_gen_extract_tl(t0, t1, lsb, msb + 1); 4858 } else { 4859 /* 4860 * The two checks together imply that lsb == 0, 4861 * so this is a simple sign-extension. 4862 */ 4863 tcg_gen_ext32s_tl(t0, t1); 4864 } 4865 break; 4866 #if defined(TARGET_MIPS64) 4867 case OPC_DEXTU: 4868 lsb += 32; 4869 goto do_dext; 4870 case OPC_DEXTM: 4871 msb += 32; 4872 goto do_dext; 4873 case OPC_DEXT: 4874 do_dext: 4875 if (lsb + msb > 63) { 4876 goto fail; 4877 } 4878 tcg_gen_extract_tl(t0, t1, lsb, msb + 1); 4879 break; 4880 #endif 4881 case OPC_INS: 4882 if (lsb > msb) { 4883 goto fail; 4884 } 4885 gen_load_gpr(t0, rt); 4886 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); 4887 tcg_gen_ext32s_tl(t0, t0); 4888 break; 4889 #if defined(TARGET_MIPS64) 4890 case OPC_DINSU: 4891 lsb += 32; 4892 /* FALLTHRU */ 4893 case OPC_DINSM: 4894 msb += 32; 4895 /* FALLTHRU */ 4896 case OPC_DINS: 4897 if (lsb > msb) { 4898 goto fail; 4899 } 4900 gen_load_gpr(t0, rt); 4901 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); 4902 break; 4903 #endif 4904 default: 4905 fail: 4906 MIPS_INVAL("bitops"); 4907 gen_reserved_instruction(ctx); 4908 return; 4909 } 4910 gen_store_gpr(t0, rt); 4911 } 4912 4913 static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd) 4914 { 4915 TCGv t0; 4916 4917 if (rd == 0) { 4918 /* If no destination, treat it as a NOP. */ 4919 return; 4920 } 4921 4922 t0 = tcg_temp_new(); 4923 gen_load_gpr(t0, rt); 4924 switch (op2) { 4925 case OPC_WSBH: 4926 { 4927 TCGv t1 = tcg_temp_new(); 4928 TCGv t2 = tcg_constant_tl(0x00FF00FF); 4929 4930 tcg_gen_shri_tl(t1, t0, 8); 4931 tcg_gen_and_tl(t1, t1, t2); 4932 tcg_gen_and_tl(t0, t0, t2); 4933 tcg_gen_shli_tl(t0, t0, 8); 4934 tcg_gen_or_tl(t0, t0, t1); 4935 tcg_gen_ext32s_tl(cpu_gpr[rd], t0); 4936 } 4937 break; 4938 case OPC_SEB: 4939 tcg_gen_ext8s_tl(cpu_gpr[rd], t0); 4940 break; 4941 case OPC_SEH: 4942 tcg_gen_ext16s_tl(cpu_gpr[rd], t0); 4943 break; 4944 #if defined(TARGET_MIPS64) 4945 case OPC_DSBH: 4946 { 4947 TCGv t1 = tcg_temp_new(); 4948 TCGv t2 = tcg_constant_tl(0x00FF00FF00FF00FFULL); 4949 4950 tcg_gen_shri_tl(t1, t0, 8); 4951 tcg_gen_and_tl(t1, t1, t2); 4952 tcg_gen_and_tl(t0, t0, t2); 4953 tcg_gen_shli_tl(t0, t0, 8); 4954 tcg_gen_or_tl(cpu_gpr[rd], t0, t1); 4955 } 4956 break; 4957 case OPC_DSHD: 4958 { 4959 TCGv t1 = tcg_temp_new(); 4960 TCGv t2 = tcg_constant_tl(0x0000FFFF0000FFFFULL); 4961 4962 tcg_gen_shri_tl(t1, t0, 16); 4963 tcg_gen_and_tl(t1, t1, t2); 4964 tcg_gen_and_tl(t0, t0, t2); 4965 tcg_gen_shli_tl(t0, t0, 16); 4966 tcg_gen_or_tl(t0, t0, t1); 4967 tcg_gen_shri_tl(t1, t0, 32); 4968 tcg_gen_shli_tl(t0, t0, 32); 4969 tcg_gen_or_tl(cpu_gpr[rd], t0, t1); 4970 } 4971 break; 4972 #endif 4973 default: 4974 MIPS_INVAL("bsfhl"); 4975 gen_reserved_instruction(ctx); 4976 return; 4977 } 4978 } 4979 4980 static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs, 4981 int rt, int bits) 4982 { 4983 TCGv t0; 4984 if (rd == 0) { 4985 /* Treat as NOP. */ 4986 return; 4987 } 4988 t0 = tcg_temp_new(); 4989 if (bits == 0 || bits == wordsz) { 4990 if (bits == 0) { 4991 gen_load_gpr(t0, rt); 4992 } else { 4993 gen_load_gpr(t0, rs); 4994 } 4995 switch (wordsz) { 4996 case 32: 4997 tcg_gen_ext32s_tl(cpu_gpr[rd], t0); 4998 break; 4999 #if defined(TARGET_MIPS64) 5000 case 64: 5001 tcg_gen_mov_tl(cpu_gpr[rd], t0); 5002 break; 5003 #endif 5004 } 5005 } else { 5006 TCGv t1 = tcg_temp_new(); 5007 gen_load_gpr(t0, rt); 5008 gen_load_gpr(t1, rs); 5009 switch (wordsz) { 5010 case 32: 5011 { 5012 TCGv_i64 t2 = tcg_temp_new_i64(); 5013 tcg_gen_concat_tl_i64(t2, t1, t0); 5014 tcg_gen_shri_i64(t2, t2, 32 - bits); 5015 gen_move_low32(cpu_gpr[rd], t2); 5016 } 5017 break; 5018 #if defined(TARGET_MIPS64) 5019 case 64: 5020 tcg_gen_shli_tl(t0, t0, bits); 5021 tcg_gen_shri_tl(t1, t1, 64 - bits); 5022 tcg_gen_or_tl(cpu_gpr[rd], t1, t0); 5023 break; 5024 #endif 5025 } 5026 } 5027 } 5028 5029 void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int bp) 5030 { 5031 gen_align_bits(ctx, wordsz, rd, rs, rt, bp * 8); 5032 } 5033 5034 static void gen_bitswap(DisasContext *ctx, int opc, int rd, int rt) 5035 { 5036 TCGv t0; 5037 if (rd == 0) { 5038 /* Treat as NOP. */ 5039 return; 5040 } 5041 t0 = tcg_temp_new(); 5042 gen_load_gpr(t0, rt); 5043 switch (opc) { 5044 case OPC_BITSWAP: 5045 gen_helper_bitswap(cpu_gpr[rd], t0); 5046 break; 5047 #if defined(TARGET_MIPS64) 5048 case OPC_DBITSWAP: 5049 gen_helper_dbitswap(cpu_gpr[rd], t0); 5050 break; 5051 #endif 5052 } 5053 } 5054 5055 #ifndef CONFIG_USER_ONLY 5056 /* CP0 (MMU and control) */ 5057 static inline void gen_mthc0_entrylo(TCGv arg, target_ulong off) 5058 { 5059 TCGv_i64 t0 = tcg_temp_new_i64(); 5060 TCGv_i64 t1 = tcg_temp_new_i64(); 5061 5062 tcg_gen_ext_tl_i64(t0, arg); 5063 tcg_gen_ld_i64(t1, cpu_env, off); 5064 #if defined(TARGET_MIPS64) 5065 tcg_gen_deposit_i64(t1, t1, t0, 30, 32); 5066 #else 5067 tcg_gen_concat32_i64(t1, t1, t0); 5068 #endif 5069 tcg_gen_st_i64(t1, cpu_env, off); 5070 } 5071 5072 static inline void gen_mthc0_store64(TCGv arg, target_ulong off) 5073 { 5074 TCGv_i64 t0 = tcg_temp_new_i64(); 5075 TCGv_i64 t1 = tcg_temp_new_i64(); 5076 5077 tcg_gen_ext_tl_i64(t0, arg); 5078 tcg_gen_ld_i64(t1, cpu_env, off); 5079 tcg_gen_concat32_i64(t1, t1, t0); 5080 tcg_gen_st_i64(t1, cpu_env, off); 5081 } 5082 5083 static inline void gen_mfhc0_entrylo(TCGv arg, target_ulong off) 5084 { 5085 TCGv_i64 t0 = tcg_temp_new_i64(); 5086 5087 tcg_gen_ld_i64(t0, cpu_env, off); 5088 #if defined(TARGET_MIPS64) 5089 tcg_gen_shri_i64(t0, t0, 30); 5090 #else 5091 tcg_gen_shri_i64(t0, t0, 32); 5092 #endif 5093 gen_move_low32(arg, t0); 5094 } 5095 5096 static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift) 5097 { 5098 TCGv_i64 t0 = tcg_temp_new_i64(); 5099 5100 tcg_gen_ld_i64(t0, cpu_env, off); 5101 tcg_gen_shri_i64(t0, t0, 32 + shift); 5102 gen_move_low32(arg, t0); 5103 } 5104 5105 static inline void gen_mfc0_load32(TCGv arg, target_ulong off) 5106 { 5107 TCGv_i32 t0 = tcg_temp_new_i32(); 5108 5109 tcg_gen_ld_i32(t0, cpu_env, off); 5110 tcg_gen_ext_i32_tl(arg, t0); 5111 } 5112 5113 static inline void gen_mfc0_load64(TCGv arg, target_ulong off) 5114 { 5115 tcg_gen_ld_tl(arg, cpu_env, off); 5116 tcg_gen_ext32s_tl(arg, arg); 5117 } 5118 5119 static inline void gen_mtc0_store32(TCGv arg, target_ulong off) 5120 { 5121 TCGv_i32 t0 = tcg_temp_new_i32(); 5122 5123 tcg_gen_trunc_tl_i32(t0, arg); 5124 tcg_gen_st_i32(t0, cpu_env, off); 5125 } 5126 5127 #define CP0_CHECK(c) \ 5128 do { \ 5129 if (!(c)) { \ 5130 goto cp0_unimplemented; \ 5131 } \ 5132 } while (0) 5133 5134 static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel) 5135 { 5136 const char *register_name = "invalid"; 5137 5138 switch (reg) { 5139 case CP0_REGISTER_02: 5140 switch (sel) { 5141 case 0: 5142 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); 5143 gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0)); 5144 register_name = "EntryLo0"; 5145 break; 5146 default: 5147 goto cp0_unimplemented; 5148 } 5149 break; 5150 case CP0_REGISTER_03: 5151 switch (sel) { 5152 case CP0_REG03__ENTRYLO1: 5153 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); 5154 gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1)); 5155 register_name = "EntryLo1"; 5156 break; 5157 default: 5158 goto cp0_unimplemented; 5159 } 5160 break; 5161 case CP0_REGISTER_09: 5162 switch (sel) { 5163 case CP0_REG09__SAAR: 5164 CP0_CHECK(ctx->saar); 5165 gen_helper_mfhc0_saar(arg, cpu_env); 5166 register_name = "SAAR"; 5167 break; 5168 default: 5169 goto cp0_unimplemented; 5170 } 5171 break; 5172 case CP0_REGISTER_17: 5173 switch (sel) { 5174 case CP0_REG17__LLADDR: 5175 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_LLAddr), 5176 ctx->CP0_LLAddr_shift); 5177 register_name = "LLAddr"; 5178 break; 5179 case CP0_REG17__MAAR: 5180 CP0_CHECK(ctx->mrp); 5181 gen_helper_mfhc0_maar(arg, cpu_env); 5182 register_name = "MAAR"; 5183 break; 5184 default: 5185 goto cp0_unimplemented; 5186 } 5187 break; 5188 case CP0_REGISTER_19: 5189 switch (sel) { 5190 case CP0_REG19__WATCHHI0: 5191 case CP0_REG19__WATCHHI1: 5192 case CP0_REG19__WATCHHI2: 5193 case CP0_REG19__WATCHHI3: 5194 case CP0_REG19__WATCHHI4: 5195 case CP0_REG19__WATCHHI5: 5196 case CP0_REG19__WATCHHI6: 5197 case CP0_REG19__WATCHHI7: 5198 /* upper 32 bits are only available when Config5MI != 0 */ 5199 CP0_CHECK(ctx->mi); 5200 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_WatchHi[sel]), 0); 5201 register_name = "WatchHi"; 5202 break; 5203 default: 5204 goto cp0_unimplemented; 5205 } 5206 break; 5207 case CP0_REGISTER_28: 5208 switch (sel) { 5209 case 0: 5210 case 2: 5211 case 4: 5212 case 6: 5213 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_TagLo), 0); 5214 register_name = "TagLo"; 5215 break; 5216 default: 5217 goto cp0_unimplemented; 5218 } 5219 break; 5220 default: 5221 goto cp0_unimplemented; 5222 } 5223 trace_mips_translate_c0("mfhc0", register_name, reg, sel); 5224 return; 5225 5226 cp0_unimplemented: 5227 qemu_log_mask(LOG_UNIMP, "mfhc0 %s (reg %d sel %d)\n", 5228 register_name, reg, sel); 5229 tcg_gen_movi_tl(arg, 0); 5230 } 5231 5232 static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel) 5233 { 5234 const char *register_name = "invalid"; 5235 uint64_t mask = ctx->PAMask >> 36; 5236 5237 switch (reg) { 5238 case CP0_REGISTER_02: 5239 switch (sel) { 5240 case 0: 5241 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); 5242 tcg_gen_andi_tl(arg, arg, mask); 5243 gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0)); 5244 register_name = "EntryLo0"; 5245 break; 5246 default: 5247 goto cp0_unimplemented; 5248 } 5249 break; 5250 case CP0_REGISTER_03: 5251 switch (sel) { 5252 case CP0_REG03__ENTRYLO1: 5253 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); 5254 tcg_gen_andi_tl(arg, arg, mask); 5255 gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1)); 5256 register_name = "EntryLo1"; 5257 break; 5258 default: 5259 goto cp0_unimplemented; 5260 } 5261 break; 5262 case CP0_REGISTER_09: 5263 switch (sel) { 5264 case CP0_REG09__SAAR: 5265 CP0_CHECK(ctx->saar); 5266 gen_helper_mthc0_saar(cpu_env, arg); 5267 register_name = "SAAR"; 5268 break; 5269 default: 5270 goto cp0_unimplemented; 5271 } 5272 break; 5273 case CP0_REGISTER_17: 5274 switch (sel) { 5275 case CP0_REG17__LLADDR: 5276 /* 5277 * LLAddr is read-only (the only exception is bit 0 if LLB is 5278 * supported); the CP0_LLAddr_rw_bitmask does not seem to be 5279 * relevant for modern MIPS cores supporting MTHC0, therefore 5280 * treating MTHC0 to LLAddr as NOP. 5281 */ 5282 register_name = "LLAddr"; 5283 break; 5284 case CP0_REG17__MAAR: 5285 CP0_CHECK(ctx->mrp); 5286 gen_helper_mthc0_maar(cpu_env, arg); 5287 register_name = "MAAR"; 5288 break; 5289 default: 5290 goto cp0_unimplemented; 5291 } 5292 break; 5293 case CP0_REGISTER_19: 5294 switch (sel) { 5295 case CP0_REG19__WATCHHI0: 5296 case CP0_REG19__WATCHHI1: 5297 case CP0_REG19__WATCHHI2: 5298 case CP0_REG19__WATCHHI3: 5299 case CP0_REG19__WATCHHI4: 5300 case CP0_REG19__WATCHHI5: 5301 case CP0_REG19__WATCHHI6: 5302 case CP0_REG19__WATCHHI7: 5303 /* upper 32 bits are only available when Config5MI != 0 */ 5304 CP0_CHECK(ctx->mi); 5305 gen_helper_0e1i(mthc0_watchhi, arg, sel); 5306 register_name = "WatchHi"; 5307 break; 5308 default: 5309 goto cp0_unimplemented; 5310 } 5311 break; 5312 case CP0_REGISTER_28: 5313 switch (sel) { 5314 case 0: 5315 case 2: 5316 case 4: 5317 case 6: 5318 tcg_gen_andi_tl(arg, arg, mask); 5319 gen_mthc0_store64(arg, offsetof(CPUMIPSState, CP0_TagLo)); 5320 register_name = "TagLo"; 5321 break; 5322 default: 5323 goto cp0_unimplemented; 5324 } 5325 break; 5326 default: 5327 goto cp0_unimplemented; 5328 } 5329 trace_mips_translate_c0("mthc0", register_name, reg, sel); 5330 return; 5331 5332 cp0_unimplemented: 5333 qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n", 5334 register_name, reg, sel); 5335 } 5336 5337 static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg) 5338 { 5339 if (ctx->insn_flags & ISA_MIPS_R6) { 5340 tcg_gen_movi_tl(arg, 0); 5341 } else { 5342 tcg_gen_movi_tl(arg, ~0); 5343 } 5344 } 5345 5346 static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) 5347 { 5348 const char *register_name = "invalid"; 5349 5350 if (sel != 0) { 5351 check_insn(ctx, ISA_MIPS_R1); 5352 } 5353 5354 switch (reg) { 5355 case CP0_REGISTER_00: 5356 switch (sel) { 5357 case CP0_REG00__INDEX: 5358 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index)); 5359 register_name = "Index"; 5360 break; 5361 case CP0_REG00__MVPCONTROL: 5362 CP0_CHECK(ctx->insn_flags & ASE_MT); 5363 gen_helper_mfc0_mvpcontrol(arg, cpu_env); 5364 register_name = "MVPControl"; 5365 break; 5366 case CP0_REG00__MVPCONF0: 5367 CP0_CHECK(ctx->insn_flags & ASE_MT); 5368 gen_helper_mfc0_mvpconf0(arg, cpu_env); 5369 register_name = "MVPConf0"; 5370 break; 5371 case CP0_REG00__MVPCONF1: 5372 CP0_CHECK(ctx->insn_flags & ASE_MT); 5373 gen_helper_mfc0_mvpconf1(arg, cpu_env); 5374 register_name = "MVPConf1"; 5375 break; 5376 case CP0_REG00__VPCONTROL: 5377 CP0_CHECK(ctx->vp); 5378 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl)); 5379 register_name = "VPControl"; 5380 break; 5381 default: 5382 goto cp0_unimplemented; 5383 } 5384 break; 5385 case CP0_REGISTER_01: 5386 switch (sel) { 5387 case CP0_REG01__RANDOM: 5388 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 5389 gen_helper_mfc0_random(arg, cpu_env); 5390 register_name = "Random"; 5391 break; 5392 case CP0_REG01__VPECONTROL: 5393 CP0_CHECK(ctx->insn_flags & ASE_MT); 5394 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl)); 5395 register_name = "VPEControl"; 5396 break; 5397 case CP0_REG01__VPECONF0: 5398 CP0_CHECK(ctx->insn_flags & ASE_MT); 5399 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0)); 5400 register_name = "VPEConf0"; 5401 break; 5402 case CP0_REG01__VPECONF1: 5403 CP0_CHECK(ctx->insn_flags & ASE_MT); 5404 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1)); 5405 register_name = "VPEConf1"; 5406 break; 5407 case CP0_REG01__YQMASK: 5408 CP0_CHECK(ctx->insn_flags & ASE_MT); 5409 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask)); 5410 register_name = "YQMask"; 5411 break; 5412 case CP0_REG01__VPESCHEDULE: 5413 CP0_CHECK(ctx->insn_flags & ASE_MT); 5414 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule)); 5415 register_name = "VPESchedule"; 5416 break; 5417 case CP0_REG01__VPESCHEFBACK: 5418 CP0_CHECK(ctx->insn_flags & ASE_MT); 5419 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack)); 5420 register_name = "VPEScheFBack"; 5421 break; 5422 case CP0_REG01__VPEOPT: 5423 CP0_CHECK(ctx->insn_flags & ASE_MT); 5424 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt)); 5425 register_name = "VPEOpt"; 5426 break; 5427 default: 5428 goto cp0_unimplemented; 5429 } 5430 break; 5431 case CP0_REGISTER_02: 5432 switch (sel) { 5433 case CP0_REG02__ENTRYLO0: 5434 { 5435 TCGv_i64 tmp = tcg_temp_new_i64(); 5436 tcg_gen_ld_i64(tmp, cpu_env, 5437 offsetof(CPUMIPSState, CP0_EntryLo0)); 5438 #if defined(TARGET_MIPS64) 5439 if (ctx->rxi) { 5440 /* Move RI/XI fields to bits 31:30 */ 5441 tcg_gen_shri_tl(arg, tmp, CP0EnLo_XI); 5442 tcg_gen_deposit_tl(tmp, tmp, arg, 30, 2); 5443 } 5444 #endif 5445 gen_move_low32(arg, tmp); 5446 } 5447 register_name = "EntryLo0"; 5448 break; 5449 case CP0_REG02__TCSTATUS: 5450 CP0_CHECK(ctx->insn_flags & ASE_MT); 5451 gen_helper_mfc0_tcstatus(arg, cpu_env); 5452 register_name = "TCStatus"; 5453 break; 5454 case CP0_REG02__TCBIND: 5455 CP0_CHECK(ctx->insn_flags & ASE_MT); 5456 gen_helper_mfc0_tcbind(arg, cpu_env); 5457 register_name = "TCBind"; 5458 break; 5459 case CP0_REG02__TCRESTART: 5460 CP0_CHECK(ctx->insn_flags & ASE_MT); 5461 gen_helper_mfc0_tcrestart(arg, cpu_env); 5462 register_name = "TCRestart"; 5463 break; 5464 case CP0_REG02__TCHALT: 5465 CP0_CHECK(ctx->insn_flags & ASE_MT); 5466 gen_helper_mfc0_tchalt(arg, cpu_env); 5467 register_name = "TCHalt"; 5468 break; 5469 case CP0_REG02__TCCONTEXT: 5470 CP0_CHECK(ctx->insn_flags & ASE_MT); 5471 gen_helper_mfc0_tccontext(arg, cpu_env); 5472 register_name = "TCContext"; 5473 break; 5474 case CP0_REG02__TCSCHEDULE: 5475 CP0_CHECK(ctx->insn_flags & ASE_MT); 5476 gen_helper_mfc0_tcschedule(arg, cpu_env); 5477 register_name = "TCSchedule"; 5478 break; 5479 case CP0_REG02__TCSCHEFBACK: 5480 CP0_CHECK(ctx->insn_flags & ASE_MT); 5481 gen_helper_mfc0_tcschefback(arg, cpu_env); 5482 register_name = "TCScheFBack"; 5483 break; 5484 default: 5485 goto cp0_unimplemented; 5486 } 5487 break; 5488 case CP0_REGISTER_03: 5489 switch (sel) { 5490 case CP0_REG03__ENTRYLO1: 5491 { 5492 TCGv_i64 tmp = tcg_temp_new_i64(); 5493 tcg_gen_ld_i64(tmp, cpu_env, 5494 offsetof(CPUMIPSState, CP0_EntryLo1)); 5495 #if defined(TARGET_MIPS64) 5496 if (ctx->rxi) { 5497 /* Move RI/XI fields to bits 31:30 */ 5498 tcg_gen_shri_tl(arg, tmp, CP0EnLo_XI); 5499 tcg_gen_deposit_tl(tmp, tmp, arg, 30, 2); 5500 } 5501 #endif 5502 gen_move_low32(arg, tmp); 5503 } 5504 register_name = "EntryLo1"; 5505 break; 5506 case CP0_REG03__GLOBALNUM: 5507 CP0_CHECK(ctx->vp); 5508 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber)); 5509 register_name = "GlobalNumber"; 5510 break; 5511 default: 5512 goto cp0_unimplemented; 5513 } 5514 break; 5515 case CP0_REGISTER_04: 5516 switch (sel) { 5517 case CP0_REG04__CONTEXT: 5518 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context)); 5519 tcg_gen_ext32s_tl(arg, arg); 5520 register_name = "Context"; 5521 break; 5522 case CP0_REG04__CONTEXTCONFIG: 5523 /* SmartMIPS ASE */ 5524 /* gen_helper_mfc0_contextconfig(arg); */ 5525 register_name = "ContextConfig"; 5526 goto cp0_unimplemented; 5527 case CP0_REG04__USERLOCAL: 5528 CP0_CHECK(ctx->ulri); 5529 tcg_gen_ld_tl(arg, cpu_env, 5530 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 5531 tcg_gen_ext32s_tl(arg, arg); 5532 register_name = "UserLocal"; 5533 break; 5534 case CP0_REG04__MMID: 5535 CP0_CHECK(ctx->mi); 5536 gen_helper_mtc0_memorymapid(cpu_env, arg); 5537 register_name = "MMID"; 5538 break; 5539 default: 5540 goto cp0_unimplemented; 5541 } 5542 break; 5543 case CP0_REGISTER_05: 5544 switch (sel) { 5545 case CP0_REG05__PAGEMASK: 5546 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask)); 5547 register_name = "PageMask"; 5548 break; 5549 case CP0_REG05__PAGEGRAIN: 5550 check_insn(ctx, ISA_MIPS_R2); 5551 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); 5552 register_name = "PageGrain"; 5553 break; 5554 case CP0_REG05__SEGCTL0: 5555 CP0_CHECK(ctx->sc); 5556 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0)); 5557 tcg_gen_ext32s_tl(arg, arg); 5558 register_name = "SegCtl0"; 5559 break; 5560 case CP0_REG05__SEGCTL1: 5561 CP0_CHECK(ctx->sc); 5562 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1)); 5563 tcg_gen_ext32s_tl(arg, arg); 5564 register_name = "SegCtl1"; 5565 break; 5566 case CP0_REG05__SEGCTL2: 5567 CP0_CHECK(ctx->sc); 5568 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2)); 5569 tcg_gen_ext32s_tl(arg, arg); 5570 register_name = "SegCtl2"; 5571 break; 5572 case CP0_REG05__PWBASE: 5573 check_pw(ctx); 5574 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase)); 5575 register_name = "PWBase"; 5576 break; 5577 case CP0_REG05__PWFIELD: 5578 check_pw(ctx); 5579 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField)); 5580 register_name = "PWField"; 5581 break; 5582 case CP0_REG05__PWSIZE: 5583 check_pw(ctx); 5584 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize)); 5585 register_name = "PWSize"; 5586 break; 5587 default: 5588 goto cp0_unimplemented; 5589 } 5590 break; 5591 case CP0_REGISTER_06: 5592 switch (sel) { 5593 case CP0_REG06__WIRED: 5594 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired)); 5595 register_name = "Wired"; 5596 break; 5597 case CP0_REG06__SRSCONF0: 5598 check_insn(ctx, ISA_MIPS_R2); 5599 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); 5600 register_name = "SRSConf0"; 5601 break; 5602 case CP0_REG06__SRSCONF1: 5603 check_insn(ctx, ISA_MIPS_R2); 5604 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); 5605 register_name = "SRSConf1"; 5606 break; 5607 case CP0_REG06__SRSCONF2: 5608 check_insn(ctx, ISA_MIPS_R2); 5609 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); 5610 register_name = "SRSConf2"; 5611 break; 5612 case CP0_REG06__SRSCONF3: 5613 check_insn(ctx, ISA_MIPS_R2); 5614 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); 5615 register_name = "SRSConf3"; 5616 break; 5617 case CP0_REG06__SRSCONF4: 5618 check_insn(ctx, ISA_MIPS_R2); 5619 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); 5620 register_name = "SRSConf4"; 5621 break; 5622 case CP0_REG06__PWCTL: 5623 check_pw(ctx); 5624 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl)); 5625 register_name = "PWCtl"; 5626 break; 5627 default: 5628 goto cp0_unimplemented; 5629 } 5630 break; 5631 case CP0_REGISTER_07: 5632 switch (sel) { 5633 case CP0_REG07__HWRENA: 5634 check_insn(ctx, ISA_MIPS_R2); 5635 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); 5636 register_name = "HWREna"; 5637 break; 5638 default: 5639 goto cp0_unimplemented; 5640 } 5641 break; 5642 case CP0_REGISTER_08: 5643 switch (sel) { 5644 case CP0_REG08__BADVADDR: 5645 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); 5646 tcg_gen_ext32s_tl(arg, arg); 5647 register_name = "BadVAddr"; 5648 break; 5649 case CP0_REG08__BADINSTR: 5650 CP0_CHECK(ctx->bi); 5651 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr)); 5652 register_name = "BadInstr"; 5653 break; 5654 case CP0_REG08__BADINSTRP: 5655 CP0_CHECK(ctx->bp); 5656 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP)); 5657 register_name = "BadInstrP"; 5658 break; 5659 case CP0_REG08__BADINSTRX: 5660 CP0_CHECK(ctx->bi); 5661 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX)); 5662 tcg_gen_andi_tl(arg, arg, ~0xffff); 5663 register_name = "BadInstrX"; 5664 break; 5665 default: 5666 goto cp0_unimplemented; 5667 } 5668 break; 5669 case CP0_REGISTER_09: 5670 switch (sel) { 5671 case CP0_REG09__COUNT: 5672 /* Mark as an IO operation because we read the time. */ 5673 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 5674 gen_io_start(); 5675 } 5676 gen_helper_mfc0_count(arg, cpu_env); 5677 /* 5678 * Break the TB to be able to take timer interrupts immediately 5679 * after reading count. DISAS_STOP isn't sufficient, we need to 5680 * ensure we break completely out of translated code. 5681 */ 5682 gen_save_pc(ctx->base.pc_next + 4); 5683 ctx->base.is_jmp = DISAS_EXIT; 5684 register_name = "Count"; 5685 break; 5686 case CP0_REG09__SAARI: 5687 CP0_CHECK(ctx->saar); 5688 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); 5689 register_name = "SAARI"; 5690 break; 5691 case CP0_REG09__SAAR: 5692 CP0_CHECK(ctx->saar); 5693 gen_helper_mfc0_saar(arg, cpu_env); 5694 register_name = "SAAR"; 5695 break; 5696 default: 5697 goto cp0_unimplemented; 5698 } 5699 break; 5700 case CP0_REGISTER_10: 5701 switch (sel) { 5702 case CP0_REG10__ENTRYHI: 5703 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi)); 5704 tcg_gen_ext32s_tl(arg, arg); 5705 register_name = "EntryHi"; 5706 break; 5707 default: 5708 goto cp0_unimplemented; 5709 } 5710 break; 5711 case CP0_REGISTER_11: 5712 switch (sel) { 5713 case CP0_REG11__COMPARE: 5714 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare)); 5715 register_name = "Compare"; 5716 break; 5717 /* 6,7 are implementation dependent */ 5718 default: 5719 goto cp0_unimplemented; 5720 } 5721 break; 5722 case CP0_REGISTER_12: 5723 switch (sel) { 5724 case CP0_REG12__STATUS: 5725 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status)); 5726 register_name = "Status"; 5727 break; 5728 case CP0_REG12__INTCTL: 5729 check_insn(ctx, ISA_MIPS_R2); 5730 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); 5731 register_name = "IntCtl"; 5732 break; 5733 case CP0_REG12__SRSCTL: 5734 check_insn(ctx, ISA_MIPS_R2); 5735 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); 5736 register_name = "SRSCtl"; 5737 break; 5738 case CP0_REG12__SRSMAP: 5739 check_insn(ctx, ISA_MIPS_R2); 5740 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); 5741 register_name = "SRSMap"; 5742 break; 5743 default: 5744 goto cp0_unimplemented; 5745 } 5746 break; 5747 case CP0_REGISTER_13: 5748 switch (sel) { 5749 case CP0_REG13__CAUSE: 5750 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause)); 5751 register_name = "Cause"; 5752 break; 5753 default: 5754 goto cp0_unimplemented; 5755 } 5756 break; 5757 case CP0_REGISTER_14: 5758 switch (sel) { 5759 case CP0_REG14__EPC: 5760 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC)); 5761 tcg_gen_ext32s_tl(arg, arg); 5762 register_name = "EPC"; 5763 break; 5764 default: 5765 goto cp0_unimplemented; 5766 } 5767 break; 5768 case CP0_REGISTER_15: 5769 switch (sel) { 5770 case CP0_REG15__PRID: 5771 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid)); 5772 register_name = "PRid"; 5773 break; 5774 case CP0_REG15__EBASE: 5775 check_insn(ctx, ISA_MIPS_R2); 5776 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); 5777 tcg_gen_ext32s_tl(arg, arg); 5778 register_name = "EBase"; 5779 break; 5780 case CP0_REG15__CMGCRBASE: 5781 check_insn(ctx, ISA_MIPS_R2); 5782 CP0_CHECK(ctx->cmgcr); 5783 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase)); 5784 tcg_gen_ext32s_tl(arg, arg); 5785 register_name = "CMGCRBase"; 5786 break; 5787 default: 5788 goto cp0_unimplemented; 5789 } 5790 break; 5791 case CP0_REGISTER_16: 5792 switch (sel) { 5793 case CP0_REG16__CONFIG: 5794 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0)); 5795 register_name = "Config"; 5796 break; 5797 case CP0_REG16__CONFIG1: 5798 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1)); 5799 register_name = "Config1"; 5800 break; 5801 case CP0_REG16__CONFIG2: 5802 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2)); 5803 register_name = "Config2"; 5804 break; 5805 case CP0_REG16__CONFIG3: 5806 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3)); 5807 register_name = "Config3"; 5808 break; 5809 case CP0_REG16__CONFIG4: 5810 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4)); 5811 register_name = "Config4"; 5812 break; 5813 case CP0_REG16__CONFIG5: 5814 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5)); 5815 register_name = "Config5"; 5816 break; 5817 /* 6,7 are implementation dependent */ 5818 case CP0_REG16__CONFIG6: 5819 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6)); 5820 register_name = "Config6"; 5821 break; 5822 case CP0_REG16__CONFIG7: 5823 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7)); 5824 register_name = "Config7"; 5825 break; 5826 default: 5827 goto cp0_unimplemented; 5828 } 5829 break; 5830 case CP0_REGISTER_17: 5831 switch (sel) { 5832 case CP0_REG17__LLADDR: 5833 gen_helper_mfc0_lladdr(arg, cpu_env); 5834 register_name = "LLAddr"; 5835 break; 5836 case CP0_REG17__MAAR: 5837 CP0_CHECK(ctx->mrp); 5838 gen_helper_mfc0_maar(arg, cpu_env); 5839 register_name = "MAAR"; 5840 break; 5841 case CP0_REG17__MAARI: 5842 CP0_CHECK(ctx->mrp); 5843 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI)); 5844 register_name = "MAARI"; 5845 break; 5846 default: 5847 goto cp0_unimplemented; 5848 } 5849 break; 5850 case CP0_REGISTER_18: 5851 switch (sel) { 5852 case CP0_REG18__WATCHLO0: 5853 case CP0_REG18__WATCHLO1: 5854 case CP0_REG18__WATCHLO2: 5855 case CP0_REG18__WATCHLO3: 5856 case CP0_REG18__WATCHLO4: 5857 case CP0_REG18__WATCHLO5: 5858 case CP0_REG18__WATCHLO6: 5859 case CP0_REG18__WATCHLO7: 5860 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 5861 gen_helper_1e0i(mfc0_watchlo, arg, sel); 5862 register_name = "WatchLo"; 5863 break; 5864 default: 5865 goto cp0_unimplemented; 5866 } 5867 break; 5868 case CP0_REGISTER_19: 5869 switch (sel) { 5870 case CP0_REG19__WATCHHI0: 5871 case CP0_REG19__WATCHHI1: 5872 case CP0_REG19__WATCHHI2: 5873 case CP0_REG19__WATCHHI3: 5874 case CP0_REG19__WATCHHI4: 5875 case CP0_REG19__WATCHHI5: 5876 case CP0_REG19__WATCHHI6: 5877 case CP0_REG19__WATCHHI7: 5878 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 5879 gen_helper_1e0i(mfc0_watchhi, arg, sel); 5880 register_name = "WatchHi"; 5881 break; 5882 default: 5883 goto cp0_unimplemented; 5884 } 5885 break; 5886 case CP0_REGISTER_20: 5887 switch (sel) { 5888 case CP0_REG20__XCONTEXT: 5889 #if defined(TARGET_MIPS64) 5890 check_insn(ctx, ISA_MIPS3); 5891 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext)); 5892 tcg_gen_ext32s_tl(arg, arg); 5893 register_name = "XContext"; 5894 break; 5895 #endif 5896 default: 5897 goto cp0_unimplemented; 5898 } 5899 break; 5900 case CP0_REGISTER_21: 5901 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 5902 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 5903 switch (sel) { 5904 case 0: 5905 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask)); 5906 register_name = "Framemask"; 5907 break; 5908 default: 5909 goto cp0_unimplemented; 5910 } 5911 break; 5912 case CP0_REGISTER_22: 5913 tcg_gen_movi_tl(arg, 0); /* unimplemented */ 5914 register_name = "'Diagnostic"; /* implementation dependent */ 5915 break; 5916 case CP0_REGISTER_23: 5917 switch (sel) { 5918 case CP0_REG23__DEBUG: 5919 gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */ 5920 register_name = "Debug"; 5921 break; 5922 case CP0_REG23__TRACECONTROL: 5923 /* PDtrace support */ 5924 /* gen_helper_mfc0_tracecontrol(arg); */ 5925 register_name = "TraceControl"; 5926 goto cp0_unimplemented; 5927 case CP0_REG23__TRACECONTROL2: 5928 /* PDtrace support */ 5929 /* gen_helper_mfc0_tracecontrol2(arg); */ 5930 register_name = "TraceControl2"; 5931 goto cp0_unimplemented; 5932 case CP0_REG23__USERTRACEDATA1: 5933 /* PDtrace support */ 5934 /* gen_helper_mfc0_usertracedata1(arg);*/ 5935 register_name = "UserTraceData1"; 5936 goto cp0_unimplemented; 5937 case CP0_REG23__TRACEIBPC: 5938 /* PDtrace support */ 5939 /* gen_helper_mfc0_traceibpc(arg); */ 5940 register_name = "TraceIBPC"; 5941 goto cp0_unimplemented; 5942 case CP0_REG23__TRACEDBPC: 5943 /* PDtrace support */ 5944 /* gen_helper_mfc0_tracedbpc(arg); */ 5945 register_name = "TraceDBPC"; 5946 goto cp0_unimplemented; 5947 default: 5948 goto cp0_unimplemented; 5949 } 5950 break; 5951 case CP0_REGISTER_24: 5952 switch (sel) { 5953 case CP0_REG24__DEPC: 5954 /* EJTAG support */ 5955 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC)); 5956 tcg_gen_ext32s_tl(arg, arg); 5957 register_name = "DEPC"; 5958 break; 5959 default: 5960 goto cp0_unimplemented; 5961 } 5962 break; 5963 case CP0_REGISTER_25: 5964 switch (sel) { 5965 case CP0_REG25__PERFCTL0: 5966 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0)); 5967 register_name = "Performance0"; 5968 break; 5969 case CP0_REG25__PERFCNT0: 5970 /* gen_helper_mfc0_performance1(arg); */ 5971 register_name = "Performance1"; 5972 goto cp0_unimplemented; 5973 case CP0_REG25__PERFCTL1: 5974 /* gen_helper_mfc0_performance2(arg); */ 5975 register_name = "Performance2"; 5976 goto cp0_unimplemented; 5977 case CP0_REG25__PERFCNT1: 5978 /* gen_helper_mfc0_performance3(arg); */ 5979 register_name = "Performance3"; 5980 goto cp0_unimplemented; 5981 case CP0_REG25__PERFCTL2: 5982 /* gen_helper_mfc0_performance4(arg); */ 5983 register_name = "Performance4"; 5984 goto cp0_unimplemented; 5985 case CP0_REG25__PERFCNT2: 5986 /* gen_helper_mfc0_performance5(arg); */ 5987 register_name = "Performance5"; 5988 goto cp0_unimplemented; 5989 case CP0_REG25__PERFCTL3: 5990 /* gen_helper_mfc0_performance6(arg); */ 5991 register_name = "Performance6"; 5992 goto cp0_unimplemented; 5993 case CP0_REG25__PERFCNT3: 5994 /* gen_helper_mfc0_performance7(arg); */ 5995 register_name = "Performance7"; 5996 goto cp0_unimplemented; 5997 default: 5998 goto cp0_unimplemented; 5999 } 6000 break; 6001 case CP0_REGISTER_26: 6002 switch (sel) { 6003 case CP0_REG26__ERRCTL: 6004 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl)); 6005 register_name = "ErrCtl"; 6006 break; 6007 default: 6008 goto cp0_unimplemented; 6009 } 6010 break; 6011 case CP0_REGISTER_27: 6012 switch (sel) { 6013 case CP0_REG27__CACHERR: 6014 tcg_gen_movi_tl(arg, 0); /* unimplemented */ 6015 register_name = "CacheErr"; 6016 break; 6017 default: 6018 goto cp0_unimplemented; 6019 } 6020 break; 6021 case CP0_REGISTER_28: 6022 switch (sel) { 6023 case CP0_REG28__TAGLO: 6024 case CP0_REG28__TAGLO1: 6025 case CP0_REG28__TAGLO2: 6026 case CP0_REG28__TAGLO3: 6027 { 6028 TCGv_i64 tmp = tcg_temp_new_i64(); 6029 tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState, CP0_TagLo)); 6030 gen_move_low32(arg, tmp); 6031 } 6032 register_name = "TagLo"; 6033 break; 6034 case CP0_REG28__DATALO: 6035 case CP0_REG28__DATALO1: 6036 case CP0_REG28__DATALO2: 6037 case CP0_REG28__DATALO3: 6038 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo)); 6039 register_name = "DataLo"; 6040 break; 6041 default: 6042 goto cp0_unimplemented; 6043 } 6044 break; 6045 case CP0_REGISTER_29: 6046 switch (sel) { 6047 case CP0_REG29__TAGHI: 6048 case CP0_REG29__TAGHI1: 6049 case CP0_REG29__TAGHI2: 6050 case CP0_REG29__TAGHI3: 6051 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi)); 6052 register_name = "TagHi"; 6053 break; 6054 case CP0_REG29__DATAHI: 6055 case CP0_REG29__DATAHI1: 6056 case CP0_REG29__DATAHI2: 6057 case CP0_REG29__DATAHI3: 6058 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi)); 6059 register_name = "DataHi"; 6060 break; 6061 default: 6062 goto cp0_unimplemented; 6063 } 6064 break; 6065 case CP0_REGISTER_30: 6066 switch (sel) { 6067 case CP0_REG30__ERROREPC: 6068 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); 6069 tcg_gen_ext32s_tl(arg, arg); 6070 register_name = "ErrorEPC"; 6071 break; 6072 default: 6073 goto cp0_unimplemented; 6074 } 6075 break; 6076 case CP0_REGISTER_31: 6077 switch (sel) { 6078 case CP0_REG31__DESAVE: 6079 /* EJTAG support */ 6080 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); 6081 register_name = "DESAVE"; 6082 break; 6083 case CP0_REG31__KSCRATCH1: 6084 case CP0_REG31__KSCRATCH2: 6085 case CP0_REG31__KSCRATCH3: 6086 case CP0_REG31__KSCRATCH4: 6087 case CP0_REG31__KSCRATCH5: 6088 case CP0_REG31__KSCRATCH6: 6089 CP0_CHECK(ctx->kscrexist & (1 << sel)); 6090 tcg_gen_ld_tl(arg, cpu_env, 6091 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); 6092 tcg_gen_ext32s_tl(arg, arg); 6093 register_name = "KScratch"; 6094 break; 6095 default: 6096 goto cp0_unimplemented; 6097 } 6098 break; 6099 default: 6100 goto cp0_unimplemented; 6101 } 6102 trace_mips_translate_c0("mfc0", register_name, reg, sel); 6103 return; 6104 6105 cp0_unimplemented: 6106 qemu_log_mask(LOG_UNIMP, "mfc0 %s (reg %d sel %d)\n", 6107 register_name, reg, sel); 6108 gen_mfc0_unimplemented(ctx, arg); 6109 } 6110 6111 static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) 6112 { 6113 const char *register_name = "invalid"; 6114 6115 if (sel != 0) { 6116 check_insn(ctx, ISA_MIPS_R1); 6117 } 6118 6119 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 6120 gen_io_start(); 6121 } 6122 6123 switch (reg) { 6124 case CP0_REGISTER_00: 6125 switch (sel) { 6126 case CP0_REG00__INDEX: 6127 gen_helper_mtc0_index(cpu_env, arg); 6128 register_name = "Index"; 6129 break; 6130 case CP0_REG00__MVPCONTROL: 6131 CP0_CHECK(ctx->insn_flags & ASE_MT); 6132 gen_helper_mtc0_mvpcontrol(cpu_env, arg); 6133 register_name = "MVPControl"; 6134 break; 6135 case CP0_REG00__MVPCONF0: 6136 CP0_CHECK(ctx->insn_flags & ASE_MT); 6137 /* ignored */ 6138 register_name = "MVPConf0"; 6139 break; 6140 case CP0_REG00__MVPCONF1: 6141 CP0_CHECK(ctx->insn_flags & ASE_MT); 6142 /* ignored */ 6143 register_name = "MVPConf1"; 6144 break; 6145 case CP0_REG00__VPCONTROL: 6146 CP0_CHECK(ctx->vp); 6147 /* ignored */ 6148 register_name = "VPControl"; 6149 break; 6150 default: 6151 goto cp0_unimplemented; 6152 } 6153 break; 6154 case CP0_REGISTER_01: 6155 switch (sel) { 6156 case CP0_REG01__RANDOM: 6157 /* ignored */ 6158 register_name = "Random"; 6159 break; 6160 case CP0_REG01__VPECONTROL: 6161 CP0_CHECK(ctx->insn_flags & ASE_MT); 6162 gen_helper_mtc0_vpecontrol(cpu_env, arg); 6163 register_name = "VPEControl"; 6164 break; 6165 case CP0_REG01__VPECONF0: 6166 CP0_CHECK(ctx->insn_flags & ASE_MT); 6167 gen_helper_mtc0_vpeconf0(cpu_env, arg); 6168 register_name = "VPEConf0"; 6169 break; 6170 case CP0_REG01__VPECONF1: 6171 CP0_CHECK(ctx->insn_flags & ASE_MT); 6172 gen_helper_mtc0_vpeconf1(cpu_env, arg); 6173 register_name = "VPEConf1"; 6174 break; 6175 case CP0_REG01__YQMASK: 6176 CP0_CHECK(ctx->insn_flags & ASE_MT); 6177 gen_helper_mtc0_yqmask(cpu_env, arg); 6178 register_name = "YQMask"; 6179 break; 6180 case CP0_REG01__VPESCHEDULE: 6181 CP0_CHECK(ctx->insn_flags & ASE_MT); 6182 tcg_gen_st_tl(arg, cpu_env, 6183 offsetof(CPUMIPSState, CP0_VPESchedule)); 6184 register_name = "VPESchedule"; 6185 break; 6186 case CP0_REG01__VPESCHEFBACK: 6187 CP0_CHECK(ctx->insn_flags & ASE_MT); 6188 tcg_gen_st_tl(arg, cpu_env, 6189 offsetof(CPUMIPSState, CP0_VPEScheFBack)); 6190 register_name = "VPEScheFBack"; 6191 break; 6192 case CP0_REG01__VPEOPT: 6193 CP0_CHECK(ctx->insn_flags & ASE_MT); 6194 gen_helper_mtc0_vpeopt(cpu_env, arg); 6195 register_name = "VPEOpt"; 6196 break; 6197 default: 6198 goto cp0_unimplemented; 6199 } 6200 break; 6201 case CP0_REGISTER_02: 6202 switch (sel) { 6203 case CP0_REG02__ENTRYLO0: 6204 gen_helper_mtc0_entrylo0(cpu_env, arg); 6205 register_name = "EntryLo0"; 6206 break; 6207 case CP0_REG02__TCSTATUS: 6208 CP0_CHECK(ctx->insn_flags & ASE_MT); 6209 gen_helper_mtc0_tcstatus(cpu_env, arg); 6210 register_name = "TCStatus"; 6211 break; 6212 case CP0_REG02__TCBIND: 6213 CP0_CHECK(ctx->insn_flags & ASE_MT); 6214 gen_helper_mtc0_tcbind(cpu_env, arg); 6215 register_name = "TCBind"; 6216 break; 6217 case CP0_REG02__TCRESTART: 6218 CP0_CHECK(ctx->insn_flags & ASE_MT); 6219 gen_helper_mtc0_tcrestart(cpu_env, arg); 6220 register_name = "TCRestart"; 6221 break; 6222 case CP0_REG02__TCHALT: 6223 CP0_CHECK(ctx->insn_flags & ASE_MT); 6224 gen_helper_mtc0_tchalt(cpu_env, arg); 6225 register_name = "TCHalt"; 6226 break; 6227 case CP0_REG02__TCCONTEXT: 6228 CP0_CHECK(ctx->insn_flags & ASE_MT); 6229 gen_helper_mtc0_tccontext(cpu_env, arg); 6230 register_name = "TCContext"; 6231 break; 6232 case CP0_REG02__TCSCHEDULE: 6233 CP0_CHECK(ctx->insn_flags & ASE_MT); 6234 gen_helper_mtc0_tcschedule(cpu_env, arg); 6235 register_name = "TCSchedule"; 6236 break; 6237 case CP0_REG02__TCSCHEFBACK: 6238 CP0_CHECK(ctx->insn_flags & ASE_MT); 6239 gen_helper_mtc0_tcschefback(cpu_env, arg); 6240 register_name = "TCScheFBack"; 6241 break; 6242 default: 6243 goto cp0_unimplemented; 6244 } 6245 break; 6246 case CP0_REGISTER_03: 6247 switch (sel) { 6248 case CP0_REG03__ENTRYLO1: 6249 gen_helper_mtc0_entrylo1(cpu_env, arg); 6250 register_name = "EntryLo1"; 6251 break; 6252 case CP0_REG03__GLOBALNUM: 6253 CP0_CHECK(ctx->vp); 6254 /* ignored */ 6255 register_name = "GlobalNumber"; 6256 break; 6257 default: 6258 goto cp0_unimplemented; 6259 } 6260 break; 6261 case CP0_REGISTER_04: 6262 switch (sel) { 6263 case CP0_REG04__CONTEXT: 6264 gen_helper_mtc0_context(cpu_env, arg); 6265 register_name = "Context"; 6266 break; 6267 case CP0_REG04__CONTEXTCONFIG: 6268 /* SmartMIPS ASE */ 6269 /* gen_helper_mtc0_contextconfig(arg); */ 6270 register_name = "ContextConfig"; 6271 goto cp0_unimplemented; 6272 case CP0_REG04__USERLOCAL: 6273 CP0_CHECK(ctx->ulri); 6274 tcg_gen_st_tl(arg, cpu_env, 6275 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 6276 register_name = "UserLocal"; 6277 break; 6278 case CP0_REG04__MMID: 6279 CP0_CHECK(ctx->mi); 6280 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MemoryMapID)); 6281 register_name = "MMID"; 6282 break; 6283 default: 6284 goto cp0_unimplemented; 6285 } 6286 break; 6287 case CP0_REGISTER_05: 6288 switch (sel) { 6289 case CP0_REG05__PAGEMASK: 6290 gen_helper_mtc0_pagemask(cpu_env, arg); 6291 register_name = "PageMask"; 6292 break; 6293 case CP0_REG05__PAGEGRAIN: 6294 check_insn(ctx, ISA_MIPS_R2); 6295 gen_helper_mtc0_pagegrain(cpu_env, arg); 6296 register_name = "PageGrain"; 6297 ctx->base.is_jmp = DISAS_STOP; 6298 break; 6299 case CP0_REG05__SEGCTL0: 6300 CP0_CHECK(ctx->sc); 6301 gen_helper_mtc0_segctl0(cpu_env, arg); 6302 register_name = "SegCtl0"; 6303 break; 6304 case CP0_REG05__SEGCTL1: 6305 CP0_CHECK(ctx->sc); 6306 gen_helper_mtc0_segctl1(cpu_env, arg); 6307 register_name = "SegCtl1"; 6308 break; 6309 case CP0_REG05__SEGCTL2: 6310 CP0_CHECK(ctx->sc); 6311 gen_helper_mtc0_segctl2(cpu_env, arg); 6312 register_name = "SegCtl2"; 6313 break; 6314 case CP0_REG05__PWBASE: 6315 check_pw(ctx); 6316 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase)); 6317 register_name = "PWBase"; 6318 break; 6319 case CP0_REG05__PWFIELD: 6320 check_pw(ctx); 6321 gen_helper_mtc0_pwfield(cpu_env, arg); 6322 register_name = "PWField"; 6323 break; 6324 case CP0_REG05__PWSIZE: 6325 check_pw(ctx); 6326 gen_helper_mtc0_pwsize(cpu_env, arg); 6327 register_name = "PWSize"; 6328 break; 6329 default: 6330 goto cp0_unimplemented; 6331 } 6332 break; 6333 case CP0_REGISTER_06: 6334 switch (sel) { 6335 case CP0_REG06__WIRED: 6336 gen_helper_mtc0_wired(cpu_env, arg); 6337 register_name = "Wired"; 6338 break; 6339 case CP0_REG06__SRSCONF0: 6340 check_insn(ctx, ISA_MIPS_R2); 6341 gen_helper_mtc0_srsconf0(cpu_env, arg); 6342 register_name = "SRSConf0"; 6343 break; 6344 case CP0_REG06__SRSCONF1: 6345 check_insn(ctx, ISA_MIPS_R2); 6346 gen_helper_mtc0_srsconf1(cpu_env, arg); 6347 register_name = "SRSConf1"; 6348 break; 6349 case CP0_REG06__SRSCONF2: 6350 check_insn(ctx, ISA_MIPS_R2); 6351 gen_helper_mtc0_srsconf2(cpu_env, arg); 6352 register_name = "SRSConf2"; 6353 break; 6354 case CP0_REG06__SRSCONF3: 6355 check_insn(ctx, ISA_MIPS_R2); 6356 gen_helper_mtc0_srsconf3(cpu_env, arg); 6357 register_name = "SRSConf3"; 6358 break; 6359 case CP0_REG06__SRSCONF4: 6360 check_insn(ctx, ISA_MIPS_R2); 6361 gen_helper_mtc0_srsconf4(cpu_env, arg); 6362 register_name = "SRSConf4"; 6363 break; 6364 case CP0_REG06__PWCTL: 6365 check_pw(ctx); 6366 gen_helper_mtc0_pwctl(cpu_env, arg); 6367 register_name = "PWCtl"; 6368 break; 6369 default: 6370 goto cp0_unimplemented; 6371 } 6372 break; 6373 case CP0_REGISTER_07: 6374 switch (sel) { 6375 case CP0_REG07__HWRENA: 6376 check_insn(ctx, ISA_MIPS_R2); 6377 gen_helper_mtc0_hwrena(cpu_env, arg); 6378 ctx->base.is_jmp = DISAS_STOP; 6379 register_name = "HWREna"; 6380 break; 6381 default: 6382 goto cp0_unimplemented; 6383 } 6384 break; 6385 case CP0_REGISTER_08: 6386 switch (sel) { 6387 case CP0_REG08__BADVADDR: 6388 /* ignored */ 6389 register_name = "BadVAddr"; 6390 break; 6391 case CP0_REG08__BADINSTR: 6392 /* ignored */ 6393 register_name = "BadInstr"; 6394 break; 6395 case CP0_REG08__BADINSTRP: 6396 /* ignored */ 6397 register_name = "BadInstrP"; 6398 break; 6399 case CP0_REG08__BADINSTRX: 6400 /* ignored */ 6401 register_name = "BadInstrX"; 6402 break; 6403 default: 6404 goto cp0_unimplemented; 6405 } 6406 break; 6407 case CP0_REGISTER_09: 6408 switch (sel) { 6409 case CP0_REG09__COUNT: 6410 gen_helper_mtc0_count(cpu_env, arg); 6411 register_name = "Count"; 6412 break; 6413 case CP0_REG09__SAARI: 6414 CP0_CHECK(ctx->saar); 6415 gen_helper_mtc0_saari(cpu_env, arg); 6416 register_name = "SAARI"; 6417 break; 6418 case CP0_REG09__SAAR: 6419 CP0_CHECK(ctx->saar); 6420 gen_helper_mtc0_saar(cpu_env, arg); 6421 register_name = "SAAR"; 6422 break; 6423 default: 6424 goto cp0_unimplemented; 6425 } 6426 break; 6427 case CP0_REGISTER_10: 6428 switch (sel) { 6429 case CP0_REG10__ENTRYHI: 6430 gen_helper_mtc0_entryhi(cpu_env, arg); 6431 register_name = "EntryHi"; 6432 break; 6433 default: 6434 goto cp0_unimplemented; 6435 } 6436 break; 6437 case CP0_REGISTER_11: 6438 switch (sel) { 6439 case CP0_REG11__COMPARE: 6440 gen_helper_mtc0_compare(cpu_env, arg); 6441 register_name = "Compare"; 6442 break; 6443 /* 6,7 are implementation dependent */ 6444 default: 6445 goto cp0_unimplemented; 6446 } 6447 break; 6448 case CP0_REGISTER_12: 6449 switch (sel) { 6450 case CP0_REG12__STATUS: 6451 save_cpu_state(ctx, 1); 6452 gen_helper_mtc0_status(cpu_env, arg); 6453 /* DISAS_STOP isn't good enough here, hflags may have changed. */ 6454 gen_save_pc(ctx->base.pc_next + 4); 6455 ctx->base.is_jmp = DISAS_EXIT; 6456 register_name = "Status"; 6457 break; 6458 case CP0_REG12__INTCTL: 6459 check_insn(ctx, ISA_MIPS_R2); 6460 gen_helper_mtc0_intctl(cpu_env, arg); 6461 /* Stop translation as we may have switched the execution mode */ 6462 ctx->base.is_jmp = DISAS_STOP; 6463 register_name = "IntCtl"; 6464 break; 6465 case CP0_REG12__SRSCTL: 6466 check_insn(ctx, ISA_MIPS_R2); 6467 gen_helper_mtc0_srsctl(cpu_env, arg); 6468 /* Stop translation as we may have switched the execution mode */ 6469 ctx->base.is_jmp = DISAS_STOP; 6470 register_name = "SRSCtl"; 6471 break; 6472 case CP0_REG12__SRSMAP: 6473 check_insn(ctx, ISA_MIPS_R2); 6474 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); 6475 /* Stop translation as we may have switched the execution mode */ 6476 ctx->base.is_jmp = DISAS_STOP; 6477 register_name = "SRSMap"; 6478 break; 6479 default: 6480 goto cp0_unimplemented; 6481 } 6482 break; 6483 case CP0_REGISTER_13: 6484 switch (sel) { 6485 case CP0_REG13__CAUSE: 6486 save_cpu_state(ctx, 1); 6487 gen_helper_mtc0_cause(cpu_env, arg); 6488 /* 6489 * Stop translation as we may have triggered an interrupt. 6490 * DISAS_STOP isn't sufficient, we need to ensure we break out of 6491 * translated code to check for pending interrupts. 6492 */ 6493 gen_save_pc(ctx->base.pc_next + 4); 6494 ctx->base.is_jmp = DISAS_EXIT; 6495 register_name = "Cause"; 6496 break; 6497 default: 6498 goto cp0_unimplemented; 6499 } 6500 break; 6501 case CP0_REGISTER_14: 6502 switch (sel) { 6503 case CP0_REG14__EPC: 6504 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC)); 6505 register_name = "EPC"; 6506 break; 6507 default: 6508 goto cp0_unimplemented; 6509 } 6510 break; 6511 case CP0_REGISTER_15: 6512 switch (sel) { 6513 case CP0_REG15__PRID: 6514 /* ignored */ 6515 register_name = "PRid"; 6516 break; 6517 case CP0_REG15__EBASE: 6518 check_insn(ctx, ISA_MIPS_R2); 6519 gen_helper_mtc0_ebase(cpu_env, arg); 6520 register_name = "EBase"; 6521 break; 6522 default: 6523 goto cp0_unimplemented; 6524 } 6525 break; 6526 case CP0_REGISTER_16: 6527 switch (sel) { 6528 case CP0_REG16__CONFIG: 6529 gen_helper_mtc0_config0(cpu_env, arg); 6530 register_name = "Config"; 6531 /* Stop translation as we may have switched the execution mode */ 6532 ctx->base.is_jmp = DISAS_STOP; 6533 break; 6534 case CP0_REG16__CONFIG1: 6535 /* ignored, read only */ 6536 register_name = "Config1"; 6537 break; 6538 case CP0_REG16__CONFIG2: 6539 gen_helper_mtc0_config2(cpu_env, arg); 6540 register_name = "Config2"; 6541 /* Stop translation as we may have switched the execution mode */ 6542 ctx->base.is_jmp = DISAS_STOP; 6543 break; 6544 case CP0_REG16__CONFIG3: 6545 gen_helper_mtc0_config3(cpu_env, arg); 6546 register_name = "Config3"; 6547 /* Stop translation as we may have switched the execution mode */ 6548 ctx->base.is_jmp = DISAS_STOP; 6549 break; 6550 case CP0_REG16__CONFIG4: 6551 gen_helper_mtc0_config4(cpu_env, arg); 6552 register_name = "Config4"; 6553 ctx->base.is_jmp = DISAS_STOP; 6554 break; 6555 case CP0_REG16__CONFIG5: 6556 gen_helper_mtc0_config5(cpu_env, arg); 6557 register_name = "Config5"; 6558 /* Stop translation as we may have switched the execution mode */ 6559 ctx->base.is_jmp = DISAS_STOP; 6560 break; 6561 /* 6,7 are implementation dependent */ 6562 case CP0_REG16__CONFIG6: 6563 /* ignored */ 6564 register_name = "Config6"; 6565 break; 6566 case CP0_REG16__CONFIG7: 6567 /* ignored */ 6568 register_name = "Config7"; 6569 break; 6570 default: 6571 register_name = "Invalid config selector"; 6572 goto cp0_unimplemented; 6573 } 6574 break; 6575 case CP0_REGISTER_17: 6576 switch (sel) { 6577 case CP0_REG17__LLADDR: 6578 gen_helper_mtc0_lladdr(cpu_env, arg); 6579 register_name = "LLAddr"; 6580 break; 6581 case CP0_REG17__MAAR: 6582 CP0_CHECK(ctx->mrp); 6583 gen_helper_mtc0_maar(cpu_env, arg); 6584 register_name = "MAAR"; 6585 break; 6586 case CP0_REG17__MAARI: 6587 CP0_CHECK(ctx->mrp); 6588 gen_helper_mtc0_maari(cpu_env, arg); 6589 register_name = "MAARI"; 6590 break; 6591 default: 6592 goto cp0_unimplemented; 6593 } 6594 break; 6595 case CP0_REGISTER_18: 6596 switch (sel) { 6597 case CP0_REG18__WATCHLO0: 6598 case CP0_REG18__WATCHLO1: 6599 case CP0_REG18__WATCHLO2: 6600 case CP0_REG18__WATCHLO3: 6601 case CP0_REG18__WATCHLO4: 6602 case CP0_REG18__WATCHLO5: 6603 case CP0_REG18__WATCHLO6: 6604 case CP0_REG18__WATCHLO7: 6605 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 6606 gen_helper_0e1i(mtc0_watchlo, arg, sel); 6607 register_name = "WatchLo"; 6608 break; 6609 default: 6610 goto cp0_unimplemented; 6611 } 6612 break; 6613 case CP0_REGISTER_19: 6614 switch (sel) { 6615 case CP0_REG19__WATCHHI0: 6616 case CP0_REG19__WATCHHI1: 6617 case CP0_REG19__WATCHHI2: 6618 case CP0_REG19__WATCHHI3: 6619 case CP0_REG19__WATCHHI4: 6620 case CP0_REG19__WATCHHI5: 6621 case CP0_REG19__WATCHHI6: 6622 case CP0_REG19__WATCHHI7: 6623 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 6624 gen_helper_0e1i(mtc0_watchhi, arg, sel); 6625 register_name = "WatchHi"; 6626 break; 6627 default: 6628 goto cp0_unimplemented; 6629 } 6630 break; 6631 case CP0_REGISTER_20: 6632 switch (sel) { 6633 case CP0_REG20__XCONTEXT: 6634 #if defined(TARGET_MIPS64) 6635 check_insn(ctx, ISA_MIPS3); 6636 gen_helper_mtc0_xcontext(cpu_env, arg); 6637 register_name = "XContext"; 6638 break; 6639 #endif 6640 default: 6641 goto cp0_unimplemented; 6642 } 6643 break; 6644 case CP0_REGISTER_21: 6645 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 6646 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 6647 switch (sel) { 6648 case 0: 6649 gen_helper_mtc0_framemask(cpu_env, arg); 6650 register_name = "Framemask"; 6651 break; 6652 default: 6653 goto cp0_unimplemented; 6654 } 6655 break; 6656 case CP0_REGISTER_22: 6657 /* ignored */ 6658 register_name = "Diagnostic"; /* implementation dependent */ 6659 break; 6660 case CP0_REGISTER_23: 6661 switch (sel) { 6662 case CP0_REG23__DEBUG: 6663 gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */ 6664 /* DISAS_STOP isn't good enough here, hflags may have changed. */ 6665 gen_save_pc(ctx->base.pc_next + 4); 6666 ctx->base.is_jmp = DISAS_EXIT; 6667 register_name = "Debug"; 6668 break; 6669 case CP0_REG23__TRACECONTROL: 6670 /* PDtrace support */ 6671 /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */ 6672 register_name = "TraceControl"; 6673 /* Stop translation as we may have switched the execution mode */ 6674 ctx->base.is_jmp = DISAS_STOP; 6675 goto cp0_unimplemented; 6676 case CP0_REG23__TRACECONTROL2: 6677 /* PDtrace support */ 6678 /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */ 6679 register_name = "TraceControl2"; 6680 /* Stop translation as we may have switched the execution mode */ 6681 ctx->base.is_jmp = DISAS_STOP; 6682 goto cp0_unimplemented; 6683 case CP0_REG23__USERTRACEDATA1: 6684 /* Stop translation as we may have switched the execution mode */ 6685 ctx->base.is_jmp = DISAS_STOP; 6686 /* PDtrace support */ 6687 /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/ 6688 register_name = "UserTraceData"; 6689 /* Stop translation as we may have switched the execution mode */ 6690 ctx->base.is_jmp = DISAS_STOP; 6691 goto cp0_unimplemented; 6692 case CP0_REG23__TRACEIBPC: 6693 /* PDtrace support */ 6694 /* gen_helper_mtc0_traceibpc(cpu_env, arg); */ 6695 /* Stop translation as we may have switched the execution mode */ 6696 ctx->base.is_jmp = DISAS_STOP; 6697 register_name = "TraceIBPC"; 6698 goto cp0_unimplemented; 6699 case CP0_REG23__TRACEDBPC: 6700 /* PDtrace support */ 6701 /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */ 6702 /* Stop translation as we may have switched the execution mode */ 6703 ctx->base.is_jmp = DISAS_STOP; 6704 register_name = "TraceDBPC"; 6705 goto cp0_unimplemented; 6706 default: 6707 goto cp0_unimplemented; 6708 } 6709 break; 6710 case CP0_REGISTER_24: 6711 switch (sel) { 6712 case CP0_REG24__DEPC: 6713 /* EJTAG support */ 6714 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC)); 6715 register_name = "DEPC"; 6716 break; 6717 default: 6718 goto cp0_unimplemented; 6719 } 6720 break; 6721 case CP0_REGISTER_25: 6722 switch (sel) { 6723 case CP0_REG25__PERFCTL0: 6724 gen_helper_mtc0_performance0(cpu_env, arg); 6725 register_name = "Performance0"; 6726 break; 6727 case CP0_REG25__PERFCNT0: 6728 /* gen_helper_mtc0_performance1(arg); */ 6729 register_name = "Performance1"; 6730 goto cp0_unimplemented; 6731 case CP0_REG25__PERFCTL1: 6732 /* gen_helper_mtc0_performance2(arg); */ 6733 register_name = "Performance2"; 6734 goto cp0_unimplemented; 6735 case CP0_REG25__PERFCNT1: 6736 /* gen_helper_mtc0_performance3(arg); */ 6737 register_name = "Performance3"; 6738 goto cp0_unimplemented; 6739 case CP0_REG25__PERFCTL2: 6740 /* gen_helper_mtc0_performance4(arg); */ 6741 register_name = "Performance4"; 6742 goto cp0_unimplemented; 6743 case CP0_REG25__PERFCNT2: 6744 /* gen_helper_mtc0_performance5(arg); */ 6745 register_name = "Performance5"; 6746 goto cp0_unimplemented; 6747 case CP0_REG25__PERFCTL3: 6748 /* gen_helper_mtc0_performance6(arg); */ 6749 register_name = "Performance6"; 6750 goto cp0_unimplemented; 6751 case CP0_REG25__PERFCNT3: 6752 /* gen_helper_mtc0_performance7(arg); */ 6753 register_name = "Performance7"; 6754 goto cp0_unimplemented; 6755 default: 6756 goto cp0_unimplemented; 6757 } 6758 break; 6759 case CP0_REGISTER_26: 6760 switch (sel) { 6761 case CP0_REG26__ERRCTL: 6762 gen_helper_mtc0_errctl(cpu_env, arg); 6763 ctx->base.is_jmp = DISAS_STOP; 6764 register_name = "ErrCtl"; 6765 break; 6766 default: 6767 goto cp0_unimplemented; 6768 } 6769 break; 6770 case CP0_REGISTER_27: 6771 switch (sel) { 6772 case CP0_REG27__CACHERR: 6773 /* ignored */ 6774 register_name = "CacheErr"; 6775 break; 6776 default: 6777 goto cp0_unimplemented; 6778 } 6779 break; 6780 case CP0_REGISTER_28: 6781 switch (sel) { 6782 case CP0_REG28__TAGLO: 6783 case CP0_REG28__TAGLO1: 6784 case CP0_REG28__TAGLO2: 6785 case CP0_REG28__TAGLO3: 6786 gen_helper_mtc0_taglo(cpu_env, arg); 6787 register_name = "TagLo"; 6788 break; 6789 case CP0_REG28__DATALO: 6790 case CP0_REG28__DATALO1: 6791 case CP0_REG28__DATALO2: 6792 case CP0_REG28__DATALO3: 6793 gen_helper_mtc0_datalo(cpu_env, arg); 6794 register_name = "DataLo"; 6795 break; 6796 default: 6797 goto cp0_unimplemented; 6798 } 6799 break; 6800 case CP0_REGISTER_29: 6801 switch (sel) { 6802 case CP0_REG29__TAGHI: 6803 case CP0_REG29__TAGHI1: 6804 case CP0_REG29__TAGHI2: 6805 case CP0_REG29__TAGHI3: 6806 gen_helper_mtc0_taghi(cpu_env, arg); 6807 register_name = "TagHi"; 6808 break; 6809 case CP0_REG29__DATAHI: 6810 case CP0_REG29__DATAHI1: 6811 case CP0_REG29__DATAHI2: 6812 case CP0_REG29__DATAHI3: 6813 gen_helper_mtc0_datahi(cpu_env, arg); 6814 register_name = "DataHi"; 6815 break; 6816 default: 6817 register_name = "invalid sel"; 6818 goto cp0_unimplemented; 6819 } 6820 break; 6821 case CP0_REGISTER_30: 6822 switch (sel) { 6823 case CP0_REG30__ERROREPC: 6824 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); 6825 register_name = "ErrorEPC"; 6826 break; 6827 default: 6828 goto cp0_unimplemented; 6829 } 6830 break; 6831 case CP0_REGISTER_31: 6832 switch (sel) { 6833 case CP0_REG31__DESAVE: 6834 /* EJTAG support */ 6835 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); 6836 register_name = "DESAVE"; 6837 break; 6838 case CP0_REG31__KSCRATCH1: 6839 case CP0_REG31__KSCRATCH2: 6840 case CP0_REG31__KSCRATCH3: 6841 case CP0_REG31__KSCRATCH4: 6842 case CP0_REG31__KSCRATCH5: 6843 case CP0_REG31__KSCRATCH6: 6844 CP0_CHECK(ctx->kscrexist & (1 << sel)); 6845 tcg_gen_st_tl(arg, cpu_env, 6846 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); 6847 register_name = "KScratch"; 6848 break; 6849 default: 6850 goto cp0_unimplemented; 6851 } 6852 break; 6853 default: 6854 goto cp0_unimplemented; 6855 } 6856 trace_mips_translate_c0("mtc0", register_name, reg, sel); 6857 6858 /* For simplicity assume that all writes can cause interrupts. */ 6859 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 6860 /* 6861 * DISAS_STOP isn't sufficient, we need to ensure we break out of 6862 * translated code to check for pending interrupts. 6863 */ 6864 gen_save_pc(ctx->base.pc_next + 4); 6865 ctx->base.is_jmp = DISAS_EXIT; 6866 } 6867 return; 6868 6869 cp0_unimplemented: 6870 qemu_log_mask(LOG_UNIMP, "mtc0 %s (reg %d sel %d)\n", 6871 register_name, reg, sel); 6872 } 6873 6874 #if defined(TARGET_MIPS64) 6875 static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) 6876 { 6877 const char *register_name = "invalid"; 6878 6879 if (sel != 0) { 6880 check_insn(ctx, ISA_MIPS_R1); 6881 } 6882 6883 switch (reg) { 6884 case CP0_REGISTER_00: 6885 switch (sel) { 6886 case CP0_REG00__INDEX: 6887 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index)); 6888 register_name = "Index"; 6889 break; 6890 case CP0_REG00__MVPCONTROL: 6891 CP0_CHECK(ctx->insn_flags & ASE_MT); 6892 gen_helper_mfc0_mvpcontrol(arg, cpu_env); 6893 register_name = "MVPControl"; 6894 break; 6895 case CP0_REG00__MVPCONF0: 6896 CP0_CHECK(ctx->insn_flags & ASE_MT); 6897 gen_helper_mfc0_mvpconf0(arg, cpu_env); 6898 register_name = "MVPConf0"; 6899 break; 6900 case CP0_REG00__MVPCONF1: 6901 CP0_CHECK(ctx->insn_flags & ASE_MT); 6902 gen_helper_mfc0_mvpconf1(arg, cpu_env); 6903 register_name = "MVPConf1"; 6904 break; 6905 case CP0_REG00__VPCONTROL: 6906 CP0_CHECK(ctx->vp); 6907 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl)); 6908 register_name = "VPControl"; 6909 break; 6910 default: 6911 goto cp0_unimplemented; 6912 } 6913 break; 6914 case CP0_REGISTER_01: 6915 switch (sel) { 6916 case CP0_REG01__RANDOM: 6917 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 6918 gen_helper_mfc0_random(arg, cpu_env); 6919 register_name = "Random"; 6920 break; 6921 case CP0_REG01__VPECONTROL: 6922 CP0_CHECK(ctx->insn_flags & ASE_MT); 6923 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl)); 6924 register_name = "VPEControl"; 6925 break; 6926 case CP0_REG01__VPECONF0: 6927 CP0_CHECK(ctx->insn_flags & ASE_MT); 6928 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0)); 6929 register_name = "VPEConf0"; 6930 break; 6931 case CP0_REG01__VPECONF1: 6932 CP0_CHECK(ctx->insn_flags & ASE_MT); 6933 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1)); 6934 register_name = "VPEConf1"; 6935 break; 6936 case CP0_REG01__YQMASK: 6937 CP0_CHECK(ctx->insn_flags & ASE_MT); 6938 tcg_gen_ld_tl(arg, cpu_env, 6939 offsetof(CPUMIPSState, CP0_YQMask)); 6940 register_name = "YQMask"; 6941 break; 6942 case CP0_REG01__VPESCHEDULE: 6943 CP0_CHECK(ctx->insn_flags & ASE_MT); 6944 tcg_gen_ld_tl(arg, cpu_env, 6945 offsetof(CPUMIPSState, CP0_VPESchedule)); 6946 register_name = "VPESchedule"; 6947 break; 6948 case CP0_REG01__VPESCHEFBACK: 6949 CP0_CHECK(ctx->insn_flags & ASE_MT); 6950 tcg_gen_ld_tl(arg, cpu_env, 6951 offsetof(CPUMIPSState, CP0_VPEScheFBack)); 6952 register_name = "VPEScheFBack"; 6953 break; 6954 case CP0_REG01__VPEOPT: 6955 CP0_CHECK(ctx->insn_flags & ASE_MT); 6956 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt)); 6957 register_name = "VPEOpt"; 6958 break; 6959 default: 6960 goto cp0_unimplemented; 6961 } 6962 break; 6963 case CP0_REGISTER_02: 6964 switch (sel) { 6965 case CP0_REG02__ENTRYLO0: 6966 tcg_gen_ld_tl(arg, cpu_env, 6967 offsetof(CPUMIPSState, CP0_EntryLo0)); 6968 register_name = "EntryLo0"; 6969 break; 6970 case CP0_REG02__TCSTATUS: 6971 CP0_CHECK(ctx->insn_flags & ASE_MT); 6972 gen_helper_mfc0_tcstatus(arg, cpu_env); 6973 register_name = "TCStatus"; 6974 break; 6975 case CP0_REG02__TCBIND: 6976 CP0_CHECK(ctx->insn_flags & ASE_MT); 6977 gen_helper_mfc0_tcbind(arg, cpu_env); 6978 register_name = "TCBind"; 6979 break; 6980 case CP0_REG02__TCRESTART: 6981 CP0_CHECK(ctx->insn_flags & ASE_MT); 6982 gen_helper_dmfc0_tcrestart(arg, cpu_env); 6983 register_name = "TCRestart"; 6984 break; 6985 case CP0_REG02__TCHALT: 6986 CP0_CHECK(ctx->insn_flags & ASE_MT); 6987 gen_helper_dmfc0_tchalt(arg, cpu_env); 6988 register_name = "TCHalt"; 6989 break; 6990 case CP0_REG02__TCCONTEXT: 6991 CP0_CHECK(ctx->insn_flags & ASE_MT); 6992 gen_helper_dmfc0_tccontext(arg, cpu_env); 6993 register_name = "TCContext"; 6994 break; 6995 case CP0_REG02__TCSCHEDULE: 6996 CP0_CHECK(ctx->insn_flags & ASE_MT); 6997 gen_helper_dmfc0_tcschedule(arg, cpu_env); 6998 register_name = "TCSchedule"; 6999 break; 7000 case CP0_REG02__TCSCHEFBACK: 7001 CP0_CHECK(ctx->insn_flags & ASE_MT); 7002 gen_helper_dmfc0_tcschefback(arg, cpu_env); 7003 register_name = "TCScheFBack"; 7004 break; 7005 default: 7006 goto cp0_unimplemented; 7007 } 7008 break; 7009 case CP0_REGISTER_03: 7010 switch (sel) { 7011 case CP0_REG03__ENTRYLO1: 7012 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1)); 7013 register_name = "EntryLo1"; 7014 break; 7015 case CP0_REG03__GLOBALNUM: 7016 CP0_CHECK(ctx->vp); 7017 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber)); 7018 register_name = "GlobalNumber"; 7019 break; 7020 default: 7021 goto cp0_unimplemented; 7022 } 7023 break; 7024 case CP0_REGISTER_04: 7025 switch (sel) { 7026 case CP0_REG04__CONTEXT: 7027 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context)); 7028 register_name = "Context"; 7029 break; 7030 case CP0_REG04__CONTEXTCONFIG: 7031 /* SmartMIPS ASE */ 7032 /* gen_helper_dmfc0_contextconfig(arg); */ 7033 register_name = "ContextConfig"; 7034 goto cp0_unimplemented; 7035 case CP0_REG04__USERLOCAL: 7036 CP0_CHECK(ctx->ulri); 7037 tcg_gen_ld_tl(arg, cpu_env, 7038 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 7039 register_name = "UserLocal"; 7040 break; 7041 case CP0_REG04__MMID: 7042 CP0_CHECK(ctx->mi); 7043 gen_helper_mtc0_memorymapid(cpu_env, arg); 7044 register_name = "MMID"; 7045 break; 7046 default: 7047 goto cp0_unimplemented; 7048 } 7049 break; 7050 case CP0_REGISTER_05: 7051 switch (sel) { 7052 case CP0_REG05__PAGEMASK: 7053 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask)); 7054 register_name = "PageMask"; 7055 break; 7056 case CP0_REG05__PAGEGRAIN: 7057 check_insn(ctx, ISA_MIPS_R2); 7058 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); 7059 register_name = "PageGrain"; 7060 break; 7061 case CP0_REG05__SEGCTL0: 7062 CP0_CHECK(ctx->sc); 7063 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0)); 7064 register_name = "SegCtl0"; 7065 break; 7066 case CP0_REG05__SEGCTL1: 7067 CP0_CHECK(ctx->sc); 7068 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1)); 7069 register_name = "SegCtl1"; 7070 break; 7071 case CP0_REG05__SEGCTL2: 7072 CP0_CHECK(ctx->sc); 7073 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2)); 7074 register_name = "SegCtl2"; 7075 break; 7076 case CP0_REG05__PWBASE: 7077 check_pw(ctx); 7078 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase)); 7079 register_name = "PWBase"; 7080 break; 7081 case CP0_REG05__PWFIELD: 7082 check_pw(ctx); 7083 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField)); 7084 register_name = "PWField"; 7085 break; 7086 case CP0_REG05__PWSIZE: 7087 check_pw(ctx); 7088 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize)); 7089 register_name = "PWSize"; 7090 break; 7091 default: 7092 goto cp0_unimplemented; 7093 } 7094 break; 7095 case CP0_REGISTER_06: 7096 switch (sel) { 7097 case CP0_REG06__WIRED: 7098 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired)); 7099 register_name = "Wired"; 7100 break; 7101 case CP0_REG06__SRSCONF0: 7102 check_insn(ctx, ISA_MIPS_R2); 7103 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); 7104 register_name = "SRSConf0"; 7105 break; 7106 case CP0_REG06__SRSCONF1: 7107 check_insn(ctx, ISA_MIPS_R2); 7108 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); 7109 register_name = "SRSConf1"; 7110 break; 7111 case CP0_REG06__SRSCONF2: 7112 check_insn(ctx, ISA_MIPS_R2); 7113 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); 7114 register_name = "SRSConf2"; 7115 break; 7116 case CP0_REG06__SRSCONF3: 7117 check_insn(ctx, ISA_MIPS_R2); 7118 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); 7119 register_name = "SRSConf3"; 7120 break; 7121 case CP0_REG06__SRSCONF4: 7122 check_insn(ctx, ISA_MIPS_R2); 7123 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); 7124 register_name = "SRSConf4"; 7125 break; 7126 case CP0_REG06__PWCTL: 7127 check_pw(ctx); 7128 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl)); 7129 register_name = "PWCtl"; 7130 break; 7131 default: 7132 goto cp0_unimplemented; 7133 } 7134 break; 7135 case CP0_REGISTER_07: 7136 switch (sel) { 7137 case CP0_REG07__HWRENA: 7138 check_insn(ctx, ISA_MIPS_R2); 7139 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); 7140 register_name = "HWREna"; 7141 break; 7142 default: 7143 goto cp0_unimplemented; 7144 } 7145 break; 7146 case CP0_REGISTER_08: 7147 switch (sel) { 7148 case CP0_REG08__BADVADDR: 7149 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); 7150 register_name = "BadVAddr"; 7151 break; 7152 case CP0_REG08__BADINSTR: 7153 CP0_CHECK(ctx->bi); 7154 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr)); 7155 register_name = "BadInstr"; 7156 break; 7157 case CP0_REG08__BADINSTRP: 7158 CP0_CHECK(ctx->bp); 7159 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP)); 7160 register_name = "BadInstrP"; 7161 break; 7162 case CP0_REG08__BADINSTRX: 7163 CP0_CHECK(ctx->bi); 7164 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX)); 7165 tcg_gen_andi_tl(arg, arg, ~0xffff); 7166 register_name = "BadInstrX"; 7167 break; 7168 default: 7169 goto cp0_unimplemented; 7170 } 7171 break; 7172 case CP0_REGISTER_09: 7173 switch (sel) { 7174 case CP0_REG09__COUNT: 7175 /* Mark as an IO operation because we read the time. */ 7176 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 7177 gen_io_start(); 7178 } 7179 gen_helper_mfc0_count(arg, cpu_env); 7180 /* 7181 * Break the TB to be able to take timer interrupts immediately 7182 * after reading count. DISAS_STOP isn't sufficient, we need to 7183 * ensure we break completely out of translated code. 7184 */ 7185 gen_save_pc(ctx->base.pc_next + 4); 7186 ctx->base.is_jmp = DISAS_EXIT; 7187 register_name = "Count"; 7188 break; 7189 case CP0_REG09__SAARI: 7190 CP0_CHECK(ctx->saar); 7191 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); 7192 register_name = "SAARI"; 7193 break; 7194 case CP0_REG09__SAAR: 7195 CP0_CHECK(ctx->saar); 7196 gen_helper_dmfc0_saar(arg, cpu_env); 7197 register_name = "SAAR"; 7198 break; 7199 default: 7200 goto cp0_unimplemented; 7201 } 7202 break; 7203 case CP0_REGISTER_10: 7204 switch (sel) { 7205 case CP0_REG10__ENTRYHI: 7206 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi)); 7207 register_name = "EntryHi"; 7208 break; 7209 default: 7210 goto cp0_unimplemented; 7211 } 7212 break; 7213 case CP0_REGISTER_11: 7214 switch (sel) { 7215 case CP0_REG11__COMPARE: 7216 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare)); 7217 register_name = "Compare"; 7218 break; 7219 /* 6,7 are implementation dependent */ 7220 default: 7221 goto cp0_unimplemented; 7222 } 7223 break; 7224 case CP0_REGISTER_12: 7225 switch (sel) { 7226 case CP0_REG12__STATUS: 7227 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status)); 7228 register_name = "Status"; 7229 break; 7230 case CP0_REG12__INTCTL: 7231 check_insn(ctx, ISA_MIPS_R2); 7232 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); 7233 register_name = "IntCtl"; 7234 break; 7235 case CP0_REG12__SRSCTL: 7236 check_insn(ctx, ISA_MIPS_R2); 7237 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); 7238 register_name = "SRSCtl"; 7239 break; 7240 case CP0_REG12__SRSMAP: 7241 check_insn(ctx, ISA_MIPS_R2); 7242 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); 7243 register_name = "SRSMap"; 7244 break; 7245 default: 7246 goto cp0_unimplemented; 7247 } 7248 break; 7249 case CP0_REGISTER_13: 7250 switch (sel) { 7251 case CP0_REG13__CAUSE: 7252 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause)); 7253 register_name = "Cause"; 7254 break; 7255 default: 7256 goto cp0_unimplemented; 7257 } 7258 break; 7259 case CP0_REGISTER_14: 7260 switch (sel) { 7261 case CP0_REG14__EPC: 7262 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC)); 7263 register_name = "EPC"; 7264 break; 7265 default: 7266 goto cp0_unimplemented; 7267 } 7268 break; 7269 case CP0_REGISTER_15: 7270 switch (sel) { 7271 case CP0_REG15__PRID: 7272 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid)); 7273 register_name = "PRid"; 7274 break; 7275 case CP0_REG15__EBASE: 7276 check_insn(ctx, ISA_MIPS_R2); 7277 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); 7278 register_name = "EBase"; 7279 break; 7280 case CP0_REG15__CMGCRBASE: 7281 check_insn(ctx, ISA_MIPS_R2); 7282 CP0_CHECK(ctx->cmgcr); 7283 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase)); 7284 register_name = "CMGCRBase"; 7285 break; 7286 default: 7287 goto cp0_unimplemented; 7288 } 7289 break; 7290 case CP0_REGISTER_16: 7291 switch (sel) { 7292 case CP0_REG16__CONFIG: 7293 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0)); 7294 register_name = "Config"; 7295 break; 7296 case CP0_REG16__CONFIG1: 7297 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1)); 7298 register_name = "Config1"; 7299 break; 7300 case CP0_REG16__CONFIG2: 7301 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2)); 7302 register_name = "Config2"; 7303 break; 7304 case CP0_REG16__CONFIG3: 7305 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3)); 7306 register_name = "Config3"; 7307 break; 7308 case CP0_REG16__CONFIG4: 7309 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4)); 7310 register_name = "Config4"; 7311 break; 7312 case CP0_REG16__CONFIG5: 7313 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5)); 7314 register_name = "Config5"; 7315 break; 7316 /* 6,7 are implementation dependent */ 7317 case CP0_REG16__CONFIG6: 7318 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6)); 7319 register_name = "Config6"; 7320 break; 7321 case CP0_REG16__CONFIG7: 7322 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7)); 7323 register_name = "Config7"; 7324 break; 7325 default: 7326 goto cp0_unimplemented; 7327 } 7328 break; 7329 case CP0_REGISTER_17: 7330 switch (sel) { 7331 case CP0_REG17__LLADDR: 7332 gen_helper_dmfc0_lladdr(arg, cpu_env); 7333 register_name = "LLAddr"; 7334 break; 7335 case CP0_REG17__MAAR: 7336 CP0_CHECK(ctx->mrp); 7337 gen_helper_dmfc0_maar(arg, cpu_env); 7338 register_name = "MAAR"; 7339 break; 7340 case CP0_REG17__MAARI: 7341 CP0_CHECK(ctx->mrp); 7342 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI)); 7343 register_name = "MAARI"; 7344 break; 7345 default: 7346 goto cp0_unimplemented; 7347 } 7348 break; 7349 case CP0_REGISTER_18: 7350 switch (sel) { 7351 case CP0_REG18__WATCHLO0: 7352 case CP0_REG18__WATCHLO1: 7353 case CP0_REG18__WATCHLO2: 7354 case CP0_REG18__WATCHLO3: 7355 case CP0_REG18__WATCHLO4: 7356 case CP0_REG18__WATCHLO5: 7357 case CP0_REG18__WATCHLO6: 7358 case CP0_REG18__WATCHLO7: 7359 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 7360 gen_helper_1e0i(dmfc0_watchlo, arg, sel); 7361 register_name = "WatchLo"; 7362 break; 7363 default: 7364 goto cp0_unimplemented; 7365 } 7366 break; 7367 case CP0_REGISTER_19: 7368 switch (sel) { 7369 case CP0_REG19__WATCHHI0: 7370 case CP0_REG19__WATCHHI1: 7371 case CP0_REG19__WATCHHI2: 7372 case CP0_REG19__WATCHHI3: 7373 case CP0_REG19__WATCHHI4: 7374 case CP0_REG19__WATCHHI5: 7375 case CP0_REG19__WATCHHI6: 7376 case CP0_REG19__WATCHHI7: 7377 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 7378 gen_helper_1e0i(dmfc0_watchhi, arg, sel); 7379 register_name = "WatchHi"; 7380 break; 7381 default: 7382 goto cp0_unimplemented; 7383 } 7384 break; 7385 case CP0_REGISTER_20: 7386 switch (sel) { 7387 case CP0_REG20__XCONTEXT: 7388 check_insn(ctx, ISA_MIPS3); 7389 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext)); 7390 register_name = "XContext"; 7391 break; 7392 default: 7393 goto cp0_unimplemented; 7394 } 7395 break; 7396 case CP0_REGISTER_21: 7397 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 7398 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 7399 switch (sel) { 7400 case 0: 7401 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask)); 7402 register_name = "Framemask"; 7403 break; 7404 default: 7405 goto cp0_unimplemented; 7406 } 7407 break; 7408 case CP0_REGISTER_22: 7409 tcg_gen_movi_tl(arg, 0); /* unimplemented */ 7410 register_name = "'Diagnostic"; /* implementation dependent */ 7411 break; 7412 case CP0_REGISTER_23: 7413 switch (sel) { 7414 case CP0_REG23__DEBUG: 7415 gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */ 7416 register_name = "Debug"; 7417 break; 7418 case CP0_REG23__TRACECONTROL: 7419 /* PDtrace support */ 7420 /* gen_helper_dmfc0_tracecontrol(arg, cpu_env); */ 7421 register_name = "TraceControl"; 7422 goto cp0_unimplemented; 7423 case CP0_REG23__TRACECONTROL2: 7424 /* PDtrace support */ 7425 /* gen_helper_dmfc0_tracecontrol2(arg, cpu_env); */ 7426 register_name = "TraceControl2"; 7427 goto cp0_unimplemented; 7428 case CP0_REG23__USERTRACEDATA1: 7429 /* PDtrace support */ 7430 /* gen_helper_dmfc0_usertracedata1(arg, cpu_env);*/ 7431 register_name = "UserTraceData1"; 7432 goto cp0_unimplemented; 7433 case CP0_REG23__TRACEIBPC: 7434 /* PDtrace support */ 7435 /* gen_helper_dmfc0_traceibpc(arg, cpu_env); */ 7436 register_name = "TraceIBPC"; 7437 goto cp0_unimplemented; 7438 case CP0_REG23__TRACEDBPC: 7439 /* PDtrace support */ 7440 /* gen_helper_dmfc0_tracedbpc(arg, cpu_env); */ 7441 register_name = "TraceDBPC"; 7442 goto cp0_unimplemented; 7443 default: 7444 goto cp0_unimplemented; 7445 } 7446 break; 7447 case CP0_REGISTER_24: 7448 switch (sel) { 7449 case CP0_REG24__DEPC: 7450 /* EJTAG support */ 7451 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC)); 7452 register_name = "DEPC"; 7453 break; 7454 default: 7455 goto cp0_unimplemented; 7456 } 7457 break; 7458 case CP0_REGISTER_25: 7459 switch (sel) { 7460 case CP0_REG25__PERFCTL0: 7461 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0)); 7462 register_name = "Performance0"; 7463 break; 7464 case CP0_REG25__PERFCNT0: 7465 /* gen_helper_dmfc0_performance1(arg); */ 7466 register_name = "Performance1"; 7467 goto cp0_unimplemented; 7468 case CP0_REG25__PERFCTL1: 7469 /* gen_helper_dmfc0_performance2(arg); */ 7470 register_name = "Performance2"; 7471 goto cp0_unimplemented; 7472 case CP0_REG25__PERFCNT1: 7473 /* gen_helper_dmfc0_performance3(arg); */ 7474 register_name = "Performance3"; 7475 goto cp0_unimplemented; 7476 case CP0_REG25__PERFCTL2: 7477 /* gen_helper_dmfc0_performance4(arg); */ 7478 register_name = "Performance4"; 7479 goto cp0_unimplemented; 7480 case CP0_REG25__PERFCNT2: 7481 /* gen_helper_dmfc0_performance5(arg); */ 7482 register_name = "Performance5"; 7483 goto cp0_unimplemented; 7484 case CP0_REG25__PERFCTL3: 7485 /* gen_helper_dmfc0_performance6(arg); */ 7486 register_name = "Performance6"; 7487 goto cp0_unimplemented; 7488 case CP0_REG25__PERFCNT3: 7489 /* gen_helper_dmfc0_performance7(arg); */ 7490 register_name = "Performance7"; 7491 goto cp0_unimplemented; 7492 default: 7493 goto cp0_unimplemented; 7494 } 7495 break; 7496 case CP0_REGISTER_26: 7497 switch (sel) { 7498 case CP0_REG26__ERRCTL: 7499 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl)); 7500 register_name = "ErrCtl"; 7501 break; 7502 default: 7503 goto cp0_unimplemented; 7504 } 7505 break; 7506 case CP0_REGISTER_27: 7507 switch (sel) { 7508 /* ignored */ 7509 case CP0_REG27__CACHERR: 7510 tcg_gen_movi_tl(arg, 0); /* unimplemented */ 7511 register_name = "CacheErr"; 7512 break; 7513 default: 7514 goto cp0_unimplemented; 7515 } 7516 break; 7517 case CP0_REGISTER_28: 7518 switch (sel) { 7519 case CP0_REG28__TAGLO: 7520 case CP0_REG28__TAGLO1: 7521 case CP0_REG28__TAGLO2: 7522 case CP0_REG28__TAGLO3: 7523 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo)); 7524 register_name = "TagLo"; 7525 break; 7526 case CP0_REG28__DATALO: 7527 case CP0_REG28__DATALO1: 7528 case CP0_REG28__DATALO2: 7529 case CP0_REG28__DATALO3: 7530 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo)); 7531 register_name = "DataLo"; 7532 break; 7533 default: 7534 goto cp0_unimplemented; 7535 } 7536 break; 7537 case CP0_REGISTER_29: 7538 switch (sel) { 7539 case CP0_REG29__TAGHI: 7540 case CP0_REG29__TAGHI1: 7541 case CP0_REG29__TAGHI2: 7542 case CP0_REG29__TAGHI3: 7543 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi)); 7544 register_name = "TagHi"; 7545 break; 7546 case CP0_REG29__DATAHI: 7547 case CP0_REG29__DATAHI1: 7548 case CP0_REG29__DATAHI2: 7549 case CP0_REG29__DATAHI3: 7550 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi)); 7551 register_name = "DataHi"; 7552 break; 7553 default: 7554 goto cp0_unimplemented; 7555 } 7556 break; 7557 case CP0_REGISTER_30: 7558 switch (sel) { 7559 case CP0_REG30__ERROREPC: 7560 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); 7561 register_name = "ErrorEPC"; 7562 break; 7563 default: 7564 goto cp0_unimplemented; 7565 } 7566 break; 7567 case CP0_REGISTER_31: 7568 switch (sel) { 7569 case CP0_REG31__DESAVE: 7570 /* EJTAG support */ 7571 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); 7572 register_name = "DESAVE"; 7573 break; 7574 case CP0_REG31__KSCRATCH1: 7575 case CP0_REG31__KSCRATCH2: 7576 case CP0_REG31__KSCRATCH3: 7577 case CP0_REG31__KSCRATCH4: 7578 case CP0_REG31__KSCRATCH5: 7579 case CP0_REG31__KSCRATCH6: 7580 CP0_CHECK(ctx->kscrexist & (1 << sel)); 7581 tcg_gen_ld_tl(arg, cpu_env, 7582 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); 7583 register_name = "KScratch"; 7584 break; 7585 default: 7586 goto cp0_unimplemented; 7587 } 7588 break; 7589 default: 7590 goto cp0_unimplemented; 7591 } 7592 trace_mips_translate_c0("dmfc0", register_name, reg, sel); 7593 return; 7594 7595 cp0_unimplemented: 7596 qemu_log_mask(LOG_UNIMP, "dmfc0 %s (reg %d sel %d)\n", 7597 register_name, reg, sel); 7598 gen_mfc0_unimplemented(ctx, arg); 7599 } 7600 7601 static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) 7602 { 7603 const char *register_name = "invalid"; 7604 7605 if (sel != 0) { 7606 check_insn(ctx, ISA_MIPS_R1); 7607 } 7608 7609 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 7610 gen_io_start(); 7611 } 7612 7613 switch (reg) { 7614 case CP0_REGISTER_00: 7615 switch (sel) { 7616 case CP0_REG00__INDEX: 7617 gen_helper_mtc0_index(cpu_env, arg); 7618 register_name = "Index"; 7619 break; 7620 case CP0_REG00__MVPCONTROL: 7621 CP0_CHECK(ctx->insn_flags & ASE_MT); 7622 gen_helper_mtc0_mvpcontrol(cpu_env, arg); 7623 register_name = "MVPControl"; 7624 break; 7625 case CP0_REG00__MVPCONF0: 7626 CP0_CHECK(ctx->insn_flags & ASE_MT); 7627 /* ignored */ 7628 register_name = "MVPConf0"; 7629 break; 7630 case CP0_REG00__MVPCONF1: 7631 CP0_CHECK(ctx->insn_flags & ASE_MT); 7632 /* ignored */ 7633 register_name = "MVPConf1"; 7634 break; 7635 case CP0_REG00__VPCONTROL: 7636 CP0_CHECK(ctx->vp); 7637 /* ignored */ 7638 register_name = "VPControl"; 7639 break; 7640 default: 7641 goto cp0_unimplemented; 7642 } 7643 break; 7644 case CP0_REGISTER_01: 7645 switch (sel) { 7646 case CP0_REG01__RANDOM: 7647 /* ignored */ 7648 register_name = "Random"; 7649 break; 7650 case CP0_REG01__VPECONTROL: 7651 CP0_CHECK(ctx->insn_flags & ASE_MT); 7652 gen_helper_mtc0_vpecontrol(cpu_env, arg); 7653 register_name = "VPEControl"; 7654 break; 7655 case CP0_REG01__VPECONF0: 7656 CP0_CHECK(ctx->insn_flags & ASE_MT); 7657 gen_helper_mtc0_vpeconf0(cpu_env, arg); 7658 register_name = "VPEConf0"; 7659 break; 7660 case CP0_REG01__VPECONF1: 7661 CP0_CHECK(ctx->insn_flags & ASE_MT); 7662 gen_helper_mtc0_vpeconf1(cpu_env, arg); 7663 register_name = "VPEConf1"; 7664 break; 7665 case CP0_REG01__YQMASK: 7666 CP0_CHECK(ctx->insn_flags & ASE_MT); 7667 gen_helper_mtc0_yqmask(cpu_env, arg); 7668 register_name = "YQMask"; 7669 break; 7670 case CP0_REG01__VPESCHEDULE: 7671 CP0_CHECK(ctx->insn_flags & ASE_MT); 7672 tcg_gen_st_tl(arg, cpu_env, 7673 offsetof(CPUMIPSState, CP0_VPESchedule)); 7674 register_name = "VPESchedule"; 7675 break; 7676 case CP0_REG01__VPESCHEFBACK: 7677 CP0_CHECK(ctx->insn_flags & ASE_MT); 7678 tcg_gen_st_tl(arg, cpu_env, 7679 offsetof(CPUMIPSState, CP0_VPEScheFBack)); 7680 register_name = "VPEScheFBack"; 7681 break; 7682 case CP0_REG01__VPEOPT: 7683 CP0_CHECK(ctx->insn_flags & ASE_MT); 7684 gen_helper_mtc0_vpeopt(cpu_env, arg); 7685 register_name = "VPEOpt"; 7686 break; 7687 default: 7688 goto cp0_unimplemented; 7689 } 7690 break; 7691 case CP0_REGISTER_02: 7692 switch (sel) { 7693 case CP0_REG02__ENTRYLO0: 7694 gen_helper_dmtc0_entrylo0(cpu_env, arg); 7695 register_name = "EntryLo0"; 7696 break; 7697 case CP0_REG02__TCSTATUS: 7698 CP0_CHECK(ctx->insn_flags & ASE_MT); 7699 gen_helper_mtc0_tcstatus(cpu_env, arg); 7700 register_name = "TCStatus"; 7701 break; 7702 case CP0_REG02__TCBIND: 7703 CP0_CHECK(ctx->insn_flags & ASE_MT); 7704 gen_helper_mtc0_tcbind(cpu_env, arg); 7705 register_name = "TCBind"; 7706 break; 7707 case CP0_REG02__TCRESTART: 7708 CP0_CHECK(ctx->insn_flags & ASE_MT); 7709 gen_helper_mtc0_tcrestart(cpu_env, arg); 7710 register_name = "TCRestart"; 7711 break; 7712 case CP0_REG02__TCHALT: 7713 CP0_CHECK(ctx->insn_flags & ASE_MT); 7714 gen_helper_mtc0_tchalt(cpu_env, arg); 7715 register_name = "TCHalt"; 7716 break; 7717 case CP0_REG02__TCCONTEXT: 7718 CP0_CHECK(ctx->insn_flags & ASE_MT); 7719 gen_helper_mtc0_tccontext(cpu_env, arg); 7720 register_name = "TCContext"; 7721 break; 7722 case CP0_REG02__TCSCHEDULE: 7723 CP0_CHECK(ctx->insn_flags & ASE_MT); 7724 gen_helper_mtc0_tcschedule(cpu_env, arg); 7725 register_name = "TCSchedule"; 7726 break; 7727 case CP0_REG02__TCSCHEFBACK: 7728 CP0_CHECK(ctx->insn_flags & ASE_MT); 7729 gen_helper_mtc0_tcschefback(cpu_env, arg); 7730 register_name = "TCScheFBack"; 7731 break; 7732 default: 7733 goto cp0_unimplemented; 7734 } 7735 break; 7736 case CP0_REGISTER_03: 7737 switch (sel) { 7738 case CP0_REG03__ENTRYLO1: 7739 gen_helper_dmtc0_entrylo1(cpu_env, arg); 7740 register_name = "EntryLo1"; 7741 break; 7742 case CP0_REG03__GLOBALNUM: 7743 CP0_CHECK(ctx->vp); 7744 /* ignored */ 7745 register_name = "GlobalNumber"; 7746 break; 7747 default: 7748 goto cp0_unimplemented; 7749 } 7750 break; 7751 case CP0_REGISTER_04: 7752 switch (sel) { 7753 case CP0_REG04__CONTEXT: 7754 gen_helper_mtc0_context(cpu_env, arg); 7755 register_name = "Context"; 7756 break; 7757 case CP0_REG04__CONTEXTCONFIG: 7758 /* SmartMIPS ASE */ 7759 /* gen_helper_dmtc0_contextconfig(arg); */ 7760 register_name = "ContextConfig"; 7761 goto cp0_unimplemented; 7762 case CP0_REG04__USERLOCAL: 7763 CP0_CHECK(ctx->ulri); 7764 tcg_gen_st_tl(arg, cpu_env, 7765 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 7766 register_name = "UserLocal"; 7767 break; 7768 case CP0_REG04__MMID: 7769 CP0_CHECK(ctx->mi); 7770 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MemoryMapID)); 7771 register_name = "MMID"; 7772 break; 7773 default: 7774 goto cp0_unimplemented; 7775 } 7776 break; 7777 case CP0_REGISTER_05: 7778 switch (sel) { 7779 case CP0_REG05__PAGEMASK: 7780 gen_helper_mtc0_pagemask(cpu_env, arg); 7781 register_name = "PageMask"; 7782 break; 7783 case CP0_REG05__PAGEGRAIN: 7784 check_insn(ctx, ISA_MIPS_R2); 7785 gen_helper_mtc0_pagegrain(cpu_env, arg); 7786 register_name = "PageGrain"; 7787 break; 7788 case CP0_REG05__SEGCTL0: 7789 CP0_CHECK(ctx->sc); 7790 gen_helper_mtc0_segctl0(cpu_env, arg); 7791 register_name = "SegCtl0"; 7792 break; 7793 case CP0_REG05__SEGCTL1: 7794 CP0_CHECK(ctx->sc); 7795 gen_helper_mtc0_segctl1(cpu_env, arg); 7796 register_name = "SegCtl1"; 7797 break; 7798 case CP0_REG05__SEGCTL2: 7799 CP0_CHECK(ctx->sc); 7800 gen_helper_mtc0_segctl2(cpu_env, arg); 7801 register_name = "SegCtl2"; 7802 break; 7803 case CP0_REG05__PWBASE: 7804 check_pw(ctx); 7805 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase)); 7806 register_name = "PWBase"; 7807 break; 7808 case CP0_REG05__PWFIELD: 7809 check_pw(ctx); 7810 gen_helper_mtc0_pwfield(cpu_env, arg); 7811 register_name = "PWField"; 7812 break; 7813 case CP0_REG05__PWSIZE: 7814 check_pw(ctx); 7815 gen_helper_mtc0_pwsize(cpu_env, arg); 7816 register_name = "PWSize"; 7817 break; 7818 default: 7819 goto cp0_unimplemented; 7820 } 7821 break; 7822 case CP0_REGISTER_06: 7823 switch (sel) { 7824 case CP0_REG06__WIRED: 7825 gen_helper_mtc0_wired(cpu_env, arg); 7826 register_name = "Wired"; 7827 break; 7828 case CP0_REG06__SRSCONF0: 7829 check_insn(ctx, ISA_MIPS_R2); 7830 gen_helper_mtc0_srsconf0(cpu_env, arg); 7831 register_name = "SRSConf0"; 7832 break; 7833 case CP0_REG06__SRSCONF1: 7834 check_insn(ctx, ISA_MIPS_R2); 7835 gen_helper_mtc0_srsconf1(cpu_env, arg); 7836 register_name = "SRSConf1"; 7837 break; 7838 case CP0_REG06__SRSCONF2: 7839 check_insn(ctx, ISA_MIPS_R2); 7840 gen_helper_mtc0_srsconf2(cpu_env, arg); 7841 register_name = "SRSConf2"; 7842 break; 7843 case CP0_REG06__SRSCONF3: 7844 check_insn(ctx, ISA_MIPS_R2); 7845 gen_helper_mtc0_srsconf3(cpu_env, arg); 7846 register_name = "SRSConf3"; 7847 break; 7848 case CP0_REG06__SRSCONF4: 7849 check_insn(ctx, ISA_MIPS_R2); 7850 gen_helper_mtc0_srsconf4(cpu_env, arg); 7851 register_name = "SRSConf4"; 7852 break; 7853 case CP0_REG06__PWCTL: 7854 check_pw(ctx); 7855 gen_helper_mtc0_pwctl(cpu_env, arg); 7856 register_name = "PWCtl"; 7857 break; 7858 default: 7859 goto cp0_unimplemented; 7860 } 7861 break; 7862 case CP0_REGISTER_07: 7863 switch (sel) { 7864 case CP0_REG07__HWRENA: 7865 check_insn(ctx, ISA_MIPS_R2); 7866 gen_helper_mtc0_hwrena(cpu_env, arg); 7867 ctx->base.is_jmp = DISAS_STOP; 7868 register_name = "HWREna"; 7869 break; 7870 default: 7871 goto cp0_unimplemented; 7872 } 7873 break; 7874 case CP0_REGISTER_08: 7875 switch (sel) { 7876 case CP0_REG08__BADVADDR: 7877 /* ignored */ 7878 register_name = "BadVAddr"; 7879 break; 7880 case CP0_REG08__BADINSTR: 7881 /* ignored */ 7882 register_name = "BadInstr"; 7883 break; 7884 case CP0_REG08__BADINSTRP: 7885 /* ignored */ 7886 register_name = "BadInstrP"; 7887 break; 7888 case CP0_REG08__BADINSTRX: 7889 /* ignored */ 7890 register_name = "BadInstrX"; 7891 break; 7892 default: 7893 goto cp0_unimplemented; 7894 } 7895 break; 7896 case CP0_REGISTER_09: 7897 switch (sel) { 7898 case CP0_REG09__COUNT: 7899 gen_helper_mtc0_count(cpu_env, arg); 7900 register_name = "Count"; 7901 break; 7902 case CP0_REG09__SAARI: 7903 CP0_CHECK(ctx->saar); 7904 gen_helper_mtc0_saari(cpu_env, arg); 7905 register_name = "SAARI"; 7906 break; 7907 case CP0_REG09__SAAR: 7908 CP0_CHECK(ctx->saar); 7909 gen_helper_mtc0_saar(cpu_env, arg); 7910 register_name = "SAAR"; 7911 break; 7912 default: 7913 goto cp0_unimplemented; 7914 } 7915 /* Stop translation as we may have switched the execution mode */ 7916 ctx->base.is_jmp = DISAS_STOP; 7917 break; 7918 case CP0_REGISTER_10: 7919 switch (sel) { 7920 case CP0_REG10__ENTRYHI: 7921 gen_helper_mtc0_entryhi(cpu_env, arg); 7922 register_name = "EntryHi"; 7923 break; 7924 default: 7925 goto cp0_unimplemented; 7926 } 7927 break; 7928 case CP0_REGISTER_11: 7929 switch (sel) { 7930 case CP0_REG11__COMPARE: 7931 gen_helper_mtc0_compare(cpu_env, arg); 7932 register_name = "Compare"; 7933 break; 7934 /* 6,7 are implementation dependent */ 7935 default: 7936 goto cp0_unimplemented; 7937 } 7938 /* Stop translation as we may have switched the execution mode */ 7939 ctx->base.is_jmp = DISAS_STOP; 7940 break; 7941 case CP0_REGISTER_12: 7942 switch (sel) { 7943 case CP0_REG12__STATUS: 7944 save_cpu_state(ctx, 1); 7945 gen_helper_mtc0_status(cpu_env, arg); 7946 /* DISAS_STOP isn't good enough here, hflags may have changed. */ 7947 gen_save_pc(ctx->base.pc_next + 4); 7948 ctx->base.is_jmp = DISAS_EXIT; 7949 register_name = "Status"; 7950 break; 7951 case CP0_REG12__INTCTL: 7952 check_insn(ctx, ISA_MIPS_R2); 7953 gen_helper_mtc0_intctl(cpu_env, arg); 7954 /* Stop translation as we may have switched the execution mode */ 7955 ctx->base.is_jmp = DISAS_STOP; 7956 register_name = "IntCtl"; 7957 break; 7958 case CP0_REG12__SRSCTL: 7959 check_insn(ctx, ISA_MIPS_R2); 7960 gen_helper_mtc0_srsctl(cpu_env, arg); 7961 /* Stop translation as we may have switched the execution mode */ 7962 ctx->base.is_jmp = DISAS_STOP; 7963 register_name = "SRSCtl"; 7964 break; 7965 case CP0_REG12__SRSMAP: 7966 check_insn(ctx, ISA_MIPS_R2); 7967 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); 7968 /* Stop translation as we may have switched the execution mode */ 7969 ctx->base.is_jmp = DISAS_STOP; 7970 register_name = "SRSMap"; 7971 break; 7972 default: 7973 goto cp0_unimplemented; 7974 } 7975 break; 7976 case CP0_REGISTER_13: 7977 switch (sel) { 7978 case CP0_REG13__CAUSE: 7979 save_cpu_state(ctx, 1); 7980 gen_helper_mtc0_cause(cpu_env, arg); 7981 /* 7982 * Stop translation as we may have triggered an interrupt. 7983 * DISAS_STOP isn't sufficient, we need to ensure we break out of 7984 * translated code to check for pending interrupts. 7985 */ 7986 gen_save_pc(ctx->base.pc_next + 4); 7987 ctx->base.is_jmp = DISAS_EXIT; 7988 register_name = "Cause"; 7989 break; 7990 default: 7991 goto cp0_unimplemented; 7992 } 7993 break; 7994 case CP0_REGISTER_14: 7995 switch (sel) { 7996 case CP0_REG14__EPC: 7997 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC)); 7998 register_name = "EPC"; 7999 break; 8000 default: 8001 goto cp0_unimplemented; 8002 } 8003 break; 8004 case CP0_REGISTER_15: 8005 switch (sel) { 8006 case CP0_REG15__PRID: 8007 /* ignored */ 8008 register_name = "PRid"; 8009 break; 8010 case CP0_REG15__EBASE: 8011 check_insn(ctx, ISA_MIPS_R2); 8012 gen_helper_mtc0_ebase(cpu_env, arg); 8013 register_name = "EBase"; 8014 break; 8015 default: 8016 goto cp0_unimplemented; 8017 } 8018 break; 8019 case CP0_REGISTER_16: 8020 switch (sel) { 8021 case CP0_REG16__CONFIG: 8022 gen_helper_mtc0_config0(cpu_env, arg); 8023 register_name = "Config"; 8024 /* Stop translation as we may have switched the execution mode */ 8025 ctx->base.is_jmp = DISAS_STOP; 8026 break; 8027 case CP0_REG16__CONFIG1: 8028 /* ignored, read only */ 8029 register_name = "Config1"; 8030 break; 8031 case CP0_REG16__CONFIG2: 8032 gen_helper_mtc0_config2(cpu_env, arg); 8033 register_name = "Config2"; 8034 /* Stop translation as we may have switched the execution mode */ 8035 ctx->base.is_jmp = DISAS_STOP; 8036 break; 8037 case CP0_REG16__CONFIG3: 8038 gen_helper_mtc0_config3(cpu_env, arg); 8039 register_name = "Config3"; 8040 /* Stop translation as we may have switched the execution mode */ 8041 ctx->base.is_jmp = DISAS_STOP; 8042 break; 8043 case CP0_REG16__CONFIG4: 8044 /* currently ignored */ 8045 register_name = "Config4"; 8046 break; 8047 case CP0_REG16__CONFIG5: 8048 gen_helper_mtc0_config5(cpu_env, arg); 8049 register_name = "Config5"; 8050 /* Stop translation as we may have switched the execution mode */ 8051 ctx->base.is_jmp = DISAS_STOP; 8052 break; 8053 /* 6,7 are implementation dependent */ 8054 default: 8055 register_name = "Invalid config selector"; 8056 goto cp0_unimplemented; 8057 } 8058 break; 8059 case CP0_REGISTER_17: 8060 switch (sel) { 8061 case CP0_REG17__LLADDR: 8062 gen_helper_mtc0_lladdr(cpu_env, arg); 8063 register_name = "LLAddr"; 8064 break; 8065 case CP0_REG17__MAAR: 8066 CP0_CHECK(ctx->mrp); 8067 gen_helper_mtc0_maar(cpu_env, arg); 8068 register_name = "MAAR"; 8069 break; 8070 case CP0_REG17__MAARI: 8071 CP0_CHECK(ctx->mrp); 8072 gen_helper_mtc0_maari(cpu_env, arg); 8073 register_name = "MAARI"; 8074 break; 8075 default: 8076 goto cp0_unimplemented; 8077 } 8078 break; 8079 case CP0_REGISTER_18: 8080 switch (sel) { 8081 case CP0_REG18__WATCHLO0: 8082 case CP0_REG18__WATCHLO1: 8083 case CP0_REG18__WATCHLO2: 8084 case CP0_REG18__WATCHLO3: 8085 case CP0_REG18__WATCHLO4: 8086 case CP0_REG18__WATCHLO5: 8087 case CP0_REG18__WATCHLO6: 8088 case CP0_REG18__WATCHLO7: 8089 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 8090 gen_helper_0e1i(mtc0_watchlo, arg, sel); 8091 register_name = "WatchLo"; 8092 break; 8093 default: 8094 goto cp0_unimplemented; 8095 } 8096 break; 8097 case CP0_REGISTER_19: 8098 switch (sel) { 8099 case CP0_REG19__WATCHHI0: 8100 case CP0_REG19__WATCHHI1: 8101 case CP0_REG19__WATCHHI2: 8102 case CP0_REG19__WATCHHI3: 8103 case CP0_REG19__WATCHHI4: 8104 case CP0_REG19__WATCHHI5: 8105 case CP0_REG19__WATCHHI6: 8106 case CP0_REG19__WATCHHI7: 8107 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 8108 gen_helper_0e1i(mtc0_watchhi, arg, sel); 8109 register_name = "WatchHi"; 8110 break; 8111 default: 8112 goto cp0_unimplemented; 8113 } 8114 break; 8115 case CP0_REGISTER_20: 8116 switch (sel) { 8117 case CP0_REG20__XCONTEXT: 8118 check_insn(ctx, ISA_MIPS3); 8119 gen_helper_mtc0_xcontext(cpu_env, arg); 8120 register_name = "XContext"; 8121 break; 8122 default: 8123 goto cp0_unimplemented; 8124 } 8125 break; 8126 case CP0_REGISTER_21: 8127 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 8128 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 8129 switch (sel) { 8130 case 0: 8131 gen_helper_mtc0_framemask(cpu_env, arg); 8132 register_name = "Framemask"; 8133 break; 8134 default: 8135 goto cp0_unimplemented; 8136 } 8137 break; 8138 case CP0_REGISTER_22: 8139 /* ignored */ 8140 register_name = "Diagnostic"; /* implementation dependent */ 8141 break; 8142 case CP0_REGISTER_23: 8143 switch (sel) { 8144 case CP0_REG23__DEBUG: 8145 gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */ 8146 /* DISAS_STOP isn't good enough here, hflags may have changed. */ 8147 gen_save_pc(ctx->base.pc_next + 4); 8148 ctx->base.is_jmp = DISAS_EXIT; 8149 register_name = "Debug"; 8150 break; 8151 case CP0_REG23__TRACECONTROL: 8152 /* PDtrace support */ 8153 /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */ 8154 /* Stop translation as we may have switched the execution mode */ 8155 ctx->base.is_jmp = DISAS_STOP; 8156 register_name = "TraceControl"; 8157 goto cp0_unimplemented; 8158 case CP0_REG23__TRACECONTROL2: 8159 /* PDtrace support */ 8160 /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */ 8161 /* Stop translation as we may have switched the execution mode */ 8162 ctx->base.is_jmp = DISAS_STOP; 8163 register_name = "TraceControl2"; 8164 goto cp0_unimplemented; 8165 case CP0_REG23__USERTRACEDATA1: 8166 /* PDtrace support */ 8167 /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/ 8168 /* Stop translation as we may have switched the execution mode */ 8169 ctx->base.is_jmp = DISAS_STOP; 8170 register_name = "UserTraceData1"; 8171 goto cp0_unimplemented; 8172 case CP0_REG23__TRACEIBPC: 8173 /* PDtrace support */ 8174 /* gen_helper_mtc0_traceibpc(cpu_env, arg); */ 8175 /* Stop translation as we may have switched the execution mode */ 8176 ctx->base.is_jmp = DISAS_STOP; 8177 register_name = "TraceIBPC"; 8178 goto cp0_unimplemented; 8179 case CP0_REG23__TRACEDBPC: 8180 /* PDtrace support */ 8181 /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */ 8182 /* Stop translation as we may have switched the execution mode */ 8183 ctx->base.is_jmp = DISAS_STOP; 8184 register_name = "TraceDBPC"; 8185 goto cp0_unimplemented; 8186 default: 8187 goto cp0_unimplemented; 8188 } 8189 break; 8190 case CP0_REGISTER_24: 8191 switch (sel) { 8192 case CP0_REG24__DEPC: 8193 /* EJTAG support */ 8194 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC)); 8195 register_name = "DEPC"; 8196 break; 8197 default: 8198 goto cp0_unimplemented; 8199 } 8200 break; 8201 case CP0_REGISTER_25: 8202 switch (sel) { 8203 case CP0_REG25__PERFCTL0: 8204 gen_helper_mtc0_performance0(cpu_env, arg); 8205 register_name = "Performance0"; 8206 break; 8207 case CP0_REG25__PERFCNT0: 8208 /* gen_helper_mtc0_performance1(cpu_env, arg); */ 8209 register_name = "Performance1"; 8210 goto cp0_unimplemented; 8211 case CP0_REG25__PERFCTL1: 8212 /* gen_helper_mtc0_performance2(cpu_env, arg); */ 8213 register_name = "Performance2"; 8214 goto cp0_unimplemented; 8215 case CP0_REG25__PERFCNT1: 8216 /* gen_helper_mtc0_performance3(cpu_env, arg); */ 8217 register_name = "Performance3"; 8218 goto cp0_unimplemented; 8219 case CP0_REG25__PERFCTL2: 8220 /* gen_helper_mtc0_performance4(cpu_env, arg); */ 8221 register_name = "Performance4"; 8222 goto cp0_unimplemented; 8223 case CP0_REG25__PERFCNT2: 8224 /* gen_helper_mtc0_performance5(cpu_env, arg); */ 8225 register_name = "Performance5"; 8226 goto cp0_unimplemented; 8227 case CP0_REG25__PERFCTL3: 8228 /* gen_helper_mtc0_performance6(cpu_env, arg); */ 8229 register_name = "Performance6"; 8230 goto cp0_unimplemented; 8231 case CP0_REG25__PERFCNT3: 8232 /* gen_helper_mtc0_performance7(cpu_env, arg); */ 8233 register_name = "Performance7"; 8234 goto cp0_unimplemented; 8235 default: 8236 goto cp0_unimplemented; 8237 } 8238 break; 8239 case CP0_REGISTER_26: 8240 switch (sel) { 8241 case CP0_REG26__ERRCTL: 8242 gen_helper_mtc0_errctl(cpu_env, arg); 8243 ctx->base.is_jmp = DISAS_STOP; 8244 register_name = "ErrCtl"; 8245 break; 8246 default: 8247 goto cp0_unimplemented; 8248 } 8249 break; 8250 case CP0_REGISTER_27: 8251 switch (sel) { 8252 case CP0_REG27__CACHERR: 8253 /* ignored */ 8254 register_name = "CacheErr"; 8255 break; 8256 default: 8257 goto cp0_unimplemented; 8258 } 8259 break; 8260 case CP0_REGISTER_28: 8261 switch (sel) { 8262 case CP0_REG28__TAGLO: 8263 case CP0_REG28__TAGLO1: 8264 case CP0_REG28__TAGLO2: 8265 case CP0_REG28__TAGLO3: 8266 gen_helper_mtc0_taglo(cpu_env, arg); 8267 register_name = "TagLo"; 8268 break; 8269 case CP0_REG28__DATALO: 8270 case CP0_REG28__DATALO1: 8271 case CP0_REG28__DATALO2: 8272 case CP0_REG28__DATALO3: 8273 gen_helper_mtc0_datalo(cpu_env, arg); 8274 register_name = "DataLo"; 8275 break; 8276 default: 8277 goto cp0_unimplemented; 8278 } 8279 break; 8280 case CP0_REGISTER_29: 8281 switch (sel) { 8282 case CP0_REG29__TAGHI: 8283 case CP0_REG29__TAGHI1: 8284 case CP0_REG29__TAGHI2: 8285 case CP0_REG29__TAGHI3: 8286 gen_helper_mtc0_taghi(cpu_env, arg); 8287 register_name = "TagHi"; 8288 break; 8289 case CP0_REG29__DATAHI: 8290 case CP0_REG29__DATAHI1: 8291 case CP0_REG29__DATAHI2: 8292 case CP0_REG29__DATAHI3: 8293 gen_helper_mtc0_datahi(cpu_env, arg); 8294 register_name = "DataHi"; 8295 break; 8296 default: 8297 register_name = "invalid sel"; 8298 goto cp0_unimplemented; 8299 } 8300 break; 8301 case CP0_REGISTER_30: 8302 switch (sel) { 8303 case CP0_REG30__ERROREPC: 8304 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); 8305 register_name = "ErrorEPC"; 8306 break; 8307 default: 8308 goto cp0_unimplemented; 8309 } 8310 break; 8311 case CP0_REGISTER_31: 8312 switch (sel) { 8313 case CP0_REG31__DESAVE: 8314 /* EJTAG support */ 8315 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); 8316 register_name = "DESAVE"; 8317 break; 8318 case CP0_REG31__KSCRATCH1: 8319 case CP0_REG31__KSCRATCH2: 8320 case CP0_REG31__KSCRATCH3: 8321 case CP0_REG31__KSCRATCH4: 8322 case CP0_REG31__KSCRATCH5: 8323 case CP0_REG31__KSCRATCH6: 8324 CP0_CHECK(ctx->kscrexist & (1 << sel)); 8325 tcg_gen_st_tl(arg, cpu_env, 8326 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); 8327 register_name = "KScratch"; 8328 break; 8329 default: 8330 goto cp0_unimplemented; 8331 } 8332 break; 8333 default: 8334 goto cp0_unimplemented; 8335 } 8336 trace_mips_translate_c0("dmtc0", register_name, reg, sel); 8337 8338 /* For simplicity assume that all writes can cause interrupts. */ 8339 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 8340 /* 8341 * DISAS_STOP isn't sufficient, we need to ensure we break out of 8342 * translated code to check for pending interrupts. 8343 */ 8344 gen_save_pc(ctx->base.pc_next + 4); 8345 ctx->base.is_jmp = DISAS_EXIT; 8346 } 8347 return; 8348 8349 cp0_unimplemented: 8350 qemu_log_mask(LOG_UNIMP, "dmtc0 %s (reg %d sel %d)\n", 8351 register_name, reg, sel); 8352 } 8353 #endif /* TARGET_MIPS64 */ 8354 8355 static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, 8356 int u, int sel, int h) 8357 { 8358 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 8359 TCGv t0 = tcg_temp_new(); 8360 8361 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && 8362 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != 8363 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) { 8364 tcg_gen_movi_tl(t0, -1); 8365 } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > 8366 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) { 8367 tcg_gen_movi_tl(t0, -1); 8368 } else if (u == 0) { 8369 switch (rt) { 8370 case 1: 8371 switch (sel) { 8372 case 1: 8373 gen_helper_mftc0_vpecontrol(t0, cpu_env); 8374 break; 8375 case 2: 8376 gen_helper_mftc0_vpeconf0(t0, cpu_env); 8377 break; 8378 default: 8379 goto die; 8380 break; 8381 } 8382 break; 8383 case 2: 8384 switch (sel) { 8385 case 1: 8386 gen_helper_mftc0_tcstatus(t0, cpu_env); 8387 break; 8388 case 2: 8389 gen_helper_mftc0_tcbind(t0, cpu_env); 8390 break; 8391 case 3: 8392 gen_helper_mftc0_tcrestart(t0, cpu_env); 8393 break; 8394 case 4: 8395 gen_helper_mftc0_tchalt(t0, cpu_env); 8396 break; 8397 case 5: 8398 gen_helper_mftc0_tccontext(t0, cpu_env); 8399 break; 8400 case 6: 8401 gen_helper_mftc0_tcschedule(t0, cpu_env); 8402 break; 8403 case 7: 8404 gen_helper_mftc0_tcschefback(t0, cpu_env); 8405 break; 8406 default: 8407 gen_mfc0(ctx, t0, rt, sel); 8408 break; 8409 } 8410 break; 8411 case 10: 8412 switch (sel) { 8413 case 0: 8414 gen_helper_mftc0_entryhi(t0, cpu_env); 8415 break; 8416 default: 8417 gen_mfc0(ctx, t0, rt, sel); 8418 break; 8419 } 8420 break; 8421 case 12: 8422 switch (sel) { 8423 case 0: 8424 gen_helper_mftc0_status(t0, cpu_env); 8425 break; 8426 default: 8427 gen_mfc0(ctx, t0, rt, sel); 8428 break; 8429 } 8430 break; 8431 case 13: 8432 switch (sel) { 8433 case 0: 8434 gen_helper_mftc0_cause(t0, cpu_env); 8435 break; 8436 default: 8437 goto die; 8438 break; 8439 } 8440 break; 8441 case 14: 8442 switch (sel) { 8443 case 0: 8444 gen_helper_mftc0_epc(t0, cpu_env); 8445 break; 8446 default: 8447 goto die; 8448 break; 8449 } 8450 break; 8451 case 15: 8452 switch (sel) { 8453 case 1: 8454 gen_helper_mftc0_ebase(t0, cpu_env); 8455 break; 8456 default: 8457 goto die; 8458 break; 8459 } 8460 break; 8461 case 16: 8462 switch (sel) { 8463 case 0: 8464 case 1: 8465 case 2: 8466 case 3: 8467 case 4: 8468 case 5: 8469 case 6: 8470 case 7: 8471 gen_helper_mftc0_configx(t0, cpu_env, tcg_constant_tl(sel)); 8472 break; 8473 default: 8474 goto die; 8475 break; 8476 } 8477 break; 8478 case 23: 8479 switch (sel) { 8480 case 0: 8481 gen_helper_mftc0_debug(t0, cpu_env); 8482 break; 8483 default: 8484 gen_mfc0(ctx, t0, rt, sel); 8485 break; 8486 } 8487 break; 8488 default: 8489 gen_mfc0(ctx, t0, rt, sel); 8490 } 8491 } else { 8492 switch (sel) { 8493 /* GPR registers. */ 8494 case 0: 8495 gen_helper_1e0i(mftgpr, t0, rt); 8496 break; 8497 /* Auxiliary CPU registers */ 8498 case 1: 8499 switch (rt) { 8500 case 0: 8501 gen_helper_1e0i(mftlo, t0, 0); 8502 break; 8503 case 1: 8504 gen_helper_1e0i(mfthi, t0, 0); 8505 break; 8506 case 2: 8507 gen_helper_1e0i(mftacx, t0, 0); 8508 break; 8509 case 4: 8510 gen_helper_1e0i(mftlo, t0, 1); 8511 break; 8512 case 5: 8513 gen_helper_1e0i(mfthi, t0, 1); 8514 break; 8515 case 6: 8516 gen_helper_1e0i(mftacx, t0, 1); 8517 break; 8518 case 8: 8519 gen_helper_1e0i(mftlo, t0, 2); 8520 break; 8521 case 9: 8522 gen_helper_1e0i(mfthi, t0, 2); 8523 break; 8524 case 10: 8525 gen_helper_1e0i(mftacx, t0, 2); 8526 break; 8527 case 12: 8528 gen_helper_1e0i(mftlo, t0, 3); 8529 break; 8530 case 13: 8531 gen_helper_1e0i(mfthi, t0, 3); 8532 break; 8533 case 14: 8534 gen_helper_1e0i(mftacx, t0, 3); 8535 break; 8536 case 16: 8537 gen_helper_mftdsp(t0, cpu_env); 8538 break; 8539 default: 8540 goto die; 8541 } 8542 break; 8543 /* Floating point (COP1). */ 8544 case 2: 8545 /* XXX: For now we support only a single FPU context. */ 8546 if (h == 0) { 8547 TCGv_i32 fp0 = tcg_temp_new_i32(); 8548 8549 gen_load_fpr32(ctx, fp0, rt); 8550 tcg_gen_ext_i32_tl(t0, fp0); 8551 } else { 8552 TCGv_i32 fp0 = tcg_temp_new_i32(); 8553 8554 gen_load_fpr32h(ctx, fp0, rt); 8555 tcg_gen_ext_i32_tl(t0, fp0); 8556 } 8557 break; 8558 case 3: 8559 /* XXX: For now we support only a single FPU context. */ 8560 gen_helper_1e0i(cfc1, t0, rt); 8561 break; 8562 /* COP2: Not implemented. */ 8563 case 4: 8564 case 5: 8565 /* fall through */ 8566 default: 8567 goto die; 8568 } 8569 } 8570 trace_mips_translate_tr("mftr", rt, u, sel, h); 8571 gen_store_gpr(t0, rd); 8572 return; 8573 8574 die: 8575 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h); 8576 gen_reserved_instruction(ctx); 8577 } 8578 8579 static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, 8580 int u, int sel, int h) 8581 { 8582 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 8583 TCGv t0 = tcg_temp_new(); 8584 8585 gen_load_gpr(t0, rt); 8586 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && 8587 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != 8588 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) { 8589 /* NOP */ 8590 ; 8591 } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > 8592 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) { 8593 /* NOP */ 8594 ; 8595 } else if (u == 0) { 8596 switch (rd) { 8597 case 1: 8598 switch (sel) { 8599 case 1: 8600 gen_helper_mttc0_vpecontrol(cpu_env, t0); 8601 break; 8602 case 2: 8603 gen_helper_mttc0_vpeconf0(cpu_env, t0); 8604 break; 8605 default: 8606 goto die; 8607 break; 8608 } 8609 break; 8610 case 2: 8611 switch (sel) { 8612 case 1: 8613 gen_helper_mttc0_tcstatus(cpu_env, t0); 8614 break; 8615 case 2: 8616 gen_helper_mttc0_tcbind(cpu_env, t0); 8617 break; 8618 case 3: 8619 gen_helper_mttc0_tcrestart(cpu_env, t0); 8620 break; 8621 case 4: 8622 gen_helper_mttc0_tchalt(cpu_env, t0); 8623 break; 8624 case 5: 8625 gen_helper_mttc0_tccontext(cpu_env, t0); 8626 break; 8627 case 6: 8628 gen_helper_mttc0_tcschedule(cpu_env, t0); 8629 break; 8630 case 7: 8631 gen_helper_mttc0_tcschefback(cpu_env, t0); 8632 break; 8633 default: 8634 gen_mtc0(ctx, t0, rd, sel); 8635 break; 8636 } 8637 break; 8638 case 10: 8639 switch (sel) { 8640 case 0: 8641 gen_helper_mttc0_entryhi(cpu_env, t0); 8642 break; 8643 default: 8644 gen_mtc0(ctx, t0, rd, sel); 8645 break; 8646 } 8647 break; 8648 case 12: 8649 switch (sel) { 8650 case 0: 8651 gen_helper_mttc0_status(cpu_env, t0); 8652 break; 8653 default: 8654 gen_mtc0(ctx, t0, rd, sel); 8655 break; 8656 } 8657 break; 8658 case 13: 8659 switch (sel) { 8660 case 0: 8661 gen_helper_mttc0_cause(cpu_env, t0); 8662 break; 8663 default: 8664 goto die; 8665 break; 8666 } 8667 break; 8668 case 15: 8669 switch (sel) { 8670 case 1: 8671 gen_helper_mttc0_ebase(cpu_env, t0); 8672 break; 8673 default: 8674 goto die; 8675 break; 8676 } 8677 break; 8678 case 23: 8679 switch (sel) { 8680 case 0: 8681 gen_helper_mttc0_debug(cpu_env, t0); 8682 break; 8683 default: 8684 gen_mtc0(ctx, t0, rd, sel); 8685 break; 8686 } 8687 break; 8688 default: 8689 gen_mtc0(ctx, t0, rd, sel); 8690 } 8691 } else { 8692 switch (sel) { 8693 /* GPR registers. */ 8694 case 0: 8695 gen_helper_0e1i(mttgpr, t0, rd); 8696 break; 8697 /* Auxiliary CPU registers */ 8698 case 1: 8699 switch (rd) { 8700 case 0: 8701 gen_helper_0e1i(mttlo, t0, 0); 8702 break; 8703 case 1: 8704 gen_helper_0e1i(mtthi, t0, 0); 8705 break; 8706 case 2: 8707 gen_helper_0e1i(mttacx, t0, 0); 8708 break; 8709 case 4: 8710 gen_helper_0e1i(mttlo, t0, 1); 8711 break; 8712 case 5: 8713 gen_helper_0e1i(mtthi, t0, 1); 8714 break; 8715 case 6: 8716 gen_helper_0e1i(mttacx, t0, 1); 8717 break; 8718 case 8: 8719 gen_helper_0e1i(mttlo, t0, 2); 8720 break; 8721 case 9: 8722 gen_helper_0e1i(mtthi, t0, 2); 8723 break; 8724 case 10: 8725 gen_helper_0e1i(mttacx, t0, 2); 8726 break; 8727 case 12: 8728 gen_helper_0e1i(mttlo, t0, 3); 8729 break; 8730 case 13: 8731 gen_helper_0e1i(mtthi, t0, 3); 8732 break; 8733 case 14: 8734 gen_helper_0e1i(mttacx, t0, 3); 8735 break; 8736 case 16: 8737 gen_helper_mttdsp(cpu_env, t0); 8738 break; 8739 default: 8740 goto die; 8741 } 8742 break; 8743 /* Floating point (COP1). */ 8744 case 2: 8745 /* XXX: For now we support only a single FPU context. */ 8746 if (h == 0) { 8747 TCGv_i32 fp0 = tcg_temp_new_i32(); 8748 8749 tcg_gen_trunc_tl_i32(fp0, t0); 8750 gen_store_fpr32(ctx, fp0, rd); 8751 } else { 8752 TCGv_i32 fp0 = tcg_temp_new_i32(); 8753 8754 tcg_gen_trunc_tl_i32(fp0, t0); 8755 gen_store_fpr32h(ctx, fp0, rd); 8756 } 8757 break; 8758 case 3: 8759 /* XXX: For now we support only a single FPU context. */ 8760 gen_helper_0e2i(ctc1, t0, tcg_constant_i32(rd), rt); 8761 /* Stop translation as we may have changed hflags */ 8762 ctx->base.is_jmp = DISAS_STOP; 8763 break; 8764 /* COP2: Not implemented. */ 8765 case 4: 8766 case 5: 8767 /* fall through */ 8768 default: 8769 goto die; 8770 } 8771 } 8772 trace_mips_translate_tr("mttr", rd, u, sel, h); 8773 return; 8774 8775 die: 8776 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h); 8777 gen_reserved_instruction(ctx); 8778 } 8779 8780 static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, 8781 int rt, int rd) 8782 { 8783 const char *opn = "ldst"; 8784 8785 check_cp0_enabled(ctx); 8786 switch (opc) { 8787 case OPC_MFC0: 8788 if (rt == 0) { 8789 /* Treat as NOP. */ 8790 return; 8791 } 8792 gen_mfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); 8793 opn = "mfc0"; 8794 break; 8795 case OPC_MTC0: 8796 { 8797 TCGv t0 = tcg_temp_new(); 8798 8799 gen_load_gpr(t0, rt); 8800 gen_mtc0(ctx, t0, rd, ctx->opcode & 0x7); 8801 } 8802 opn = "mtc0"; 8803 break; 8804 #if defined(TARGET_MIPS64) 8805 case OPC_DMFC0: 8806 check_insn(ctx, ISA_MIPS3); 8807 if (rt == 0) { 8808 /* Treat as NOP. */ 8809 return; 8810 } 8811 gen_dmfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); 8812 opn = "dmfc0"; 8813 break; 8814 case OPC_DMTC0: 8815 check_insn(ctx, ISA_MIPS3); 8816 { 8817 TCGv t0 = tcg_temp_new(); 8818 8819 gen_load_gpr(t0, rt); 8820 gen_dmtc0(ctx, t0, rd, ctx->opcode & 0x7); 8821 } 8822 opn = "dmtc0"; 8823 break; 8824 #endif 8825 case OPC_MFHC0: 8826 check_mvh(ctx); 8827 if (rt == 0) { 8828 /* Treat as NOP. */ 8829 return; 8830 } 8831 gen_mfhc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); 8832 opn = "mfhc0"; 8833 break; 8834 case OPC_MTHC0: 8835 check_mvh(ctx); 8836 { 8837 TCGv t0 = tcg_temp_new(); 8838 gen_load_gpr(t0, rt); 8839 gen_mthc0(ctx, t0, rd, ctx->opcode & 0x7); 8840 } 8841 opn = "mthc0"; 8842 break; 8843 case OPC_MFTR: 8844 check_cp0_enabled(ctx); 8845 if (rd == 0) { 8846 /* Treat as NOP. */ 8847 return; 8848 } 8849 gen_mftr(env, ctx, rt, rd, (ctx->opcode >> 5) & 1, 8850 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); 8851 opn = "mftr"; 8852 break; 8853 case OPC_MTTR: 8854 check_cp0_enabled(ctx); 8855 gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1, 8856 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); 8857 opn = "mttr"; 8858 break; 8859 case OPC_TLBWI: 8860 opn = "tlbwi"; 8861 if (!env->tlb->helper_tlbwi) { 8862 goto die; 8863 } 8864 gen_helper_tlbwi(cpu_env); 8865 break; 8866 case OPC_TLBINV: 8867 opn = "tlbinv"; 8868 if (ctx->ie >= 2) { 8869 if (!env->tlb->helper_tlbinv) { 8870 goto die; 8871 } 8872 gen_helper_tlbinv(cpu_env); 8873 } /* treat as nop if TLBINV not supported */ 8874 break; 8875 case OPC_TLBINVF: 8876 opn = "tlbinvf"; 8877 if (ctx->ie >= 2) { 8878 if (!env->tlb->helper_tlbinvf) { 8879 goto die; 8880 } 8881 gen_helper_tlbinvf(cpu_env); 8882 } /* treat as nop if TLBINV not supported */ 8883 break; 8884 case OPC_TLBWR: 8885 opn = "tlbwr"; 8886 if (!env->tlb->helper_tlbwr) { 8887 goto die; 8888 } 8889 gen_helper_tlbwr(cpu_env); 8890 break; 8891 case OPC_TLBP: 8892 opn = "tlbp"; 8893 if (!env->tlb->helper_tlbp) { 8894 goto die; 8895 } 8896 gen_helper_tlbp(cpu_env); 8897 break; 8898 case OPC_TLBR: 8899 opn = "tlbr"; 8900 if (!env->tlb->helper_tlbr) { 8901 goto die; 8902 } 8903 gen_helper_tlbr(cpu_env); 8904 break; 8905 case OPC_ERET: /* OPC_ERETNC */ 8906 if ((ctx->insn_flags & ISA_MIPS_R6) && 8907 (ctx->hflags & MIPS_HFLAG_BMASK)) { 8908 goto die; 8909 } else { 8910 int bit_shift = (ctx->hflags & MIPS_HFLAG_M16) ? 16 : 6; 8911 if (ctx->opcode & (1 << bit_shift)) { 8912 /* OPC_ERETNC */ 8913 opn = "eretnc"; 8914 check_insn(ctx, ISA_MIPS_R5); 8915 gen_helper_eretnc(cpu_env); 8916 } else { 8917 /* OPC_ERET */ 8918 opn = "eret"; 8919 check_insn(ctx, ISA_MIPS2); 8920 gen_helper_eret(cpu_env); 8921 } 8922 ctx->base.is_jmp = DISAS_EXIT; 8923 } 8924 break; 8925 case OPC_DERET: 8926 opn = "deret"; 8927 check_insn(ctx, ISA_MIPS_R1); 8928 if ((ctx->insn_flags & ISA_MIPS_R6) && 8929 (ctx->hflags & MIPS_HFLAG_BMASK)) { 8930 goto die; 8931 } 8932 if (!(ctx->hflags & MIPS_HFLAG_DM)) { 8933 MIPS_INVAL(opn); 8934 gen_reserved_instruction(ctx); 8935 } else { 8936 gen_helper_deret(cpu_env); 8937 ctx->base.is_jmp = DISAS_EXIT; 8938 } 8939 break; 8940 case OPC_WAIT: 8941 opn = "wait"; 8942 check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); 8943 if ((ctx->insn_flags & ISA_MIPS_R6) && 8944 (ctx->hflags & MIPS_HFLAG_BMASK)) { 8945 goto die; 8946 } 8947 /* If we get an exception, we want to restart at next instruction */ 8948 ctx->base.pc_next += 4; 8949 save_cpu_state(ctx, 1); 8950 ctx->base.pc_next -= 4; 8951 gen_helper_wait(cpu_env); 8952 ctx->base.is_jmp = DISAS_NORETURN; 8953 break; 8954 default: 8955 die: 8956 MIPS_INVAL(opn); 8957 gen_reserved_instruction(ctx); 8958 return; 8959 } 8960 (void)opn; /* avoid a compiler warning */ 8961 } 8962 #endif /* !CONFIG_USER_ONLY */ 8963 8964 /* CP1 Branches (before delay slot) */ 8965 static void gen_compute_branch1(DisasContext *ctx, uint32_t op, 8966 int32_t cc, int32_t offset) 8967 { 8968 target_ulong btarget; 8969 TCGv_i32 t0 = tcg_temp_new_i32(); 8970 8971 if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { 8972 gen_reserved_instruction(ctx); 8973 return; 8974 } 8975 8976 if (cc != 0) { 8977 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); 8978 } 8979 8980 btarget = ctx->base.pc_next + 4 + offset; 8981 8982 switch (op) { 8983 case OPC_BC1F: 8984 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 8985 tcg_gen_not_i32(t0, t0); 8986 tcg_gen_andi_i32(t0, t0, 1); 8987 tcg_gen_extu_i32_tl(bcond, t0); 8988 goto not_likely; 8989 case OPC_BC1FL: 8990 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 8991 tcg_gen_not_i32(t0, t0); 8992 tcg_gen_andi_i32(t0, t0, 1); 8993 tcg_gen_extu_i32_tl(bcond, t0); 8994 goto likely; 8995 case OPC_BC1T: 8996 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 8997 tcg_gen_andi_i32(t0, t0, 1); 8998 tcg_gen_extu_i32_tl(bcond, t0); 8999 goto not_likely; 9000 case OPC_BC1TL: 9001 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 9002 tcg_gen_andi_i32(t0, t0, 1); 9003 tcg_gen_extu_i32_tl(bcond, t0); 9004 likely: 9005 ctx->hflags |= MIPS_HFLAG_BL; 9006 break; 9007 case OPC_BC1FANY2: 9008 { 9009 TCGv_i32 t1 = tcg_temp_new_i32(); 9010 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 9011 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); 9012 tcg_gen_nand_i32(t0, t0, t1); 9013 tcg_gen_andi_i32(t0, t0, 1); 9014 tcg_gen_extu_i32_tl(bcond, t0); 9015 } 9016 goto not_likely; 9017 case OPC_BC1TANY2: 9018 { 9019 TCGv_i32 t1 = tcg_temp_new_i32(); 9020 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 9021 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); 9022 tcg_gen_or_i32(t0, t0, t1); 9023 tcg_gen_andi_i32(t0, t0, 1); 9024 tcg_gen_extu_i32_tl(bcond, t0); 9025 } 9026 goto not_likely; 9027 case OPC_BC1FANY4: 9028 { 9029 TCGv_i32 t1 = tcg_temp_new_i32(); 9030 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 9031 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); 9032 tcg_gen_and_i32(t0, t0, t1); 9033 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 2)); 9034 tcg_gen_and_i32(t0, t0, t1); 9035 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3)); 9036 tcg_gen_nand_i32(t0, t0, t1); 9037 tcg_gen_andi_i32(t0, t0, 1); 9038 tcg_gen_extu_i32_tl(bcond, t0); 9039 } 9040 goto not_likely; 9041 case OPC_BC1TANY4: 9042 { 9043 TCGv_i32 t1 = tcg_temp_new_i32(); 9044 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 9045 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); 9046 tcg_gen_or_i32(t0, t0, t1); 9047 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 2)); 9048 tcg_gen_or_i32(t0, t0, t1); 9049 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3)); 9050 tcg_gen_or_i32(t0, t0, t1); 9051 tcg_gen_andi_i32(t0, t0, 1); 9052 tcg_gen_extu_i32_tl(bcond, t0); 9053 } 9054 not_likely: 9055 ctx->hflags |= MIPS_HFLAG_BC; 9056 break; 9057 default: 9058 MIPS_INVAL("cp1 cond branch"); 9059 gen_reserved_instruction(ctx); 9060 return; 9061 } 9062 ctx->btarget = btarget; 9063 ctx->hflags |= MIPS_HFLAG_BDS32; 9064 } 9065 9066 /* R6 CP1 Branches */ 9067 static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op, 9068 int32_t ft, int32_t offset, 9069 int delayslot_size) 9070 { 9071 target_ulong btarget; 9072 TCGv_i64 t0 = tcg_temp_new_i64(); 9073 9074 if (ctx->hflags & MIPS_HFLAG_BMASK) { 9075 #ifdef MIPS_DEBUG_DISAS 9076 LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx 9077 "\n", ctx->base.pc_next); 9078 #endif 9079 gen_reserved_instruction(ctx); 9080 return; 9081 } 9082 9083 gen_load_fpr64(ctx, t0, ft); 9084 tcg_gen_andi_i64(t0, t0, 1); 9085 9086 btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 9087 9088 switch (op) { 9089 case OPC_BC1EQZ: 9090 tcg_gen_xori_i64(t0, t0, 1); 9091 ctx->hflags |= MIPS_HFLAG_BC; 9092 break; 9093 case OPC_BC1NEZ: 9094 /* t0 already set */ 9095 ctx->hflags |= MIPS_HFLAG_BC; 9096 break; 9097 default: 9098 MIPS_INVAL("cp1 cond branch"); 9099 gen_reserved_instruction(ctx); 9100 return; 9101 } 9102 9103 tcg_gen_trunc_i64_tl(bcond, t0); 9104 9105 ctx->btarget = btarget; 9106 9107 switch (delayslot_size) { 9108 case 2: 9109 ctx->hflags |= MIPS_HFLAG_BDS16; 9110 break; 9111 case 4: 9112 ctx->hflags |= MIPS_HFLAG_BDS32; 9113 break; 9114 } 9115 } 9116 9117 /* Coprocessor 1 (FPU) */ 9118 9119 #define FOP(func, fmt) (((fmt) << 21) | (func)) 9120 9121 enum fopcode { 9122 OPC_ADD_S = FOP(0, FMT_S), 9123 OPC_SUB_S = FOP(1, FMT_S), 9124 OPC_MUL_S = FOP(2, FMT_S), 9125 OPC_DIV_S = FOP(3, FMT_S), 9126 OPC_SQRT_S = FOP(4, FMT_S), 9127 OPC_ABS_S = FOP(5, FMT_S), 9128 OPC_MOV_S = FOP(6, FMT_S), 9129 OPC_NEG_S = FOP(7, FMT_S), 9130 OPC_ROUND_L_S = FOP(8, FMT_S), 9131 OPC_TRUNC_L_S = FOP(9, FMT_S), 9132 OPC_CEIL_L_S = FOP(10, FMT_S), 9133 OPC_FLOOR_L_S = FOP(11, FMT_S), 9134 OPC_ROUND_W_S = FOP(12, FMT_S), 9135 OPC_TRUNC_W_S = FOP(13, FMT_S), 9136 OPC_CEIL_W_S = FOP(14, FMT_S), 9137 OPC_FLOOR_W_S = FOP(15, FMT_S), 9138 OPC_SEL_S = FOP(16, FMT_S), 9139 OPC_MOVCF_S = FOP(17, FMT_S), 9140 OPC_MOVZ_S = FOP(18, FMT_S), 9141 OPC_MOVN_S = FOP(19, FMT_S), 9142 OPC_SELEQZ_S = FOP(20, FMT_S), 9143 OPC_RECIP_S = FOP(21, FMT_S), 9144 OPC_RSQRT_S = FOP(22, FMT_S), 9145 OPC_SELNEZ_S = FOP(23, FMT_S), 9146 OPC_MADDF_S = FOP(24, FMT_S), 9147 OPC_MSUBF_S = FOP(25, FMT_S), 9148 OPC_RINT_S = FOP(26, FMT_S), 9149 OPC_CLASS_S = FOP(27, FMT_S), 9150 OPC_MIN_S = FOP(28, FMT_S), 9151 OPC_RECIP2_S = FOP(28, FMT_S), 9152 OPC_MINA_S = FOP(29, FMT_S), 9153 OPC_RECIP1_S = FOP(29, FMT_S), 9154 OPC_MAX_S = FOP(30, FMT_S), 9155 OPC_RSQRT1_S = FOP(30, FMT_S), 9156 OPC_MAXA_S = FOP(31, FMT_S), 9157 OPC_RSQRT2_S = FOP(31, FMT_S), 9158 OPC_CVT_D_S = FOP(33, FMT_S), 9159 OPC_CVT_W_S = FOP(36, FMT_S), 9160 OPC_CVT_L_S = FOP(37, FMT_S), 9161 OPC_CVT_PS_S = FOP(38, FMT_S), 9162 OPC_CMP_F_S = FOP(48, FMT_S), 9163 OPC_CMP_UN_S = FOP(49, FMT_S), 9164 OPC_CMP_EQ_S = FOP(50, FMT_S), 9165 OPC_CMP_UEQ_S = FOP(51, FMT_S), 9166 OPC_CMP_OLT_S = FOP(52, FMT_S), 9167 OPC_CMP_ULT_S = FOP(53, FMT_S), 9168 OPC_CMP_OLE_S = FOP(54, FMT_S), 9169 OPC_CMP_ULE_S = FOP(55, FMT_S), 9170 OPC_CMP_SF_S = FOP(56, FMT_S), 9171 OPC_CMP_NGLE_S = FOP(57, FMT_S), 9172 OPC_CMP_SEQ_S = FOP(58, FMT_S), 9173 OPC_CMP_NGL_S = FOP(59, FMT_S), 9174 OPC_CMP_LT_S = FOP(60, FMT_S), 9175 OPC_CMP_NGE_S = FOP(61, FMT_S), 9176 OPC_CMP_LE_S = FOP(62, FMT_S), 9177 OPC_CMP_NGT_S = FOP(63, FMT_S), 9178 9179 OPC_ADD_D = FOP(0, FMT_D), 9180 OPC_SUB_D = FOP(1, FMT_D), 9181 OPC_MUL_D = FOP(2, FMT_D), 9182 OPC_DIV_D = FOP(3, FMT_D), 9183 OPC_SQRT_D = FOP(4, FMT_D), 9184 OPC_ABS_D = FOP(5, FMT_D), 9185 OPC_MOV_D = FOP(6, FMT_D), 9186 OPC_NEG_D = FOP(7, FMT_D), 9187 OPC_ROUND_L_D = FOP(8, FMT_D), 9188 OPC_TRUNC_L_D = FOP(9, FMT_D), 9189 OPC_CEIL_L_D = FOP(10, FMT_D), 9190 OPC_FLOOR_L_D = FOP(11, FMT_D), 9191 OPC_ROUND_W_D = FOP(12, FMT_D), 9192 OPC_TRUNC_W_D = FOP(13, FMT_D), 9193 OPC_CEIL_W_D = FOP(14, FMT_D), 9194 OPC_FLOOR_W_D = FOP(15, FMT_D), 9195 OPC_SEL_D = FOP(16, FMT_D), 9196 OPC_MOVCF_D = FOP(17, FMT_D), 9197 OPC_MOVZ_D = FOP(18, FMT_D), 9198 OPC_MOVN_D = FOP(19, FMT_D), 9199 OPC_SELEQZ_D = FOP(20, FMT_D), 9200 OPC_RECIP_D = FOP(21, FMT_D), 9201 OPC_RSQRT_D = FOP(22, FMT_D), 9202 OPC_SELNEZ_D = FOP(23, FMT_D), 9203 OPC_MADDF_D = FOP(24, FMT_D), 9204 OPC_MSUBF_D = FOP(25, FMT_D), 9205 OPC_RINT_D = FOP(26, FMT_D), 9206 OPC_CLASS_D = FOP(27, FMT_D), 9207 OPC_MIN_D = FOP(28, FMT_D), 9208 OPC_RECIP2_D = FOP(28, FMT_D), 9209 OPC_MINA_D = FOP(29, FMT_D), 9210 OPC_RECIP1_D = FOP(29, FMT_D), 9211 OPC_MAX_D = FOP(30, FMT_D), 9212 OPC_RSQRT1_D = FOP(30, FMT_D), 9213 OPC_MAXA_D = FOP(31, FMT_D), 9214 OPC_RSQRT2_D = FOP(31, FMT_D), 9215 OPC_CVT_S_D = FOP(32, FMT_D), 9216 OPC_CVT_W_D = FOP(36, FMT_D), 9217 OPC_CVT_L_D = FOP(37, FMT_D), 9218 OPC_CMP_F_D = FOP(48, FMT_D), 9219 OPC_CMP_UN_D = FOP(49, FMT_D), 9220 OPC_CMP_EQ_D = FOP(50, FMT_D), 9221 OPC_CMP_UEQ_D = FOP(51, FMT_D), 9222 OPC_CMP_OLT_D = FOP(52, FMT_D), 9223 OPC_CMP_ULT_D = FOP(53, FMT_D), 9224 OPC_CMP_OLE_D = FOP(54, FMT_D), 9225 OPC_CMP_ULE_D = FOP(55, FMT_D), 9226 OPC_CMP_SF_D = FOP(56, FMT_D), 9227 OPC_CMP_NGLE_D = FOP(57, FMT_D), 9228 OPC_CMP_SEQ_D = FOP(58, FMT_D), 9229 OPC_CMP_NGL_D = FOP(59, FMT_D), 9230 OPC_CMP_LT_D = FOP(60, FMT_D), 9231 OPC_CMP_NGE_D = FOP(61, FMT_D), 9232 OPC_CMP_LE_D = FOP(62, FMT_D), 9233 OPC_CMP_NGT_D = FOP(63, FMT_D), 9234 9235 OPC_CVT_S_W = FOP(32, FMT_W), 9236 OPC_CVT_D_W = FOP(33, FMT_W), 9237 OPC_CVT_S_L = FOP(32, FMT_L), 9238 OPC_CVT_D_L = FOP(33, FMT_L), 9239 OPC_CVT_PS_PW = FOP(38, FMT_W), 9240 9241 OPC_ADD_PS = FOP(0, FMT_PS), 9242 OPC_SUB_PS = FOP(1, FMT_PS), 9243 OPC_MUL_PS = FOP(2, FMT_PS), 9244 OPC_DIV_PS = FOP(3, FMT_PS), 9245 OPC_ABS_PS = FOP(5, FMT_PS), 9246 OPC_MOV_PS = FOP(6, FMT_PS), 9247 OPC_NEG_PS = FOP(7, FMT_PS), 9248 OPC_MOVCF_PS = FOP(17, FMT_PS), 9249 OPC_MOVZ_PS = FOP(18, FMT_PS), 9250 OPC_MOVN_PS = FOP(19, FMT_PS), 9251 OPC_ADDR_PS = FOP(24, FMT_PS), 9252 OPC_MULR_PS = FOP(26, FMT_PS), 9253 OPC_RECIP2_PS = FOP(28, FMT_PS), 9254 OPC_RECIP1_PS = FOP(29, FMT_PS), 9255 OPC_RSQRT1_PS = FOP(30, FMT_PS), 9256 OPC_RSQRT2_PS = FOP(31, FMT_PS), 9257 9258 OPC_CVT_S_PU = FOP(32, FMT_PS), 9259 OPC_CVT_PW_PS = FOP(36, FMT_PS), 9260 OPC_CVT_S_PL = FOP(40, FMT_PS), 9261 OPC_PLL_PS = FOP(44, FMT_PS), 9262 OPC_PLU_PS = FOP(45, FMT_PS), 9263 OPC_PUL_PS = FOP(46, FMT_PS), 9264 OPC_PUU_PS = FOP(47, FMT_PS), 9265 OPC_CMP_F_PS = FOP(48, FMT_PS), 9266 OPC_CMP_UN_PS = FOP(49, FMT_PS), 9267 OPC_CMP_EQ_PS = FOP(50, FMT_PS), 9268 OPC_CMP_UEQ_PS = FOP(51, FMT_PS), 9269 OPC_CMP_OLT_PS = FOP(52, FMT_PS), 9270 OPC_CMP_ULT_PS = FOP(53, FMT_PS), 9271 OPC_CMP_OLE_PS = FOP(54, FMT_PS), 9272 OPC_CMP_ULE_PS = FOP(55, FMT_PS), 9273 OPC_CMP_SF_PS = FOP(56, FMT_PS), 9274 OPC_CMP_NGLE_PS = FOP(57, FMT_PS), 9275 OPC_CMP_SEQ_PS = FOP(58, FMT_PS), 9276 OPC_CMP_NGL_PS = FOP(59, FMT_PS), 9277 OPC_CMP_LT_PS = FOP(60, FMT_PS), 9278 OPC_CMP_NGE_PS = FOP(61, FMT_PS), 9279 OPC_CMP_LE_PS = FOP(62, FMT_PS), 9280 OPC_CMP_NGT_PS = FOP(63, FMT_PS), 9281 }; 9282 9283 enum r6_f_cmp_op { 9284 R6_OPC_CMP_AF_S = FOP(0, FMT_W), 9285 R6_OPC_CMP_UN_S = FOP(1, FMT_W), 9286 R6_OPC_CMP_EQ_S = FOP(2, FMT_W), 9287 R6_OPC_CMP_UEQ_S = FOP(3, FMT_W), 9288 R6_OPC_CMP_LT_S = FOP(4, FMT_W), 9289 R6_OPC_CMP_ULT_S = FOP(5, FMT_W), 9290 R6_OPC_CMP_LE_S = FOP(6, FMT_W), 9291 R6_OPC_CMP_ULE_S = FOP(7, FMT_W), 9292 R6_OPC_CMP_SAF_S = FOP(8, FMT_W), 9293 R6_OPC_CMP_SUN_S = FOP(9, FMT_W), 9294 R6_OPC_CMP_SEQ_S = FOP(10, FMT_W), 9295 R6_OPC_CMP_SEUQ_S = FOP(11, FMT_W), 9296 R6_OPC_CMP_SLT_S = FOP(12, FMT_W), 9297 R6_OPC_CMP_SULT_S = FOP(13, FMT_W), 9298 R6_OPC_CMP_SLE_S = FOP(14, FMT_W), 9299 R6_OPC_CMP_SULE_S = FOP(15, FMT_W), 9300 R6_OPC_CMP_OR_S = FOP(17, FMT_W), 9301 R6_OPC_CMP_UNE_S = FOP(18, FMT_W), 9302 R6_OPC_CMP_NE_S = FOP(19, FMT_W), 9303 R6_OPC_CMP_SOR_S = FOP(25, FMT_W), 9304 R6_OPC_CMP_SUNE_S = FOP(26, FMT_W), 9305 R6_OPC_CMP_SNE_S = FOP(27, FMT_W), 9306 9307 R6_OPC_CMP_AF_D = FOP(0, FMT_L), 9308 R6_OPC_CMP_UN_D = FOP(1, FMT_L), 9309 R6_OPC_CMP_EQ_D = FOP(2, FMT_L), 9310 R6_OPC_CMP_UEQ_D = FOP(3, FMT_L), 9311 R6_OPC_CMP_LT_D = FOP(4, FMT_L), 9312 R6_OPC_CMP_ULT_D = FOP(5, FMT_L), 9313 R6_OPC_CMP_LE_D = FOP(6, FMT_L), 9314 R6_OPC_CMP_ULE_D = FOP(7, FMT_L), 9315 R6_OPC_CMP_SAF_D = FOP(8, FMT_L), 9316 R6_OPC_CMP_SUN_D = FOP(9, FMT_L), 9317 R6_OPC_CMP_SEQ_D = FOP(10, FMT_L), 9318 R6_OPC_CMP_SEUQ_D = FOP(11, FMT_L), 9319 R6_OPC_CMP_SLT_D = FOP(12, FMT_L), 9320 R6_OPC_CMP_SULT_D = FOP(13, FMT_L), 9321 R6_OPC_CMP_SLE_D = FOP(14, FMT_L), 9322 R6_OPC_CMP_SULE_D = FOP(15, FMT_L), 9323 R6_OPC_CMP_OR_D = FOP(17, FMT_L), 9324 R6_OPC_CMP_UNE_D = FOP(18, FMT_L), 9325 R6_OPC_CMP_NE_D = FOP(19, FMT_L), 9326 R6_OPC_CMP_SOR_D = FOP(25, FMT_L), 9327 R6_OPC_CMP_SUNE_D = FOP(26, FMT_L), 9328 R6_OPC_CMP_SNE_D = FOP(27, FMT_L), 9329 }; 9330 9331 static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs) 9332 { 9333 TCGv t0 = tcg_temp_new(); 9334 9335 switch (opc) { 9336 case OPC_MFC1: 9337 { 9338 TCGv_i32 fp0 = tcg_temp_new_i32(); 9339 9340 gen_load_fpr32(ctx, fp0, fs); 9341 tcg_gen_ext_i32_tl(t0, fp0); 9342 } 9343 gen_store_gpr(t0, rt); 9344 break; 9345 case OPC_MTC1: 9346 gen_load_gpr(t0, rt); 9347 { 9348 TCGv_i32 fp0 = tcg_temp_new_i32(); 9349 9350 tcg_gen_trunc_tl_i32(fp0, t0); 9351 gen_store_fpr32(ctx, fp0, fs); 9352 } 9353 break; 9354 case OPC_CFC1: 9355 gen_helper_1e0i(cfc1, t0, fs); 9356 gen_store_gpr(t0, rt); 9357 break; 9358 case OPC_CTC1: 9359 gen_load_gpr(t0, rt); 9360 save_cpu_state(ctx, 0); 9361 gen_helper_0e2i(ctc1, t0, tcg_constant_i32(fs), rt); 9362 /* Stop translation as we may have changed hflags */ 9363 ctx->base.is_jmp = DISAS_STOP; 9364 break; 9365 #if defined(TARGET_MIPS64) 9366 case OPC_DMFC1: 9367 gen_load_fpr64(ctx, t0, fs); 9368 gen_store_gpr(t0, rt); 9369 break; 9370 case OPC_DMTC1: 9371 gen_load_gpr(t0, rt); 9372 gen_store_fpr64(ctx, t0, fs); 9373 break; 9374 #endif 9375 case OPC_MFHC1: 9376 { 9377 TCGv_i32 fp0 = tcg_temp_new_i32(); 9378 9379 gen_load_fpr32h(ctx, fp0, fs); 9380 tcg_gen_ext_i32_tl(t0, fp0); 9381 } 9382 gen_store_gpr(t0, rt); 9383 break; 9384 case OPC_MTHC1: 9385 gen_load_gpr(t0, rt); 9386 { 9387 TCGv_i32 fp0 = tcg_temp_new_i32(); 9388 9389 tcg_gen_trunc_tl_i32(fp0, t0); 9390 gen_store_fpr32h(ctx, fp0, fs); 9391 } 9392 break; 9393 default: 9394 MIPS_INVAL("cp1 move"); 9395 gen_reserved_instruction(ctx); 9396 return; 9397 } 9398 } 9399 9400 static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf) 9401 { 9402 TCGLabel *l1; 9403 TCGCond cond; 9404 TCGv_i32 t0; 9405 9406 if (rd == 0) { 9407 /* Treat as NOP. */ 9408 return; 9409 } 9410 9411 if (tf) { 9412 cond = TCG_COND_EQ; 9413 } else { 9414 cond = TCG_COND_NE; 9415 } 9416 9417 l1 = gen_new_label(); 9418 t0 = tcg_temp_new_i32(); 9419 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); 9420 tcg_gen_brcondi_i32(cond, t0, 0, l1); 9421 gen_load_gpr(cpu_gpr[rd], rs); 9422 gen_set_label(l1); 9423 } 9424 9425 static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc, 9426 int tf) 9427 { 9428 int cond; 9429 TCGv_i32 t0 = tcg_temp_new_i32(); 9430 TCGLabel *l1 = gen_new_label(); 9431 9432 if (tf) { 9433 cond = TCG_COND_EQ; 9434 } else { 9435 cond = TCG_COND_NE; 9436 } 9437 9438 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); 9439 tcg_gen_brcondi_i32(cond, t0, 0, l1); 9440 gen_load_fpr32(ctx, t0, fs); 9441 gen_store_fpr32(ctx, t0, fd); 9442 gen_set_label(l1); 9443 } 9444 9445 static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc, 9446 int tf) 9447 { 9448 int cond; 9449 TCGv_i32 t0 = tcg_temp_new_i32(); 9450 TCGv_i64 fp0; 9451 TCGLabel *l1 = gen_new_label(); 9452 9453 if (tf) { 9454 cond = TCG_COND_EQ; 9455 } else { 9456 cond = TCG_COND_NE; 9457 } 9458 9459 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); 9460 tcg_gen_brcondi_i32(cond, t0, 0, l1); 9461 fp0 = tcg_temp_new_i64(); 9462 gen_load_fpr64(ctx, fp0, fs); 9463 gen_store_fpr64(ctx, fp0, fd); 9464 gen_set_label(l1); 9465 } 9466 9467 static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd, 9468 int cc, int tf) 9469 { 9470 int cond; 9471 TCGv_i32 t0 = tcg_temp_new_i32(); 9472 TCGLabel *l1 = gen_new_label(); 9473 TCGLabel *l2 = gen_new_label(); 9474 9475 if (tf) { 9476 cond = TCG_COND_EQ; 9477 } else { 9478 cond = TCG_COND_NE; 9479 } 9480 9481 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); 9482 tcg_gen_brcondi_i32(cond, t0, 0, l1); 9483 gen_load_fpr32(ctx, t0, fs); 9484 gen_store_fpr32(ctx, t0, fd); 9485 gen_set_label(l1); 9486 9487 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc + 1)); 9488 tcg_gen_brcondi_i32(cond, t0, 0, l2); 9489 gen_load_fpr32h(ctx, t0, fs); 9490 gen_store_fpr32h(ctx, t0, fd); 9491 gen_set_label(l2); 9492 } 9493 9494 static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft, 9495 int fs) 9496 { 9497 TCGv_i32 t1 = tcg_constant_i32(0); 9498 TCGv_i32 fp0 = tcg_temp_new_i32(); 9499 TCGv_i32 fp1 = tcg_temp_new_i32(); 9500 TCGv_i32 fp2 = tcg_temp_new_i32(); 9501 gen_load_fpr32(ctx, fp0, fd); 9502 gen_load_fpr32(ctx, fp1, ft); 9503 gen_load_fpr32(ctx, fp2, fs); 9504 9505 switch (op1) { 9506 case OPC_SEL_S: 9507 tcg_gen_andi_i32(fp0, fp0, 1); 9508 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp0, t1, fp1, fp2); 9509 break; 9510 case OPC_SELEQZ_S: 9511 tcg_gen_andi_i32(fp1, fp1, 1); 9512 tcg_gen_movcond_i32(TCG_COND_EQ, fp0, fp1, t1, fp2, t1); 9513 break; 9514 case OPC_SELNEZ_S: 9515 tcg_gen_andi_i32(fp1, fp1, 1); 9516 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp1, t1, fp2, t1); 9517 break; 9518 default: 9519 MIPS_INVAL("gen_sel_s"); 9520 gen_reserved_instruction(ctx); 9521 break; 9522 } 9523 9524 gen_store_fpr32(ctx, fp0, fd); 9525 } 9526 9527 static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft, 9528 int fs) 9529 { 9530 TCGv_i64 t1 = tcg_constant_i64(0); 9531 TCGv_i64 fp0 = tcg_temp_new_i64(); 9532 TCGv_i64 fp1 = tcg_temp_new_i64(); 9533 TCGv_i64 fp2 = tcg_temp_new_i64(); 9534 gen_load_fpr64(ctx, fp0, fd); 9535 gen_load_fpr64(ctx, fp1, ft); 9536 gen_load_fpr64(ctx, fp2, fs); 9537 9538 switch (op1) { 9539 case OPC_SEL_D: 9540 tcg_gen_andi_i64(fp0, fp0, 1); 9541 tcg_gen_movcond_i64(TCG_COND_NE, fp0, fp0, t1, fp1, fp2); 9542 break; 9543 case OPC_SELEQZ_D: 9544 tcg_gen_andi_i64(fp1, fp1, 1); 9545 tcg_gen_movcond_i64(TCG_COND_EQ, fp0, fp1, t1, fp2, t1); 9546 break; 9547 case OPC_SELNEZ_D: 9548 tcg_gen_andi_i64(fp1, fp1, 1); 9549 tcg_gen_movcond_i64(TCG_COND_NE, fp0, fp1, t1, fp2, t1); 9550 break; 9551 default: 9552 MIPS_INVAL("gen_sel_d"); 9553 gen_reserved_instruction(ctx); 9554 break; 9555 } 9556 9557 gen_store_fpr64(ctx, fp0, fd); 9558 } 9559 9560 static void gen_farith(DisasContext *ctx, enum fopcode op1, 9561 int ft, int fs, int fd, int cc) 9562 { 9563 uint32_t func = ctx->opcode & 0x3f; 9564 switch (op1) { 9565 case OPC_ADD_S: 9566 { 9567 TCGv_i32 fp0 = tcg_temp_new_i32(); 9568 TCGv_i32 fp1 = tcg_temp_new_i32(); 9569 9570 gen_load_fpr32(ctx, fp0, fs); 9571 gen_load_fpr32(ctx, fp1, ft); 9572 gen_helper_float_add_s(fp0, cpu_env, fp0, fp1); 9573 gen_store_fpr32(ctx, fp0, fd); 9574 } 9575 break; 9576 case OPC_SUB_S: 9577 { 9578 TCGv_i32 fp0 = tcg_temp_new_i32(); 9579 TCGv_i32 fp1 = tcg_temp_new_i32(); 9580 9581 gen_load_fpr32(ctx, fp0, fs); 9582 gen_load_fpr32(ctx, fp1, ft); 9583 gen_helper_float_sub_s(fp0, cpu_env, fp0, fp1); 9584 gen_store_fpr32(ctx, fp0, fd); 9585 } 9586 break; 9587 case OPC_MUL_S: 9588 { 9589 TCGv_i32 fp0 = tcg_temp_new_i32(); 9590 TCGv_i32 fp1 = tcg_temp_new_i32(); 9591 9592 gen_load_fpr32(ctx, fp0, fs); 9593 gen_load_fpr32(ctx, fp1, ft); 9594 gen_helper_float_mul_s(fp0, cpu_env, fp0, fp1); 9595 gen_store_fpr32(ctx, fp0, fd); 9596 } 9597 break; 9598 case OPC_DIV_S: 9599 { 9600 TCGv_i32 fp0 = tcg_temp_new_i32(); 9601 TCGv_i32 fp1 = tcg_temp_new_i32(); 9602 9603 gen_load_fpr32(ctx, fp0, fs); 9604 gen_load_fpr32(ctx, fp1, ft); 9605 gen_helper_float_div_s(fp0, cpu_env, fp0, fp1); 9606 gen_store_fpr32(ctx, fp0, fd); 9607 } 9608 break; 9609 case OPC_SQRT_S: 9610 { 9611 TCGv_i32 fp0 = tcg_temp_new_i32(); 9612 9613 gen_load_fpr32(ctx, fp0, fs); 9614 gen_helper_float_sqrt_s(fp0, cpu_env, fp0); 9615 gen_store_fpr32(ctx, fp0, fd); 9616 } 9617 break; 9618 case OPC_ABS_S: 9619 { 9620 TCGv_i32 fp0 = tcg_temp_new_i32(); 9621 9622 gen_load_fpr32(ctx, fp0, fs); 9623 if (ctx->abs2008) { 9624 tcg_gen_andi_i32(fp0, fp0, 0x7fffffffUL); 9625 } else { 9626 gen_helper_float_abs_s(fp0, fp0); 9627 } 9628 gen_store_fpr32(ctx, fp0, fd); 9629 } 9630 break; 9631 case OPC_MOV_S: 9632 { 9633 TCGv_i32 fp0 = tcg_temp_new_i32(); 9634 9635 gen_load_fpr32(ctx, fp0, fs); 9636 gen_store_fpr32(ctx, fp0, fd); 9637 } 9638 break; 9639 case OPC_NEG_S: 9640 { 9641 TCGv_i32 fp0 = tcg_temp_new_i32(); 9642 9643 gen_load_fpr32(ctx, fp0, fs); 9644 if (ctx->abs2008) { 9645 tcg_gen_xori_i32(fp0, fp0, 1UL << 31); 9646 } else { 9647 gen_helper_float_chs_s(fp0, fp0); 9648 } 9649 gen_store_fpr32(ctx, fp0, fd); 9650 } 9651 break; 9652 case OPC_ROUND_L_S: 9653 check_cp1_64bitmode(ctx); 9654 { 9655 TCGv_i32 fp32 = tcg_temp_new_i32(); 9656 TCGv_i64 fp64 = tcg_temp_new_i64(); 9657 9658 gen_load_fpr32(ctx, fp32, fs); 9659 if (ctx->nan2008) { 9660 gen_helper_float_round_2008_l_s(fp64, cpu_env, fp32); 9661 } else { 9662 gen_helper_float_round_l_s(fp64, cpu_env, fp32); 9663 } 9664 gen_store_fpr64(ctx, fp64, fd); 9665 } 9666 break; 9667 case OPC_TRUNC_L_S: 9668 check_cp1_64bitmode(ctx); 9669 { 9670 TCGv_i32 fp32 = tcg_temp_new_i32(); 9671 TCGv_i64 fp64 = tcg_temp_new_i64(); 9672 9673 gen_load_fpr32(ctx, fp32, fs); 9674 if (ctx->nan2008) { 9675 gen_helper_float_trunc_2008_l_s(fp64, cpu_env, fp32); 9676 } else { 9677 gen_helper_float_trunc_l_s(fp64, cpu_env, fp32); 9678 } 9679 gen_store_fpr64(ctx, fp64, fd); 9680 } 9681 break; 9682 case OPC_CEIL_L_S: 9683 check_cp1_64bitmode(ctx); 9684 { 9685 TCGv_i32 fp32 = tcg_temp_new_i32(); 9686 TCGv_i64 fp64 = tcg_temp_new_i64(); 9687 9688 gen_load_fpr32(ctx, fp32, fs); 9689 if (ctx->nan2008) { 9690 gen_helper_float_ceil_2008_l_s(fp64, cpu_env, fp32); 9691 } else { 9692 gen_helper_float_ceil_l_s(fp64, cpu_env, fp32); 9693 } 9694 gen_store_fpr64(ctx, fp64, fd); 9695 } 9696 break; 9697 case OPC_FLOOR_L_S: 9698 check_cp1_64bitmode(ctx); 9699 { 9700 TCGv_i32 fp32 = tcg_temp_new_i32(); 9701 TCGv_i64 fp64 = tcg_temp_new_i64(); 9702 9703 gen_load_fpr32(ctx, fp32, fs); 9704 if (ctx->nan2008) { 9705 gen_helper_float_floor_2008_l_s(fp64, cpu_env, fp32); 9706 } else { 9707 gen_helper_float_floor_l_s(fp64, cpu_env, fp32); 9708 } 9709 gen_store_fpr64(ctx, fp64, fd); 9710 } 9711 break; 9712 case OPC_ROUND_W_S: 9713 { 9714 TCGv_i32 fp0 = tcg_temp_new_i32(); 9715 9716 gen_load_fpr32(ctx, fp0, fs); 9717 if (ctx->nan2008) { 9718 gen_helper_float_round_2008_w_s(fp0, cpu_env, fp0); 9719 } else { 9720 gen_helper_float_round_w_s(fp0, cpu_env, fp0); 9721 } 9722 gen_store_fpr32(ctx, fp0, fd); 9723 } 9724 break; 9725 case OPC_TRUNC_W_S: 9726 { 9727 TCGv_i32 fp0 = tcg_temp_new_i32(); 9728 9729 gen_load_fpr32(ctx, fp0, fs); 9730 if (ctx->nan2008) { 9731 gen_helper_float_trunc_2008_w_s(fp0, cpu_env, fp0); 9732 } else { 9733 gen_helper_float_trunc_w_s(fp0, cpu_env, fp0); 9734 } 9735 gen_store_fpr32(ctx, fp0, fd); 9736 } 9737 break; 9738 case OPC_CEIL_W_S: 9739 { 9740 TCGv_i32 fp0 = tcg_temp_new_i32(); 9741 9742 gen_load_fpr32(ctx, fp0, fs); 9743 if (ctx->nan2008) { 9744 gen_helper_float_ceil_2008_w_s(fp0, cpu_env, fp0); 9745 } else { 9746 gen_helper_float_ceil_w_s(fp0, cpu_env, fp0); 9747 } 9748 gen_store_fpr32(ctx, fp0, fd); 9749 } 9750 break; 9751 case OPC_FLOOR_W_S: 9752 { 9753 TCGv_i32 fp0 = tcg_temp_new_i32(); 9754 9755 gen_load_fpr32(ctx, fp0, fs); 9756 if (ctx->nan2008) { 9757 gen_helper_float_floor_2008_w_s(fp0, cpu_env, fp0); 9758 } else { 9759 gen_helper_float_floor_w_s(fp0, cpu_env, fp0); 9760 } 9761 gen_store_fpr32(ctx, fp0, fd); 9762 } 9763 break; 9764 case OPC_SEL_S: 9765 check_insn(ctx, ISA_MIPS_R6); 9766 gen_sel_s(ctx, op1, fd, ft, fs); 9767 break; 9768 case OPC_SELEQZ_S: 9769 check_insn(ctx, ISA_MIPS_R6); 9770 gen_sel_s(ctx, op1, fd, ft, fs); 9771 break; 9772 case OPC_SELNEZ_S: 9773 check_insn(ctx, ISA_MIPS_R6); 9774 gen_sel_s(ctx, op1, fd, ft, fs); 9775 break; 9776 case OPC_MOVCF_S: 9777 check_insn_opc_removed(ctx, ISA_MIPS_R6); 9778 gen_movcf_s(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); 9779 break; 9780 case OPC_MOVZ_S: 9781 check_insn_opc_removed(ctx, ISA_MIPS_R6); 9782 { 9783 TCGLabel *l1 = gen_new_label(); 9784 TCGv_i32 fp0; 9785 9786 if (ft != 0) { 9787 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); 9788 } 9789 fp0 = tcg_temp_new_i32(); 9790 gen_load_fpr32(ctx, fp0, fs); 9791 gen_store_fpr32(ctx, fp0, fd); 9792 gen_set_label(l1); 9793 } 9794 break; 9795 case OPC_MOVN_S: 9796 check_insn_opc_removed(ctx, ISA_MIPS_R6); 9797 { 9798 TCGLabel *l1 = gen_new_label(); 9799 TCGv_i32 fp0; 9800 9801 if (ft != 0) { 9802 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); 9803 fp0 = tcg_temp_new_i32(); 9804 gen_load_fpr32(ctx, fp0, fs); 9805 gen_store_fpr32(ctx, fp0, fd); 9806 gen_set_label(l1); 9807 } 9808 } 9809 break; 9810 case OPC_RECIP_S: 9811 { 9812 TCGv_i32 fp0 = tcg_temp_new_i32(); 9813 9814 gen_load_fpr32(ctx, fp0, fs); 9815 gen_helper_float_recip_s(fp0, cpu_env, fp0); 9816 gen_store_fpr32(ctx, fp0, fd); 9817 } 9818 break; 9819 case OPC_RSQRT_S: 9820 { 9821 TCGv_i32 fp0 = tcg_temp_new_i32(); 9822 9823 gen_load_fpr32(ctx, fp0, fs); 9824 gen_helper_float_rsqrt_s(fp0, cpu_env, fp0); 9825 gen_store_fpr32(ctx, fp0, fd); 9826 } 9827 break; 9828 case OPC_MADDF_S: 9829 check_insn(ctx, ISA_MIPS_R6); 9830 { 9831 TCGv_i32 fp0 = tcg_temp_new_i32(); 9832 TCGv_i32 fp1 = tcg_temp_new_i32(); 9833 TCGv_i32 fp2 = tcg_temp_new_i32(); 9834 gen_load_fpr32(ctx, fp0, fs); 9835 gen_load_fpr32(ctx, fp1, ft); 9836 gen_load_fpr32(ctx, fp2, fd); 9837 gen_helper_float_maddf_s(fp2, cpu_env, fp0, fp1, fp2); 9838 gen_store_fpr32(ctx, fp2, fd); 9839 } 9840 break; 9841 case OPC_MSUBF_S: 9842 check_insn(ctx, ISA_MIPS_R6); 9843 { 9844 TCGv_i32 fp0 = tcg_temp_new_i32(); 9845 TCGv_i32 fp1 = tcg_temp_new_i32(); 9846 TCGv_i32 fp2 = tcg_temp_new_i32(); 9847 gen_load_fpr32(ctx, fp0, fs); 9848 gen_load_fpr32(ctx, fp1, ft); 9849 gen_load_fpr32(ctx, fp2, fd); 9850 gen_helper_float_msubf_s(fp2, cpu_env, fp0, fp1, fp2); 9851 gen_store_fpr32(ctx, fp2, fd); 9852 } 9853 break; 9854 case OPC_RINT_S: 9855 check_insn(ctx, ISA_MIPS_R6); 9856 { 9857 TCGv_i32 fp0 = tcg_temp_new_i32(); 9858 gen_load_fpr32(ctx, fp0, fs); 9859 gen_helper_float_rint_s(fp0, cpu_env, fp0); 9860 gen_store_fpr32(ctx, fp0, fd); 9861 } 9862 break; 9863 case OPC_CLASS_S: 9864 check_insn(ctx, ISA_MIPS_R6); 9865 { 9866 TCGv_i32 fp0 = tcg_temp_new_i32(); 9867 gen_load_fpr32(ctx, fp0, fs); 9868 gen_helper_float_class_s(fp0, cpu_env, fp0); 9869 gen_store_fpr32(ctx, fp0, fd); 9870 } 9871 break; 9872 case OPC_MIN_S: /* OPC_RECIP2_S */ 9873 if (ctx->insn_flags & ISA_MIPS_R6) { 9874 /* OPC_MIN_S */ 9875 TCGv_i32 fp0 = tcg_temp_new_i32(); 9876 TCGv_i32 fp1 = tcg_temp_new_i32(); 9877 TCGv_i32 fp2 = tcg_temp_new_i32(); 9878 gen_load_fpr32(ctx, fp0, fs); 9879 gen_load_fpr32(ctx, fp1, ft); 9880 gen_helper_float_min_s(fp2, cpu_env, fp0, fp1); 9881 gen_store_fpr32(ctx, fp2, fd); 9882 } else { 9883 /* OPC_RECIP2_S */ 9884 check_cp1_64bitmode(ctx); 9885 { 9886 TCGv_i32 fp0 = tcg_temp_new_i32(); 9887 TCGv_i32 fp1 = tcg_temp_new_i32(); 9888 9889 gen_load_fpr32(ctx, fp0, fs); 9890 gen_load_fpr32(ctx, fp1, ft); 9891 gen_helper_float_recip2_s(fp0, cpu_env, fp0, fp1); 9892 gen_store_fpr32(ctx, fp0, fd); 9893 } 9894 } 9895 break; 9896 case OPC_MINA_S: /* OPC_RECIP1_S */ 9897 if (ctx->insn_flags & ISA_MIPS_R6) { 9898 /* OPC_MINA_S */ 9899 TCGv_i32 fp0 = tcg_temp_new_i32(); 9900 TCGv_i32 fp1 = tcg_temp_new_i32(); 9901 TCGv_i32 fp2 = tcg_temp_new_i32(); 9902 gen_load_fpr32(ctx, fp0, fs); 9903 gen_load_fpr32(ctx, fp1, ft); 9904 gen_helper_float_mina_s(fp2, cpu_env, fp0, fp1); 9905 gen_store_fpr32(ctx, fp2, fd); 9906 } else { 9907 /* OPC_RECIP1_S */ 9908 check_cp1_64bitmode(ctx); 9909 { 9910 TCGv_i32 fp0 = tcg_temp_new_i32(); 9911 9912 gen_load_fpr32(ctx, fp0, fs); 9913 gen_helper_float_recip1_s(fp0, cpu_env, fp0); 9914 gen_store_fpr32(ctx, fp0, fd); 9915 } 9916 } 9917 break; 9918 case OPC_MAX_S: /* OPC_RSQRT1_S */ 9919 if (ctx->insn_flags & ISA_MIPS_R6) { 9920 /* OPC_MAX_S */ 9921 TCGv_i32 fp0 = tcg_temp_new_i32(); 9922 TCGv_i32 fp1 = tcg_temp_new_i32(); 9923 gen_load_fpr32(ctx, fp0, fs); 9924 gen_load_fpr32(ctx, fp1, ft); 9925 gen_helper_float_max_s(fp1, cpu_env, fp0, fp1); 9926 gen_store_fpr32(ctx, fp1, fd); 9927 } else { 9928 /* OPC_RSQRT1_S */ 9929 check_cp1_64bitmode(ctx); 9930 { 9931 TCGv_i32 fp0 = tcg_temp_new_i32(); 9932 9933 gen_load_fpr32(ctx, fp0, fs); 9934 gen_helper_float_rsqrt1_s(fp0, cpu_env, fp0); 9935 gen_store_fpr32(ctx, fp0, fd); 9936 } 9937 } 9938 break; 9939 case OPC_MAXA_S: /* OPC_RSQRT2_S */ 9940 if (ctx->insn_flags & ISA_MIPS_R6) { 9941 /* OPC_MAXA_S */ 9942 TCGv_i32 fp0 = tcg_temp_new_i32(); 9943 TCGv_i32 fp1 = tcg_temp_new_i32(); 9944 gen_load_fpr32(ctx, fp0, fs); 9945 gen_load_fpr32(ctx, fp1, ft); 9946 gen_helper_float_maxa_s(fp1, cpu_env, fp0, fp1); 9947 gen_store_fpr32(ctx, fp1, fd); 9948 } else { 9949 /* OPC_RSQRT2_S */ 9950 check_cp1_64bitmode(ctx); 9951 { 9952 TCGv_i32 fp0 = tcg_temp_new_i32(); 9953 TCGv_i32 fp1 = tcg_temp_new_i32(); 9954 9955 gen_load_fpr32(ctx, fp0, fs); 9956 gen_load_fpr32(ctx, fp1, ft); 9957 gen_helper_float_rsqrt2_s(fp0, cpu_env, fp0, fp1); 9958 gen_store_fpr32(ctx, fp0, fd); 9959 } 9960 } 9961 break; 9962 case OPC_CVT_D_S: 9963 check_cp1_registers(ctx, fd); 9964 { 9965 TCGv_i32 fp32 = tcg_temp_new_i32(); 9966 TCGv_i64 fp64 = tcg_temp_new_i64(); 9967 9968 gen_load_fpr32(ctx, fp32, fs); 9969 gen_helper_float_cvtd_s(fp64, cpu_env, fp32); 9970 gen_store_fpr64(ctx, fp64, fd); 9971 } 9972 break; 9973 case OPC_CVT_W_S: 9974 { 9975 TCGv_i32 fp0 = tcg_temp_new_i32(); 9976 9977 gen_load_fpr32(ctx, fp0, fs); 9978 if (ctx->nan2008) { 9979 gen_helper_float_cvt_2008_w_s(fp0, cpu_env, fp0); 9980 } else { 9981 gen_helper_float_cvt_w_s(fp0, cpu_env, fp0); 9982 } 9983 gen_store_fpr32(ctx, fp0, fd); 9984 } 9985 break; 9986 case OPC_CVT_L_S: 9987 check_cp1_64bitmode(ctx); 9988 { 9989 TCGv_i32 fp32 = tcg_temp_new_i32(); 9990 TCGv_i64 fp64 = tcg_temp_new_i64(); 9991 9992 gen_load_fpr32(ctx, fp32, fs); 9993 if (ctx->nan2008) { 9994 gen_helper_float_cvt_2008_l_s(fp64, cpu_env, fp32); 9995 } else { 9996 gen_helper_float_cvt_l_s(fp64, cpu_env, fp32); 9997 } 9998 gen_store_fpr64(ctx, fp64, fd); 9999 } 10000 break; 10001 case OPC_CVT_PS_S: 10002 check_ps(ctx); 10003 { 10004 TCGv_i64 fp64 = tcg_temp_new_i64(); 10005 TCGv_i32 fp32_0 = tcg_temp_new_i32(); 10006 TCGv_i32 fp32_1 = tcg_temp_new_i32(); 10007 10008 gen_load_fpr32(ctx, fp32_0, fs); 10009 gen_load_fpr32(ctx, fp32_1, ft); 10010 tcg_gen_concat_i32_i64(fp64, fp32_1, fp32_0); 10011 gen_store_fpr64(ctx, fp64, fd); 10012 } 10013 break; 10014 case OPC_CMP_F_S: 10015 case OPC_CMP_UN_S: 10016 case OPC_CMP_EQ_S: 10017 case OPC_CMP_UEQ_S: 10018 case OPC_CMP_OLT_S: 10019 case OPC_CMP_ULT_S: 10020 case OPC_CMP_OLE_S: 10021 case OPC_CMP_ULE_S: 10022 case OPC_CMP_SF_S: 10023 case OPC_CMP_NGLE_S: 10024 case OPC_CMP_SEQ_S: 10025 case OPC_CMP_NGL_S: 10026 case OPC_CMP_LT_S: 10027 case OPC_CMP_NGE_S: 10028 case OPC_CMP_LE_S: 10029 case OPC_CMP_NGT_S: 10030 check_insn_opc_removed(ctx, ISA_MIPS_R6); 10031 if (ctx->opcode & (1 << 6)) { 10032 gen_cmpabs_s(ctx, func - 48, ft, fs, cc); 10033 } else { 10034 gen_cmp_s(ctx, func - 48, ft, fs, cc); 10035 } 10036 break; 10037 case OPC_ADD_D: 10038 check_cp1_registers(ctx, fs | ft | fd); 10039 { 10040 TCGv_i64 fp0 = tcg_temp_new_i64(); 10041 TCGv_i64 fp1 = tcg_temp_new_i64(); 10042 10043 gen_load_fpr64(ctx, fp0, fs); 10044 gen_load_fpr64(ctx, fp1, ft); 10045 gen_helper_float_add_d(fp0, cpu_env, fp0, fp1); 10046 gen_store_fpr64(ctx, fp0, fd); 10047 } 10048 break; 10049 case OPC_SUB_D: 10050 check_cp1_registers(ctx, fs | ft | fd); 10051 { 10052 TCGv_i64 fp0 = tcg_temp_new_i64(); 10053 TCGv_i64 fp1 = tcg_temp_new_i64(); 10054 10055 gen_load_fpr64(ctx, fp0, fs); 10056 gen_load_fpr64(ctx, fp1, ft); 10057 gen_helper_float_sub_d(fp0, cpu_env, fp0, fp1); 10058 gen_store_fpr64(ctx, fp0, fd); 10059 } 10060 break; 10061 case OPC_MUL_D: 10062 check_cp1_registers(ctx, fs | ft | fd); 10063 { 10064 TCGv_i64 fp0 = tcg_temp_new_i64(); 10065 TCGv_i64 fp1 = tcg_temp_new_i64(); 10066 10067 gen_load_fpr64(ctx, fp0, fs); 10068 gen_load_fpr64(ctx, fp1, ft); 10069 gen_helper_float_mul_d(fp0, cpu_env, fp0, fp1); 10070 gen_store_fpr64(ctx, fp0, fd); 10071 } 10072 break; 10073 case OPC_DIV_D: 10074 check_cp1_registers(ctx, fs | ft | fd); 10075 { 10076 TCGv_i64 fp0 = tcg_temp_new_i64(); 10077 TCGv_i64 fp1 = tcg_temp_new_i64(); 10078 10079 gen_load_fpr64(ctx, fp0, fs); 10080 gen_load_fpr64(ctx, fp1, ft); 10081 gen_helper_float_div_d(fp0, cpu_env, fp0, fp1); 10082 gen_store_fpr64(ctx, fp0, fd); 10083 } 10084 break; 10085 case OPC_SQRT_D: 10086 check_cp1_registers(ctx, fs | fd); 10087 { 10088 TCGv_i64 fp0 = tcg_temp_new_i64(); 10089 10090 gen_load_fpr64(ctx, fp0, fs); 10091 gen_helper_float_sqrt_d(fp0, cpu_env, fp0); 10092 gen_store_fpr64(ctx, fp0, fd); 10093 } 10094 break; 10095 case OPC_ABS_D: 10096 check_cp1_registers(ctx, fs | fd); 10097 { 10098 TCGv_i64 fp0 = tcg_temp_new_i64(); 10099 10100 gen_load_fpr64(ctx, fp0, fs); 10101 if (ctx->abs2008) { 10102 tcg_gen_andi_i64(fp0, fp0, 0x7fffffffffffffffULL); 10103 } else { 10104 gen_helper_float_abs_d(fp0, fp0); 10105 } 10106 gen_store_fpr64(ctx, fp0, fd); 10107 } 10108 break; 10109 case OPC_MOV_D: 10110 check_cp1_registers(ctx, fs | fd); 10111 { 10112 TCGv_i64 fp0 = tcg_temp_new_i64(); 10113 10114 gen_load_fpr64(ctx, fp0, fs); 10115 gen_store_fpr64(ctx, fp0, fd); 10116 } 10117 break; 10118 case OPC_NEG_D: 10119 check_cp1_registers(ctx, fs | fd); 10120 { 10121 TCGv_i64 fp0 = tcg_temp_new_i64(); 10122 10123 gen_load_fpr64(ctx, fp0, fs); 10124 if (ctx->abs2008) { 10125 tcg_gen_xori_i64(fp0, fp0, 1ULL << 63); 10126 } else { 10127 gen_helper_float_chs_d(fp0, fp0); 10128 } 10129 gen_store_fpr64(ctx, fp0, fd); 10130 } 10131 break; 10132 case OPC_ROUND_L_D: 10133 check_cp1_64bitmode(ctx); 10134 { 10135 TCGv_i64 fp0 = tcg_temp_new_i64(); 10136 10137 gen_load_fpr64(ctx, fp0, fs); 10138 if (ctx->nan2008) { 10139 gen_helper_float_round_2008_l_d(fp0, cpu_env, fp0); 10140 } else { 10141 gen_helper_float_round_l_d(fp0, cpu_env, fp0); 10142 } 10143 gen_store_fpr64(ctx, fp0, fd); 10144 } 10145 break; 10146 case OPC_TRUNC_L_D: 10147 check_cp1_64bitmode(ctx); 10148 { 10149 TCGv_i64 fp0 = tcg_temp_new_i64(); 10150 10151 gen_load_fpr64(ctx, fp0, fs); 10152 if (ctx->nan2008) { 10153 gen_helper_float_trunc_2008_l_d(fp0, cpu_env, fp0); 10154 } else { 10155 gen_helper_float_trunc_l_d(fp0, cpu_env, fp0); 10156 } 10157 gen_store_fpr64(ctx, fp0, fd); 10158 } 10159 break; 10160 case OPC_CEIL_L_D: 10161 check_cp1_64bitmode(ctx); 10162 { 10163 TCGv_i64 fp0 = tcg_temp_new_i64(); 10164 10165 gen_load_fpr64(ctx, fp0, fs); 10166 if (ctx->nan2008) { 10167 gen_helper_float_ceil_2008_l_d(fp0, cpu_env, fp0); 10168 } else { 10169 gen_helper_float_ceil_l_d(fp0, cpu_env, fp0); 10170 } 10171 gen_store_fpr64(ctx, fp0, fd); 10172 } 10173 break; 10174 case OPC_FLOOR_L_D: 10175 check_cp1_64bitmode(ctx); 10176 { 10177 TCGv_i64 fp0 = tcg_temp_new_i64(); 10178 10179 gen_load_fpr64(ctx, fp0, fs); 10180 if (ctx->nan2008) { 10181 gen_helper_float_floor_2008_l_d(fp0, cpu_env, fp0); 10182 } else { 10183 gen_helper_float_floor_l_d(fp0, cpu_env, fp0); 10184 } 10185 gen_store_fpr64(ctx, fp0, fd); 10186 } 10187 break; 10188 case OPC_ROUND_W_D: 10189 check_cp1_registers(ctx, fs); 10190 { 10191 TCGv_i32 fp32 = tcg_temp_new_i32(); 10192 TCGv_i64 fp64 = tcg_temp_new_i64(); 10193 10194 gen_load_fpr64(ctx, fp64, fs); 10195 if (ctx->nan2008) { 10196 gen_helper_float_round_2008_w_d(fp32, cpu_env, fp64); 10197 } else { 10198 gen_helper_float_round_w_d(fp32, cpu_env, fp64); 10199 } 10200 gen_store_fpr32(ctx, fp32, fd); 10201 } 10202 break; 10203 case OPC_TRUNC_W_D: 10204 check_cp1_registers(ctx, fs); 10205 { 10206 TCGv_i32 fp32 = tcg_temp_new_i32(); 10207 TCGv_i64 fp64 = tcg_temp_new_i64(); 10208 10209 gen_load_fpr64(ctx, fp64, fs); 10210 if (ctx->nan2008) { 10211 gen_helper_float_trunc_2008_w_d(fp32, cpu_env, fp64); 10212 } else { 10213 gen_helper_float_trunc_w_d(fp32, cpu_env, fp64); 10214 } 10215 gen_store_fpr32(ctx, fp32, fd); 10216 } 10217 break; 10218 case OPC_CEIL_W_D: 10219 check_cp1_registers(ctx, fs); 10220 { 10221 TCGv_i32 fp32 = tcg_temp_new_i32(); 10222 TCGv_i64 fp64 = tcg_temp_new_i64(); 10223 10224 gen_load_fpr64(ctx, fp64, fs); 10225 if (ctx->nan2008) { 10226 gen_helper_float_ceil_2008_w_d(fp32, cpu_env, fp64); 10227 } else { 10228 gen_helper_float_ceil_w_d(fp32, cpu_env, fp64); 10229 } 10230 gen_store_fpr32(ctx, fp32, fd); 10231 } 10232 break; 10233 case OPC_FLOOR_W_D: 10234 check_cp1_registers(ctx, fs); 10235 { 10236 TCGv_i32 fp32 = tcg_temp_new_i32(); 10237 TCGv_i64 fp64 = tcg_temp_new_i64(); 10238 10239 gen_load_fpr64(ctx, fp64, fs); 10240 if (ctx->nan2008) { 10241 gen_helper_float_floor_2008_w_d(fp32, cpu_env, fp64); 10242 } else { 10243 gen_helper_float_floor_w_d(fp32, cpu_env, fp64); 10244 } 10245 gen_store_fpr32(ctx, fp32, fd); 10246 } 10247 break; 10248 case OPC_SEL_D: 10249 check_insn(ctx, ISA_MIPS_R6); 10250 gen_sel_d(ctx, op1, fd, ft, fs); 10251 break; 10252 case OPC_SELEQZ_D: 10253 check_insn(ctx, ISA_MIPS_R6); 10254 gen_sel_d(ctx, op1, fd, ft, fs); 10255 break; 10256 case OPC_SELNEZ_D: 10257 check_insn(ctx, ISA_MIPS_R6); 10258 gen_sel_d(ctx, op1, fd, ft, fs); 10259 break; 10260 case OPC_MOVCF_D: 10261 check_insn_opc_removed(ctx, ISA_MIPS_R6); 10262 gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); 10263 break; 10264 case OPC_MOVZ_D: 10265 check_insn_opc_removed(ctx, ISA_MIPS_R6); 10266 { 10267 TCGLabel *l1 = gen_new_label(); 10268 TCGv_i64 fp0; 10269 10270 if (ft != 0) { 10271 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); 10272 } 10273 fp0 = tcg_temp_new_i64(); 10274 gen_load_fpr64(ctx, fp0, fs); 10275 gen_store_fpr64(ctx, fp0, fd); 10276 gen_set_label(l1); 10277 } 10278 break; 10279 case OPC_MOVN_D: 10280 check_insn_opc_removed(ctx, ISA_MIPS_R6); 10281 { 10282 TCGLabel *l1 = gen_new_label(); 10283 TCGv_i64 fp0; 10284 10285 if (ft != 0) { 10286 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); 10287 fp0 = tcg_temp_new_i64(); 10288 gen_load_fpr64(ctx, fp0, fs); 10289 gen_store_fpr64(ctx, fp0, fd); 10290 gen_set_label(l1); 10291 } 10292 } 10293 break; 10294 case OPC_RECIP_D: 10295 check_cp1_registers(ctx, fs | fd); 10296 { 10297 TCGv_i64 fp0 = tcg_temp_new_i64(); 10298 10299 gen_load_fpr64(ctx, fp0, fs); 10300 gen_helper_float_recip_d(fp0, cpu_env, fp0); 10301 gen_store_fpr64(ctx, fp0, fd); 10302 } 10303 break; 10304 case OPC_RSQRT_D: 10305 check_cp1_registers(ctx, fs | fd); 10306 { 10307 TCGv_i64 fp0 = tcg_temp_new_i64(); 10308 10309 gen_load_fpr64(ctx, fp0, fs); 10310 gen_helper_float_rsqrt_d(fp0, cpu_env, fp0); 10311 gen_store_fpr64(ctx, fp0, fd); 10312 } 10313 break; 10314 case OPC_MADDF_D: 10315 check_insn(ctx, ISA_MIPS_R6); 10316 { 10317 TCGv_i64 fp0 = tcg_temp_new_i64(); 10318 TCGv_i64 fp1 = tcg_temp_new_i64(); 10319 TCGv_i64 fp2 = tcg_temp_new_i64(); 10320 gen_load_fpr64(ctx, fp0, fs); 10321 gen_load_fpr64(ctx, fp1, ft); 10322 gen_load_fpr64(ctx, fp2, fd); 10323 gen_helper_float_maddf_d(fp2, cpu_env, fp0, fp1, fp2); 10324 gen_store_fpr64(ctx, fp2, fd); 10325 } 10326 break; 10327 case OPC_MSUBF_D: 10328 check_insn(ctx, ISA_MIPS_R6); 10329 { 10330 TCGv_i64 fp0 = tcg_temp_new_i64(); 10331 TCGv_i64 fp1 = tcg_temp_new_i64(); 10332 TCGv_i64 fp2 = tcg_temp_new_i64(); 10333 gen_load_fpr64(ctx, fp0, fs); 10334 gen_load_fpr64(ctx, fp1, ft); 10335 gen_load_fpr64(ctx, fp2, fd); 10336 gen_helper_float_msubf_d(fp2, cpu_env, fp0, fp1, fp2); 10337 gen_store_fpr64(ctx, fp2, fd); 10338 } 10339 break; 10340 case OPC_RINT_D: 10341 check_insn(ctx, ISA_MIPS_R6); 10342 { 10343 TCGv_i64 fp0 = tcg_temp_new_i64(); 10344 gen_load_fpr64(ctx, fp0, fs); 10345 gen_helper_float_rint_d(fp0, cpu_env, fp0); 10346 gen_store_fpr64(ctx, fp0, fd); 10347 } 10348 break; 10349 case OPC_CLASS_D: 10350 check_insn(ctx, ISA_MIPS_R6); 10351 { 10352 TCGv_i64 fp0 = tcg_temp_new_i64(); 10353 gen_load_fpr64(ctx, fp0, fs); 10354 gen_helper_float_class_d(fp0, cpu_env, fp0); 10355 gen_store_fpr64(ctx, fp0, fd); 10356 } 10357 break; 10358 case OPC_MIN_D: /* OPC_RECIP2_D */ 10359 if (ctx->insn_flags & ISA_MIPS_R6) { 10360 /* OPC_MIN_D */ 10361 TCGv_i64 fp0 = tcg_temp_new_i64(); 10362 TCGv_i64 fp1 = tcg_temp_new_i64(); 10363 gen_load_fpr64(ctx, fp0, fs); 10364 gen_load_fpr64(ctx, fp1, ft); 10365 gen_helper_float_min_d(fp1, cpu_env, fp0, fp1); 10366 gen_store_fpr64(ctx, fp1, fd); 10367 } else { 10368 /* OPC_RECIP2_D */ 10369 check_cp1_64bitmode(ctx); 10370 { 10371 TCGv_i64 fp0 = tcg_temp_new_i64(); 10372 TCGv_i64 fp1 = tcg_temp_new_i64(); 10373 10374 gen_load_fpr64(ctx, fp0, fs); 10375 gen_load_fpr64(ctx, fp1, ft); 10376 gen_helper_float_recip2_d(fp0, cpu_env, fp0, fp1); 10377 gen_store_fpr64(ctx, fp0, fd); 10378 } 10379 } 10380 break; 10381 case OPC_MINA_D: /* OPC_RECIP1_D */ 10382 if (ctx->insn_flags & ISA_MIPS_R6) { 10383 /* OPC_MINA_D */ 10384 TCGv_i64 fp0 = tcg_temp_new_i64(); 10385 TCGv_i64 fp1 = tcg_temp_new_i64(); 10386 gen_load_fpr64(ctx, fp0, fs); 10387 gen_load_fpr64(ctx, fp1, ft); 10388 gen_helper_float_mina_d(fp1, cpu_env, fp0, fp1); 10389 gen_store_fpr64(ctx, fp1, fd); 10390 } else { 10391 /* OPC_RECIP1_D */ 10392 check_cp1_64bitmode(ctx); 10393 { 10394 TCGv_i64 fp0 = tcg_temp_new_i64(); 10395 10396 gen_load_fpr64(ctx, fp0, fs); 10397 gen_helper_float_recip1_d(fp0, cpu_env, fp0); 10398 gen_store_fpr64(ctx, fp0, fd); 10399 } 10400 } 10401 break; 10402 case OPC_MAX_D: /* OPC_RSQRT1_D */ 10403 if (ctx->insn_flags & ISA_MIPS_R6) { 10404 /* OPC_MAX_D */ 10405 TCGv_i64 fp0 = tcg_temp_new_i64(); 10406 TCGv_i64 fp1 = tcg_temp_new_i64(); 10407 gen_load_fpr64(ctx, fp0, fs); 10408 gen_load_fpr64(ctx, fp1, ft); 10409 gen_helper_float_max_d(fp1, cpu_env, fp0, fp1); 10410 gen_store_fpr64(ctx, fp1, fd); 10411 } else { 10412 /* OPC_RSQRT1_D */ 10413 check_cp1_64bitmode(ctx); 10414 { 10415 TCGv_i64 fp0 = tcg_temp_new_i64(); 10416 10417 gen_load_fpr64(ctx, fp0, fs); 10418 gen_helper_float_rsqrt1_d(fp0, cpu_env, fp0); 10419 gen_store_fpr64(ctx, fp0, fd); 10420 } 10421 } 10422 break; 10423 case OPC_MAXA_D: /* OPC_RSQRT2_D */ 10424 if (ctx->insn_flags & ISA_MIPS_R6) { 10425 /* OPC_MAXA_D */ 10426 TCGv_i64 fp0 = tcg_temp_new_i64(); 10427 TCGv_i64 fp1 = tcg_temp_new_i64(); 10428 gen_load_fpr64(ctx, fp0, fs); 10429 gen_load_fpr64(ctx, fp1, ft); 10430 gen_helper_float_maxa_d(fp1, cpu_env, fp0, fp1); 10431 gen_store_fpr64(ctx, fp1, fd); 10432 } else { 10433 /* OPC_RSQRT2_D */ 10434 check_cp1_64bitmode(ctx); 10435 { 10436 TCGv_i64 fp0 = tcg_temp_new_i64(); 10437 TCGv_i64 fp1 = tcg_temp_new_i64(); 10438 10439 gen_load_fpr64(ctx, fp0, fs); 10440 gen_load_fpr64(ctx, fp1, ft); 10441 gen_helper_float_rsqrt2_d(fp0, cpu_env, fp0, fp1); 10442 gen_store_fpr64(ctx, fp0, fd); 10443 } 10444 } 10445 break; 10446 case OPC_CMP_F_D: 10447 case OPC_CMP_UN_D: 10448 case OPC_CMP_EQ_D: 10449 case OPC_CMP_UEQ_D: 10450 case OPC_CMP_OLT_D: 10451 case OPC_CMP_ULT_D: 10452 case OPC_CMP_OLE_D: 10453 case OPC_CMP_ULE_D: 10454 case OPC_CMP_SF_D: 10455 case OPC_CMP_NGLE_D: 10456 case OPC_CMP_SEQ_D: 10457 case OPC_CMP_NGL_D: 10458 case OPC_CMP_LT_D: 10459 case OPC_CMP_NGE_D: 10460 case OPC_CMP_LE_D: 10461 case OPC_CMP_NGT_D: 10462 check_insn_opc_removed(ctx, ISA_MIPS_R6); 10463 if (ctx->opcode & (1 << 6)) { 10464 gen_cmpabs_d(ctx, func - 48, ft, fs, cc); 10465 } else { 10466 gen_cmp_d(ctx, func - 48, ft, fs, cc); 10467 } 10468 break; 10469 case OPC_CVT_S_D: 10470 check_cp1_registers(ctx, fs); 10471 { 10472 TCGv_i32 fp32 = tcg_temp_new_i32(); 10473 TCGv_i64 fp64 = tcg_temp_new_i64(); 10474 10475 gen_load_fpr64(ctx, fp64, fs); 10476 gen_helper_float_cvts_d(fp32, cpu_env, fp64); 10477 gen_store_fpr32(ctx, fp32, fd); 10478 } 10479 break; 10480 case OPC_CVT_W_D: 10481 check_cp1_registers(ctx, fs); 10482 { 10483 TCGv_i32 fp32 = tcg_temp_new_i32(); 10484 TCGv_i64 fp64 = tcg_temp_new_i64(); 10485 10486 gen_load_fpr64(ctx, fp64, fs); 10487 if (ctx->nan2008) { 10488 gen_helper_float_cvt_2008_w_d(fp32, cpu_env, fp64); 10489 } else { 10490 gen_helper_float_cvt_w_d(fp32, cpu_env, fp64); 10491 } 10492 gen_store_fpr32(ctx, fp32, fd); 10493 } 10494 break; 10495 case OPC_CVT_L_D: 10496 check_cp1_64bitmode(ctx); 10497 { 10498 TCGv_i64 fp0 = tcg_temp_new_i64(); 10499 10500 gen_load_fpr64(ctx, fp0, fs); 10501 if (ctx->nan2008) { 10502 gen_helper_float_cvt_2008_l_d(fp0, cpu_env, fp0); 10503 } else { 10504 gen_helper_float_cvt_l_d(fp0, cpu_env, fp0); 10505 } 10506 gen_store_fpr64(ctx, fp0, fd); 10507 } 10508 break; 10509 case OPC_CVT_S_W: 10510 { 10511 TCGv_i32 fp0 = tcg_temp_new_i32(); 10512 10513 gen_load_fpr32(ctx, fp0, fs); 10514 gen_helper_float_cvts_w(fp0, cpu_env, fp0); 10515 gen_store_fpr32(ctx, fp0, fd); 10516 } 10517 break; 10518 case OPC_CVT_D_W: 10519 check_cp1_registers(ctx, fd); 10520 { 10521 TCGv_i32 fp32 = tcg_temp_new_i32(); 10522 TCGv_i64 fp64 = tcg_temp_new_i64(); 10523 10524 gen_load_fpr32(ctx, fp32, fs); 10525 gen_helper_float_cvtd_w(fp64, cpu_env, fp32); 10526 gen_store_fpr64(ctx, fp64, fd); 10527 } 10528 break; 10529 case OPC_CVT_S_L: 10530 check_cp1_64bitmode(ctx); 10531 { 10532 TCGv_i32 fp32 = tcg_temp_new_i32(); 10533 TCGv_i64 fp64 = tcg_temp_new_i64(); 10534 10535 gen_load_fpr64(ctx, fp64, fs); 10536 gen_helper_float_cvts_l(fp32, cpu_env, fp64); 10537 gen_store_fpr32(ctx, fp32, fd); 10538 } 10539 break; 10540 case OPC_CVT_D_L: 10541 check_cp1_64bitmode(ctx); 10542 { 10543 TCGv_i64 fp0 = tcg_temp_new_i64(); 10544 10545 gen_load_fpr64(ctx, fp0, fs); 10546 gen_helper_float_cvtd_l(fp0, cpu_env, fp0); 10547 gen_store_fpr64(ctx, fp0, fd); 10548 } 10549 break; 10550 case OPC_CVT_PS_PW: 10551 check_ps(ctx); 10552 { 10553 TCGv_i64 fp0 = tcg_temp_new_i64(); 10554 10555 gen_load_fpr64(ctx, fp0, fs); 10556 gen_helper_float_cvtps_pw(fp0, cpu_env, fp0); 10557 gen_store_fpr64(ctx, fp0, fd); 10558 } 10559 break; 10560 case OPC_ADD_PS: 10561 check_ps(ctx); 10562 { 10563 TCGv_i64 fp0 = tcg_temp_new_i64(); 10564 TCGv_i64 fp1 = tcg_temp_new_i64(); 10565 10566 gen_load_fpr64(ctx, fp0, fs); 10567 gen_load_fpr64(ctx, fp1, ft); 10568 gen_helper_float_add_ps(fp0, cpu_env, fp0, fp1); 10569 gen_store_fpr64(ctx, fp0, fd); 10570 } 10571 break; 10572 case OPC_SUB_PS: 10573 check_ps(ctx); 10574 { 10575 TCGv_i64 fp0 = tcg_temp_new_i64(); 10576 TCGv_i64 fp1 = tcg_temp_new_i64(); 10577 10578 gen_load_fpr64(ctx, fp0, fs); 10579 gen_load_fpr64(ctx, fp1, ft); 10580 gen_helper_float_sub_ps(fp0, cpu_env, fp0, fp1); 10581 gen_store_fpr64(ctx, fp0, fd); 10582 } 10583 break; 10584 case OPC_MUL_PS: 10585 check_ps(ctx); 10586 { 10587 TCGv_i64 fp0 = tcg_temp_new_i64(); 10588 TCGv_i64 fp1 = tcg_temp_new_i64(); 10589 10590 gen_load_fpr64(ctx, fp0, fs); 10591 gen_load_fpr64(ctx, fp1, ft); 10592 gen_helper_float_mul_ps(fp0, cpu_env, fp0, fp1); 10593 gen_store_fpr64(ctx, fp0, fd); 10594 } 10595 break; 10596 case OPC_ABS_PS: 10597 check_ps(ctx); 10598 { 10599 TCGv_i64 fp0 = tcg_temp_new_i64(); 10600 10601 gen_load_fpr64(ctx, fp0, fs); 10602 gen_helper_float_abs_ps(fp0, fp0); 10603 gen_store_fpr64(ctx, fp0, fd); 10604 } 10605 break; 10606 case OPC_MOV_PS: 10607 check_ps(ctx); 10608 { 10609 TCGv_i64 fp0 = tcg_temp_new_i64(); 10610 10611 gen_load_fpr64(ctx, fp0, fs); 10612 gen_store_fpr64(ctx, fp0, fd); 10613 } 10614 break; 10615 case OPC_NEG_PS: 10616 check_ps(ctx); 10617 { 10618 TCGv_i64 fp0 = tcg_temp_new_i64(); 10619 10620 gen_load_fpr64(ctx, fp0, fs); 10621 gen_helper_float_chs_ps(fp0, fp0); 10622 gen_store_fpr64(ctx, fp0, fd); 10623 } 10624 break; 10625 case OPC_MOVCF_PS: 10626 check_ps(ctx); 10627 gen_movcf_ps(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); 10628 break; 10629 case OPC_MOVZ_PS: 10630 check_ps(ctx); 10631 { 10632 TCGLabel *l1 = gen_new_label(); 10633 TCGv_i64 fp0; 10634 10635 if (ft != 0) { 10636 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); 10637 } 10638 fp0 = tcg_temp_new_i64(); 10639 gen_load_fpr64(ctx, fp0, fs); 10640 gen_store_fpr64(ctx, fp0, fd); 10641 gen_set_label(l1); 10642 } 10643 break; 10644 case OPC_MOVN_PS: 10645 check_ps(ctx); 10646 { 10647 TCGLabel *l1 = gen_new_label(); 10648 TCGv_i64 fp0; 10649 10650 if (ft != 0) { 10651 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); 10652 fp0 = tcg_temp_new_i64(); 10653 gen_load_fpr64(ctx, fp0, fs); 10654 gen_store_fpr64(ctx, fp0, fd); 10655 gen_set_label(l1); 10656 } 10657 } 10658 break; 10659 case OPC_ADDR_PS: 10660 check_ps(ctx); 10661 { 10662 TCGv_i64 fp0 = tcg_temp_new_i64(); 10663 TCGv_i64 fp1 = tcg_temp_new_i64(); 10664 10665 gen_load_fpr64(ctx, fp0, ft); 10666 gen_load_fpr64(ctx, fp1, fs); 10667 gen_helper_float_addr_ps(fp0, cpu_env, fp0, fp1); 10668 gen_store_fpr64(ctx, fp0, fd); 10669 } 10670 break; 10671 case OPC_MULR_PS: 10672 check_ps(ctx); 10673 { 10674 TCGv_i64 fp0 = tcg_temp_new_i64(); 10675 TCGv_i64 fp1 = tcg_temp_new_i64(); 10676 10677 gen_load_fpr64(ctx, fp0, ft); 10678 gen_load_fpr64(ctx, fp1, fs); 10679 gen_helper_float_mulr_ps(fp0, cpu_env, fp0, fp1); 10680 gen_store_fpr64(ctx, fp0, fd); 10681 } 10682 break; 10683 case OPC_RECIP2_PS: 10684 check_ps(ctx); 10685 { 10686 TCGv_i64 fp0 = tcg_temp_new_i64(); 10687 TCGv_i64 fp1 = tcg_temp_new_i64(); 10688 10689 gen_load_fpr64(ctx, fp0, fs); 10690 gen_load_fpr64(ctx, fp1, ft); 10691 gen_helper_float_recip2_ps(fp0, cpu_env, fp0, fp1); 10692 gen_store_fpr64(ctx, fp0, fd); 10693 } 10694 break; 10695 case OPC_RECIP1_PS: 10696 check_ps(ctx); 10697 { 10698 TCGv_i64 fp0 = tcg_temp_new_i64(); 10699 10700 gen_load_fpr64(ctx, fp0, fs); 10701 gen_helper_float_recip1_ps(fp0, cpu_env, fp0); 10702 gen_store_fpr64(ctx, fp0, fd); 10703 } 10704 break; 10705 case OPC_RSQRT1_PS: 10706 check_ps(ctx); 10707 { 10708 TCGv_i64 fp0 = tcg_temp_new_i64(); 10709 10710 gen_load_fpr64(ctx, fp0, fs); 10711 gen_helper_float_rsqrt1_ps(fp0, cpu_env, fp0); 10712 gen_store_fpr64(ctx, fp0, fd); 10713 } 10714 break; 10715 case OPC_RSQRT2_PS: 10716 check_ps(ctx); 10717 { 10718 TCGv_i64 fp0 = tcg_temp_new_i64(); 10719 TCGv_i64 fp1 = tcg_temp_new_i64(); 10720 10721 gen_load_fpr64(ctx, fp0, fs); 10722 gen_load_fpr64(ctx, fp1, ft); 10723 gen_helper_float_rsqrt2_ps(fp0, cpu_env, fp0, fp1); 10724 gen_store_fpr64(ctx, fp0, fd); 10725 } 10726 break; 10727 case OPC_CVT_S_PU: 10728 check_cp1_64bitmode(ctx); 10729 { 10730 TCGv_i32 fp0 = tcg_temp_new_i32(); 10731 10732 gen_load_fpr32h(ctx, fp0, fs); 10733 gen_helper_float_cvts_pu(fp0, cpu_env, fp0); 10734 gen_store_fpr32(ctx, fp0, fd); 10735 } 10736 break; 10737 case OPC_CVT_PW_PS: 10738 check_ps(ctx); 10739 { 10740 TCGv_i64 fp0 = tcg_temp_new_i64(); 10741 10742 gen_load_fpr64(ctx, fp0, fs); 10743 gen_helper_float_cvtpw_ps(fp0, cpu_env, fp0); 10744 gen_store_fpr64(ctx, fp0, fd); 10745 } 10746 break; 10747 case OPC_CVT_S_PL: 10748 check_cp1_64bitmode(ctx); 10749 { 10750 TCGv_i32 fp0 = tcg_temp_new_i32(); 10751 10752 gen_load_fpr32(ctx, fp0, fs); 10753 gen_helper_float_cvts_pl(fp0, cpu_env, fp0); 10754 gen_store_fpr32(ctx, fp0, fd); 10755 } 10756 break; 10757 case OPC_PLL_PS: 10758 check_ps(ctx); 10759 { 10760 TCGv_i32 fp0 = tcg_temp_new_i32(); 10761 TCGv_i32 fp1 = tcg_temp_new_i32(); 10762 10763 gen_load_fpr32(ctx, fp0, fs); 10764 gen_load_fpr32(ctx, fp1, ft); 10765 gen_store_fpr32h(ctx, fp0, fd); 10766 gen_store_fpr32(ctx, fp1, fd); 10767 } 10768 break; 10769 case OPC_PLU_PS: 10770 check_ps(ctx); 10771 { 10772 TCGv_i32 fp0 = tcg_temp_new_i32(); 10773 TCGv_i32 fp1 = tcg_temp_new_i32(); 10774 10775 gen_load_fpr32(ctx, fp0, fs); 10776 gen_load_fpr32h(ctx, fp1, ft); 10777 gen_store_fpr32(ctx, fp1, fd); 10778 gen_store_fpr32h(ctx, fp0, fd); 10779 } 10780 break; 10781 case OPC_PUL_PS: 10782 check_ps(ctx); 10783 { 10784 TCGv_i32 fp0 = tcg_temp_new_i32(); 10785 TCGv_i32 fp1 = tcg_temp_new_i32(); 10786 10787 gen_load_fpr32h(ctx, fp0, fs); 10788 gen_load_fpr32(ctx, fp1, ft); 10789 gen_store_fpr32(ctx, fp1, fd); 10790 gen_store_fpr32h(ctx, fp0, fd); 10791 } 10792 break; 10793 case OPC_PUU_PS: 10794 check_ps(ctx); 10795 { 10796 TCGv_i32 fp0 = tcg_temp_new_i32(); 10797 TCGv_i32 fp1 = tcg_temp_new_i32(); 10798 10799 gen_load_fpr32h(ctx, fp0, fs); 10800 gen_load_fpr32h(ctx, fp1, ft); 10801 gen_store_fpr32(ctx, fp1, fd); 10802 gen_store_fpr32h(ctx, fp0, fd); 10803 } 10804 break; 10805 case OPC_CMP_F_PS: 10806 case OPC_CMP_UN_PS: 10807 case OPC_CMP_EQ_PS: 10808 case OPC_CMP_UEQ_PS: 10809 case OPC_CMP_OLT_PS: 10810 case OPC_CMP_ULT_PS: 10811 case OPC_CMP_OLE_PS: 10812 case OPC_CMP_ULE_PS: 10813 case OPC_CMP_SF_PS: 10814 case OPC_CMP_NGLE_PS: 10815 case OPC_CMP_SEQ_PS: 10816 case OPC_CMP_NGL_PS: 10817 case OPC_CMP_LT_PS: 10818 case OPC_CMP_NGE_PS: 10819 case OPC_CMP_LE_PS: 10820 case OPC_CMP_NGT_PS: 10821 if (ctx->opcode & (1 << 6)) { 10822 gen_cmpabs_ps(ctx, func - 48, ft, fs, cc); 10823 } else { 10824 gen_cmp_ps(ctx, func - 48, ft, fs, cc); 10825 } 10826 break; 10827 default: 10828 MIPS_INVAL("farith"); 10829 gen_reserved_instruction(ctx); 10830 return; 10831 } 10832 } 10833 10834 /* Coprocessor 3 (FPU) */ 10835 static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, 10836 int fd, int fs, int base, int index) 10837 { 10838 TCGv t0 = tcg_temp_new(); 10839 10840 if (base == 0) { 10841 gen_load_gpr(t0, index); 10842 } else if (index == 0) { 10843 gen_load_gpr(t0, base); 10844 } else { 10845 gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]); 10846 } 10847 /* 10848 * Don't do NOP if destination is zero: we must perform the actual 10849 * memory access. 10850 */ 10851 switch (opc) { 10852 case OPC_LWXC1: 10853 check_cop1x(ctx); 10854 { 10855 TCGv_i32 fp0 = tcg_temp_new_i32(); 10856 10857 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL); 10858 tcg_gen_trunc_tl_i32(fp0, t0); 10859 gen_store_fpr32(ctx, fp0, fd); 10860 } 10861 break; 10862 case OPC_LDXC1: 10863 check_cop1x(ctx); 10864 check_cp1_registers(ctx, fd); 10865 { 10866 TCGv_i64 fp0 = tcg_temp_new_i64(); 10867 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); 10868 gen_store_fpr64(ctx, fp0, fd); 10869 } 10870 break; 10871 case OPC_LUXC1: 10872 check_cp1_64bitmode(ctx); 10873 tcg_gen_andi_tl(t0, t0, ~0x7); 10874 { 10875 TCGv_i64 fp0 = tcg_temp_new_i64(); 10876 10877 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); 10878 gen_store_fpr64(ctx, fp0, fd); 10879 } 10880 break; 10881 case OPC_SWXC1: 10882 check_cop1x(ctx); 10883 { 10884 TCGv_i32 fp0 = tcg_temp_new_i32(); 10885 gen_load_fpr32(ctx, fp0, fs); 10886 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL); 10887 } 10888 break; 10889 case OPC_SDXC1: 10890 check_cop1x(ctx); 10891 check_cp1_registers(ctx, fs); 10892 { 10893 TCGv_i64 fp0 = tcg_temp_new_i64(); 10894 gen_load_fpr64(ctx, fp0, fs); 10895 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); 10896 } 10897 break; 10898 case OPC_SUXC1: 10899 check_cp1_64bitmode(ctx); 10900 tcg_gen_andi_tl(t0, t0, ~0x7); 10901 { 10902 TCGv_i64 fp0 = tcg_temp_new_i64(); 10903 gen_load_fpr64(ctx, fp0, fs); 10904 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); 10905 } 10906 break; 10907 } 10908 } 10909 10910 static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, 10911 int fd, int fr, int fs, int ft) 10912 { 10913 switch (opc) { 10914 case OPC_ALNV_PS: 10915 check_ps(ctx); 10916 { 10917 TCGv t0 = tcg_temp_new(); 10918 TCGv_i32 fp = tcg_temp_new_i32(); 10919 TCGv_i32 fph = tcg_temp_new_i32(); 10920 TCGLabel *l1 = gen_new_label(); 10921 TCGLabel *l2 = gen_new_label(); 10922 10923 gen_load_gpr(t0, fr); 10924 tcg_gen_andi_tl(t0, t0, 0x7); 10925 10926 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1); 10927 gen_load_fpr32(ctx, fp, fs); 10928 gen_load_fpr32h(ctx, fph, fs); 10929 gen_store_fpr32(ctx, fp, fd); 10930 gen_store_fpr32h(ctx, fph, fd); 10931 tcg_gen_br(l2); 10932 gen_set_label(l1); 10933 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2); 10934 if (cpu_is_bigendian(ctx)) { 10935 gen_load_fpr32(ctx, fp, fs); 10936 gen_load_fpr32h(ctx, fph, ft); 10937 gen_store_fpr32h(ctx, fp, fd); 10938 gen_store_fpr32(ctx, fph, fd); 10939 } else { 10940 gen_load_fpr32h(ctx, fph, fs); 10941 gen_load_fpr32(ctx, fp, ft); 10942 gen_store_fpr32(ctx, fph, fd); 10943 gen_store_fpr32h(ctx, fp, fd); 10944 } 10945 gen_set_label(l2); 10946 } 10947 break; 10948 case OPC_MADD_S: 10949 check_cop1x(ctx); 10950 { 10951 TCGv_i32 fp0 = tcg_temp_new_i32(); 10952 TCGv_i32 fp1 = tcg_temp_new_i32(); 10953 TCGv_i32 fp2 = tcg_temp_new_i32(); 10954 10955 gen_load_fpr32(ctx, fp0, fs); 10956 gen_load_fpr32(ctx, fp1, ft); 10957 gen_load_fpr32(ctx, fp2, fr); 10958 gen_helper_float_madd_s(fp2, cpu_env, fp0, fp1, fp2); 10959 gen_store_fpr32(ctx, fp2, fd); 10960 } 10961 break; 10962 case OPC_MADD_D: 10963 check_cop1x(ctx); 10964 check_cp1_registers(ctx, fd | fs | ft | fr); 10965 { 10966 TCGv_i64 fp0 = tcg_temp_new_i64(); 10967 TCGv_i64 fp1 = tcg_temp_new_i64(); 10968 TCGv_i64 fp2 = tcg_temp_new_i64(); 10969 10970 gen_load_fpr64(ctx, fp0, fs); 10971 gen_load_fpr64(ctx, fp1, ft); 10972 gen_load_fpr64(ctx, fp2, fr); 10973 gen_helper_float_madd_d(fp2, cpu_env, fp0, fp1, fp2); 10974 gen_store_fpr64(ctx, fp2, fd); 10975 } 10976 break; 10977 case OPC_MADD_PS: 10978 check_ps(ctx); 10979 { 10980 TCGv_i64 fp0 = tcg_temp_new_i64(); 10981 TCGv_i64 fp1 = tcg_temp_new_i64(); 10982 TCGv_i64 fp2 = tcg_temp_new_i64(); 10983 10984 gen_load_fpr64(ctx, fp0, fs); 10985 gen_load_fpr64(ctx, fp1, ft); 10986 gen_load_fpr64(ctx, fp2, fr); 10987 gen_helper_float_madd_ps(fp2, cpu_env, fp0, fp1, fp2); 10988 gen_store_fpr64(ctx, fp2, fd); 10989 } 10990 break; 10991 case OPC_MSUB_S: 10992 check_cop1x(ctx); 10993 { 10994 TCGv_i32 fp0 = tcg_temp_new_i32(); 10995 TCGv_i32 fp1 = tcg_temp_new_i32(); 10996 TCGv_i32 fp2 = tcg_temp_new_i32(); 10997 10998 gen_load_fpr32(ctx, fp0, fs); 10999 gen_load_fpr32(ctx, fp1, ft); 11000 gen_load_fpr32(ctx, fp2, fr); 11001 gen_helper_float_msub_s(fp2, cpu_env, fp0, fp1, fp2); 11002 gen_store_fpr32(ctx, fp2, fd); 11003 } 11004 break; 11005 case OPC_MSUB_D: 11006 check_cop1x(ctx); 11007 check_cp1_registers(ctx, fd | fs | ft | fr); 11008 { 11009 TCGv_i64 fp0 = tcg_temp_new_i64(); 11010 TCGv_i64 fp1 = tcg_temp_new_i64(); 11011 TCGv_i64 fp2 = tcg_temp_new_i64(); 11012 11013 gen_load_fpr64(ctx, fp0, fs); 11014 gen_load_fpr64(ctx, fp1, ft); 11015 gen_load_fpr64(ctx, fp2, fr); 11016 gen_helper_float_msub_d(fp2, cpu_env, fp0, fp1, fp2); 11017 gen_store_fpr64(ctx, fp2, fd); 11018 } 11019 break; 11020 case OPC_MSUB_PS: 11021 check_ps(ctx); 11022 { 11023 TCGv_i64 fp0 = tcg_temp_new_i64(); 11024 TCGv_i64 fp1 = tcg_temp_new_i64(); 11025 TCGv_i64 fp2 = tcg_temp_new_i64(); 11026 11027 gen_load_fpr64(ctx, fp0, fs); 11028 gen_load_fpr64(ctx, fp1, ft); 11029 gen_load_fpr64(ctx, fp2, fr); 11030 gen_helper_float_msub_ps(fp2, cpu_env, fp0, fp1, fp2); 11031 gen_store_fpr64(ctx, fp2, fd); 11032 } 11033 break; 11034 case OPC_NMADD_S: 11035 check_cop1x(ctx); 11036 { 11037 TCGv_i32 fp0 = tcg_temp_new_i32(); 11038 TCGv_i32 fp1 = tcg_temp_new_i32(); 11039 TCGv_i32 fp2 = tcg_temp_new_i32(); 11040 11041 gen_load_fpr32(ctx, fp0, fs); 11042 gen_load_fpr32(ctx, fp1, ft); 11043 gen_load_fpr32(ctx, fp2, fr); 11044 gen_helper_float_nmadd_s(fp2, cpu_env, fp0, fp1, fp2); 11045 gen_store_fpr32(ctx, fp2, fd); 11046 } 11047 break; 11048 case OPC_NMADD_D: 11049 check_cop1x(ctx); 11050 check_cp1_registers(ctx, fd | fs | ft | fr); 11051 { 11052 TCGv_i64 fp0 = tcg_temp_new_i64(); 11053 TCGv_i64 fp1 = tcg_temp_new_i64(); 11054 TCGv_i64 fp2 = tcg_temp_new_i64(); 11055 11056 gen_load_fpr64(ctx, fp0, fs); 11057 gen_load_fpr64(ctx, fp1, ft); 11058 gen_load_fpr64(ctx, fp2, fr); 11059 gen_helper_float_nmadd_d(fp2, cpu_env, fp0, fp1, fp2); 11060 gen_store_fpr64(ctx, fp2, fd); 11061 } 11062 break; 11063 case OPC_NMADD_PS: 11064 check_ps(ctx); 11065 { 11066 TCGv_i64 fp0 = tcg_temp_new_i64(); 11067 TCGv_i64 fp1 = tcg_temp_new_i64(); 11068 TCGv_i64 fp2 = tcg_temp_new_i64(); 11069 11070 gen_load_fpr64(ctx, fp0, fs); 11071 gen_load_fpr64(ctx, fp1, ft); 11072 gen_load_fpr64(ctx, fp2, fr); 11073 gen_helper_float_nmadd_ps(fp2, cpu_env, fp0, fp1, fp2); 11074 gen_store_fpr64(ctx, fp2, fd); 11075 } 11076 break; 11077 case OPC_NMSUB_S: 11078 check_cop1x(ctx); 11079 { 11080 TCGv_i32 fp0 = tcg_temp_new_i32(); 11081 TCGv_i32 fp1 = tcg_temp_new_i32(); 11082 TCGv_i32 fp2 = tcg_temp_new_i32(); 11083 11084 gen_load_fpr32(ctx, fp0, fs); 11085 gen_load_fpr32(ctx, fp1, ft); 11086 gen_load_fpr32(ctx, fp2, fr); 11087 gen_helper_float_nmsub_s(fp2, cpu_env, fp0, fp1, fp2); 11088 gen_store_fpr32(ctx, fp2, fd); 11089 } 11090 break; 11091 case OPC_NMSUB_D: 11092 check_cop1x(ctx); 11093 check_cp1_registers(ctx, fd | fs | ft | fr); 11094 { 11095 TCGv_i64 fp0 = tcg_temp_new_i64(); 11096 TCGv_i64 fp1 = tcg_temp_new_i64(); 11097 TCGv_i64 fp2 = tcg_temp_new_i64(); 11098 11099 gen_load_fpr64(ctx, fp0, fs); 11100 gen_load_fpr64(ctx, fp1, ft); 11101 gen_load_fpr64(ctx, fp2, fr); 11102 gen_helper_float_nmsub_d(fp2, cpu_env, fp0, fp1, fp2); 11103 gen_store_fpr64(ctx, fp2, fd); 11104 } 11105 break; 11106 case OPC_NMSUB_PS: 11107 check_ps(ctx); 11108 { 11109 TCGv_i64 fp0 = tcg_temp_new_i64(); 11110 TCGv_i64 fp1 = tcg_temp_new_i64(); 11111 TCGv_i64 fp2 = tcg_temp_new_i64(); 11112 11113 gen_load_fpr64(ctx, fp0, fs); 11114 gen_load_fpr64(ctx, fp1, ft); 11115 gen_load_fpr64(ctx, fp2, fr); 11116 gen_helper_float_nmsub_ps(fp2, cpu_env, fp0, fp1, fp2); 11117 gen_store_fpr64(ctx, fp2, fd); 11118 } 11119 break; 11120 default: 11121 MIPS_INVAL("flt3_arith"); 11122 gen_reserved_instruction(ctx); 11123 return; 11124 } 11125 } 11126 11127 void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel) 11128 { 11129 TCGv t0; 11130 11131 #if !defined(CONFIG_USER_ONLY) 11132 /* 11133 * The Linux kernel will emulate rdhwr if it's not supported natively. 11134 * Therefore only check the ISA in system mode. 11135 */ 11136 check_insn(ctx, ISA_MIPS_R2); 11137 #endif 11138 t0 = tcg_temp_new(); 11139 11140 switch (rd) { 11141 case 0: 11142 gen_helper_rdhwr_cpunum(t0, cpu_env); 11143 gen_store_gpr(t0, rt); 11144 break; 11145 case 1: 11146 gen_helper_rdhwr_synci_step(t0, cpu_env); 11147 gen_store_gpr(t0, rt); 11148 break; 11149 case 2: 11150 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 11151 gen_io_start(); 11152 } 11153 gen_helper_rdhwr_cc(t0, cpu_env); 11154 gen_store_gpr(t0, rt); 11155 /* 11156 * Break the TB to be able to take timer interrupts immediately 11157 * after reading count. DISAS_STOP isn't sufficient, we need to ensure 11158 * we break completely out of translated code. 11159 */ 11160 gen_save_pc(ctx->base.pc_next + 4); 11161 ctx->base.is_jmp = DISAS_EXIT; 11162 break; 11163 case 3: 11164 gen_helper_rdhwr_ccres(t0, cpu_env); 11165 gen_store_gpr(t0, rt); 11166 break; 11167 case 4: 11168 check_insn(ctx, ISA_MIPS_R6); 11169 if (sel != 0) { 11170 /* 11171 * Performance counter registers are not implemented other than 11172 * control register 0. 11173 */ 11174 generate_exception(ctx, EXCP_RI); 11175 } 11176 gen_helper_rdhwr_performance(t0, cpu_env); 11177 gen_store_gpr(t0, rt); 11178 break; 11179 case 5: 11180 check_insn(ctx, ISA_MIPS_R6); 11181 gen_helper_rdhwr_xnp(t0, cpu_env); 11182 gen_store_gpr(t0, rt); 11183 break; 11184 case 29: 11185 #if defined(CONFIG_USER_ONLY) 11186 tcg_gen_ld_tl(t0, cpu_env, 11187 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 11188 gen_store_gpr(t0, rt); 11189 break; 11190 #else 11191 if ((ctx->hflags & MIPS_HFLAG_CP0) || 11192 (ctx->hflags & MIPS_HFLAG_HWRENA_ULR)) { 11193 tcg_gen_ld_tl(t0, cpu_env, 11194 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 11195 gen_store_gpr(t0, rt); 11196 } else { 11197 gen_reserved_instruction(ctx); 11198 } 11199 break; 11200 #endif 11201 default: /* Invalid */ 11202 MIPS_INVAL("rdhwr"); 11203 gen_reserved_instruction(ctx); 11204 break; 11205 } 11206 } 11207 11208 static inline void clear_branch_hflags(DisasContext *ctx) 11209 { 11210 ctx->hflags &= ~MIPS_HFLAG_BMASK; 11211 if (ctx->base.is_jmp == DISAS_NEXT) { 11212 save_cpu_state(ctx, 0); 11213 } else { 11214 /* 11215 * It is not safe to save ctx->hflags as hflags may be changed 11216 * in execution time by the instruction in delay / forbidden slot. 11217 */ 11218 tcg_gen_andi_i32(hflags, hflags, ~MIPS_HFLAG_BMASK); 11219 } 11220 } 11221 11222 static void gen_branch(DisasContext *ctx, int insn_bytes) 11223 { 11224 if (ctx->hflags & MIPS_HFLAG_BMASK) { 11225 int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK; 11226 /* Branches completion */ 11227 clear_branch_hflags(ctx); 11228 ctx->base.is_jmp = DISAS_NORETURN; 11229 /* FIXME: Need to clear can_do_io. */ 11230 switch (proc_hflags & MIPS_HFLAG_BMASK_BASE) { 11231 case MIPS_HFLAG_FBNSLOT: 11232 gen_goto_tb(ctx, 0, ctx->base.pc_next + insn_bytes); 11233 break; 11234 case MIPS_HFLAG_B: 11235 /* unconditional branch */ 11236 if (proc_hflags & MIPS_HFLAG_BX) { 11237 tcg_gen_xori_i32(hflags, hflags, MIPS_HFLAG_M16); 11238 } 11239 gen_goto_tb(ctx, 0, ctx->btarget); 11240 break; 11241 case MIPS_HFLAG_BL: 11242 /* blikely taken case */ 11243 gen_goto_tb(ctx, 0, ctx->btarget); 11244 break; 11245 case MIPS_HFLAG_BC: 11246 /* Conditional branch */ 11247 { 11248 TCGLabel *l1 = gen_new_label(); 11249 11250 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); 11251 gen_goto_tb(ctx, 1, ctx->base.pc_next + insn_bytes); 11252 gen_set_label(l1); 11253 gen_goto_tb(ctx, 0, ctx->btarget); 11254 } 11255 break; 11256 case MIPS_HFLAG_BR: 11257 /* unconditional branch to register */ 11258 if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) { 11259 TCGv t0 = tcg_temp_new(); 11260 TCGv_i32 t1 = tcg_temp_new_i32(); 11261 11262 tcg_gen_andi_tl(t0, btarget, 0x1); 11263 tcg_gen_trunc_tl_i32(t1, t0); 11264 tcg_gen_andi_i32(hflags, hflags, ~(uint32_t)MIPS_HFLAG_M16); 11265 tcg_gen_shli_i32(t1, t1, MIPS_HFLAG_M16_SHIFT); 11266 tcg_gen_or_i32(hflags, hflags, t1); 11267 11268 tcg_gen_andi_tl(cpu_PC, btarget, ~(target_ulong)0x1); 11269 } else { 11270 tcg_gen_mov_tl(cpu_PC, btarget); 11271 } 11272 tcg_gen_lookup_and_goto_ptr(); 11273 break; 11274 default: 11275 LOG_DISAS("unknown branch 0x%x\n", proc_hflags); 11276 gen_reserved_instruction(ctx); 11277 } 11278 } 11279 } 11280 11281 /* Compact Branches */ 11282 static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, 11283 int rs, int rt, int32_t offset) 11284 { 11285 int bcond_compute = 0; 11286 TCGv t0 = tcg_temp_new(); 11287 TCGv t1 = tcg_temp_new(); 11288 int m16_lowbit = (ctx->hflags & MIPS_HFLAG_M16) != 0; 11289 11290 if (ctx->hflags & MIPS_HFLAG_BMASK) { 11291 #ifdef MIPS_DEBUG_DISAS 11292 LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx 11293 "\n", ctx->base.pc_next); 11294 #endif 11295 gen_reserved_instruction(ctx); 11296 return; 11297 } 11298 11299 /* Load needed operands and calculate btarget */ 11300 switch (opc) { 11301 /* compact branch */ 11302 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */ 11303 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */ 11304 gen_load_gpr(t0, rs); 11305 gen_load_gpr(t1, rt); 11306 bcond_compute = 1; 11307 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 11308 if (rs <= rt && rs == 0) { 11309 /* OPC_BEQZALC, OPC_BNEZALC */ 11310 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); 11311 } 11312 break; 11313 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */ 11314 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */ 11315 gen_load_gpr(t0, rs); 11316 gen_load_gpr(t1, rt); 11317 bcond_compute = 1; 11318 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 11319 break; 11320 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */ 11321 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */ 11322 if (rs == 0 || rs == rt) { 11323 /* OPC_BLEZALC, OPC_BGEZALC */ 11324 /* OPC_BGTZALC, OPC_BLTZALC */ 11325 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); 11326 } 11327 gen_load_gpr(t0, rs); 11328 gen_load_gpr(t1, rt); 11329 bcond_compute = 1; 11330 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 11331 break; 11332 case OPC_BC: 11333 case OPC_BALC: 11334 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 11335 break; 11336 case OPC_BEQZC: 11337 case OPC_BNEZC: 11338 if (rs != 0) { 11339 /* OPC_BEQZC, OPC_BNEZC */ 11340 gen_load_gpr(t0, rs); 11341 bcond_compute = 1; 11342 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 11343 } else { 11344 /* OPC_JIC, OPC_JIALC */ 11345 TCGv tbase = tcg_temp_new(); 11346 TCGv toffset = tcg_constant_tl(offset); 11347 11348 gen_load_gpr(tbase, rt); 11349 gen_op_addr_add(ctx, btarget, tbase, toffset); 11350 } 11351 break; 11352 default: 11353 MIPS_INVAL("Compact branch/jump"); 11354 gen_reserved_instruction(ctx); 11355 return; 11356 } 11357 11358 if (bcond_compute == 0) { 11359 /* Unconditional compact branch */ 11360 switch (opc) { 11361 case OPC_JIALC: 11362 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); 11363 /* Fallthrough */ 11364 case OPC_JIC: 11365 ctx->hflags |= MIPS_HFLAG_BR; 11366 break; 11367 case OPC_BALC: 11368 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); 11369 /* Fallthrough */ 11370 case OPC_BC: 11371 ctx->hflags |= MIPS_HFLAG_B; 11372 break; 11373 default: 11374 MIPS_INVAL("Compact branch/jump"); 11375 gen_reserved_instruction(ctx); 11376 return; 11377 } 11378 11379 /* Generating branch here as compact branches don't have delay slot */ 11380 gen_branch(ctx, 4); 11381 } else { 11382 /* Conditional compact branch */ 11383 TCGLabel *fs = gen_new_label(); 11384 save_cpu_state(ctx, 0); 11385 11386 switch (opc) { 11387 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */ 11388 if (rs == 0 && rt != 0) { 11389 /* OPC_BLEZALC */ 11390 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs); 11391 } else if (rs != 0 && rt != 0 && rs == rt) { 11392 /* OPC_BGEZALC */ 11393 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs); 11394 } else { 11395 /* OPC_BGEUC */ 11396 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU), t0, t1, fs); 11397 } 11398 break; 11399 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */ 11400 if (rs == 0 && rt != 0) { 11401 /* OPC_BGTZALC */ 11402 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs); 11403 } else if (rs != 0 && rt != 0 && rs == rt) { 11404 /* OPC_BLTZALC */ 11405 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs); 11406 } else { 11407 /* OPC_BLTUC */ 11408 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU), t0, t1, fs); 11409 } 11410 break; 11411 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */ 11412 if (rs == 0 && rt != 0) { 11413 /* OPC_BLEZC */ 11414 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs); 11415 } else if (rs != 0 && rt != 0 && rs == rt) { 11416 /* OPC_BGEZC */ 11417 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs); 11418 } else { 11419 /* OPC_BGEC */ 11420 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE), t0, t1, fs); 11421 } 11422 break; 11423 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */ 11424 if (rs == 0 && rt != 0) { 11425 /* OPC_BGTZC */ 11426 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs); 11427 } else if (rs != 0 && rt != 0 && rs == rt) { 11428 /* OPC_BLTZC */ 11429 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs); 11430 } else { 11431 /* OPC_BLTC */ 11432 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT), t0, t1, fs); 11433 } 11434 break; 11435 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */ 11436 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */ 11437 if (rs >= rt) { 11438 /* OPC_BOVC, OPC_BNVC */ 11439 TCGv t2 = tcg_temp_new(); 11440 TCGv t3 = tcg_temp_new(); 11441 TCGv t4 = tcg_temp_new(); 11442 TCGv input_overflow = tcg_temp_new(); 11443 11444 gen_load_gpr(t0, rs); 11445 gen_load_gpr(t1, rt); 11446 tcg_gen_ext32s_tl(t2, t0); 11447 tcg_gen_setcond_tl(TCG_COND_NE, input_overflow, t2, t0); 11448 tcg_gen_ext32s_tl(t3, t1); 11449 tcg_gen_setcond_tl(TCG_COND_NE, t4, t3, t1); 11450 tcg_gen_or_tl(input_overflow, input_overflow, t4); 11451 11452 tcg_gen_add_tl(t4, t2, t3); 11453 tcg_gen_ext32s_tl(t4, t4); 11454 tcg_gen_xor_tl(t2, t2, t3); 11455 tcg_gen_xor_tl(t3, t4, t3); 11456 tcg_gen_andc_tl(t2, t3, t2); 11457 tcg_gen_setcondi_tl(TCG_COND_LT, t4, t2, 0); 11458 tcg_gen_or_tl(t4, t4, input_overflow); 11459 if (opc == OPC_BOVC) { 11460 /* OPC_BOVC */ 11461 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t4, 0, fs); 11462 } else { 11463 /* OPC_BNVC */ 11464 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t4, 0, fs); 11465 } 11466 } else if (rs < rt && rs == 0) { 11467 /* OPC_BEQZALC, OPC_BNEZALC */ 11468 if (opc == OPC_BEQZALC) { 11469 /* OPC_BEQZALC */ 11470 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t1, 0, fs); 11471 } else { 11472 /* OPC_BNEZALC */ 11473 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t1, 0, fs); 11474 } 11475 } else { 11476 /* OPC_BEQC, OPC_BNEC */ 11477 if (opc == OPC_BEQC) { 11478 /* OPC_BEQC */ 11479 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ), t0, t1, fs); 11480 } else { 11481 /* OPC_BNEC */ 11482 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE), t0, t1, fs); 11483 } 11484 } 11485 break; 11486 case OPC_BEQZC: 11487 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t0, 0, fs); 11488 break; 11489 case OPC_BNEZC: 11490 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t0, 0, fs); 11491 break; 11492 default: 11493 MIPS_INVAL("Compact conditional branch/jump"); 11494 gen_reserved_instruction(ctx); 11495 return; 11496 } 11497 11498 /* Generating branch here as compact branches don't have delay slot */ 11499 gen_goto_tb(ctx, 1, ctx->btarget); 11500 gen_set_label(fs); 11501 11502 ctx->hflags |= MIPS_HFLAG_FBNSLOT; 11503 } 11504 } 11505 11506 void gen_addiupc(DisasContext *ctx, int rx, int imm, 11507 int is_64_bit, int extended) 11508 { 11509 TCGv t0; 11510 11511 if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) { 11512 gen_reserved_instruction(ctx); 11513 return; 11514 } 11515 11516 t0 = tcg_temp_new(); 11517 11518 tcg_gen_movi_tl(t0, pc_relative_pc(ctx)); 11519 tcg_gen_addi_tl(cpu_gpr[rx], t0, imm); 11520 if (!is_64_bit) { 11521 tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]); 11522 } 11523 } 11524 11525 static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base, 11526 int16_t offset) 11527 { 11528 TCGv_i32 t0 = tcg_constant_i32(op); 11529 TCGv t1 = tcg_temp_new(); 11530 gen_base_offset_addr(ctx, t1, base, offset); 11531 gen_helper_cache(cpu_env, t1, t0); 11532 } 11533 11534 static inline bool is_uhi(DisasContext *ctx, int sdbbp_code) 11535 { 11536 #ifdef CONFIG_USER_ONLY 11537 return false; 11538 #else 11539 bool is_user = (ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM; 11540 return semihosting_enabled(is_user) && sdbbp_code == 1; 11541 #endif 11542 } 11543 11544 void gen_ldxs(DisasContext *ctx, int base, int index, int rd) 11545 { 11546 TCGv t0 = tcg_temp_new(); 11547 TCGv t1 = tcg_temp_new(); 11548 11549 gen_load_gpr(t0, base); 11550 11551 if (index != 0) { 11552 gen_load_gpr(t1, index); 11553 tcg_gen_shli_tl(t1, t1, 2); 11554 gen_op_addr_add(ctx, t0, t1, t0); 11555 } 11556 11557 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); 11558 gen_store_gpr(t1, rd); 11559 } 11560 11561 static void gen_sync(int stype) 11562 { 11563 TCGBar tcg_mo = TCG_BAR_SC; 11564 11565 switch (stype) { 11566 case 0x4: /* SYNC_WMB */ 11567 tcg_mo |= TCG_MO_ST_ST; 11568 break; 11569 case 0x10: /* SYNC_MB */ 11570 tcg_mo |= TCG_MO_ALL; 11571 break; 11572 case 0x11: /* SYNC_ACQUIRE */ 11573 tcg_mo |= TCG_MO_LD_LD | TCG_MO_LD_ST; 11574 break; 11575 case 0x12: /* SYNC_RELEASE */ 11576 tcg_mo |= TCG_MO_ST_ST | TCG_MO_LD_ST; 11577 break; 11578 case 0x13: /* SYNC_RMB */ 11579 tcg_mo |= TCG_MO_LD_LD; 11580 break; 11581 default: 11582 tcg_mo |= TCG_MO_ALL; 11583 break; 11584 } 11585 11586 tcg_gen_mb(tcg_mo); 11587 } 11588 11589 /* ISA extensions (ASEs) */ 11590 11591 /* MIPS16 extension to MIPS32 */ 11592 #include "mips16e_translate.c.inc" 11593 11594 /* microMIPS extension to MIPS32/MIPS64 */ 11595 11596 /* 11597 * Values for microMIPS fmt field. Variable-width, depending on which 11598 * formats the instruction supports. 11599 */ 11600 enum { 11601 FMT_SD_S = 0, 11602 FMT_SD_D = 1, 11603 11604 FMT_SDPS_S = 0, 11605 FMT_SDPS_D = 1, 11606 FMT_SDPS_PS = 2, 11607 11608 FMT_SWL_S = 0, 11609 FMT_SWL_W = 1, 11610 FMT_SWL_L = 2, 11611 11612 FMT_DWL_D = 0, 11613 FMT_DWL_W = 1, 11614 FMT_DWL_L = 2 11615 }; 11616 11617 #include "micromips_translate.c.inc" 11618 11619 #include "nanomips_translate.c.inc" 11620 11621 /* MIPSDSP functions. */ 11622 11623 /* Indexed load is not for DSP only */ 11624 static void gen_mips_lx(DisasContext *ctx, uint32_t opc, 11625 int rd, int base, int offset) 11626 { 11627 TCGv t0; 11628 11629 if (!(ctx->insn_flags & INSN_OCTEON)) { 11630 check_dsp(ctx); 11631 } 11632 t0 = tcg_temp_new(); 11633 11634 if (base == 0) { 11635 gen_load_gpr(t0, offset); 11636 } else if (offset == 0) { 11637 gen_load_gpr(t0, base); 11638 } else { 11639 gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]); 11640 } 11641 11642 switch (opc) { 11643 case OPC_LBUX: 11644 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB); 11645 gen_store_gpr(t0, rd); 11646 break; 11647 case OPC_LHX: 11648 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW); 11649 gen_store_gpr(t0, rd); 11650 break; 11651 case OPC_LWX: 11652 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL); 11653 gen_store_gpr(t0, rd); 11654 break; 11655 #if defined(TARGET_MIPS64) 11656 case OPC_LDX: 11657 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ); 11658 gen_store_gpr(t0, rd); 11659 break; 11660 #endif 11661 } 11662 } 11663 11664 static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2, 11665 int ret, int v1, int v2) 11666 { 11667 TCGv v1_t; 11668 TCGv v2_t; 11669 11670 if (ret == 0) { 11671 /* Treat as NOP. */ 11672 return; 11673 } 11674 11675 v1_t = tcg_temp_new(); 11676 v2_t = tcg_temp_new(); 11677 11678 gen_load_gpr(v1_t, v1); 11679 gen_load_gpr(v2_t, v2); 11680 11681 switch (op1) { 11682 /* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */ 11683 case OPC_MULT_G_2E: 11684 check_dsp_r2(ctx); 11685 switch (op2) { 11686 case OPC_ADDUH_QB: 11687 gen_helper_adduh_qb(cpu_gpr[ret], v1_t, v2_t); 11688 break; 11689 case OPC_ADDUH_R_QB: 11690 gen_helper_adduh_r_qb(cpu_gpr[ret], v1_t, v2_t); 11691 break; 11692 case OPC_ADDQH_PH: 11693 gen_helper_addqh_ph(cpu_gpr[ret], v1_t, v2_t); 11694 break; 11695 case OPC_ADDQH_R_PH: 11696 gen_helper_addqh_r_ph(cpu_gpr[ret], v1_t, v2_t); 11697 break; 11698 case OPC_ADDQH_W: 11699 gen_helper_addqh_w(cpu_gpr[ret], v1_t, v2_t); 11700 break; 11701 case OPC_ADDQH_R_W: 11702 gen_helper_addqh_r_w(cpu_gpr[ret], v1_t, v2_t); 11703 break; 11704 case OPC_SUBUH_QB: 11705 gen_helper_subuh_qb(cpu_gpr[ret], v1_t, v2_t); 11706 break; 11707 case OPC_SUBUH_R_QB: 11708 gen_helper_subuh_r_qb(cpu_gpr[ret], v1_t, v2_t); 11709 break; 11710 case OPC_SUBQH_PH: 11711 gen_helper_subqh_ph(cpu_gpr[ret], v1_t, v2_t); 11712 break; 11713 case OPC_SUBQH_R_PH: 11714 gen_helper_subqh_r_ph(cpu_gpr[ret], v1_t, v2_t); 11715 break; 11716 case OPC_SUBQH_W: 11717 gen_helper_subqh_w(cpu_gpr[ret], v1_t, v2_t); 11718 break; 11719 case OPC_SUBQH_R_W: 11720 gen_helper_subqh_r_w(cpu_gpr[ret], v1_t, v2_t); 11721 break; 11722 } 11723 break; 11724 case OPC_ABSQ_S_PH_DSP: 11725 switch (op2) { 11726 case OPC_ABSQ_S_QB: 11727 check_dsp_r2(ctx); 11728 gen_helper_absq_s_qb(cpu_gpr[ret], v2_t, cpu_env); 11729 break; 11730 case OPC_ABSQ_S_PH: 11731 check_dsp(ctx); 11732 gen_helper_absq_s_ph(cpu_gpr[ret], v2_t, cpu_env); 11733 break; 11734 case OPC_ABSQ_S_W: 11735 check_dsp(ctx); 11736 gen_helper_absq_s_w(cpu_gpr[ret], v2_t, cpu_env); 11737 break; 11738 case OPC_PRECEQ_W_PHL: 11739 check_dsp(ctx); 11740 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFF0000); 11741 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); 11742 break; 11743 case OPC_PRECEQ_W_PHR: 11744 check_dsp(ctx); 11745 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0x0000FFFF); 11746 tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 16); 11747 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); 11748 break; 11749 case OPC_PRECEQU_PH_QBL: 11750 check_dsp(ctx); 11751 gen_helper_precequ_ph_qbl(cpu_gpr[ret], v2_t); 11752 break; 11753 case OPC_PRECEQU_PH_QBR: 11754 check_dsp(ctx); 11755 gen_helper_precequ_ph_qbr(cpu_gpr[ret], v2_t); 11756 break; 11757 case OPC_PRECEQU_PH_QBLA: 11758 check_dsp(ctx); 11759 gen_helper_precequ_ph_qbla(cpu_gpr[ret], v2_t); 11760 break; 11761 case OPC_PRECEQU_PH_QBRA: 11762 check_dsp(ctx); 11763 gen_helper_precequ_ph_qbra(cpu_gpr[ret], v2_t); 11764 break; 11765 case OPC_PRECEU_PH_QBL: 11766 check_dsp(ctx); 11767 gen_helper_preceu_ph_qbl(cpu_gpr[ret], v2_t); 11768 break; 11769 case OPC_PRECEU_PH_QBR: 11770 check_dsp(ctx); 11771 gen_helper_preceu_ph_qbr(cpu_gpr[ret], v2_t); 11772 break; 11773 case OPC_PRECEU_PH_QBLA: 11774 check_dsp(ctx); 11775 gen_helper_preceu_ph_qbla(cpu_gpr[ret], v2_t); 11776 break; 11777 case OPC_PRECEU_PH_QBRA: 11778 check_dsp(ctx); 11779 gen_helper_preceu_ph_qbra(cpu_gpr[ret], v2_t); 11780 break; 11781 } 11782 break; 11783 case OPC_ADDU_QB_DSP: 11784 switch (op2) { 11785 case OPC_ADDQ_PH: 11786 check_dsp(ctx); 11787 gen_helper_addq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11788 break; 11789 case OPC_ADDQ_S_PH: 11790 check_dsp(ctx); 11791 gen_helper_addq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11792 break; 11793 case OPC_ADDQ_S_W: 11794 check_dsp(ctx); 11795 gen_helper_addq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11796 break; 11797 case OPC_ADDU_QB: 11798 check_dsp(ctx); 11799 gen_helper_addu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11800 break; 11801 case OPC_ADDU_S_QB: 11802 check_dsp(ctx); 11803 gen_helper_addu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11804 break; 11805 case OPC_ADDU_PH: 11806 check_dsp_r2(ctx); 11807 gen_helper_addu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11808 break; 11809 case OPC_ADDU_S_PH: 11810 check_dsp_r2(ctx); 11811 gen_helper_addu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11812 break; 11813 case OPC_SUBQ_PH: 11814 check_dsp(ctx); 11815 gen_helper_subq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11816 break; 11817 case OPC_SUBQ_S_PH: 11818 check_dsp(ctx); 11819 gen_helper_subq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11820 break; 11821 case OPC_SUBQ_S_W: 11822 check_dsp(ctx); 11823 gen_helper_subq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11824 break; 11825 case OPC_SUBU_QB: 11826 check_dsp(ctx); 11827 gen_helper_subu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11828 break; 11829 case OPC_SUBU_S_QB: 11830 check_dsp(ctx); 11831 gen_helper_subu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11832 break; 11833 case OPC_SUBU_PH: 11834 check_dsp_r2(ctx); 11835 gen_helper_subu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11836 break; 11837 case OPC_SUBU_S_PH: 11838 check_dsp_r2(ctx); 11839 gen_helper_subu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11840 break; 11841 case OPC_ADDSC: 11842 check_dsp(ctx); 11843 gen_helper_addsc(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11844 break; 11845 case OPC_ADDWC: 11846 check_dsp(ctx); 11847 gen_helper_addwc(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11848 break; 11849 case OPC_MODSUB: 11850 check_dsp(ctx); 11851 gen_helper_modsub(cpu_gpr[ret], v1_t, v2_t); 11852 break; 11853 case OPC_RADDU_W_QB: 11854 check_dsp(ctx); 11855 gen_helper_raddu_w_qb(cpu_gpr[ret], v1_t); 11856 break; 11857 } 11858 break; 11859 case OPC_CMPU_EQ_QB_DSP: 11860 switch (op2) { 11861 case OPC_PRECR_QB_PH: 11862 check_dsp_r2(ctx); 11863 gen_helper_precr_qb_ph(cpu_gpr[ret], v1_t, v2_t); 11864 break; 11865 case OPC_PRECRQ_QB_PH: 11866 check_dsp(ctx); 11867 gen_helper_precrq_qb_ph(cpu_gpr[ret], v1_t, v2_t); 11868 break; 11869 case OPC_PRECR_SRA_PH_W: 11870 check_dsp_r2(ctx); 11871 { 11872 TCGv_i32 sa_t = tcg_constant_i32(v2); 11873 gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t, v1_t, 11874 cpu_gpr[ret]); 11875 break; 11876 } 11877 case OPC_PRECR_SRA_R_PH_W: 11878 check_dsp_r2(ctx); 11879 { 11880 TCGv_i32 sa_t = tcg_constant_i32(v2); 11881 gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t, v1_t, 11882 cpu_gpr[ret]); 11883 break; 11884 } 11885 case OPC_PRECRQ_PH_W: 11886 check_dsp(ctx); 11887 gen_helper_precrq_ph_w(cpu_gpr[ret], v1_t, v2_t); 11888 break; 11889 case OPC_PRECRQ_RS_PH_W: 11890 check_dsp(ctx); 11891 gen_helper_precrq_rs_ph_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11892 break; 11893 case OPC_PRECRQU_S_QB_PH: 11894 check_dsp(ctx); 11895 gen_helper_precrqu_s_qb_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11896 break; 11897 } 11898 break; 11899 #ifdef TARGET_MIPS64 11900 case OPC_ABSQ_S_QH_DSP: 11901 switch (op2) { 11902 case OPC_PRECEQ_L_PWL: 11903 check_dsp(ctx); 11904 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFFFFFF00000000ull); 11905 break; 11906 case OPC_PRECEQ_L_PWR: 11907 check_dsp(ctx); 11908 tcg_gen_shli_tl(cpu_gpr[ret], v2_t, 32); 11909 break; 11910 case OPC_PRECEQ_PW_QHL: 11911 check_dsp(ctx); 11912 gen_helper_preceq_pw_qhl(cpu_gpr[ret], v2_t); 11913 break; 11914 case OPC_PRECEQ_PW_QHR: 11915 check_dsp(ctx); 11916 gen_helper_preceq_pw_qhr(cpu_gpr[ret], v2_t); 11917 break; 11918 case OPC_PRECEQ_PW_QHLA: 11919 check_dsp(ctx); 11920 gen_helper_preceq_pw_qhla(cpu_gpr[ret], v2_t); 11921 break; 11922 case OPC_PRECEQ_PW_QHRA: 11923 check_dsp(ctx); 11924 gen_helper_preceq_pw_qhra(cpu_gpr[ret], v2_t); 11925 break; 11926 case OPC_PRECEQU_QH_OBL: 11927 check_dsp(ctx); 11928 gen_helper_precequ_qh_obl(cpu_gpr[ret], v2_t); 11929 break; 11930 case OPC_PRECEQU_QH_OBR: 11931 check_dsp(ctx); 11932 gen_helper_precequ_qh_obr(cpu_gpr[ret], v2_t); 11933 break; 11934 case OPC_PRECEQU_QH_OBLA: 11935 check_dsp(ctx); 11936 gen_helper_precequ_qh_obla(cpu_gpr[ret], v2_t); 11937 break; 11938 case OPC_PRECEQU_QH_OBRA: 11939 check_dsp(ctx); 11940 gen_helper_precequ_qh_obra(cpu_gpr[ret], v2_t); 11941 break; 11942 case OPC_PRECEU_QH_OBL: 11943 check_dsp(ctx); 11944 gen_helper_preceu_qh_obl(cpu_gpr[ret], v2_t); 11945 break; 11946 case OPC_PRECEU_QH_OBR: 11947 check_dsp(ctx); 11948 gen_helper_preceu_qh_obr(cpu_gpr[ret], v2_t); 11949 break; 11950 case OPC_PRECEU_QH_OBLA: 11951 check_dsp(ctx); 11952 gen_helper_preceu_qh_obla(cpu_gpr[ret], v2_t); 11953 break; 11954 case OPC_PRECEU_QH_OBRA: 11955 check_dsp(ctx); 11956 gen_helper_preceu_qh_obra(cpu_gpr[ret], v2_t); 11957 break; 11958 case OPC_ABSQ_S_OB: 11959 check_dsp_r2(ctx); 11960 gen_helper_absq_s_ob(cpu_gpr[ret], v2_t, cpu_env); 11961 break; 11962 case OPC_ABSQ_S_PW: 11963 check_dsp(ctx); 11964 gen_helper_absq_s_pw(cpu_gpr[ret], v2_t, cpu_env); 11965 break; 11966 case OPC_ABSQ_S_QH: 11967 check_dsp(ctx); 11968 gen_helper_absq_s_qh(cpu_gpr[ret], v2_t, cpu_env); 11969 break; 11970 } 11971 break; 11972 case OPC_ADDU_OB_DSP: 11973 switch (op2) { 11974 case OPC_RADDU_L_OB: 11975 check_dsp(ctx); 11976 gen_helper_raddu_l_ob(cpu_gpr[ret], v1_t); 11977 break; 11978 case OPC_SUBQ_PW: 11979 check_dsp(ctx); 11980 gen_helper_subq_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11981 break; 11982 case OPC_SUBQ_S_PW: 11983 check_dsp(ctx); 11984 gen_helper_subq_s_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11985 break; 11986 case OPC_SUBQ_QH: 11987 check_dsp(ctx); 11988 gen_helper_subq_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11989 break; 11990 case OPC_SUBQ_S_QH: 11991 check_dsp(ctx); 11992 gen_helper_subq_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11993 break; 11994 case OPC_SUBU_OB: 11995 check_dsp(ctx); 11996 gen_helper_subu_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11997 break; 11998 case OPC_SUBU_S_OB: 11999 check_dsp(ctx); 12000 gen_helper_subu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12001 break; 12002 case OPC_SUBU_QH: 12003 check_dsp_r2(ctx); 12004 gen_helper_subu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12005 break; 12006 case OPC_SUBU_S_QH: 12007 check_dsp_r2(ctx); 12008 gen_helper_subu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12009 break; 12010 case OPC_SUBUH_OB: 12011 check_dsp_r2(ctx); 12012 gen_helper_subuh_ob(cpu_gpr[ret], v1_t, v2_t); 12013 break; 12014 case OPC_SUBUH_R_OB: 12015 check_dsp_r2(ctx); 12016 gen_helper_subuh_r_ob(cpu_gpr[ret], v1_t, v2_t); 12017 break; 12018 case OPC_ADDQ_PW: 12019 check_dsp(ctx); 12020 gen_helper_addq_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12021 break; 12022 case OPC_ADDQ_S_PW: 12023 check_dsp(ctx); 12024 gen_helper_addq_s_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12025 break; 12026 case OPC_ADDQ_QH: 12027 check_dsp(ctx); 12028 gen_helper_addq_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12029 break; 12030 case OPC_ADDQ_S_QH: 12031 check_dsp(ctx); 12032 gen_helper_addq_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12033 break; 12034 case OPC_ADDU_OB: 12035 check_dsp(ctx); 12036 gen_helper_addu_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12037 break; 12038 case OPC_ADDU_S_OB: 12039 check_dsp(ctx); 12040 gen_helper_addu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12041 break; 12042 case OPC_ADDU_QH: 12043 check_dsp_r2(ctx); 12044 gen_helper_addu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12045 break; 12046 case OPC_ADDU_S_QH: 12047 check_dsp_r2(ctx); 12048 gen_helper_addu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12049 break; 12050 case OPC_ADDUH_OB: 12051 check_dsp_r2(ctx); 12052 gen_helper_adduh_ob(cpu_gpr[ret], v1_t, v2_t); 12053 break; 12054 case OPC_ADDUH_R_OB: 12055 check_dsp_r2(ctx); 12056 gen_helper_adduh_r_ob(cpu_gpr[ret], v1_t, v2_t); 12057 break; 12058 } 12059 break; 12060 case OPC_CMPU_EQ_OB_DSP: 12061 switch (op2) { 12062 case OPC_PRECR_OB_QH: 12063 check_dsp_r2(ctx); 12064 gen_helper_precr_ob_qh(cpu_gpr[ret], v1_t, v2_t); 12065 break; 12066 case OPC_PRECR_SRA_QH_PW: 12067 check_dsp_r2(ctx); 12068 { 12069 TCGv_i32 ret_t = tcg_constant_i32(ret); 12070 gen_helper_precr_sra_qh_pw(v2_t, v1_t, v2_t, ret_t); 12071 break; 12072 } 12073 case OPC_PRECR_SRA_R_QH_PW: 12074 check_dsp_r2(ctx); 12075 { 12076 TCGv_i32 sa_v = tcg_constant_i32(ret); 12077 gen_helper_precr_sra_r_qh_pw(v2_t, v1_t, v2_t, sa_v); 12078 break; 12079 } 12080 case OPC_PRECRQ_OB_QH: 12081 check_dsp(ctx); 12082 gen_helper_precrq_ob_qh(cpu_gpr[ret], v1_t, v2_t); 12083 break; 12084 case OPC_PRECRQ_PW_L: 12085 check_dsp(ctx); 12086 gen_helper_precrq_pw_l(cpu_gpr[ret], v1_t, v2_t); 12087 break; 12088 case OPC_PRECRQ_QH_PW: 12089 check_dsp(ctx); 12090 gen_helper_precrq_qh_pw(cpu_gpr[ret], v1_t, v2_t); 12091 break; 12092 case OPC_PRECRQ_RS_QH_PW: 12093 check_dsp(ctx); 12094 gen_helper_precrq_rs_qh_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12095 break; 12096 case OPC_PRECRQU_S_OB_QH: 12097 check_dsp(ctx); 12098 gen_helper_precrqu_s_ob_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12099 break; 12100 } 12101 break; 12102 #endif 12103 } 12104 } 12105 12106 static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc, 12107 int ret, int v1, int v2) 12108 { 12109 uint32_t op2; 12110 TCGv t0; 12111 TCGv v1_t; 12112 TCGv v2_t; 12113 12114 if (ret == 0) { 12115 /* Treat as NOP. */ 12116 return; 12117 } 12118 12119 t0 = tcg_temp_new(); 12120 v1_t = tcg_temp_new(); 12121 v2_t = tcg_temp_new(); 12122 12123 tcg_gen_movi_tl(t0, v1); 12124 gen_load_gpr(v1_t, v1); 12125 gen_load_gpr(v2_t, v2); 12126 12127 switch (opc) { 12128 case OPC_SHLL_QB_DSP: 12129 { 12130 op2 = MASK_SHLL_QB(ctx->opcode); 12131 switch (op2) { 12132 case OPC_SHLL_QB: 12133 check_dsp(ctx); 12134 gen_helper_shll_qb(cpu_gpr[ret], t0, v2_t, cpu_env); 12135 break; 12136 case OPC_SHLLV_QB: 12137 check_dsp(ctx); 12138 gen_helper_shll_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12139 break; 12140 case OPC_SHLL_PH: 12141 check_dsp(ctx); 12142 gen_helper_shll_ph(cpu_gpr[ret], t0, v2_t, cpu_env); 12143 break; 12144 case OPC_SHLLV_PH: 12145 check_dsp(ctx); 12146 gen_helper_shll_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12147 break; 12148 case OPC_SHLL_S_PH: 12149 check_dsp(ctx); 12150 gen_helper_shll_s_ph(cpu_gpr[ret], t0, v2_t, cpu_env); 12151 break; 12152 case OPC_SHLLV_S_PH: 12153 check_dsp(ctx); 12154 gen_helper_shll_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12155 break; 12156 case OPC_SHLL_S_W: 12157 check_dsp(ctx); 12158 gen_helper_shll_s_w(cpu_gpr[ret], t0, v2_t, cpu_env); 12159 break; 12160 case OPC_SHLLV_S_W: 12161 check_dsp(ctx); 12162 gen_helper_shll_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12163 break; 12164 case OPC_SHRL_QB: 12165 check_dsp(ctx); 12166 gen_helper_shrl_qb(cpu_gpr[ret], t0, v2_t); 12167 break; 12168 case OPC_SHRLV_QB: 12169 check_dsp(ctx); 12170 gen_helper_shrl_qb(cpu_gpr[ret], v1_t, v2_t); 12171 break; 12172 case OPC_SHRL_PH: 12173 check_dsp_r2(ctx); 12174 gen_helper_shrl_ph(cpu_gpr[ret], t0, v2_t); 12175 break; 12176 case OPC_SHRLV_PH: 12177 check_dsp_r2(ctx); 12178 gen_helper_shrl_ph(cpu_gpr[ret], v1_t, v2_t); 12179 break; 12180 case OPC_SHRA_QB: 12181 check_dsp_r2(ctx); 12182 gen_helper_shra_qb(cpu_gpr[ret], t0, v2_t); 12183 break; 12184 case OPC_SHRA_R_QB: 12185 check_dsp_r2(ctx); 12186 gen_helper_shra_r_qb(cpu_gpr[ret], t0, v2_t); 12187 break; 12188 case OPC_SHRAV_QB: 12189 check_dsp_r2(ctx); 12190 gen_helper_shra_qb(cpu_gpr[ret], v1_t, v2_t); 12191 break; 12192 case OPC_SHRAV_R_QB: 12193 check_dsp_r2(ctx); 12194 gen_helper_shra_r_qb(cpu_gpr[ret], v1_t, v2_t); 12195 break; 12196 case OPC_SHRA_PH: 12197 check_dsp(ctx); 12198 gen_helper_shra_ph(cpu_gpr[ret], t0, v2_t); 12199 break; 12200 case OPC_SHRA_R_PH: 12201 check_dsp(ctx); 12202 gen_helper_shra_r_ph(cpu_gpr[ret], t0, v2_t); 12203 break; 12204 case OPC_SHRAV_PH: 12205 check_dsp(ctx); 12206 gen_helper_shra_ph(cpu_gpr[ret], v1_t, v2_t); 12207 break; 12208 case OPC_SHRAV_R_PH: 12209 check_dsp(ctx); 12210 gen_helper_shra_r_ph(cpu_gpr[ret], v1_t, v2_t); 12211 break; 12212 case OPC_SHRA_R_W: 12213 check_dsp(ctx); 12214 gen_helper_shra_r_w(cpu_gpr[ret], t0, v2_t); 12215 break; 12216 case OPC_SHRAV_R_W: 12217 check_dsp(ctx); 12218 gen_helper_shra_r_w(cpu_gpr[ret], v1_t, v2_t); 12219 break; 12220 default: /* Invalid */ 12221 MIPS_INVAL("MASK SHLL.QB"); 12222 gen_reserved_instruction(ctx); 12223 break; 12224 } 12225 break; 12226 } 12227 #ifdef TARGET_MIPS64 12228 case OPC_SHLL_OB_DSP: 12229 op2 = MASK_SHLL_OB(ctx->opcode); 12230 switch (op2) { 12231 case OPC_SHLL_PW: 12232 check_dsp(ctx); 12233 gen_helper_shll_pw(cpu_gpr[ret], v2_t, t0, cpu_env); 12234 break; 12235 case OPC_SHLLV_PW: 12236 check_dsp(ctx); 12237 gen_helper_shll_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env); 12238 break; 12239 case OPC_SHLL_S_PW: 12240 check_dsp(ctx); 12241 gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, t0, cpu_env); 12242 break; 12243 case OPC_SHLLV_S_PW: 12244 check_dsp(ctx); 12245 gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env); 12246 break; 12247 case OPC_SHLL_OB: 12248 check_dsp(ctx); 12249 gen_helper_shll_ob(cpu_gpr[ret], v2_t, t0, cpu_env); 12250 break; 12251 case OPC_SHLLV_OB: 12252 check_dsp(ctx); 12253 gen_helper_shll_ob(cpu_gpr[ret], v2_t, v1_t, cpu_env); 12254 break; 12255 case OPC_SHLL_QH: 12256 check_dsp(ctx); 12257 gen_helper_shll_qh(cpu_gpr[ret], v2_t, t0, cpu_env); 12258 break; 12259 case OPC_SHLLV_QH: 12260 check_dsp(ctx); 12261 gen_helper_shll_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env); 12262 break; 12263 case OPC_SHLL_S_QH: 12264 check_dsp(ctx); 12265 gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, t0, cpu_env); 12266 break; 12267 case OPC_SHLLV_S_QH: 12268 check_dsp(ctx); 12269 gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env); 12270 break; 12271 case OPC_SHRA_OB: 12272 check_dsp_r2(ctx); 12273 gen_helper_shra_ob(cpu_gpr[ret], v2_t, t0); 12274 break; 12275 case OPC_SHRAV_OB: 12276 check_dsp_r2(ctx); 12277 gen_helper_shra_ob(cpu_gpr[ret], v2_t, v1_t); 12278 break; 12279 case OPC_SHRA_R_OB: 12280 check_dsp_r2(ctx); 12281 gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, t0); 12282 break; 12283 case OPC_SHRAV_R_OB: 12284 check_dsp_r2(ctx); 12285 gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, v1_t); 12286 break; 12287 case OPC_SHRA_PW: 12288 check_dsp(ctx); 12289 gen_helper_shra_pw(cpu_gpr[ret], v2_t, t0); 12290 break; 12291 case OPC_SHRAV_PW: 12292 check_dsp(ctx); 12293 gen_helper_shra_pw(cpu_gpr[ret], v2_t, v1_t); 12294 break; 12295 case OPC_SHRA_R_PW: 12296 check_dsp(ctx); 12297 gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, t0); 12298 break; 12299 case OPC_SHRAV_R_PW: 12300 check_dsp(ctx); 12301 gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, v1_t); 12302 break; 12303 case OPC_SHRA_QH: 12304 check_dsp(ctx); 12305 gen_helper_shra_qh(cpu_gpr[ret], v2_t, t0); 12306 break; 12307 case OPC_SHRAV_QH: 12308 check_dsp(ctx); 12309 gen_helper_shra_qh(cpu_gpr[ret], v2_t, v1_t); 12310 break; 12311 case OPC_SHRA_R_QH: 12312 check_dsp(ctx); 12313 gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, t0); 12314 break; 12315 case OPC_SHRAV_R_QH: 12316 check_dsp(ctx); 12317 gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, v1_t); 12318 break; 12319 case OPC_SHRL_OB: 12320 check_dsp(ctx); 12321 gen_helper_shrl_ob(cpu_gpr[ret], v2_t, t0); 12322 break; 12323 case OPC_SHRLV_OB: 12324 check_dsp(ctx); 12325 gen_helper_shrl_ob(cpu_gpr[ret], v2_t, v1_t); 12326 break; 12327 case OPC_SHRL_QH: 12328 check_dsp_r2(ctx); 12329 gen_helper_shrl_qh(cpu_gpr[ret], v2_t, t0); 12330 break; 12331 case OPC_SHRLV_QH: 12332 check_dsp_r2(ctx); 12333 gen_helper_shrl_qh(cpu_gpr[ret], v2_t, v1_t); 12334 break; 12335 default: /* Invalid */ 12336 MIPS_INVAL("MASK SHLL.OB"); 12337 gen_reserved_instruction(ctx); 12338 break; 12339 } 12340 break; 12341 #endif 12342 } 12343 } 12344 12345 static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2, 12346 int ret, int v1, int v2, int check_ret) 12347 { 12348 TCGv_i32 t0; 12349 TCGv v1_t; 12350 TCGv v2_t; 12351 12352 if ((ret == 0) && (check_ret == 1)) { 12353 /* Treat as NOP. */ 12354 return; 12355 } 12356 12357 t0 = tcg_temp_new_i32(); 12358 v1_t = tcg_temp_new(); 12359 v2_t = tcg_temp_new(); 12360 12361 tcg_gen_movi_i32(t0, ret); 12362 gen_load_gpr(v1_t, v1); 12363 gen_load_gpr(v2_t, v2); 12364 12365 switch (op1) { 12366 /* 12367 * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have 12368 * the same mask and op1. 12369 */ 12370 case OPC_MULT_G_2E: 12371 check_dsp_r2(ctx); 12372 switch (op2) { 12373 case OPC_MUL_PH: 12374 gen_helper_mul_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12375 break; 12376 case OPC_MUL_S_PH: 12377 gen_helper_mul_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12378 break; 12379 case OPC_MULQ_S_W: 12380 gen_helper_mulq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12381 break; 12382 case OPC_MULQ_RS_W: 12383 gen_helper_mulq_rs_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12384 break; 12385 } 12386 break; 12387 case OPC_DPA_W_PH_DSP: 12388 switch (op2) { 12389 case OPC_DPAU_H_QBL: 12390 check_dsp(ctx); 12391 gen_helper_dpau_h_qbl(t0, v1_t, v2_t, cpu_env); 12392 break; 12393 case OPC_DPAU_H_QBR: 12394 check_dsp(ctx); 12395 gen_helper_dpau_h_qbr(t0, v1_t, v2_t, cpu_env); 12396 break; 12397 case OPC_DPSU_H_QBL: 12398 check_dsp(ctx); 12399 gen_helper_dpsu_h_qbl(t0, v1_t, v2_t, cpu_env); 12400 break; 12401 case OPC_DPSU_H_QBR: 12402 check_dsp(ctx); 12403 gen_helper_dpsu_h_qbr(t0, v1_t, v2_t, cpu_env); 12404 break; 12405 case OPC_DPA_W_PH: 12406 check_dsp_r2(ctx); 12407 gen_helper_dpa_w_ph(t0, v1_t, v2_t, cpu_env); 12408 break; 12409 case OPC_DPAX_W_PH: 12410 check_dsp_r2(ctx); 12411 gen_helper_dpax_w_ph(t0, v1_t, v2_t, cpu_env); 12412 break; 12413 case OPC_DPAQ_S_W_PH: 12414 check_dsp(ctx); 12415 gen_helper_dpaq_s_w_ph(t0, v1_t, v2_t, cpu_env); 12416 break; 12417 case OPC_DPAQX_S_W_PH: 12418 check_dsp_r2(ctx); 12419 gen_helper_dpaqx_s_w_ph(t0, v1_t, v2_t, cpu_env); 12420 break; 12421 case OPC_DPAQX_SA_W_PH: 12422 check_dsp_r2(ctx); 12423 gen_helper_dpaqx_sa_w_ph(t0, v1_t, v2_t, cpu_env); 12424 break; 12425 case OPC_DPS_W_PH: 12426 check_dsp_r2(ctx); 12427 gen_helper_dps_w_ph(t0, v1_t, v2_t, cpu_env); 12428 break; 12429 case OPC_DPSX_W_PH: 12430 check_dsp_r2(ctx); 12431 gen_helper_dpsx_w_ph(t0, v1_t, v2_t, cpu_env); 12432 break; 12433 case OPC_DPSQ_S_W_PH: 12434 check_dsp(ctx); 12435 gen_helper_dpsq_s_w_ph(t0, v1_t, v2_t, cpu_env); 12436 break; 12437 case OPC_DPSQX_S_W_PH: 12438 check_dsp_r2(ctx); 12439 gen_helper_dpsqx_s_w_ph(t0, v1_t, v2_t, cpu_env); 12440 break; 12441 case OPC_DPSQX_SA_W_PH: 12442 check_dsp_r2(ctx); 12443 gen_helper_dpsqx_sa_w_ph(t0, v1_t, v2_t, cpu_env); 12444 break; 12445 case OPC_MULSAQ_S_W_PH: 12446 check_dsp(ctx); 12447 gen_helper_mulsaq_s_w_ph(t0, v1_t, v2_t, cpu_env); 12448 break; 12449 case OPC_DPAQ_SA_L_W: 12450 check_dsp(ctx); 12451 gen_helper_dpaq_sa_l_w(t0, v1_t, v2_t, cpu_env); 12452 break; 12453 case OPC_DPSQ_SA_L_W: 12454 check_dsp(ctx); 12455 gen_helper_dpsq_sa_l_w(t0, v1_t, v2_t, cpu_env); 12456 break; 12457 case OPC_MAQ_S_W_PHL: 12458 check_dsp(ctx); 12459 gen_helper_maq_s_w_phl(t0, v1_t, v2_t, cpu_env); 12460 break; 12461 case OPC_MAQ_S_W_PHR: 12462 check_dsp(ctx); 12463 gen_helper_maq_s_w_phr(t0, v1_t, v2_t, cpu_env); 12464 break; 12465 case OPC_MAQ_SA_W_PHL: 12466 check_dsp(ctx); 12467 gen_helper_maq_sa_w_phl(t0, v1_t, v2_t, cpu_env); 12468 break; 12469 case OPC_MAQ_SA_W_PHR: 12470 check_dsp(ctx); 12471 gen_helper_maq_sa_w_phr(t0, v1_t, v2_t, cpu_env); 12472 break; 12473 case OPC_MULSA_W_PH: 12474 check_dsp_r2(ctx); 12475 gen_helper_mulsa_w_ph(t0, v1_t, v2_t, cpu_env); 12476 break; 12477 } 12478 break; 12479 #ifdef TARGET_MIPS64 12480 case OPC_DPAQ_W_QH_DSP: 12481 { 12482 int ac = ret & 0x03; 12483 tcg_gen_movi_i32(t0, ac); 12484 12485 switch (op2) { 12486 case OPC_DMADD: 12487 check_dsp(ctx); 12488 gen_helper_dmadd(v1_t, v2_t, t0, cpu_env); 12489 break; 12490 case OPC_DMADDU: 12491 check_dsp(ctx); 12492 gen_helper_dmaddu(v1_t, v2_t, t0, cpu_env); 12493 break; 12494 case OPC_DMSUB: 12495 check_dsp(ctx); 12496 gen_helper_dmsub(v1_t, v2_t, t0, cpu_env); 12497 break; 12498 case OPC_DMSUBU: 12499 check_dsp(ctx); 12500 gen_helper_dmsubu(v1_t, v2_t, t0, cpu_env); 12501 break; 12502 case OPC_DPA_W_QH: 12503 check_dsp_r2(ctx); 12504 gen_helper_dpa_w_qh(v1_t, v2_t, t0, cpu_env); 12505 break; 12506 case OPC_DPAQ_S_W_QH: 12507 check_dsp(ctx); 12508 gen_helper_dpaq_s_w_qh(v1_t, v2_t, t0, cpu_env); 12509 break; 12510 case OPC_DPAQ_SA_L_PW: 12511 check_dsp(ctx); 12512 gen_helper_dpaq_sa_l_pw(v1_t, v2_t, t0, cpu_env); 12513 break; 12514 case OPC_DPAU_H_OBL: 12515 check_dsp(ctx); 12516 gen_helper_dpau_h_obl(v1_t, v2_t, t0, cpu_env); 12517 break; 12518 case OPC_DPAU_H_OBR: 12519 check_dsp(ctx); 12520 gen_helper_dpau_h_obr(v1_t, v2_t, t0, cpu_env); 12521 break; 12522 case OPC_DPS_W_QH: 12523 check_dsp_r2(ctx); 12524 gen_helper_dps_w_qh(v1_t, v2_t, t0, cpu_env); 12525 break; 12526 case OPC_DPSQ_S_W_QH: 12527 check_dsp(ctx); 12528 gen_helper_dpsq_s_w_qh(v1_t, v2_t, t0, cpu_env); 12529 break; 12530 case OPC_DPSQ_SA_L_PW: 12531 check_dsp(ctx); 12532 gen_helper_dpsq_sa_l_pw(v1_t, v2_t, t0, cpu_env); 12533 break; 12534 case OPC_DPSU_H_OBL: 12535 check_dsp(ctx); 12536 gen_helper_dpsu_h_obl(v1_t, v2_t, t0, cpu_env); 12537 break; 12538 case OPC_DPSU_H_OBR: 12539 check_dsp(ctx); 12540 gen_helper_dpsu_h_obr(v1_t, v2_t, t0, cpu_env); 12541 break; 12542 case OPC_MAQ_S_L_PWL: 12543 check_dsp(ctx); 12544 gen_helper_maq_s_l_pwl(v1_t, v2_t, t0, cpu_env); 12545 break; 12546 case OPC_MAQ_S_L_PWR: 12547 check_dsp(ctx); 12548 gen_helper_maq_s_l_pwr(v1_t, v2_t, t0, cpu_env); 12549 break; 12550 case OPC_MAQ_S_W_QHLL: 12551 check_dsp(ctx); 12552 gen_helper_maq_s_w_qhll(v1_t, v2_t, t0, cpu_env); 12553 break; 12554 case OPC_MAQ_SA_W_QHLL: 12555 check_dsp(ctx); 12556 gen_helper_maq_sa_w_qhll(v1_t, v2_t, t0, cpu_env); 12557 break; 12558 case OPC_MAQ_S_W_QHLR: 12559 check_dsp(ctx); 12560 gen_helper_maq_s_w_qhlr(v1_t, v2_t, t0, cpu_env); 12561 break; 12562 case OPC_MAQ_SA_W_QHLR: 12563 check_dsp(ctx); 12564 gen_helper_maq_sa_w_qhlr(v1_t, v2_t, t0, cpu_env); 12565 break; 12566 case OPC_MAQ_S_W_QHRL: 12567 check_dsp(ctx); 12568 gen_helper_maq_s_w_qhrl(v1_t, v2_t, t0, cpu_env); 12569 break; 12570 case OPC_MAQ_SA_W_QHRL: 12571 check_dsp(ctx); 12572 gen_helper_maq_sa_w_qhrl(v1_t, v2_t, t0, cpu_env); 12573 break; 12574 case OPC_MAQ_S_W_QHRR: 12575 check_dsp(ctx); 12576 gen_helper_maq_s_w_qhrr(v1_t, v2_t, t0, cpu_env); 12577 break; 12578 case OPC_MAQ_SA_W_QHRR: 12579 check_dsp(ctx); 12580 gen_helper_maq_sa_w_qhrr(v1_t, v2_t, t0, cpu_env); 12581 break; 12582 case OPC_MULSAQ_S_L_PW: 12583 check_dsp(ctx); 12584 gen_helper_mulsaq_s_l_pw(v1_t, v2_t, t0, cpu_env); 12585 break; 12586 case OPC_MULSAQ_S_W_QH: 12587 check_dsp(ctx); 12588 gen_helper_mulsaq_s_w_qh(v1_t, v2_t, t0, cpu_env); 12589 break; 12590 } 12591 } 12592 break; 12593 #endif 12594 case OPC_ADDU_QB_DSP: 12595 switch (op2) { 12596 case OPC_MULEU_S_PH_QBL: 12597 check_dsp(ctx); 12598 gen_helper_muleu_s_ph_qbl(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12599 break; 12600 case OPC_MULEU_S_PH_QBR: 12601 check_dsp(ctx); 12602 gen_helper_muleu_s_ph_qbr(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12603 break; 12604 case OPC_MULQ_RS_PH: 12605 check_dsp(ctx); 12606 gen_helper_mulq_rs_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12607 break; 12608 case OPC_MULEQ_S_W_PHL: 12609 check_dsp(ctx); 12610 gen_helper_muleq_s_w_phl(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12611 break; 12612 case OPC_MULEQ_S_W_PHR: 12613 check_dsp(ctx); 12614 gen_helper_muleq_s_w_phr(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12615 break; 12616 case OPC_MULQ_S_PH: 12617 check_dsp_r2(ctx); 12618 gen_helper_mulq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12619 break; 12620 } 12621 break; 12622 #ifdef TARGET_MIPS64 12623 case OPC_ADDU_OB_DSP: 12624 switch (op2) { 12625 case OPC_MULEQ_S_PW_QHL: 12626 check_dsp(ctx); 12627 gen_helper_muleq_s_pw_qhl(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12628 break; 12629 case OPC_MULEQ_S_PW_QHR: 12630 check_dsp(ctx); 12631 gen_helper_muleq_s_pw_qhr(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12632 break; 12633 case OPC_MULEU_S_QH_OBL: 12634 check_dsp(ctx); 12635 gen_helper_muleu_s_qh_obl(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12636 break; 12637 case OPC_MULEU_S_QH_OBR: 12638 check_dsp(ctx); 12639 gen_helper_muleu_s_qh_obr(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12640 break; 12641 case OPC_MULQ_RS_QH: 12642 check_dsp(ctx); 12643 gen_helper_mulq_rs_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12644 break; 12645 } 12646 break; 12647 #endif 12648 } 12649 } 12650 12651 static void gen_mipsdsp_bitinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, 12652 int ret, int val) 12653 { 12654 int16_t imm; 12655 TCGv t0; 12656 TCGv val_t; 12657 12658 if (ret == 0) { 12659 /* Treat as NOP. */ 12660 return; 12661 } 12662 12663 t0 = tcg_temp_new(); 12664 val_t = tcg_temp_new(); 12665 gen_load_gpr(val_t, val); 12666 12667 switch (op1) { 12668 case OPC_ABSQ_S_PH_DSP: 12669 switch (op2) { 12670 case OPC_BITREV: 12671 check_dsp(ctx); 12672 gen_helper_bitrev(cpu_gpr[ret], val_t); 12673 break; 12674 case OPC_REPL_QB: 12675 check_dsp(ctx); 12676 { 12677 target_long result; 12678 imm = (ctx->opcode >> 16) & 0xFF; 12679 result = (uint32_t)imm << 24 | 12680 (uint32_t)imm << 16 | 12681 (uint32_t)imm << 8 | 12682 (uint32_t)imm; 12683 result = (int32_t)result; 12684 tcg_gen_movi_tl(cpu_gpr[ret], result); 12685 } 12686 break; 12687 case OPC_REPLV_QB: 12688 check_dsp(ctx); 12689 tcg_gen_ext8u_tl(cpu_gpr[ret], val_t); 12690 tcg_gen_shli_tl(t0, cpu_gpr[ret], 8); 12691 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12692 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); 12693 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12694 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); 12695 break; 12696 case OPC_REPL_PH: 12697 check_dsp(ctx); 12698 { 12699 imm = (ctx->opcode >> 16) & 0x03FF; 12700 imm = (int16_t)(imm << 6) >> 6; 12701 tcg_gen_movi_tl(cpu_gpr[ret], \ 12702 (target_long)((int32_t)imm << 16 | \ 12703 (uint16_t)imm)); 12704 } 12705 break; 12706 case OPC_REPLV_PH: 12707 check_dsp(ctx); 12708 tcg_gen_ext16u_tl(cpu_gpr[ret], val_t); 12709 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); 12710 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12711 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); 12712 break; 12713 } 12714 break; 12715 #ifdef TARGET_MIPS64 12716 case OPC_ABSQ_S_QH_DSP: 12717 switch (op2) { 12718 case OPC_REPL_OB: 12719 check_dsp(ctx); 12720 { 12721 target_long temp; 12722 12723 imm = (ctx->opcode >> 16) & 0xFF; 12724 temp = ((uint64_t)imm << 8) | (uint64_t)imm; 12725 temp = (temp << 16) | temp; 12726 temp = (temp << 32) | temp; 12727 tcg_gen_movi_tl(cpu_gpr[ret], temp); 12728 break; 12729 } 12730 case OPC_REPL_PW: 12731 check_dsp(ctx); 12732 { 12733 target_long temp; 12734 12735 imm = (ctx->opcode >> 16) & 0x03FF; 12736 imm = (int16_t)(imm << 6) >> 6; 12737 temp = ((target_long)imm << 32) \ 12738 | ((target_long)imm & 0xFFFFFFFF); 12739 tcg_gen_movi_tl(cpu_gpr[ret], temp); 12740 break; 12741 } 12742 case OPC_REPL_QH: 12743 check_dsp(ctx); 12744 { 12745 target_long temp; 12746 12747 imm = (ctx->opcode >> 16) & 0x03FF; 12748 imm = (int16_t)(imm << 6) >> 6; 12749 12750 temp = ((uint64_t)(uint16_t)imm << 48) | 12751 ((uint64_t)(uint16_t)imm << 32) | 12752 ((uint64_t)(uint16_t)imm << 16) | 12753 (uint64_t)(uint16_t)imm; 12754 tcg_gen_movi_tl(cpu_gpr[ret], temp); 12755 break; 12756 } 12757 case OPC_REPLV_OB: 12758 check_dsp(ctx); 12759 tcg_gen_ext8u_tl(cpu_gpr[ret], val_t); 12760 tcg_gen_shli_tl(t0, cpu_gpr[ret], 8); 12761 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12762 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); 12763 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12764 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32); 12765 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12766 break; 12767 case OPC_REPLV_PW: 12768 check_dsp(ctx); 12769 tcg_gen_ext32u_i64(cpu_gpr[ret], val_t); 12770 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32); 12771 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12772 break; 12773 case OPC_REPLV_QH: 12774 check_dsp(ctx); 12775 tcg_gen_ext16u_tl(cpu_gpr[ret], val_t); 12776 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); 12777 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12778 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32); 12779 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12780 break; 12781 } 12782 break; 12783 #endif 12784 } 12785 } 12786 12787 static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx, 12788 uint32_t op1, uint32_t op2, 12789 int ret, int v1, int v2, int check_ret) 12790 { 12791 TCGv t1; 12792 TCGv v1_t; 12793 TCGv v2_t; 12794 12795 if ((ret == 0) && (check_ret == 1)) { 12796 /* Treat as NOP. */ 12797 return; 12798 } 12799 12800 t1 = tcg_temp_new(); 12801 v1_t = tcg_temp_new(); 12802 v2_t = tcg_temp_new(); 12803 12804 gen_load_gpr(v1_t, v1); 12805 gen_load_gpr(v2_t, v2); 12806 12807 switch (op1) { 12808 case OPC_CMPU_EQ_QB_DSP: 12809 switch (op2) { 12810 case OPC_CMPU_EQ_QB: 12811 check_dsp(ctx); 12812 gen_helper_cmpu_eq_qb(v1_t, v2_t, cpu_env); 12813 break; 12814 case OPC_CMPU_LT_QB: 12815 check_dsp(ctx); 12816 gen_helper_cmpu_lt_qb(v1_t, v2_t, cpu_env); 12817 break; 12818 case OPC_CMPU_LE_QB: 12819 check_dsp(ctx); 12820 gen_helper_cmpu_le_qb(v1_t, v2_t, cpu_env); 12821 break; 12822 case OPC_CMPGU_EQ_QB: 12823 check_dsp(ctx); 12824 gen_helper_cmpgu_eq_qb(cpu_gpr[ret], v1_t, v2_t); 12825 break; 12826 case OPC_CMPGU_LT_QB: 12827 check_dsp(ctx); 12828 gen_helper_cmpgu_lt_qb(cpu_gpr[ret], v1_t, v2_t); 12829 break; 12830 case OPC_CMPGU_LE_QB: 12831 check_dsp(ctx); 12832 gen_helper_cmpgu_le_qb(cpu_gpr[ret], v1_t, v2_t); 12833 break; 12834 case OPC_CMPGDU_EQ_QB: 12835 check_dsp_r2(ctx); 12836 gen_helper_cmpgu_eq_qb(t1, v1_t, v2_t); 12837 tcg_gen_mov_tl(cpu_gpr[ret], t1); 12838 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); 12839 tcg_gen_shli_tl(t1, t1, 24); 12840 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); 12841 break; 12842 case OPC_CMPGDU_LT_QB: 12843 check_dsp_r2(ctx); 12844 gen_helper_cmpgu_lt_qb(t1, v1_t, v2_t); 12845 tcg_gen_mov_tl(cpu_gpr[ret], t1); 12846 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); 12847 tcg_gen_shli_tl(t1, t1, 24); 12848 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); 12849 break; 12850 case OPC_CMPGDU_LE_QB: 12851 check_dsp_r2(ctx); 12852 gen_helper_cmpgu_le_qb(t1, v1_t, v2_t); 12853 tcg_gen_mov_tl(cpu_gpr[ret], t1); 12854 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); 12855 tcg_gen_shli_tl(t1, t1, 24); 12856 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); 12857 break; 12858 case OPC_CMP_EQ_PH: 12859 check_dsp(ctx); 12860 gen_helper_cmp_eq_ph(v1_t, v2_t, cpu_env); 12861 break; 12862 case OPC_CMP_LT_PH: 12863 check_dsp(ctx); 12864 gen_helper_cmp_lt_ph(v1_t, v2_t, cpu_env); 12865 break; 12866 case OPC_CMP_LE_PH: 12867 check_dsp(ctx); 12868 gen_helper_cmp_le_ph(v1_t, v2_t, cpu_env); 12869 break; 12870 case OPC_PICK_QB: 12871 check_dsp(ctx); 12872 gen_helper_pick_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12873 break; 12874 case OPC_PICK_PH: 12875 check_dsp(ctx); 12876 gen_helper_pick_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12877 break; 12878 case OPC_PACKRL_PH: 12879 check_dsp(ctx); 12880 gen_helper_packrl_ph(cpu_gpr[ret], v1_t, v2_t); 12881 break; 12882 } 12883 break; 12884 #ifdef TARGET_MIPS64 12885 case OPC_CMPU_EQ_OB_DSP: 12886 switch (op2) { 12887 case OPC_CMP_EQ_PW: 12888 check_dsp(ctx); 12889 gen_helper_cmp_eq_pw(v1_t, v2_t, cpu_env); 12890 break; 12891 case OPC_CMP_LT_PW: 12892 check_dsp(ctx); 12893 gen_helper_cmp_lt_pw(v1_t, v2_t, cpu_env); 12894 break; 12895 case OPC_CMP_LE_PW: 12896 check_dsp(ctx); 12897 gen_helper_cmp_le_pw(v1_t, v2_t, cpu_env); 12898 break; 12899 case OPC_CMP_EQ_QH: 12900 check_dsp(ctx); 12901 gen_helper_cmp_eq_qh(v1_t, v2_t, cpu_env); 12902 break; 12903 case OPC_CMP_LT_QH: 12904 check_dsp(ctx); 12905 gen_helper_cmp_lt_qh(v1_t, v2_t, cpu_env); 12906 break; 12907 case OPC_CMP_LE_QH: 12908 check_dsp(ctx); 12909 gen_helper_cmp_le_qh(v1_t, v2_t, cpu_env); 12910 break; 12911 case OPC_CMPGDU_EQ_OB: 12912 check_dsp_r2(ctx); 12913 gen_helper_cmpgdu_eq_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12914 break; 12915 case OPC_CMPGDU_LT_OB: 12916 check_dsp_r2(ctx); 12917 gen_helper_cmpgdu_lt_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12918 break; 12919 case OPC_CMPGDU_LE_OB: 12920 check_dsp_r2(ctx); 12921 gen_helper_cmpgdu_le_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12922 break; 12923 case OPC_CMPGU_EQ_OB: 12924 check_dsp(ctx); 12925 gen_helper_cmpgu_eq_ob(cpu_gpr[ret], v1_t, v2_t); 12926 break; 12927 case OPC_CMPGU_LT_OB: 12928 check_dsp(ctx); 12929 gen_helper_cmpgu_lt_ob(cpu_gpr[ret], v1_t, v2_t); 12930 break; 12931 case OPC_CMPGU_LE_OB: 12932 check_dsp(ctx); 12933 gen_helper_cmpgu_le_ob(cpu_gpr[ret], v1_t, v2_t); 12934 break; 12935 case OPC_CMPU_EQ_OB: 12936 check_dsp(ctx); 12937 gen_helper_cmpu_eq_ob(v1_t, v2_t, cpu_env); 12938 break; 12939 case OPC_CMPU_LT_OB: 12940 check_dsp(ctx); 12941 gen_helper_cmpu_lt_ob(v1_t, v2_t, cpu_env); 12942 break; 12943 case OPC_CMPU_LE_OB: 12944 check_dsp(ctx); 12945 gen_helper_cmpu_le_ob(v1_t, v2_t, cpu_env); 12946 break; 12947 case OPC_PACKRL_PW: 12948 check_dsp(ctx); 12949 gen_helper_packrl_pw(cpu_gpr[ret], v1_t, v2_t); 12950 break; 12951 case OPC_PICK_OB: 12952 check_dsp(ctx); 12953 gen_helper_pick_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12954 break; 12955 case OPC_PICK_PW: 12956 check_dsp(ctx); 12957 gen_helper_pick_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12958 break; 12959 case OPC_PICK_QH: 12960 check_dsp(ctx); 12961 gen_helper_pick_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12962 break; 12963 } 12964 break; 12965 #endif 12966 } 12967 } 12968 12969 static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx, 12970 uint32_t op1, int rt, int rs, int sa) 12971 { 12972 TCGv t0; 12973 12974 check_dsp_r2(ctx); 12975 12976 if (rt == 0) { 12977 /* Treat as NOP. */ 12978 return; 12979 } 12980 12981 t0 = tcg_temp_new(); 12982 gen_load_gpr(t0, rs); 12983 12984 switch (op1) { 12985 case OPC_APPEND_DSP: 12986 switch (MASK_APPEND(ctx->opcode)) { 12987 case OPC_APPEND: 12988 if (sa != 0) { 12989 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 32 - sa); 12990 } 12991 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 12992 break; 12993 case OPC_PREPEND: 12994 if (sa != 0) { 12995 tcg_gen_ext32u_tl(cpu_gpr[rt], cpu_gpr[rt]); 12996 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], sa); 12997 tcg_gen_shli_tl(t0, t0, 32 - sa); 12998 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); 12999 } 13000 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 13001 break; 13002 case OPC_BALIGN: 13003 sa &= 3; 13004 if (sa != 0 && sa != 2) { 13005 tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa); 13006 tcg_gen_ext32u_tl(t0, t0); 13007 tcg_gen_shri_tl(t0, t0, 8 * (4 - sa)); 13008 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); 13009 } 13010 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 13011 break; 13012 default: /* Invalid */ 13013 MIPS_INVAL("MASK APPEND"); 13014 gen_reserved_instruction(ctx); 13015 break; 13016 } 13017 break; 13018 #ifdef TARGET_MIPS64 13019 case OPC_DAPPEND_DSP: 13020 switch (MASK_DAPPEND(ctx->opcode)) { 13021 case OPC_DAPPEND: 13022 if (sa != 0) { 13023 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 64 - sa); 13024 } 13025 break; 13026 case OPC_PREPENDD: 13027 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], 0x20 | sa); 13028 tcg_gen_shli_tl(t0, t0, 64 - (0x20 | sa)); 13029 tcg_gen_or_tl(cpu_gpr[rt], t0, t0); 13030 break; 13031 case OPC_PREPENDW: 13032 if (sa != 0) { 13033 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], sa); 13034 tcg_gen_shli_tl(t0, t0, 64 - sa); 13035 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); 13036 } 13037 break; 13038 case OPC_DBALIGN: 13039 sa &= 7; 13040 if (sa != 0 && sa != 2 && sa != 4) { 13041 tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa); 13042 tcg_gen_shri_tl(t0, t0, 8 * (8 - sa)); 13043 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); 13044 } 13045 break; 13046 default: /* Invalid */ 13047 MIPS_INVAL("MASK DAPPEND"); 13048 gen_reserved_instruction(ctx); 13049 break; 13050 } 13051 break; 13052 #endif 13053 } 13054 } 13055 13056 static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, 13057 int ret, int v1, int v2, int check_ret) 13058 13059 { 13060 TCGv t0; 13061 TCGv t1; 13062 TCGv v1_t; 13063 int16_t imm; 13064 13065 if ((ret == 0) && (check_ret == 1)) { 13066 /* Treat as NOP. */ 13067 return; 13068 } 13069 13070 t0 = tcg_temp_new(); 13071 t1 = tcg_temp_new(); 13072 v1_t = tcg_temp_new(); 13073 13074 gen_load_gpr(v1_t, v1); 13075 13076 switch (op1) { 13077 case OPC_EXTR_W_DSP: 13078 check_dsp(ctx); 13079 switch (op2) { 13080 case OPC_EXTR_W: 13081 tcg_gen_movi_tl(t0, v2); 13082 tcg_gen_movi_tl(t1, v1); 13083 gen_helper_extr_w(cpu_gpr[ret], t0, t1, cpu_env); 13084 break; 13085 case OPC_EXTR_R_W: 13086 tcg_gen_movi_tl(t0, v2); 13087 tcg_gen_movi_tl(t1, v1); 13088 gen_helper_extr_r_w(cpu_gpr[ret], t0, t1, cpu_env); 13089 break; 13090 case OPC_EXTR_RS_W: 13091 tcg_gen_movi_tl(t0, v2); 13092 tcg_gen_movi_tl(t1, v1); 13093 gen_helper_extr_rs_w(cpu_gpr[ret], t0, t1, cpu_env); 13094 break; 13095 case OPC_EXTR_S_H: 13096 tcg_gen_movi_tl(t0, v2); 13097 tcg_gen_movi_tl(t1, v1); 13098 gen_helper_extr_s_h(cpu_gpr[ret], t0, t1, cpu_env); 13099 break; 13100 case OPC_EXTRV_S_H: 13101 tcg_gen_movi_tl(t0, v2); 13102 gen_helper_extr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env); 13103 break; 13104 case OPC_EXTRV_W: 13105 tcg_gen_movi_tl(t0, v2); 13106 gen_helper_extr_w(cpu_gpr[ret], t0, v1_t, cpu_env); 13107 break; 13108 case OPC_EXTRV_R_W: 13109 tcg_gen_movi_tl(t0, v2); 13110 gen_helper_extr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env); 13111 break; 13112 case OPC_EXTRV_RS_W: 13113 tcg_gen_movi_tl(t0, v2); 13114 gen_helper_extr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env); 13115 break; 13116 case OPC_EXTP: 13117 tcg_gen_movi_tl(t0, v2); 13118 tcg_gen_movi_tl(t1, v1); 13119 gen_helper_extp(cpu_gpr[ret], t0, t1, cpu_env); 13120 break; 13121 case OPC_EXTPV: 13122 tcg_gen_movi_tl(t0, v2); 13123 gen_helper_extp(cpu_gpr[ret], t0, v1_t, cpu_env); 13124 break; 13125 case OPC_EXTPDP: 13126 tcg_gen_movi_tl(t0, v2); 13127 tcg_gen_movi_tl(t1, v1); 13128 gen_helper_extpdp(cpu_gpr[ret], t0, t1, cpu_env); 13129 break; 13130 case OPC_EXTPDPV: 13131 tcg_gen_movi_tl(t0, v2); 13132 gen_helper_extpdp(cpu_gpr[ret], t0, v1_t, cpu_env); 13133 break; 13134 case OPC_SHILO: 13135 imm = (ctx->opcode >> 20) & 0x3F; 13136 tcg_gen_movi_tl(t0, ret); 13137 tcg_gen_movi_tl(t1, imm); 13138 gen_helper_shilo(t0, t1, cpu_env); 13139 break; 13140 case OPC_SHILOV: 13141 tcg_gen_movi_tl(t0, ret); 13142 gen_helper_shilo(t0, v1_t, cpu_env); 13143 break; 13144 case OPC_MTHLIP: 13145 tcg_gen_movi_tl(t0, ret); 13146 gen_helper_mthlip(t0, v1_t, cpu_env); 13147 break; 13148 case OPC_WRDSP: 13149 imm = (ctx->opcode >> 11) & 0x3FF; 13150 tcg_gen_movi_tl(t0, imm); 13151 gen_helper_wrdsp(v1_t, t0, cpu_env); 13152 break; 13153 case OPC_RDDSP: 13154 imm = (ctx->opcode >> 16) & 0x03FF; 13155 tcg_gen_movi_tl(t0, imm); 13156 gen_helper_rddsp(cpu_gpr[ret], t0, cpu_env); 13157 break; 13158 } 13159 break; 13160 #ifdef TARGET_MIPS64 13161 case OPC_DEXTR_W_DSP: 13162 check_dsp(ctx); 13163 switch (op2) { 13164 case OPC_DMTHLIP: 13165 tcg_gen_movi_tl(t0, ret); 13166 gen_helper_dmthlip(v1_t, t0, cpu_env); 13167 break; 13168 case OPC_DSHILO: 13169 { 13170 int shift = (ctx->opcode >> 19) & 0x7F; 13171 int ac = (ctx->opcode >> 11) & 0x03; 13172 tcg_gen_movi_tl(t0, shift); 13173 tcg_gen_movi_tl(t1, ac); 13174 gen_helper_dshilo(t0, t1, cpu_env); 13175 break; 13176 } 13177 case OPC_DSHILOV: 13178 { 13179 int ac = (ctx->opcode >> 11) & 0x03; 13180 tcg_gen_movi_tl(t0, ac); 13181 gen_helper_dshilo(v1_t, t0, cpu_env); 13182 break; 13183 } 13184 case OPC_DEXTP: 13185 tcg_gen_movi_tl(t0, v2); 13186 tcg_gen_movi_tl(t1, v1); 13187 13188 gen_helper_dextp(cpu_gpr[ret], t0, t1, cpu_env); 13189 break; 13190 case OPC_DEXTPV: 13191 tcg_gen_movi_tl(t0, v2); 13192 gen_helper_dextp(cpu_gpr[ret], t0, v1_t, cpu_env); 13193 break; 13194 case OPC_DEXTPDP: 13195 tcg_gen_movi_tl(t0, v2); 13196 tcg_gen_movi_tl(t1, v1); 13197 gen_helper_dextpdp(cpu_gpr[ret], t0, t1, cpu_env); 13198 break; 13199 case OPC_DEXTPDPV: 13200 tcg_gen_movi_tl(t0, v2); 13201 gen_helper_dextpdp(cpu_gpr[ret], t0, v1_t, cpu_env); 13202 break; 13203 case OPC_DEXTR_L: 13204 tcg_gen_movi_tl(t0, v2); 13205 tcg_gen_movi_tl(t1, v1); 13206 gen_helper_dextr_l(cpu_gpr[ret], t0, t1, cpu_env); 13207 break; 13208 case OPC_DEXTR_R_L: 13209 tcg_gen_movi_tl(t0, v2); 13210 tcg_gen_movi_tl(t1, v1); 13211 gen_helper_dextr_r_l(cpu_gpr[ret], t0, t1, cpu_env); 13212 break; 13213 case OPC_DEXTR_RS_L: 13214 tcg_gen_movi_tl(t0, v2); 13215 tcg_gen_movi_tl(t1, v1); 13216 gen_helper_dextr_rs_l(cpu_gpr[ret], t0, t1, cpu_env); 13217 break; 13218 case OPC_DEXTR_W: 13219 tcg_gen_movi_tl(t0, v2); 13220 tcg_gen_movi_tl(t1, v1); 13221 gen_helper_dextr_w(cpu_gpr[ret], t0, t1, cpu_env); 13222 break; 13223 case OPC_DEXTR_R_W: 13224 tcg_gen_movi_tl(t0, v2); 13225 tcg_gen_movi_tl(t1, v1); 13226 gen_helper_dextr_r_w(cpu_gpr[ret], t0, t1, cpu_env); 13227 break; 13228 case OPC_DEXTR_RS_W: 13229 tcg_gen_movi_tl(t0, v2); 13230 tcg_gen_movi_tl(t1, v1); 13231 gen_helper_dextr_rs_w(cpu_gpr[ret], t0, t1, cpu_env); 13232 break; 13233 case OPC_DEXTR_S_H: 13234 tcg_gen_movi_tl(t0, v2); 13235 tcg_gen_movi_tl(t1, v1); 13236 gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env); 13237 break; 13238 case OPC_DEXTRV_S_H: 13239 tcg_gen_movi_tl(t0, v2); 13240 gen_helper_dextr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env); 13241 break; 13242 case OPC_DEXTRV_L: 13243 tcg_gen_movi_tl(t0, v2); 13244 gen_helper_dextr_l(cpu_gpr[ret], t0, v1_t, cpu_env); 13245 break; 13246 case OPC_DEXTRV_R_L: 13247 tcg_gen_movi_tl(t0, v2); 13248 gen_helper_dextr_r_l(cpu_gpr[ret], t0, v1_t, cpu_env); 13249 break; 13250 case OPC_DEXTRV_RS_L: 13251 tcg_gen_movi_tl(t0, v2); 13252 gen_helper_dextr_rs_l(cpu_gpr[ret], t0, v1_t, cpu_env); 13253 break; 13254 case OPC_DEXTRV_W: 13255 tcg_gen_movi_tl(t0, v2); 13256 gen_helper_dextr_w(cpu_gpr[ret], t0, v1_t, cpu_env); 13257 break; 13258 case OPC_DEXTRV_R_W: 13259 tcg_gen_movi_tl(t0, v2); 13260 gen_helper_dextr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env); 13261 break; 13262 case OPC_DEXTRV_RS_W: 13263 tcg_gen_movi_tl(t0, v2); 13264 gen_helper_dextr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env); 13265 break; 13266 } 13267 break; 13268 #endif 13269 } 13270 } 13271 13272 /* End MIPSDSP functions. */ 13273 13274 static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) 13275 { 13276 int rs, rt, rd, sa; 13277 uint32_t op1, op2; 13278 13279 rs = (ctx->opcode >> 21) & 0x1f; 13280 rt = (ctx->opcode >> 16) & 0x1f; 13281 rd = (ctx->opcode >> 11) & 0x1f; 13282 sa = (ctx->opcode >> 6) & 0x1f; 13283 13284 op1 = MASK_SPECIAL(ctx->opcode); 13285 switch (op1) { 13286 case OPC_MULT: 13287 case OPC_MULTU: 13288 case OPC_DIV: 13289 case OPC_DIVU: 13290 op2 = MASK_R6_MULDIV(ctx->opcode); 13291 switch (op2) { 13292 case R6_OPC_MUL: 13293 case R6_OPC_MUH: 13294 case R6_OPC_MULU: 13295 case R6_OPC_MUHU: 13296 case R6_OPC_DIV: 13297 case R6_OPC_MOD: 13298 case R6_OPC_DIVU: 13299 case R6_OPC_MODU: 13300 gen_r6_muldiv(ctx, op2, rd, rs, rt); 13301 break; 13302 default: 13303 MIPS_INVAL("special_r6 muldiv"); 13304 gen_reserved_instruction(ctx); 13305 break; 13306 } 13307 break; 13308 case OPC_SELEQZ: 13309 case OPC_SELNEZ: 13310 gen_cond_move(ctx, op1, rd, rs, rt); 13311 break; 13312 case R6_OPC_CLO: 13313 case R6_OPC_CLZ: 13314 if (rt == 0 && sa == 1) { 13315 /* 13316 * Major opcode and function field is shared with preR6 MFHI/MTHI. 13317 * We need additionally to check other fields. 13318 */ 13319 gen_cl(ctx, op1, rd, rs); 13320 } else { 13321 gen_reserved_instruction(ctx); 13322 } 13323 break; 13324 case R6_OPC_SDBBP: 13325 if (is_uhi(ctx, extract32(ctx->opcode, 6, 20))) { 13326 ctx->base.is_jmp = DISAS_SEMIHOST; 13327 } else { 13328 if (ctx->hflags & MIPS_HFLAG_SBRI) { 13329 gen_reserved_instruction(ctx); 13330 } else { 13331 generate_exception_end(ctx, EXCP_DBp); 13332 } 13333 } 13334 break; 13335 #if defined(TARGET_MIPS64) 13336 case R6_OPC_DCLO: 13337 case R6_OPC_DCLZ: 13338 if (rt == 0 && sa == 1) { 13339 /* 13340 * Major opcode and function field is shared with preR6 MFHI/MTHI. 13341 * We need additionally to check other fields. 13342 */ 13343 check_mips_64(ctx); 13344 gen_cl(ctx, op1, rd, rs); 13345 } else { 13346 gen_reserved_instruction(ctx); 13347 } 13348 break; 13349 case OPC_DMULT: 13350 case OPC_DMULTU: 13351 case OPC_DDIV: 13352 case OPC_DDIVU: 13353 13354 op2 = MASK_R6_MULDIV(ctx->opcode); 13355 switch (op2) { 13356 case R6_OPC_DMUL: 13357 case R6_OPC_DMUH: 13358 case R6_OPC_DMULU: 13359 case R6_OPC_DMUHU: 13360 case R6_OPC_DDIV: 13361 case R6_OPC_DMOD: 13362 case R6_OPC_DDIVU: 13363 case R6_OPC_DMODU: 13364 check_mips_64(ctx); 13365 gen_r6_muldiv(ctx, op2, rd, rs, rt); 13366 break; 13367 default: 13368 MIPS_INVAL("special_r6 muldiv"); 13369 gen_reserved_instruction(ctx); 13370 break; 13371 } 13372 break; 13373 #endif 13374 default: /* Invalid */ 13375 MIPS_INVAL("special_r6"); 13376 gen_reserved_instruction(ctx); 13377 break; 13378 } 13379 } 13380 13381 static void decode_opc_special_tx79(CPUMIPSState *env, DisasContext *ctx) 13382 { 13383 int rs = extract32(ctx->opcode, 21, 5); 13384 int rt = extract32(ctx->opcode, 16, 5); 13385 int rd = extract32(ctx->opcode, 11, 5); 13386 uint32_t op1 = MASK_SPECIAL(ctx->opcode); 13387 13388 switch (op1) { 13389 case OPC_MOVN: /* Conditional move */ 13390 case OPC_MOVZ: 13391 gen_cond_move(ctx, op1, rd, rs, rt); 13392 break; 13393 case OPC_MFHI: /* Move from HI/LO */ 13394 case OPC_MFLO: 13395 gen_HILO(ctx, op1, 0, rd); 13396 break; 13397 case OPC_MTHI: 13398 case OPC_MTLO: /* Move to HI/LO */ 13399 gen_HILO(ctx, op1, 0, rs); 13400 break; 13401 case OPC_MULT: 13402 case OPC_MULTU: 13403 gen_mul_txx9(ctx, op1, rd, rs, rt); 13404 break; 13405 case OPC_DIV: 13406 case OPC_DIVU: 13407 gen_muldiv(ctx, op1, 0, rs, rt); 13408 break; 13409 #if defined(TARGET_MIPS64) 13410 case OPC_DMULT: 13411 case OPC_DMULTU: 13412 case OPC_DDIV: 13413 case OPC_DDIVU: 13414 check_insn_opc_user_only(ctx, INSN_R5900); 13415 gen_muldiv(ctx, op1, 0, rs, rt); 13416 break; 13417 #endif 13418 case OPC_JR: 13419 gen_compute_branch(ctx, op1, 4, rs, 0, 0, 4); 13420 break; 13421 default: /* Invalid */ 13422 MIPS_INVAL("special_tx79"); 13423 gen_reserved_instruction(ctx); 13424 break; 13425 } 13426 } 13427 13428 static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) 13429 { 13430 int rs, rt, rd; 13431 uint32_t op1; 13432 13433 rs = (ctx->opcode >> 21) & 0x1f; 13434 rt = (ctx->opcode >> 16) & 0x1f; 13435 rd = (ctx->opcode >> 11) & 0x1f; 13436 13437 op1 = MASK_SPECIAL(ctx->opcode); 13438 switch (op1) { 13439 case OPC_MOVN: /* Conditional move */ 13440 case OPC_MOVZ: 13441 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | 13442 INSN_LOONGSON2E | INSN_LOONGSON2F); 13443 gen_cond_move(ctx, op1, rd, rs, rt); 13444 break; 13445 case OPC_MFHI: /* Move from HI/LO */ 13446 case OPC_MFLO: 13447 gen_HILO(ctx, op1, rs & 3, rd); 13448 break; 13449 case OPC_MTHI: 13450 case OPC_MTLO: /* Move to HI/LO */ 13451 gen_HILO(ctx, op1, rd & 3, rs); 13452 break; 13453 case OPC_MOVCI: 13454 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); 13455 if (env->CP0_Config1 & (1 << CP0C1_FP)) { 13456 check_cp1_enabled(ctx); 13457 gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7, 13458 (ctx->opcode >> 16) & 1); 13459 } else { 13460 generate_exception_err(ctx, EXCP_CpU, 1); 13461 } 13462 break; 13463 case OPC_MULT: 13464 case OPC_MULTU: 13465 gen_muldiv(ctx, op1, rd & 3, rs, rt); 13466 break; 13467 case OPC_DIV: 13468 case OPC_DIVU: 13469 gen_muldiv(ctx, op1, 0, rs, rt); 13470 break; 13471 #if defined(TARGET_MIPS64) 13472 case OPC_DMULT: 13473 case OPC_DMULTU: 13474 case OPC_DDIV: 13475 case OPC_DDIVU: 13476 check_insn(ctx, ISA_MIPS3); 13477 check_mips_64(ctx); 13478 gen_muldiv(ctx, op1, 0, rs, rt); 13479 break; 13480 #endif 13481 case OPC_JR: 13482 gen_compute_branch(ctx, op1, 4, rs, 0, 0, 4); 13483 break; 13484 case OPC_SPIM: 13485 #ifdef MIPS_STRICT_STANDARD 13486 MIPS_INVAL("SPIM"); 13487 gen_reserved_instruction(ctx); 13488 #else 13489 /* Implemented as RI exception for now. */ 13490 MIPS_INVAL("spim (unofficial)"); 13491 gen_reserved_instruction(ctx); 13492 #endif 13493 break; 13494 default: /* Invalid */ 13495 MIPS_INVAL("special_legacy"); 13496 gen_reserved_instruction(ctx); 13497 break; 13498 } 13499 } 13500 13501 static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) 13502 { 13503 int rs, rt, rd, sa; 13504 uint32_t op1; 13505 13506 rs = (ctx->opcode >> 21) & 0x1f; 13507 rt = (ctx->opcode >> 16) & 0x1f; 13508 rd = (ctx->opcode >> 11) & 0x1f; 13509 sa = (ctx->opcode >> 6) & 0x1f; 13510 13511 op1 = MASK_SPECIAL(ctx->opcode); 13512 switch (op1) { 13513 case OPC_SLL: /* Shift with immediate */ 13514 if (sa == 5 && rd == 0 && 13515 rs == 0 && rt == 0) { /* PAUSE */ 13516 if ((ctx->insn_flags & ISA_MIPS_R6) && 13517 (ctx->hflags & MIPS_HFLAG_BMASK)) { 13518 gen_reserved_instruction(ctx); 13519 break; 13520 } 13521 } 13522 /* Fallthrough */ 13523 case OPC_SRA: 13524 gen_shift_imm(ctx, op1, rd, rt, sa); 13525 break; 13526 case OPC_SRL: 13527 switch ((ctx->opcode >> 21) & 0x1f) { 13528 case 1: 13529 /* rotr is decoded as srl on non-R2 CPUs */ 13530 if (ctx->insn_flags & ISA_MIPS_R2) { 13531 op1 = OPC_ROTR; 13532 } 13533 /* Fallthrough */ 13534 case 0: 13535 gen_shift_imm(ctx, op1, rd, rt, sa); 13536 break; 13537 default: 13538 gen_reserved_instruction(ctx); 13539 break; 13540 } 13541 break; 13542 case OPC_ADD: 13543 case OPC_ADDU: 13544 case OPC_SUB: 13545 case OPC_SUBU: 13546 gen_arith(ctx, op1, rd, rs, rt); 13547 break; 13548 case OPC_SLLV: /* Shifts */ 13549 case OPC_SRAV: 13550 gen_shift(ctx, op1, rd, rs, rt); 13551 break; 13552 case OPC_SRLV: 13553 switch ((ctx->opcode >> 6) & 0x1f) { 13554 case 1: 13555 /* rotrv is decoded as srlv on non-R2 CPUs */ 13556 if (ctx->insn_flags & ISA_MIPS_R2) { 13557 op1 = OPC_ROTRV; 13558 } 13559 /* Fallthrough */ 13560 case 0: 13561 gen_shift(ctx, op1, rd, rs, rt); 13562 break; 13563 default: 13564 gen_reserved_instruction(ctx); 13565 break; 13566 } 13567 break; 13568 case OPC_SLT: /* Set on less than */ 13569 case OPC_SLTU: 13570 gen_slt(ctx, op1, rd, rs, rt); 13571 break; 13572 case OPC_AND: /* Logic*/ 13573 case OPC_OR: 13574 case OPC_NOR: 13575 case OPC_XOR: 13576 gen_logic(ctx, op1, rd, rs, rt); 13577 break; 13578 case OPC_JALR: 13579 gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4); 13580 break; 13581 case OPC_TGE: /* Traps */ 13582 case OPC_TGEU: 13583 case OPC_TLT: 13584 case OPC_TLTU: 13585 case OPC_TEQ: 13586 case OPC_TNE: 13587 check_insn(ctx, ISA_MIPS2); 13588 gen_trap(ctx, op1, rs, rt, -1, extract32(ctx->opcode, 6, 10)); 13589 break; 13590 case OPC_PMON: 13591 /* Pmon entry point, also R4010 selsl */ 13592 #ifdef MIPS_STRICT_STANDARD 13593 MIPS_INVAL("PMON / selsl"); 13594 gen_reserved_instruction(ctx); 13595 #else 13596 gen_helper_pmon(cpu_env, tcg_constant_i32(sa)); 13597 #endif 13598 break; 13599 case OPC_SYSCALL: 13600 generate_exception_end(ctx, EXCP_SYSCALL); 13601 break; 13602 case OPC_BREAK: 13603 generate_exception_break(ctx, extract32(ctx->opcode, 6, 20)); 13604 break; 13605 case OPC_SYNC: 13606 check_insn(ctx, ISA_MIPS2); 13607 gen_sync(extract32(ctx->opcode, 6, 5)); 13608 break; 13609 13610 #if defined(TARGET_MIPS64) 13611 /* MIPS64 specific opcodes */ 13612 case OPC_DSLL: 13613 case OPC_DSRA: 13614 case OPC_DSLL32: 13615 case OPC_DSRA32: 13616 check_insn(ctx, ISA_MIPS3); 13617 check_mips_64(ctx); 13618 gen_shift_imm(ctx, op1, rd, rt, sa); 13619 break; 13620 case OPC_DSRL: 13621 switch ((ctx->opcode >> 21) & 0x1f) { 13622 case 1: 13623 /* drotr is decoded as dsrl on non-R2 CPUs */ 13624 if (ctx->insn_flags & ISA_MIPS_R2) { 13625 op1 = OPC_DROTR; 13626 } 13627 /* Fallthrough */ 13628 case 0: 13629 check_insn(ctx, ISA_MIPS3); 13630 check_mips_64(ctx); 13631 gen_shift_imm(ctx, op1, rd, rt, sa); 13632 break; 13633 default: 13634 gen_reserved_instruction(ctx); 13635 break; 13636 } 13637 break; 13638 case OPC_DSRL32: 13639 switch ((ctx->opcode >> 21) & 0x1f) { 13640 case 1: 13641 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */ 13642 if (ctx->insn_flags & ISA_MIPS_R2) { 13643 op1 = OPC_DROTR32; 13644 } 13645 /* Fallthrough */ 13646 case 0: 13647 check_insn(ctx, ISA_MIPS3); 13648 check_mips_64(ctx); 13649 gen_shift_imm(ctx, op1, rd, rt, sa); 13650 break; 13651 default: 13652 gen_reserved_instruction(ctx); 13653 break; 13654 } 13655 break; 13656 case OPC_DADD: 13657 case OPC_DADDU: 13658 case OPC_DSUB: 13659 case OPC_DSUBU: 13660 check_insn(ctx, ISA_MIPS3); 13661 check_mips_64(ctx); 13662 gen_arith(ctx, op1, rd, rs, rt); 13663 break; 13664 case OPC_DSLLV: 13665 case OPC_DSRAV: 13666 check_insn(ctx, ISA_MIPS3); 13667 check_mips_64(ctx); 13668 gen_shift(ctx, op1, rd, rs, rt); 13669 break; 13670 case OPC_DSRLV: 13671 switch ((ctx->opcode >> 6) & 0x1f) { 13672 case 1: 13673 /* drotrv is decoded as dsrlv on non-R2 CPUs */ 13674 if (ctx->insn_flags & ISA_MIPS_R2) { 13675 op1 = OPC_DROTRV; 13676 } 13677 /* Fallthrough */ 13678 case 0: 13679 check_insn(ctx, ISA_MIPS3); 13680 check_mips_64(ctx); 13681 gen_shift(ctx, op1, rd, rs, rt); 13682 break; 13683 default: 13684 gen_reserved_instruction(ctx); 13685 break; 13686 } 13687 break; 13688 #endif 13689 default: 13690 if (ctx->insn_flags & ISA_MIPS_R6) { 13691 decode_opc_special_r6(env, ctx); 13692 } else if (ctx->insn_flags & INSN_R5900) { 13693 decode_opc_special_tx79(env, ctx); 13694 } else { 13695 decode_opc_special_legacy(env, ctx); 13696 } 13697 } 13698 } 13699 13700 13701 static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) 13702 { 13703 int rs, rt, rd; 13704 uint32_t op1; 13705 13706 rs = (ctx->opcode >> 21) & 0x1f; 13707 rt = (ctx->opcode >> 16) & 0x1f; 13708 rd = (ctx->opcode >> 11) & 0x1f; 13709 13710 op1 = MASK_SPECIAL2(ctx->opcode); 13711 switch (op1) { 13712 case OPC_MADD: /* Multiply and add/sub */ 13713 case OPC_MADDU: 13714 case OPC_MSUB: 13715 case OPC_MSUBU: 13716 check_insn(ctx, ISA_MIPS_R1); 13717 gen_muldiv(ctx, op1, rd & 3, rs, rt); 13718 break; 13719 case OPC_MUL: 13720 gen_arith(ctx, op1, rd, rs, rt); 13721 break; 13722 case OPC_DIV_G_2F: 13723 case OPC_DIVU_G_2F: 13724 case OPC_MULT_G_2F: 13725 case OPC_MULTU_G_2F: 13726 case OPC_MOD_G_2F: 13727 case OPC_MODU_G_2F: 13728 check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); 13729 gen_loongson_integer(ctx, op1, rd, rs, rt); 13730 break; 13731 case OPC_CLO: 13732 case OPC_CLZ: 13733 check_insn(ctx, ISA_MIPS_R1); 13734 gen_cl(ctx, op1, rd, rs); 13735 break; 13736 case OPC_SDBBP: 13737 if (is_uhi(ctx, extract32(ctx->opcode, 6, 20))) { 13738 ctx->base.is_jmp = DISAS_SEMIHOST; 13739 } else { 13740 /* 13741 * XXX: not clear which exception should be raised 13742 * when in debug mode... 13743 */ 13744 check_insn(ctx, ISA_MIPS_R1); 13745 generate_exception_end(ctx, EXCP_DBp); 13746 } 13747 break; 13748 #if defined(TARGET_MIPS64) 13749 case OPC_DCLO: 13750 case OPC_DCLZ: 13751 check_insn(ctx, ISA_MIPS_R1); 13752 check_mips_64(ctx); 13753 gen_cl(ctx, op1, rd, rs); 13754 break; 13755 case OPC_DMULT_G_2F: 13756 case OPC_DMULTU_G_2F: 13757 case OPC_DDIV_G_2F: 13758 case OPC_DDIVU_G_2F: 13759 case OPC_DMOD_G_2F: 13760 case OPC_DMODU_G_2F: 13761 check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); 13762 gen_loongson_integer(ctx, op1, rd, rs, rt); 13763 break; 13764 #endif 13765 default: /* Invalid */ 13766 MIPS_INVAL("special2_legacy"); 13767 gen_reserved_instruction(ctx); 13768 break; 13769 } 13770 } 13771 13772 static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) 13773 { 13774 int rs, rt, rd, sa; 13775 uint32_t op1, op2; 13776 int16_t imm; 13777 13778 rs = (ctx->opcode >> 21) & 0x1f; 13779 rt = (ctx->opcode >> 16) & 0x1f; 13780 rd = (ctx->opcode >> 11) & 0x1f; 13781 sa = (ctx->opcode >> 6) & 0x1f; 13782 imm = (int16_t)ctx->opcode >> 7; 13783 13784 op1 = MASK_SPECIAL3(ctx->opcode); 13785 switch (op1) { 13786 case R6_OPC_PREF: 13787 if (rt >= 24) { 13788 /* hint codes 24-31 are reserved and signal RI */ 13789 gen_reserved_instruction(ctx); 13790 } 13791 /* Treat as NOP. */ 13792 break; 13793 case R6_OPC_CACHE: 13794 check_cp0_enabled(ctx); 13795 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { 13796 gen_cache_operation(ctx, rt, rs, imm); 13797 } 13798 break; 13799 case R6_OPC_SC: 13800 gen_st_cond(ctx, rt, rs, imm, MO_TESL, false); 13801 break; 13802 case R6_OPC_LL: 13803 gen_ld(ctx, op1, rt, rs, imm); 13804 break; 13805 case OPC_BSHFL: 13806 { 13807 if (rd == 0) { 13808 /* Treat as NOP. */ 13809 break; 13810 } 13811 op2 = MASK_BSHFL(ctx->opcode); 13812 switch (op2) { 13813 case OPC_ALIGN: 13814 case OPC_ALIGN_1: 13815 case OPC_ALIGN_2: 13816 case OPC_ALIGN_3: 13817 gen_align(ctx, 32, rd, rs, rt, sa & 3); 13818 break; 13819 case OPC_BITSWAP: 13820 gen_bitswap(ctx, op2, rd, rt); 13821 break; 13822 } 13823 } 13824 break; 13825 #ifndef CONFIG_USER_ONLY 13826 case OPC_GINV: 13827 if (unlikely(ctx->gi <= 1)) { 13828 gen_reserved_instruction(ctx); 13829 } 13830 check_cp0_enabled(ctx); 13831 switch ((ctx->opcode >> 6) & 3) { 13832 case 0: /* GINVI */ 13833 /* Treat as NOP. */ 13834 break; 13835 case 2: /* GINVT */ 13836 gen_helper_0e1i(ginvt, cpu_gpr[rs], extract32(ctx->opcode, 8, 2)); 13837 break; 13838 default: 13839 gen_reserved_instruction(ctx); 13840 break; 13841 } 13842 break; 13843 #endif 13844 #if defined(TARGET_MIPS64) 13845 case R6_OPC_SCD: 13846 gen_st_cond(ctx, rt, rs, imm, MO_TEUQ, false); 13847 break; 13848 case R6_OPC_LLD: 13849 gen_ld(ctx, op1, rt, rs, imm); 13850 break; 13851 case OPC_DBSHFL: 13852 check_mips_64(ctx); 13853 { 13854 if (rd == 0) { 13855 /* Treat as NOP. */ 13856 break; 13857 } 13858 op2 = MASK_DBSHFL(ctx->opcode); 13859 switch (op2) { 13860 case OPC_DALIGN: 13861 case OPC_DALIGN_1: 13862 case OPC_DALIGN_2: 13863 case OPC_DALIGN_3: 13864 case OPC_DALIGN_4: 13865 case OPC_DALIGN_5: 13866 case OPC_DALIGN_6: 13867 case OPC_DALIGN_7: 13868 gen_align(ctx, 64, rd, rs, rt, sa & 7); 13869 break; 13870 case OPC_DBITSWAP: 13871 gen_bitswap(ctx, op2, rd, rt); 13872 break; 13873 } 13874 13875 } 13876 break; 13877 #endif 13878 default: /* Invalid */ 13879 MIPS_INVAL("special3_r6"); 13880 gen_reserved_instruction(ctx); 13881 break; 13882 } 13883 } 13884 13885 static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) 13886 { 13887 int rs, rt, rd; 13888 uint32_t op1, op2; 13889 13890 rs = (ctx->opcode >> 21) & 0x1f; 13891 rt = (ctx->opcode >> 16) & 0x1f; 13892 rd = (ctx->opcode >> 11) & 0x1f; 13893 13894 op1 = MASK_SPECIAL3(ctx->opcode); 13895 switch (op1) { 13896 case OPC_DIV_G_2E: 13897 case OPC_DIVU_G_2E: 13898 case OPC_MOD_G_2E: 13899 case OPC_MODU_G_2E: 13900 case OPC_MULT_G_2E: 13901 case OPC_MULTU_G_2E: 13902 /* 13903 * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have 13904 * the same mask and op1. 13905 */ 13906 if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MULT_G_2E)) { 13907 op2 = MASK_ADDUH_QB(ctx->opcode); 13908 switch (op2) { 13909 case OPC_ADDUH_QB: 13910 case OPC_ADDUH_R_QB: 13911 case OPC_ADDQH_PH: 13912 case OPC_ADDQH_R_PH: 13913 case OPC_ADDQH_W: 13914 case OPC_ADDQH_R_W: 13915 case OPC_SUBUH_QB: 13916 case OPC_SUBUH_R_QB: 13917 case OPC_SUBQH_PH: 13918 case OPC_SUBQH_R_PH: 13919 case OPC_SUBQH_W: 13920 case OPC_SUBQH_R_W: 13921 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 13922 break; 13923 case OPC_MUL_PH: 13924 case OPC_MUL_S_PH: 13925 case OPC_MULQ_S_W: 13926 case OPC_MULQ_RS_W: 13927 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1); 13928 break; 13929 default: 13930 MIPS_INVAL("MASK ADDUH.QB"); 13931 gen_reserved_instruction(ctx); 13932 break; 13933 } 13934 } else if (ctx->insn_flags & INSN_LOONGSON2E) { 13935 gen_loongson_integer(ctx, op1, rd, rs, rt); 13936 } else { 13937 gen_reserved_instruction(ctx); 13938 } 13939 break; 13940 case OPC_LX_DSP: 13941 op2 = MASK_LX(ctx->opcode); 13942 switch (op2) { 13943 #if defined(TARGET_MIPS64) 13944 case OPC_LDX: 13945 #endif 13946 case OPC_LBUX: 13947 case OPC_LHX: 13948 case OPC_LWX: 13949 gen_mips_lx(ctx, op2, rd, rs, rt); 13950 break; 13951 default: /* Invalid */ 13952 MIPS_INVAL("MASK LX"); 13953 gen_reserved_instruction(ctx); 13954 break; 13955 } 13956 break; 13957 case OPC_ABSQ_S_PH_DSP: 13958 op2 = MASK_ABSQ_S_PH(ctx->opcode); 13959 switch (op2) { 13960 case OPC_ABSQ_S_QB: 13961 case OPC_ABSQ_S_PH: 13962 case OPC_ABSQ_S_W: 13963 case OPC_PRECEQ_W_PHL: 13964 case OPC_PRECEQ_W_PHR: 13965 case OPC_PRECEQU_PH_QBL: 13966 case OPC_PRECEQU_PH_QBR: 13967 case OPC_PRECEQU_PH_QBLA: 13968 case OPC_PRECEQU_PH_QBRA: 13969 case OPC_PRECEU_PH_QBL: 13970 case OPC_PRECEU_PH_QBR: 13971 case OPC_PRECEU_PH_QBLA: 13972 case OPC_PRECEU_PH_QBRA: 13973 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 13974 break; 13975 case OPC_BITREV: 13976 case OPC_REPL_QB: 13977 case OPC_REPLV_QB: 13978 case OPC_REPL_PH: 13979 case OPC_REPLV_PH: 13980 gen_mipsdsp_bitinsn(ctx, op1, op2, rd, rt); 13981 break; 13982 default: 13983 MIPS_INVAL("MASK ABSQ_S.PH"); 13984 gen_reserved_instruction(ctx); 13985 break; 13986 } 13987 break; 13988 case OPC_ADDU_QB_DSP: 13989 op2 = MASK_ADDU_QB(ctx->opcode); 13990 switch (op2) { 13991 case OPC_ADDQ_PH: 13992 case OPC_ADDQ_S_PH: 13993 case OPC_ADDQ_S_W: 13994 case OPC_ADDU_QB: 13995 case OPC_ADDU_S_QB: 13996 case OPC_ADDU_PH: 13997 case OPC_ADDU_S_PH: 13998 case OPC_SUBQ_PH: 13999 case OPC_SUBQ_S_PH: 14000 case OPC_SUBQ_S_W: 14001 case OPC_SUBU_QB: 14002 case OPC_SUBU_S_QB: 14003 case OPC_SUBU_PH: 14004 case OPC_SUBU_S_PH: 14005 case OPC_ADDSC: 14006 case OPC_ADDWC: 14007 case OPC_MODSUB: 14008 case OPC_RADDU_W_QB: 14009 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 14010 break; 14011 case OPC_MULEU_S_PH_QBL: 14012 case OPC_MULEU_S_PH_QBR: 14013 case OPC_MULQ_RS_PH: 14014 case OPC_MULEQ_S_W_PHL: 14015 case OPC_MULEQ_S_W_PHR: 14016 case OPC_MULQ_S_PH: 14017 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1); 14018 break; 14019 default: /* Invalid */ 14020 MIPS_INVAL("MASK ADDU.QB"); 14021 gen_reserved_instruction(ctx); 14022 break; 14023 14024 } 14025 break; 14026 case OPC_CMPU_EQ_QB_DSP: 14027 op2 = MASK_CMPU_EQ_QB(ctx->opcode); 14028 switch (op2) { 14029 case OPC_PRECR_SRA_PH_W: 14030 case OPC_PRECR_SRA_R_PH_W: 14031 gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd); 14032 break; 14033 case OPC_PRECR_QB_PH: 14034 case OPC_PRECRQ_QB_PH: 14035 case OPC_PRECRQ_PH_W: 14036 case OPC_PRECRQ_RS_PH_W: 14037 case OPC_PRECRQU_S_QB_PH: 14038 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 14039 break; 14040 case OPC_CMPU_EQ_QB: 14041 case OPC_CMPU_LT_QB: 14042 case OPC_CMPU_LE_QB: 14043 case OPC_CMP_EQ_PH: 14044 case OPC_CMP_LT_PH: 14045 case OPC_CMP_LE_PH: 14046 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0); 14047 break; 14048 case OPC_CMPGU_EQ_QB: 14049 case OPC_CMPGU_LT_QB: 14050 case OPC_CMPGU_LE_QB: 14051 case OPC_CMPGDU_EQ_QB: 14052 case OPC_CMPGDU_LT_QB: 14053 case OPC_CMPGDU_LE_QB: 14054 case OPC_PICK_QB: 14055 case OPC_PICK_PH: 14056 case OPC_PACKRL_PH: 14057 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1); 14058 break; 14059 default: /* Invalid */ 14060 MIPS_INVAL("MASK CMPU.EQ.QB"); 14061 gen_reserved_instruction(ctx); 14062 break; 14063 } 14064 break; 14065 case OPC_SHLL_QB_DSP: 14066 gen_mipsdsp_shift(ctx, op1, rd, rs, rt); 14067 break; 14068 case OPC_DPA_W_PH_DSP: 14069 op2 = MASK_DPA_W_PH(ctx->opcode); 14070 switch (op2) { 14071 case OPC_DPAU_H_QBL: 14072 case OPC_DPAU_H_QBR: 14073 case OPC_DPSU_H_QBL: 14074 case OPC_DPSU_H_QBR: 14075 case OPC_DPA_W_PH: 14076 case OPC_DPAX_W_PH: 14077 case OPC_DPAQ_S_W_PH: 14078 case OPC_DPAQX_S_W_PH: 14079 case OPC_DPAQX_SA_W_PH: 14080 case OPC_DPS_W_PH: 14081 case OPC_DPSX_W_PH: 14082 case OPC_DPSQ_S_W_PH: 14083 case OPC_DPSQX_S_W_PH: 14084 case OPC_DPSQX_SA_W_PH: 14085 case OPC_MULSAQ_S_W_PH: 14086 case OPC_DPAQ_SA_L_W: 14087 case OPC_DPSQ_SA_L_W: 14088 case OPC_MAQ_S_W_PHL: 14089 case OPC_MAQ_S_W_PHR: 14090 case OPC_MAQ_SA_W_PHL: 14091 case OPC_MAQ_SA_W_PHR: 14092 case OPC_MULSA_W_PH: 14093 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0); 14094 break; 14095 default: /* Invalid */ 14096 MIPS_INVAL("MASK DPAW.PH"); 14097 gen_reserved_instruction(ctx); 14098 break; 14099 } 14100 break; 14101 case OPC_INSV_DSP: 14102 op2 = MASK_INSV(ctx->opcode); 14103 switch (op2) { 14104 case OPC_INSV: 14105 check_dsp(ctx); 14106 { 14107 TCGv t0, t1; 14108 14109 if (rt == 0) { 14110 break; 14111 } 14112 14113 t0 = tcg_temp_new(); 14114 t1 = tcg_temp_new(); 14115 14116 gen_load_gpr(t0, rt); 14117 gen_load_gpr(t1, rs); 14118 14119 gen_helper_insv(cpu_gpr[rt], cpu_env, t1, t0); 14120 break; 14121 } 14122 default: /* Invalid */ 14123 MIPS_INVAL("MASK INSV"); 14124 gen_reserved_instruction(ctx); 14125 break; 14126 } 14127 break; 14128 case OPC_APPEND_DSP: 14129 gen_mipsdsp_append(env, ctx, op1, rt, rs, rd); 14130 break; 14131 case OPC_EXTR_W_DSP: 14132 op2 = MASK_EXTR_W(ctx->opcode); 14133 switch (op2) { 14134 case OPC_EXTR_W: 14135 case OPC_EXTR_R_W: 14136 case OPC_EXTR_RS_W: 14137 case OPC_EXTR_S_H: 14138 case OPC_EXTRV_S_H: 14139 case OPC_EXTRV_W: 14140 case OPC_EXTRV_R_W: 14141 case OPC_EXTRV_RS_W: 14142 case OPC_EXTP: 14143 case OPC_EXTPV: 14144 case OPC_EXTPDP: 14145 case OPC_EXTPDPV: 14146 gen_mipsdsp_accinsn(ctx, op1, op2, rt, rs, rd, 1); 14147 break; 14148 case OPC_RDDSP: 14149 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 1); 14150 break; 14151 case OPC_SHILO: 14152 case OPC_SHILOV: 14153 case OPC_MTHLIP: 14154 case OPC_WRDSP: 14155 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 0); 14156 break; 14157 default: /* Invalid */ 14158 MIPS_INVAL("MASK EXTR.W"); 14159 gen_reserved_instruction(ctx); 14160 break; 14161 } 14162 break; 14163 #if defined(TARGET_MIPS64) 14164 case OPC_DDIV_G_2E: 14165 case OPC_DDIVU_G_2E: 14166 case OPC_DMULT_G_2E: 14167 case OPC_DMULTU_G_2E: 14168 case OPC_DMOD_G_2E: 14169 case OPC_DMODU_G_2E: 14170 check_insn(ctx, INSN_LOONGSON2E); 14171 gen_loongson_integer(ctx, op1, rd, rs, rt); 14172 break; 14173 case OPC_ABSQ_S_QH_DSP: 14174 op2 = MASK_ABSQ_S_QH(ctx->opcode); 14175 switch (op2) { 14176 case OPC_PRECEQ_L_PWL: 14177 case OPC_PRECEQ_L_PWR: 14178 case OPC_PRECEQ_PW_QHL: 14179 case OPC_PRECEQ_PW_QHR: 14180 case OPC_PRECEQ_PW_QHLA: 14181 case OPC_PRECEQ_PW_QHRA: 14182 case OPC_PRECEQU_QH_OBL: 14183 case OPC_PRECEQU_QH_OBR: 14184 case OPC_PRECEQU_QH_OBLA: 14185 case OPC_PRECEQU_QH_OBRA: 14186 case OPC_PRECEU_QH_OBL: 14187 case OPC_PRECEU_QH_OBR: 14188 case OPC_PRECEU_QH_OBLA: 14189 case OPC_PRECEU_QH_OBRA: 14190 case OPC_ABSQ_S_OB: 14191 case OPC_ABSQ_S_PW: 14192 case OPC_ABSQ_S_QH: 14193 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 14194 break; 14195 case OPC_REPL_OB: 14196 case OPC_REPL_PW: 14197 case OPC_REPL_QH: 14198 case OPC_REPLV_OB: 14199 case OPC_REPLV_PW: 14200 case OPC_REPLV_QH: 14201 gen_mipsdsp_bitinsn(ctx, op1, op2, rd, rt); 14202 break; 14203 default: /* Invalid */ 14204 MIPS_INVAL("MASK ABSQ_S.QH"); 14205 gen_reserved_instruction(ctx); 14206 break; 14207 } 14208 break; 14209 case OPC_ADDU_OB_DSP: 14210 op2 = MASK_ADDU_OB(ctx->opcode); 14211 switch (op2) { 14212 case OPC_RADDU_L_OB: 14213 case OPC_SUBQ_PW: 14214 case OPC_SUBQ_S_PW: 14215 case OPC_SUBQ_QH: 14216 case OPC_SUBQ_S_QH: 14217 case OPC_SUBU_OB: 14218 case OPC_SUBU_S_OB: 14219 case OPC_SUBU_QH: 14220 case OPC_SUBU_S_QH: 14221 case OPC_SUBUH_OB: 14222 case OPC_SUBUH_R_OB: 14223 case OPC_ADDQ_PW: 14224 case OPC_ADDQ_S_PW: 14225 case OPC_ADDQ_QH: 14226 case OPC_ADDQ_S_QH: 14227 case OPC_ADDU_OB: 14228 case OPC_ADDU_S_OB: 14229 case OPC_ADDU_QH: 14230 case OPC_ADDU_S_QH: 14231 case OPC_ADDUH_OB: 14232 case OPC_ADDUH_R_OB: 14233 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 14234 break; 14235 case OPC_MULEQ_S_PW_QHL: 14236 case OPC_MULEQ_S_PW_QHR: 14237 case OPC_MULEU_S_QH_OBL: 14238 case OPC_MULEU_S_QH_OBR: 14239 case OPC_MULQ_RS_QH: 14240 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1); 14241 break; 14242 default: /* Invalid */ 14243 MIPS_INVAL("MASK ADDU.OB"); 14244 gen_reserved_instruction(ctx); 14245 break; 14246 } 14247 break; 14248 case OPC_CMPU_EQ_OB_DSP: 14249 op2 = MASK_CMPU_EQ_OB(ctx->opcode); 14250 switch (op2) { 14251 case OPC_PRECR_SRA_QH_PW: 14252 case OPC_PRECR_SRA_R_QH_PW: 14253 /* Return value is rt. */ 14254 gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd); 14255 break; 14256 case OPC_PRECR_OB_QH: 14257 case OPC_PRECRQ_OB_QH: 14258 case OPC_PRECRQ_PW_L: 14259 case OPC_PRECRQ_QH_PW: 14260 case OPC_PRECRQ_RS_QH_PW: 14261 case OPC_PRECRQU_S_OB_QH: 14262 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 14263 break; 14264 case OPC_CMPU_EQ_OB: 14265 case OPC_CMPU_LT_OB: 14266 case OPC_CMPU_LE_OB: 14267 case OPC_CMP_EQ_QH: 14268 case OPC_CMP_LT_QH: 14269 case OPC_CMP_LE_QH: 14270 case OPC_CMP_EQ_PW: 14271 case OPC_CMP_LT_PW: 14272 case OPC_CMP_LE_PW: 14273 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0); 14274 break; 14275 case OPC_CMPGDU_EQ_OB: 14276 case OPC_CMPGDU_LT_OB: 14277 case OPC_CMPGDU_LE_OB: 14278 case OPC_CMPGU_EQ_OB: 14279 case OPC_CMPGU_LT_OB: 14280 case OPC_CMPGU_LE_OB: 14281 case OPC_PACKRL_PW: 14282 case OPC_PICK_OB: 14283 case OPC_PICK_PW: 14284 case OPC_PICK_QH: 14285 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1); 14286 break; 14287 default: /* Invalid */ 14288 MIPS_INVAL("MASK CMPU_EQ.OB"); 14289 gen_reserved_instruction(ctx); 14290 break; 14291 } 14292 break; 14293 case OPC_DAPPEND_DSP: 14294 gen_mipsdsp_append(env, ctx, op1, rt, rs, rd); 14295 break; 14296 case OPC_DEXTR_W_DSP: 14297 op2 = MASK_DEXTR_W(ctx->opcode); 14298 switch (op2) { 14299 case OPC_DEXTP: 14300 case OPC_DEXTPDP: 14301 case OPC_DEXTPDPV: 14302 case OPC_DEXTPV: 14303 case OPC_DEXTR_L: 14304 case OPC_DEXTR_R_L: 14305 case OPC_DEXTR_RS_L: 14306 case OPC_DEXTR_W: 14307 case OPC_DEXTR_R_W: 14308 case OPC_DEXTR_RS_W: 14309 case OPC_DEXTR_S_H: 14310 case OPC_DEXTRV_L: 14311 case OPC_DEXTRV_R_L: 14312 case OPC_DEXTRV_RS_L: 14313 case OPC_DEXTRV_S_H: 14314 case OPC_DEXTRV_W: 14315 case OPC_DEXTRV_R_W: 14316 case OPC_DEXTRV_RS_W: 14317 gen_mipsdsp_accinsn(ctx, op1, op2, rt, rs, rd, 1); 14318 break; 14319 case OPC_DMTHLIP: 14320 case OPC_DSHILO: 14321 case OPC_DSHILOV: 14322 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 0); 14323 break; 14324 default: /* Invalid */ 14325 MIPS_INVAL("MASK EXTR.W"); 14326 gen_reserved_instruction(ctx); 14327 break; 14328 } 14329 break; 14330 case OPC_DPAQ_W_QH_DSP: 14331 op2 = MASK_DPAQ_W_QH(ctx->opcode); 14332 switch (op2) { 14333 case OPC_DPAU_H_OBL: 14334 case OPC_DPAU_H_OBR: 14335 case OPC_DPSU_H_OBL: 14336 case OPC_DPSU_H_OBR: 14337 case OPC_DPA_W_QH: 14338 case OPC_DPAQ_S_W_QH: 14339 case OPC_DPS_W_QH: 14340 case OPC_DPSQ_S_W_QH: 14341 case OPC_MULSAQ_S_W_QH: 14342 case OPC_DPAQ_SA_L_PW: 14343 case OPC_DPSQ_SA_L_PW: 14344 case OPC_MULSAQ_S_L_PW: 14345 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0); 14346 break; 14347 case OPC_MAQ_S_W_QHLL: 14348 case OPC_MAQ_S_W_QHLR: 14349 case OPC_MAQ_S_W_QHRL: 14350 case OPC_MAQ_S_W_QHRR: 14351 case OPC_MAQ_SA_W_QHLL: 14352 case OPC_MAQ_SA_W_QHLR: 14353 case OPC_MAQ_SA_W_QHRL: 14354 case OPC_MAQ_SA_W_QHRR: 14355 case OPC_MAQ_S_L_PWL: 14356 case OPC_MAQ_S_L_PWR: 14357 case OPC_DMADD: 14358 case OPC_DMADDU: 14359 case OPC_DMSUB: 14360 case OPC_DMSUBU: 14361 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0); 14362 break; 14363 default: /* Invalid */ 14364 MIPS_INVAL("MASK DPAQ.W.QH"); 14365 gen_reserved_instruction(ctx); 14366 break; 14367 } 14368 break; 14369 case OPC_DINSV_DSP: 14370 op2 = MASK_INSV(ctx->opcode); 14371 switch (op2) { 14372 case OPC_DINSV: 14373 { 14374 TCGv t0, t1; 14375 14376 check_dsp(ctx); 14377 14378 if (rt == 0) { 14379 break; 14380 } 14381 14382 t0 = tcg_temp_new(); 14383 t1 = tcg_temp_new(); 14384 14385 gen_load_gpr(t0, rt); 14386 gen_load_gpr(t1, rs); 14387 14388 gen_helper_dinsv(cpu_gpr[rt], cpu_env, t1, t0); 14389 break; 14390 } 14391 default: /* Invalid */ 14392 MIPS_INVAL("MASK DINSV"); 14393 gen_reserved_instruction(ctx); 14394 break; 14395 } 14396 break; 14397 case OPC_SHLL_OB_DSP: 14398 gen_mipsdsp_shift(ctx, op1, rd, rs, rt); 14399 break; 14400 #endif 14401 default: /* Invalid */ 14402 MIPS_INVAL("special3_legacy"); 14403 gen_reserved_instruction(ctx); 14404 break; 14405 } 14406 } 14407 14408 14409 #if defined(TARGET_MIPS64) 14410 14411 static void decode_mmi(CPUMIPSState *env, DisasContext *ctx) 14412 { 14413 uint32_t opc = MASK_MMI(ctx->opcode); 14414 int rs = extract32(ctx->opcode, 21, 5); 14415 int rt = extract32(ctx->opcode, 16, 5); 14416 int rd = extract32(ctx->opcode, 11, 5); 14417 14418 switch (opc) { 14419 case MMI_OPC_MULT1: 14420 case MMI_OPC_MULTU1: 14421 case MMI_OPC_MADD: 14422 case MMI_OPC_MADDU: 14423 case MMI_OPC_MADD1: 14424 case MMI_OPC_MADDU1: 14425 gen_mul_txx9(ctx, opc, rd, rs, rt); 14426 break; 14427 case MMI_OPC_DIV1: 14428 case MMI_OPC_DIVU1: 14429 gen_div1_tx79(ctx, opc, rs, rt); 14430 break; 14431 default: 14432 MIPS_INVAL("TX79 MMI class"); 14433 gen_reserved_instruction(ctx); 14434 break; 14435 } 14436 } 14437 14438 static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset) 14439 { 14440 gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */ 14441 } 14442 14443 /* 14444 * The TX79-specific instruction Store Quadword 14445 * 14446 * +--------+-------+-------+------------------------+ 14447 * | 011111 | base | rt | offset | SQ 14448 * +--------+-------+-------+------------------------+ 14449 * 6 5 5 16 14450 * 14451 * has the same opcode as the Read Hardware Register instruction 14452 * 14453 * +--------+-------+-------+-------+-------+--------+ 14454 * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR 14455 * +--------+-------+-------+-------+-------+--------+ 14456 * 6 5 5 5 5 6 14457 * 14458 * that is required, trapped and emulated by the Linux kernel. However, all 14459 * RDHWR encodings yield address error exceptions on the TX79 since the SQ 14460 * offset is odd. Therefore all valid SQ instructions can execute normally. 14461 * In user mode, QEMU must verify the upper and lower 11 bits to distinguish 14462 * between SQ and RDHWR, as the Linux kernel does. 14463 */ 14464 static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx) 14465 { 14466 int base = extract32(ctx->opcode, 21, 5); 14467 int rt = extract32(ctx->opcode, 16, 5); 14468 int offset = extract32(ctx->opcode, 0, 16); 14469 14470 #ifdef CONFIG_USER_ONLY 14471 uint32_t op1 = MASK_SPECIAL3(ctx->opcode); 14472 uint32_t op2 = extract32(ctx->opcode, 6, 5); 14473 14474 if (base == 0 && op2 == 0 && op1 == OPC_RDHWR) { 14475 int rd = extract32(ctx->opcode, 11, 5); 14476 14477 gen_rdhwr(ctx, rt, rd, 0); 14478 return; 14479 } 14480 #endif 14481 14482 gen_mmi_sq(ctx, base, rt, offset); 14483 } 14484 14485 #endif 14486 14487 static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) 14488 { 14489 int rs, rt, rd, sa; 14490 uint32_t op1, op2; 14491 int16_t imm; 14492 14493 rs = (ctx->opcode >> 21) & 0x1f; 14494 rt = (ctx->opcode >> 16) & 0x1f; 14495 rd = (ctx->opcode >> 11) & 0x1f; 14496 sa = (ctx->opcode >> 6) & 0x1f; 14497 imm = sextract32(ctx->opcode, 7, 9); 14498 14499 op1 = MASK_SPECIAL3(ctx->opcode); 14500 14501 /* 14502 * EVA loads and stores overlap Loongson 2E instructions decoded by 14503 * decode_opc_special3_legacy(), so be careful to allow their decoding when 14504 * EVA is absent. 14505 */ 14506 if (ctx->eva) { 14507 switch (op1) { 14508 case OPC_LWLE: 14509 case OPC_LWRE: 14510 case OPC_LBUE: 14511 case OPC_LHUE: 14512 case OPC_LBE: 14513 case OPC_LHE: 14514 case OPC_LLE: 14515 case OPC_LWE: 14516 check_cp0_enabled(ctx); 14517 gen_ld(ctx, op1, rt, rs, imm); 14518 return; 14519 case OPC_SWLE: 14520 case OPC_SWRE: 14521 case OPC_SBE: 14522 case OPC_SHE: 14523 case OPC_SWE: 14524 check_cp0_enabled(ctx); 14525 gen_st(ctx, op1, rt, rs, imm); 14526 return; 14527 case OPC_SCE: 14528 check_cp0_enabled(ctx); 14529 gen_st_cond(ctx, rt, rs, imm, MO_TESL, true); 14530 return; 14531 case OPC_CACHEE: 14532 check_eva(ctx); 14533 check_cp0_enabled(ctx); 14534 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { 14535 gen_cache_operation(ctx, rt, rs, imm); 14536 } 14537 return; 14538 case OPC_PREFE: 14539 check_cp0_enabled(ctx); 14540 /* Treat as NOP. */ 14541 return; 14542 } 14543 } 14544 14545 switch (op1) { 14546 case OPC_EXT: 14547 case OPC_INS: 14548 check_insn(ctx, ISA_MIPS_R2); 14549 gen_bitops(ctx, op1, rt, rs, sa, rd); 14550 break; 14551 case OPC_BSHFL: 14552 op2 = MASK_BSHFL(ctx->opcode); 14553 switch (op2) { 14554 case OPC_ALIGN: 14555 case OPC_ALIGN_1: 14556 case OPC_ALIGN_2: 14557 case OPC_ALIGN_3: 14558 case OPC_BITSWAP: 14559 check_insn(ctx, ISA_MIPS_R6); 14560 decode_opc_special3_r6(env, ctx); 14561 break; 14562 default: 14563 check_insn(ctx, ISA_MIPS_R2); 14564 gen_bshfl(ctx, op2, rt, rd); 14565 break; 14566 } 14567 break; 14568 #if defined(TARGET_MIPS64) 14569 case OPC_DEXTM: 14570 case OPC_DEXTU: 14571 case OPC_DEXT: 14572 case OPC_DINSM: 14573 case OPC_DINSU: 14574 case OPC_DINS: 14575 check_insn(ctx, ISA_MIPS_R2); 14576 check_mips_64(ctx); 14577 gen_bitops(ctx, op1, rt, rs, sa, rd); 14578 break; 14579 case OPC_DBSHFL: 14580 op2 = MASK_DBSHFL(ctx->opcode); 14581 switch (op2) { 14582 case OPC_DALIGN: 14583 case OPC_DALIGN_1: 14584 case OPC_DALIGN_2: 14585 case OPC_DALIGN_3: 14586 case OPC_DALIGN_4: 14587 case OPC_DALIGN_5: 14588 case OPC_DALIGN_6: 14589 case OPC_DALIGN_7: 14590 case OPC_DBITSWAP: 14591 check_insn(ctx, ISA_MIPS_R6); 14592 decode_opc_special3_r6(env, ctx); 14593 break; 14594 default: 14595 check_insn(ctx, ISA_MIPS_R2); 14596 check_mips_64(ctx); 14597 op2 = MASK_DBSHFL(ctx->opcode); 14598 gen_bshfl(ctx, op2, rt, rd); 14599 break; 14600 } 14601 break; 14602 #endif 14603 case OPC_RDHWR: 14604 gen_rdhwr(ctx, rt, rd, extract32(ctx->opcode, 6, 3)); 14605 break; 14606 case OPC_FORK: 14607 check_mt(ctx); 14608 { 14609 TCGv t0 = tcg_temp_new(); 14610 TCGv t1 = tcg_temp_new(); 14611 14612 gen_load_gpr(t0, rt); 14613 gen_load_gpr(t1, rs); 14614 gen_helper_fork(t0, t1); 14615 } 14616 break; 14617 case OPC_YIELD: 14618 check_mt(ctx); 14619 { 14620 TCGv t0 = tcg_temp_new(); 14621 14622 gen_load_gpr(t0, rs); 14623 gen_helper_yield(t0, cpu_env, t0); 14624 gen_store_gpr(t0, rd); 14625 } 14626 break; 14627 default: 14628 if (ctx->insn_flags & ISA_MIPS_R6) { 14629 decode_opc_special3_r6(env, ctx); 14630 } else { 14631 decode_opc_special3_legacy(env, ctx); 14632 } 14633 } 14634 } 14635 14636 static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) 14637 { 14638 int32_t offset; 14639 int rs, rt, rd, sa; 14640 uint32_t op, op1; 14641 int16_t imm; 14642 14643 op = MASK_OP_MAJOR(ctx->opcode); 14644 rs = (ctx->opcode >> 21) & 0x1f; 14645 rt = (ctx->opcode >> 16) & 0x1f; 14646 rd = (ctx->opcode >> 11) & 0x1f; 14647 sa = (ctx->opcode >> 6) & 0x1f; 14648 imm = (int16_t)ctx->opcode; 14649 switch (op) { 14650 case OPC_SPECIAL: 14651 decode_opc_special(env, ctx); 14652 break; 14653 case OPC_SPECIAL2: 14654 #if defined(TARGET_MIPS64) 14655 if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) { 14656 decode_mmi(env, ctx); 14657 break; 14658 } 14659 #endif 14660 if (TARGET_LONG_BITS == 32 && (ctx->insn_flags & ASE_MXU)) { 14661 if (MASK_SPECIAL2(ctx->opcode) == OPC_MUL) { 14662 gen_arith(ctx, OPC_MUL, rd, rs, rt); 14663 } else { 14664 decode_ase_mxu(ctx, ctx->opcode); 14665 } 14666 break; 14667 } 14668 decode_opc_special2_legacy(env, ctx); 14669 break; 14670 case OPC_SPECIAL3: 14671 #if defined(TARGET_MIPS64) 14672 if (ctx->insn_flags & INSN_R5900) { 14673 decode_mmi_sq(env, ctx); /* MMI_OPC_SQ */ 14674 } else { 14675 decode_opc_special3(env, ctx); 14676 } 14677 #else 14678 decode_opc_special3(env, ctx); 14679 #endif 14680 break; 14681 case OPC_REGIMM: 14682 op1 = MASK_REGIMM(ctx->opcode); 14683 switch (op1) { 14684 case OPC_BLTZL: /* REGIMM branches */ 14685 case OPC_BGEZL: 14686 case OPC_BLTZALL: 14687 case OPC_BGEZALL: 14688 check_insn(ctx, ISA_MIPS2); 14689 check_insn_opc_removed(ctx, ISA_MIPS_R6); 14690 /* Fallthrough */ 14691 case OPC_BLTZ: 14692 case OPC_BGEZ: 14693 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); 14694 break; 14695 case OPC_BLTZAL: 14696 case OPC_BGEZAL: 14697 if (ctx->insn_flags & ISA_MIPS_R6) { 14698 if (rs == 0) { 14699 /* OPC_NAL, OPC_BAL */ 14700 gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4); 14701 } else { 14702 gen_reserved_instruction(ctx); 14703 } 14704 } else { 14705 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); 14706 } 14707 break; 14708 case OPC_TGEI: /* REGIMM traps */ 14709 case OPC_TGEIU: 14710 case OPC_TLTI: 14711 case OPC_TLTIU: 14712 case OPC_TEQI: 14713 case OPC_TNEI: 14714 check_insn(ctx, ISA_MIPS2); 14715 check_insn_opc_removed(ctx, ISA_MIPS_R6); 14716 gen_trap(ctx, op1, rs, -1, imm, 0); 14717 break; 14718 case OPC_SIGRIE: 14719 check_insn(ctx, ISA_MIPS_R6); 14720 gen_reserved_instruction(ctx); 14721 break; 14722 case OPC_SYNCI: 14723 check_insn(ctx, ISA_MIPS_R2); 14724 /* 14725 * Break the TB to be able to sync copied instructions 14726 * immediately. 14727 */ 14728 ctx->base.is_jmp = DISAS_STOP; 14729 break; 14730 case OPC_BPOSGE32: /* MIPS DSP branch */ 14731 #if defined(TARGET_MIPS64) 14732 case OPC_BPOSGE64: 14733 #endif 14734 check_dsp(ctx); 14735 gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2, 4); 14736 break; 14737 #if defined(TARGET_MIPS64) 14738 case OPC_DAHI: 14739 check_insn(ctx, ISA_MIPS_R6); 14740 check_mips_64(ctx); 14741 if (rs != 0) { 14742 tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 32); 14743 } 14744 break; 14745 case OPC_DATI: 14746 check_insn(ctx, ISA_MIPS_R6); 14747 check_mips_64(ctx); 14748 if (rs != 0) { 14749 tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 48); 14750 } 14751 break; 14752 #endif 14753 default: /* Invalid */ 14754 MIPS_INVAL("regimm"); 14755 gen_reserved_instruction(ctx); 14756 break; 14757 } 14758 break; 14759 case OPC_CP0: 14760 check_cp0_enabled(ctx); 14761 op1 = MASK_CP0(ctx->opcode); 14762 switch (op1) { 14763 case OPC_MFC0: 14764 case OPC_MTC0: 14765 case OPC_MFTR: 14766 case OPC_MTTR: 14767 case OPC_MFHC0: 14768 case OPC_MTHC0: 14769 #if defined(TARGET_MIPS64) 14770 case OPC_DMFC0: 14771 case OPC_DMTC0: 14772 #endif 14773 #ifndef CONFIG_USER_ONLY 14774 gen_cp0(env, ctx, op1, rt, rd); 14775 #endif /* !CONFIG_USER_ONLY */ 14776 break; 14777 case OPC_C0: 14778 case OPC_C0_1: 14779 case OPC_C0_2: 14780 case OPC_C0_3: 14781 case OPC_C0_4: 14782 case OPC_C0_5: 14783 case OPC_C0_6: 14784 case OPC_C0_7: 14785 case OPC_C0_8: 14786 case OPC_C0_9: 14787 case OPC_C0_A: 14788 case OPC_C0_B: 14789 case OPC_C0_C: 14790 case OPC_C0_D: 14791 case OPC_C0_E: 14792 case OPC_C0_F: 14793 #ifndef CONFIG_USER_ONLY 14794 gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd); 14795 #endif /* !CONFIG_USER_ONLY */ 14796 break; 14797 case OPC_MFMC0: 14798 #ifndef CONFIG_USER_ONLY 14799 { 14800 uint32_t op2; 14801 TCGv t0 = tcg_temp_new(); 14802 14803 op2 = MASK_MFMC0(ctx->opcode); 14804 switch (op2) { 14805 case OPC_DMT: 14806 check_cp0_mt(ctx); 14807 gen_helper_dmt(t0); 14808 gen_store_gpr(t0, rt); 14809 break; 14810 case OPC_EMT: 14811 check_cp0_mt(ctx); 14812 gen_helper_emt(t0); 14813 gen_store_gpr(t0, rt); 14814 break; 14815 case OPC_DVPE: 14816 check_cp0_mt(ctx); 14817 gen_helper_dvpe(t0, cpu_env); 14818 gen_store_gpr(t0, rt); 14819 break; 14820 case OPC_EVPE: 14821 check_cp0_mt(ctx); 14822 gen_helper_evpe(t0, cpu_env); 14823 gen_store_gpr(t0, rt); 14824 break; 14825 case OPC_DVP: 14826 check_insn(ctx, ISA_MIPS_R6); 14827 if (ctx->vp) { 14828 gen_helper_dvp(t0, cpu_env); 14829 gen_store_gpr(t0, rt); 14830 } 14831 break; 14832 case OPC_EVP: 14833 check_insn(ctx, ISA_MIPS_R6); 14834 if (ctx->vp) { 14835 gen_helper_evp(t0, cpu_env); 14836 gen_store_gpr(t0, rt); 14837 } 14838 break; 14839 case OPC_DI: 14840 check_insn(ctx, ISA_MIPS_R2); 14841 save_cpu_state(ctx, 1); 14842 gen_helper_di(t0, cpu_env); 14843 gen_store_gpr(t0, rt); 14844 /* 14845 * Stop translation as we may have switched 14846 * the execution mode. 14847 */ 14848 ctx->base.is_jmp = DISAS_STOP; 14849 break; 14850 case OPC_EI: 14851 check_insn(ctx, ISA_MIPS_R2); 14852 save_cpu_state(ctx, 1); 14853 gen_helper_ei(t0, cpu_env); 14854 gen_store_gpr(t0, rt); 14855 /* 14856 * DISAS_STOP isn't sufficient, we need to ensure we break 14857 * out of translated code to check for pending interrupts. 14858 */ 14859 gen_save_pc(ctx->base.pc_next + 4); 14860 ctx->base.is_jmp = DISAS_EXIT; 14861 break; 14862 default: /* Invalid */ 14863 MIPS_INVAL("mfmc0"); 14864 gen_reserved_instruction(ctx); 14865 break; 14866 } 14867 } 14868 #endif /* !CONFIG_USER_ONLY */ 14869 break; 14870 case OPC_RDPGPR: 14871 check_insn(ctx, ISA_MIPS_R2); 14872 gen_load_srsgpr(rt, rd); 14873 break; 14874 case OPC_WRPGPR: 14875 check_insn(ctx, ISA_MIPS_R2); 14876 gen_store_srsgpr(rt, rd); 14877 break; 14878 default: 14879 MIPS_INVAL("cp0"); 14880 gen_reserved_instruction(ctx); 14881 break; 14882 } 14883 break; 14884 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC, OPC_ADDI */ 14885 if (ctx->insn_flags & ISA_MIPS_R6) { 14886 /* OPC_BOVC, OPC_BEQZALC, OPC_BEQC */ 14887 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 14888 } else { 14889 /* OPC_ADDI */ 14890 /* Arithmetic with immediate opcode */ 14891 gen_arith_imm(ctx, op, rt, rs, imm); 14892 } 14893 break; 14894 case OPC_ADDIU: 14895 gen_arith_imm(ctx, op, rt, rs, imm); 14896 break; 14897 case OPC_SLTI: /* Set on less than with immediate opcode */ 14898 case OPC_SLTIU: 14899 gen_slt_imm(ctx, op, rt, rs, imm); 14900 break; 14901 case OPC_ANDI: /* Arithmetic with immediate opcode */ 14902 case OPC_LUI: /* OPC_AUI */ 14903 case OPC_ORI: 14904 case OPC_XORI: 14905 gen_logic_imm(ctx, op, rt, rs, imm); 14906 break; 14907 case OPC_J: /* Jump */ 14908 case OPC_JAL: 14909 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; 14910 gen_compute_branch(ctx, op, 4, rs, rt, offset, 4); 14911 break; 14912 /* Branch */ 14913 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */ 14914 if (ctx->insn_flags & ISA_MIPS_R6) { 14915 if (rt == 0) { 14916 gen_reserved_instruction(ctx); 14917 break; 14918 } 14919 /* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */ 14920 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 14921 } else { 14922 /* OPC_BLEZL */ 14923 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); 14924 } 14925 break; 14926 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */ 14927 if (ctx->insn_flags & ISA_MIPS_R6) { 14928 if (rt == 0) { 14929 gen_reserved_instruction(ctx); 14930 break; 14931 } 14932 /* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */ 14933 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 14934 } else { 14935 /* OPC_BGTZL */ 14936 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); 14937 } 14938 break; 14939 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC, OPC_BLEZ */ 14940 if (rt == 0) { 14941 /* OPC_BLEZ */ 14942 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); 14943 } else { 14944 check_insn(ctx, ISA_MIPS_R6); 14945 /* OPC_BLEZALC, OPC_BGEZALC, OPC_BGEUC */ 14946 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 14947 } 14948 break; 14949 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC, OPC_BGTZ */ 14950 if (rt == 0) { 14951 /* OPC_BGTZ */ 14952 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); 14953 } else { 14954 check_insn(ctx, ISA_MIPS_R6); 14955 /* OPC_BGTZALC, OPC_BLTZALC, OPC_BLTUC */ 14956 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 14957 } 14958 break; 14959 case OPC_BEQL: 14960 case OPC_BNEL: 14961 check_insn(ctx, ISA_MIPS2); 14962 check_insn_opc_removed(ctx, ISA_MIPS_R6); 14963 /* Fallthrough */ 14964 case OPC_BEQ: 14965 case OPC_BNE: 14966 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); 14967 break; 14968 case OPC_LL: /* Load and stores */ 14969 check_insn(ctx, ISA_MIPS2); 14970 if (ctx->insn_flags & INSN_R5900) { 14971 check_insn_opc_user_only(ctx, INSN_R5900); 14972 } 14973 /* Fallthrough */ 14974 case OPC_LWL: 14975 case OPC_LWR: 14976 case OPC_LB: 14977 case OPC_LH: 14978 case OPC_LW: 14979 case OPC_LWPC: 14980 case OPC_LBU: 14981 case OPC_LHU: 14982 gen_ld(ctx, op, rt, rs, imm); 14983 break; 14984 case OPC_SWL: 14985 case OPC_SWR: 14986 case OPC_SB: 14987 case OPC_SH: 14988 case OPC_SW: 14989 gen_st(ctx, op, rt, rs, imm); 14990 break; 14991 case OPC_SC: 14992 check_insn(ctx, ISA_MIPS2); 14993 if (ctx->insn_flags & INSN_R5900) { 14994 check_insn_opc_user_only(ctx, INSN_R5900); 14995 } 14996 gen_st_cond(ctx, rt, rs, imm, MO_TESL, false); 14997 break; 14998 case OPC_CACHE: 14999 check_cp0_enabled(ctx); 15000 check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); 15001 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { 15002 gen_cache_operation(ctx, rt, rs, imm); 15003 } 15004 /* Treat as NOP. */ 15005 break; 15006 case OPC_PREF: 15007 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | INSN_R5900); 15008 /* Treat as NOP. */ 15009 break; 15010 15011 /* Floating point (COP1). */ 15012 case OPC_LWC1: 15013 case OPC_LDC1: 15014 case OPC_SWC1: 15015 case OPC_SDC1: 15016 gen_cop1_ldst(ctx, op, rt, rs, imm); 15017 break; 15018 15019 case OPC_CP1: 15020 op1 = MASK_CP1(ctx->opcode); 15021 15022 switch (op1) { 15023 case OPC_MFHC1: 15024 case OPC_MTHC1: 15025 check_cp1_enabled(ctx); 15026 check_insn(ctx, ISA_MIPS_R2); 15027 /* fall through */ 15028 case OPC_MFC1: 15029 case OPC_CFC1: 15030 case OPC_MTC1: 15031 case OPC_CTC1: 15032 check_cp1_enabled(ctx); 15033 gen_cp1(ctx, op1, rt, rd); 15034 break; 15035 #if defined(TARGET_MIPS64) 15036 case OPC_DMFC1: 15037 case OPC_DMTC1: 15038 check_cp1_enabled(ctx); 15039 check_insn(ctx, ISA_MIPS3); 15040 check_mips_64(ctx); 15041 gen_cp1(ctx, op1, rt, rd); 15042 break; 15043 #endif 15044 case OPC_BC1EQZ: /* OPC_BC1ANY2 */ 15045 check_cp1_enabled(ctx); 15046 if (ctx->insn_flags & ISA_MIPS_R6) { 15047 /* OPC_BC1EQZ */ 15048 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), 15049 rt, imm << 2, 4); 15050 } else { 15051 /* OPC_BC1ANY2 */ 15052 check_cop1x(ctx); 15053 check_insn(ctx, ASE_MIPS3D); 15054 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), 15055 (rt >> 2) & 0x7, imm << 2); 15056 } 15057 break; 15058 case OPC_BC1NEZ: 15059 check_cp1_enabled(ctx); 15060 check_insn(ctx, ISA_MIPS_R6); 15061 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), 15062 rt, imm << 2, 4); 15063 break; 15064 case OPC_BC1ANY4: 15065 check_cp1_enabled(ctx); 15066 check_insn_opc_removed(ctx, ISA_MIPS_R6); 15067 check_cop1x(ctx); 15068 check_insn(ctx, ASE_MIPS3D); 15069 /* fall through */ 15070 case OPC_BC1: 15071 check_cp1_enabled(ctx); 15072 check_insn_opc_removed(ctx, ISA_MIPS_R6); 15073 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), 15074 (rt >> 2) & 0x7, imm << 2); 15075 break; 15076 case OPC_PS_FMT: 15077 check_ps(ctx); 15078 /* fall through */ 15079 case OPC_S_FMT: 15080 case OPC_D_FMT: 15081 check_cp1_enabled(ctx); 15082 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa, 15083 (imm >> 8) & 0x7); 15084 break; 15085 case OPC_W_FMT: 15086 case OPC_L_FMT: 15087 { 15088 int r6_op = ctx->opcode & FOP(0x3f, 0x1f); 15089 check_cp1_enabled(ctx); 15090 if (ctx->insn_flags & ISA_MIPS_R6) { 15091 switch (r6_op) { 15092 case R6_OPC_CMP_AF_S: 15093 case R6_OPC_CMP_UN_S: 15094 case R6_OPC_CMP_EQ_S: 15095 case R6_OPC_CMP_UEQ_S: 15096 case R6_OPC_CMP_LT_S: 15097 case R6_OPC_CMP_ULT_S: 15098 case R6_OPC_CMP_LE_S: 15099 case R6_OPC_CMP_ULE_S: 15100 case R6_OPC_CMP_SAF_S: 15101 case R6_OPC_CMP_SUN_S: 15102 case R6_OPC_CMP_SEQ_S: 15103 case R6_OPC_CMP_SEUQ_S: 15104 case R6_OPC_CMP_SLT_S: 15105 case R6_OPC_CMP_SULT_S: 15106 case R6_OPC_CMP_SLE_S: 15107 case R6_OPC_CMP_SULE_S: 15108 case R6_OPC_CMP_OR_S: 15109 case R6_OPC_CMP_UNE_S: 15110 case R6_OPC_CMP_NE_S: 15111 case R6_OPC_CMP_SOR_S: 15112 case R6_OPC_CMP_SUNE_S: 15113 case R6_OPC_CMP_SNE_S: 15114 gen_r6_cmp_s(ctx, ctx->opcode & 0x1f, rt, rd, sa); 15115 break; 15116 case R6_OPC_CMP_AF_D: 15117 case R6_OPC_CMP_UN_D: 15118 case R6_OPC_CMP_EQ_D: 15119 case R6_OPC_CMP_UEQ_D: 15120 case R6_OPC_CMP_LT_D: 15121 case R6_OPC_CMP_ULT_D: 15122 case R6_OPC_CMP_LE_D: 15123 case R6_OPC_CMP_ULE_D: 15124 case R6_OPC_CMP_SAF_D: 15125 case R6_OPC_CMP_SUN_D: 15126 case R6_OPC_CMP_SEQ_D: 15127 case R6_OPC_CMP_SEUQ_D: 15128 case R6_OPC_CMP_SLT_D: 15129 case R6_OPC_CMP_SULT_D: 15130 case R6_OPC_CMP_SLE_D: 15131 case R6_OPC_CMP_SULE_D: 15132 case R6_OPC_CMP_OR_D: 15133 case R6_OPC_CMP_UNE_D: 15134 case R6_OPC_CMP_NE_D: 15135 case R6_OPC_CMP_SOR_D: 15136 case R6_OPC_CMP_SUNE_D: 15137 case R6_OPC_CMP_SNE_D: 15138 gen_r6_cmp_d(ctx, ctx->opcode & 0x1f, rt, rd, sa); 15139 break; 15140 default: 15141 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), 15142 rt, rd, sa, (imm >> 8) & 0x7); 15143 15144 break; 15145 } 15146 } else { 15147 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa, 15148 (imm >> 8) & 0x7); 15149 } 15150 break; 15151 } 15152 default: 15153 MIPS_INVAL("cp1"); 15154 gen_reserved_instruction(ctx); 15155 break; 15156 } 15157 break; 15158 15159 /* Compact branches [R6] and COP2 [non-R6] */ 15160 case OPC_BC: /* OPC_LWC2 */ 15161 case OPC_BALC: /* OPC_SWC2 */ 15162 if (ctx->insn_flags & ISA_MIPS_R6) { 15163 /* OPC_BC, OPC_BALC */ 15164 gen_compute_compact_branch(ctx, op, 0, 0, 15165 sextract32(ctx->opcode << 2, 0, 28)); 15166 } else if (ctx->insn_flags & ASE_LEXT) { 15167 gen_loongson_lswc2(ctx, rt, rs, rd); 15168 } else { 15169 /* OPC_LWC2, OPC_SWC2 */ 15170 /* COP2: Not implemented. */ 15171 generate_exception_err(ctx, EXCP_CpU, 2); 15172 } 15173 break; 15174 case OPC_BEQZC: /* OPC_JIC, OPC_LDC2 */ 15175 case OPC_BNEZC: /* OPC_JIALC, OPC_SDC2 */ 15176 if (ctx->insn_flags & ISA_MIPS_R6) { 15177 if (rs != 0) { 15178 /* OPC_BEQZC, OPC_BNEZC */ 15179 gen_compute_compact_branch(ctx, op, rs, 0, 15180 sextract32(ctx->opcode << 2, 0, 23)); 15181 } else { 15182 /* OPC_JIC, OPC_JIALC */ 15183 gen_compute_compact_branch(ctx, op, 0, rt, imm); 15184 } 15185 } else if (ctx->insn_flags & ASE_LEXT) { 15186 gen_loongson_lsdc2(ctx, rt, rs, rd); 15187 } else { 15188 /* OPC_LWC2, OPC_SWC2 */ 15189 /* COP2: Not implemented. */ 15190 generate_exception_err(ctx, EXCP_CpU, 2); 15191 } 15192 break; 15193 case OPC_CP2: 15194 check_insn(ctx, ASE_LMMI); 15195 /* Note that these instructions use different fields. */ 15196 gen_loongson_multimedia(ctx, sa, rd, rt); 15197 break; 15198 15199 case OPC_CP3: 15200 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { 15201 check_cp1_enabled(ctx); 15202 op1 = MASK_CP3(ctx->opcode); 15203 switch (op1) { 15204 case OPC_LUXC1: 15205 case OPC_SUXC1: 15206 check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2); 15207 /* Fallthrough */ 15208 case OPC_LWXC1: 15209 case OPC_LDXC1: 15210 case OPC_SWXC1: 15211 case OPC_SDXC1: 15212 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); 15213 gen_flt3_ldst(ctx, op1, sa, rd, rs, rt); 15214 break; 15215 case OPC_PREFX: 15216 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); 15217 /* Treat as NOP. */ 15218 break; 15219 case OPC_ALNV_PS: 15220 check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2); 15221 /* Fallthrough */ 15222 case OPC_MADD_S: 15223 case OPC_MADD_D: 15224 case OPC_MADD_PS: 15225 case OPC_MSUB_S: 15226 case OPC_MSUB_D: 15227 case OPC_MSUB_PS: 15228 case OPC_NMADD_S: 15229 case OPC_NMADD_D: 15230 case OPC_NMADD_PS: 15231 case OPC_NMSUB_S: 15232 case OPC_NMSUB_D: 15233 case OPC_NMSUB_PS: 15234 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); 15235 gen_flt3_arith(ctx, op1, sa, rs, rd, rt); 15236 break; 15237 default: 15238 MIPS_INVAL("cp3"); 15239 gen_reserved_instruction(ctx); 15240 break; 15241 } 15242 } else { 15243 generate_exception_err(ctx, EXCP_CpU, 1); 15244 } 15245 break; 15246 15247 #if defined(TARGET_MIPS64) 15248 /* MIPS64 opcodes */ 15249 case OPC_LLD: 15250 if (ctx->insn_flags & INSN_R5900) { 15251 check_insn_opc_user_only(ctx, INSN_R5900); 15252 } 15253 /* fall through */ 15254 case OPC_LDL: 15255 case OPC_LDR: 15256 case OPC_LWU: 15257 case OPC_LD: 15258 check_insn(ctx, ISA_MIPS3); 15259 check_mips_64(ctx); 15260 gen_ld(ctx, op, rt, rs, imm); 15261 break; 15262 case OPC_SDL: 15263 case OPC_SDR: 15264 case OPC_SD: 15265 check_insn(ctx, ISA_MIPS3); 15266 check_mips_64(ctx); 15267 gen_st(ctx, op, rt, rs, imm); 15268 break; 15269 case OPC_SCD: 15270 check_insn(ctx, ISA_MIPS3); 15271 if (ctx->insn_flags & INSN_R5900) { 15272 check_insn_opc_user_only(ctx, INSN_R5900); 15273 } 15274 check_mips_64(ctx); 15275 gen_st_cond(ctx, rt, rs, imm, MO_TEUQ, false); 15276 break; 15277 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */ 15278 if (ctx->insn_flags & ISA_MIPS_R6) { 15279 /* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */ 15280 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 15281 } else { 15282 /* OPC_DADDI */ 15283 check_insn(ctx, ISA_MIPS3); 15284 check_mips_64(ctx); 15285 gen_arith_imm(ctx, op, rt, rs, imm); 15286 } 15287 break; 15288 case OPC_DADDIU: 15289 check_insn(ctx, ISA_MIPS3); 15290 check_mips_64(ctx); 15291 gen_arith_imm(ctx, op, rt, rs, imm); 15292 break; 15293 #else 15294 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */ 15295 if (ctx->insn_flags & ISA_MIPS_R6) { 15296 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 15297 } else { 15298 MIPS_INVAL("major opcode"); 15299 gen_reserved_instruction(ctx); 15300 } 15301 break; 15302 #endif 15303 case OPC_DAUI: /* OPC_JALX */ 15304 if (ctx->insn_flags & ISA_MIPS_R6) { 15305 #if defined(TARGET_MIPS64) 15306 /* OPC_DAUI */ 15307 check_mips_64(ctx); 15308 if (rs == 0) { 15309 generate_exception(ctx, EXCP_RI); 15310 } else if (rt != 0) { 15311 TCGv t0 = tcg_temp_new(); 15312 gen_load_gpr(t0, rs); 15313 tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16); 15314 } 15315 #else 15316 gen_reserved_instruction(ctx); 15317 MIPS_INVAL("major opcode"); 15318 #endif 15319 } else { 15320 /* OPC_JALX */ 15321 check_insn(ctx, ASE_MIPS16 | ASE_MICROMIPS); 15322 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; 15323 gen_compute_branch(ctx, op, 4, rs, rt, offset, 4); 15324 } 15325 break; 15326 case OPC_MDMX: 15327 /* MDMX: Not implemented. */ 15328 break; 15329 case OPC_PCREL: 15330 check_insn(ctx, ISA_MIPS_R6); 15331 gen_pcrel(ctx, ctx->opcode, ctx->base.pc_next, rs); 15332 break; 15333 default: /* Invalid */ 15334 MIPS_INVAL("major opcode"); 15335 return false; 15336 } 15337 return true; 15338 } 15339 15340 static void decode_opc(CPUMIPSState *env, DisasContext *ctx) 15341 { 15342 /* make sure instructions are on a word boundary */ 15343 if (ctx->base.pc_next & 0x3) { 15344 env->CP0_BadVAddr = ctx->base.pc_next; 15345 generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL); 15346 return; 15347 } 15348 15349 /* Handle blikely not taken case */ 15350 if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) { 15351 TCGLabel *l1 = gen_new_label(); 15352 15353 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); 15354 tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK); 15355 gen_goto_tb(ctx, 1, ctx->base.pc_next + 4); 15356 gen_set_label(l1); 15357 } 15358 15359 /* Transition to the auto-generated decoder. */ 15360 15361 /* Vendor specific extensions */ 15362 if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opcode)) { 15363 return; 15364 } 15365 if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) { 15366 return; 15367 } 15368 #if defined(TARGET_MIPS64) 15369 if (cpu_supports_isa(env, INSN_OCTEON) && decode_ext_octeon(ctx, ctx->opcode)) { 15370 return; 15371 } 15372 #endif 15373 15374 /* ISA extensions */ 15375 if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) { 15376 return; 15377 } 15378 15379 /* ISA (from latest to oldest) */ 15380 if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->opcode)) { 15381 return; 15382 } 15383 15384 if (decode_opc_legacy(env, ctx)) { 15385 return; 15386 } 15387 15388 gen_reserved_instruction(ctx); 15389 } 15390 15391 static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 15392 { 15393 DisasContext *ctx = container_of(dcbase, DisasContext, base); 15394 CPUMIPSState *env = cs->env_ptr; 15395 15396 ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 15397 ctx->saved_pc = -1; 15398 ctx->insn_flags = env->insn_flags; 15399 ctx->CP0_Config0 = env->CP0_Config0; 15400 ctx->CP0_Config1 = env->CP0_Config1; 15401 ctx->CP0_Config2 = env->CP0_Config2; 15402 ctx->CP0_Config3 = env->CP0_Config3; 15403 ctx->CP0_Config5 = env->CP0_Config5; 15404 ctx->btarget = 0; 15405 ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; 15406 ctx->rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1; 15407 ctx->ie = (env->CP0_Config4 >> CP0C4_IE) & 3; 15408 ctx->bi = (env->CP0_Config3 >> CP0C3_BI) & 1; 15409 ctx->bp = (env->CP0_Config3 >> CP0C3_BP) & 1; 15410 ctx->PAMask = env->PAMask; 15411 ctx->mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1; 15412 ctx->eva = (env->CP0_Config5 >> CP0C5_EVA) & 1; 15413 ctx->sc = (env->CP0_Config3 >> CP0C3_SC) & 1; 15414 ctx->CP0_LLAddr_shift = env->CP0_LLAddr_shift; 15415 ctx->cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1; 15416 /* Restore delay slot state from the tb context. */ 15417 ctx->hflags = (uint32_t)ctx->base.tb->flags; /* FIXME: maybe use 64 bits? */ 15418 ctx->ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1; 15419 ctx->ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) || 15420 (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)); 15421 ctx->vp = (env->CP0_Config5 >> CP0C5_VP) & 1; 15422 ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1; 15423 ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; 15424 ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; 15425 ctx->mi = (env->CP0_Config5 >> CP0C5_MI) & 1; 15426 ctx->gi = (env->CP0_Config5 >> CP0C5_GI) & 3; 15427 restore_cpu_state(env, ctx); 15428 #ifdef CONFIG_USER_ONLY 15429 ctx->mem_idx = MIPS_HFLAG_UM; 15430 #else 15431 ctx->mem_idx = hflags_mmu_index(ctx->hflags); 15432 #endif 15433 ctx->default_tcg_memop_mask = (!(ctx->insn_flags & ISA_NANOMIPS32) && 15434 (ctx->insn_flags & (ISA_MIPS_R6 | 15435 INSN_LOONGSON3A))) ? MO_UNALN : MO_ALIGN; 15436 15437 /* 15438 * Execute a branch and its delay slot as a single instruction. 15439 * This is what GDB expects and is consistent with what the 15440 * hardware does (e.g. if a delay slot instruction faults, the 15441 * reported PC is the PC of the branch). 15442 */ 15443 if (ctx->base.singlestep_enabled && (ctx->hflags & MIPS_HFLAG_BMASK)) { 15444 ctx->base.max_insns = 2; 15445 } 15446 15447 LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, 15448 ctx->hflags); 15449 } 15450 15451 static void mips_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) 15452 { 15453 } 15454 15455 static void mips_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 15456 { 15457 DisasContext *ctx = container_of(dcbase, DisasContext, base); 15458 15459 tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMASK, 15460 ctx->btarget); 15461 } 15462 15463 static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 15464 { 15465 CPUMIPSState *env = cs->env_ptr; 15466 DisasContext *ctx = container_of(dcbase, DisasContext, base); 15467 int insn_bytes; 15468 int is_slot; 15469 15470 is_slot = ctx->hflags & MIPS_HFLAG_BMASK; 15471 if (ctx->insn_flags & ISA_NANOMIPS32) { 15472 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); 15473 insn_bytes = decode_isa_nanomips(env, ctx); 15474 } else if (!(ctx->hflags & MIPS_HFLAG_M16)) { 15475 ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next); 15476 insn_bytes = 4; 15477 decode_opc(env, ctx); 15478 } else if (ctx->insn_flags & ASE_MICROMIPS) { 15479 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); 15480 insn_bytes = decode_isa_micromips(env, ctx); 15481 } else if (ctx->insn_flags & ASE_MIPS16) { 15482 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); 15483 insn_bytes = decode_ase_mips16e(env, ctx); 15484 } else { 15485 gen_reserved_instruction(ctx); 15486 g_assert(ctx->base.is_jmp == DISAS_NORETURN); 15487 return; 15488 } 15489 15490 if (ctx->hflags & MIPS_HFLAG_BMASK) { 15491 if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 | 15492 MIPS_HFLAG_FBNSLOT))) { 15493 /* 15494 * Force to generate branch as there is neither delay nor 15495 * forbidden slot. 15496 */ 15497 is_slot = 1; 15498 } 15499 if ((ctx->hflags & MIPS_HFLAG_M16) && 15500 (ctx->hflags & MIPS_HFLAG_FBNSLOT)) { 15501 /* 15502 * Force to generate branch as microMIPS R6 doesn't restrict 15503 * branches in the forbidden slot. 15504 */ 15505 is_slot = 1; 15506 } 15507 } 15508 if (is_slot) { 15509 gen_branch(ctx, insn_bytes); 15510 } 15511 if (ctx->base.is_jmp == DISAS_SEMIHOST) { 15512 generate_exception_err(ctx, EXCP_SEMIHOST, insn_bytes); 15513 } 15514 ctx->base.pc_next += insn_bytes; 15515 15516 if (ctx->base.is_jmp != DISAS_NEXT) { 15517 return; 15518 } 15519 15520 /* 15521 * End the TB on (most) page crossings. 15522 * See mips_tr_init_disas_context about single-stepping a branch 15523 * together with its delay slot. 15524 */ 15525 if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE 15526 && !ctx->base.singlestep_enabled) { 15527 ctx->base.is_jmp = DISAS_TOO_MANY; 15528 } 15529 } 15530 15531 static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 15532 { 15533 DisasContext *ctx = container_of(dcbase, DisasContext, base); 15534 15535 switch (ctx->base.is_jmp) { 15536 case DISAS_STOP: 15537 gen_save_pc(ctx->base.pc_next); 15538 tcg_gen_lookup_and_goto_ptr(); 15539 break; 15540 case DISAS_NEXT: 15541 case DISAS_TOO_MANY: 15542 save_cpu_state(ctx, 0); 15543 gen_goto_tb(ctx, 0, ctx->base.pc_next); 15544 break; 15545 case DISAS_EXIT: 15546 tcg_gen_exit_tb(NULL, 0); 15547 break; 15548 case DISAS_NORETURN: 15549 break; 15550 default: 15551 g_assert_not_reached(); 15552 } 15553 } 15554 15555 static void mips_tr_disas_log(const DisasContextBase *dcbase, 15556 CPUState *cs, FILE *logfile) 15557 { 15558 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 15559 target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 15560 } 15561 15562 static const TranslatorOps mips_tr_ops = { 15563 .init_disas_context = mips_tr_init_disas_context, 15564 .tb_start = mips_tr_tb_start, 15565 .insn_start = mips_tr_insn_start, 15566 .translate_insn = mips_tr_translate_insn, 15567 .tb_stop = mips_tr_tb_stop, 15568 .disas_log = mips_tr_disas_log, 15569 }; 15570 15571 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 15572 target_ulong pc, void *host_pc) 15573 { 15574 DisasContext ctx; 15575 15576 translator_loop(cs, tb, max_insns, pc, host_pc, &mips_tr_ops, &ctx.base); 15577 } 15578 15579 void mips_tcg_init(void) 15580 { 15581 int i; 15582 15583 cpu_gpr[0] = NULL; 15584 for (i = 1; i < 32; i++) 15585 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 15586 offsetof(CPUMIPSState, 15587 active_tc.gpr[i]), 15588 regnames[i]); 15589 #if defined(TARGET_MIPS64) 15590 cpu_gpr_hi[0] = NULL; 15591 15592 for (unsigned i = 1; i < 32; i++) { 15593 g_autofree char *rname = g_strdup_printf("%s[hi]", regnames[i]); 15594 15595 cpu_gpr_hi[i] = tcg_global_mem_new_i64(cpu_env, 15596 offsetof(CPUMIPSState, 15597 active_tc.gpr_hi[i]), 15598 rname); 15599 } 15600 #endif /* !TARGET_MIPS64 */ 15601 for (i = 0; i < 32; i++) { 15602 int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); 15603 15604 fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]); 15605 } 15606 msa_translate_init(); 15607 cpu_PC = tcg_global_mem_new(cpu_env, 15608 offsetof(CPUMIPSState, active_tc.PC), "PC"); 15609 for (i = 0; i < MIPS_DSP_ACC; i++) { 15610 cpu_HI[i] = tcg_global_mem_new(cpu_env, 15611 offsetof(CPUMIPSState, active_tc.HI[i]), 15612 regnames_HI[i]); 15613 cpu_LO[i] = tcg_global_mem_new(cpu_env, 15614 offsetof(CPUMIPSState, active_tc.LO[i]), 15615 regnames_LO[i]); 15616 } 15617 cpu_dspctrl = tcg_global_mem_new(cpu_env, 15618 offsetof(CPUMIPSState, 15619 active_tc.DSPControl), 15620 "DSPControl"); 15621 bcond = tcg_global_mem_new(cpu_env, 15622 offsetof(CPUMIPSState, bcond), "bcond"); 15623 btarget = tcg_global_mem_new(cpu_env, 15624 offsetof(CPUMIPSState, btarget), "btarget"); 15625 hflags = tcg_global_mem_new_i32(cpu_env, 15626 offsetof(CPUMIPSState, hflags), "hflags"); 15627 15628 fpu_fcr0 = tcg_global_mem_new_i32(cpu_env, 15629 offsetof(CPUMIPSState, active_fpu.fcr0), 15630 "fcr0"); 15631 fpu_fcr31 = tcg_global_mem_new_i32(cpu_env, 15632 offsetof(CPUMIPSState, active_fpu.fcr31), 15633 "fcr31"); 15634 cpu_lladdr = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, lladdr), 15635 "lladdr"); 15636 cpu_llval = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval), 15637 "llval"); 15638 15639 if (TARGET_LONG_BITS == 32) { 15640 mxu_translate_init(); 15641 } 15642 } 15643 15644 void mips_restore_state_to_opc(CPUState *cs, 15645 const TranslationBlock *tb, 15646 const uint64_t *data) 15647 { 15648 MIPSCPU *cpu = MIPS_CPU(cs); 15649 CPUMIPSState *env = &cpu->env; 15650 15651 env->active_tc.PC = data[0]; 15652 env->hflags &= ~MIPS_HFLAG_BMASK; 15653 env->hflags |= data[1]; 15654 switch (env->hflags & MIPS_HFLAG_BMASK_BASE) { 15655 case MIPS_HFLAG_BR: 15656 break; 15657 case MIPS_HFLAG_BC: 15658 case MIPS_HFLAG_BL: 15659 case MIPS_HFLAG_B: 15660 env->btarget = data[2]; 15661 break; 15662 } 15663 } 15664