1 /* 2 * MIPS emulation for QEMU - main translation routines 3 * 4 * Copyright (c) 2004-2005 Jocelyn Mayer 5 * Copyright (c) 2006 Marius Groeger (FPU operations) 6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) 7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) 8 * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) 9 * Copyright (c) 2020 Philippe Mathieu-Daudé 10 * 11 * This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU Lesser General Public 13 * License as published by the Free Software Foundation; either 14 * version 2.1 of the License, or (at your option) any later version. 15 * 16 * This library is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * Lesser General Public License for more details. 20 * 21 * You should have received a copy of the GNU Lesser General Public 22 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "cpu.h" 27 #include "internal.h" 28 #include "tcg/tcg-op.h" 29 #include "exec/translator.h" 30 #include "exec/helper-proto.h" 31 #include "exec/helper-gen.h" 32 #include "semihosting/semihost.h" 33 34 #include "trace.h" 35 #include "exec/log.h" 36 #include "qemu/qemu-print.h" 37 #include "fpu_helper.h" 38 #include "translate.h" 39 40 /* 41 * Many sysemu-only helpers are not reachable for user-only. 42 * Define stub generators here, so that we need not either sprinkle 43 * ifdefs through the translator, nor provide the helper function. 44 */ 45 #define STUB_HELPER(NAME, ...) \ 46 static inline void gen_helper_##NAME(__VA_ARGS__) \ 47 { g_assert_not_reached(); } 48 49 #ifdef CONFIG_USER_ONLY 50 STUB_HELPER(cache, TCGv_env env, TCGv val, TCGv_i32 reg) 51 #endif 52 53 enum { 54 /* indirect opcode tables */ 55 OPC_SPECIAL = (0x00 << 26), 56 OPC_REGIMM = (0x01 << 26), 57 OPC_CP0 = (0x10 << 26), 58 OPC_CP2 = (0x12 << 26), 59 OPC_CP3 = (0x13 << 26), 60 OPC_SPECIAL2 = (0x1C << 26), 61 OPC_SPECIAL3 = (0x1F << 26), 62 /* arithmetic with immediate */ 63 OPC_ADDI = (0x08 << 26), 64 OPC_ADDIU = (0x09 << 26), 65 OPC_SLTI = (0x0A << 26), 66 OPC_SLTIU = (0x0B << 26), 67 /* logic with immediate */ 68 OPC_ANDI = (0x0C << 26), 69 OPC_ORI = (0x0D << 26), 70 OPC_XORI = (0x0E << 26), 71 OPC_LUI = (0x0F << 26), 72 /* arithmetic with immediate */ 73 OPC_DADDI = (0x18 << 26), 74 OPC_DADDIU = (0x19 << 26), 75 /* Jump and branches */ 76 OPC_J = (0x02 << 26), 77 OPC_JAL = (0x03 << 26), 78 OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */ 79 OPC_BEQL = (0x14 << 26), 80 OPC_BNE = (0x05 << 26), 81 OPC_BNEL = (0x15 << 26), 82 OPC_BLEZ = (0x06 << 26), 83 OPC_BLEZL = (0x16 << 26), 84 OPC_BGTZ = (0x07 << 26), 85 OPC_BGTZL = (0x17 << 26), 86 OPC_JALX = (0x1D << 26), 87 OPC_DAUI = (0x1D << 26), 88 /* Load and stores */ 89 OPC_LDL = (0x1A << 26), 90 OPC_LDR = (0x1B << 26), 91 OPC_LB = (0x20 << 26), 92 OPC_LH = (0x21 << 26), 93 OPC_LWL = (0x22 << 26), 94 OPC_LW = (0x23 << 26), 95 OPC_LWPC = OPC_LW | 0x5, 96 OPC_LBU = (0x24 << 26), 97 OPC_LHU = (0x25 << 26), 98 OPC_LWR = (0x26 << 26), 99 OPC_LWU = (0x27 << 26), 100 OPC_SB = (0x28 << 26), 101 OPC_SH = (0x29 << 26), 102 OPC_SWL = (0x2A << 26), 103 OPC_SW = (0x2B << 26), 104 OPC_SDL = (0x2C << 26), 105 OPC_SDR = (0x2D << 26), 106 OPC_SWR = (0x2E << 26), 107 OPC_LL = (0x30 << 26), 108 OPC_LLD = (0x34 << 26), 109 OPC_LD = (0x37 << 26), 110 OPC_LDPC = OPC_LD | 0x5, 111 OPC_SC = (0x38 << 26), 112 OPC_SCD = (0x3C << 26), 113 OPC_SD = (0x3F << 26), 114 /* Floating point load/store */ 115 OPC_LWC1 = (0x31 << 26), 116 OPC_LWC2 = (0x32 << 26), 117 OPC_LDC1 = (0x35 << 26), 118 OPC_LDC2 = (0x36 << 26), 119 OPC_SWC1 = (0x39 << 26), 120 OPC_SWC2 = (0x3A << 26), 121 OPC_SDC1 = (0x3D << 26), 122 OPC_SDC2 = (0x3E << 26), 123 /* Compact Branches */ 124 OPC_BLEZALC = (0x06 << 26), 125 OPC_BGEZALC = (0x06 << 26), 126 OPC_BGEUC = (0x06 << 26), 127 OPC_BGTZALC = (0x07 << 26), 128 OPC_BLTZALC = (0x07 << 26), 129 OPC_BLTUC = (0x07 << 26), 130 OPC_BOVC = (0x08 << 26), 131 OPC_BEQZALC = (0x08 << 26), 132 OPC_BEQC = (0x08 << 26), 133 OPC_BLEZC = (0x16 << 26), 134 OPC_BGEZC = (0x16 << 26), 135 OPC_BGEC = (0x16 << 26), 136 OPC_BGTZC = (0x17 << 26), 137 OPC_BLTZC = (0x17 << 26), 138 OPC_BLTC = (0x17 << 26), 139 OPC_BNVC = (0x18 << 26), 140 OPC_BNEZALC = (0x18 << 26), 141 OPC_BNEC = (0x18 << 26), 142 OPC_BC = (0x32 << 26), 143 OPC_BEQZC = (0x36 << 26), 144 OPC_JIC = (0x36 << 26), 145 OPC_BALC = (0x3A << 26), 146 OPC_BNEZC = (0x3E << 26), 147 OPC_JIALC = (0x3E << 26), 148 /* MDMX ASE specific */ 149 OPC_MDMX = (0x1E << 26), 150 /* Cache and prefetch */ 151 OPC_CACHE = (0x2F << 26), 152 OPC_PREF = (0x33 << 26), 153 /* PC-relative address computation / loads */ 154 OPC_PCREL = (0x3B << 26), 155 }; 156 157 /* PC-relative address computation / loads */ 158 #define MASK_OPC_PCREL_TOP2BITS(op) (MASK_OP_MAJOR(op) | (op & (3 << 19))) 159 #define MASK_OPC_PCREL_TOP5BITS(op) (MASK_OP_MAJOR(op) | (op & (0x1f << 16))) 160 enum { 161 /* Instructions determined by bits 19 and 20 */ 162 OPC_ADDIUPC = OPC_PCREL | (0 << 19), 163 R6_OPC_LWPC = OPC_PCREL | (1 << 19), 164 OPC_LWUPC = OPC_PCREL | (2 << 19), 165 166 /* Instructions determined by bits 16 ... 20 */ 167 OPC_AUIPC = OPC_PCREL | (0x1e << 16), 168 OPC_ALUIPC = OPC_PCREL | (0x1f << 16), 169 170 /* Other */ 171 R6_OPC_LDPC = OPC_PCREL | (6 << 18), 172 }; 173 174 /* MIPS special opcodes */ 175 #define MASK_SPECIAL(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) 176 177 enum { 178 /* Shifts */ 179 OPC_SLL = 0x00 | OPC_SPECIAL, 180 /* NOP is SLL r0, r0, 0 */ 181 /* SSNOP is SLL r0, r0, 1 */ 182 /* EHB is SLL r0, r0, 3 */ 183 OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */ 184 OPC_ROTR = OPC_SRL | (1 << 21), 185 OPC_SRA = 0x03 | OPC_SPECIAL, 186 OPC_SLLV = 0x04 | OPC_SPECIAL, 187 OPC_SRLV = 0x06 | OPC_SPECIAL, /* also ROTRV */ 188 OPC_ROTRV = OPC_SRLV | (1 << 6), 189 OPC_SRAV = 0x07 | OPC_SPECIAL, 190 OPC_DSLLV = 0x14 | OPC_SPECIAL, 191 OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */ 192 OPC_DROTRV = OPC_DSRLV | (1 << 6), 193 OPC_DSRAV = 0x17 | OPC_SPECIAL, 194 OPC_DSLL = 0x38 | OPC_SPECIAL, 195 OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */ 196 OPC_DROTR = OPC_DSRL | (1 << 21), 197 OPC_DSRA = 0x3B | OPC_SPECIAL, 198 OPC_DSLL32 = 0x3C | OPC_SPECIAL, 199 OPC_DSRL32 = 0x3E | OPC_SPECIAL, /* also DROTR32 */ 200 OPC_DROTR32 = OPC_DSRL32 | (1 << 21), 201 OPC_DSRA32 = 0x3F | OPC_SPECIAL, 202 /* Multiplication / division */ 203 OPC_MULT = 0x18 | OPC_SPECIAL, 204 OPC_MULTU = 0x19 | OPC_SPECIAL, 205 OPC_DIV = 0x1A | OPC_SPECIAL, 206 OPC_DIVU = 0x1B | OPC_SPECIAL, 207 OPC_DMULT = 0x1C | OPC_SPECIAL, 208 OPC_DMULTU = 0x1D | OPC_SPECIAL, 209 OPC_DDIV = 0x1E | OPC_SPECIAL, 210 OPC_DDIVU = 0x1F | OPC_SPECIAL, 211 212 /* 2 registers arithmetic / logic */ 213 OPC_ADD = 0x20 | OPC_SPECIAL, 214 OPC_ADDU = 0x21 | OPC_SPECIAL, 215 OPC_SUB = 0x22 | OPC_SPECIAL, 216 OPC_SUBU = 0x23 | OPC_SPECIAL, 217 OPC_AND = 0x24 | OPC_SPECIAL, 218 OPC_OR = 0x25 | OPC_SPECIAL, 219 OPC_XOR = 0x26 | OPC_SPECIAL, 220 OPC_NOR = 0x27 | OPC_SPECIAL, 221 OPC_SLT = 0x2A | OPC_SPECIAL, 222 OPC_SLTU = 0x2B | OPC_SPECIAL, 223 OPC_DADD = 0x2C | OPC_SPECIAL, 224 OPC_DADDU = 0x2D | OPC_SPECIAL, 225 OPC_DSUB = 0x2E | OPC_SPECIAL, 226 OPC_DSUBU = 0x2F | OPC_SPECIAL, 227 /* Jumps */ 228 OPC_JR = 0x08 | OPC_SPECIAL, /* Also JR.HB */ 229 OPC_JALR = 0x09 | OPC_SPECIAL, /* Also JALR.HB */ 230 /* Traps */ 231 OPC_TGE = 0x30 | OPC_SPECIAL, 232 OPC_TGEU = 0x31 | OPC_SPECIAL, 233 OPC_TLT = 0x32 | OPC_SPECIAL, 234 OPC_TLTU = 0x33 | OPC_SPECIAL, 235 OPC_TEQ = 0x34 | OPC_SPECIAL, 236 OPC_TNE = 0x36 | OPC_SPECIAL, 237 /* HI / LO registers load & stores */ 238 OPC_MFHI = 0x10 | OPC_SPECIAL, 239 OPC_MTHI = 0x11 | OPC_SPECIAL, 240 OPC_MFLO = 0x12 | OPC_SPECIAL, 241 OPC_MTLO = 0x13 | OPC_SPECIAL, 242 /* Conditional moves */ 243 OPC_MOVZ = 0x0A | OPC_SPECIAL, 244 OPC_MOVN = 0x0B | OPC_SPECIAL, 245 246 OPC_SELEQZ = 0x35 | OPC_SPECIAL, 247 OPC_SELNEZ = 0x37 | OPC_SPECIAL, 248 249 OPC_MOVCI = 0x01 | OPC_SPECIAL, 250 251 /* Special */ 252 OPC_PMON = 0x05 | OPC_SPECIAL, /* unofficial */ 253 OPC_SYSCALL = 0x0C | OPC_SPECIAL, 254 OPC_BREAK = 0x0D | OPC_SPECIAL, 255 OPC_SPIM = 0x0E | OPC_SPECIAL, /* unofficial */ 256 OPC_SYNC = 0x0F | OPC_SPECIAL, 257 258 OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL, 259 OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL, 260 OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL, 261 OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL, 262 }; 263 264 /* 265 * R6 Multiply and Divide instructions have the same opcode 266 * and function field as legacy OPC_MULT[U]/OPC_DIV[U] 267 */ 268 #define MASK_R6_MULDIV(op) (MASK_SPECIAL(op) | (op & (0x7ff))) 269 270 enum { 271 R6_OPC_MUL = OPC_MULT | (2 << 6), 272 R6_OPC_MUH = OPC_MULT | (3 << 6), 273 R6_OPC_MULU = OPC_MULTU | (2 << 6), 274 R6_OPC_MUHU = OPC_MULTU | (3 << 6), 275 R6_OPC_DIV = OPC_DIV | (2 << 6), 276 R6_OPC_MOD = OPC_DIV | (3 << 6), 277 R6_OPC_DIVU = OPC_DIVU | (2 << 6), 278 R6_OPC_MODU = OPC_DIVU | (3 << 6), 279 280 R6_OPC_DMUL = OPC_DMULT | (2 << 6), 281 R6_OPC_DMUH = OPC_DMULT | (3 << 6), 282 R6_OPC_DMULU = OPC_DMULTU | (2 << 6), 283 R6_OPC_DMUHU = OPC_DMULTU | (3 << 6), 284 R6_OPC_DDIV = OPC_DDIV | (2 << 6), 285 R6_OPC_DMOD = OPC_DDIV | (3 << 6), 286 R6_OPC_DDIVU = OPC_DDIVU | (2 << 6), 287 R6_OPC_DMODU = OPC_DDIVU | (3 << 6), 288 289 R6_OPC_CLZ = 0x10 | OPC_SPECIAL, 290 R6_OPC_CLO = 0x11 | OPC_SPECIAL, 291 R6_OPC_DCLZ = 0x12 | OPC_SPECIAL, 292 R6_OPC_DCLO = 0x13 | OPC_SPECIAL, 293 R6_OPC_SDBBP = 0x0e | OPC_SPECIAL, 294 }; 295 296 /* REGIMM (rt field) opcodes */ 297 #define MASK_REGIMM(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 16))) 298 299 enum { 300 OPC_BLTZ = (0x00 << 16) | OPC_REGIMM, 301 OPC_BLTZL = (0x02 << 16) | OPC_REGIMM, 302 OPC_BGEZ = (0x01 << 16) | OPC_REGIMM, 303 OPC_BGEZL = (0x03 << 16) | OPC_REGIMM, 304 OPC_BLTZAL = (0x10 << 16) | OPC_REGIMM, 305 OPC_BLTZALL = (0x12 << 16) | OPC_REGIMM, 306 OPC_BGEZAL = (0x11 << 16) | OPC_REGIMM, 307 OPC_BGEZALL = (0x13 << 16) | OPC_REGIMM, 308 OPC_TGEI = (0x08 << 16) | OPC_REGIMM, 309 OPC_TGEIU = (0x09 << 16) | OPC_REGIMM, 310 OPC_TLTI = (0x0A << 16) | OPC_REGIMM, 311 OPC_TLTIU = (0x0B << 16) | OPC_REGIMM, 312 OPC_TEQI = (0x0C << 16) | OPC_REGIMM, 313 OPC_TNEI = (0x0E << 16) | OPC_REGIMM, 314 OPC_SIGRIE = (0x17 << 16) | OPC_REGIMM, 315 OPC_SYNCI = (0x1F << 16) | OPC_REGIMM, 316 317 OPC_DAHI = (0x06 << 16) | OPC_REGIMM, 318 OPC_DATI = (0x1e << 16) | OPC_REGIMM, 319 }; 320 321 /* Special2 opcodes */ 322 #define MASK_SPECIAL2(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) 323 324 enum { 325 /* Multiply & xxx operations */ 326 OPC_MADD = 0x00 | OPC_SPECIAL2, 327 OPC_MADDU = 0x01 | OPC_SPECIAL2, 328 OPC_MUL = 0x02 | OPC_SPECIAL2, 329 OPC_MSUB = 0x04 | OPC_SPECIAL2, 330 OPC_MSUBU = 0x05 | OPC_SPECIAL2, 331 /* Loongson 2F */ 332 OPC_MULT_G_2F = 0x10 | OPC_SPECIAL2, 333 OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2, 334 OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2, 335 OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2, 336 OPC_DIV_G_2F = 0x14 | OPC_SPECIAL2, 337 OPC_DDIV_G_2F = 0x15 | OPC_SPECIAL2, 338 OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2, 339 OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2, 340 OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2, 341 OPC_DMOD_G_2F = 0x1d | OPC_SPECIAL2, 342 OPC_MODU_G_2F = 0x1e | OPC_SPECIAL2, 343 OPC_DMODU_G_2F = 0x1f | OPC_SPECIAL2, 344 /* Misc */ 345 OPC_CLZ = 0x20 | OPC_SPECIAL2, 346 OPC_CLO = 0x21 | OPC_SPECIAL2, 347 OPC_DCLZ = 0x24 | OPC_SPECIAL2, 348 OPC_DCLO = 0x25 | OPC_SPECIAL2, 349 /* Special */ 350 OPC_SDBBP = 0x3F | OPC_SPECIAL2, 351 }; 352 353 /* Special3 opcodes */ 354 #define MASK_SPECIAL3(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) 355 356 enum { 357 OPC_EXT = 0x00 | OPC_SPECIAL3, 358 OPC_DEXTM = 0x01 | OPC_SPECIAL3, 359 OPC_DEXTU = 0x02 | OPC_SPECIAL3, 360 OPC_DEXT = 0x03 | OPC_SPECIAL3, 361 OPC_INS = 0x04 | OPC_SPECIAL3, 362 OPC_DINSM = 0x05 | OPC_SPECIAL3, 363 OPC_DINSU = 0x06 | OPC_SPECIAL3, 364 OPC_DINS = 0x07 | OPC_SPECIAL3, 365 OPC_FORK = 0x08 | OPC_SPECIAL3, 366 OPC_YIELD = 0x09 | OPC_SPECIAL3, 367 OPC_BSHFL = 0x20 | OPC_SPECIAL3, 368 OPC_DBSHFL = 0x24 | OPC_SPECIAL3, 369 OPC_RDHWR = 0x3B | OPC_SPECIAL3, 370 OPC_GINV = 0x3D | OPC_SPECIAL3, 371 372 /* Loongson 2E */ 373 OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3, 374 OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3, 375 OPC_DIV_G_2E = 0x1A | OPC_SPECIAL3, 376 OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3, 377 OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3, 378 OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3, 379 OPC_DDIV_G_2E = 0x1E | OPC_SPECIAL3, 380 OPC_DDIVU_G_2E = 0x1F | OPC_SPECIAL3, 381 OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3, 382 OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3, 383 OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3, 384 OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3, 385 386 /* MIPS DSP Load */ 387 OPC_LX_DSP = 0x0A | OPC_SPECIAL3, 388 /* MIPS DSP Arithmetic */ 389 OPC_ADDU_QB_DSP = 0x10 | OPC_SPECIAL3, 390 OPC_ADDU_OB_DSP = 0x14 | OPC_SPECIAL3, 391 OPC_ABSQ_S_PH_DSP = 0x12 | OPC_SPECIAL3, 392 OPC_ABSQ_S_QH_DSP = 0x16 | OPC_SPECIAL3, 393 /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */ 394 /* OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, */ 395 OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3, 396 OPC_CMPU_EQ_OB_DSP = 0x15 | OPC_SPECIAL3, 397 /* MIPS DSP GPR-Based Shift Sub-class */ 398 OPC_SHLL_QB_DSP = 0x13 | OPC_SPECIAL3, 399 OPC_SHLL_OB_DSP = 0x17 | OPC_SPECIAL3, 400 /* MIPS DSP Multiply Sub-class insns */ 401 /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP. */ 402 /* OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, */ 403 OPC_DPA_W_PH_DSP = 0x30 | OPC_SPECIAL3, 404 OPC_DPAQ_W_QH_DSP = 0x34 | OPC_SPECIAL3, 405 /* DSP Bit/Manipulation Sub-class */ 406 OPC_INSV_DSP = 0x0C | OPC_SPECIAL3, 407 OPC_DINSV_DSP = 0x0D | OPC_SPECIAL3, 408 /* MIPS DSP Append Sub-class */ 409 OPC_APPEND_DSP = 0x31 | OPC_SPECIAL3, 410 OPC_DAPPEND_DSP = 0x35 | OPC_SPECIAL3, 411 /* MIPS DSP Accumulator and DSPControl Access Sub-class */ 412 OPC_EXTR_W_DSP = 0x38 | OPC_SPECIAL3, 413 OPC_DEXTR_W_DSP = 0x3C | OPC_SPECIAL3, 414 415 /* EVA */ 416 OPC_LWLE = 0x19 | OPC_SPECIAL3, 417 OPC_LWRE = 0x1A | OPC_SPECIAL3, 418 OPC_CACHEE = 0x1B | OPC_SPECIAL3, 419 OPC_SBE = 0x1C | OPC_SPECIAL3, 420 OPC_SHE = 0x1D | OPC_SPECIAL3, 421 OPC_SCE = 0x1E | OPC_SPECIAL3, 422 OPC_SWE = 0x1F | OPC_SPECIAL3, 423 OPC_SWLE = 0x21 | OPC_SPECIAL3, 424 OPC_SWRE = 0x22 | OPC_SPECIAL3, 425 OPC_PREFE = 0x23 | OPC_SPECIAL3, 426 OPC_LBUE = 0x28 | OPC_SPECIAL3, 427 OPC_LHUE = 0x29 | OPC_SPECIAL3, 428 OPC_LBE = 0x2C | OPC_SPECIAL3, 429 OPC_LHE = 0x2D | OPC_SPECIAL3, 430 OPC_LLE = 0x2E | OPC_SPECIAL3, 431 OPC_LWE = 0x2F | OPC_SPECIAL3, 432 433 /* R6 */ 434 R6_OPC_PREF = 0x35 | OPC_SPECIAL3, 435 R6_OPC_CACHE = 0x25 | OPC_SPECIAL3, 436 R6_OPC_LL = 0x36 | OPC_SPECIAL3, 437 R6_OPC_SC = 0x26 | OPC_SPECIAL3, 438 R6_OPC_LLD = 0x37 | OPC_SPECIAL3, 439 R6_OPC_SCD = 0x27 | OPC_SPECIAL3, 440 }; 441 442 /* Loongson EXT load/store quad word opcodes */ 443 #define MASK_LOONGSON_GSLSQ(op) (MASK_OP_MAJOR(op) | (op & 0x8020)) 444 enum { 445 OPC_GSLQ = 0x0020 | OPC_LWC2, 446 OPC_GSLQC1 = 0x8020 | OPC_LWC2, 447 OPC_GSSHFL = OPC_LWC2, 448 OPC_GSSQ = 0x0020 | OPC_SWC2, 449 OPC_GSSQC1 = 0x8020 | OPC_SWC2, 450 OPC_GSSHFS = OPC_SWC2, 451 }; 452 453 /* Loongson EXT shifted load/store opcodes */ 454 #define MASK_LOONGSON_GSSHFLS(op) (MASK_OP_MAJOR(op) | (op & 0xc03f)) 455 enum { 456 OPC_GSLWLC1 = 0x4 | OPC_GSSHFL, 457 OPC_GSLWRC1 = 0x5 | OPC_GSSHFL, 458 OPC_GSLDLC1 = 0x6 | OPC_GSSHFL, 459 OPC_GSLDRC1 = 0x7 | OPC_GSSHFL, 460 OPC_GSSWLC1 = 0x4 | OPC_GSSHFS, 461 OPC_GSSWRC1 = 0x5 | OPC_GSSHFS, 462 OPC_GSSDLC1 = 0x6 | OPC_GSSHFS, 463 OPC_GSSDRC1 = 0x7 | OPC_GSSHFS, 464 }; 465 466 /* Loongson EXT LDC2/SDC2 opcodes */ 467 #define MASK_LOONGSON_LSDC2(op) (MASK_OP_MAJOR(op) | (op & 0x7)) 468 469 enum { 470 OPC_GSLBX = 0x0 | OPC_LDC2, 471 OPC_GSLHX = 0x1 | OPC_LDC2, 472 OPC_GSLWX = 0x2 | OPC_LDC2, 473 OPC_GSLDX = 0x3 | OPC_LDC2, 474 OPC_GSLWXC1 = 0x6 | OPC_LDC2, 475 OPC_GSLDXC1 = 0x7 | OPC_LDC2, 476 OPC_GSSBX = 0x0 | OPC_SDC2, 477 OPC_GSSHX = 0x1 | OPC_SDC2, 478 OPC_GSSWX = 0x2 | OPC_SDC2, 479 OPC_GSSDX = 0x3 | OPC_SDC2, 480 OPC_GSSWXC1 = 0x6 | OPC_SDC2, 481 OPC_GSSDXC1 = 0x7 | OPC_SDC2, 482 }; 483 484 /* BSHFL opcodes */ 485 #define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 486 487 enum { 488 OPC_WSBH = (0x02 << 6) | OPC_BSHFL, 489 OPC_SEB = (0x10 << 6) | OPC_BSHFL, 490 OPC_SEH = (0x18 << 6) | OPC_BSHFL, 491 OPC_ALIGN = (0x08 << 6) | OPC_BSHFL, /* 010.bp (010.00 to 010.11) */ 492 OPC_ALIGN_1 = (0x09 << 6) | OPC_BSHFL, 493 OPC_ALIGN_2 = (0x0A << 6) | OPC_BSHFL, 494 OPC_ALIGN_3 = (0x0B << 6) | OPC_BSHFL, 495 OPC_BITSWAP = (0x00 << 6) | OPC_BSHFL /* 00000 */ 496 }; 497 498 /* DBSHFL opcodes */ 499 #define MASK_DBSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 500 501 enum { 502 OPC_DSBH = (0x02 << 6) | OPC_DBSHFL, 503 OPC_DSHD = (0x05 << 6) | OPC_DBSHFL, 504 OPC_DALIGN = (0x08 << 6) | OPC_DBSHFL, /* 01.bp (01.000 to 01.111) */ 505 OPC_DALIGN_1 = (0x09 << 6) | OPC_DBSHFL, 506 OPC_DALIGN_2 = (0x0A << 6) | OPC_DBSHFL, 507 OPC_DALIGN_3 = (0x0B << 6) | OPC_DBSHFL, 508 OPC_DALIGN_4 = (0x0C << 6) | OPC_DBSHFL, 509 OPC_DALIGN_5 = (0x0D << 6) | OPC_DBSHFL, 510 OPC_DALIGN_6 = (0x0E << 6) | OPC_DBSHFL, 511 OPC_DALIGN_7 = (0x0F << 6) | OPC_DBSHFL, 512 OPC_DBITSWAP = (0x00 << 6) | OPC_DBSHFL, /* 00000 */ 513 }; 514 515 /* MIPS DSP REGIMM opcodes */ 516 enum { 517 OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM, 518 OPC_BPOSGE64 = (0x1D << 16) | OPC_REGIMM, 519 }; 520 521 #define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 522 /* MIPS DSP Load */ 523 enum { 524 OPC_LBUX = (0x06 << 6) | OPC_LX_DSP, 525 OPC_LHX = (0x04 << 6) | OPC_LX_DSP, 526 OPC_LWX = (0x00 << 6) | OPC_LX_DSP, 527 OPC_LDX = (0x08 << 6) | OPC_LX_DSP, 528 }; 529 530 #define MASK_ADDU_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 531 enum { 532 /* MIPS DSP Arithmetic Sub-class */ 533 OPC_ADDQ_PH = (0x0A << 6) | OPC_ADDU_QB_DSP, 534 OPC_ADDQ_S_PH = (0x0E << 6) | OPC_ADDU_QB_DSP, 535 OPC_ADDQ_S_W = (0x16 << 6) | OPC_ADDU_QB_DSP, 536 OPC_ADDU_QB = (0x00 << 6) | OPC_ADDU_QB_DSP, 537 OPC_ADDU_S_QB = (0x04 << 6) | OPC_ADDU_QB_DSP, 538 OPC_ADDU_PH = (0x08 << 6) | OPC_ADDU_QB_DSP, 539 OPC_ADDU_S_PH = (0x0C << 6) | OPC_ADDU_QB_DSP, 540 OPC_SUBQ_PH = (0x0B << 6) | OPC_ADDU_QB_DSP, 541 OPC_SUBQ_S_PH = (0x0F << 6) | OPC_ADDU_QB_DSP, 542 OPC_SUBQ_S_W = (0x17 << 6) | OPC_ADDU_QB_DSP, 543 OPC_SUBU_QB = (0x01 << 6) | OPC_ADDU_QB_DSP, 544 OPC_SUBU_S_QB = (0x05 << 6) | OPC_ADDU_QB_DSP, 545 OPC_SUBU_PH = (0x09 << 6) | OPC_ADDU_QB_DSP, 546 OPC_SUBU_S_PH = (0x0D << 6) | OPC_ADDU_QB_DSP, 547 OPC_ADDSC = (0x10 << 6) | OPC_ADDU_QB_DSP, 548 OPC_ADDWC = (0x11 << 6) | OPC_ADDU_QB_DSP, 549 OPC_MODSUB = (0x12 << 6) | OPC_ADDU_QB_DSP, 550 OPC_RADDU_W_QB = (0x14 << 6) | OPC_ADDU_QB_DSP, 551 /* MIPS DSP Multiply Sub-class insns */ 552 OPC_MULEU_S_PH_QBL = (0x06 << 6) | OPC_ADDU_QB_DSP, 553 OPC_MULEU_S_PH_QBR = (0x07 << 6) | OPC_ADDU_QB_DSP, 554 OPC_MULQ_RS_PH = (0x1F << 6) | OPC_ADDU_QB_DSP, 555 OPC_MULEQ_S_W_PHL = (0x1C << 6) | OPC_ADDU_QB_DSP, 556 OPC_MULEQ_S_W_PHR = (0x1D << 6) | OPC_ADDU_QB_DSP, 557 OPC_MULQ_S_PH = (0x1E << 6) | OPC_ADDU_QB_DSP, 558 }; 559 560 #define OPC_ADDUH_QB_DSP OPC_MULT_G_2E 561 #define MASK_ADDUH_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 562 enum { 563 /* MIPS DSP Arithmetic Sub-class */ 564 OPC_ADDUH_QB = (0x00 << 6) | OPC_ADDUH_QB_DSP, 565 OPC_ADDUH_R_QB = (0x02 << 6) | OPC_ADDUH_QB_DSP, 566 OPC_ADDQH_PH = (0x08 << 6) | OPC_ADDUH_QB_DSP, 567 OPC_ADDQH_R_PH = (0x0A << 6) | OPC_ADDUH_QB_DSP, 568 OPC_ADDQH_W = (0x10 << 6) | OPC_ADDUH_QB_DSP, 569 OPC_ADDQH_R_W = (0x12 << 6) | OPC_ADDUH_QB_DSP, 570 OPC_SUBUH_QB = (0x01 << 6) | OPC_ADDUH_QB_DSP, 571 OPC_SUBUH_R_QB = (0x03 << 6) | OPC_ADDUH_QB_DSP, 572 OPC_SUBQH_PH = (0x09 << 6) | OPC_ADDUH_QB_DSP, 573 OPC_SUBQH_R_PH = (0x0B << 6) | OPC_ADDUH_QB_DSP, 574 OPC_SUBQH_W = (0x11 << 6) | OPC_ADDUH_QB_DSP, 575 OPC_SUBQH_R_W = (0x13 << 6) | OPC_ADDUH_QB_DSP, 576 /* MIPS DSP Multiply Sub-class insns */ 577 OPC_MUL_PH = (0x0C << 6) | OPC_ADDUH_QB_DSP, 578 OPC_MUL_S_PH = (0x0E << 6) | OPC_ADDUH_QB_DSP, 579 OPC_MULQ_S_W = (0x16 << 6) | OPC_ADDUH_QB_DSP, 580 OPC_MULQ_RS_W = (0x17 << 6) | OPC_ADDUH_QB_DSP, 581 }; 582 583 #define MASK_ABSQ_S_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 584 enum { 585 /* MIPS DSP Arithmetic Sub-class */ 586 OPC_ABSQ_S_QB = (0x01 << 6) | OPC_ABSQ_S_PH_DSP, 587 OPC_ABSQ_S_PH = (0x09 << 6) | OPC_ABSQ_S_PH_DSP, 588 OPC_ABSQ_S_W = (0x11 << 6) | OPC_ABSQ_S_PH_DSP, 589 OPC_PRECEQ_W_PHL = (0x0C << 6) | OPC_ABSQ_S_PH_DSP, 590 OPC_PRECEQ_W_PHR = (0x0D << 6) | OPC_ABSQ_S_PH_DSP, 591 OPC_PRECEQU_PH_QBL = (0x04 << 6) | OPC_ABSQ_S_PH_DSP, 592 OPC_PRECEQU_PH_QBR = (0x05 << 6) | OPC_ABSQ_S_PH_DSP, 593 OPC_PRECEQU_PH_QBLA = (0x06 << 6) | OPC_ABSQ_S_PH_DSP, 594 OPC_PRECEQU_PH_QBRA = (0x07 << 6) | OPC_ABSQ_S_PH_DSP, 595 OPC_PRECEU_PH_QBL = (0x1C << 6) | OPC_ABSQ_S_PH_DSP, 596 OPC_PRECEU_PH_QBR = (0x1D << 6) | OPC_ABSQ_S_PH_DSP, 597 OPC_PRECEU_PH_QBLA = (0x1E << 6) | OPC_ABSQ_S_PH_DSP, 598 OPC_PRECEU_PH_QBRA = (0x1F << 6) | OPC_ABSQ_S_PH_DSP, 599 /* DSP Bit/Manipulation Sub-class */ 600 OPC_BITREV = (0x1B << 6) | OPC_ABSQ_S_PH_DSP, 601 OPC_REPL_QB = (0x02 << 6) | OPC_ABSQ_S_PH_DSP, 602 OPC_REPLV_QB = (0x03 << 6) | OPC_ABSQ_S_PH_DSP, 603 OPC_REPL_PH = (0x0A << 6) | OPC_ABSQ_S_PH_DSP, 604 OPC_REPLV_PH = (0x0B << 6) | OPC_ABSQ_S_PH_DSP, 605 }; 606 607 #define MASK_CMPU_EQ_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 608 enum { 609 /* MIPS DSP Arithmetic Sub-class */ 610 OPC_PRECR_QB_PH = (0x0D << 6) | OPC_CMPU_EQ_QB_DSP, 611 OPC_PRECRQ_QB_PH = (0x0C << 6) | OPC_CMPU_EQ_QB_DSP, 612 OPC_PRECR_SRA_PH_W = (0x1E << 6) | OPC_CMPU_EQ_QB_DSP, 613 OPC_PRECR_SRA_R_PH_W = (0x1F << 6) | OPC_CMPU_EQ_QB_DSP, 614 OPC_PRECRQ_PH_W = (0x14 << 6) | OPC_CMPU_EQ_QB_DSP, 615 OPC_PRECRQ_RS_PH_W = (0x15 << 6) | OPC_CMPU_EQ_QB_DSP, 616 OPC_PRECRQU_S_QB_PH = (0x0F << 6) | OPC_CMPU_EQ_QB_DSP, 617 /* DSP Compare-Pick Sub-class */ 618 OPC_CMPU_EQ_QB = (0x00 << 6) | OPC_CMPU_EQ_QB_DSP, 619 OPC_CMPU_LT_QB = (0x01 << 6) | OPC_CMPU_EQ_QB_DSP, 620 OPC_CMPU_LE_QB = (0x02 << 6) | OPC_CMPU_EQ_QB_DSP, 621 OPC_CMPGU_EQ_QB = (0x04 << 6) | OPC_CMPU_EQ_QB_DSP, 622 OPC_CMPGU_LT_QB = (0x05 << 6) | OPC_CMPU_EQ_QB_DSP, 623 OPC_CMPGU_LE_QB = (0x06 << 6) | OPC_CMPU_EQ_QB_DSP, 624 OPC_CMPGDU_EQ_QB = (0x18 << 6) | OPC_CMPU_EQ_QB_DSP, 625 OPC_CMPGDU_LT_QB = (0x19 << 6) | OPC_CMPU_EQ_QB_DSP, 626 OPC_CMPGDU_LE_QB = (0x1A << 6) | OPC_CMPU_EQ_QB_DSP, 627 OPC_CMP_EQ_PH = (0x08 << 6) | OPC_CMPU_EQ_QB_DSP, 628 OPC_CMP_LT_PH = (0x09 << 6) | OPC_CMPU_EQ_QB_DSP, 629 OPC_CMP_LE_PH = (0x0A << 6) | OPC_CMPU_EQ_QB_DSP, 630 OPC_PICK_QB = (0x03 << 6) | OPC_CMPU_EQ_QB_DSP, 631 OPC_PICK_PH = (0x0B << 6) | OPC_CMPU_EQ_QB_DSP, 632 OPC_PACKRL_PH = (0x0E << 6) | OPC_CMPU_EQ_QB_DSP, 633 }; 634 635 #define MASK_SHLL_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 636 enum { 637 /* MIPS DSP GPR-Based Shift Sub-class */ 638 OPC_SHLL_QB = (0x00 << 6) | OPC_SHLL_QB_DSP, 639 OPC_SHLLV_QB = (0x02 << 6) | OPC_SHLL_QB_DSP, 640 OPC_SHLL_PH = (0x08 << 6) | OPC_SHLL_QB_DSP, 641 OPC_SHLLV_PH = (0x0A << 6) | OPC_SHLL_QB_DSP, 642 OPC_SHLL_S_PH = (0x0C << 6) | OPC_SHLL_QB_DSP, 643 OPC_SHLLV_S_PH = (0x0E << 6) | OPC_SHLL_QB_DSP, 644 OPC_SHLL_S_W = (0x14 << 6) | OPC_SHLL_QB_DSP, 645 OPC_SHLLV_S_W = (0x16 << 6) | OPC_SHLL_QB_DSP, 646 OPC_SHRL_QB = (0x01 << 6) | OPC_SHLL_QB_DSP, 647 OPC_SHRLV_QB = (0x03 << 6) | OPC_SHLL_QB_DSP, 648 OPC_SHRL_PH = (0x19 << 6) | OPC_SHLL_QB_DSP, 649 OPC_SHRLV_PH = (0x1B << 6) | OPC_SHLL_QB_DSP, 650 OPC_SHRA_QB = (0x04 << 6) | OPC_SHLL_QB_DSP, 651 OPC_SHRA_R_QB = (0x05 << 6) | OPC_SHLL_QB_DSP, 652 OPC_SHRAV_QB = (0x06 << 6) | OPC_SHLL_QB_DSP, 653 OPC_SHRAV_R_QB = (0x07 << 6) | OPC_SHLL_QB_DSP, 654 OPC_SHRA_PH = (0x09 << 6) | OPC_SHLL_QB_DSP, 655 OPC_SHRAV_PH = (0x0B << 6) | OPC_SHLL_QB_DSP, 656 OPC_SHRA_R_PH = (0x0D << 6) | OPC_SHLL_QB_DSP, 657 OPC_SHRAV_R_PH = (0x0F << 6) | OPC_SHLL_QB_DSP, 658 OPC_SHRA_R_W = (0x15 << 6) | OPC_SHLL_QB_DSP, 659 OPC_SHRAV_R_W = (0x17 << 6) | OPC_SHLL_QB_DSP, 660 }; 661 662 #define MASK_DPA_W_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 663 enum { 664 /* MIPS DSP Multiply Sub-class insns */ 665 OPC_DPAU_H_QBL = (0x03 << 6) | OPC_DPA_W_PH_DSP, 666 OPC_DPAU_H_QBR = (0x07 << 6) | OPC_DPA_W_PH_DSP, 667 OPC_DPSU_H_QBL = (0x0B << 6) | OPC_DPA_W_PH_DSP, 668 OPC_DPSU_H_QBR = (0x0F << 6) | OPC_DPA_W_PH_DSP, 669 OPC_DPA_W_PH = (0x00 << 6) | OPC_DPA_W_PH_DSP, 670 OPC_DPAX_W_PH = (0x08 << 6) | OPC_DPA_W_PH_DSP, 671 OPC_DPAQ_S_W_PH = (0x04 << 6) | OPC_DPA_W_PH_DSP, 672 OPC_DPAQX_S_W_PH = (0x18 << 6) | OPC_DPA_W_PH_DSP, 673 OPC_DPAQX_SA_W_PH = (0x1A << 6) | OPC_DPA_W_PH_DSP, 674 OPC_DPS_W_PH = (0x01 << 6) | OPC_DPA_W_PH_DSP, 675 OPC_DPSX_W_PH = (0x09 << 6) | OPC_DPA_W_PH_DSP, 676 OPC_DPSQ_S_W_PH = (0x05 << 6) | OPC_DPA_W_PH_DSP, 677 OPC_DPSQX_S_W_PH = (0x19 << 6) | OPC_DPA_W_PH_DSP, 678 OPC_DPSQX_SA_W_PH = (0x1B << 6) | OPC_DPA_W_PH_DSP, 679 OPC_MULSAQ_S_W_PH = (0x06 << 6) | OPC_DPA_W_PH_DSP, 680 OPC_DPAQ_SA_L_W = (0x0C << 6) | OPC_DPA_W_PH_DSP, 681 OPC_DPSQ_SA_L_W = (0x0D << 6) | OPC_DPA_W_PH_DSP, 682 OPC_MAQ_S_W_PHL = (0x14 << 6) | OPC_DPA_W_PH_DSP, 683 OPC_MAQ_S_W_PHR = (0x16 << 6) | OPC_DPA_W_PH_DSP, 684 OPC_MAQ_SA_W_PHL = (0x10 << 6) | OPC_DPA_W_PH_DSP, 685 OPC_MAQ_SA_W_PHR = (0x12 << 6) | OPC_DPA_W_PH_DSP, 686 OPC_MULSA_W_PH = (0x02 << 6) | OPC_DPA_W_PH_DSP, 687 }; 688 689 #define MASK_INSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 690 enum { 691 /* DSP Bit/Manipulation Sub-class */ 692 OPC_INSV = (0x00 << 6) | OPC_INSV_DSP, 693 }; 694 695 #define MASK_APPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 696 enum { 697 /* MIPS DSP Append Sub-class */ 698 OPC_APPEND = (0x00 << 6) | OPC_APPEND_DSP, 699 OPC_PREPEND = (0x01 << 6) | OPC_APPEND_DSP, 700 OPC_BALIGN = (0x10 << 6) | OPC_APPEND_DSP, 701 }; 702 703 #define MASK_EXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 704 enum { 705 /* MIPS DSP Accumulator and DSPControl Access Sub-class */ 706 OPC_EXTR_W = (0x00 << 6) | OPC_EXTR_W_DSP, 707 OPC_EXTR_R_W = (0x04 << 6) | OPC_EXTR_W_DSP, 708 OPC_EXTR_RS_W = (0x06 << 6) | OPC_EXTR_W_DSP, 709 OPC_EXTR_S_H = (0x0E << 6) | OPC_EXTR_W_DSP, 710 OPC_EXTRV_S_H = (0x0F << 6) | OPC_EXTR_W_DSP, 711 OPC_EXTRV_W = (0x01 << 6) | OPC_EXTR_W_DSP, 712 OPC_EXTRV_R_W = (0x05 << 6) | OPC_EXTR_W_DSP, 713 OPC_EXTRV_RS_W = (0x07 << 6) | OPC_EXTR_W_DSP, 714 OPC_EXTP = (0x02 << 6) | OPC_EXTR_W_DSP, 715 OPC_EXTPV = (0x03 << 6) | OPC_EXTR_W_DSP, 716 OPC_EXTPDP = (0x0A << 6) | OPC_EXTR_W_DSP, 717 OPC_EXTPDPV = (0x0B << 6) | OPC_EXTR_W_DSP, 718 OPC_SHILO = (0x1A << 6) | OPC_EXTR_W_DSP, 719 OPC_SHILOV = (0x1B << 6) | OPC_EXTR_W_DSP, 720 OPC_MTHLIP = (0x1F << 6) | OPC_EXTR_W_DSP, 721 OPC_WRDSP = (0x13 << 6) | OPC_EXTR_W_DSP, 722 OPC_RDDSP = (0x12 << 6) | OPC_EXTR_W_DSP, 723 }; 724 725 #define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 726 enum { 727 /* MIPS DSP Arithmetic Sub-class */ 728 OPC_PRECEQ_L_PWL = (0x14 << 6) | OPC_ABSQ_S_QH_DSP, 729 OPC_PRECEQ_L_PWR = (0x15 << 6) | OPC_ABSQ_S_QH_DSP, 730 OPC_PRECEQ_PW_QHL = (0x0C << 6) | OPC_ABSQ_S_QH_DSP, 731 OPC_PRECEQ_PW_QHR = (0x0D << 6) | OPC_ABSQ_S_QH_DSP, 732 OPC_PRECEQ_PW_QHLA = (0x0E << 6) | OPC_ABSQ_S_QH_DSP, 733 OPC_PRECEQ_PW_QHRA = (0x0F << 6) | OPC_ABSQ_S_QH_DSP, 734 OPC_PRECEQU_QH_OBL = (0x04 << 6) | OPC_ABSQ_S_QH_DSP, 735 OPC_PRECEQU_QH_OBR = (0x05 << 6) | OPC_ABSQ_S_QH_DSP, 736 OPC_PRECEQU_QH_OBLA = (0x06 << 6) | OPC_ABSQ_S_QH_DSP, 737 OPC_PRECEQU_QH_OBRA = (0x07 << 6) | OPC_ABSQ_S_QH_DSP, 738 OPC_PRECEU_QH_OBL = (0x1C << 6) | OPC_ABSQ_S_QH_DSP, 739 OPC_PRECEU_QH_OBR = (0x1D << 6) | OPC_ABSQ_S_QH_DSP, 740 OPC_PRECEU_QH_OBLA = (0x1E << 6) | OPC_ABSQ_S_QH_DSP, 741 OPC_PRECEU_QH_OBRA = (0x1F << 6) | OPC_ABSQ_S_QH_DSP, 742 OPC_ABSQ_S_OB = (0x01 << 6) | OPC_ABSQ_S_QH_DSP, 743 OPC_ABSQ_S_PW = (0x11 << 6) | OPC_ABSQ_S_QH_DSP, 744 OPC_ABSQ_S_QH = (0x09 << 6) | OPC_ABSQ_S_QH_DSP, 745 /* DSP Bit/Manipulation Sub-class */ 746 OPC_REPL_OB = (0x02 << 6) | OPC_ABSQ_S_QH_DSP, 747 OPC_REPL_PW = (0x12 << 6) | OPC_ABSQ_S_QH_DSP, 748 OPC_REPL_QH = (0x0A << 6) | OPC_ABSQ_S_QH_DSP, 749 OPC_REPLV_OB = (0x03 << 6) | OPC_ABSQ_S_QH_DSP, 750 OPC_REPLV_PW = (0x13 << 6) | OPC_ABSQ_S_QH_DSP, 751 OPC_REPLV_QH = (0x0B << 6) | OPC_ABSQ_S_QH_DSP, 752 }; 753 754 #define MASK_ADDU_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 755 enum { 756 /* MIPS DSP Multiply Sub-class insns */ 757 OPC_MULEQ_S_PW_QHL = (0x1C << 6) | OPC_ADDU_OB_DSP, 758 OPC_MULEQ_S_PW_QHR = (0x1D << 6) | OPC_ADDU_OB_DSP, 759 OPC_MULEU_S_QH_OBL = (0x06 << 6) | OPC_ADDU_OB_DSP, 760 OPC_MULEU_S_QH_OBR = (0x07 << 6) | OPC_ADDU_OB_DSP, 761 OPC_MULQ_RS_QH = (0x1F << 6) | OPC_ADDU_OB_DSP, 762 /* MIPS DSP Arithmetic Sub-class */ 763 OPC_RADDU_L_OB = (0x14 << 6) | OPC_ADDU_OB_DSP, 764 OPC_SUBQ_PW = (0x13 << 6) | OPC_ADDU_OB_DSP, 765 OPC_SUBQ_S_PW = (0x17 << 6) | OPC_ADDU_OB_DSP, 766 OPC_SUBQ_QH = (0x0B << 6) | OPC_ADDU_OB_DSP, 767 OPC_SUBQ_S_QH = (0x0F << 6) | OPC_ADDU_OB_DSP, 768 OPC_SUBU_OB = (0x01 << 6) | OPC_ADDU_OB_DSP, 769 OPC_SUBU_S_OB = (0x05 << 6) | OPC_ADDU_OB_DSP, 770 OPC_SUBU_QH = (0x09 << 6) | OPC_ADDU_OB_DSP, 771 OPC_SUBU_S_QH = (0x0D << 6) | OPC_ADDU_OB_DSP, 772 OPC_SUBUH_OB = (0x19 << 6) | OPC_ADDU_OB_DSP, 773 OPC_SUBUH_R_OB = (0x1B << 6) | OPC_ADDU_OB_DSP, 774 OPC_ADDQ_PW = (0x12 << 6) | OPC_ADDU_OB_DSP, 775 OPC_ADDQ_S_PW = (0x16 << 6) | OPC_ADDU_OB_DSP, 776 OPC_ADDQ_QH = (0x0A << 6) | OPC_ADDU_OB_DSP, 777 OPC_ADDQ_S_QH = (0x0E << 6) | OPC_ADDU_OB_DSP, 778 OPC_ADDU_OB = (0x00 << 6) | OPC_ADDU_OB_DSP, 779 OPC_ADDU_S_OB = (0x04 << 6) | OPC_ADDU_OB_DSP, 780 OPC_ADDU_QH = (0x08 << 6) | OPC_ADDU_OB_DSP, 781 OPC_ADDU_S_QH = (0x0C << 6) | OPC_ADDU_OB_DSP, 782 OPC_ADDUH_OB = (0x18 << 6) | OPC_ADDU_OB_DSP, 783 OPC_ADDUH_R_OB = (0x1A << 6) | OPC_ADDU_OB_DSP, 784 }; 785 786 #define MASK_CMPU_EQ_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 787 enum { 788 /* DSP Compare-Pick Sub-class */ 789 OPC_CMP_EQ_PW = (0x10 << 6) | OPC_CMPU_EQ_OB_DSP, 790 OPC_CMP_LT_PW = (0x11 << 6) | OPC_CMPU_EQ_OB_DSP, 791 OPC_CMP_LE_PW = (0x12 << 6) | OPC_CMPU_EQ_OB_DSP, 792 OPC_CMP_EQ_QH = (0x08 << 6) | OPC_CMPU_EQ_OB_DSP, 793 OPC_CMP_LT_QH = (0x09 << 6) | OPC_CMPU_EQ_OB_DSP, 794 OPC_CMP_LE_QH = (0x0A << 6) | OPC_CMPU_EQ_OB_DSP, 795 OPC_CMPGDU_EQ_OB = (0x18 << 6) | OPC_CMPU_EQ_OB_DSP, 796 OPC_CMPGDU_LT_OB = (0x19 << 6) | OPC_CMPU_EQ_OB_DSP, 797 OPC_CMPGDU_LE_OB = (0x1A << 6) | OPC_CMPU_EQ_OB_DSP, 798 OPC_CMPGU_EQ_OB = (0x04 << 6) | OPC_CMPU_EQ_OB_DSP, 799 OPC_CMPGU_LT_OB = (0x05 << 6) | OPC_CMPU_EQ_OB_DSP, 800 OPC_CMPGU_LE_OB = (0x06 << 6) | OPC_CMPU_EQ_OB_DSP, 801 OPC_CMPU_EQ_OB = (0x00 << 6) | OPC_CMPU_EQ_OB_DSP, 802 OPC_CMPU_LT_OB = (0x01 << 6) | OPC_CMPU_EQ_OB_DSP, 803 OPC_CMPU_LE_OB = (0x02 << 6) | OPC_CMPU_EQ_OB_DSP, 804 OPC_PACKRL_PW = (0x0E << 6) | OPC_CMPU_EQ_OB_DSP, 805 OPC_PICK_OB = (0x03 << 6) | OPC_CMPU_EQ_OB_DSP, 806 OPC_PICK_PW = (0x13 << 6) | OPC_CMPU_EQ_OB_DSP, 807 OPC_PICK_QH = (0x0B << 6) | OPC_CMPU_EQ_OB_DSP, 808 /* MIPS DSP Arithmetic Sub-class */ 809 OPC_PRECR_OB_QH = (0x0D << 6) | OPC_CMPU_EQ_OB_DSP, 810 OPC_PRECR_SRA_QH_PW = (0x1E << 6) | OPC_CMPU_EQ_OB_DSP, 811 OPC_PRECR_SRA_R_QH_PW = (0x1F << 6) | OPC_CMPU_EQ_OB_DSP, 812 OPC_PRECRQ_OB_QH = (0x0C << 6) | OPC_CMPU_EQ_OB_DSP, 813 OPC_PRECRQ_PW_L = (0x1C << 6) | OPC_CMPU_EQ_OB_DSP, 814 OPC_PRECRQ_QH_PW = (0x14 << 6) | OPC_CMPU_EQ_OB_DSP, 815 OPC_PRECRQ_RS_QH_PW = (0x15 << 6) | OPC_CMPU_EQ_OB_DSP, 816 OPC_PRECRQU_S_OB_QH = (0x0F << 6) | OPC_CMPU_EQ_OB_DSP, 817 }; 818 819 #define MASK_DAPPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 820 enum { 821 /* DSP Append Sub-class */ 822 OPC_DAPPEND = (0x00 << 6) | OPC_DAPPEND_DSP, 823 OPC_PREPENDD = (0x03 << 6) | OPC_DAPPEND_DSP, 824 OPC_PREPENDW = (0x01 << 6) | OPC_DAPPEND_DSP, 825 OPC_DBALIGN = (0x10 << 6) | OPC_DAPPEND_DSP, 826 }; 827 828 #define MASK_DEXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 829 enum { 830 /* MIPS DSP Accumulator and DSPControl Access Sub-class */ 831 OPC_DMTHLIP = (0x1F << 6) | OPC_DEXTR_W_DSP, 832 OPC_DSHILO = (0x1A << 6) | OPC_DEXTR_W_DSP, 833 OPC_DEXTP = (0x02 << 6) | OPC_DEXTR_W_DSP, 834 OPC_DEXTPDP = (0x0A << 6) | OPC_DEXTR_W_DSP, 835 OPC_DEXTPDPV = (0x0B << 6) | OPC_DEXTR_W_DSP, 836 OPC_DEXTPV = (0x03 << 6) | OPC_DEXTR_W_DSP, 837 OPC_DEXTR_L = (0x10 << 6) | OPC_DEXTR_W_DSP, 838 OPC_DEXTR_R_L = (0x14 << 6) | OPC_DEXTR_W_DSP, 839 OPC_DEXTR_RS_L = (0x16 << 6) | OPC_DEXTR_W_DSP, 840 OPC_DEXTR_W = (0x00 << 6) | OPC_DEXTR_W_DSP, 841 OPC_DEXTR_R_W = (0x04 << 6) | OPC_DEXTR_W_DSP, 842 OPC_DEXTR_RS_W = (0x06 << 6) | OPC_DEXTR_W_DSP, 843 OPC_DEXTR_S_H = (0x0E << 6) | OPC_DEXTR_W_DSP, 844 OPC_DEXTRV_L = (0x11 << 6) | OPC_DEXTR_W_DSP, 845 OPC_DEXTRV_R_L = (0x15 << 6) | OPC_DEXTR_W_DSP, 846 OPC_DEXTRV_RS_L = (0x17 << 6) | OPC_DEXTR_W_DSP, 847 OPC_DEXTRV_S_H = (0x0F << 6) | OPC_DEXTR_W_DSP, 848 OPC_DEXTRV_W = (0x01 << 6) | OPC_DEXTR_W_DSP, 849 OPC_DEXTRV_R_W = (0x05 << 6) | OPC_DEXTR_W_DSP, 850 OPC_DEXTRV_RS_W = (0x07 << 6) | OPC_DEXTR_W_DSP, 851 OPC_DSHILOV = (0x1B << 6) | OPC_DEXTR_W_DSP, 852 }; 853 854 #define MASK_DINSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 855 enum { 856 /* DSP Bit/Manipulation Sub-class */ 857 OPC_DINSV = (0x00 << 6) | OPC_DINSV_DSP, 858 }; 859 860 #define MASK_DPAQ_W_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 861 enum { 862 /* MIPS DSP Multiply Sub-class insns */ 863 OPC_DMADD = (0x19 << 6) | OPC_DPAQ_W_QH_DSP, 864 OPC_DMADDU = (0x1D << 6) | OPC_DPAQ_W_QH_DSP, 865 OPC_DMSUB = (0x1B << 6) | OPC_DPAQ_W_QH_DSP, 866 OPC_DMSUBU = (0x1F << 6) | OPC_DPAQ_W_QH_DSP, 867 OPC_DPA_W_QH = (0x00 << 6) | OPC_DPAQ_W_QH_DSP, 868 OPC_DPAQ_S_W_QH = (0x04 << 6) | OPC_DPAQ_W_QH_DSP, 869 OPC_DPAQ_SA_L_PW = (0x0C << 6) | OPC_DPAQ_W_QH_DSP, 870 OPC_DPAU_H_OBL = (0x03 << 6) | OPC_DPAQ_W_QH_DSP, 871 OPC_DPAU_H_OBR = (0x07 << 6) | OPC_DPAQ_W_QH_DSP, 872 OPC_DPS_W_QH = (0x01 << 6) | OPC_DPAQ_W_QH_DSP, 873 OPC_DPSQ_S_W_QH = (0x05 << 6) | OPC_DPAQ_W_QH_DSP, 874 OPC_DPSQ_SA_L_PW = (0x0D << 6) | OPC_DPAQ_W_QH_DSP, 875 OPC_DPSU_H_OBL = (0x0B << 6) | OPC_DPAQ_W_QH_DSP, 876 OPC_DPSU_H_OBR = (0x0F << 6) | OPC_DPAQ_W_QH_DSP, 877 OPC_MAQ_S_L_PWL = (0x1C << 6) | OPC_DPAQ_W_QH_DSP, 878 OPC_MAQ_S_L_PWR = (0x1E << 6) | OPC_DPAQ_W_QH_DSP, 879 OPC_MAQ_S_W_QHLL = (0x14 << 6) | OPC_DPAQ_W_QH_DSP, 880 OPC_MAQ_SA_W_QHLL = (0x10 << 6) | OPC_DPAQ_W_QH_DSP, 881 OPC_MAQ_S_W_QHLR = (0x15 << 6) | OPC_DPAQ_W_QH_DSP, 882 OPC_MAQ_SA_W_QHLR = (0x11 << 6) | OPC_DPAQ_W_QH_DSP, 883 OPC_MAQ_S_W_QHRL = (0x16 << 6) | OPC_DPAQ_W_QH_DSP, 884 OPC_MAQ_SA_W_QHRL = (0x12 << 6) | OPC_DPAQ_W_QH_DSP, 885 OPC_MAQ_S_W_QHRR = (0x17 << 6) | OPC_DPAQ_W_QH_DSP, 886 OPC_MAQ_SA_W_QHRR = (0x13 << 6) | OPC_DPAQ_W_QH_DSP, 887 OPC_MULSAQ_S_L_PW = (0x0E << 6) | OPC_DPAQ_W_QH_DSP, 888 OPC_MULSAQ_S_W_QH = (0x06 << 6) | OPC_DPAQ_W_QH_DSP, 889 }; 890 891 #define MASK_SHLL_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 892 enum { 893 /* MIPS DSP GPR-Based Shift Sub-class */ 894 OPC_SHLL_PW = (0x10 << 6) | OPC_SHLL_OB_DSP, 895 OPC_SHLL_S_PW = (0x14 << 6) | OPC_SHLL_OB_DSP, 896 OPC_SHLLV_OB = (0x02 << 6) | OPC_SHLL_OB_DSP, 897 OPC_SHLLV_PW = (0x12 << 6) | OPC_SHLL_OB_DSP, 898 OPC_SHLLV_S_PW = (0x16 << 6) | OPC_SHLL_OB_DSP, 899 OPC_SHLLV_QH = (0x0A << 6) | OPC_SHLL_OB_DSP, 900 OPC_SHLLV_S_QH = (0x0E << 6) | OPC_SHLL_OB_DSP, 901 OPC_SHRA_PW = (0x11 << 6) | OPC_SHLL_OB_DSP, 902 OPC_SHRA_R_PW = (0x15 << 6) | OPC_SHLL_OB_DSP, 903 OPC_SHRAV_OB = (0x06 << 6) | OPC_SHLL_OB_DSP, 904 OPC_SHRAV_R_OB = (0x07 << 6) | OPC_SHLL_OB_DSP, 905 OPC_SHRAV_PW = (0x13 << 6) | OPC_SHLL_OB_DSP, 906 OPC_SHRAV_R_PW = (0x17 << 6) | OPC_SHLL_OB_DSP, 907 OPC_SHRAV_QH = (0x0B << 6) | OPC_SHLL_OB_DSP, 908 OPC_SHRAV_R_QH = (0x0F << 6) | OPC_SHLL_OB_DSP, 909 OPC_SHRLV_OB = (0x03 << 6) | OPC_SHLL_OB_DSP, 910 OPC_SHRLV_QH = (0x1B << 6) | OPC_SHLL_OB_DSP, 911 OPC_SHLL_OB = (0x00 << 6) | OPC_SHLL_OB_DSP, 912 OPC_SHLL_QH = (0x08 << 6) | OPC_SHLL_OB_DSP, 913 OPC_SHLL_S_QH = (0x0C << 6) | OPC_SHLL_OB_DSP, 914 OPC_SHRA_OB = (0x04 << 6) | OPC_SHLL_OB_DSP, 915 OPC_SHRA_R_OB = (0x05 << 6) | OPC_SHLL_OB_DSP, 916 OPC_SHRA_QH = (0x09 << 6) | OPC_SHLL_OB_DSP, 917 OPC_SHRA_R_QH = (0x0D << 6) | OPC_SHLL_OB_DSP, 918 OPC_SHRL_OB = (0x01 << 6) | OPC_SHLL_OB_DSP, 919 OPC_SHRL_QH = (0x19 << 6) | OPC_SHLL_OB_DSP, 920 }; 921 922 /* Coprocessor 0 (rs field) */ 923 #define MASK_CP0(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21))) 924 925 enum { 926 OPC_MFC0 = (0x00 << 21) | OPC_CP0, 927 OPC_DMFC0 = (0x01 << 21) | OPC_CP0, 928 OPC_MFHC0 = (0x02 << 21) | OPC_CP0, 929 OPC_MTC0 = (0x04 << 21) | OPC_CP0, 930 OPC_DMTC0 = (0x05 << 21) | OPC_CP0, 931 OPC_MTHC0 = (0x06 << 21) | OPC_CP0, 932 OPC_MFTR = (0x08 << 21) | OPC_CP0, 933 OPC_RDPGPR = (0x0A << 21) | OPC_CP0, 934 OPC_MFMC0 = (0x0B << 21) | OPC_CP0, 935 OPC_MTTR = (0x0C << 21) | OPC_CP0, 936 OPC_WRPGPR = (0x0E << 21) | OPC_CP0, 937 OPC_C0 = (0x10 << 21) | OPC_CP0, 938 OPC_C0_1 = (0x11 << 21) | OPC_CP0, 939 OPC_C0_2 = (0x12 << 21) | OPC_CP0, 940 OPC_C0_3 = (0x13 << 21) | OPC_CP0, 941 OPC_C0_4 = (0x14 << 21) | OPC_CP0, 942 OPC_C0_5 = (0x15 << 21) | OPC_CP0, 943 OPC_C0_6 = (0x16 << 21) | OPC_CP0, 944 OPC_C0_7 = (0x17 << 21) | OPC_CP0, 945 OPC_C0_8 = (0x18 << 21) | OPC_CP0, 946 OPC_C0_9 = (0x19 << 21) | OPC_CP0, 947 OPC_C0_A = (0x1A << 21) | OPC_CP0, 948 OPC_C0_B = (0x1B << 21) | OPC_CP0, 949 OPC_C0_C = (0x1C << 21) | OPC_CP0, 950 OPC_C0_D = (0x1D << 21) | OPC_CP0, 951 OPC_C0_E = (0x1E << 21) | OPC_CP0, 952 OPC_C0_F = (0x1F << 21) | OPC_CP0, 953 }; 954 955 /* MFMC0 opcodes */ 956 #define MASK_MFMC0(op) (MASK_CP0(op) | (op & 0xFFFF)) 957 958 enum { 959 OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0, 960 OPC_EMT = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0, 961 OPC_DVPE = 0x01 | (0 << 5) | OPC_MFMC0, 962 OPC_EVPE = 0x01 | (1 << 5) | OPC_MFMC0, 963 OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0, 964 OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0, 965 OPC_DVP = 0x04 | (0 << 3) | (1 << 5) | (0 << 11) | OPC_MFMC0, 966 OPC_EVP = 0x04 | (0 << 3) | (0 << 5) | (0 << 11) | OPC_MFMC0, 967 }; 968 969 /* Coprocessor 0 (with rs == C0) */ 970 #define MASK_C0(op) (MASK_CP0(op) | (op & 0x3F)) 971 972 enum { 973 OPC_TLBR = 0x01 | OPC_C0, 974 OPC_TLBWI = 0x02 | OPC_C0, 975 OPC_TLBINV = 0x03 | OPC_C0, 976 OPC_TLBINVF = 0x04 | OPC_C0, 977 OPC_TLBWR = 0x06 | OPC_C0, 978 OPC_TLBP = 0x08 | OPC_C0, 979 OPC_RFE = 0x10 | OPC_C0, 980 OPC_ERET = 0x18 | OPC_C0, 981 OPC_DERET = 0x1F | OPC_C0, 982 OPC_WAIT = 0x20 | OPC_C0, 983 }; 984 985 #define MASK_CP2(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21))) 986 987 enum { 988 OPC_MFC2 = (0x00 << 21) | OPC_CP2, 989 OPC_DMFC2 = (0x01 << 21) | OPC_CP2, 990 OPC_CFC2 = (0x02 << 21) | OPC_CP2, 991 OPC_MFHC2 = (0x03 << 21) | OPC_CP2, 992 OPC_MTC2 = (0x04 << 21) | OPC_CP2, 993 OPC_DMTC2 = (0x05 << 21) | OPC_CP2, 994 OPC_CTC2 = (0x06 << 21) | OPC_CP2, 995 OPC_MTHC2 = (0x07 << 21) | OPC_CP2, 996 OPC_BC2 = (0x08 << 21) | OPC_CP2, 997 OPC_BC2EQZ = (0x09 << 21) | OPC_CP2, 998 OPC_BC2NEZ = (0x0D << 21) | OPC_CP2, 999 }; 1000 1001 #define MASK_LMMI(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F)) 1002 1003 enum { 1004 OPC_PADDSH = (24 << 21) | (0x00) | OPC_CP2, 1005 OPC_PADDUSH = (25 << 21) | (0x00) | OPC_CP2, 1006 OPC_PADDH = (26 << 21) | (0x00) | OPC_CP2, 1007 OPC_PADDW = (27 << 21) | (0x00) | OPC_CP2, 1008 OPC_PADDSB = (28 << 21) | (0x00) | OPC_CP2, 1009 OPC_PADDUSB = (29 << 21) | (0x00) | OPC_CP2, 1010 OPC_PADDB = (30 << 21) | (0x00) | OPC_CP2, 1011 OPC_PADDD = (31 << 21) | (0x00) | OPC_CP2, 1012 1013 OPC_PSUBSH = (24 << 21) | (0x01) | OPC_CP2, 1014 OPC_PSUBUSH = (25 << 21) | (0x01) | OPC_CP2, 1015 OPC_PSUBH = (26 << 21) | (0x01) | OPC_CP2, 1016 OPC_PSUBW = (27 << 21) | (0x01) | OPC_CP2, 1017 OPC_PSUBSB = (28 << 21) | (0x01) | OPC_CP2, 1018 OPC_PSUBUSB = (29 << 21) | (0x01) | OPC_CP2, 1019 OPC_PSUBB = (30 << 21) | (0x01) | OPC_CP2, 1020 OPC_PSUBD = (31 << 21) | (0x01) | OPC_CP2, 1021 1022 OPC_PSHUFH = (24 << 21) | (0x02) | OPC_CP2, 1023 OPC_PACKSSWH = (25 << 21) | (0x02) | OPC_CP2, 1024 OPC_PACKSSHB = (26 << 21) | (0x02) | OPC_CP2, 1025 OPC_PACKUSHB = (27 << 21) | (0x02) | OPC_CP2, 1026 OPC_XOR_CP2 = (28 << 21) | (0x02) | OPC_CP2, 1027 OPC_NOR_CP2 = (29 << 21) | (0x02) | OPC_CP2, 1028 OPC_AND_CP2 = (30 << 21) | (0x02) | OPC_CP2, 1029 OPC_PANDN = (31 << 21) | (0x02) | OPC_CP2, 1030 1031 OPC_PUNPCKLHW = (24 << 21) | (0x03) | OPC_CP2, 1032 OPC_PUNPCKHHW = (25 << 21) | (0x03) | OPC_CP2, 1033 OPC_PUNPCKLBH = (26 << 21) | (0x03) | OPC_CP2, 1034 OPC_PUNPCKHBH = (27 << 21) | (0x03) | OPC_CP2, 1035 OPC_PINSRH_0 = (28 << 21) | (0x03) | OPC_CP2, 1036 OPC_PINSRH_1 = (29 << 21) | (0x03) | OPC_CP2, 1037 OPC_PINSRH_2 = (30 << 21) | (0x03) | OPC_CP2, 1038 OPC_PINSRH_3 = (31 << 21) | (0x03) | OPC_CP2, 1039 1040 OPC_PAVGH = (24 << 21) | (0x08) | OPC_CP2, 1041 OPC_PAVGB = (25 << 21) | (0x08) | OPC_CP2, 1042 OPC_PMAXSH = (26 << 21) | (0x08) | OPC_CP2, 1043 OPC_PMINSH = (27 << 21) | (0x08) | OPC_CP2, 1044 OPC_PMAXUB = (28 << 21) | (0x08) | OPC_CP2, 1045 OPC_PMINUB = (29 << 21) | (0x08) | OPC_CP2, 1046 1047 OPC_PCMPEQW = (24 << 21) | (0x09) | OPC_CP2, 1048 OPC_PCMPGTW = (25 << 21) | (0x09) | OPC_CP2, 1049 OPC_PCMPEQH = (26 << 21) | (0x09) | OPC_CP2, 1050 OPC_PCMPGTH = (27 << 21) | (0x09) | OPC_CP2, 1051 OPC_PCMPEQB = (28 << 21) | (0x09) | OPC_CP2, 1052 OPC_PCMPGTB = (29 << 21) | (0x09) | OPC_CP2, 1053 1054 OPC_PSLLW = (24 << 21) | (0x0A) | OPC_CP2, 1055 OPC_PSLLH = (25 << 21) | (0x0A) | OPC_CP2, 1056 OPC_PMULLH = (26 << 21) | (0x0A) | OPC_CP2, 1057 OPC_PMULHH = (27 << 21) | (0x0A) | OPC_CP2, 1058 OPC_PMULUW = (28 << 21) | (0x0A) | OPC_CP2, 1059 OPC_PMULHUH = (29 << 21) | (0x0A) | OPC_CP2, 1060 1061 OPC_PSRLW = (24 << 21) | (0x0B) | OPC_CP2, 1062 OPC_PSRLH = (25 << 21) | (0x0B) | OPC_CP2, 1063 OPC_PSRAW = (26 << 21) | (0x0B) | OPC_CP2, 1064 OPC_PSRAH = (27 << 21) | (0x0B) | OPC_CP2, 1065 OPC_PUNPCKLWD = (28 << 21) | (0x0B) | OPC_CP2, 1066 OPC_PUNPCKHWD = (29 << 21) | (0x0B) | OPC_CP2, 1067 1068 OPC_ADDU_CP2 = (24 << 21) | (0x0C) | OPC_CP2, 1069 OPC_OR_CP2 = (25 << 21) | (0x0C) | OPC_CP2, 1070 OPC_ADD_CP2 = (26 << 21) | (0x0C) | OPC_CP2, 1071 OPC_DADD_CP2 = (27 << 21) | (0x0C) | OPC_CP2, 1072 OPC_SEQU_CP2 = (28 << 21) | (0x0C) | OPC_CP2, 1073 OPC_SEQ_CP2 = (29 << 21) | (0x0C) | OPC_CP2, 1074 1075 OPC_SUBU_CP2 = (24 << 21) | (0x0D) | OPC_CP2, 1076 OPC_PASUBUB = (25 << 21) | (0x0D) | OPC_CP2, 1077 OPC_SUB_CP2 = (26 << 21) | (0x0D) | OPC_CP2, 1078 OPC_DSUB_CP2 = (27 << 21) | (0x0D) | OPC_CP2, 1079 OPC_SLTU_CP2 = (28 << 21) | (0x0D) | OPC_CP2, 1080 OPC_SLT_CP2 = (29 << 21) | (0x0D) | OPC_CP2, 1081 1082 OPC_SLL_CP2 = (24 << 21) | (0x0E) | OPC_CP2, 1083 OPC_DSLL_CP2 = (25 << 21) | (0x0E) | OPC_CP2, 1084 OPC_PEXTRH = (26 << 21) | (0x0E) | OPC_CP2, 1085 OPC_PMADDHW = (27 << 21) | (0x0E) | OPC_CP2, 1086 OPC_SLEU_CP2 = (28 << 21) | (0x0E) | OPC_CP2, 1087 OPC_SLE_CP2 = (29 << 21) | (0x0E) | OPC_CP2, 1088 1089 OPC_SRL_CP2 = (24 << 21) | (0x0F) | OPC_CP2, 1090 OPC_DSRL_CP2 = (25 << 21) | (0x0F) | OPC_CP2, 1091 OPC_SRA_CP2 = (26 << 21) | (0x0F) | OPC_CP2, 1092 OPC_DSRA_CP2 = (27 << 21) | (0x0F) | OPC_CP2, 1093 OPC_BIADD = (28 << 21) | (0x0F) | OPC_CP2, 1094 OPC_PMOVMSKB = (29 << 21) | (0x0F) | OPC_CP2, 1095 }; 1096 1097 1098 #define MASK_CP3(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) 1099 1100 enum { 1101 OPC_LWXC1 = 0x00 | OPC_CP3, 1102 OPC_LDXC1 = 0x01 | OPC_CP3, 1103 OPC_LUXC1 = 0x05 | OPC_CP3, 1104 OPC_SWXC1 = 0x08 | OPC_CP3, 1105 OPC_SDXC1 = 0x09 | OPC_CP3, 1106 OPC_SUXC1 = 0x0D | OPC_CP3, 1107 OPC_PREFX = 0x0F | OPC_CP3, 1108 OPC_ALNV_PS = 0x1E | OPC_CP3, 1109 OPC_MADD_S = 0x20 | OPC_CP3, 1110 OPC_MADD_D = 0x21 | OPC_CP3, 1111 OPC_MADD_PS = 0x26 | OPC_CP3, 1112 OPC_MSUB_S = 0x28 | OPC_CP3, 1113 OPC_MSUB_D = 0x29 | OPC_CP3, 1114 OPC_MSUB_PS = 0x2E | OPC_CP3, 1115 OPC_NMADD_S = 0x30 | OPC_CP3, 1116 OPC_NMADD_D = 0x31 | OPC_CP3, 1117 OPC_NMADD_PS = 0x36 | OPC_CP3, 1118 OPC_NMSUB_S = 0x38 | OPC_CP3, 1119 OPC_NMSUB_D = 0x39 | OPC_CP3, 1120 OPC_NMSUB_PS = 0x3E | OPC_CP3, 1121 }; 1122 1123 /* 1124 * MMI (MultiMedia Instruction) encodings 1125 * ====================================== 1126 * 1127 * MMI instructions encoding table keys: 1128 * 1129 * * This code is reserved for future use. An attempt to execute it 1130 * causes a Reserved Instruction exception. 1131 * % This code indicates an instruction class. The instruction word 1132 * must be further decoded by examining additional tables that show 1133 * the values for other instruction fields. 1134 * # This code is reserved for the unsupported instructions DMULT, 1135 * DMULTU, DDIV, DDIVU, LL, LLD, SC, SCD, LWC2 and SWC2. An attempt 1136 * to execute it causes a Reserved Instruction exception. 1137 * 1138 * MMI instructions encoded by opcode field (MMI, LQ, SQ): 1139 * 1140 * 31 26 0 1141 * +--------+----------------------------------------+ 1142 * | opcode | | 1143 * +--------+----------------------------------------+ 1144 * 1145 * opcode bits 28..26 1146 * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 1147 * 31..29 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 1148 * -------+-------+-------+-------+-------+-------+-------+-------+------- 1149 * 0 000 |SPECIAL| REGIMM| J | JAL | BEQ | BNE | BLEZ | BGTZ 1150 * 1 001 | ADDI | ADDIU | SLTI | SLTIU | ANDI | ORI | XORI | LUI 1151 * 2 010 | COP0 | COP1 | * | * | BEQL | BNEL | BLEZL | BGTZL 1152 * 3 011 | DADDI | DADDIU| LDL | LDR | MMI% | * | LQ | SQ 1153 * 4 100 | LB | LH | LWL | LW | LBU | LHU | LWR | LWU 1154 * 5 101 | SB | SH | SWL | SW | SDL | SDR | SWR | CACHE 1155 * 6 110 | # | LWC1 | # | PREF | # | LDC1 | # | LD 1156 * 7 111 | # | SWC1 | # | * | # | SDC1 | # | SD 1157 */ 1158 1159 enum { 1160 MMI_OPC_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */ 1161 MMI_OPC_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */ 1162 }; 1163 1164 /* 1165 * MMI instructions with opcode field = MMI: 1166 * 1167 * 31 26 5 0 1168 * +--------+-------------------------------+--------+ 1169 * | MMI | |function| 1170 * +--------+-------------------------------+--------+ 1171 * 1172 * function bits 2..0 1173 * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 1174 * 5..3 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 1175 * -------+-------+-------+-------+-------+-------+-------+-------+------- 1176 * 0 000 | MADD | MADDU | * | * | PLZCW | * | * | * 1177 * 1 001 | MMI0% | MMI2% | * | * | * | * | * | * 1178 * 2 010 | MFHI1 | MTHI1 | MFLO1 | MTLO1 | * | * | * | * 1179 * 3 011 | MULT1 | MULTU1| DIV1 | DIVU1 | * | * | * | * 1180 * 4 100 | MADD1 | MADDU1| * | * | * | * | * | * 1181 * 5 101 | MMI1% | MMI3% | * | * | * | * | * | * 1182 * 6 110 | PMFHL | PMTHL | * | * | PSLLH | * | PSRLH | PSRAH 1183 * 7 111 | * | * | * | * | PSLLW | * | PSRLW | PSRAW 1184 */ 1185 1186 #define MASK_MMI(op) (MASK_OP_MAJOR(op) | ((op) & 0x3F)) 1187 enum { 1188 MMI_OPC_MADD = 0x00 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADD */ 1189 MMI_OPC_MADDU = 0x01 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADDU */ 1190 MMI_OPC_MULT1 = 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MULT */ 1191 MMI_OPC_MULTU1 = 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_MULTU */ 1192 MMI_OPC_DIV1 = 0x1A | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIV */ 1193 MMI_OPC_DIVU1 = 0x1B | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIVU */ 1194 MMI_OPC_MADD1 = 0x20 | MMI_OPC_CLASS_MMI, 1195 MMI_OPC_MADDU1 = 0x21 | MMI_OPC_CLASS_MMI, 1196 }; 1197 1198 /* global register indices */ 1199 TCGv cpu_gpr[32], cpu_PC; 1200 /* 1201 * For CPUs using 128-bit GPR registers, we put the lower halves in cpu_gpr[]) 1202 * and the upper halves in cpu_gpr_hi[]. 1203 */ 1204 TCGv_i64 cpu_gpr_hi[32]; 1205 TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; 1206 static TCGv cpu_dspctrl, btarget; 1207 TCGv bcond; 1208 static TCGv cpu_lladdr, cpu_llval; 1209 static TCGv_i32 hflags; 1210 TCGv_i32 fpu_fcr0, fpu_fcr31; 1211 TCGv_i64 fpu_f64[32]; 1212 1213 #include "exec/gen-icount.h" 1214 1215 static const char regnames_HI[][4] = { 1216 "HI0", "HI1", "HI2", "HI3", 1217 }; 1218 1219 static const char regnames_LO[][4] = { 1220 "LO0", "LO1", "LO2", "LO3", 1221 }; 1222 1223 /* General purpose registers moves. */ 1224 void gen_load_gpr(TCGv t, int reg) 1225 { 1226 if (reg == 0) { 1227 tcg_gen_movi_tl(t, 0); 1228 } else { 1229 tcg_gen_mov_tl(t, cpu_gpr[reg]); 1230 } 1231 } 1232 1233 void gen_store_gpr(TCGv t, int reg) 1234 { 1235 if (reg != 0) { 1236 tcg_gen_mov_tl(cpu_gpr[reg], t); 1237 } 1238 } 1239 1240 #if defined(TARGET_MIPS64) 1241 void gen_load_gpr_hi(TCGv_i64 t, int reg) 1242 { 1243 if (reg == 0) { 1244 tcg_gen_movi_i64(t, 0); 1245 } else { 1246 tcg_gen_mov_i64(t, cpu_gpr_hi[reg]); 1247 } 1248 } 1249 1250 void gen_store_gpr_hi(TCGv_i64 t, int reg) 1251 { 1252 if (reg != 0) { 1253 tcg_gen_mov_i64(cpu_gpr_hi[reg], t); 1254 } 1255 } 1256 #endif /* TARGET_MIPS64 */ 1257 1258 /* Moves to/from shadow registers. */ 1259 static inline void gen_load_srsgpr(int from, int to) 1260 { 1261 TCGv t0 = tcg_temp_new(); 1262 1263 if (from == 0) { 1264 tcg_gen_movi_tl(t0, 0); 1265 } else { 1266 TCGv_i32 t2 = tcg_temp_new_i32(); 1267 TCGv_ptr addr = tcg_temp_new_ptr(); 1268 1269 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl)); 1270 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); 1271 tcg_gen_andi_i32(t2, t2, 0xf); 1272 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32); 1273 tcg_gen_ext_i32_ptr(addr, t2); 1274 tcg_gen_add_ptr(addr, cpu_env, addr); 1275 1276 tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from); 1277 } 1278 gen_store_gpr(t0, to); 1279 } 1280 1281 static inline void gen_store_srsgpr(int from, int to) 1282 { 1283 if (to != 0) { 1284 TCGv t0 = tcg_temp_new(); 1285 TCGv_i32 t2 = tcg_temp_new_i32(); 1286 TCGv_ptr addr = tcg_temp_new_ptr(); 1287 1288 gen_load_gpr(t0, from); 1289 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl)); 1290 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); 1291 tcg_gen_andi_i32(t2, t2, 0xf); 1292 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32); 1293 tcg_gen_ext_i32_ptr(addr, t2); 1294 tcg_gen_add_ptr(addr, cpu_env, addr); 1295 1296 tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to); 1297 } 1298 } 1299 1300 /* Tests */ 1301 static inline void gen_save_pc(target_ulong pc) 1302 { 1303 tcg_gen_movi_tl(cpu_PC, pc); 1304 } 1305 1306 static inline void save_cpu_state(DisasContext *ctx, int do_save_pc) 1307 { 1308 LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags); 1309 if (do_save_pc && ctx->base.pc_next != ctx->saved_pc) { 1310 gen_save_pc(ctx->base.pc_next); 1311 ctx->saved_pc = ctx->base.pc_next; 1312 } 1313 if (ctx->hflags != ctx->saved_hflags) { 1314 tcg_gen_movi_i32(hflags, ctx->hflags); 1315 ctx->saved_hflags = ctx->hflags; 1316 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) { 1317 case MIPS_HFLAG_BR: 1318 break; 1319 case MIPS_HFLAG_BC: 1320 case MIPS_HFLAG_BL: 1321 case MIPS_HFLAG_B: 1322 tcg_gen_movi_tl(btarget, ctx->btarget); 1323 break; 1324 } 1325 } 1326 } 1327 1328 static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx) 1329 { 1330 ctx->saved_hflags = ctx->hflags; 1331 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) { 1332 case MIPS_HFLAG_BR: 1333 break; 1334 case MIPS_HFLAG_BC: 1335 case MIPS_HFLAG_BL: 1336 case MIPS_HFLAG_B: 1337 ctx->btarget = env->btarget; 1338 break; 1339 } 1340 } 1341 1342 void generate_exception_err(DisasContext *ctx, int excp, int err) 1343 { 1344 save_cpu_state(ctx, 1); 1345 gen_helper_raise_exception_err(cpu_env, tcg_constant_i32(excp), 1346 tcg_constant_i32(err)); 1347 ctx->base.is_jmp = DISAS_NORETURN; 1348 } 1349 1350 void generate_exception(DisasContext *ctx, int excp) 1351 { 1352 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 1353 } 1354 1355 void generate_exception_end(DisasContext *ctx, int excp) 1356 { 1357 generate_exception_err(ctx, excp, 0); 1358 } 1359 1360 void generate_exception_break(DisasContext *ctx, int code) 1361 { 1362 #ifdef CONFIG_USER_ONLY 1363 /* Pass the break code along to cpu_loop. */ 1364 tcg_gen_st_i32(tcg_constant_i32(code), cpu_env, 1365 offsetof(CPUMIPSState, error_code)); 1366 #endif 1367 generate_exception_end(ctx, EXCP_BREAK); 1368 } 1369 1370 void gen_reserved_instruction(DisasContext *ctx) 1371 { 1372 generate_exception_end(ctx, EXCP_RI); 1373 } 1374 1375 /* Floating point register moves. */ 1376 void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) 1377 { 1378 if (ctx->hflags & MIPS_HFLAG_FRE) { 1379 generate_exception(ctx, EXCP_RI); 1380 } 1381 tcg_gen_extrl_i64_i32(t, fpu_f64[reg]); 1382 } 1383 1384 void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) 1385 { 1386 TCGv_i64 t64; 1387 if (ctx->hflags & MIPS_HFLAG_FRE) { 1388 generate_exception(ctx, EXCP_RI); 1389 } 1390 t64 = tcg_temp_new_i64(); 1391 tcg_gen_extu_i32_i64(t64, t); 1392 tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 0, 32); 1393 } 1394 1395 static void gen_load_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg) 1396 { 1397 if (ctx->hflags & MIPS_HFLAG_F64) { 1398 tcg_gen_extrh_i64_i32(t, fpu_f64[reg]); 1399 } else { 1400 gen_load_fpr32(ctx, t, reg | 1); 1401 } 1402 } 1403 1404 static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg) 1405 { 1406 if (ctx->hflags & MIPS_HFLAG_F64) { 1407 TCGv_i64 t64 = tcg_temp_new_i64(); 1408 tcg_gen_extu_i32_i64(t64, t); 1409 tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 32, 32); 1410 } else { 1411 gen_store_fpr32(ctx, t, reg | 1); 1412 } 1413 } 1414 1415 void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) 1416 { 1417 if (ctx->hflags & MIPS_HFLAG_F64) { 1418 tcg_gen_mov_i64(t, fpu_f64[reg]); 1419 } else { 1420 tcg_gen_concat32_i64(t, fpu_f64[reg & ~1], fpu_f64[reg | 1]); 1421 } 1422 } 1423 1424 void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) 1425 { 1426 if (ctx->hflags & MIPS_HFLAG_F64) { 1427 tcg_gen_mov_i64(fpu_f64[reg], t); 1428 } else { 1429 TCGv_i64 t0; 1430 tcg_gen_deposit_i64(fpu_f64[reg & ~1], fpu_f64[reg & ~1], t, 0, 32); 1431 t0 = tcg_temp_new_i64(); 1432 tcg_gen_shri_i64(t0, t, 32); 1433 tcg_gen_deposit_i64(fpu_f64[reg | 1], fpu_f64[reg | 1], t0, 0, 32); 1434 } 1435 } 1436 1437 int get_fp_bit(int cc) 1438 { 1439 if (cc) { 1440 return 24 + cc; 1441 } else { 1442 return 23; 1443 } 1444 } 1445 1446 /* Addresses computation */ 1447 void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1) 1448 { 1449 tcg_gen_add_tl(ret, arg0, arg1); 1450 1451 #if defined(TARGET_MIPS64) 1452 if (ctx->hflags & MIPS_HFLAG_AWRAP) { 1453 tcg_gen_ext32s_i64(ret, ret); 1454 } 1455 #endif 1456 } 1457 1458 static inline void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base, 1459 target_long ofs) 1460 { 1461 tcg_gen_addi_tl(ret, base, ofs); 1462 1463 #if defined(TARGET_MIPS64) 1464 if (ctx->hflags & MIPS_HFLAG_AWRAP) { 1465 tcg_gen_ext32s_i64(ret, ret); 1466 } 1467 #endif 1468 } 1469 1470 /* Addresses computation (translation time) */ 1471 static target_long addr_add(DisasContext *ctx, target_long base, 1472 target_long offset) 1473 { 1474 target_long sum = base + offset; 1475 1476 #if defined(TARGET_MIPS64) 1477 if (ctx->hflags & MIPS_HFLAG_AWRAP) { 1478 sum = (int32_t)sum; 1479 } 1480 #endif 1481 return sum; 1482 } 1483 1484 /* Sign-extract the low 32-bits to a target_long. */ 1485 void gen_move_low32(TCGv ret, TCGv_i64 arg) 1486 { 1487 #if defined(TARGET_MIPS64) 1488 tcg_gen_ext32s_i64(ret, arg); 1489 #else 1490 tcg_gen_extrl_i64_i32(ret, arg); 1491 #endif 1492 } 1493 1494 /* Sign-extract the high 32-bits to a target_long. */ 1495 void gen_move_high32(TCGv ret, TCGv_i64 arg) 1496 { 1497 #if defined(TARGET_MIPS64) 1498 tcg_gen_sari_i64(ret, arg, 32); 1499 #else 1500 tcg_gen_extrh_i64_i32(ret, arg); 1501 #endif 1502 } 1503 1504 bool check_cp0_enabled(DisasContext *ctx) 1505 { 1506 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { 1507 generate_exception_end(ctx, EXCP_CpU); 1508 return false; 1509 } 1510 return true; 1511 } 1512 1513 void check_cp1_enabled(DisasContext *ctx) 1514 { 1515 if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) { 1516 generate_exception_err(ctx, EXCP_CpU, 1); 1517 } 1518 } 1519 1520 /* 1521 * Verify that the processor is running with COP1X instructions enabled. 1522 * This is associated with the nabla symbol in the MIPS32 and MIPS64 1523 * opcode tables. 1524 */ 1525 void check_cop1x(DisasContext *ctx) 1526 { 1527 if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) { 1528 gen_reserved_instruction(ctx); 1529 } 1530 } 1531 1532 /* 1533 * Verify that the processor is running with 64-bit floating-point 1534 * operations enabled. 1535 */ 1536 void check_cp1_64bitmode(DisasContext *ctx) 1537 { 1538 if (unlikely(~ctx->hflags & MIPS_HFLAG_F64)) { 1539 gen_reserved_instruction(ctx); 1540 } 1541 } 1542 1543 /* 1544 * Verify if floating point register is valid; an operation is not defined 1545 * if bit 0 of any register specification is set and the FR bit in the 1546 * Status register equals zero, since the register numbers specify an 1547 * even-odd pair of adjacent coprocessor general registers. When the FR bit 1548 * in the Status register equals one, both even and odd register numbers 1549 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers. 1550 * 1551 * Multiple 64 bit wide registers can be checked by calling 1552 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN); 1553 */ 1554 void check_cp1_registers(DisasContext *ctx, int regs) 1555 { 1556 if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) { 1557 gen_reserved_instruction(ctx); 1558 } 1559 } 1560 1561 /* 1562 * Verify that the processor is running with DSP instructions enabled. 1563 * This is enabled by CP0 Status register MX(24) bit. 1564 */ 1565 static inline void check_dsp(DisasContext *ctx) 1566 { 1567 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) { 1568 if (ctx->insn_flags & ASE_DSP) { 1569 generate_exception_end(ctx, EXCP_DSPDIS); 1570 } else { 1571 gen_reserved_instruction(ctx); 1572 } 1573 } 1574 } 1575 1576 static inline void check_dsp_r2(DisasContext *ctx) 1577 { 1578 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R2))) { 1579 if (ctx->insn_flags & ASE_DSP) { 1580 generate_exception_end(ctx, EXCP_DSPDIS); 1581 } else { 1582 gen_reserved_instruction(ctx); 1583 } 1584 } 1585 } 1586 1587 static inline void check_dsp_r3(DisasContext *ctx) 1588 { 1589 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R3))) { 1590 if (ctx->insn_flags & ASE_DSP) { 1591 generate_exception_end(ctx, EXCP_DSPDIS); 1592 } else { 1593 gen_reserved_instruction(ctx); 1594 } 1595 } 1596 } 1597 1598 /* 1599 * This code generates a "reserved instruction" exception if the 1600 * CPU does not support the instruction set corresponding to flags. 1601 */ 1602 void check_insn(DisasContext *ctx, uint64_t flags) 1603 { 1604 if (unlikely(!(ctx->insn_flags & flags))) { 1605 gen_reserved_instruction(ctx); 1606 } 1607 } 1608 1609 /* 1610 * This code generates a "reserved instruction" exception if the 1611 * CPU has corresponding flag set which indicates that the instruction 1612 * has been removed. 1613 */ 1614 static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags) 1615 { 1616 if (unlikely(ctx->insn_flags & flags)) { 1617 gen_reserved_instruction(ctx); 1618 } 1619 } 1620 1621 /* 1622 * The Linux kernel traps certain reserved instruction exceptions to 1623 * emulate the corresponding instructions. QEMU is the kernel in user 1624 * mode, so those traps are emulated by accepting the instructions. 1625 * 1626 * A reserved instruction exception is generated for flagged CPUs if 1627 * QEMU runs in system mode. 1628 */ 1629 static inline void check_insn_opc_user_only(DisasContext *ctx, uint64_t flags) 1630 { 1631 #ifndef CONFIG_USER_ONLY 1632 check_insn_opc_removed(ctx, flags); 1633 #endif 1634 } 1635 1636 /* 1637 * This code generates a "reserved instruction" exception if the 1638 * CPU does not support 64-bit paired-single (PS) floating point data type. 1639 */ 1640 static inline void check_ps(DisasContext *ctx) 1641 { 1642 if (unlikely(!ctx->ps)) { 1643 generate_exception(ctx, EXCP_RI); 1644 } 1645 check_cp1_64bitmode(ctx); 1646 } 1647 1648 /* 1649 * This code generates a "reserved instruction" exception if cpu is not 1650 * 64-bit or 64-bit instructions are not enabled. 1651 */ 1652 void check_mips_64(DisasContext *ctx) 1653 { 1654 if (unlikely((TARGET_LONG_BITS != 64) || !(ctx->hflags & MIPS_HFLAG_64))) { 1655 gen_reserved_instruction(ctx); 1656 } 1657 } 1658 1659 #ifndef CONFIG_USER_ONLY 1660 static inline void check_mvh(DisasContext *ctx) 1661 { 1662 if (unlikely(!ctx->mvh)) { 1663 generate_exception(ctx, EXCP_RI); 1664 } 1665 } 1666 #endif 1667 1668 /* 1669 * This code generates a "reserved instruction" exception if the 1670 * Config5 XNP bit is set. 1671 */ 1672 static inline void check_xnp(DisasContext *ctx) 1673 { 1674 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) { 1675 gen_reserved_instruction(ctx); 1676 } 1677 } 1678 1679 #ifndef CONFIG_USER_ONLY 1680 /* 1681 * This code generates a "reserved instruction" exception if the 1682 * Config3 PW bit is NOT set. 1683 */ 1684 static inline void check_pw(DisasContext *ctx) 1685 { 1686 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_PW)))) { 1687 gen_reserved_instruction(ctx); 1688 } 1689 } 1690 #endif 1691 1692 /* 1693 * This code generates a "reserved instruction" exception if the 1694 * Config3 MT bit is NOT set. 1695 */ 1696 static inline void check_mt(DisasContext *ctx) 1697 { 1698 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { 1699 gen_reserved_instruction(ctx); 1700 } 1701 } 1702 1703 #ifndef CONFIG_USER_ONLY 1704 /* 1705 * This code generates a "coprocessor unusable" exception if CP0 is not 1706 * available, and, if that is not the case, generates a "reserved instruction" 1707 * exception if the Config5 MT bit is NOT set. This is needed for availability 1708 * control of some of MT ASE instructions. 1709 */ 1710 static inline void check_cp0_mt(DisasContext *ctx) 1711 { 1712 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { 1713 generate_exception_end(ctx, EXCP_CpU); 1714 } else { 1715 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { 1716 gen_reserved_instruction(ctx); 1717 } 1718 } 1719 } 1720 #endif 1721 1722 /* 1723 * This code generates a "reserved instruction" exception if the 1724 * Config5 NMS bit is set. 1725 */ 1726 static inline void check_nms(DisasContext *ctx) 1727 { 1728 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) { 1729 gen_reserved_instruction(ctx); 1730 } 1731 } 1732 1733 /* 1734 * This code generates a "reserved instruction" exception if the 1735 * Config5 NMS bit is set, and Config1 DL, Config1 IL, Config2 SL, 1736 * Config2 TL, and Config5 L2C are unset. 1737 */ 1738 static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx) 1739 { 1740 if (unlikely((ctx->CP0_Config5 & (1 << CP0C5_NMS)) && 1741 !(ctx->CP0_Config1 & (1 << CP0C1_DL)) && 1742 !(ctx->CP0_Config1 & (1 << CP0C1_IL)) && 1743 !(ctx->CP0_Config2 & (1 << CP0C2_SL)) && 1744 !(ctx->CP0_Config2 & (1 << CP0C2_TL)) && 1745 !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) { 1746 gen_reserved_instruction(ctx); 1747 } 1748 } 1749 1750 /* 1751 * This code generates a "reserved instruction" exception if the 1752 * Config5 EVA bit is NOT set. 1753 */ 1754 static inline void check_eva(DisasContext *ctx) 1755 { 1756 if (unlikely(!(ctx->CP0_Config5 & (1 << CP0C5_EVA)))) { 1757 gen_reserved_instruction(ctx); 1758 } 1759 } 1760 1761 1762 /* 1763 * Define small wrappers for gen_load_fpr* so that we have a uniform 1764 * calling interface for 32 and 64-bit FPRs. No sense in changing 1765 * all callers for gen_load_fpr32 when we need the CTX parameter for 1766 * this one use. 1767 */ 1768 #define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(ctx, x, y) 1769 #define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y) 1770 #define FOP_CONDS(type, abs, fmt, ifmt, bits) \ 1771 static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \ 1772 int ft, int fs, int cc) \ 1773 { \ 1774 TCGv_i##bits fp0 = tcg_temp_new_i##bits(); \ 1775 TCGv_i##bits fp1 = tcg_temp_new_i##bits(); \ 1776 switch (ifmt) { \ 1777 case FMT_PS: \ 1778 check_ps(ctx); \ 1779 break; \ 1780 case FMT_D: \ 1781 if (abs) { \ 1782 check_cop1x(ctx); \ 1783 } \ 1784 check_cp1_registers(ctx, fs | ft); \ 1785 break; \ 1786 case FMT_S: \ 1787 if (abs) { \ 1788 check_cop1x(ctx); \ 1789 } \ 1790 break; \ 1791 } \ 1792 gen_ldcmp_fpr##bits(ctx, fp0, fs); \ 1793 gen_ldcmp_fpr##bits(ctx, fp1, ft); \ 1794 switch (n) { \ 1795 case 0: \ 1796 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); \ 1797 break; \ 1798 case 1: \ 1799 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); \ 1800 break; \ 1801 case 2: \ 1802 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); \ 1803 break; \ 1804 case 3: \ 1805 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); \ 1806 break; \ 1807 case 4: \ 1808 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); \ 1809 break; \ 1810 case 5: \ 1811 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); \ 1812 break; \ 1813 case 6: \ 1814 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); \ 1815 break; \ 1816 case 7: \ 1817 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); \ 1818 break; \ 1819 case 8: \ 1820 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); \ 1821 break; \ 1822 case 9: \ 1823 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); \ 1824 break; \ 1825 case 10: \ 1826 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); \ 1827 break; \ 1828 case 11: \ 1829 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); \ 1830 break; \ 1831 case 12: \ 1832 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); \ 1833 break; \ 1834 case 13: \ 1835 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); \ 1836 break; \ 1837 case 14: \ 1838 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); \ 1839 break; \ 1840 case 15: \ 1841 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); \ 1842 break; \ 1843 default: \ 1844 abort(); \ 1845 } \ 1846 } 1847 1848 FOP_CONDS(, 0, d, FMT_D, 64) 1849 FOP_CONDS(abs, 1, d, FMT_D, 64) 1850 FOP_CONDS(, 0, s, FMT_S, 32) 1851 FOP_CONDS(abs, 1, s, FMT_S, 32) 1852 FOP_CONDS(, 0, ps, FMT_PS, 64) 1853 FOP_CONDS(abs, 1, ps, FMT_PS, 64) 1854 #undef FOP_CONDS 1855 1856 #define FOP_CONDNS(fmt, ifmt, bits, STORE) \ 1857 static inline void gen_r6_cmp_ ## fmt(DisasContext *ctx, int n, \ 1858 int ft, int fs, int fd) \ 1859 { \ 1860 TCGv_i ## bits fp0 = tcg_temp_new_i ## bits(); \ 1861 TCGv_i ## bits fp1 = tcg_temp_new_i ## bits(); \ 1862 if (ifmt == FMT_D) { \ 1863 check_cp1_registers(ctx, fs | ft | fd); \ 1864 } \ 1865 gen_ldcmp_fpr ## bits(ctx, fp0, fs); \ 1866 gen_ldcmp_fpr ## bits(ctx, fp1, ft); \ 1867 switch (n) { \ 1868 case 0: \ 1869 gen_helper_r6_cmp_ ## fmt ## _af(fp0, cpu_env, fp0, fp1); \ 1870 break; \ 1871 case 1: \ 1872 gen_helper_r6_cmp_ ## fmt ## _un(fp0, cpu_env, fp0, fp1); \ 1873 break; \ 1874 case 2: \ 1875 gen_helper_r6_cmp_ ## fmt ## _eq(fp0, cpu_env, fp0, fp1); \ 1876 break; \ 1877 case 3: \ 1878 gen_helper_r6_cmp_ ## fmt ## _ueq(fp0, cpu_env, fp0, fp1); \ 1879 break; \ 1880 case 4: \ 1881 gen_helper_r6_cmp_ ## fmt ## _lt(fp0, cpu_env, fp0, fp1); \ 1882 break; \ 1883 case 5: \ 1884 gen_helper_r6_cmp_ ## fmt ## _ult(fp0, cpu_env, fp0, fp1); \ 1885 break; \ 1886 case 6: \ 1887 gen_helper_r6_cmp_ ## fmt ## _le(fp0, cpu_env, fp0, fp1); \ 1888 break; \ 1889 case 7: \ 1890 gen_helper_r6_cmp_ ## fmt ## _ule(fp0, cpu_env, fp0, fp1); \ 1891 break; \ 1892 case 8: \ 1893 gen_helper_r6_cmp_ ## fmt ## _saf(fp0, cpu_env, fp0, fp1); \ 1894 break; \ 1895 case 9: \ 1896 gen_helper_r6_cmp_ ## fmt ## _sun(fp0, cpu_env, fp0, fp1); \ 1897 break; \ 1898 case 10: \ 1899 gen_helper_r6_cmp_ ## fmt ## _seq(fp0, cpu_env, fp0, fp1); \ 1900 break; \ 1901 case 11: \ 1902 gen_helper_r6_cmp_ ## fmt ## _sueq(fp0, cpu_env, fp0, fp1); \ 1903 break; \ 1904 case 12: \ 1905 gen_helper_r6_cmp_ ## fmt ## _slt(fp0, cpu_env, fp0, fp1); \ 1906 break; \ 1907 case 13: \ 1908 gen_helper_r6_cmp_ ## fmt ## _sult(fp0, cpu_env, fp0, fp1); \ 1909 break; \ 1910 case 14: \ 1911 gen_helper_r6_cmp_ ## fmt ## _sle(fp0, cpu_env, fp0, fp1); \ 1912 break; \ 1913 case 15: \ 1914 gen_helper_r6_cmp_ ## fmt ## _sule(fp0, cpu_env, fp0, fp1); \ 1915 break; \ 1916 case 17: \ 1917 gen_helper_r6_cmp_ ## fmt ## _or(fp0, cpu_env, fp0, fp1); \ 1918 break; \ 1919 case 18: \ 1920 gen_helper_r6_cmp_ ## fmt ## _une(fp0, cpu_env, fp0, fp1); \ 1921 break; \ 1922 case 19: \ 1923 gen_helper_r6_cmp_ ## fmt ## _ne(fp0, cpu_env, fp0, fp1); \ 1924 break; \ 1925 case 25: \ 1926 gen_helper_r6_cmp_ ## fmt ## _sor(fp0, cpu_env, fp0, fp1); \ 1927 break; \ 1928 case 26: \ 1929 gen_helper_r6_cmp_ ## fmt ## _sune(fp0, cpu_env, fp0, fp1); \ 1930 break; \ 1931 case 27: \ 1932 gen_helper_r6_cmp_ ## fmt ## _sne(fp0, cpu_env, fp0, fp1); \ 1933 break; \ 1934 default: \ 1935 abort(); \ 1936 } \ 1937 STORE; \ 1938 } 1939 1940 FOP_CONDNS(d, FMT_D, 64, gen_store_fpr64(ctx, fp0, fd)) 1941 FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, fd)) 1942 #undef FOP_CONDNS 1943 #undef gen_ldcmp_fpr32 1944 #undef gen_ldcmp_fpr64 1945 1946 /* load/store instructions. */ 1947 #ifdef CONFIG_USER_ONLY 1948 #define OP_LD_ATOMIC(insn, fname) \ 1949 static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \ 1950 DisasContext *ctx) \ 1951 { \ 1952 TCGv t0 = tcg_temp_new(); \ 1953 tcg_gen_mov_tl(t0, arg1); \ 1954 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \ 1955 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \ 1956 tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); \ 1957 } 1958 #else 1959 #define OP_LD_ATOMIC(insn, fname) \ 1960 static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \ 1961 DisasContext *ctx) \ 1962 { \ 1963 gen_helper_##insn(ret, cpu_env, arg1, tcg_constant_i32(mem_idx)); \ 1964 } 1965 #endif 1966 OP_LD_ATOMIC(ll, ld32s); 1967 #if defined(TARGET_MIPS64) 1968 OP_LD_ATOMIC(lld, ld64); 1969 #endif 1970 #undef OP_LD_ATOMIC 1971 1972 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset) 1973 { 1974 if (base == 0) { 1975 tcg_gen_movi_tl(addr, offset); 1976 } else if (offset == 0) { 1977 gen_load_gpr(addr, base); 1978 } else { 1979 tcg_gen_movi_tl(addr, offset); 1980 gen_op_addr_add(ctx, addr, cpu_gpr[base], addr); 1981 } 1982 } 1983 1984 static target_ulong pc_relative_pc(DisasContext *ctx) 1985 { 1986 target_ulong pc = ctx->base.pc_next; 1987 1988 if (ctx->hflags & MIPS_HFLAG_BMASK) { 1989 int branch_bytes = ctx->hflags & MIPS_HFLAG_BDS16 ? 2 : 4; 1990 1991 pc -= branch_bytes; 1992 } 1993 1994 pc &= ~(target_ulong)3; 1995 return pc; 1996 } 1997 1998 /* Load */ 1999 static void gen_ld(DisasContext *ctx, uint32_t opc, 2000 int rt, int base, int offset) 2001 { 2002 TCGv t0, t1, t2; 2003 int mem_idx = ctx->mem_idx; 2004 2005 if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F | 2006 INSN_LOONGSON3A)) { 2007 /* 2008 * Loongson CPU uses a load to zero register for prefetch. 2009 * We emulate it as a NOP. On other CPU we must perform the 2010 * actual memory access. 2011 */ 2012 return; 2013 } 2014 2015 t0 = tcg_temp_new(); 2016 gen_base_offset_addr(ctx, t0, base, offset); 2017 2018 switch (opc) { 2019 #if defined(TARGET_MIPS64) 2020 case OPC_LWU: 2021 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL | 2022 ctx->default_tcg_memop_mask); 2023 gen_store_gpr(t0, rt); 2024 break; 2025 case OPC_LD: 2026 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ | 2027 ctx->default_tcg_memop_mask); 2028 gen_store_gpr(t0, rt); 2029 break; 2030 case OPC_LLD: 2031 case R6_OPC_LLD: 2032 op_ld_lld(t0, t0, mem_idx, ctx); 2033 gen_store_gpr(t0, rt); 2034 break; 2035 case OPC_LDL: 2036 t1 = tcg_temp_new(); 2037 /* 2038 * Do a byte access to possibly trigger a page 2039 * fault with the unaligned address. 2040 */ 2041 tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB); 2042 tcg_gen_andi_tl(t1, t0, 7); 2043 if (!cpu_is_bigendian(ctx)) { 2044 tcg_gen_xori_tl(t1, t1, 7); 2045 } 2046 tcg_gen_shli_tl(t1, t1, 3); 2047 tcg_gen_andi_tl(t0, t0, ~7); 2048 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ); 2049 tcg_gen_shl_tl(t0, t0, t1); 2050 t2 = tcg_const_tl(-1); 2051 tcg_gen_shl_tl(t2, t2, t1); 2052 gen_load_gpr(t1, rt); 2053 tcg_gen_andc_tl(t1, t1, t2); 2054 tcg_gen_or_tl(t0, t0, t1); 2055 gen_store_gpr(t0, rt); 2056 break; 2057 case OPC_LDR: 2058 t1 = tcg_temp_new(); 2059 /* 2060 * Do a byte access to possibly trigger a page 2061 * fault with the unaligned address. 2062 */ 2063 tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB); 2064 tcg_gen_andi_tl(t1, t0, 7); 2065 if (cpu_is_bigendian(ctx)) { 2066 tcg_gen_xori_tl(t1, t1, 7); 2067 } 2068 tcg_gen_shli_tl(t1, t1, 3); 2069 tcg_gen_andi_tl(t0, t0, ~7); 2070 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ); 2071 tcg_gen_shr_tl(t0, t0, t1); 2072 tcg_gen_xori_tl(t1, t1, 63); 2073 t2 = tcg_const_tl(0xfffffffffffffffeull); 2074 tcg_gen_shl_tl(t2, t2, t1); 2075 gen_load_gpr(t1, rt); 2076 tcg_gen_and_tl(t1, t1, t2); 2077 tcg_gen_or_tl(t0, t0, t1); 2078 gen_store_gpr(t0, rt); 2079 break; 2080 case OPC_LDPC: 2081 t1 = tcg_const_tl(pc_relative_pc(ctx)); 2082 gen_op_addr_add(ctx, t0, t0, t1); 2083 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ); 2084 gen_store_gpr(t0, rt); 2085 break; 2086 #endif 2087 case OPC_LWPC: 2088 t1 = tcg_const_tl(pc_relative_pc(ctx)); 2089 gen_op_addr_add(ctx, t0, t0, t1); 2090 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL); 2091 gen_store_gpr(t0, rt); 2092 break; 2093 case OPC_LWE: 2094 mem_idx = MIPS_HFLAG_UM; 2095 /* fall through */ 2096 case OPC_LW: 2097 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL | 2098 ctx->default_tcg_memop_mask); 2099 gen_store_gpr(t0, rt); 2100 break; 2101 case OPC_LHE: 2102 mem_idx = MIPS_HFLAG_UM; 2103 /* fall through */ 2104 case OPC_LH: 2105 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESW | 2106 ctx->default_tcg_memop_mask); 2107 gen_store_gpr(t0, rt); 2108 break; 2109 case OPC_LHUE: 2110 mem_idx = MIPS_HFLAG_UM; 2111 /* fall through */ 2112 case OPC_LHU: 2113 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUW | 2114 ctx->default_tcg_memop_mask); 2115 gen_store_gpr(t0, rt); 2116 break; 2117 case OPC_LBE: 2118 mem_idx = MIPS_HFLAG_UM; 2119 /* fall through */ 2120 case OPC_LB: 2121 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_SB); 2122 gen_store_gpr(t0, rt); 2123 break; 2124 case OPC_LBUE: 2125 mem_idx = MIPS_HFLAG_UM; 2126 /* fall through */ 2127 case OPC_LBU: 2128 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_UB); 2129 gen_store_gpr(t0, rt); 2130 break; 2131 case OPC_LWLE: 2132 mem_idx = MIPS_HFLAG_UM; 2133 /* fall through */ 2134 case OPC_LWL: 2135 t1 = tcg_temp_new(); 2136 /* 2137 * Do a byte access to possibly trigger a page 2138 * fault with the unaligned address. 2139 */ 2140 tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB); 2141 tcg_gen_andi_tl(t1, t0, 3); 2142 if (!cpu_is_bigendian(ctx)) { 2143 tcg_gen_xori_tl(t1, t1, 3); 2144 } 2145 tcg_gen_shli_tl(t1, t1, 3); 2146 tcg_gen_andi_tl(t0, t0, ~3); 2147 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL); 2148 tcg_gen_shl_tl(t0, t0, t1); 2149 t2 = tcg_const_tl(-1); 2150 tcg_gen_shl_tl(t2, t2, t1); 2151 gen_load_gpr(t1, rt); 2152 tcg_gen_andc_tl(t1, t1, t2); 2153 tcg_gen_or_tl(t0, t0, t1); 2154 tcg_gen_ext32s_tl(t0, t0); 2155 gen_store_gpr(t0, rt); 2156 break; 2157 case OPC_LWRE: 2158 mem_idx = MIPS_HFLAG_UM; 2159 /* fall through */ 2160 case OPC_LWR: 2161 t1 = tcg_temp_new(); 2162 /* 2163 * Do a byte access to possibly trigger a page 2164 * fault with the unaligned address. 2165 */ 2166 tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB); 2167 tcg_gen_andi_tl(t1, t0, 3); 2168 if (cpu_is_bigendian(ctx)) { 2169 tcg_gen_xori_tl(t1, t1, 3); 2170 } 2171 tcg_gen_shli_tl(t1, t1, 3); 2172 tcg_gen_andi_tl(t0, t0, ~3); 2173 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL); 2174 tcg_gen_shr_tl(t0, t0, t1); 2175 tcg_gen_xori_tl(t1, t1, 31); 2176 t2 = tcg_const_tl(0xfffffffeull); 2177 tcg_gen_shl_tl(t2, t2, t1); 2178 gen_load_gpr(t1, rt); 2179 tcg_gen_and_tl(t1, t1, t2); 2180 tcg_gen_or_tl(t0, t0, t1); 2181 tcg_gen_ext32s_tl(t0, t0); 2182 gen_store_gpr(t0, rt); 2183 break; 2184 case OPC_LLE: 2185 mem_idx = MIPS_HFLAG_UM; 2186 /* fall through */ 2187 case OPC_LL: 2188 case R6_OPC_LL: 2189 op_ld_ll(t0, t0, mem_idx, ctx); 2190 gen_store_gpr(t0, rt); 2191 break; 2192 } 2193 } 2194 2195 /* Store */ 2196 static void gen_st(DisasContext *ctx, uint32_t opc, int rt, 2197 int base, int offset) 2198 { 2199 TCGv t0 = tcg_temp_new(); 2200 TCGv t1 = tcg_temp_new(); 2201 int mem_idx = ctx->mem_idx; 2202 2203 gen_base_offset_addr(ctx, t0, base, offset); 2204 gen_load_gpr(t1, rt); 2205 switch (opc) { 2206 #if defined(TARGET_MIPS64) 2207 case OPC_SD: 2208 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUQ | 2209 ctx->default_tcg_memop_mask); 2210 break; 2211 case OPC_SDL: 2212 gen_helper_0e2i(sdl, t1, t0, mem_idx); 2213 break; 2214 case OPC_SDR: 2215 gen_helper_0e2i(sdr, t1, t0, mem_idx); 2216 break; 2217 #endif 2218 case OPC_SWE: 2219 mem_idx = MIPS_HFLAG_UM; 2220 /* fall through */ 2221 case OPC_SW: 2222 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUL | 2223 ctx->default_tcg_memop_mask); 2224 break; 2225 case OPC_SHE: 2226 mem_idx = MIPS_HFLAG_UM; 2227 /* fall through */ 2228 case OPC_SH: 2229 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUW | 2230 ctx->default_tcg_memop_mask); 2231 break; 2232 case OPC_SBE: 2233 mem_idx = MIPS_HFLAG_UM; 2234 /* fall through */ 2235 case OPC_SB: 2236 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_8); 2237 break; 2238 case OPC_SWLE: 2239 mem_idx = MIPS_HFLAG_UM; 2240 /* fall through */ 2241 case OPC_SWL: 2242 gen_helper_0e2i(swl, t1, t0, mem_idx); 2243 break; 2244 case OPC_SWRE: 2245 mem_idx = MIPS_HFLAG_UM; 2246 /* fall through */ 2247 case OPC_SWR: 2248 gen_helper_0e2i(swr, t1, t0, mem_idx); 2249 break; 2250 } 2251 } 2252 2253 2254 /* Store conditional */ 2255 static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset, 2256 MemOp tcg_mo, bool eva) 2257 { 2258 TCGv addr, t0, val; 2259 TCGLabel *l1 = gen_new_label(); 2260 TCGLabel *done = gen_new_label(); 2261 2262 t0 = tcg_temp_new(); 2263 addr = tcg_temp_new(); 2264 /* compare the address against that of the preceding LL */ 2265 gen_base_offset_addr(ctx, addr, base, offset); 2266 tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1); 2267 tcg_gen_movi_tl(t0, 0); 2268 gen_store_gpr(t0, rt); 2269 tcg_gen_br(done); 2270 2271 gen_set_label(l1); 2272 /* generate cmpxchg */ 2273 val = tcg_temp_new(); 2274 gen_load_gpr(val, rt); 2275 tcg_gen_atomic_cmpxchg_tl(t0, cpu_lladdr, cpu_llval, val, 2276 eva ? MIPS_HFLAG_UM : ctx->mem_idx, tcg_mo); 2277 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_llval); 2278 gen_store_gpr(t0, rt); 2279 2280 gen_set_label(done); 2281 } 2282 2283 /* Load and store */ 2284 static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft, 2285 TCGv t0) 2286 { 2287 /* 2288 * Don't do NOP if destination is zero: we must perform the actual 2289 * memory access. 2290 */ 2291 switch (opc) { 2292 case OPC_LWC1: 2293 { 2294 TCGv_i32 fp0 = tcg_temp_new_i32(); 2295 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL | 2296 ctx->default_tcg_memop_mask); 2297 gen_store_fpr32(ctx, fp0, ft); 2298 } 2299 break; 2300 case OPC_SWC1: 2301 { 2302 TCGv_i32 fp0 = tcg_temp_new_i32(); 2303 gen_load_fpr32(ctx, fp0, ft); 2304 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL | 2305 ctx->default_tcg_memop_mask); 2306 } 2307 break; 2308 case OPC_LDC1: 2309 { 2310 TCGv_i64 fp0 = tcg_temp_new_i64(); 2311 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ | 2312 ctx->default_tcg_memop_mask); 2313 gen_store_fpr64(ctx, fp0, ft); 2314 } 2315 break; 2316 case OPC_SDC1: 2317 { 2318 TCGv_i64 fp0 = tcg_temp_new_i64(); 2319 gen_load_fpr64(ctx, fp0, ft); 2320 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ | 2321 ctx->default_tcg_memop_mask); 2322 } 2323 break; 2324 default: 2325 MIPS_INVAL("flt_ldst"); 2326 gen_reserved_instruction(ctx); 2327 break; 2328 } 2329 } 2330 2331 static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt, 2332 int rs, int16_t imm) 2333 { 2334 TCGv t0 = tcg_temp_new(); 2335 2336 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { 2337 check_cp1_enabled(ctx); 2338 switch (op) { 2339 case OPC_LDC1: 2340 case OPC_SDC1: 2341 check_insn(ctx, ISA_MIPS2); 2342 /* Fallthrough */ 2343 default: 2344 gen_base_offset_addr(ctx, t0, rs, imm); 2345 gen_flt_ldst(ctx, op, rt, t0); 2346 } 2347 } else { 2348 generate_exception_err(ctx, EXCP_CpU, 1); 2349 } 2350 } 2351 2352 /* Arithmetic with immediate operand */ 2353 static void gen_arith_imm(DisasContext *ctx, uint32_t opc, 2354 int rt, int rs, int imm) 2355 { 2356 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ 2357 2358 if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) { 2359 /* 2360 * If no destination, treat it as a NOP. 2361 * For addi, we must generate the overflow exception when needed. 2362 */ 2363 return; 2364 } 2365 switch (opc) { 2366 case OPC_ADDI: 2367 { 2368 TCGv t0 = tcg_temp_new(); 2369 TCGv t1 = tcg_temp_new(); 2370 TCGv t2 = tcg_temp_new(); 2371 TCGLabel *l1 = gen_new_label(); 2372 2373 gen_load_gpr(t1, rs); 2374 tcg_gen_addi_tl(t0, t1, uimm); 2375 tcg_gen_ext32s_tl(t0, t0); 2376 2377 tcg_gen_xori_tl(t1, t1, ~uimm); 2378 tcg_gen_xori_tl(t2, t0, uimm); 2379 tcg_gen_and_tl(t1, t1, t2); 2380 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2381 /* operands of same sign, result different sign */ 2382 generate_exception(ctx, EXCP_OVERFLOW); 2383 gen_set_label(l1); 2384 tcg_gen_ext32s_tl(t0, t0); 2385 gen_store_gpr(t0, rt); 2386 } 2387 break; 2388 case OPC_ADDIU: 2389 if (rs != 0) { 2390 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); 2391 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 2392 } else { 2393 tcg_gen_movi_tl(cpu_gpr[rt], uimm); 2394 } 2395 break; 2396 #if defined(TARGET_MIPS64) 2397 case OPC_DADDI: 2398 { 2399 TCGv t0 = tcg_temp_new(); 2400 TCGv t1 = tcg_temp_new(); 2401 TCGv t2 = tcg_temp_new(); 2402 TCGLabel *l1 = gen_new_label(); 2403 2404 gen_load_gpr(t1, rs); 2405 tcg_gen_addi_tl(t0, t1, uimm); 2406 2407 tcg_gen_xori_tl(t1, t1, ~uimm); 2408 tcg_gen_xori_tl(t2, t0, uimm); 2409 tcg_gen_and_tl(t1, t1, t2); 2410 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2411 /* operands of same sign, result different sign */ 2412 generate_exception(ctx, EXCP_OVERFLOW); 2413 gen_set_label(l1); 2414 gen_store_gpr(t0, rt); 2415 } 2416 break; 2417 case OPC_DADDIU: 2418 if (rs != 0) { 2419 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); 2420 } else { 2421 tcg_gen_movi_tl(cpu_gpr[rt], uimm); 2422 } 2423 break; 2424 #endif 2425 } 2426 } 2427 2428 /* Logic with immediate operand */ 2429 static void gen_logic_imm(DisasContext *ctx, uint32_t opc, 2430 int rt, int rs, int16_t imm) 2431 { 2432 target_ulong uimm; 2433 2434 if (rt == 0) { 2435 /* If no destination, treat it as a NOP. */ 2436 return; 2437 } 2438 uimm = (uint16_t)imm; 2439 switch (opc) { 2440 case OPC_ANDI: 2441 if (likely(rs != 0)) { 2442 tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); 2443 } else { 2444 tcg_gen_movi_tl(cpu_gpr[rt], 0); 2445 } 2446 break; 2447 case OPC_ORI: 2448 if (rs != 0) { 2449 tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); 2450 } else { 2451 tcg_gen_movi_tl(cpu_gpr[rt], uimm); 2452 } 2453 break; 2454 case OPC_XORI: 2455 if (likely(rs != 0)) { 2456 tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); 2457 } else { 2458 tcg_gen_movi_tl(cpu_gpr[rt], uimm); 2459 } 2460 break; 2461 case OPC_LUI: 2462 if (rs != 0 && (ctx->insn_flags & ISA_MIPS_R6)) { 2463 /* OPC_AUI */ 2464 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm << 16); 2465 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 2466 } else { 2467 tcg_gen_movi_tl(cpu_gpr[rt], imm << 16); 2468 } 2469 break; 2470 2471 default: 2472 break; 2473 } 2474 } 2475 2476 /* Set on less than with immediate operand */ 2477 static void gen_slt_imm(DisasContext *ctx, uint32_t opc, 2478 int rt, int rs, int16_t imm) 2479 { 2480 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ 2481 TCGv t0; 2482 2483 if (rt == 0) { 2484 /* If no destination, treat it as a NOP. */ 2485 return; 2486 } 2487 t0 = tcg_temp_new(); 2488 gen_load_gpr(t0, rs); 2489 switch (opc) { 2490 case OPC_SLTI: 2491 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr[rt], t0, uimm); 2492 break; 2493 case OPC_SLTIU: 2494 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rt], t0, uimm); 2495 break; 2496 } 2497 } 2498 2499 /* Shifts with immediate operand */ 2500 static void gen_shift_imm(DisasContext *ctx, uint32_t opc, 2501 int rt, int rs, int16_t imm) 2502 { 2503 target_ulong uimm = ((uint16_t)imm) & 0x1f; 2504 TCGv t0; 2505 2506 if (rt == 0) { 2507 /* If no destination, treat it as a NOP. */ 2508 return; 2509 } 2510 2511 t0 = tcg_temp_new(); 2512 gen_load_gpr(t0, rs); 2513 switch (opc) { 2514 case OPC_SLL: 2515 tcg_gen_shli_tl(t0, t0, uimm); 2516 tcg_gen_ext32s_tl(cpu_gpr[rt], t0); 2517 break; 2518 case OPC_SRA: 2519 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm); 2520 break; 2521 case OPC_SRL: 2522 if (uimm != 0) { 2523 tcg_gen_ext32u_tl(t0, t0); 2524 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm); 2525 } else { 2526 tcg_gen_ext32s_tl(cpu_gpr[rt], t0); 2527 } 2528 break; 2529 case OPC_ROTR: 2530 if (uimm != 0) { 2531 TCGv_i32 t1 = tcg_temp_new_i32(); 2532 2533 tcg_gen_trunc_tl_i32(t1, t0); 2534 tcg_gen_rotri_i32(t1, t1, uimm); 2535 tcg_gen_ext_i32_tl(cpu_gpr[rt], t1); 2536 } else { 2537 tcg_gen_ext32s_tl(cpu_gpr[rt], t0); 2538 } 2539 break; 2540 #if defined(TARGET_MIPS64) 2541 case OPC_DSLL: 2542 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm); 2543 break; 2544 case OPC_DSRA: 2545 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm); 2546 break; 2547 case OPC_DSRL: 2548 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm); 2549 break; 2550 case OPC_DROTR: 2551 if (uimm != 0) { 2552 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm); 2553 } else { 2554 tcg_gen_mov_tl(cpu_gpr[rt], t0); 2555 } 2556 break; 2557 case OPC_DSLL32: 2558 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm + 32); 2559 break; 2560 case OPC_DSRA32: 2561 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm + 32); 2562 break; 2563 case OPC_DSRL32: 2564 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32); 2565 break; 2566 case OPC_DROTR32: 2567 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm + 32); 2568 break; 2569 #endif 2570 } 2571 } 2572 2573 /* Arithmetic */ 2574 static void gen_arith(DisasContext *ctx, uint32_t opc, 2575 int rd, int rs, int rt) 2576 { 2577 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB 2578 && opc != OPC_DADD && opc != OPC_DSUB) { 2579 /* 2580 * If no destination, treat it as a NOP. 2581 * For add & sub, we must generate the overflow exception when needed. 2582 */ 2583 return; 2584 } 2585 2586 switch (opc) { 2587 case OPC_ADD: 2588 { 2589 TCGv t0 = tcg_temp_new(); 2590 TCGv t1 = tcg_temp_new(); 2591 TCGv t2 = tcg_temp_new(); 2592 TCGLabel *l1 = gen_new_label(); 2593 2594 gen_load_gpr(t1, rs); 2595 gen_load_gpr(t2, rt); 2596 tcg_gen_add_tl(t0, t1, t2); 2597 tcg_gen_ext32s_tl(t0, t0); 2598 tcg_gen_xor_tl(t1, t1, t2); 2599 tcg_gen_xor_tl(t2, t0, t2); 2600 tcg_gen_andc_tl(t1, t2, t1); 2601 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2602 /* operands of same sign, result different sign */ 2603 generate_exception(ctx, EXCP_OVERFLOW); 2604 gen_set_label(l1); 2605 gen_store_gpr(t0, rd); 2606 } 2607 break; 2608 case OPC_ADDU: 2609 if (rs != 0 && rt != 0) { 2610 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2611 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 2612 } else if (rs == 0 && rt != 0) { 2613 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); 2614 } else if (rs != 0 && rt == 0) { 2615 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2616 } else { 2617 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2618 } 2619 break; 2620 case OPC_SUB: 2621 { 2622 TCGv t0 = tcg_temp_new(); 2623 TCGv t1 = tcg_temp_new(); 2624 TCGv t2 = tcg_temp_new(); 2625 TCGLabel *l1 = gen_new_label(); 2626 2627 gen_load_gpr(t1, rs); 2628 gen_load_gpr(t2, rt); 2629 tcg_gen_sub_tl(t0, t1, t2); 2630 tcg_gen_ext32s_tl(t0, t0); 2631 tcg_gen_xor_tl(t2, t1, t2); 2632 tcg_gen_xor_tl(t1, t0, t1); 2633 tcg_gen_and_tl(t1, t1, t2); 2634 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2635 /* 2636 * operands of different sign, first operand and the result 2637 * of different sign 2638 */ 2639 generate_exception(ctx, EXCP_OVERFLOW); 2640 gen_set_label(l1); 2641 gen_store_gpr(t0, rd); 2642 } 2643 break; 2644 case OPC_SUBU: 2645 if (rs != 0 && rt != 0) { 2646 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2647 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 2648 } else if (rs == 0 && rt != 0) { 2649 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]); 2650 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 2651 } else if (rs != 0 && rt == 0) { 2652 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2653 } else { 2654 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2655 } 2656 break; 2657 #if defined(TARGET_MIPS64) 2658 case OPC_DADD: 2659 { 2660 TCGv t0 = tcg_temp_new(); 2661 TCGv t1 = tcg_temp_new(); 2662 TCGv t2 = tcg_temp_new(); 2663 TCGLabel *l1 = gen_new_label(); 2664 2665 gen_load_gpr(t1, rs); 2666 gen_load_gpr(t2, rt); 2667 tcg_gen_add_tl(t0, t1, t2); 2668 tcg_gen_xor_tl(t1, t1, t2); 2669 tcg_gen_xor_tl(t2, t0, t2); 2670 tcg_gen_andc_tl(t1, t2, t1); 2671 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2672 /* operands of same sign, result different sign */ 2673 generate_exception(ctx, EXCP_OVERFLOW); 2674 gen_set_label(l1); 2675 gen_store_gpr(t0, rd); 2676 } 2677 break; 2678 case OPC_DADDU: 2679 if (rs != 0 && rt != 0) { 2680 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2681 } else if (rs == 0 && rt != 0) { 2682 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); 2683 } else if (rs != 0 && rt == 0) { 2684 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2685 } else { 2686 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2687 } 2688 break; 2689 case OPC_DSUB: 2690 { 2691 TCGv t0 = tcg_temp_new(); 2692 TCGv t1 = tcg_temp_new(); 2693 TCGv t2 = tcg_temp_new(); 2694 TCGLabel *l1 = gen_new_label(); 2695 2696 gen_load_gpr(t1, rs); 2697 gen_load_gpr(t2, rt); 2698 tcg_gen_sub_tl(t0, t1, t2); 2699 tcg_gen_xor_tl(t2, t1, t2); 2700 tcg_gen_xor_tl(t1, t0, t1); 2701 tcg_gen_and_tl(t1, t1, t2); 2702 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2703 /* 2704 * Operands of different sign, first operand and result different 2705 * sign. 2706 */ 2707 generate_exception(ctx, EXCP_OVERFLOW); 2708 gen_set_label(l1); 2709 gen_store_gpr(t0, rd); 2710 } 2711 break; 2712 case OPC_DSUBU: 2713 if (rs != 0 && rt != 0) { 2714 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2715 } else if (rs == 0 && rt != 0) { 2716 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]); 2717 } else if (rs != 0 && rt == 0) { 2718 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2719 } else { 2720 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2721 } 2722 break; 2723 #endif 2724 case OPC_MUL: 2725 if (likely(rs != 0 && rt != 0)) { 2726 tcg_gen_mul_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2727 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 2728 } else { 2729 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2730 } 2731 break; 2732 } 2733 } 2734 2735 /* Conditional move */ 2736 static void gen_cond_move(DisasContext *ctx, uint32_t opc, 2737 int rd, int rs, int rt) 2738 { 2739 TCGv t0, t1, t2; 2740 2741 if (rd == 0) { 2742 /* If no destination, treat it as a NOP. */ 2743 return; 2744 } 2745 2746 t0 = tcg_temp_new(); 2747 gen_load_gpr(t0, rt); 2748 t1 = tcg_const_tl(0); 2749 t2 = tcg_temp_new(); 2750 gen_load_gpr(t2, rs); 2751 switch (opc) { 2752 case OPC_MOVN: 2753 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]); 2754 break; 2755 case OPC_MOVZ: 2756 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]); 2757 break; 2758 case OPC_SELNEZ: 2759 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, t1); 2760 break; 2761 case OPC_SELEQZ: 2762 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, t1); 2763 break; 2764 } 2765 } 2766 2767 /* Logic */ 2768 static void gen_logic(DisasContext *ctx, uint32_t opc, 2769 int rd, int rs, int rt) 2770 { 2771 if (rd == 0) { 2772 /* If no destination, treat it as a NOP. */ 2773 return; 2774 } 2775 2776 switch (opc) { 2777 case OPC_AND: 2778 if (likely(rs != 0 && rt != 0)) { 2779 tcg_gen_and_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2780 } else { 2781 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2782 } 2783 break; 2784 case OPC_NOR: 2785 if (rs != 0 && rt != 0) { 2786 tcg_gen_nor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2787 } else if (rs == 0 && rt != 0) { 2788 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rt]); 2789 } else if (rs != 0 && rt == 0) { 2790 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rs]); 2791 } else { 2792 tcg_gen_movi_tl(cpu_gpr[rd], ~((target_ulong)0)); 2793 } 2794 break; 2795 case OPC_OR: 2796 if (likely(rs != 0 && rt != 0)) { 2797 tcg_gen_or_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2798 } else if (rs == 0 && rt != 0) { 2799 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); 2800 } else if (rs != 0 && rt == 0) { 2801 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2802 } else { 2803 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2804 } 2805 break; 2806 case OPC_XOR: 2807 if (likely(rs != 0 && rt != 0)) { 2808 tcg_gen_xor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2809 } else if (rs == 0 && rt != 0) { 2810 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); 2811 } else if (rs != 0 && rt == 0) { 2812 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2813 } else { 2814 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2815 } 2816 break; 2817 } 2818 } 2819 2820 /* Set on lower than */ 2821 static void gen_slt(DisasContext *ctx, uint32_t opc, 2822 int rd, int rs, int rt) 2823 { 2824 TCGv t0, t1; 2825 2826 if (rd == 0) { 2827 /* If no destination, treat it as a NOP. */ 2828 return; 2829 } 2830 2831 t0 = tcg_temp_new(); 2832 t1 = tcg_temp_new(); 2833 gen_load_gpr(t0, rs); 2834 gen_load_gpr(t1, rt); 2835 switch (opc) { 2836 case OPC_SLT: 2837 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr[rd], t0, t1); 2838 break; 2839 case OPC_SLTU: 2840 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr[rd], t0, t1); 2841 break; 2842 } 2843 } 2844 2845 /* Shifts */ 2846 static void gen_shift(DisasContext *ctx, uint32_t opc, 2847 int rd, int rs, int rt) 2848 { 2849 TCGv t0, t1; 2850 2851 if (rd == 0) { 2852 /* 2853 * If no destination, treat it as a NOP. 2854 * For add & sub, we must generate the overflow exception when needed. 2855 */ 2856 return; 2857 } 2858 2859 t0 = tcg_temp_new(); 2860 t1 = tcg_temp_new(); 2861 gen_load_gpr(t0, rs); 2862 gen_load_gpr(t1, rt); 2863 switch (opc) { 2864 case OPC_SLLV: 2865 tcg_gen_andi_tl(t0, t0, 0x1f); 2866 tcg_gen_shl_tl(t0, t1, t0); 2867 tcg_gen_ext32s_tl(cpu_gpr[rd], t0); 2868 break; 2869 case OPC_SRAV: 2870 tcg_gen_andi_tl(t0, t0, 0x1f); 2871 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0); 2872 break; 2873 case OPC_SRLV: 2874 tcg_gen_ext32u_tl(t1, t1); 2875 tcg_gen_andi_tl(t0, t0, 0x1f); 2876 tcg_gen_shr_tl(t0, t1, t0); 2877 tcg_gen_ext32s_tl(cpu_gpr[rd], t0); 2878 break; 2879 case OPC_ROTRV: 2880 { 2881 TCGv_i32 t2 = tcg_temp_new_i32(); 2882 TCGv_i32 t3 = tcg_temp_new_i32(); 2883 2884 tcg_gen_trunc_tl_i32(t2, t0); 2885 tcg_gen_trunc_tl_i32(t3, t1); 2886 tcg_gen_andi_i32(t2, t2, 0x1f); 2887 tcg_gen_rotr_i32(t2, t3, t2); 2888 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); 2889 } 2890 break; 2891 #if defined(TARGET_MIPS64) 2892 case OPC_DSLLV: 2893 tcg_gen_andi_tl(t0, t0, 0x3f); 2894 tcg_gen_shl_tl(cpu_gpr[rd], t1, t0); 2895 break; 2896 case OPC_DSRAV: 2897 tcg_gen_andi_tl(t0, t0, 0x3f); 2898 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0); 2899 break; 2900 case OPC_DSRLV: 2901 tcg_gen_andi_tl(t0, t0, 0x3f); 2902 tcg_gen_shr_tl(cpu_gpr[rd], t1, t0); 2903 break; 2904 case OPC_DROTRV: 2905 tcg_gen_andi_tl(t0, t0, 0x3f); 2906 tcg_gen_rotr_tl(cpu_gpr[rd], t1, t0); 2907 break; 2908 #endif 2909 } 2910 } 2911 2912 /* Arithmetic on HI/LO registers */ 2913 static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) 2914 { 2915 if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) { 2916 /* Treat as NOP. */ 2917 return; 2918 } 2919 2920 if (acc != 0) { 2921 check_dsp(ctx); 2922 } 2923 2924 switch (opc) { 2925 case OPC_MFHI: 2926 #if defined(TARGET_MIPS64) 2927 if (acc != 0) { 2928 tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]); 2929 } else 2930 #endif 2931 { 2932 tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[acc]); 2933 } 2934 break; 2935 case OPC_MFLO: 2936 #if defined(TARGET_MIPS64) 2937 if (acc != 0) { 2938 tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]); 2939 } else 2940 #endif 2941 { 2942 tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[acc]); 2943 } 2944 break; 2945 case OPC_MTHI: 2946 if (reg != 0) { 2947 #if defined(TARGET_MIPS64) 2948 if (acc != 0) { 2949 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_gpr[reg]); 2950 } else 2951 #endif 2952 { 2953 tcg_gen_mov_tl(cpu_HI[acc], cpu_gpr[reg]); 2954 } 2955 } else { 2956 tcg_gen_movi_tl(cpu_HI[acc], 0); 2957 } 2958 break; 2959 case OPC_MTLO: 2960 if (reg != 0) { 2961 #if defined(TARGET_MIPS64) 2962 if (acc != 0) { 2963 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_gpr[reg]); 2964 } else 2965 #endif 2966 { 2967 tcg_gen_mov_tl(cpu_LO[acc], cpu_gpr[reg]); 2968 } 2969 } else { 2970 tcg_gen_movi_tl(cpu_LO[acc], 0); 2971 } 2972 break; 2973 } 2974 } 2975 2976 static inline void gen_r6_ld(target_long addr, int reg, int memidx, 2977 MemOp memop) 2978 { 2979 TCGv t0 = tcg_const_tl(addr); 2980 tcg_gen_qemu_ld_tl(t0, t0, memidx, memop); 2981 gen_store_gpr(t0, reg); 2982 } 2983 2984 static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc, 2985 int rs) 2986 { 2987 target_long offset; 2988 target_long addr; 2989 2990 switch (MASK_OPC_PCREL_TOP2BITS(opc)) { 2991 case OPC_ADDIUPC: 2992 if (rs != 0) { 2993 offset = sextract32(ctx->opcode << 2, 0, 21); 2994 addr = addr_add(ctx, pc, offset); 2995 tcg_gen_movi_tl(cpu_gpr[rs], addr); 2996 } 2997 break; 2998 case R6_OPC_LWPC: 2999 offset = sextract32(ctx->opcode << 2, 0, 21); 3000 addr = addr_add(ctx, pc, offset); 3001 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TESL); 3002 break; 3003 #if defined(TARGET_MIPS64) 3004 case OPC_LWUPC: 3005 check_mips_64(ctx); 3006 offset = sextract32(ctx->opcode << 2, 0, 21); 3007 addr = addr_add(ctx, pc, offset); 3008 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUL); 3009 break; 3010 #endif 3011 default: 3012 switch (MASK_OPC_PCREL_TOP5BITS(opc)) { 3013 case OPC_AUIPC: 3014 if (rs != 0) { 3015 offset = sextract32(ctx->opcode, 0, 16) << 16; 3016 addr = addr_add(ctx, pc, offset); 3017 tcg_gen_movi_tl(cpu_gpr[rs], addr); 3018 } 3019 break; 3020 case OPC_ALUIPC: 3021 if (rs != 0) { 3022 offset = sextract32(ctx->opcode, 0, 16) << 16; 3023 addr = ~0xFFFF & addr_add(ctx, pc, offset); 3024 tcg_gen_movi_tl(cpu_gpr[rs], addr); 3025 } 3026 break; 3027 #if defined(TARGET_MIPS64) 3028 case R6_OPC_LDPC: /* bits 16 and 17 are part of immediate */ 3029 case R6_OPC_LDPC + (1 << 16): 3030 case R6_OPC_LDPC + (2 << 16): 3031 case R6_OPC_LDPC + (3 << 16): 3032 check_mips_64(ctx); 3033 offset = sextract32(ctx->opcode << 3, 0, 21); 3034 addr = addr_add(ctx, (pc & ~0x7), offset); 3035 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUQ); 3036 break; 3037 #endif 3038 default: 3039 MIPS_INVAL("OPC_PCREL"); 3040 gen_reserved_instruction(ctx); 3041 break; 3042 } 3043 break; 3044 } 3045 } 3046 3047 static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) 3048 { 3049 TCGv t0, t1; 3050 3051 if (rd == 0) { 3052 /* Treat as NOP. */ 3053 return; 3054 } 3055 3056 t0 = tcg_temp_new(); 3057 t1 = tcg_temp_new(); 3058 3059 gen_load_gpr(t0, rs); 3060 gen_load_gpr(t1, rt); 3061 3062 switch (opc) { 3063 case R6_OPC_DIV: 3064 { 3065 TCGv t2 = tcg_temp_new(); 3066 TCGv t3 = tcg_temp_new(); 3067 tcg_gen_ext32s_tl(t0, t0); 3068 tcg_gen_ext32s_tl(t1, t1); 3069 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); 3070 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); 3071 tcg_gen_and_tl(t2, t2, t3); 3072 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3073 tcg_gen_or_tl(t2, t2, t3); 3074 tcg_gen_movi_tl(t3, 0); 3075 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3076 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); 3077 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3078 } 3079 break; 3080 case R6_OPC_MOD: 3081 { 3082 TCGv t2 = tcg_temp_new(); 3083 TCGv t3 = tcg_temp_new(); 3084 tcg_gen_ext32s_tl(t0, t0); 3085 tcg_gen_ext32s_tl(t1, t1); 3086 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); 3087 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); 3088 tcg_gen_and_tl(t2, t2, t3); 3089 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3090 tcg_gen_or_tl(t2, t2, t3); 3091 tcg_gen_movi_tl(t3, 0); 3092 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3093 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); 3094 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3095 } 3096 break; 3097 case R6_OPC_DIVU: 3098 { 3099 TCGv t2 = tcg_const_tl(0); 3100 TCGv t3 = tcg_const_tl(1); 3101 tcg_gen_ext32u_tl(t0, t0); 3102 tcg_gen_ext32u_tl(t1, t1); 3103 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3104 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); 3105 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3106 } 3107 break; 3108 case R6_OPC_MODU: 3109 { 3110 TCGv t2 = tcg_const_tl(0); 3111 TCGv t3 = tcg_const_tl(1); 3112 tcg_gen_ext32u_tl(t0, t0); 3113 tcg_gen_ext32u_tl(t1, t1); 3114 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3115 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); 3116 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3117 } 3118 break; 3119 case R6_OPC_MUL: 3120 { 3121 TCGv_i32 t2 = tcg_temp_new_i32(); 3122 TCGv_i32 t3 = tcg_temp_new_i32(); 3123 tcg_gen_trunc_tl_i32(t2, t0); 3124 tcg_gen_trunc_tl_i32(t3, t1); 3125 tcg_gen_mul_i32(t2, t2, t3); 3126 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); 3127 } 3128 break; 3129 case R6_OPC_MUH: 3130 { 3131 TCGv_i32 t2 = tcg_temp_new_i32(); 3132 TCGv_i32 t3 = tcg_temp_new_i32(); 3133 tcg_gen_trunc_tl_i32(t2, t0); 3134 tcg_gen_trunc_tl_i32(t3, t1); 3135 tcg_gen_muls2_i32(t2, t3, t2, t3); 3136 tcg_gen_ext_i32_tl(cpu_gpr[rd], t3); 3137 } 3138 break; 3139 case R6_OPC_MULU: 3140 { 3141 TCGv_i32 t2 = tcg_temp_new_i32(); 3142 TCGv_i32 t3 = tcg_temp_new_i32(); 3143 tcg_gen_trunc_tl_i32(t2, t0); 3144 tcg_gen_trunc_tl_i32(t3, t1); 3145 tcg_gen_mul_i32(t2, t2, t3); 3146 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); 3147 } 3148 break; 3149 case R6_OPC_MUHU: 3150 { 3151 TCGv_i32 t2 = tcg_temp_new_i32(); 3152 TCGv_i32 t3 = tcg_temp_new_i32(); 3153 tcg_gen_trunc_tl_i32(t2, t0); 3154 tcg_gen_trunc_tl_i32(t3, t1); 3155 tcg_gen_mulu2_i32(t2, t3, t2, t3); 3156 tcg_gen_ext_i32_tl(cpu_gpr[rd], t3); 3157 } 3158 break; 3159 #if defined(TARGET_MIPS64) 3160 case R6_OPC_DDIV: 3161 { 3162 TCGv t2 = tcg_temp_new(); 3163 TCGv t3 = tcg_temp_new(); 3164 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); 3165 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); 3166 tcg_gen_and_tl(t2, t2, t3); 3167 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3168 tcg_gen_or_tl(t2, t2, t3); 3169 tcg_gen_movi_tl(t3, 0); 3170 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3171 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); 3172 } 3173 break; 3174 case R6_OPC_DMOD: 3175 { 3176 TCGv t2 = tcg_temp_new(); 3177 TCGv t3 = tcg_temp_new(); 3178 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); 3179 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); 3180 tcg_gen_and_tl(t2, t2, t3); 3181 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3182 tcg_gen_or_tl(t2, t2, t3); 3183 tcg_gen_movi_tl(t3, 0); 3184 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3185 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); 3186 } 3187 break; 3188 case R6_OPC_DDIVU: 3189 { 3190 TCGv t2 = tcg_const_tl(0); 3191 TCGv t3 = tcg_const_tl(1); 3192 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3193 tcg_gen_divu_i64(cpu_gpr[rd], t0, t1); 3194 } 3195 break; 3196 case R6_OPC_DMODU: 3197 { 3198 TCGv t2 = tcg_const_tl(0); 3199 TCGv t3 = tcg_const_tl(1); 3200 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3201 tcg_gen_remu_i64(cpu_gpr[rd], t0, t1); 3202 } 3203 break; 3204 case R6_OPC_DMUL: 3205 tcg_gen_mul_i64(cpu_gpr[rd], t0, t1); 3206 break; 3207 case R6_OPC_DMUH: 3208 { 3209 TCGv t2 = tcg_temp_new(); 3210 tcg_gen_muls2_i64(t2, cpu_gpr[rd], t0, t1); 3211 } 3212 break; 3213 case R6_OPC_DMULU: 3214 tcg_gen_mul_i64(cpu_gpr[rd], t0, t1); 3215 break; 3216 case R6_OPC_DMUHU: 3217 { 3218 TCGv t2 = tcg_temp_new(); 3219 tcg_gen_mulu2_i64(t2, cpu_gpr[rd], t0, t1); 3220 } 3221 break; 3222 #endif 3223 default: 3224 MIPS_INVAL("r6 mul/div"); 3225 gen_reserved_instruction(ctx); 3226 break; 3227 } 3228 } 3229 3230 #if defined(TARGET_MIPS64) 3231 static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt) 3232 { 3233 TCGv t0, t1; 3234 3235 t0 = tcg_temp_new(); 3236 t1 = tcg_temp_new(); 3237 3238 gen_load_gpr(t0, rs); 3239 gen_load_gpr(t1, rt); 3240 3241 switch (opc) { 3242 case MMI_OPC_DIV1: 3243 { 3244 TCGv t2 = tcg_temp_new(); 3245 TCGv t3 = tcg_temp_new(); 3246 tcg_gen_ext32s_tl(t0, t0); 3247 tcg_gen_ext32s_tl(t1, t1); 3248 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); 3249 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); 3250 tcg_gen_and_tl(t2, t2, t3); 3251 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3252 tcg_gen_or_tl(t2, t2, t3); 3253 tcg_gen_movi_tl(t3, 0); 3254 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3255 tcg_gen_div_tl(cpu_LO[1], t0, t1); 3256 tcg_gen_rem_tl(cpu_HI[1], t0, t1); 3257 tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]); 3258 tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]); 3259 } 3260 break; 3261 case MMI_OPC_DIVU1: 3262 { 3263 TCGv t2 = tcg_const_tl(0); 3264 TCGv t3 = tcg_const_tl(1); 3265 tcg_gen_ext32u_tl(t0, t0); 3266 tcg_gen_ext32u_tl(t1, t1); 3267 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3268 tcg_gen_divu_tl(cpu_LO[1], t0, t1); 3269 tcg_gen_remu_tl(cpu_HI[1], t0, t1); 3270 tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]); 3271 tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]); 3272 } 3273 break; 3274 default: 3275 MIPS_INVAL("div1 TX79"); 3276 gen_reserved_instruction(ctx); 3277 break; 3278 } 3279 } 3280 #endif 3281 3282 static void gen_muldiv(DisasContext *ctx, uint32_t opc, 3283 int acc, int rs, int rt) 3284 { 3285 TCGv t0, t1; 3286 3287 t0 = tcg_temp_new(); 3288 t1 = tcg_temp_new(); 3289 3290 gen_load_gpr(t0, rs); 3291 gen_load_gpr(t1, rt); 3292 3293 if (acc != 0) { 3294 check_dsp(ctx); 3295 } 3296 3297 switch (opc) { 3298 case OPC_DIV: 3299 { 3300 TCGv t2 = tcg_temp_new(); 3301 TCGv t3 = tcg_temp_new(); 3302 tcg_gen_ext32s_tl(t0, t0); 3303 tcg_gen_ext32s_tl(t1, t1); 3304 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); 3305 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); 3306 tcg_gen_and_tl(t2, t2, t3); 3307 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3308 tcg_gen_or_tl(t2, t2, t3); 3309 tcg_gen_movi_tl(t3, 0); 3310 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3311 tcg_gen_div_tl(cpu_LO[acc], t0, t1); 3312 tcg_gen_rem_tl(cpu_HI[acc], t0, t1); 3313 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]); 3314 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]); 3315 } 3316 break; 3317 case OPC_DIVU: 3318 { 3319 TCGv t2 = tcg_const_tl(0); 3320 TCGv t3 = tcg_const_tl(1); 3321 tcg_gen_ext32u_tl(t0, t0); 3322 tcg_gen_ext32u_tl(t1, t1); 3323 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3324 tcg_gen_divu_tl(cpu_LO[acc], t0, t1); 3325 tcg_gen_remu_tl(cpu_HI[acc], t0, t1); 3326 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]); 3327 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]); 3328 } 3329 break; 3330 case OPC_MULT: 3331 { 3332 TCGv_i32 t2 = tcg_temp_new_i32(); 3333 TCGv_i32 t3 = tcg_temp_new_i32(); 3334 tcg_gen_trunc_tl_i32(t2, t0); 3335 tcg_gen_trunc_tl_i32(t3, t1); 3336 tcg_gen_muls2_i32(t2, t3, t2, t3); 3337 tcg_gen_ext_i32_tl(cpu_LO[acc], t2); 3338 tcg_gen_ext_i32_tl(cpu_HI[acc], t3); 3339 } 3340 break; 3341 case OPC_MULTU: 3342 { 3343 TCGv_i32 t2 = tcg_temp_new_i32(); 3344 TCGv_i32 t3 = tcg_temp_new_i32(); 3345 tcg_gen_trunc_tl_i32(t2, t0); 3346 tcg_gen_trunc_tl_i32(t3, t1); 3347 tcg_gen_mulu2_i32(t2, t3, t2, t3); 3348 tcg_gen_ext_i32_tl(cpu_LO[acc], t2); 3349 tcg_gen_ext_i32_tl(cpu_HI[acc], t3); 3350 } 3351 break; 3352 #if defined(TARGET_MIPS64) 3353 case OPC_DDIV: 3354 { 3355 TCGv t2 = tcg_temp_new(); 3356 TCGv t3 = tcg_temp_new(); 3357 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); 3358 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); 3359 tcg_gen_and_tl(t2, t2, t3); 3360 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3361 tcg_gen_or_tl(t2, t2, t3); 3362 tcg_gen_movi_tl(t3, 0); 3363 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3364 tcg_gen_div_tl(cpu_LO[acc], t0, t1); 3365 tcg_gen_rem_tl(cpu_HI[acc], t0, t1); 3366 } 3367 break; 3368 case OPC_DDIVU: 3369 { 3370 TCGv t2 = tcg_const_tl(0); 3371 TCGv t3 = tcg_const_tl(1); 3372 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3373 tcg_gen_divu_i64(cpu_LO[acc], t0, t1); 3374 tcg_gen_remu_i64(cpu_HI[acc], t0, t1); 3375 } 3376 break; 3377 case OPC_DMULT: 3378 tcg_gen_muls2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1); 3379 break; 3380 case OPC_DMULTU: 3381 tcg_gen_mulu2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1); 3382 break; 3383 #endif 3384 case OPC_MADD: 3385 { 3386 TCGv_i64 t2 = tcg_temp_new_i64(); 3387 TCGv_i64 t3 = tcg_temp_new_i64(); 3388 3389 tcg_gen_ext_tl_i64(t2, t0); 3390 tcg_gen_ext_tl_i64(t3, t1); 3391 tcg_gen_mul_i64(t2, t2, t3); 3392 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3393 tcg_gen_add_i64(t2, t2, t3); 3394 gen_move_low32(cpu_LO[acc], t2); 3395 gen_move_high32(cpu_HI[acc], t2); 3396 } 3397 break; 3398 case OPC_MADDU: 3399 { 3400 TCGv_i64 t2 = tcg_temp_new_i64(); 3401 TCGv_i64 t3 = tcg_temp_new_i64(); 3402 3403 tcg_gen_ext32u_tl(t0, t0); 3404 tcg_gen_ext32u_tl(t1, t1); 3405 tcg_gen_extu_tl_i64(t2, t0); 3406 tcg_gen_extu_tl_i64(t3, t1); 3407 tcg_gen_mul_i64(t2, t2, t3); 3408 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3409 tcg_gen_add_i64(t2, t2, t3); 3410 gen_move_low32(cpu_LO[acc], t2); 3411 gen_move_high32(cpu_HI[acc], t2); 3412 } 3413 break; 3414 case OPC_MSUB: 3415 { 3416 TCGv_i64 t2 = tcg_temp_new_i64(); 3417 TCGv_i64 t3 = tcg_temp_new_i64(); 3418 3419 tcg_gen_ext_tl_i64(t2, t0); 3420 tcg_gen_ext_tl_i64(t3, t1); 3421 tcg_gen_mul_i64(t2, t2, t3); 3422 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3423 tcg_gen_sub_i64(t2, t3, t2); 3424 gen_move_low32(cpu_LO[acc], t2); 3425 gen_move_high32(cpu_HI[acc], t2); 3426 } 3427 break; 3428 case OPC_MSUBU: 3429 { 3430 TCGv_i64 t2 = tcg_temp_new_i64(); 3431 TCGv_i64 t3 = tcg_temp_new_i64(); 3432 3433 tcg_gen_ext32u_tl(t0, t0); 3434 tcg_gen_ext32u_tl(t1, t1); 3435 tcg_gen_extu_tl_i64(t2, t0); 3436 tcg_gen_extu_tl_i64(t3, t1); 3437 tcg_gen_mul_i64(t2, t2, t3); 3438 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3439 tcg_gen_sub_i64(t2, t3, t2); 3440 gen_move_low32(cpu_LO[acc], t2); 3441 gen_move_high32(cpu_HI[acc], t2); 3442 } 3443 break; 3444 default: 3445 MIPS_INVAL("mul/div"); 3446 gen_reserved_instruction(ctx); 3447 break; 3448 } 3449 } 3450 3451 /* 3452 * These MULT[U] and MADD[U] instructions implemented in for example 3453 * the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core 3454 * architectures are special three-operand variants with the syntax 3455 * 3456 * MULT[U][1] rd, rs, rt 3457 * 3458 * such that 3459 * 3460 * (rd, LO, HI) <- rs * rt 3461 * 3462 * and 3463 * 3464 * MADD[U][1] rd, rs, rt 3465 * 3466 * such that 3467 * 3468 * (rd, LO, HI) <- (LO, HI) + rs * rt 3469 * 3470 * where the low-order 32-bits of the result is placed into both the 3471 * GPR rd and the special register LO. The high-order 32-bits of the 3472 * result is placed into the special register HI. 3473 * 3474 * If the GPR rd is omitted in assembly language, it is taken to be 0, 3475 * which is the zero register that always reads as 0. 3476 */ 3477 static void gen_mul_txx9(DisasContext *ctx, uint32_t opc, 3478 int rd, int rs, int rt) 3479 { 3480 TCGv t0 = tcg_temp_new(); 3481 TCGv t1 = tcg_temp_new(); 3482 int acc = 0; 3483 3484 gen_load_gpr(t0, rs); 3485 gen_load_gpr(t1, rt); 3486 3487 switch (opc) { 3488 case MMI_OPC_MULT1: 3489 acc = 1; 3490 /* Fall through */ 3491 case OPC_MULT: 3492 { 3493 TCGv_i32 t2 = tcg_temp_new_i32(); 3494 TCGv_i32 t3 = tcg_temp_new_i32(); 3495 tcg_gen_trunc_tl_i32(t2, t0); 3496 tcg_gen_trunc_tl_i32(t3, t1); 3497 tcg_gen_muls2_i32(t2, t3, t2, t3); 3498 if (rd) { 3499 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); 3500 } 3501 tcg_gen_ext_i32_tl(cpu_LO[acc], t2); 3502 tcg_gen_ext_i32_tl(cpu_HI[acc], t3); 3503 } 3504 break; 3505 case MMI_OPC_MULTU1: 3506 acc = 1; 3507 /* Fall through */ 3508 case OPC_MULTU: 3509 { 3510 TCGv_i32 t2 = tcg_temp_new_i32(); 3511 TCGv_i32 t3 = tcg_temp_new_i32(); 3512 tcg_gen_trunc_tl_i32(t2, t0); 3513 tcg_gen_trunc_tl_i32(t3, t1); 3514 tcg_gen_mulu2_i32(t2, t3, t2, t3); 3515 if (rd) { 3516 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); 3517 } 3518 tcg_gen_ext_i32_tl(cpu_LO[acc], t2); 3519 tcg_gen_ext_i32_tl(cpu_HI[acc], t3); 3520 } 3521 break; 3522 case MMI_OPC_MADD1: 3523 acc = 1; 3524 /* Fall through */ 3525 case MMI_OPC_MADD: 3526 { 3527 TCGv_i64 t2 = tcg_temp_new_i64(); 3528 TCGv_i64 t3 = tcg_temp_new_i64(); 3529 3530 tcg_gen_ext_tl_i64(t2, t0); 3531 tcg_gen_ext_tl_i64(t3, t1); 3532 tcg_gen_mul_i64(t2, t2, t3); 3533 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3534 tcg_gen_add_i64(t2, t2, t3); 3535 gen_move_low32(cpu_LO[acc], t2); 3536 gen_move_high32(cpu_HI[acc], t2); 3537 if (rd) { 3538 gen_move_low32(cpu_gpr[rd], t2); 3539 } 3540 } 3541 break; 3542 case MMI_OPC_MADDU1: 3543 acc = 1; 3544 /* Fall through */ 3545 case MMI_OPC_MADDU: 3546 { 3547 TCGv_i64 t2 = tcg_temp_new_i64(); 3548 TCGv_i64 t3 = tcg_temp_new_i64(); 3549 3550 tcg_gen_ext32u_tl(t0, t0); 3551 tcg_gen_ext32u_tl(t1, t1); 3552 tcg_gen_extu_tl_i64(t2, t0); 3553 tcg_gen_extu_tl_i64(t3, t1); 3554 tcg_gen_mul_i64(t2, t2, t3); 3555 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3556 tcg_gen_add_i64(t2, t2, t3); 3557 gen_move_low32(cpu_LO[acc], t2); 3558 gen_move_high32(cpu_HI[acc], t2); 3559 if (rd) { 3560 gen_move_low32(cpu_gpr[rd], t2); 3561 } 3562 } 3563 break; 3564 default: 3565 MIPS_INVAL("mul/madd TXx9"); 3566 gen_reserved_instruction(ctx); 3567 break; 3568 } 3569 } 3570 3571 static void gen_cl(DisasContext *ctx, uint32_t opc, 3572 int rd, int rs) 3573 { 3574 TCGv t0; 3575 3576 if (rd == 0) { 3577 /* Treat as NOP. */ 3578 return; 3579 } 3580 t0 = cpu_gpr[rd]; 3581 gen_load_gpr(t0, rs); 3582 3583 switch (opc) { 3584 case OPC_CLO: 3585 case R6_OPC_CLO: 3586 #if defined(TARGET_MIPS64) 3587 case OPC_DCLO: 3588 case R6_OPC_DCLO: 3589 #endif 3590 tcg_gen_not_tl(t0, t0); 3591 break; 3592 } 3593 3594 switch (opc) { 3595 case OPC_CLO: 3596 case R6_OPC_CLO: 3597 case OPC_CLZ: 3598 case R6_OPC_CLZ: 3599 tcg_gen_ext32u_tl(t0, t0); 3600 tcg_gen_clzi_tl(t0, t0, TARGET_LONG_BITS); 3601 tcg_gen_subi_tl(t0, t0, TARGET_LONG_BITS - 32); 3602 break; 3603 #if defined(TARGET_MIPS64) 3604 case OPC_DCLO: 3605 case R6_OPC_DCLO: 3606 case OPC_DCLZ: 3607 case R6_OPC_DCLZ: 3608 tcg_gen_clzi_i64(t0, t0, 64); 3609 break; 3610 #endif 3611 } 3612 } 3613 3614 /* Godson integer instructions */ 3615 static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, 3616 int rd, int rs, int rt) 3617 { 3618 TCGv t0, t1; 3619 3620 if (rd == 0) { 3621 /* Treat as NOP. */ 3622 return; 3623 } 3624 3625 t0 = tcg_temp_new(); 3626 t1 = tcg_temp_new(); 3627 gen_load_gpr(t0, rs); 3628 gen_load_gpr(t1, rt); 3629 3630 switch (opc) { 3631 case OPC_MULT_G_2E: 3632 case OPC_MULT_G_2F: 3633 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); 3634 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3635 break; 3636 case OPC_MULTU_G_2E: 3637 case OPC_MULTU_G_2F: 3638 tcg_gen_ext32u_tl(t0, t0); 3639 tcg_gen_ext32u_tl(t1, t1); 3640 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); 3641 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3642 break; 3643 case OPC_DIV_G_2E: 3644 case OPC_DIV_G_2F: 3645 { 3646 TCGLabel *l1 = gen_new_label(); 3647 TCGLabel *l2 = gen_new_label(); 3648 TCGLabel *l3 = gen_new_label(); 3649 tcg_gen_ext32s_tl(t0, t0); 3650 tcg_gen_ext32s_tl(t1, t1); 3651 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3652 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3653 tcg_gen_br(l3); 3654 gen_set_label(l1); 3655 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2); 3656 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2); 3657 tcg_gen_mov_tl(cpu_gpr[rd], t0); 3658 tcg_gen_br(l3); 3659 gen_set_label(l2); 3660 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); 3661 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3662 gen_set_label(l3); 3663 } 3664 break; 3665 case OPC_DIVU_G_2E: 3666 case OPC_DIVU_G_2F: 3667 { 3668 TCGLabel *l1 = gen_new_label(); 3669 TCGLabel *l2 = gen_new_label(); 3670 tcg_gen_ext32u_tl(t0, t0); 3671 tcg_gen_ext32u_tl(t1, t1); 3672 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3673 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3674 tcg_gen_br(l2); 3675 gen_set_label(l1); 3676 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); 3677 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3678 gen_set_label(l2); 3679 } 3680 break; 3681 case OPC_MOD_G_2E: 3682 case OPC_MOD_G_2F: 3683 { 3684 TCGLabel *l1 = gen_new_label(); 3685 TCGLabel *l2 = gen_new_label(); 3686 TCGLabel *l3 = gen_new_label(); 3687 tcg_gen_ext32u_tl(t0, t0); 3688 tcg_gen_ext32u_tl(t1, t1); 3689 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 3690 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2); 3691 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2); 3692 gen_set_label(l1); 3693 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3694 tcg_gen_br(l3); 3695 gen_set_label(l2); 3696 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); 3697 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3698 gen_set_label(l3); 3699 } 3700 break; 3701 case OPC_MODU_G_2E: 3702 case OPC_MODU_G_2F: 3703 { 3704 TCGLabel *l1 = gen_new_label(); 3705 TCGLabel *l2 = gen_new_label(); 3706 tcg_gen_ext32u_tl(t0, t0); 3707 tcg_gen_ext32u_tl(t1, t1); 3708 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3709 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3710 tcg_gen_br(l2); 3711 gen_set_label(l1); 3712 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); 3713 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3714 gen_set_label(l2); 3715 } 3716 break; 3717 #if defined(TARGET_MIPS64) 3718 case OPC_DMULT_G_2E: 3719 case OPC_DMULT_G_2F: 3720 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); 3721 break; 3722 case OPC_DMULTU_G_2E: 3723 case OPC_DMULTU_G_2F: 3724 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); 3725 break; 3726 case OPC_DDIV_G_2E: 3727 case OPC_DDIV_G_2F: 3728 { 3729 TCGLabel *l1 = gen_new_label(); 3730 TCGLabel *l2 = gen_new_label(); 3731 TCGLabel *l3 = gen_new_label(); 3732 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3733 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3734 tcg_gen_br(l3); 3735 gen_set_label(l1); 3736 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); 3737 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); 3738 tcg_gen_mov_tl(cpu_gpr[rd], t0); 3739 tcg_gen_br(l3); 3740 gen_set_label(l2); 3741 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); 3742 gen_set_label(l3); 3743 } 3744 break; 3745 case OPC_DDIVU_G_2E: 3746 case OPC_DDIVU_G_2F: 3747 { 3748 TCGLabel *l1 = gen_new_label(); 3749 TCGLabel *l2 = gen_new_label(); 3750 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3751 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3752 tcg_gen_br(l2); 3753 gen_set_label(l1); 3754 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); 3755 gen_set_label(l2); 3756 } 3757 break; 3758 case OPC_DMOD_G_2E: 3759 case OPC_DMOD_G_2F: 3760 { 3761 TCGLabel *l1 = gen_new_label(); 3762 TCGLabel *l2 = gen_new_label(); 3763 TCGLabel *l3 = gen_new_label(); 3764 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 3765 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); 3766 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); 3767 gen_set_label(l1); 3768 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3769 tcg_gen_br(l3); 3770 gen_set_label(l2); 3771 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); 3772 gen_set_label(l3); 3773 } 3774 break; 3775 case OPC_DMODU_G_2E: 3776 case OPC_DMODU_G_2F: 3777 { 3778 TCGLabel *l1 = gen_new_label(); 3779 TCGLabel *l2 = gen_new_label(); 3780 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3781 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3782 tcg_gen_br(l2); 3783 gen_set_label(l1); 3784 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); 3785 gen_set_label(l2); 3786 } 3787 break; 3788 #endif 3789 } 3790 } 3791 3792 /* Loongson multimedia instructions */ 3793 static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) 3794 { 3795 uint32_t opc, shift_max; 3796 TCGv_i64 t0, t1; 3797 TCGCond cond; 3798 3799 opc = MASK_LMMI(ctx->opcode); 3800 check_cp1_enabled(ctx); 3801 3802 t0 = tcg_temp_new_i64(); 3803 t1 = tcg_temp_new_i64(); 3804 gen_load_fpr64(ctx, t0, rs); 3805 gen_load_fpr64(ctx, t1, rt); 3806 3807 switch (opc) { 3808 case OPC_PADDSH: 3809 gen_helper_paddsh(t0, t0, t1); 3810 break; 3811 case OPC_PADDUSH: 3812 gen_helper_paddush(t0, t0, t1); 3813 break; 3814 case OPC_PADDH: 3815 gen_helper_paddh(t0, t0, t1); 3816 break; 3817 case OPC_PADDW: 3818 gen_helper_paddw(t0, t0, t1); 3819 break; 3820 case OPC_PADDSB: 3821 gen_helper_paddsb(t0, t0, t1); 3822 break; 3823 case OPC_PADDUSB: 3824 gen_helper_paddusb(t0, t0, t1); 3825 break; 3826 case OPC_PADDB: 3827 gen_helper_paddb(t0, t0, t1); 3828 break; 3829 3830 case OPC_PSUBSH: 3831 gen_helper_psubsh(t0, t0, t1); 3832 break; 3833 case OPC_PSUBUSH: 3834 gen_helper_psubush(t0, t0, t1); 3835 break; 3836 case OPC_PSUBH: 3837 gen_helper_psubh(t0, t0, t1); 3838 break; 3839 case OPC_PSUBW: 3840 gen_helper_psubw(t0, t0, t1); 3841 break; 3842 case OPC_PSUBSB: 3843 gen_helper_psubsb(t0, t0, t1); 3844 break; 3845 case OPC_PSUBUSB: 3846 gen_helper_psubusb(t0, t0, t1); 3847 break; 3848 case OPC_PSUBB: 3849 gen_helper_psubb(t0, t0, t1); 3850 break; 3851 3852 case OPC_PSHUFH: 3853 gen_helper_pshufh(t0, t0, t1); 3854 break; 3855 case OPC_PACKSSWH: 3856 gen_helper_packsswh(t0, t0, t1); 3857 break; 3858 case OPC_PACKSSHB: 3859 gen_helper_packsshb(t0, t0, t1); 3860 break; 3861 case OPC_PACKUSHB: 3862 gen_helper_packushb(t0, t0, t1); 3863 break; 3864 3865 case OPC_PUNPCKLHW: 3866 gen_helper_punpcklhw(t0, t0, t1); 3867 break; 3868 case OPC_PUNPCKHHW: 3869 gen_helper_punpckhhw(t0, t0, t1); 3870 break; 3871 case OPC_PUNPCKLBH: 3872 gen_helper_punpcklbh(t0, t0, t1); 3873 break; 3874 case OPC_PUNPCKHBH: 3875 gen_helper_punpckhbh(t0, t0, t1); 3876 break; 3877 case OPC_PUNPCKLWD: 3878 gen_helper_punpcklwd(t0, t0, t1); 3879 break; 3880 case OPC_PUNPCKHWD: 3881 gen_helper_punpckhwd(t0, t0, t1); 3882 break; 3883 3884 case OPC_PAVGH: 3885 gen_helper_pavgh(t0, t0, t1); 3886 break; 3887 case OPC_PAVGB: 3888 gen_helper_pavgb(t0, t0, t1); 3889 break; 3890 case OPC_PMAXSH: 3891 gen_helper_pmaxsh(t0, t0, t1); 3892 break; 3893 case OPC_PMINSH: 3894 gen_helper_pminsh(t0, t0, t1); 3895 break; 3896 case OPC_PMAXUB: 3897 gen_helper_pmaxub(t0, t0, t1); 3898 break; 3899 case OPC_PMINUB: 3900 gen_helper_pminub(t0, t0, t1); 3901 break; 3902 3903 case OPC_PCMPEQW: 3904 gen_helper_pcmpeqw(t0, t0, t1); 3905 break; 3906 case OPC_PCMPGTW: 3907 gen_helper_pcmpgtw(t0, t0, t1); 3908 break; 3909 case OPC_PCMPEQH: 3910 gen_helper_pcmpeqh(t0, t0, t1); 3911 break; 3912 case OPC_PCMPGTH: 3913 gen_helper_pcmpgth(t0, t0, t1); 3914 break; 3915 case OPC_PCMPEQB: 3916 gen_helper_pcmpeqb(t0, t0, t1); 3917 break; 3918 case OPC_PCMPGTB: 3919 gen_helper_pcmpgtb(t0, t0, t1); 3920 break; 3921 3922 case OPC_PSLLW: 3923 gen_helper_psllw(t0, t0, t1); 3924 break; 3925 case OPC_PSLLH: 3926 gen_helper_psllh(t0, t0, t1); 3927 break; 3928 case OPC_PSRLW: 3929 gen_helper_psrlw(t0, t0, t1); 3930 break; 3931 case OPC_PSRLH: 3932 gen_helper_psrlh(t0, t0, t1); 3933 break; 3934 case OPC_PSRAW: 3935 gen_helper_psraw(t0, t0, t1); 3936 break; 3937 case OPC_PSRAH: 3938 gen_helper_psrah(t0, t0, t1); 3939 break; 3940 3941 case OPC_PMULLH: 3942 gen_helper_pmullh(t0, t0, t1); 3943 break; 3944 case OPC_PMULHH: 3945 gen_helper_pmulhh(t0, t0, t1); 3946 break; 3947 case OPC_PMULHUH: 3948 gen_helper_pmulhuh(t0, t0, t1); 3949 break; 3950 case OPC_PMADDHW: 3951 gen_helper_pmaddhw(t0, t0, t1); 3952 break; 3953 3954 case OPC_PASUBUB: 3955 gen_helper_pasubub(t0, t0, t1); 3956 break; 3957 case OPC_BIADD: 3958 gen_helper_biadd(t0, t0); 3959 break; 3960 case OPC_PMOVMSKB: 3961 gen_helper_pmovmskb(t0, t0); 3962 break; 3963 3964 case OPC_PADDD: 3965 tcg_gen_add_i64(t0, t0, t1); 3966 break; 3967 case OPC_PSUBD: 3968 tcg_gen_sub_i64(t0, t0, t1); 3969 break; 3970 case OPC_XOR_CP2: 3971 tcg_gen_xor_i64(t0, t0, t1); 3972 break; 3973 case OPC_NOR_CP2: 3974 tcg_gen_nor_i64(t0, t0, t1); 3975 break; 3976 case OPC_AND_CP2: 3977 tcg_gen_and_i64(t0, t0, t1); 3978 break; 3979 case OPC_OR_CP2: 3980 tcg_gen_or_i64(t0, t0, t1); 3981 break; 3982 3983 case OPC_PANDN: 3984 tcg_gen_andc_i64(t0, t1, t0); 3985 break; 3986 3987 case OPC_PINSRH_0: 3988 tcg_gen_deposit_i64(t0, t0, t1, 0, 16); 3989 break; 3990 case OPC_PINSRH_1: 3991 tcg_gen_deposit_i64(t0, t0, t1, 16, 16); 3992 break; 3993 case OPC_PINSRH_2: 3994 tcg_gen_deposit_i64(t0, t0, t1, 32, 16); 3995 break; 3996 case OPC_PINSRH_3: 3997 tcg_gen_deposit_i64(t0, t0, t1, 48, 16); 3998 break; 3999 4000 case OPC_PEXTRH: 4001 tcg_gen_andi_i64(t1, t1, 3); 4002 tcg_gen_shli_i64(t1, t1, 4); 4003 tcg_gen_shr_i64(t0, t0, t1); 4004 tcg_gen_ext16u_i64(t0, t0); 4005 break; 4006 4007 case OPC_ADDU_CP2: 4008 tcg_gen_add_i64(t0, t0, t1); 4009 tcg_gen_ext32s_i64(t0, t0); 4010 break; 4011 case OPC_SUBU_CP2: 4012 tcg_gen_sub_i64(t0, t0, t1); 4013 tcg_gen_ext32s_i64(t0, t0); 4014 break; 4015 4016 case OPC_SLL_CP2: 4017 shift_max = 32; 4018 goto do_shift; 4019 case OPC_SRL_CP2: 4020 shift_max = 32; 4021 goto do_shift; 4022 case OPC_SRA_CP2: 4023 shift_max = 32; 4024 goto do_shift; 4025 case OPC_DSLL_CP2: 4026 shift_max = 64; 4027 goto do_shift; 4028 case OPC_DSRL_CP2: 4029 shift_max = 64; 4030 goto do_shift; 4031 case OPC_DSRA_CP2: 4032 shift_max = 64; 4033 goto do_shift; 4034 do_shift: 4035 /* Make sure shift count isn't TCG undefined behaviour. */ 4036 tcg_gen_andi_i64(t1, t1, shift_max - 1); 4037 4038 switch (opc) { 4039 case OPC_SLL_CP2: 4040 case OPC_DSLL_CP2: 4041 tcg_gen_shl_i64(t0, t0, t1); 4042 break; 4043 case OPC_SRA_CP2: 4044 case OPC_DSRA_CP2: 4045 /* 4046 * Since SRA is UndefinedResult without sign-extended inputs, 4047 * we can treat SRA and DSRA the same. 4048 */ 4049 tcg_gen_sar_i64(t0, t0, t1); 4050 break; 4051 case OPC_SRL_CP2: 4052 /* We want to shift in zeros for SRL; zero-extend first. */ 4053 tcg_gen_ext32u_i64(t0, t0); 4054 /* FALLTHRU */ 4055 case OPC_DSRL_CP2: 4056 tcg_gen_shr_i64(t0, t0, t1); 4057 break; 4058 } 4059 4060 if (shift_max == 32) { 4061 tcg_gen_ext32s_i64(t0, t0); 4062 } 4063 4064 /* Shifts larger than MAX produce zero. */ 4065 tcg_gen_setcondi_i64(TCG_COND_LTU, t1, t1, shift_max); 4066 tcg_gen_neg_i64(t1, t1); 4067 tcg_gen_and_i64(t0, t0, t1); 4068 break; 4069 4070 case OPC_ADD_CP2: 4071 case OPC_DADD_CP2: 4072 { 4073 TCGv_i64 t2 = tcg_temp_new_i64(); 4074 TCGLabel *lab = gen_new_label(); 4075 4076 tcg_gen_mov_i64(t2, t0); 4077 tcg_gen_add_i64(t0, t1, t2); 4078 if (opc == OPC_ADD_CP2) { 4079 tcg_gen_ext32s_i64(t0, t0); 4080 } 4081 tcg_gen_xor_i64(t1, t1, t2); 4082 tcg_gen_xor_i64(t2, t2, t0); 4083 tcg_gen_andc_i64(t1, t2, t1); 4084 tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab); 4085 generate_exception(ctx, EXCP_OVERFLOW); 4086 gen_set_label(lab); 4087 break; 4088 } 4089 4090 case OPC_SUB_CP2: 4091 case OPC_DSUB_CP2: 4092 { 4093 TCGv_i64 t2 = tcg_temp_new_i64(); 4094 TCGLabel *lab = gen_new_label(); 4095 4096 tcg_gen_mov_i64(t2, t0); 4097 tcg_gen_sub_i64(t0, t1, t2); 4098 if (opc == OPC_SUB_CP2) { 4099 tcg_gen_ext32s_i64(t0, t0); 4100 } 4101 tcg_gen_xor_i64(t1, t1, t2); 4102 tcg_gen_xor_i64(t2, t2, t0); 4103 tcg_gen_and_i64(t1, t1, t2); 4104 tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab); 4105 generate_exception(ctx, EXCP_OVERFLOW); 4106 gen_set_label(lab); 4107 break; 4108 } 4109 4110 case OPC_PMULUW: 4111 tcg_gen_ext32u_i64(t0, t0); 4112 tcg_gen_ext32u_i64(t1, t1); 4113 tcg_gen_mul_i64(t0, t0, t1); 4114 break; 4115 4116 case OPC_SEQU_CP2: 4117 case OPC_SEQ_CP2: 4118 cond = TCG_COND_EQ; 4119 goto do_cc_cond; 4120 break; 4121 case OPC_SLTU_CP2: 4122 cond = TCG_COND_LTU; 4123 goto do_cc_cond; 4124 break; 4125 case OPC_SLT_CP2: 4126 cond = TCG_COND_LT; 4127 goto do_cc_cond; 4128 break; 4129 case OPC_SLEU_CP2: 4130 cond = TCG_COND_LEU; 4131 goto do_cc_cond; 4132 break; 4133 case OPC_SLE_CP2: 4134 cond = TCG_COND_LE; 4135 do_cc_cond: 4136 { 4137 int cc = (ctx->opcode >> 8) & 0x7; 4138 TCGv_i64 t64 = tcg_temp_new_i64(); 4139 TCGv_i32 t32 = tcg_temp_new_i32(); 4140 4141 tcg_gen_setcond_i64(cond, t64, t0, t1); 4142 tcg_gen_extrl_i64_i32(t32, t64); 4143 tcg_gen_deposit_i32(fpu_fcr31, fpu_fcr31, t32, 4144 get_fp_bit(cc), 1); 4145 } 4146 return; 4147 default: 4148 MIPS_INVAL("loongson_cp2"); 4149 gen_reserved_instruction(ctx); 4150 return; 4151 } 4152 4153 gen_store_fpr64(ctx, t0, rd); 4154 } 4155 4156 static void gen_loongson_lswc2(DisasContext *ctx, int rt, 4157 int rs, int rd) 4158 { 4159 TCGv t0, t1, t2; 4160 TCGv_i32 fp0; 4161 #if defined(TARGET_MIPS64) 4162 int lsq_rt1 = ctx->opcode & 0x1f; 4163 int lsq_offset = sextract32(ctx->opcode, 6, 9) << 4; 4164 #endif 4165 int shf_offset = sextract32(ctx->opcode, 6, 8); 4166 4167 t0 = tcg_temp_new(); 4168 4169 switch (MASK_LOONGSON_GSLSQ(ctx->opcode)) { 4170 #if defined(TARGET_MIPS64) 4171 case OPC_GSLQ: 4172 t1 = tcg_temp_new(); 4173 gen_base_offset_addr(ctx, t0, rs, lsq_offset); 4174 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4175 ctx->default_tcg_memop_mask); 4176 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); 4177 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ | 4178 ctx->default_tcg_memop_mask); 4179 gen_store_gpr(t1, rt); 4180 gen_store_gpr(t0, lsq_rt1); 4181 break; 4182 case OPC_GSLQC1: 4183 check_cp1_enabled(ctx); 4184 t1 = tcg_temp_new(); 4185 gen_base_offset_addr(ctx, t0, rs, lsq_offset); 4186 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4187 ctx->default_tcg_memop_mask); 4188 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); 4189 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ | 4190 ctx->default_tcg_memop_mask); 4191 gen_store_fpr64(ctx, t1, rt); 4192 gen_store_fpr64(ctx, t0, lsq_rt1); 4193 break; 4194 case OPC_GSSQ: 4195 t1 = tcg_temp_new(); 4196 gen_base_offset_addr(ctx, t0, rs, lsq_offset); 4197 gen_load_gpr(t1, rt); 4198 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4199 ctx->default_tcg_memop_mask); 4200 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); 4201 gen_load_gpr(t1, lsq_rt1); 4202 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4203 ctx->default_tcg_memop_mask); 4204 break; 4205 case OPC_GSSQC1: 4206 check_cp1_enabled(ctx); 4207 t1 = tcg_temp_new(); 4208 gen_base_offset_addr(ctx, t0, rs, lsq_offset); 4209 gen_load_fpr64(ctx, t1, rt); 4210 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4211 ctx->default_tcg_memop_mask); 4212 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); 4213 gen_load_fpr64(ctx, t1, lsq_rt1); 4214 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4215 ctx->default_tcg_memop_mask); 4216 break; 4217 #endif 4218 case OPC_GSSHFL: 4219 switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) { 4220 case OPC_GSLWLC1: 4221 check_cp1_enabled(ctx); 4222 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4223 t1 = tcg_temp_new(); 4224 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); 4225 tcg_gen_andi_tl(t1, t0, 3); 4226 if (!cpu_is_bigendian(ctx)) { 4227 tcg_gen_xori_tl(t1, t1, 3); 4228 } 4229 tcg_gen_shli_tl(t1, t1, 3); 4230 tcg_gen_andi_tl(t0, t0, ~3); 4231 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL); 4232 tcg_gen_shl_tl(t0, t0, t1); 4233 t2 = tcg_const_tl(-1); 4234 tcg_gen_shl_tl(t2, t2, t1); 4235 fp0 = tcg_temp_new_i32(); 4236 gen_load_fpr32(ctx, fp0, rt); 4237 tcg_gen_ext_i32_tl(t1, fp0); 4238 tcg_gen_andc_tl(t1, t1, t2); 4239 tcg_gen_or_tl(t0, t0, t1); 4240 #if defined(TARGET_MIPS64) 4241 tcg_gen_extrl_i64_i32(fp0, t0); 4242 #else 4243 tcg_gen_ext32s_tl(fp0, t0); 4244 #endif 4245 gen_store_fpr32(ctx, fp0, rt); 4246 break; 4247 case OPC_GSLWRC1: 4248 check_cp1_enabled(ctx); 4249 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4250 t1 = tcg_temp_new(); 4251 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); 4252 tcg_gen_andi_tl(t1, t0, 3); 4253 if (cpu_is_bigendian(ctx)) { 4254 tcg_gen_xori_tl(t1, t1, 3); 4255 } 4256 tcg_gen_shli_tl(t1, t1, 3); 4257 tcg_gen_andi_tl(t0, t0, ~3); 4258 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL); 4259 tcg_gen_shr_tl(t0, t0, t1); 4260 tcg_gen_xori_tl(t1, t1, 31); 4261 t2 = tcg_const_tl(0xfffffffeull); 4262 tcg_gen_shl_tl(t2, t2, t1); 4263 fp0 = tcg_temp_new_i32(); 4264 gen_load_fpr32(ctx, fp0, rt); 4265 tcg_gen_ext_i32_tl(t1, fp0); 4266 tcg_gen_and_tl(t1, t1, t2); 4267 tcg_gen_or_tl(t0, t0, t1); 4268 #if defined(TARGET_MIPS64) 4269 tcg_gen_extrl_i64_i32(fp0, t0); 4270 #else 4271 tcg_gen_ext32s_tl(fp0, t0); 4272 #endif 4273 gen_store_fpr32(ctx, fp0, rt); 4274 break; 4275 #if defined(TARGET_MIPS64) 4276 case OPC_GSLDLC1: 4277 check_cp1_enabled(ctx); 4278 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4279 t1 = tcg_temp_new(); 4280 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); 4281 tcg_gen_andi_tl(t1, t0, 7); 4282 if (!cpu_is_bigendian(ctx)) { 4283 tcg_gen_xori_tl(t1, t1, 7); 4284 } 4285 tcg_gen_shli_tl(t1, t1, 3); 4286 tcg_gen_andi_tl(t0, t0, ~7); 4287 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ); 4288 tcg_gen_shl_tl(t0, t0, t1); 4289 t2 = tcg_const_tl(-1); 4290 tcg_gen_shl_tl(t2, t2, t1); 4291 gen_load_fpr64(ctx, t1, rt); 4292 tcg_gen_andc_tl(t1, t1, t2); 4293 tcg_gen_or_tl(t0, t0, t1); 4294 gen_store_fpr64(ctx, t0, rt); 4295 break; 4296 case OPC_GSLDRC1: 4297 check_cp1_enabled(ctx); 4298 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4299 t1 = tcg_temp_new(); 4300 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); 4301 tcg_gen_andi_tl(t1, t0, 7); 4302 if (cpu_is_bigendian(ctx)) { 4303 tcg_gen_xori_tl(t1, t1, 7); 4304 } 4305 tcg_gen_shli_tl(t1, t1, 3); 4306 tcg_gen_andi_tl(t0, t0, ~7); 4307 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ); 4308 tcg_gen_shr_tl(t0, t0, t1); 4309 tcg_gen_xori_tl(t1, t1, 63); 4310 t2 = tcg_const_tl(0xfffffffffffffffeull); 4311 tcg_gen_shl_tl(t2, t2, t1); 4312 gen_load_fpr64(ctx, t1, rt); 4313 tcg_gen_and_tl(t1, t1, t2); 4314 tcg_gen_or_tl(t0, t0, t1); 4315 gen_store_fpr64(ctx, t0, rt); 4316 break; 4317 #endif 4318 default: 4319 MIPS_INVAL("loongson_gsshfl"); 4320 gen_reserved_instruction(ctx); 4321 break; 4322 } 4323 break; 4324 case OPC_GSSHFS: 4325 switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) { 4326 case OPC_GSSWLC1: 4327 check_cp1_enabled(ctx); 4328 t1 = tcg_temp_new(); 4329 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4330 fp0 = tcg_temp_new_i32(); 4331 gen_load_fpr32(ctx, fp0, rt); 4332 tcg_gen_ext_i32_tl(t1, fp0); 4333 gen_helper_0e2i(swl, t1, t0, ctx->mem_idx); 4334 break; 4335 case OPC_GSSWRC1: 4336 check_cp1_enabled(ctx); 4337 t1 = tcg_temp_new(); 4338 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4339 fp0 = tcg_temp_new_i32(); 4340 gen_load_fpr32(ctx, fp0, rt); 4341 tcg_gen_ext_i32_tl(t1, fp0); 4342 gen_helper_0e2i(swr, t1, t0, ctx->mem_idx); 4343 break; 4344 #if defined(TARGET_MIPS64) 4345 case OPC_GSSDLC1: 4346 check_cp1_enabled(ctx); 4347 t1 = tcg_temp_new(); 4348 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4349 gen_load_fpr64(ctx, t1, rt); 4350 gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx); 4351 break; 4352 case OPC_GSSDRC1: 4353 check_cp1_enabled(ctx); 4354 t1 = tcg_temp_new(); 4355 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4356 gen_load_fpr64(ctx, t1, rt); 4357 gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx); 4358 break; 4359 #endif 4360 default: 4361 MIPS_INVAL("loongson_gsshfs"); 4362 gen_reserved_instruction(ctx); 4363 break; 4364 } 4365 break; 4366 default: 4367 MIPS_INVAL("loongson_gslsq"); 4368 gen_reserved_instruction(ctx); 4369 break; 4370 } 4371 } 4372 4373 /* Loongson EXT LDC2/SDC2 */ 4374 static void gen_loongson_lsdc2(DisasContext *ctx, int rt, 4375 int rs, int rd) 4376 { 4377 int offset = sextract32(ctx->opcode, 3, 8); 4378 uint32_t opc = MASK_LOONGSON_LSDC2(ctx->opcode); 4379 TCGv t0, t1; 4380 TCGv_i32 fp0; 4381 4382 /* Pre-conditions */ 4383 switch (opc) { 4384 case OPC_GSLBX: 4385 case OPC_GSLHX: 4386 case OPC_GSLWX: 4387 case OPC_GSLDX: 4388 /* prefetch, implement as NOP */ 4389 if (rt == 0) { 4390 return; 4391 } 4392 break; 4393 case OPC_GSSBX: 4394 case OPC_GSSHX: 4395 case OPC_GSSWX: 4396 case OPC_GSSDX: 4397 break; 4398 case OPC_GSLWXC1: 4399 #if defined(TARGET_MIPS64) 4400 case OPC_GSLDXC1: 4401 #endif 4402 check_cp1_enabled(ctx); 4403 /* prefetch, implement as NOP */ 4404 if (rt == 0) { 4405 return; 4406 } 4407 break; 4408 case OPC_GSSWXC1: 4409 #if defined(TARGET_MIPS64) 4410 case OPC_GSSDXC1: 4411 #endif 4412 check_cp1_enabled(ctx); 4413 break; 4414 default: 4415 MIPS_INVAL("loongson_lsdc2"); 4416 gen_reserved_instruction(ctx); 4417 return; 4418 break; 4419 } 4420 4421 t0 = tcg_temp_new(); 4422 4423 gen_base_offset_addr(ctx, t0, rs, offset); 4424 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); 4425 4426 switch (opc) { 4427 case OPC_GSLBX: 4428 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB); 4429 gen_store_gpr(t0, rt); 4430 break; 4431 case OPC_GSLHX: 4432 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW | 4433 ctx->default_tcg_memop_mask); 4434 gen_store_gpr(t0, rt); 4435 break; 4436 case OPC_GSLWX: 4437 gen_base_offset_addr(ctx, t0, rs, offset); 4438 if (rd) { 4439 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); 4440 } 4441 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL | 4442 ctx->default_tcg_memop_mask); 4443 gen_store_gpr(t0, rt); 4444 break; 4445 #if defined(TARGET_MIPS64) 4446 case OPC_GSLDX: 4447 gen_base_offset_addr(ctx, t0, rs, offset); 4448 if (rd) { 4449 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); 4450 } 4451 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ | 4452 ctx->default_tcg_memop_mask); 4453 gen_store_gpr(t0, rt); 4454 break; 4455 #endif 4456 case OPC_GSLWXC1: 4457 gen_base_offset_addr(ctx, t0, rs, offset); 4458 if (rd) { 4459 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); 4460 } 4461 fp0 = tcg_temp_new_i32(); 4462 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL | 4463 ctx->default_tcg_memop_mask); 4464 gen_store_fpr32(ctx, fp0, rt); 4465 break; 4466 #if defined(TARGET_MIPS64) 4467 case OPC_GSLDXC1: 4468 gen_base_offset_addr(ctx, t0, rs, offset); 4469 if (rd) { 4470 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); 4471 } 4472 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ | 4473 ctx->default_tcg_memop_mask); 4474 gen_store_fpr64(ctx, t0, rt); 4475 break; 4476 #endif 4477 case OPC_GSSBX: 4478 t1 = tcg_temp_new(); 4479 gen_load_gpr(t1, rt); 4480 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_SB); 4481 break; 4482 case OPC_GSSHX: 4483 t1 = tcg_temp_new(); 4484 gen_load_gpr(t1, rt); 4485 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW | 4486 ctx->default_tcg_memop_mask); 4487 break; 4488 case OPC_GSSWX: 4489 t1 = tcg_temp_new(); 4490 gen_load_gpr(t1, rt); 4491 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | 4492 ctx->default_tcg_memop_mask); 4493 break; 4494 #if defined(TARGET_MIPS64) 4495 case OPC_GSSDX: 4496 t1 = tcg_temp_new(); 4497 gen_load_gpr(t1, rt); 4498 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4499 ctx->default_tcg_memop_mask); 4500 break; 4501 #endif 4502 case OPC_GSSWXC1: 4503 fp0 = tcg_temp_new_i32(); 4504 gen_load_fpr32(ctx, fp0, rt); 4505 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL | 4506 ctx->default_tcg_memop_mask); 4507 break; 4508 #if defined(TARGET_MIPS64) 4509 case OPC_GSSDXC1: 4510 t1 = tcg_temp_new(); 4511 gen_load_fpr64(ctx, t1, rt); 4512 tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TEUQ | 4513 ctx->default_tcg_memop_mask); 4514 break; 4515 #endif 4516 default: 4517 break; 4518 } 4519 } 4520 4521 /* Traps */ 4522 static void gen_trap(DisasContext *ctx, uint32_t opc, 4523 int rs, int rt, int16_t imm, int code) 4524 { 4525 int cond; 4526 TCGv t0 = tcg_temp_new(); 4527 TCGv t1 = tcg_temp_new(); 4528 4529 cond = 0; 4530 /* Load needed operands */ 4531 switch (opc) { 4532 case OPC_TEQ: 4533 case OPC_TGE: 4534 case OPC_TGEU: 4535 case OPC_TLT: 4536 case OPC_TLTU: 4537 case OPC_TNE: 4538 /* Compare two registers */ 4539 if (rs != rt) { 4540 gen_load_gpr(t0, rs); 4541 gen_load_gpr(t1, rt); 4542 cond = 1; 4543 } 4544 break; 4545 case OPC_TEQI: 4546 case OPC_TGEI: 4547 case OPC_TGEIU: 4548 case OPC_TLTI: 4549 case OPC_TLTIU: 4550 case OPC_TNEI: 4551 /* Compare register to immediate */ 4552 if (rs != 0 || imm != 0) { 4553 gen_load_gpr(t0, rs); 4554 tcg_gen_movi_tl(t1, (int32_t)imm); 4555 cond = 1; 4556 } 4557 break; 4558 } 4559 if (cond == 0) { 4560 switch (opc) { 4561 case OPC_TEQ: /* rs == rs */ 4562 case OPC_TEQI: /* r0 == 0 */ 4563 case OPC_TGE: /* rs >= rs */ 4564 case OPC_TGEI: /* r0 >= 0 */ 4565 case OPC_TGEU: /* rs >= rs unsigned */ 4566 case OPC_TGEIU: /* r0 >= 0 unsigned */ 4567 /* Always trap */ 4568 #ifdef CONFIG_USER_ONLY 4569 /* Pass the break code along to cpu_loop. */ 4570 tcg_gen_st_i32(tcg_constant_i32(code), cpu_env, 4571 offsetof(CPUMIPSState, error_code)); 4572 #endif 4573 generate_exception_end(ctx, EXCP_TRAP); 4574 break; 4575 case OPC_TLT: /* rs < rs */ 4576 case OPC_TLTI: /* r0 < 0 */ 4577 case OPC_TLTU: /* rs < rs unsigned */ 4578 case OPC_TLTIU: /* r0 < 0 unsigned */ 4579 case OPC_TNE: /* rs != rs */ 4580 case OPC_TNEI: /* r0 != 0 */ 4581 /* Never trap: treat as NOP. */ 4582 break; 4583 } 4584 } else { 4585 TCGLabel *l1 = gen_new_label(); 4586 4587 switch (opc) { 4588 case OPC_TEQ: 4589 case OPC_TEQI: 4590 tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1); 4591 break; 4592 case OPC_TGE: 4593 case OPC_TGEI: 4594 tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1); 4595 break; 4596 case OPC_TGEU: 4597 case OPC_TGEIU: 4598 tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1); 4599 break; 4600 case OPC_TLT: 4601 case OPC_TLTI: 4602 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 4603 break; 4604 case OPC_TLTU: 4605 case OPC_TLTIU: 4606 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 4607 break; 4608 case OPC_TNE: 4609 case OPC_TNEI: 4610 tcg_gen_brcond_tl(TCG_COND_EQ, t0, t1, l1); 4611 break; 4612 } 4613 #ifdef CONFIG_USER_ONLY 4614 /* Pass the break code along to cpu_loop. */ 4615 tcg_gen_st_i32(tcg_constant_i32(code), cpu_env, 4616 offsetof(CPUMIPSState, error_code)); 4617 #endif 4618 /* Like save_cpu_state, only don't update saved values. */ 4619 if (ctx->base.pc_next != ctx->saved_pc) { 4620 gen_save_pc(ctx->base.pc_next); 4621 } 4622 if (ctx->hflags != ctx->saved_hflags) { 4623 tcg_gen_movi_i32(hflags, ctx->hflags); 4624 } 4625 generate_exception(ctx, EXCP_TRAP); 4626 gen_set_label(l1); 4627 } 4628 } 4629 4630 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4631 { 4632 if (translator_use_goto_tb(&ctx->base, dest)) { 4633 tcg_gen_goto_tb(n); 4634 gen_save_pc(dest); 4635 tcg_gen_exit_tb(ctx->base.tb, n); 4636 } else { 4637 gen_save_pc(dest); 4638 tcg_gen_lookup_and_goto_ptr(); 4639 } 4640 } 4641 4642 /* Branches (before delay slot) */ 4643 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, 4644 int insn_bytes, 4645 int rs, int rt, int32_t offset, 4646 int delayslot_size) 4647 { 4648 target_ulong btgt = -1; 4649 int blink = 0; 4650 int bcond_compute = 0; 4651 TCGv t0 = tcg_temp_new(); 4652 TCGv t1 = tcg_temp_new(); 4653 4654 if (ctx->hflags & MIPS_HFLAG_BMASK) { 4655 #ifdef MIPS_DEBUG_DISAS 4656 LOG_DISAS("Branch in delay / forbidden slot at PC 0x" 4657 TARGET_FMT_lx "\n", ctx->base.pc_next); 4658 #endif 4659 gen_reserved_instruction(ctx); 4660 goto out; 4661 } 4662 4663 /* Load needed operands */ 4664 switch (opc) { 4665 case OPC_BEQ: 4666 case OPC_BEQL: 4667 case OPC_BNE: 4668 case OPC_BNEL: 4669 /* Compare two registers */ 4670 if (rs != rt) { 4671 gen_load_gpr(t0, rs); 4672 gen_load_gpr(t1, rt); 4673 bcond_compute = 1; 4674 } 4675 btgt = ctx->base.pc_next + insn_bytes + offset; 4676 break; 4677 case OPC_BGEZ: 4678 case OPC_BGEZAL: 4679 case OPC_BGEZALL: 4680 case OPC_BGEZL: 4681 case OPC_BGTZ: 4682 case OPC_BGTZL: 4683 case OPC_BLEZ: 4684 case OPC_BLEZL: 4685 case OPC_BLTZ: 4686 case OPC_BLTZAL: 4687 case OPC_BLTZALL: 4688 case OPC_BLTZL: 4689 /* Compare to zero */ 4690 if (rs != 0) { 4691 gen_load_gpr(t0, rs); 4692 bcond_compute = 1; 4693 } 4694 btgt = ctx->base.pc_next + insn_bytes + offset; 4695 break; 4696 case OPC_BPOSGE32: 4697 #if defined(TARGET_MIPS64) 4698 case OPC_BPOSGE64: 4699 tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F); 4700 #else 4701 tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F); 4702 #endif 4703 bcond_compute = 1; 4704 btgt = ctx->base.pc_next + insn_bytes + offset; 4705 break; 4706 case OPC_J: 4707 case OPC_JAL: 4708 { 4709 /* Jump to immediate */ 4710 int jal_mask = ctx->hflags & MIPS_HFLAG_M16 ? 0xF8000000 4711 : 0xF0000000; 4712 btgt = ((ctx->base.pc_next + insn_bytes) & jal_mask) 4713 | (uint32_t)offset; 4714 break; 4715 } 4716 case OPC_JALX: 4717 /* Jump to immediate */ 4718 btgt = ((ctx->base.pc_next + insn_bytes) & (int32_t)0xF0000000) | 4719 (uint32_t)offset; 4720 break; 4721 case OPC_JR: 4722 case OPC_JALR: 4723 /* Jump to register */ 4724 if (offset != 0 && offset != 16) { 4725 /* 4726 * Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the 4727 * others are reserved. 4728 */ 4729 MIPS_INVAL("jump hint"); 4730 gen_reserved_instruction(ctx); 4731 goto out; 4732 } 4733 gen_load_gpr(btarget, rs); 4734 break; 4735 default: 4736 MIPS_INVAL("branch/jump"); 4737 gen_reserved_instruction(ctx); 4738 goto out; 4739 } 4740 if (bcond_compute == 0) { 4741 /* No condition to be computed */ 4742 switch (opc) { 4743 case OPC_BEQ: /* rx == rx */ 4744 case OPC_BEQL: /* rx == rx likely */ 4745 case OPC_BGEZ: /* 0 >= 0 */ 4746 case OPC_BGEZL: /* 0 >= 0 likely */ 4747 case OPC_BLEZ: /* 0 <= 0 */ 4748 case OPC_BLEZL: /* 0 <= 0 likely */ 4749 /* Always take */ 4750 ctx->hflags |= MIPS_HFLAG_B; 4751 break; 4752 case OPC_BGEZAL: /* 0 >= 0 */ 4753 case OPC_BGEZALL: /* 0 >= 0 likely */ 4754 /* Always take and link */ 4755 blink = 31; 4756 ctx->hflags |= MIPS_HFLAG_B; 4757 break; 4758 case OPC_BNE: /* rx != rx */ 4759 case OPC_BGTZ: /* 0 > 0 */ 4760 case OPC_BLTZ: /* 0 < 0 */ 4761 /* Treat as NOP. */ 4762 goto out; 4763 case OPC_BLTZAL: /* 0 < 0 */ 4764 /* 4765 * Handle as an unconditional branch to get correct delay 4766 * slot checking. 4767 */ 4768 blink = 31; 4769 btgt = ctx->base.pc_next + insn_bytes + delayslot_size; 4770 ctx->hflags |= MIPS_HFLAG_B; 4771 break; 4772 case OPC_BLTZALL: /* 0 < 0 likely */ 4773 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 8); 4774 /* Skip the instruction in the delay slot */ 4775 ctx->base.pc_next += 4; 4776 goto out; 4777 case OPC_BNEL: /* rx != rx likely */ 4778 case OPC_BGTZL: /* 0 > 0 likely */ 4779 case OPC_BLTZL: /* 0 < 0 likely */ 4780 /* Skip the instruction in the delay slot */ 4781 ctx->base.pc_next += 4; 4782 goto out; 4783 case OPC_J: 4784 ctx->hflags |= MIPS_HFLAG_B; 4785 break; 4786 case OPC_JALX: 4787 ctx->hflags |= MIPS_HFLAG_BX; 4788 /* Fallthrough */ 4789 case OPC_JAL: 4790 blink = 31; 4791 ctx->hflags |= MIPS_HFLAG_B; 4792 break; 4793 case OPC_JR: 4794 ctx->hflags |= MIPS_HFLAG_BR; 4795 break; 4796 case OPC_JALR: 4797 blink = rt; 4798 ctx->hflags |= MIPS_HFLAG_BR; 4799 break; 4800 default: 4801 MIPS_INVAL("branch/jump"); 4802 gen_reserved_instruction(ctx); 4803 goto out; 4804 } 4805 } else { 4806 switch (opc) { 4807 case OPC_BEQ: 4808 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1); 4809 goto not_likely; 4810 case OPC_BEQL: 4811 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1); 4812 goto likely; 4813 case OPC_BNE: 4814 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1); 4815 goto not_likely; 4816 case OPC_BNEL: 4817 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1); 4818 goto likely; 4819 case OPC_BGEZ: 4820 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); 4821 goto not_likely; 4822 case OPC_BGEZL: 4823 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); 4824 goto likely; 4825 case OPC_BGEZAL: 4826 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); 4827 blink = 31; 4828 goto not_likely; 4829 case OPC_BGEZALL: 4830 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); 4831 blink = 31; 4832 goto likely; 4833 case OPC_BGTZ: 4834 tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0); 4835 goto not_likely; 4836 case OPC_BGTZL: 4837 tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0); 4838 goto likely; 4839 case OPC_BLEZ: 4840 tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0); 4841 goto not_likely; 4842 case OPC_BLEZL: 4843 tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0); 4844 goto likely; 4845 case OPC_BLTZ: 4846 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); 4847 goto not_likely; 4848 case OPC_BLTZL: 4849 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); 4850 goto likely; 4851 case OPC_BPOSGE32: 4852 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32); 4853 goto not_likely; 4854 #if defined(TARGET_MIPS64) 4855 case OPC_BPOSGE64: 4856 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 64); 4857 goto not_likely; 4858 #endif 4859 case OPC_BLTZAL: 4860 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); 4861 blink = 31; 4862 not_likely: 4863 ctx->hflags |= MIPS_HFLAG_BC; 4864 break; 4865 case OPC_BLTZALL: 4866 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); 4867 blink = 31; 4868 likely: 4869 ctx->hflags |= MIPS_HFLAG_BL; 4870 break; 4871 default: 4872 MIPS_INVAL("conditional branch/jump"); 4873 gen_reserved_instruction(ctx); 4874 goto out; 4875 } 4876 } 4877 4878 ctx->btarget = btgt; 4879 4880 switch (delayslot_size) { 4881 case 2: 4882 ctx->hflags |= MIPS_HFLAG_BDS16; 4883 break; 4884 case 4: 4885 ctx->hflags |= MIPS_HFLAG_BDS32; 4886 break; 4887 } 4888 4889 if (blink > 0) { 4890 int post_delay = insn_bytes + delayslot_size; 4891 int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16); 4892 4893 tcg_gen_movi_tl(cpu_gpr[blink], 4894 ctx->base.pc_next + post_delay + lowbit); 4895 } 4896 4897 out: 4898 if (insn_bytes == 2) { 4899 ctx->hflags |= MIPS_HFLAG_B16; 4900 } 4901 } 4902 4903 4904 /* special3 bitfield operations */ 4905 static void gen_bitops(DisasContext *ctx, uint32_t opc, int rt, 4906 int rs, int lsb, int msb) 4907 { 4908 TCGv t0 = tcg_temp_new(); 4909 TCGv t1 = tcg_temp_new(); 4910 4911 gen_load_gpr(t1, rs); 4912 switch (opc) { 4913 case OPC_EXT: 4914 if (lsb + msb > 31) { 4915 goto fail; 4916 } 4917 if (msb != 31) { 4918 tcg_gen_extract_tl(t0, t1, lsb, msb + 1); 4919 } else { 4920 /* 4921 * The two checks together imply that lsb == 0, 4922 * so this is a simple sign-extension. 4923 */ 4924 tcg_gen_ext32s_tl(t0, t1); 4925 } 4926 break; 4927 #if defined(TARGET_MIPS64) 4928 case OPC_DEXTU: 4929 lsb += 32; 4930 goto do_dext; 4931 case OPC_DEXTM: 4932 msb += 32; 4933 goto do_dext; 4934 case OPC_DEXT: 4935 do_dext: 4936 if (lsb + msb > 63) { 4937 goto fail; 4938 } 4939 tcg_gen_extract_tl(t0, t1, lsb, msb + 1); 4940 break; 4941 #endif 4942 case OPC_INS: 4943 if (lsb > msb) { 4944 goto fail; 4945 } 4946 gen_load_gpr(t0, rt); 4947 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); 4948 tcg_gen_ext32s_tl(t0, t0); 4949 break; 4950 #if defined(TARGET_MIPS64) 4951 case OPC_DINSU: 4952 lsb += 32; 4953 /* FALLTHRU */ 4954 case OPC_DINSM: 4955 msb += 32; 4956 /* FALLTHRU */ 4957 case OPC_DINS: 4958 if (lsb > msb) { 4959 goto fail; 4960 } 4961 gen_load_gpr(t0, rt); 4962 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); 4963 break; 4964 #endif 4965 default: 4966 fail: 4967 MIPS_INVAL("bitops"); 4968 gen_reserved_instruction(ctx); 4969 return; 4970 } 4971 gen_store_gpr(t0, rt); 4972 } 4973 4974 static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd) 4975 { 4976 TCGv t0; 4977 4978 if (rd == 0) { 4979 /* If no destination, treat it as a NOP. */ 4980 return; 4981 } 4982 4983 t0 = tcg_temp_new(); 4984 gen_load_gpr(t0, rt); 4985 switch (op2) { 4986 case OPC_WSBH: 4987 { 4988 TCGv t1 = tcg_temp_new(); 4989 TCGv t2 = tcg_const_tl(0x00FF00FF); 4990 4991 tcg_gen_shri_tl(t1, t0, 8); 4992 tcg_gen_and_tl(t1, t1, t2); 4993 tcg_gen_and_tl(t0, t0, t2); 4994 tcg_gen_shli_tl(t0, t0, 8); 4995 tcg_gen_or_tl(t0, t0, t1); 4996 tcg_gen_ext32s_tl(cpu_gpr[rd], t0); 4997 } 4998 break; 4999 case OPC_SEB: 5000 tcg_gen_ext8s_tl(cpu_gpr[rd], t0); 5001 break; 5002 case OPC_SEH: 5003 tcg_gen_ext16s_tl(cpu_gpr[rd], t0); 5004 break; 5005 #if defined(TARGET_MIPS64) 5006 case OPC_DSBH: 5007 { 5008 TCGv t1 = tcg_temp_new(); 5009 TCGv t2 = tcg_const_tl(0x00FF00FF00FF00FFULL); 5010 5011 tcg_gen_shri_tl(t1, t0, 8); 5012 tcg_gen_and_tl(t1, t1, t2); 5013 tcg_gen_and_tl(t0, t0, t2); 5014 tcg_gen_shli_tl(t0, t0, 8); 5015 tcg_gen_or_tl(cpu_gpr[rd], t0, t1); 5016 } 5017 break; 5018 case OPC_DSHD: 5019 { 5020 TCGv t1 = tcg_temp_new(); 5021 TCGv t2 = tcg_const_tl(0x0000FFFF0000FFFFULL); 5022 5023 tcg_gen_shri_tl(t1, t0, 16); 5024 tcg_gen_and_tl(t1, t1, t2); 5025 tcg_gen_and_tl(t0, t0, t2); 5026 tcg_gen_shli_tl(t0, t0, 16); 5027 tcg_gen_or_tl(t0, t0, t1); 5028 tcg_gen_shri_tl(t1, t0, 32); 5029 tcg_gen_shli_tl(t0, t0, 32); 5030 tcg_gen_or_tl(cpu_gpr[rd], t0, t1); 5031 } 5032 break; 5033 #endif 5034 default: 5035 MIPS_INVAL("bsfhl"); 5036 gen_reserved_instruction(ctx); 5037 return; 5038 } 5039 } 5040 5041 static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs, 5042 int rt, int bits) 5043 { 5044 TCGv t0; 5045 if (rd == 0) { 5046 /* Treat as NOP. */ 5047 return; 5048 } 5049 t0 = tcg_temp_new(); 5050 if (bits == 0 || bits == wordsz) { 5051 if (bits == 0) { 5052 gen_load_gpr(t0, rt); 5053 } else { 5054 gen_load_gpr(t0, rs); 5055 } 5056 switch (wordsz) { 5057 case 32: 5058 tcg_gen_ext32s_tl(cpu_gpr[rd], t0); 5059 break; 5060 #if defined(TARGET_MIPS64) 5061 case 64: 5062 tcg_gen_mov_tl(cpu_gpr[rd], t0); 5063 break; 5064 #endif 5065 } 5066 } else { 5067 TCGv t1 = tcg_temp_new(); 5068 gen_load_gpr(t0, rt); 5069 gen_load_gpr(t1, rs); 5070 switch (wordsz) { 5071 case 32: 5072 { 5073 TCGv_i64 t2 = tcg_temp_new_i64(); 5074 tcg_gen_concat_tl_i64(t2, t1, t0); 5075 tcg_gen_shri_i64(t2, t2, 32 - bits); 5076 gen_move_low32(cpu_gpr[rd], t2); 5077 } 5078 break; 5079 #if defined(TARGET_MIPS64) 5080 case 64: 5081 tcg_gen_shli_tl(t0, t0, bits); 5082 tcg_gen_shri_tl(t1, t1, 64 - bits); 5083 tcg_gen_or_tl(cpu_gpr[rd], t1, t0); 5084 break; 5085 #endif 5086 } 5087 } 5088 } 5089 5090 void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int bp) 5091 { 5092 gen_align_bits(ctx, wordsz, rd, rs, rt, bp * 8); 5093 } 5094 5095 static void gen_bitswap(DisasContext *ctx, int opc, int rd, int rt) 5096 { 5097 TCGv t0; 5098 if (rd == 0) { 5099 /* Treat as NOP. */ 5100 return; 5101 } 5102 t0 = tcg_temp_new(); 5103 gen_load_gpr(t0, rt); 5104 switch (opc) { 5105 case OPC_BITSWAP: 5106 gen_helper_bitswap(cpu_gpr[rd], t0); 5107 break; 5108 #if defined(TARGET_MIPS64) 5109 case OPC_DBITSWAP: 5110 gen_helper_dbitswap(cpu_gpr[rd], t0); 5111 break; 5112 #endif 5113 } 5114 } 5115 5116 #ifndef CONFIG_USER_ONLY 5117 /* CP0 (MMU and control) */ 5118 static inline void gen_mthc0_entrylo(TCGv arg, target_ulong off) 5119 { 5120 TCGv_i64 t0 = tcg_temp_new_i64(); 5121 TCGv_i64 t1 = tcg_temp_new_i64(); 5122 5123 tcg_gen_ext_tl_i64(t0, arg); 5124 tcg_gen_ld_i64(t1, cpu_env, off); 5125 #if defined(TARGET_MIPS64) 5126 tcg_gen_deposit_i64(t1, t1, t0, 30, 32); 5127 #else 5128 tcg_gen_concat32_i64(t1, t1, t0); 5129 #endif 5130 tcg_gen_st_i64(t1, cpu_env, off); 5131 } 5132 5133 static inline void gen_mthc0_store64(TCGv arg, target_ulong off) 5134 { 5135 TCGv_i64 t0 = tcg_temp_new_i64(); 5136 TCGv_i64 t1 = tcg_temp_new_i64(); 5137 5138 tcg_gen_ext_tl_i64(t0, arg); 5139 tcg_gen_ld_i64(t1, cpu_env, off); 5140 tcg_gen_concat32_i64(t1, t1, t0); 5141 tcg_gen_st_i64(t1, cpu_env, off); 5142 } 5143 5144 static inline void gen_mfhc0_entrylo(TCGv arg, target_ulong off) 5145 { 5146 TCGv_i64 t0 = tcg_temp_new_i64(); 5147 5148 tcg_gen_ld_i64(t0, cpu_env, off); 5149 #if defined(TARGET_MIPS64) 5150 tcg_gen_shri_i64(t0, t0, 30); 5151 #else 5152 tcg_gen_shri_i64(t0, t0, 32); 5153 #endif 5154 gen_move_low32(arg, t0); 5155 } 5156 5157 static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift) 5158 { 5159 TCGv_i64 t0 = tcg_temp_new_i64(); 5160 5161 tcg_gen_ld_i64(t0, cpu_env, off); 5162 tcg_gen_shri_i64(t0, t0, 32 + shift); 5163 gen_move_low32(arg, t0); 5164 } 5165 5166 static inline void gen_mfc0_load32(TCGv arg, target_ulong off) 5167 { 5168 TCGv_i32 t0 = tcg_temp_new_i32(); 5169 5170 tcg_gen_ld_i32(t0, cpu_env, off); 5171 tcg_gen_ext_i32_tl(arg, t0); 5172 } 5173 5174 static inline void gen_mfc0_load64(TCGv arg, target_ulong off) 5175 { 5176 tcg_gen_ld_tl(arg, cpu_env, off); 5177 tcg_gen_ext32s_tl(arg, arg); 5178 } 5179 5180 static inline void gen_mtc0_store32(TCGv arg, target_ulong off) 5181 { 5182 TCGv_i32 t0 = tcg_temp_new_i32(); 5183 5184 tcg_gen_trunc_tl_i32(t0, arg); 5185 tcg_gen_st_i32(t0, cpu_env, off); 5186 } 5187 5188 #define CP0_CHECK(c) \ 5189 do { \ 5190 if (!(c)) { \ 5191 goto cp0_unimplemented; \ 5192 } \ 5193 } while (0) 5194 5195 static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel) 5196 { 5197 const char *register_name = "invalid"; 5198 5199 switch (reg) { 5200 case CP0_REGISTER_02: 5201 switch (sel) { 5202 case 0: 5203 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); 5204 gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0)); 5205 register_name = "EntryLo0"; 5206 break; 5207 default: 5208 goto cp0_unimplemented; 5209 } 5210 break; 5211 case CP0_REGISTER_03: 5212 switch (sel) { 5213 case CP0_REG03__ENTRYLO1: 5214 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); 5215 gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1)); 5216 register_name = "EntryLo1"; 5217 break; 5218 default: 5219 goto cp0_unimplemented; 5220 } 5221 break; 5222 case CP0_REGISTER_09: 5223 switch (sel) { 5224 case CP0_REG09__SAAR: 5225 CP0_CHECK(ctx->saar); 5226 gen_helper_mfhc0_saar(arg, cpu_env); 5227 register_name = "SAAR"; 5228 break; 5229 default: 5230 goto cp0_unimplemented; 5231 } 5232 break; 5233 case CP0_REGISTER_17: 5234 switch (sel) { 5235 case CP0_REG17__LLADDR: 5236 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_LLAddr), 5237 ctx->CP0_LLAddr_shift); 5238 register_name = "LLAddr"; 5239 break; 5240 case CP0_REG17__MAAR: 5241 CP0_CHECK(ctx->mrp); 5242 gen_helper_mfhc0_maar(arg, cpu_env); 5243 register_name = "MAAR"; 5244 break; 5245 default: 5246 goto cp0_unimplemented; 5247 } 5248 break; 5249 case CP0_REGISTER_19: 5250 switch (sel) { 5251 case CP0_REG19__WATCHHI0: 5252 case CP0_REG19__WATCHHI1: 5253 case CP0_REG19__WATCHHI2: 5254 case CP0_REG19__WATCHHI3: 5255 case CP0_REG19__WATCHHI4: 5256 case CP0_REG19__WATCHHI5: 5257 case CP0_REG19__WATCHHI6: 5258 case CP0_REG19__WATCHHI7: 5259 /* upper 32 bits are only available when Config5MI != 0 */ 5260 CP0_CHECK(ctx->mi); 5261 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_WatchHi[sel]), 0); 5262 register_name = "WatchHi"; 5263 break; 5264 default: 5265 goto cp0_unimplemented; 5266 } 5267 break; 5268 case CP0_REGISTER_28: 5269 switch (sel) { 5270 case 0: 5271 case 2: 5272 case 4: 5273 case 6: 5274 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_TagLo), 0); 5275 register_name = "TagLo"; 5276 break; 5277 default: 5278 goto cp0_unimplemented; 5279 } 5280 break; 5281 default: 5282 goto cp0_unimplemented; 5283 } 5284 trace_mips_translate_c0("mfhc0", register_name, reg, sel); 5285 return; 5286 5287 cp0_unimplemented: 5288 qemu_log_mask(LOG_UNIMP, "mfhc0 %s (reg %d sel %d)\n", 5289 register_name, reg, sel); 5290 tcg_gen_movi_tl(arg, 0); 5291 } 5292 5293 static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel) 5294 { 5295 const char *register_name = "invalid"; 5296 uint64_t mask = ctx->PAMask >> 36; 5297 5298 switch (reg) { 5299 case CP0_REGISTER_02: 5300 switch (sel) { 5301 case 0: 5302 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); 5303 tcg_gen_andi_tl(arg, arg, mask); 5304 gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0)); 5305 register_name = "EntryLo0"; 5306 break; 5307 default: 5308 goto cp0_unimplemented; 5309 } 5310 break; 5311 case CP0_REGISTER_03: 5312 switch (sel) { 5313 case CP0_REG03__ENTRYLO1: 5314 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); 5315 tcg_gen_andi_tl(arg, arg, mask); 5316 gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1)); 5317 register_name = "EntryLo1"; 5318 break; 5319 default: 5320 goto cp0_unimplemented; 5321 } 5322 break; 5323 case CP0_REGISTER_09: 5324 switch (sel) { 5325 case CP0_REG09__SAAR: 5326 CP0_CHECK(ctx->saar); 5327 gen_helper_mthc0_saar(cpu_env, arg); 5328 register_name = "SAAR"; 5329 break; 5330 default: 5331 goto cp0_unimplemented; 5332 } 5333 break; 5334 case CP0_REGISTER_17: 5335 switch (sel) { 5336 case CP0_REG17__LLADDR: 5337 /* 5338 * LLAddr is read-only (the only exception is bit 0 if LLB is 5339 * supported); the CP0_LLAddr_rw_bitmask does not seem to be 5340 * relevant for modern MIPS cores supporting MTHC0, therefore 5341 * treating MTHC0 to LLAddr as NOP. 5342 */ 5343 register_name = "LLAddr"; 5344 break; 5345 case CP0_REG17__MAAR: 5346 CP0_CHECK(ctx->mrp); 5347 gen_helper_mthc0_maar(cpu_env, arg); 5348 register_name = "MAAR"; 5349 break; 5350 default: 5351 goto cp0_unimplemented; 5352 } 5353 break; 5354 case CP0_REGISTER_19: 5355 switch (sel) { 5356 case CP0_REG19__WATCHHI0: 5357 case CP0_REG19__WATCHHI1: 5358 case CP0_REG19__WATCHHI2: 5359 case CP0_REG19__WATCHHI3: 5360 case CP0_REG19__WATCHHI4: 5361 case CP0_REG19__WATCHHI5: 5362 case CP0_REG19__WATCHHI6: 5363 case CP0_REG19__WATCHHI7: 5364 /* upper 32 bits are only available when Config5MI != 0 */ 5365 CP0_CHECK(ctx->mi); 5366 gen_helper_0e1i(mthc0_watchhi, arg, sel); 5367 register_name = "WatchHi"; 5368 break; 5369 default: 5370 goto cp0_unimplemented; 5371 } 5372 break; 5373 case CP0_REGISTER_28: 5374 switch (sel) { 5375 case 0: 5376 case 2: 5377 case 4: 5378 case 6: 5379 tcg_gen_andi_tl(arg, arg, mask); 5380 gen_mthc0_store64(arg, offsetof(CPUMIPSState, CP0_TagLo)); 5381 register_name = "TagLo"; 5382 break; 5383 default: 5384 goto cp0_unimplemented; 5385 } 5386 break; 5387 default: 5388 goto cp0_unimplemented; 5389 } 5390 trace_mips_translate_c0("mthc0", register_name, reg, sel); 5391 return; 5392 5393 cp0_unimplemented: 5394 qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n", 5395 register_name, reg, sel); 5396 } 5397 5398 static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg) 5399 { 5400 if (ctx->insn_flags & ISA_MIPS_R6) { 5401 tcg_gen_movi_tl(arg, 0); 5402 } else { 5403 tcg_gen_movi_tl(arg, ~0); 5404 } 5405 } 5406 5407 static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) 5408 { 5409 const char *register_name = "invalid"; 5410 5411 if (sel != 0) { 5412 check_insn(ctx, ISA_MIPS_R1); 5413 } 5414 5415 switch (reg) { 5416 case CP0_REGISTER_00: 5417 switch (sel) { 5418 case CP0_REG00__INDEX: 5419 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index)); 5420 register_name = "Index"; 5421 break; 5422 case CP0_REG00__MVPCONTROL: 5423 CP0_CHECK(ctx->insn_flags & ASE_MT); 5424 gen_helper_mfc0_mvpcontrol(arg, cpu_env); 5425 register_name = "MVPControl"; 5426 break; 5427 case CP0_REG00__MVPCONF0: 5428 CP0_CHECK(ctx->insn_flags & ASE_MT); 5429 gen_helper_mfc0_mvpconf0(arg, cpu_env); 5430 register_name = "MVPConf0"; 5431 break; 5432 case CP0_REG00__MVPCONF1: 5433 CP0_CHECK(ctx->insn_flags & ASE_MT); 5434 gen_helper_mfc0_mvpconf1(arg, cpu_env); 5435 register_name = "MVPConf1"; 5436 break; 5437 case CP0_REG00__VPCONTROL: 5438 CP0_CHECK(ctx->vp); 5439 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl)); 5440 register_name = "VPControl"; 5441 break; 5442 default: 5443 goto cp0_unimplemented; 5444 } 5445 break; 5446 case CP0_REGISTER_01: 5447 switch (sel) { 5448 case CP0_REG01__RANDOM: 5449 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 5450 gen_helper_mfc0_random(arg, cpu_env); 5451 register_name = "Random"; 5452 break; 5453 case CP0_REG01__VPECONTROL: 5454 CP0_CHECK(ctx->insn_flags & ASE_MT); 5455 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl)); 5456 register_name = "VPEControl"; 5457 break; 5458 case CP0_REG01__VPECONF0: 5459 CP0_CHECK(ctx->insn_flags & ASE_MT); 5460 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0)); 5461 register_name = "VPEConf0"; 5462 break; 5463 case CP0_REG01__VPECONF1: 5464 CP0_CHECK(ctx->insn_flags & ASE_MT); 5465 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1)); 5466 register_name = "VPEConf1"; 5467 break; 5468 case CP0_REG01__YQMASK: 5469 CP0_CHECK(ctx->insn_flags & ASE_MT); 5470 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask)); 5471 register_name = "YQMask"; 5472 break; 5473 case CP0_REG01__VPESCHEDULE: 5474 CP0_CHECK(ctx->insn_flags & ASE_MT); 5475 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule)); 5476 register_name = "VPESchedule"; 5477 break; 5478 case CP0_REG01__VPESCHEFBACK: 5479 CP0_CHECK(ctx->insn_flags & ASE_MT); 5480 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack)); 5481 register_name = "VPEScheFBack"; 5482 break; 5483 case CP0_REG01__VPEOPT: 5484 CP0_CHECK(ctx->insn_flags & ASE_MT); 5485 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt)); 5486 register_name = "VPEOpt"; 5487 break; 5488 default: 5489 goto cp0_unimplemented; 5490 } 5491 break; 5492 case CP0_REGISTER_02: 5493 switch (sel) { 5494 case CP0_REG02__ENTRYLO0: 5495 { 5496 TCGv_i64 tmp = tcg_temp_new_i64(); 5497 tcg_gen_ld_i64(tmp, cpu_env, 5498 offsetof(CPUMIPSState, CP0_EntryLo0)); 5499 #if defined(TARGET_MIPS64) 5500 if (ctx->rxi) { 5501 /* Move RI/XI fields to bits 31:30 */ 5502 tcg_gen_shri_tl(arg, tmp, CP0EnLo_XI); 5503 tcg_gen_deposit_tl(tmp, tmp, arg, 30, 2); 5504 } 5505 #endif 5506 gen_move_low32(arg, tmp); 5507 } 5508 register_name = "EntryLo0"; 5509 break; 5510 case CP0_REG02__TCSTATUS: 5511 CP0_CHECK(ctx->insn_flags & ASE_MT); 5512 gen_helper_mfc0_tcstatus(arg, cpu_env); 5513 register_name = "TCStatus"; 5514 break; 5515 case CP0_REG02__TCBIND: 5516 CP0_CHECK(ctx->insn_flags & ASE_MT); 5517 gen_helper_mfc0_tcbind(arg, cpu_env); 5518 register_name = "TCBind"; 5519 break; 5520 case CP0_REG02__TCRESTART: 5521 CP0_CHECK(ctx->insn_flags & ASE_MT); 5522 gen_helper_mfc0_tcrestart(arg, cpu_env); 5523 register_name = "TCRestart"; 5524 break; 5525 case CP0_REG02__TCHALT: 5526 CP0_CHECK(ctx->insn_flags & ASE_MT); 5527 gen_helper_mfc0_tchalt(arg, cpu_env); 5528 register_name = "TCHalt"; 5529 break; 5530 case CP0_REG02__TCCONTEXT: 5531 CP0_CHECK(ctx->insn_flags & ASE_MT); 5532 gen_helper_mfc0_tccontext(arg, cpu_env); 5533 register_name = "TCContext"; 5534 break; 5535 case CP0_REG02__TCSCHEDULE: 5536 CP0_CHECK(ctx->insn_flags & ASE_MT); 5537 gen_helper_mfc0_tcschedule(arg, cpu_env); 5538 register_name = "TCSchedule"; 5539 break; 5540 case CP0_REG02__TCSCHEFBACK: 5541 CP0_CHECK(ctx->insn_flags & ASE_MT); 5542 gen_helper_mfc0_tcschefback(arg, cpu_env); 5543 register_name = "TCScheFBack"; 5544 break; 5545 default: 5546 goto cp0_unimplemented; 5547 } 5548 break; 5549 case CP0_REGISTER_03: 5550 switch (sel) { 5551 case CP0_REG03__ENTRYLO1: 5552 { 5553 TCGv_i64 tmp = tcg_temp_new_i64(); 5554 tcg_gen_ld_i64(tmp, cpu_env, 5555 offsetof(CPUMIPSState, CP0_EntryLo1)); 5556 #if defined(TARGET_MIPS64) 5557 if (ctx->rxi) { 5558 /* Move RI/XI fields to bits 31:30 */ 5559 tcg_gen_shri_tl(arg, tmp, CP0EnLo_XI); 5560 tcg_gen_deposit_tl(tmp, tmp, arg, 30, 2); 5561 } 5562 #endif 5563 gen_move_low32(arg, tmp); 5564 } 5565 register_name = "EntryLo1"; 5566 break; 5567 case CP0_REG03__GLOBALNUM: 5568 CP0_CHECK(ctx->vp); 5569 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber)); 5570 register_name = "GlobalNumber"; 5571 break; 5572 default: 5573 goto cp0_unimplemented; 5574 } 5575 break; 5576 case CP0_REGISTER_04: 5577 switch (sel) { 5578 case CP0_REG04__CONTEXT: 5579 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context)); 5580 tcg_gen_ext32s_tl(arg, arg); 5581 register_name = "Context"; 5582 break; 5583 case CP0_REG04__CONTEXTCONFIG: 5584 /* SmartMIPS ASE */ 5585 /* gen_helper_mfc0_contextconfig(arg); */ 5586 register_name = "ContextConfig"; 5587 goto cp0_unimplemented; 5588 case CP0_REG04__USERLOCAL: 5589 CP0_CHECK(ctx->ulri); 5590 tcg_gen_ld_tl(arg, cpu_env, 5591 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 5592 tcg_gen_ext32s_tl(arg, arg); 5593 register_name = "UserLocal"; 5594 break; 5595 case CP0_REG04__MMID: 5596 CP0_CHECK(ctx->mi); 5597 gen_helper_mtc0_memorymapid(cpu_env, arg); 5598 register_name = "MMID"; 5599 break; 5600 default: 5601 goto cp0_unimplemented; 5602 } 5603 break; 5604 case CP0_REGISTER_05: 5605 switch (sel) { 5606 case CP0_REG05__PAGEMASK: 5607 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask)); 5608 register_name = "PageMask"; 5609 break; 5610 case CP0_REG05__PAGEGRAIN: 5611 check_insn(ctx, ISA_MIPS_R2); 5612 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); 5613 register_name = "PageGrain"; 5614 break; 5615 case CP0_REG05__SEGCTL0: 5616 CP0_CHECK(ctx->sc); 5617 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0)); 5618 tcg_gen_ext32s_tl(arg, arg); 5619 register_name = "SegCtl0"; 5620 break; 5621 case CP0_REG05__SEGCTL1: 5622 CP0_CHECK(ctx->sc); 5623 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1)); 5624 tcg_gen_ext32s_tl(arg, arg); 5625 register_name = "SegCtl1"; 5626 break; 5627 case CP0_REG05__SEGCTL2: 5628 CP0_CHECK(ctx->sc); 5629 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2)); 5630 tcg_gen_ext32s_tl(arg, arg); 5631 register_name = "SegCtl2"; 5632 break; 5633 case CP0_REG05__PWBASE: 5634 check_pw(ctx); 5635 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase)); 5636 register_name = "PWBase"; 5637 break; 5638 case CP0_REG05__PWFIELD: 5639 check_pw(ctx); 5640 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField)); 5641 register_name = "PWField"; 5642 break; 5643 case CP0_REG05__PWSIZE: 5644 check_pw(ctx); 5645 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize)); 5646 register_name = "PWSize"; 5647 break; 5648 default: 5649 goto cp0_unimplemented; 5650 } 5651 break; 5652 case CP0_REGISTER_06: 5653 switch (sel) { 5654 case CP0_REG06__WIRED: 5655 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired)); 5656 register_name = "Wired"; 5657 break; 5658 case CP0_REG06__SRSCONF0: 5659 check_insn(ctx, ISA_MIPS_R2); 5660 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); 5661 register_name = "SRSConf0"; 5662 break; 5663 case CP0_REG06__SRSCONF1: 5664 check_insn(ctx, ISA_MIPS_R2); 5665 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); 5666 register_name = "SRSConf1"; 5667 break; 5668 case CP0_REG06__SRSCONF2: 5669 check_insn(ctx, ISA_MIPS_R2); 5670 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); 5671 register_name = "SRSConf2"; 5672 break; 5673 case CP0_REG06__SRSCONF3: 5674 check_insn(ctx, ISA_MIPS_R2); 5675 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); 5676 register_name = "SRSConf3"; 5677 break; 5678 case CP0_REG06__SRSCONF4: 5679 check_insn(ctx, ISA_MIPS_R2); 5680 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); 5681 register_name = "SRSConf4"; 5682 break; 5683 case CP0_REG06__PWCTL: 5684 check_pw(ctx); 5685 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl)); 5686 register_name = "PWCtl"; 5687 break; 5688 default: 5689 goto cp0_unimplemented; 5690 } 5691 break; 5692 case CP0_REGISTER_07: 5693 switch (sel) { 5694 case CP0_REG07__HWRENA: 5695 check_insn(ctx, ISA_MIPS_R2); 5696 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); 5697 register_name = "HWREna"; 5698 break; 5699 default: 5700 goto cp0_unimplemented; 5701 } 5702 break; 5703 case CP0_REGISTER_08: 5704 switch (sel) { 5705 case CP0_REG08__BADVADDR: 5706 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); 5707 tcg_gen_ext32s_tl(arg, arg); 5708 register_name = "BadVAddr"; 5709 break; 5710 case CP0_REG08__BADINSTR: 5711 CP0_CHECK(ctx->bi); 5712 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr)); 5713 register_name = "BadInstr"; 5714 break; 5715 case CP0_REG08__BADINSTRP: 5716 CP0_CHECK(ctx->bp); 5717 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP)); 5718 register_name = "BadInstrP"; 5719 break; 5720 case CP0_REG08__BADINSTRX: 5721 CP0_CHECK(ctx->bi); 5722 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX)); 5723 tcg_gen_andi_tl(arg, arg, ~0xffff); 5724 register_name = "BadInstrX"; 5725 break; 5726 default: 5727 goto cp0_unimplemented; 5728 } 5729 break; 5730 case CP0_REGISTER_09: 5731 switch (sel) { 5732 case CP0_REG09__COUNT: 5733 /* Mark as an IO operation because we read the time. */ 5734 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 5735 gen_io_start(); 5736 } 5737 gen_helper_mfc0_count(arg, cpu_env); 5738 /* 5739 * Break the TB to be able to take timer interrupts immediately 5740 * after reading count. DISAS_STOP isn't sufficient, we need to 5741 * ensure we break completely out of translated code. 5742 */ 5743 gen_save_pc(ctx->base.pc_next + 4); 5744 ctx->base.is_jmp = DISAS_EXIT; 5745 register_name = "Count"; 5746 break; 5747 case CP0_REG09__SAARI: 5748 CP0_CHECK(ctx->saar); 5749 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); 5750 register_name = "SAARI"; 5751 break; 5752 case CP0_REG09__SAAR: 5753 CP0_CHECK(ctx->saar); 5754 gen_helper_mfc0_saar(arg, cpu_env); 5755 register_name = "SAAR"; 5756 break; 5757 default: 5758 goto cp0_unimplemented; 5759 } 5760 break; 5761 case CP0_REGISTER_10: 5762 switch (sel) { 5763 case CP0_REG10__ENTRYHI: 5764 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi)); 5765 tcg_gen_ext32s_tl(arg, arg); 5766 register_name = "EntryHi"; 5767 break; 5768 default: 5769 goto cp0_unimplemented; 5770 } 5771 break; 5772 case CP0_REGISTER_11: 5773 switch (sel) { 5774 case CP0_REG11__COMPARE: 5775 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare)); 5776 register_name = "Compare"; 5777 break; 5778 /* 6,7 are implementation dependent */ 5779 default: 5780 goto cp0_unimplemented; 5781 } 5782 break; 5783 case CP0_REGISTER_12: 5784 switch (sel) { 5785 case CP0_REG12__STATUS: 5786 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status)); 5787 register_name = "Status"; 5788 break; 5789 case CP0_REG12__INTCTL: 5790 check_insn(ctx, ISA_MIPS_R2); 5791 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); 5792 register_name = "IntCtl"; 5793 break; 5794 case CP0_REG12__SRSCTL: 5795 check_insn(ctx, ISA_MIPS_R2); 5796 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); 5797 register_name = "SRSCtl"; 5798 break; 5799 case CP0_REG12__SRSMAP: 5800 check_insn(ctx, ISA_MIPS_R2); 5801 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); 5802 register_name = "SRSMap"; 5803 break; 5804 default: 5805 goto cp0_unimplemented; 5806 } 5807 break; 5808 case CP0_REGISTER_13: 5809 switch (sel) { 5810 case CP0_REG13__CAUSE: 5811 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause)); 5812 register_name = "Cause"; 5813 break; 5814 default: 5815 goto cp0_unimplemented; 5816 } 5817 break; 5818 case CP0_REGISTER_14: 5819 switch (sel) { 5820 case CP0_REG14__EPC: 5821 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC)); 5822 tcg_gen_ext32s_tl(arg, arg); 5823 register_name = "EPC"; 5824 break; 5825 default: 5826 goto cp0_unimplemented; 5827 } 5828 break; 5829 case CP0_REGISTER_15: 5830 switch (sel) { 5831 case CP0_REG15__PRID: 5832 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid)); 5833 register_name = "PRid"; 5834 break; 5835 case CP0_REG15__EBASE: 5836 check_insn(ctx, ISA_MIPS_R2); 5837 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); 5838 tcg_gen_ext32s_tl(arg, arg); 5839 register_name = "EBase"; 5840 break; 5841 case CP0_REG15__CMGCRBASE: 5842 check_insn(ctx, ISA_MIPS_R2); 5843 CP0_CHECK(ctx->cmgcr); 5844 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase)); 5845 tcg_gen_ext32s_tl(arg, arg); 5846 register_name = "CMGCRBase"; 5847 break; 5848 default: 5849 goto cp0_unimplemented; 5850 } 5851 break; 5852 case CP0_REGISTER_16: 5853 switch (sel) { 5854 case CP0_REG16__CONFIG: 5855 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0)); 5856 register_name = "Config"; 5857 break; 5858 case CP0_REG16__CONFIG1: 5859 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1)); 5860 register_name = "Config1"; 5861 break; 5862 case CP0_REG16__CONFIG2: 5863 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2)); 5864 register_name = "Config2"; 5865 break; 5866 case CP0_REG16__CONFIG3: 5867 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3)); 5868 register_name = "Config3"; 5869 break; 5870 case CP0_REG16__CONFIG4: 5871 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4)); 5872 register_name = "Config4"; 5873 break; 5874 case CP0_REG16__CONFIG5: 5875 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5)); 5876 register_name = "Config5"; 5877 break; 5878 /* 6,7 are implementation dependent */ 5879 case CP0_REG16__CONFIG6: 5880 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6)); 5881 register_name = "Config6"; 5882 break; 5883 case CP0_REG16__CONFIG7: 5884 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7)); 5885 register_name = "Config7"; 5886 break; 5887 default: 5888 goto cp0_unimplemented; 5889 } 5890 break; 5891 case CP0_REGISTER_17: 5892 switch (sel) { 5893 case CP0_REG17__LLADDR: 5894 gen_helper_mfc0_lladdr(arg, cpu_env); 5895 register_name = "LLAddr"; 5896 break; 5897 case CP0_REG17__MAAR: 5898 CP0_CHECK(ctx->mrp); 5899 gen_helper_mfc0_maar(arg, cpu_env); 5900 register_name = "MAAR"; 5901 break; 5902 case CP0_REG17__MAARI: 5903 CP0_CHECK(ctx->mrp); 5904 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI)); 5905 register_name = "MAARI"; 5906 break; 5907 default: 5908 goto cp0_unimplemented; 5909 } 5910 break; 5911 case CP0_REGISTER_18: 5912 switch (sel) { 5913 case CP0_REG18__WATCHLO0: 5914 case CP0_REG18__WATCHLO1: 5915 case CP0_REG18__WATCHLO2: 5916 case CP0_REG18__WATCHLO3: 5917 case CP0_REG18__WATCHLO4: 5918 case CP0_REG18__WATCHLO5: 5919 case CP0_REG18__WATCHLO6: 5920 case CP0_REG18__WATCHLO7: 5921 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 5922 gen_helper_1e0i(mfc0_watchlo, arg, sel); 5923 register_name = "WatchLo"; 5924 break; 5925 default: 5926 goto cp0_unimplemented; 5927 } 5928 break; 5929 case CP0_REGISTER_19: 5930 switch (sel) { 5931 case CP0_REG19__WATCHHI0: 5932 case CP0_REG19__WATCHHI1: 5933 case CP0_REG19__WATCHHI2: 5934 case CP0_REG19__WATCHHI3: 5935 case CP0_REG19__WATCHHI4: 5936 case CP0_REG19__WATCHHI5: 5937 case CP0_REG19__WATCHHI6: 5938 case CP0_REG19__WATCHHI7: 5939 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 5940 gen_helper_1e0i(mfc0_watchhi, arg, sel); 5941 register_name = "WatchHi"; 5942 break; 5943 default: 5944 goto cp0_unimplemented; 5945 } 5946 break; 5947 case CP0_REGISTER_20: 5948 switch (sel) { 5949 case CP0_REG20__XCONTEXT: 5950 #if defined(TARGET_MIPS64) 5951 check_insn(ctx, ISA_MIPS3); 5952 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext)); 5953 tcg_gen_ext32s_tl(arg, arg); 5954 register_name = "XContext"; 5955 break; 5956 #endif 5957 default: 5958 goto cp0_unimplemented; 5959 } 5960 break; 5961 case CP0_REGISTER_21: 5962 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 5963 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 5964 switch (sel) { 5965 case 0: 5966 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask)); 5967 register_name = "Framemask"; 5968 break; 5969 default: 5970 goto cp0_unimplemented; 5971 } 5972 break; 5973 case CP0_REGISTER_22: 5974 tcg_gen_movi_tl(arg, 0); /* unimplemented */ 5975 register_name = "'Diagnostic"; /* implementation dependent */ 5976 break; 5977 case CP0_REGISTER_23: 5978 switch (sel) { 5979 case CP0_REG23__DEBUG: 5980 gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */ 5981 register_name = "Debug"; 5982 break; 5983 case CP0_REG23__TRACECONTROL: 5984 /* PDtrace support */ 5985 /* gen_helper_mfc0_tracecontrol(arg); */ 5986 register_name = "TraceControl"; 5987 goto cp0_unimplemented; 5988 case CP0_REG23__TRACECONTROL2: 5989 /* PDtrace support */ 5990 /* gen_helper_mfc0_tracecontrol2(arg); */ 5991 register_name = "TraceControl2"; 5992 goto cp0_unimplemented; 5993 case CP0_REG23__USERTRACEDATA1: 5994 /* PDtrace support */ 5995 /* gen_helper_mfc0_usertracedata1(arg);*/ 5996 register_name = "UserTraceData1"; 5997 goto cp0_unimplemented; 5998 case CP0_REG23__TRACEIBPC: 5999 /* PDtrace support */ 6000 /* gen_helper_mfc0_traceibpc(arg); */ 6001 register_name = "TraceIBPC"; 6002 goto cp0_unimplemented; 6003 case CP0_REG23__TRACEDBPC: 6004 /* PDtrace support */ 6005 /* gen_helper_mfc0_tracedbpc(arg); */ 6006 register_name = "TraceDBPC"; 6007 goto cp0_unimplemented; 6008 default: 6009 goto cp0_unimplemented; 6010 } 6011 break; 6012 case CP0_REGISTER_24: 6013 switch (sel) { 6014 case CP0_REG24__DEPC: 6015 /* EJTAG support */ 6016 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC)); 6017 tcg_gen_ext32s_tl(arg, arg); 6018 register_name = "DEPC"; 6019 break; 6020 default: 6021 goto cp0_unimplemented; 6022 } 6023 break; 6024 case CP0_REGISTER_25: 6025 switch (sel) { 6026 case CP0_REG25__PERFCTL0: 6027 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0)); 6028 register_name = "Performance0"; 6029 break; 6030 case CP0_REG25__PERFCNT0: 6031 /* gen_helper_mfc0_performance1(arg); */ 6032 register_name = "Performance1"; 6033 goto cp0_unimplemented; 6034 case CP0_REG25__PERFCTL1: 6035 /* gen_helper_mfc0_performance2(arg); */ 6036 register_name = "Performance2"; 6037 goto cp0_unimplemented; 6038 case CP0_REG25__PERFCNT1: 6039 /* gen_helper_mfc0_performance3(arg); */ 6040 register_name = "Performance3"; 6041 goto cp0_unimplemented; 6042 case CP0_REG25__PERFCTL2: 6043 /* gen_helper_mfc0_performance4(arg); */ 6044 register_name = "Performance4"; 6045 goto cp0_unimplemented; 6046 case CP0_REG25__PERFCNT2: 6047 /* gen_helper_mfc0_performance5(arg); */ 6048 register_name = "Performance5"; 6049 goto cp0_unimplemented; 6050 case CP0_REG25__PERFCTL3: 6051 /* gen_helper_mfc0_performance6(arg); */ 6052 register_name = "Performance6"; 6053 goto cp0_unimplemented; 6054 case CP0_REG25__PERFCNT3: 6055 /* gen_helper_mfc0_performance7(arg); */ 6056 register_name = "Performance7"; 6057 goto cp0_unimplemented; 6058 default: 6059 goto cp0_unimplemented; 6060 } 6061 break; 6062 case CP0_REGISTER_26: 6063 switch (sel) { 6064 case CP0_REG26__ERRCTL: 6065 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl)); 6066 register_name = "ErrCtl"; 6067 break; 6068 default: 6069 goto cp0_unimplemented; 6070 } 6071 break; 6072 case CP0_REGISTER_27: 6073 switch (sel) { 6074 case CP0_REG27__CACHERR: 6075 tcg_gen_movi_tl(arg, 0); /* unimplemented */ 6076 register_name = "CacheErr"; 6077 break; 6078 default: 6079 goto cp0_unimplemented; 6080 } 6081 break; 6082 case CP0_REGISTER_28: 6083 switch (sel) { 6084 case CP0_REG28__TAGLO: 6085 case CP0_REG28__TAGLO1: 6086 case CP0_REG28__TAGLO2: 6087 case CP0_REG28__TAGLO3: 6088 { 6089 TCGv_i64 tmp = tcg_temp_new_i64(); 6090 tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState, CP0_TagLo)); 6091 gen_move_low32(arg, tmp); 6092 } 6093 register_name = "TagLo"; 6094 break; 6095 case CP0_REG28__DATALO: 6096 case CP0_REG28__DATALO1: 6097 case CP0_REG28__DATALO2: 6098 case CP0_REG28__DATALO3: 6099 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo)); 6100 register_name = "DataLo"; 6101 break; 6102 default: 6103 goto cp0_unimplemented; 6104 } 6105 break; 6106 case CP0_REGISTER_29: 6107 switch (sel) { 6108 case CP0_REG29__TAGHI: 6109 case CP0_REG29__TAGHI1: 6110 case CP0_REG29__TAGHI2: 6111 case CP0_REG29__TAGHI3: 6112 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi)); 6113 register_name = "TagHi"; 6114 break; 6115 case CP0_REG29__DATAHI: 6116 case CP0_REG29__DATAHI1: 6117 case CP0_REG29__DATAHI2: 6118 case CP0_REG29__DATAHI3: 6119 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi)); 6120 register_name = "DataHi"; 6121 break; 6122 default: 6123 goto cp0_unimplemented; 6124 } 6125 break; 6126 case CP0_REGISTER_30: 6127 switch (sel) { 6128 case CP0_REG30__ERROREPC: 6129 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); 6130 tcg_gen_ext32s_tl(arg, arg); 6131 register_name = "ErrorEPC"; 6132 break; 6133 default: 6134 goto cp0_unimplemented; 6135 } 6136 break; 6137 case CP0_REGISTER_31: 6138 switch (sel) { 6139 case CP0_REG31__DESAVE: 6140 /* EJTAG support */ 6141 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); 6142 register_name = "DESAVE"; 6143 break; 6144 case CP0_REG31__KSCRATCH1: 6145 case CP0_REG31__KSCRATCH2: 6146 case CP0_REG31__KSCRATCH3: 6147 case CP0_REG31__KSCRATCH4: 6148 case CP0_REG31__KSCRATCH5: 6149 case CP0_REG31__KSCRATCH6: 6150 CP0_CHECK(ctx->kscrexist & (1 << sel)); 6151 tcg_gen_ld_tl(arg, cpu_env, 6152 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); 6153 tcg_gen_ext32s_tl(arg, arg); 6154 register_name = "KScratch"; 6155 break; 6156 default: 6157 goto cp0_unimplemented; 6158 } 6159 break; 6160 default: 6161 goto cp0_unimplemented; 6162 } 6163 trace_mips_translate_c0("mfc0", register_name, reg, sel); 6164 return; 6165 6166 cp0_unimplemented: 6167 qemu_log_mask(LOG_UNIMP, "mfc0 %s (reg %d sel %d)\n", 6168 register_name, reg, sel); 6169 gen_mfc0_unimplemented(ctx, arg); 6170 } 6171 6172 static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) 6173 { 6174 const char *register_name = "invalid"; 6175 6176 if (sel != 0) { 6177 check_insn(ctx, ISA_MIPS_R1); 6178 } 6179 6180 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 6181 gen_io_start(); 6182 } 6183 6184 switch (reg) { 6185 case CP0_REGISTER_00: 6186 switch (sel) { 6187 case CP0_REG00__INDEX: 6188 gen_helper_mtc0_index(cpu_env, arg); 6189 register_name = "Index"; 6190 break; 6191 case CP0_REG00__MVPCONTROL: 6192 CP0_CHECK(ctx->insn_flags & ASE_MT); 6193 gen_helper_mtc0_mvpcontrol(cpu_env, arg); 6194 register_name = "MVPControl"; 6195 break; 6196 case CP0_REG00__MVPCONF0: 6197 CP0_CHECK(ctx->insn_flags & ASE_MT); 6198 /* ignored */ 6199 register_name = "MVPConf0"; 6200 break; 6201 case CP0_REG00__MVPCONF1: 6202 CP0_CHECK(ctx->insn_flags & ASE_MT); 6203 /* ignored */ 6204 register_name = "MVPConf1"; 6205 break; 6206 case CP0_REG00__VPCONTROL: 6207 CP0_CHECK(ctx->vp); 6208 /* ignored */ 6209 register_name = "VPControl"; 6210 break; 6211 default: 6212 goto cp0_unimplemented; 6213 } 6214 break; 6215 case CP0_REGISTER_01: 6216 switch (sel) { 6217 case CP0_REG01__RANDOM: 6218 /* ignored */ 6219 register_name = "Random"; 6220 break; 6221 case CP0_REG01__VPECONTROL: 6222 CP0_CHECK(ctx->insn_flags & ASE_MT); 6223 gen_helper_mtc0_vpecontrol(cpu_env, arg); 6224 register_name = "VPEControl"; 6225 break; 6226 case CP0_REG01__VPECONF0: 6227 CP0_CHECK(ctx->insn_flags & ASE_MT); 6228 gen_helper_mtc0_vpeconf0(cpu_env, arg); 6229 register_name = "VPEConf0"; 6230 break; 6231 case CP0_REG01__VPECONF1: 6232 CP0_CHECK(ctx->insn_flags & ASE_MT); 6233 gen_helper_mtc0_vpeconf1(cpu_env, arg); 6234 register_name = "VPEConf1"; 6235 break; 6236 case CP0_REG01__YQMASK: 6237 CP0_CHECK(ctx->insn_flags & ASE_MT); 6238 gen_helper_mtc0_yqmask(cpu_env, arg); 6239 register_name = "YQMask"; 6240 break; 6241 case CP0_REG01__VPESCHEDULE: 6242 CP0_CHECK(ctx->insn_flags & ASE_MT); 6243 tcg_gen_st_tl(arg, cpu_env, 6244 offsetof(CPUMIPSState, CP0_VPESchedule)); 6245 register_name = "VPESchedule"; 6246 break; 6247 case CP0_REG01__VPESCHEFBACK: 6248 CP0_CHECK(ctx->insn_flags & ASE_MT); 6249 tcg_gen_st_tl(arg, cpu_env, 6250 offsetof(CPUMIPSState, CP0_VPEScheFBack)); 6251 register_name = "VPEScheFBack"; 6252 break; 6253 case CP0_REG01__VPEOPT: 6254 CP0_CHECK(ctx->insn_flags & ASE_MT); 6255 gen_helper_mtc0_vpeopt(cpu_env, arg); 6256 register_name = "VPEOpt"; 6257 break; 6258 default: 6259 goto cp0_unimplemented; 6260 } 6261 break; 6262 case CP0_REGISTER_02: 6263 switch (sel) { 6264 case CP0_REG02__ENTRYLO0: 6265 gen_helper_mtc0_entrylo0(cpu_env, arg); 6266 register_name = "EntryLo0"; 6267 break; 6268 case CP0_REG02__TCSTATUS: 6269 CP0_CHECK(ctx->insn_flags & ASE_MT); 6270 gen_helper_mtc0_tcstatus(cpu_env, arg); 6271 register_name = "TCStatus"; 6272 break; 6273 case CP0_REG02__TCBIND: 6274 CP0_CHECK(ctx->insn_flags & ASE_MT); 6275 gen_helper_mtc0_tcbind(cpu_env, arg); 6276 register_name = "TCBind"; 6277 break; 6278 case CP0_REG02__TCRESTART: 6279 CP0_CHECK(ctx->insn_flags & ASE_MT); 6280 gen_helper_mtc0_tcrestart(cpu_env, arg); 6281 register_name = "TCRestart"; 6282 break; 6283 case CP0_REG02__TCHALT: 6284 CP0_CHECK(ctx->insn_flags & ASE_MT); 6285 gen_helper_mtc0_tchalt(cpu_env, arg); 6286 register_name = "TCHalt"; 6287 break; 6288 case CP0_REG02__TCCONTEXT: 6289 CP0_CHECK(ctx->insn_flags & ASE_MT); 6290 gen_helper_mtc0_tccontext(cpu_env, arg); 6291 register_name = "TCContext"; 6292 break; 6293 case CP0_REG02__TCSCHEDULE: 6294 CP0_CHECK(ctx->insn_flags & ASE_MT); 6295 gen_helper_mtc0_tcschedule(cpu_env, arg); 6296 register_name = "TCSchedule"; 6297 break; 6298 case CP0_REG02__TCSCHEFBACK: 6299 CP0_CHECK(ctx->insn_flags & ASE_MT); 6300 gen_helper_mtc0_tcschefback(cpu_env, arg); 6301 register_name = "TCScheFBack"; 6302 break; 6303 default: 6304 goto cp0_unimplemented; 6305 } 6306 break; 6307 case CP0_REGISTER_03: 6308 switch (sel) { 6309 case CP0_REG03__ENTRYLO1: 6310 gen_helper_mtc0_entrylo1(cpu_env, arg); 6311 register_name = "EntryLo1"; 6312 break; 6313 case CP0_REG03__GLOBALNUM: 6314 CP0_CHECK(ctx->vp); 6315 /* ignored */ 6316 register_name = "GlobalNumber"; 6317 break; 6318 default: 6319 goto cp0_unimplemented; 6320 } 6321 break; 6322 case CP0_REGISTER_04: 6323 switch (sel) { 6324 case CP0_REG04__CONTEXT: 6325 gen_helper_mtc0_context(cpu_env, arg); 6326 register_name = "Context"; 6327 break; 6328 case CP0_REG04__CONTEXTCONFIG: 6329 /* SmartMIPS ASE */ 6330 /* gen_helper_mtc0_contextconfig(arg); */ 6331 register_name = "ContextConfig"; 6332 goto cp0_unimplemented; 6333 case CP0_REG04__USERLOCAL: 6334 CP0_CHECK(ctx->ulri); 6335 tcg_gen_st_tl(arg, cpu_env, 6336 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 6337 register_name = "UserLocal"; 6338 break; 6339 case CP0_REG04__MMID: 6340 CP0_CHECK(ctx->mi); 6341 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MemoryMapID)); 6342 register_name = "MMID"; 6343 break; 6344 default: 6345 goto cp0_unimplemented; 6346 } 6347 break; 6348 case CP0_REGISTER_05: 6349 switch (sel) { 6350 case CP0_REG05__PAGEMASK: 6351 gen_helper_mtc0_pagemask(cpu_env, arg); 6352 register_name = "PageMask"; 6353 break; 6354 case CP0_REG05__PAGEGRAIN: 6355 check_insn(ctx, ISA_MIPS_R2); 6356 gen_helper_mtc0_pagegrain(cpu_env, arg); 6357 register_name = "PageGrain"; 6358 ctx->base.is_jmp = DISAS_STOP; 6359 break; 6360 case CP0_REG05__SEGCTL0: 6361 CP0_CHECK(ctx->sc); 6362 gen_helper_mtc0_segctl0(cpu_env, arg); 6363 register_name = "SegCtl0"; 6364 break; 6365 case CP0_REG05__SEGCTL1: 6366 CP0_CHECK(ctx->sc); 6367 gen_helper_mtc0_segctl1(cpu_env, arg); 6368 register_name = "SegCtl1"; 6369 break; 6370 case CP0_REG05__SEGCTL2: 6371 CP0_CHECK(ctx->sc); 6372 gen_helper_mtc0_segctl2(cpu_env, arg); 6373 register_name = "SegCtl2"; 6374 break; 6375 case CP0_REG05__PWBASE: 6376 check_pw(ctx); 6377 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase)); 6378 register_name = "PWBase"; 6379 break; 6380 case CP0_REG05__PWFIELD: 6381 check_pw(ctx); 6382 gen_helper_mtc0_pwfield(cpu_env, arg); 6383 register_name = "PWField"; 6384 break; 6385 case CP0_REG05__PWSIZE: 6386 check_pw(ctx); 6387 gen_helper_mtc0_pwsize(cpu_env, arg); 6388 register_name = "PWSize"; 6389 break; 6390 default: 6391 goto cp0_unimplemented; 6392 } 6393 break; 6394 case CP0_REGISTER_06: 6395 switch (sel) { 6396 case CP0_REG06__WIRED: 6397 gen_helper_mtc0_wired(cpu_env, arg); 6398 register_name = "Wired"; 6399 break; 6400 case CP0_REG06__SRSCONF0: 6401 check_insn(ctx, ISA_MIPS_R2); 6402 gen_helper_mtc0_srsconf0(cpu_env, arg); 6403 register_name = "SRSConf0"; 6404 break; 6405 case CP0_REG06__SRSCONF1: 6406 check_insn(ctx, ISA_MIPS_R2); 6407 gen_helper_mtc0_srsconf1(cpu_env, arg); 6408 register_name = "SRSConf1"; 6409 break; 6410 case CP0_REG06__SRSCONF2: 6411 check_insn(ctx, ISA_MIPS_R2); 6412 gen_helper_mtc0_srsconf2(cpu_env, arg); 6413 register_name = "SRSConf2"; 6414 break; 6415 case CP0_REG06__SRSCONF3: 6416 check_insn(ctx, ISA_MIPS_R2); 6417 gen_helper_mtc0_srsconf3(cpu_env, arg); 6418 register_name = "SRSConf3"; 6419 break; 6420 case CP0_REG06__SRSCONF4: 6421 check_insn(ctx, ISA_MIPS_R2); 6422 gen_helper_mtc0_srsconf4(cpu_env, arg); 6423 register_name = "SRSConf4"; 6424 break; 6425 case CP0_REG06__PWCTL: 6426 check_pw(ctx); 6427 gen_helper_mtc0_pwctl(cpu_env, arg); 6428 register_name = "PWCtl"; 6429 break; 6430 default: 6431 goto cp0_unimplemented; 6432 } 6433 break; 6434 case CP0_REGISTER_07: 6435 switch (sel) { 6436 case CP0_REG07__HWRENA: 6437 check_insn(ctx, ISA_MIPS_R2); 6438 gen_helper_mtc0_hwrena(cpu_env, arg); 6439 ctx->base.is_jmp = DISAS_STOP; 6440 register_name = "HWREna"; 6441 break; 6442 default: 6443 goto cp0_unimplemented; 6444 } 6445 break; 6446 case CP0_REGISTER_08: 6447 switch (sel) { 6448 case CP0_REG08__BADVADDR: 6449 /* ignored */ 6450 register_name = "BadVAddr"; 6451 break; 6452 case CP0_REG08__BADINSTR: 6453 /* ignored */ 6454 register_name = "BadInstr"; 6455 break; 6456 case CP0_REG08__BADINSTRP: 6457 /* ignored */ 6458 register_name = "BadInstrP"; 6459 break; 6460 case CP0_REG08__BADINSTRX: 6461 /* ignored */ 6462 register_name = "BadInstrX"; 6463 break; 6464 default: 6465 goto cp0_unimplemented; 6466 } 6467 break; 6468 case CP0_REGISTER_09: 6469 switch (sel) { 6470 case CP0_REG09__COUNT: 6471 gen_helper_mtc0_count(cpu_env, arg); 6472 register_name = "Count"; 6473 break; 6474 case CP0_REG09__SAARI: 6475 CP0_CHECK(ctx->saar); 6476 gen_helper_mtc0_saari(cpu_env, arg); 6477 register_name = "SAARI"; 6478 break; 6479 case CP0_REG09__SAAR: 6480 CP0_CHECK(ctx->saar); 6481 gen_helper_mtc0_saar(cpu_env, arg); 6482 register_name = "SAAR"; 6483 break; 6484 default: 6485 goto cp0_unimplemented; 6486 } 6487 break; 6488 case CP0_REGISTER_10: 6489 switch (sel) { 6490 case CP0_REG10__ENTRYHI: 6491 gen_helper_mtc0_entryhi(cpu_env, arg); 6492 register_name = "EntryHi"; 6493 break; 6494 default: 6495 goto cp0_unimplemented; 6496 } 6497 break; 6498 case CP0_REGISTER_11: 6499 switch (sel) { 6500 case CP0_REG11__COMPARE: 6501 gen_helper_mtc0_compare(cpu_env, arg); 6502 register_name = "Compare"; 6503 break; 6504 /* 6,7 are implementation dependent */ 6505 default: 6506 goto cp0_unimplemented; 6507 } 6508 break; 6509 case CP0_REGISTER_12: 6510 switch (sel) { 6511 case CP0_REG12__STATUS: 6512 save_cpu_state(ctx, 1); 6513 gen_helper_mtc0_status(cpu_env, arg); 6514 /* DISAS_STOP isn't good enough here, hflags may have changed. */ 6515 gen_save_pc(ctx->base.pc_next + 4); 6516 ctx->base.is_jmp = DISAS_EXIT; 6517 register_name = "Status"; 6518 break; 6519 case CP0_REG12__INTCTL: 6520 check_insn(ctx, ISA_MIPS_R2); 6521 gen_helper_mtc0_intctl(cpu_env, arg); 6522 /* Stop translation as we may have switched the execution mode */ 6523 ctx->base.is_jmp = DISAS_STOP; 6524 register_name = "IntCtl"; 6525 break; 6526 case CP0_REG12__SRSCTL: 6527 check_insn(ctx, ISA_MIPS_R2); 6528 gen_helper_mtc0_srsctl(cpu_env, arg); 6529 /* Stop translation as we may have switched the execution mode */ 6530 ctx->base.is_jmp = DISAS_STOP; 6531 register_name = "SRSCtl"; 6532 break; 6533 case CP0_REG12__SRSMAP: 6534 check_insn(ctx, ISA_MIPS_R2); 6535 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); 6536 /* Stop translation as we may have switched the execution mode */ 6537 ctx->base.is_jmp = DISAS_STOP; 6538 register_name = "SRSMap"; 6539 break; 6540 default: 6541 goto cp0_unimplemented; 6542 } 6543 break; 6544 case CP0_REGISTER_13: 6545 switch (sel) { 6546 case CP0_REG13__CAUSE: 6547 save_cpu_state(ctx, 1); 6548 gen_helper_mtc0_cause(cpu_env, arg); 6549 /* 6550 * Stop translation as we may have triggered an interrupt. 6551 * DISAS_STOP isn't sufficient, we need to ensure we break out of 6552 * translated code to check for pending interrupts. 6553 */ 6554 gen_save_pc(ctx->base.pc_next + 4); 6555 ctx->base.is_jmp = DISAS_EXIT; 6556 register_name = "Cause"; 6557 break; 6558 default: 6559 goto cp0_unimplemented; 6560 } 6561 break; 6562 case CP0_REGISTER_14: 6563 switch (sel) { 6564 case CP0_REG14__EPC: 6565 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC)); 6566 register_name = "EPC"; 6567 break; 6568 default: 6569 goto cp0_unimplemented; 6570 } 6571 break; 6572 case CP0_REGISTER_15: 6573 switch (sel) { 6574 case CP0_REG15__PRID: 6575 /* ignored */ 6576 register_name = "PRid"; 6577 break; 6578 case CP0_REG15__EBASE: 6579 check_insn(ctx, ISA_MIPS_R2); 6580 gen_helper_mtc0_ebase(cpu_env, arg); 6581 register_name = "EBase"; 6582 break; 6583 default: 6584 goto cp0_unimplemented; 6585 } 6586 break; 6587 case CP0_REGISTER_16: 6588 switch (sel) { 6589 case CP0_REG16__CONFIG: 6590 gen_helper_mtc0_config0(cpu_env, arg); 6591 register_name = "Config"; 6592 /* Stop translation as we may have switched the execution mode */ 6593 ctx->base.is_jmp = DISAS_STOP; 6594 break; 6595 case CP0_REG16__CONFIG1: 6596 /* ignored, read only */ 6597 register_name = "Config1"; 6598 break; 6599 case CP0_REG16__CONFIG2: 6600 gen_helper_mtc0_config2(cpu_env, arg); 6601 register_name = "Config2"; 6602 /* Stop translation as we may have switched the execution mode */ 6603 ctx->base.is_jmp = DISAS_STOP; 6604 break; 6605 case CP0_REG16__CONFIG3: 6606 gen_helper_mtc0_config3(cpu_env, arg); 6607 register_name = "Config3"; 6608 /* Stop translation as we may have switched the execution mode */ 6609 ctx->base.is_jmp = DISAS_STOP; 6610 break; 6611 case CP0_REG16__CONFIG4: 6612 gen_helper_mtc0_config4(cpu_env, arg); 6613 register_name = "Config4"; 6614 ctx->base.is_jmp = DISAS_STOP; 6615 break; 6616 case CP0_REG16__CONFIG5: 6617 gen_helper_mtc0_config5(cpu_env, arg); 6618 register_name = "Config5"; 6619 /* Stop translation as we may have switched the execution mode */ 6620 ctx->base.is_jmp = DISAS_STOP; 6621 break; 6622 /* 6,7 are implementation dependent */ 6623 case CP0_REG16__CONFIG6: 6624 /* ignored */ 6625 register_name = "Config6"; 6626 break; 6627 case CP0_REG16__CONFIG7: 6628 /* ignored */ 6629 register_name = "Config7"; 6630 break; 6631 default: 6632 register_name = "Invalid config selector"; 6633 goto cp0_unimplemented; 6634 } 6635 break; 6636 case CP0_REGISTER_17: 6637 switch (sel) { 6638 case CP0_REG17__LLADDR: 6639 gen_helper_mtc0_lladdr(cpu_env, arg); 6640 register_name = "LLAddr"; 6641 break; 6642 case CP0_REG17__MAAR: 6643 CP0_CHECK(ctx->mrp); 6644 gen_helper_mtc0_maar(cpu_env, arg); 6645 register_name = "MAAR"; 6646 break; 6647 case CP0_REG17__MAARI: 6648 CP0_CHECK(ctx->mrp); 6649 gen_helper_mtc0_maari(cpu_env, arg); 6650 register_name = "MAARI"; 6651 break; 6652 default: 6653 goto cp0_unimplemented; 6654 } 6655 break; 6656 case CP0_REGISTER_18: 6657 switch (sel) { 6658 case CP0_REG18__WATCHLO0: 6659 case CP0_REG18__WATCHLO1: 6660 case CP0_REG18__WATCHLO2: 6661 case CP0_REG18__WATCHLO3: 6662 case CP0_REG18__WATCHLO4: 6663 case CP0_REG18__WATCHLO5: 6664 case CP0_REG18__WATCHLO6: 6665 case CP0_REG18__WATCHLO7: 6666 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 6667 gen_helper_0e1i(mtc0_watchlo, arg, sel); 6668 register_name = "WatchLo"; 6669 break; 6670 default: 6671 goto cp0_unimplemented; 6672 } 6673 break; 6674 case CP0_REGISTER_19: 6675 switch (sel) { 6676 case CP0_REG19__WATCHHI0: 6677 case CP0_REG19__WATCHHI1: 6678 case CP0_REG19__WATCHHI2: 6679 case CP0_REG19__WATCHHI3: 6680 case CP0_REG19__WATCHHI4: 6681 case CP0_REG19__WATCHHI5: 6682 case CP0_REG19__WATCHHI6: 6683 case CP0_REG19__WATCHHI7: 6684 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 6685 gen_helper_0e1i(mtc0_watchhi, arg, sel); 6686 register_name = "WatchHi"; 6687 break; 6688 default: 6689 goto cp0_unimplemented; 6690 } 6691 break; 6692 case CP0_REGISTER_20: 6693 switch (sel) { 6694 case CP0_REG20__XCONTEXT: 6695 #if defined(TARGET_MIPS64) 6696 check_insn(ctx, ISA_MIPS3); 6697 gen_helper_mtc0_xcontext(cpu_env, arg); 6698 register_name = "XContext"; 6699 break; 6700 #endif 6701 default: 6702 goto cp0_unimplemented; 6703 } 6704 break; 6705 case CP0_REGISTER_21: 6706 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 6707 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 6708 switch (sel) { 6709 case 0: 6710 gen_helper_mtc0_framemask(cpu_env, arg); 6711 register_name = "Framemask"; 6712 break; 6713 default: 6714 goto cp0_unimplemented; 6715 } 6716 break; 6717 case CP0_REGISTER_22: 6718 /* ignored */ 6719 register_name = "Diagnostic"; /* implementation dependent */ 6720 break; 6721 case CP0_REGISTER_23: 6722 switch (sel) { 6723 case CP0_REG23__DEBUG: 6724 gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */ 6725 /* DISAS_STOP isn't good enough here, hflags may have changed. */ 6726 gen_save_pc(ctx->base.pc_next + 4); 6727 ctx->base.is_jmp = DISAS_EXIT; 6728 register_name = "Debug"; 6729 break; 6730 case CP0_REG23__TRACECONTROL: 6731 /* PDtrace support */ 6732 /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */ 6733 register_name = "TraceControl"; 6734 /* Stop translation as we may have switched the execution mode */ 6735 ctx->base.is_jmp = DISAS_STOP; 6736 goto cp0_unimplemented; 6737 case CP0_REG23__TRACECONTROL2: 6738 /* PDtrace support */ 6739 /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */ 6740 register_name = "TraceControl2"; 6741 /* Stop translation as we may have switched the execution mode */ 6742 ctx->base.is_jmp = DISAS_STOP; 6743 goto cp0_unimplemented; 6744 case CP0_REG23__USERTRACEDATA1: 6745 /* Stop translation as we may have switched the execution mode */ 6746 ctx->base.is_jmp = DISAS_STOP; 6747 /* PDtrace support */ 6748 /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/ 6749 register_name = "UserTraceData"; 6750 /* Stop translation as we may have switched the execution mode */ 6751 ctx->base.is_jmp = DISAS_STOP; 6752 goto cp0_unimplemented; 6753 case CP0_REG23__TRACEIBPC: 6754 /* PDtrace support */ 6755 /* gen_helper_mtc0_traceibpc(cpu_env, arg); */ 6756 /* Stop translation as we may have switched the execution mode */ 6757 ctx->base.is_jmp = DISAS_STOP; 6758 register_name = "TraceIBPC"; 6759 goto cp0_unimplemented; 6760 case CP0_REG23__TRACEDBPC: 6761 /* PDtrace support */ 6762 /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */ 6763 /* Stop translation as we may have switched the execution mode */ 6764 ctx->base.is_jmp = DISAS_STOP; 6765 register_name = "TraceDBPC"; 6766 goto cp0_unimplemented; 6767 default: 6768 goto cp0_unimplemented; 6769 } 6770 break; 6771 case CP0_REGISTER_24: 6772 switch (sel) { 6773 case CP0_REG24__DEPC: 6774 /* EJTAG support */ 6775 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC)); 6776 register_name = "DEPC"; 6777 break; 6778 default: 6779 goto cp0_unimplemented; 6780 } 6781 break; 6782 case CP0_REGISTER_25: 6783 switch (sel) { 6784 case CP0_REG25__PERFCTL0: 6785 gen_helper_mtc0_performance0(cpu_env, arg); 6786 register_name = "Performance0"; 6787 break; 6788 case CP0_REG25__PERFCNT0: 6789 /* gen_helper_mtc0_performance1(arg); */ 6790 register_name = "Performance1"; 6791 goto cp0_unimplemented; 6792 case CP0_REG25__PERFCTL1: 6793 /* gen_helper_mtc0_performance2(arg); */ 6794 register_name = "Performance2"; 6795 goto cp0_unimplemented; 6796 case CP0_REG25__PERFCNT1: 6797 /* gen_helper_mtc0_performance3(arg); */ 6798 register_name = "Performance3"; 6799 goto cp0_unimplemented; 6800 case CP0_REG25__PERFCTL2: 6801 /* gen_helper_mtc0_performance4(arg); */ 6802 register_name = "Performance4"; 6803 goto cp0_unimplemented; 6804 case CP0_REG25__PERFCNT2: 6805 /* gen_helper_mtc0_performance5(arg); */ 6806 register_name = "Performance5"; 6807 goto cp0_unimplemented; 6808 case CP0_REG25__PERFCTL3: 6809 /* gen_helper_mtc0_performance6(arg); */ 6810 register_name = "Performance6"; 6811 goto cp0_unimplemented; 6812 case CP0_REG25__PERFCNT3: 6813 /* gen_helper_mtc0_performance7(arg); */ 6814 register_name = "Performance7"; 6815 goto cp0_unimplemented; 6816 default: 6817 goto cp0_unimplemented; 6818 } 6819 break; 6820 case CP0_REGISTER_26: 6821 switch (sel) { 6822 case CP0_REG26__ERRCTL: 6823 gen_helper_mtc0_errctl(cpu_env, arg); 6824 ctx->base.is_jmp = DISAS_STOP; 6825 register_name = "ErrCtl"; 6826 break; 6827 default: 6828 goto cp0_unimplemented; 6829 } 6830 break; 6831 case CP0_REGISTER_27: 6832 switch (sel) { 6833 case CP0_REG27__CACHERR: 6834 /* ignored */ 6835 register_name = "CacheErr"; 6836 break; 6837 default: 6838 goto cp0_unimplemented; 6839 } 6840 break; 6841 case CP0_REGISTER_28: 6842 switch (sel) { 6843 case CP0_REG28__TAGLO: 6844 case CP0_REG28__TAGLO1: 6845 case CP0_REG28__TAGLO2: 6846 case CP0_REG28__TAGLO3: 6847 gen_helper_mtc0_taglo(cpu_env, arg); 6848 register_name = "TagLo"; 6849 break; 6850 case CP0_REG28__DATALO: 6851 case CP0_REG28__DATALO1: 6852 case CP0_REG28__DATALO2: 6853 case CP0_REG28__DATALO3: 6854 gen_helper_mtc0_datalo(cpu_env, arg); 6855 register_name = "DataLo"; 6856 break; 6857 default: 6858 goto cp0_unimplemented; 6859 } 6860 break; 6861 case CP0_REGISTER_29: 6862 switch (sel) { 6863 case CP0_REG29__TAGHI: 6864 case CP0_REG29__TAGHI1: 6865 case CP0_REG29__TAGHI2: 6866 case CP0_REG29__TAGHI3: 6867 gen_helper_mtc0_taghi(cpu_env, arg); 6868 register_name = "TagHi"; 6869 break; 6870 case CP0_REG29__DATAHI: 6871 case CP0_REG29__DATAHI1: 6872 case CP0_REG29__DATAHI2: 6873 case CP0_REG29__DATAHI3: 6874 gen_helper_mtc0_datahi(cpu_env, arg); 6875 register_name = "DataHi"; 6876 break; 6877 default: 6878 register_name = "invalid sel"; 6879 goto cp0_unimplemented; 6880 } 6881 break; 6882 case CP0_REGISTER_30: 6883 switch (sel) { 6884 case CP0_REG30__ERROREPC: 6885 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); 6886 register_name = "ErrorEPC"; 6887 break; 6888 default: 6889 goto cp0_unimplemented; 6890 } 6891 break; 6892 case CP0_REGISTER_31: 6893 switch (sel) { 6894 case CP0_REG31__DESAVE: 6895 /* EJTAG support */ 6896 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); 6897 register_name = "DESAVE"; 6898 break; 6899 case CP0_REG31__KSCRATCH1: 6900 case CP0_REG31__KSCRATCH2: 6901 case CP0_REG31__KSCRATCH3: 6902 case CP0_REG31__KSCRATCH4: 6903 case CP0_REG31__KSCRATCH5: 6904 case CP0_REG31__KSCRATCH6: 6905 CP0_CHECK(ctx->kscrexist & (1 << sel)); 6906 tcg_gen_st_tl(arg, cpu_env, 6907 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); 6908 register_name = "KScratch"; 6909 break; 6910 default: 6911 goto cp0_unimplemented; 6912 } 6913 break; 6914 default: 6915 goto cp0_unimplemented; 6916 } 6917 trace_mips_translate_c0("mtc0", register_name, reg, sel); 6918 6919 /* For simplicity assume that all writes can cause interrupts. */ 6920 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 6921 /* 6922 * DISAS_STOP isn't sufficient, we need to ensure we break out of 6923 * translated code to check for pending interrupts. 6924 */ 6925 gen_save_pc(ctx->base.pc_next + 4); 6926 ctx->base.is_jmp = DISAS_EXIT; 6927 } 6928 return; 6929 6930 cp0_unimplemented: 6931 qemu_log_mask(LOG_UNIMP, "mtc0 %s (reg %d sel %d)\n", 6932 register_name, reg, sel); 6933 } 6934 6935 #if defined(TARGET_MIPS64) 6936 static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) 6937 { 6938 const char *register_name = "invalid"; 6939 6940 if (sel != 0) { 6941 check_insn(ctx, ISA_MIPS_R1); 6942 } 6943 6944 switch (reg) { 6945 case CP0_REGISTER_00: 6946 switch (sel) { 6947 case CP0_REG00__INDEX: 6948 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index)); 6949 register_name = "Index"; 6950 break; 6951 case CP0_REG00__MVPCONTROL: 6952 CP0_CHECK(ctx->insn_flags & ASE_MT); 6953 gen_helper_mfc0_mvpcontrol(arg, cpu_env); 6954 register_name = "MVPControl"; 6955 break; 6956 case CP0_REG00__MVPCONF0: 6957 CP0_CHECK(ctx->insn_flags & ASE_MT); 6958 gen_helper_mfc0_mvpconf0(arg, cpu_env); 6959 register_name = "MVPConf0"; 6960 break; 6961 case CP0_REG00__MVPCONF1: 6962 CP0_CHECK(ctx->insn_flags & ASE_MT); 6963 gen_helper_mfc0_mvpconf1(arg, cpu_env); 6964 register_name = "MVPConf1"; 6965 break; 6966 case CP0_REG00__VPCONTROL: 6967 CP0_CHECK(ctx->vp); 6968 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl)); 6969 register_name = "VPControl"; 6970 break; 6971 default: 6972 goto cp0_unimplemented; 6973 } 6974 break; 6975 case CP0_REGISTER_01: 6976 switch (sel) { 6977 case CP0_REG01__RANDOM: 6978 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 6979 gen_helper_mfc0_random(arg, cpu_env); 6980 register_name = "Random"; 6981 break; 6982 case CP0_REG01__VPECONTROL: 6983 CP0_CHECK(ctx->insn_flags & ASE_MT); 6984 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl)); 6985 register_name = "VPEControl"; 6986 break; 6987 case CP0_REG01__VPECONF0: 6988 CP0_CHECK(ctx->insn_flags & ASE_MT); 6989 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0)); 6990 register_name = "VPEConf0"; 6991 break; 6992 case CP0_REG01__VPECONF1: 6993 CP0_CHECK(ctx->insn_flags & ASE_MT); 6994 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1)); 6995 register_name = "VPEConf1"; 6996 break; 6997 case CP0_REG01__YQMASK: 6998 CP0_CHECK(ctx->insn_flags & ASE_MT); 6999 tcg_gen_ld_tl(arg, cpu_env, 7000 offsetof(CPUMIPSState, CP0_YQMask)); 7001 register_name = "YQMask"; 7002 break; 7003 case CP0_REG01__VPESCHEDULE: 7004 CP0_CHECK(ctx->insn_flags & ASE_MT); 7005 tcg_gen_ld_tl(arg, cpu_env, 7006 offsetof(CPUMIPSState, CP0_VPESchedule)); 7007 register_name = "VPESchedule"; 7008 break; 7009 case CP0_REG01__VPESCHEFBACK: 7010 CP0_CHECK(ctx->insn_flags & ASE_MT); 7011 tcg_gen_ld_tl(arg, cpu_env, 7012 offsetof(CPUMIPSState, CP0_VPEScheFBack)); 7013 register_name = "VPEScheFBack"; 7014 break; 7015 case CP0_REG01__VPEOPT: 7016 CP0_CHECK(ctx->insn_flags & ASE_MT); 7017 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt)); 7018 register_name = "VPEOpt"; 7019 break; 7020 default: 7021 goto cp0_unimplemented; 7022 } 7023 break; 7024 case CP0_REGISTER_02: 7025 switch (sel) { 7026 case CP0_REG02__ENTRYLO0: 7027 tcg_gen_ld_tl(arg, cpu_env, 7028 offsetof(CPUMIPSState, CP0_EntryLo0)); 7029 register_name = "EntryLo0"; 7030 break; 7031 case CP0_REG02__TCSTATUS: 7032 CP0_CHECK(ctx->insn_flags & ASE_MT); 7033 gen_helper_mfc0_tcstatus(arg, cpu_env); 7034 register_name = "TCStatus"; 7035 break; 7036 case CP0_REG02__TCBIND: 7037 CP0_CHECK(ctx->insn_flags & ASE_MT); 7038 gen_helper_mfc0_tcbind(arg, cpu_env); 7039 register_name = "TCBind"; 7040 break; 7041 case CP0_REG02__TCRESTART: 7042 CP0_CHECK(ctx->insn_flags & ASE_MT); 7043 gen_helper_dmfc0_tcrestart(arg, cpu_env); 7044 register_name = "TCRestart"; 7045 break; 7046 case CP0_REG02__TCHALT: 7047 CP0_CHECK(ctx->insn_flags & ASE_MT); 7048 gen_helper_dmfc0_tchalt(arg, cpu_env); 7049 register_name = "TCHalt"; 7050 break; 7051 case CP0_REG02__TCCONTEXT: 7052 CP0_CHECK(ctx->insn_flags & ASE_MT); 7053 gen_helper_dmfc0_tccontext(arg, cpu_env); 7054 register_name = "TCContext"; 7055 break; 7056 case CP0_REG02__TCSCHEDULE: 7057 CP0_CHECK(ctx->insn_flags & ASE_MT); 7058 gen_helper_dmfc0_tcschedule(arg, cpu_env); 7059 register_name = "TCSchedule"; 7060 break; 7061 case CP0_REG02__TCSCHEFBACK: 7062 CP0_CHECK(ctx->insn_flags & ASE_MT); 7063 gen_helper_dmfc0_tcschefback(arg, cpu_env); 7064 register_name = "TCScheFBack"; 7065 break; 7066 default: 7067 goto cp0_unimplemented; 7068 } 7069 break; 7070 case CP0_REGISTER_03: 7071 switch (sel) { 7072 case CP0_REG03__ENTRYLO1: 7073 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1)); 7074 register_name = "EntryLo1"; 7075 break; 7076 case CP0_REG03__GLOBALNUM: 7077 CP0_CHECK(ctx->vp); 7078 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber)); 7079 register_name = "GlobalNumber"; 7080 break; 7081 default: 7082 goto cp0_unimplemented; 7083 } 7084 break; 7085 case CP0_REGISTER_04: 7086 switch (sel) { 7087 case CP0_REG04__CONTEXT: 7088 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context)); 7089 register_name = "Context"; 7090 break; 7091 case CP0_REG04__CONTEXTCONFIG: 7092 /* SmartMIPS ASE */ 7093 /* gen_helper_dmfc0_contextconfig(arg); */ 7094 register_name = "ContextConfig"; 7095 goto cp0_unimplemented; 7096 case CP0_REG04__USERLOCAL: 7097 CP0_CHECK(ctx->ulri); 7098 tcg_gen_ld_tl(arg, cpu_env, 7099 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 7100 register_name = "UserLocal"; 7101 break; 7102 case CP0_REG04__MMID: 7103 CP0_CHECK(ctx->mi); 7104 gen_helper_mtc0_memorymapid(cpu_env, arg); 7105 register_name = "MMID"; 7106 break; 7107 default: 7108 goto cp0_unimplemented; 7109 } 7110 break; 7111 case CP0_REGISTER_05: 7112 switch (sel) { 7113 case CP0_REG05__PAGEMASK: 7114 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask)); 7115 register_name = "PageMask"; 7116 break; 7117 case CP0_REG05__PAGEGRAIN: 7118 check_insn(ctx, ISA_MIPS_R2); 7119 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); 7120 register_name = "PageGrain"; 7121 break; 7122 case CP0_REG05__SEGCTL0: 7123 CP0_CHECK(ctx->sc); 7124 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0)); 7125 register_name = "SegCtl0"; 7126 break; 7127 case CP0_REG05__SEGCTL1: 7128 CP0_CHECK(ctx->sc); 7129 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1)); 7130 register_name = "SegCtl1"; 7131 break; 7132 case CP0_REG05__SEGCTL2: 7133 CP0_CHECK(ctx->sc); 7134 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2)); 7135 register_name = "SegCtl2"; 7136 break; 7137 case CP0_REG05__PWBASE: 7138 check_pw(ctx); 7139 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase)); 7140 register_name = "PWBase"; 7141 break; 7142 case CP0_REG05__PWFIELD: 7143 check_pw(ctx); 7144 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField)); 7145 register_name = "PWField"; 7146 break; 7147 case CP0_REG05__PWSIZE: 7148 check_pw(ctx); 7149 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize)); 7150 register_name = "PWSize"; 7151 break; 7152 default: 7153 goto cp0_unimplemented; 7154 } 7155 break; 7156 case CP0_REGISTER_06: 7157 switch (sel) { 7158 case CP0_REG06__WIRED: 7159 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired)); 7160 register_name = "Wired"; 7161 break; 7162 case CP0_REG06__SRSCONF0: 7163 check_insn(ctx, ISA_MIPS_R2); 7164 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); 7165 register_name = "SRSConf0"; 7166 break; 7167 case CP0_REG06__SRSCONF1: 7168 check_insn(ctx, ISA_MIPS_R2); 7169 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); 7170 register_name = "SRSConf1"; 7171 break; 7172 case CP0_REG06__SRSCONF2: 7173 check_insn(ctx, ISA_MIPS_R2); 7174 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); 7175 register_name = "SRSConf2"; 7176 break; 7177 case CP0_REG06__SRSCONF3: 7178 check_insn(ctx, ISA_MIPS_R2); 7179 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); 7180 register_name = "SRSConf3"; 7181 break; 7182 case CP0_REG06__SRSCONF4: 7183 check_insn(ctx, ISA_MIPS_R2); 7184 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); 7185 register_name = "SRSConf4"; 7186 break; 7187 case CP0_REG06__PWCTL: 7188 check_pw(ctx); 7189 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl)); 7190 register_name = "PWCtl"; 7191 break; 7192 default: 7193 goto cp0_unimplemented; 7194 } 7195 break; 7196 case CP0_REGISTER_07: 7197 switch (sel) { 7198 case CP0_REG07__HWRENA: 7199 check_insn(ctx, ISA_MIPS_R2); 7200 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); 7201 register_name = "HWREna"; 7202 break; 7203 default: 7204 goto cp0_unimplemented; 7205 } 7206 break; 7207 case CP0_REGISTER_08: 7208 switch (sel) { 7209 case CP0_REG08__BADVADDR: 7210 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); 7211 register_name = "BadVAddr"; 7212 break; 7213 case CP0_REG08__BADINSTR: 7214 CP0_CHECK(ctx->bi); 7215 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr)); 7216 register_name = "BadInstr"; 7217 break; 7218 case CP0_REG08__BADINSTRP: 7219 CP0_CHECK(ctx->bp); 7220 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP)); 7221 register_name = "BadInstrP"; 7222 break; 7223 case CP0_REG08__BADINSTRX: 7224 CP0_CHECK(ctx->bi); 7225 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX)); 7226 tcg_gen_andi_tl(arg, arg, ~0xffff); 7227 register_name = "BadInstrX"; 7228 break; 7229 default: 7230 goto cp0_unimplemented; 7231 } 7232 break; 7233 case CP0_REGISTER_09: 7234 switch (sel) { 7235 case CP0_REG09__COUNT: 7236 /* Mark as an IO operation because we read the time. */ 7237 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 7238 gen_io_start(); 7239 } 7240 gen_helper_mfc0_count(arg, cpu_env); 7241 /* 7242 * Break the TB to be able to take timer interrupts immediately 7243 * after reading count. DISAS_STOP isn't sufficient, we need to 7244 * ensure we break completely out of translated code. 7245 */ 7246 gen_save_pc(ctx->base.pc_next + 4); 7247 ctx->base.is_jmp = DISAS_EXIT; 7248 register_name = "Count"; 7249 break; 7250 case CP0_REG09__SAARI: 7251 CP0_CHECK(ctx->saar); 7252 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); 7253 register_name = "SAARI"; 7254 break; 7255 case CP0_REG09__SAAR: 7256 CP0_CHECK(ctx->saar); 7257 gen_helper_dmfc0_saar(arg, cpu_env); 7258 register_name = "SAAR"; 7259 break; 7260 default: 7261 goto cp0_unimplemented; 7262 } 7263 break; 7264 case CP0_REGISTER_10: 7265 switch (sel) { 7266 case CP0_REG10__ENTRYHI: 7267 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi)); 7268 register_name = "EntryHi"; 7269 break; 7270 default: 7271 goto cp0_unimplemented; 7272 } 7273 break; 7274 case CP0_REGISTER_11: 7275 switch (sel) { 7276 case CP0_REG11__COMPARE: 7277 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare)); 7278 register_name = "Compare"; 7279 break; 7280 /* 6,7 are implementation dependent */ 7281 default: 7282 goto cp0_unimplemented; 7283 } 7284 break; 7285 case CP0_REGISTER_12: 7286 switch (sel) { 7287 case CP0_REG12__STATUS: 7288 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status)); 7289 register_name = "Status"; 7290 break; 7291 case CP0_REG12__INTCTL: 7292 check_insn(ctx, ISA_MIPS_R2); 7293 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); 7294 register_name = "IntCtl"; 7295 break; 7296 case CP0_REG12__SRSCTL: 7297 check_insn(ctx, ISA_MIPS_R2); 7298 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); 7299 register_name = "SRSCtl"; 7300 break; 7301 case CP0_REG12__SRSMAP: 7302 check_insn(ctx, ISA_MIPS_R2); 7303 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); 7304 register_name = "SRSMap"; 7305 break; 7306 default: 7307 goto cp0_unimplemented; 7308 } 7309 break; 7310 case CP0_REGISTER_13: 7311 switch (sel) { 7312 case CP0_REG13__CAUSE: 7313 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause)); 7314 register_name = "Cause"; 7315 break; 7316 default: 7317 goto cp0_unimplemented; 7318 } 7319 break; 7320 case CP0_REGISTER_14: 7321 switch (sel) { 7322 case CP0_REG14__EPC: 7323 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC)); 7324 register_name = "EPC"; 7325 break; 7326 default: 7327 goto cp0_unimplemented; 7328 } 7329 break; 7330 case CP0_REGISTER_15: 7331 switch (sel) { 7332 case CP0_REG15__PRID: 7333 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid)); 7334 register_name = "PRid"; 7335 break; 7336 case CP0_REG15__EBASE: 7337 check_insn(ctx, ISA_MIPS_R2); 7338 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); 7339 register_name = "EBase"; 7340 break; 7341 case CP0_REG15__CMGCRBASE: 7342 check_insn(ctx, ISA_MIPS_R2); 7343 CP0_CHECK(ctx->cmgcr); 7344 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase)); 7345 register_name = "CMGCRBase"; 7346 break; 7347 default: 7348 goto cp0_unimplemented; 7349 } 7350 break; 7351 case CP0_REGISTER_16: 7352 switch (sel) { 7353 case CP0_REG16__CONFIG: 7354 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0)); 7355 register_name = "Config"; 7356 break; 7357 case CP0_REG16__CONFIG1: 7358 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1)); 7359 register_name = "Config1"; 7360 break; 7361 case CP0_REG16__CONFIG2: 7362 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2)); 7363 register_name = "Config2"; 7364 break; 7365 case CP0_REG16__CONFIG3: 7366 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3)); 7367 register_name = "Config3"; 7368 break; 7369 case CP0_REG16__CONFIG4: 7370 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4)); 7371 register_name = "Config4"; 7372 break; 7373 case CP0_REG16__CONFIG5: 7374 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5)); 7375 register_name = "Config5"; 7376 break; 7377 /* 6,7 are implementation dependent */ 7378 case CP0_REG16__CONFIG6: 7379 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6)); 7380 register_name = "Config6"; 7381 break; 7382 case CP0_REG16__CONFIG7: 7383 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7)); 7384 register_name = "Config7"; 7385 break; 7386 default: 7387 goto cp0_unimplemented; 7388 } 7389 break; 7390 case CP0_REGISTER_17: 7391 switch (sel) { 7392 case CP0_REG17__LLADDR: 7393 gen_helper_dmfc0_lladdr(arg, cpu_env); 7394 register_name = "LLAddr"; 7395 break; 7396 case CP0_REG17__MAAR: 7397 CP0_CHECK(ctx->mrp); 7398 gen_helper_dmfc0_maar(arg, cpu_env); 7399 register_name = "MAAR"; 7400 break; 7401 case CP0_REG17__MAARI: 7402 CP0_CHECK(ctx->mrp); 7403 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI)); 7404 register_name = "MAARI"; 7405 break; 7406 default: 7407 goto cp0_unimplemented; 7408 } 7409 break; 7410 case CP0_REGISTER_18: 7411 switch (sel) { 7412 case CP0_REG18__WATCHLO0: 7413 case CP0_REG18__WATCHLO1: 7414 case CP0_REG18__WATCHLO2: 7415 case CP0_REG18__WATCHLO3: 7416 case CP0_REG18__WATCHLO4: 7417 case CP0_REG18__WATCHLO5: 7418 case CP0_REG18__WATCHLO6: 7419 case CP0_REG18__WATCHLO7: 7420 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 7421 gen_helper_1e0i(dmfc0_watchlo, arg, sel); 7422 register_name = "WatchLo"; 7423 break; 7424 default: 7425 goto cp0_unimplemented; 7426 } 7427 break; 7428 case CP0_REGISTER_19: 7429 switch (sel) { 7430 case CP0_REG19__WATCHHI0: 7431 case CP0_REG19__WATCHHI1: 7432 case CP0_REG19__WATCHHI2: 7433 case CP0_REG19__WATCHHI3: 7434 case CP0_REG19__WATCHHI4: 7435 case CP0_REG19__WATCHHI5: 7436 case CP0_REG19__WATCHHI6: 7437 case CP0_REG19__WATCHHI7: 7438 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 7439 gen_helper_1e0i(dmfc0_watchhi, arg, sel); 7440 register_name = "WatchHi"; 7441 break; 7442 default: 7443 goto cp0_unimplemented; 7444 } 7445 break; 7446 case CP0_REGISTER_20: 7447 switch (sel) { 7448 case CP0_REG20__XCONTEXT: 7449 check_insn(ctx, ISA_MIPS3); 7450 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext)); 7451 register_name = "XContext"; 7452 break; 7453 default: 7454 goto cp0_unimplemented; 7455 } 7456 break; 7457 case CP0_REGISTER_21: 7458 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 7459 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 7460 switch (sel) { 7461 case 0: 7462 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask)); 7463 register_name = "Framemask"; 7464 break; 7465 default: 7466 goto cp0_unimplemented; 7467 } 7468 break; 7469 case CP0_REGISTER_22: 7470 tcg_gen_movi_tl(arg, 0); /* unimplemented */ 7471 register_name = "'Diagnostic"; /* implementation dependent */ 7472 break; 7473 case CP0_REGISTER_23: 7474 switch (sel) { 7475 case CP0_REG23__DEBUG: 7476 gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */ 7477 register_name = "Debug"; 7478 break; 7479 case CP0_REG23__TRACECONTROL: 7480 /* PDtrace support */ 7481 /* gen_helper_dmfc0_tracecontrol(arg, cpu_env); */ 7482 register_name = "TraceControl"; 7483 goto cp0_unimplemented; 7484 case CP0_REG23__TRACECONTROL2: 7485 /* PDtrace support */ 7486 /* gen_helper_dmfc0_tracecontrol2(arg, cpu_env); */ 7487 register_name = "TraceControl2"; 7488 goto cp0_unimplemented; 7489 case CP0_REG23__USERTRACEDATA1: 7490 /* PDtrace support */ 7491 /* gen_helper_dmfc0_usertracedata1(arg, cpu_env);*/ 7492 register_name = "UserTraceData1"; 7493 goto cp0_unimplemented; 7494 case CP0_REG23__TRACEIBPC: 7495 /* PDtrace support */ 7496 /* gen_helper_dmfc0_traceibpc(arg, cpu_env); */ 7497 register_name = "TraceIBPC"; 7498 goto cp0_unimplemented; 7499 case CP0_REG23__TRACEDBPC: 7500 /* PDtrace support */ 7501 /* gen_helper_dmfc0_tracedbpc(arg, cpu_env); */ 7502 register_name = "TraceDBPC"; 7503 goto cp0_unimplemented; 7504 default: 7505 goto cp0_unimplemented; 7506 } 7507 break; 7508 case CP0_REGISTER_24: 7509 switch (sel) { 7510 case CP0_REG24__DEPC: 7511 /* EJTAG support */ 7512 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC)); 7513 register_name = "DEPC"; 7514 break; 7515 default: 7516 goto cp0_unimplemented; 7517 } 7518 break; 7519 case CP0_REGISTER_25: 7520 switch (sel) { 7521 case CP0_REG25__PERFCTL0: 7522 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0)); 7523 register_name = "Performance0"; 7524 break; 7525 case CP0_REG25__PERFCNT0: 7526 /* gen_helper_dmfc0_performance1(arg); */ 7527 register_name = "Performance1"; 7528 goto cp0_unimplemented; 7529 case CP0_REG25__PERFCTL1: 7530 /* gen_helper_dmfc0_performance2(arg); */ 7531 register_name = "Performance2"; 7532 goto cp0_unimplemented; 7533 case CP0_REG25__PERFCNT1: 7534 /* gen_helper_dmfc0_performance3(arg); */ 7535 register_name = "Performance3"; 7536 goto cp0_unimplemented; 7537 case CP0_REG25__PERFCTL2: 7538 /* gen_helper_dmfc0_performance4(arg); */ 7539 register_name = "Performance4"; 7540 goto cp0_unimplemented; 7541 case CP0_REG25__PERFCNT2: 7542 /* gen_helper_dmfc0_performance5(arg); */ 7543 register_name = "Performance5"; 7544 goto cp0_unimplemented; 7545 case CP0_REG25__PERFCTL3: 7546 /* gen_helper_dmfc0_performance6(arg); */ 7547 register_name = "Performance6"; 7548 goto cp0_unimplemented; 7549 case CP0_REG25__PERFCNT3: 7550 /* gen_helper_dmfc0_performance7(arg); */ 7551 register_name = "Performance7"; 7552 goto cp0_unimplemented; 7553 default: 7554 goto cp0_unimplemented; 7555 } 7556 break; 7557 case CP0_REGISTER_26: 7558 switch (sel) { 7559 case CP0_REG26__ERRCTL: 7560 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl)); 7561 register_name = "ErrCtl"; 7562 break; 7563 default: 7564 goto cp0_unimplemented; 7565 } 7566 break; 7567 case CP0_REGISTER_27: 7568 switch (sel) { 7569 /* ignored */ 7570 case CP0_REG27__CACHERR: 7571 tcg_gen_movi_tl(arg, 0); /* unimplemented */ 7572 register_name = "CacheErr"; 7573 break; 7574 default: 7575 goto cp0_unimplemented; 7576 } 7577 break; 7578 case CP0_REGISTER_28: 7579 switch (sel) { 7580 case CP0_REG28__TAGLO: 7581 case CP0_REG28__TAGLO1: 7582 case CP0_REG28__TAGLO2: 7583 case CP0_REG28__TAGLO3: 7584 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo)); 7585 register_name = "TagLo"; 7586 break; 7587 case CP0_REG28__DATALO: 7588 case CP0_REG28__DATALO1: 7589 case CP0_REG28__DATALO2: 7590 case CP0_REG28__DATALO3: 7591 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo)); 7592 register_name = "DataLo"; 7593 break; 7594 default: 7595 goto cp0_unimplemented; 7596 } 7597 break; 7598 case CP0_REGISTER_29: 7599 switch (sel) { 7600 case CP0_REG29__TAGHI: 7601 case CP0_REG29__TAGHI1: 7602 case CP0_REG29__TAGHI2: 7603 case CP0_REG29__TAGHI3: 7604 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi)); 7605 register_name = "TagHi"; 7606 break; 7607 case CP0_REG29__DATAHI: 7608 case CP0_REG29__DATAHI1: 7609 case CP0_REG29__DATAHI2: 7610 case CP0_REG29__DATAHI3: 7611 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi)); 7612 register_name = "DataHi"; 7613 break; 7614 default: 7615 goto cp0_unimplemented; 7616 } 7617 break; 7618 case CP0_REGISTER_30: 7619 switch (sel) { 7620 case CP0_REG30__ERROREPC: 7621 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); 7622 register_name = "ErrorEPC"; 7623 break; 7624 default: 7625 goto cp0_unimplemented; 7626 } 7627 break; 7628 case CP0_REGISTER_31: 7629 switch (sel) { 7630 case CP0_REG31__DESAVE: 7631 /* EJTAG support */ 7632 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); 7633 register_name = "DESAVE"; 7634 break; 7635 case CP0_REG31__KSCRATCH1: 7636 case CP0_REG31__KSCRATCH2: 7637 case CP0_REG31__KSCRATCH3: 7638 case CP0_REG31__KSCRATCH4: 7639 case CP0_REG31__KSCRATCH5: 7640 case CP0_REG31__KSCRATCH6: 7641 CP0_CHECK(ctx->kscrexist & (1 << sel)); 7642 tcg_gen_ld_tl(arg, cpu_env, 7643 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); 7644 register_name = "KScratch"; 7645 break; 7646 default: 7647 goto cp0_unimplemented; 7648 } 7649 break; 7650 default: 7651 goto cp0_unimplemented; 7652 } 7653 trace_mips_translate_c0("dmfc0", register_name, reg, sel); 7654 return; 7655 7656 cp0_unimplemented: 7657 qemu_log_mask(LOG_UNIMP, "dmfc0 %s (reg %d sel %d)\n", 7658 register_name, reg, sel); 7659 gen_mfc0_unimplemented(ctx, arg); 7660 } 7661 7662 static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) 7663 { 7664 const char *register_name = "invalid"; 7665 7666 if (sel != 0) { 7667 check_insn(ctx, ISA_MIPS_R1); 7668 } 7669 7670 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 7671 gen_io_start(); 7672 } 7673 7674 switch (reg) { 7675 case CP0_REGISTER_00: 7676 switch (sel) { 7677 case CP0_REG00__INDEX: 7678 gen_helper_mtc0_index(cpu_env, arg); 7679 register_name = "Index"; 7680 break; 7681 case CP0_REG00__MVPCONTROL: 7682 CP0_CHECK(ctx->insn_flags & ASE_MT); 7683 gen_helper_mtc0_mvpcontrol(cpu_env, arg); 7684 register_name = "MVPControl"; 7685 break; 7686 case CP0_REG00__MVPCONF0: 7687 CP0_CHECK(ctx->insn_flags & ASE_MT); 7688 /* ignored */ 7689 register_name = "MVPConf0"; 7690 break; 7691 case CP0_REG00__MVPCONF1: 7692 CP0_CHECK(ctx->insn_flags & ASE_MT); 7693 /* ignored */ 7694 register_name = "MVPConf1"; 7695 break; 7696 case CP0_REG00__VPCONTROL: 7697 CP0_CHECK(ctx->vp); 7698 /* ignored */ 7699 register_name = "VPControl"; 7700 break; 7701 default: 7702 goto cp0_unimplemented; 7703 } 7704 break; 7705 case CP0_REGISTER_01: 7706 switch (sel) { 7707 case CP0_REG01__RANDOM: 7708 /* ignored */ 7709 register_name = "Random"; 7710 break; 7711 case CP0_REG01__VPECONTROL: 7712 CP0_CHECK(ctx->insn_flags & ASE_MT); 7713 gen_helper_mtc0_vpecontrol(cpu_env, arg); 7714 register_name = "VPEControl"; 7715 break; 7716 case CP0_REG01__VPECONF0: 7717 CP0_CHECK(ctx->insn_flags & ASE_MT); 7718 gen_helper_mtc0_vpeconf0(cpu_env, arg); 7719 register_name = "VPEConf0"; 7720 break; 7721 case CP0_REG01__VPECONF1: 7722 CP0_CHECK(ctx->insn_flags & ASE_MT); 7723 gen_helper_mtc0_vpeconf1(cpu_env, arg); 7724 register_name = "VPEConf1"; 7725 break; 7726 case CP0_REG01__YQMASK: 7727 CP0_CHECK(ctx->insn_flags & ASE_MT); 7728 gen_helper_mtc0_yqmask(cpu_env, arg); 7729 register_name = "YQMask"; 7730 break; 7731 case CP0_REG01__VPESCHEDULE: 7732 CP0_CHECK(ctx->insn_flags & ASE_MT); 7733 tcg_gen_st_tl(arg, cpu_env, 7734 offsetof(CPUMIPSState, CP0_VPESchedule)); 7735 register_name = "VPESchedule"; 7736 break; 7737 case CP0_REG01__VPESCHEFBACK: 7738 CP0_CHECK(ctx->insn_flags & ASE_MT); 7739 tcg_gen_st_tl(arg, cpu_env, 7740 offsetof(CPUMIPSState, CP0_VPEScheFBack)); 7741 register_name = "VPEScheFBack"; 7742 break; 7743 case CP0_REG01__VPEOPT: 7744 CP0_CHECK(ctx->insn_flags & ASE_MT); 7745 gen_helper_mtc0_vpeopt(cpu_env, arg); 7746 register_name = "VPEOpt"; 7747 break; 7748 default: 7749 goto cp0_unimplemented; 7750 } 7751 break; 7752 case CP0_REGISTER_02: 7753 switch (sel) { 7754 case CP0_REG02__ENTRYLO0: 7755 gen_helper_dmtc0_entrylo0(cpu_env, arg); 7756 register_name = "EntryLo0"; 7757 break; 7758 case CP0_REG02__TCSTATUS: 7759 CP0_CHECK(ctx->insn_flags & ASE_MT); 7760 gen_helper_mtc0_tcstatus(cpu_env, arg); 7761 register_name = "TCStatus"; 7762 break; 7763 case CP0_REG02__TCBIND: 7764 CP0_CHECK(ctx->insn_flags & ASE_MT); 7765 gen_helper_mtc0_tcbind(cpu_env, arg); 7766 register_name = "TCBind"; 7767 break; 7768 case CP0_REG02__TCRESTART: 7769 CP0_CHECK(ctx->insn_flags & ASE_MT); 7770 gen_helper_mtc0_tcrestart(cpu_env, arg); 7771 register_name = "TCRestart"; 7772 break; 7773 case CP0_REG02__TCHALT: 7774 CP0_CHECK(ctx->insn_flags & ASE_MT); 7775 gen_helper_mtc0_tchalt(cpu_env, arg); 7776 register_name = "TCHalt"; 7777 break; 7778 case CP0_REG02__TCCONTEXT: 7779 CP0_CHECK(ctx->insn_flags & ASE_MT); 7780 gen_helper_mtc0_tccontext(cpu_env, arg); 7781 register_name = "TCContext"; 7782 break; 7783 case CP0_REG02__TCSCHEDULE: 7784 CP0_CHECK(ctx->insn_flags & ASE_MT); 7785 gen_helper_mtc0_tcschedule(cpu_env, arg); 7786 register_name = "TCSchedule"; 7787 break; 7788 case CP0_REG02__TCSCHEFBACK: 7789 CP0_CHECK(ctx->insn_flags & ASE_MT); 7790 gen_helper_mtc0_tcschefback(cpu_env, arg); 7791 register_name = "TCScheFBack"; 7792 break; 7793 default: 7794 goto cp0_unimplemented; 7795 } 7796 break; 7797 case CP0_REGISTER_03: 7798 switch (sel) { 7799 case CP0_REG03__ENTRYLO1: 7800 gen_helper_dmtc0_entrylo1(cpu_env, arg); 7801 register_name = "EntryLo1"; 7802 break; 7803 case CP0_REG03__GLOBALNUM: 7804 CP0_CHECK(ctx->vp); 7805 /* ignored */ 7806 register_name = "GlobalNumber"; 7807 break; 7808 default: 7809 goto cp0_unimplemented; 7810 } 7811 break; 7812 case CP0_REGISTER_04: 7813 switch (sel) { 7814 case CP0_REG04__CONTEXT: 7815 gen_helper_mtc0_context(cpu_env, arg); 7816 register_name = "Context"; 7817 break; 7818 case CP0_REG04__CONTEXTCONFIG: 7819 /* SmartMIPS ASE */ 7820 /* gen_helper_dmtc0_contextconfig(arg); */ 7821 register_name = "ContextConfig"; 7822 goto cp0_unimplemented; 7823 case CP0_REG04__USERLOCAL: 7824 CP0_CHECK(ctx->ulri); 7825 tcg_gen_st_tl(arg, cpu_env, 7826 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 7827 register_name = "UserLocal"; 7828 break; 7829 case CP0_REG04__MMID: 7830 CP0_CHECK(ctx->mi); 7831 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MemoryMapID)); 7832 register_name = "MMID"; 7833 break; 7834 default: 7835 goto cp0_unimplemented; 7836 } 7837 break; 7838 case CP0_REGISTER_05: 7839 switch (sel) { 7840 case CP0_REG05__PAGEMASK: 7841 gen_helper_mtc0_pagemask(cpu_env, arg); 7842 register_name = "PageMask"; 7843 break; 7844 case CP0_REG05__PAGEGRAIN: 7845 check_insn(ctx, ISA_MIPS_R2); 7846 gen_helper_mtc0_pagegrain(cpu_env, arg); 7847 register_name = "PageGrain"; 7848 break; 7849 case CP0_REG05__SEGCTL0: 7850 CP0_CHECK(ctx->sc); 7851 gen_helper_mtc0_segctl0(cpu_env, arg); 7852 register_name = "SegCtl0"; 7853 break; 7854 case CP0_REG05__SEGCTL1: 7855 CP0_CHECK(ctx->sc); 7856 gen_helper_mtc0_segctl1(cpu_env, arg); 7857 register_name = "SegCtl1"; 7858 break; 7859 case CP0_REG05__SEGCTL2: 7860 CP0_CHECK(ctx->sc); 7861 gen_helper_mtc0_segctl2(cpu_env, arg); 7862 register_name = "SegCtl2"; 7863 break; 7864 case CP0_REG05__PWBASE: 7865 check_pw(ctx); 7866 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase)); 7867 register_name = "PWBase"; 7868 break; 7869 case CP0_REG05__PWFIELD: 7870 check_pw(ctx); 7871 gen_helper_mtc0_pwfield(cpu_env, arg); 7872 register_name = "PWField"; 7873 break; 7874 case CP0_REG05__PWSIZE: 7875 check_pw(ctx); 7876 gen_helper_mtc0_pwsize(cpu_env, arg); 7877 register_name = "PWSize"; 7878 break; 7879 default: 7880 goto cp0_unimplemented; 7881 } 7882 break; 7883 case CP0_REGISTER_06: 7884 switch (sel) { 7885 case CP0_REG06__WIRED: 7886 gen_helper_mtc0_wired(cpu_env, arg); 7887 register_name = "Wired"; 7888 break; 7889 case CP0_REG06__SRSCONF0: 7890 check_insn(ctx, ISA_MIPS_R2); 7891 gen_helper_mtc0_srsconf0(cpu_env, arg); 7892 register_name = "SRSConf0"; 7893 break; 7894 case CP0_REG06__SRSCONF1: 7895 check_insn(ctx, ISA_MIPS_R2); 7896 gen_helper_mtc0_srsconf1(cpu_env, arg); 7897 register_name = "SRSConf1"; 7898 break; 7899 case CP0_REG06__SRSCONF2: 7900 check_insn(ctx, ISA_MIPS_R2); 7901 gen_helper_mtc0_srsconf2(cpu_env, arg); 7902 register_name = "SRSConf2"; 7903 break; 7904 case CP0_REG06__SRSCONF3: 7905 check_insn(ctx, ISA_MIPS_R2); 7906 gen_helper_mtc0_srsconf3(cpu_env, arg); 7907 register_name = "SRSConf3"; 7908 break; 7909 case CP0_REG06__SRSCONF4: 7910 check_insn(ctx, ISA_MIPS_R2); 7911 gen_helper_mtc0_srsconf4(cpu_env, arg); 7912 register_name = "SRSConf4"; 7913 break; 7914 case CP0_REG06__PWCTL: 7915 check_pw(ctx); 7916 gen_helper_mtc0_pwctl(cpu_env, arg); 7917 register_name = "PWCtl"; 7918 break; 7919 default: 7920 goto cp0_unimplemented; 7921 } 7922 break; 7923 case CP0_REGISTER_07: 7924 switch (sel) { 7925 case CP0_REG07__HWRENA: 7926 check_insn(ctx, ISA_MIPS_R2); 7927 gen_helper_mtc0_hwrena(cpu_env, arg); 7928 ctx->base.is_jmp = DISAS_STOP; 7929 register_name = "HWREna"; 7930 break; 7931 default: 7932 goto cp0_unimplemented; 7933 } 7934 break; 7935 case CP0_REGISTER_08: 7936 switch (sel) { 7937 case CP0_REG08__BADVADDR: 7938 /* ignored */ 7939 register_name = "BadVAddr"; 7940 break; 7941 case CP0_REG08__BADINSTR: 7942 /* ignored */ 7943 register_name = "BadInstr"; 7944 break; 7945 case CP0_REG08__BADINSTRP: 7946 /* ignored */ 7947 register_name = "BadInstrP"; 7948 break; 7949 case CP0_REG08__BADINSTRX: 7950 /* ignored */ 7951 register_name = "BadInstrX"; 7952 break; 7953 default: 7954 goto cp0_unimplemented; 7955 } 7956 break; 7957 case CP0_REGISTER_09: 7958 switch (sel) { 7959 case CP0_REG09__COUNT: 7960 gen_helper_mtc0_count(cpu_env, arg); 7961 register_name = "Count"; 7962 break; 7963 case CP0_REG09__SAARI: 7964 CP0_CHECK(ctx->saar); 7965 gen_helper_mtc0_saari(cpu_env, arg); 7966 register_name = "SAARI"; 7967 break; 7968 case CP0_REG09__SAAR: 7969 CP0_CHECK(ctx->saar); 7970 gen_helper_mtc0_saar(cpu_env, arg); 7971 register_name = "SAAR"; 7972 break; 7973 default: 7974 goto cp0_unimplemented; 7975 } 7976 /* Stop translation as we may have switched the execution mode */ 7977 ctx->base.is_jmp = DISAS_STOP; 7978 break; 7979 case CP0_REGISTER_10: 7980 switch (sel) { 7981 case CP0_REG10__ENTRYHI: 7982 gen_helper_mtc0_entryhi(cpu_env, arg); 7983 register_name = "EntryHi"; 7984 break; 7985 default: 7986 goto cp0_unimplemented; 7987 } 7988 break; 7989 case CP0_REGISTER_11: 7990 switch (sel) { 7991 case CP0_REG11__COMPARE: 7992 gen_helper_mtc0_compare(cpu_env, arg); 7993 register_name = "Compare"; 7994 break; 7995 /* 6,7 are implementation dependent */ 7996 default: 7997 goto cp0_unimplemented; 7998 } 7999 /* Stop translation as we may have switched the execution mode */ 8000 ctx->base.is_jmp = DISAS_STOP; 8001 break; 8002 case CP0_REGISTER_12: 8003 switch (sel) { 8004 case CP0_REG12__STATUS: 8005 save_cpu_state(ctx, 1); 8006 gen_helper_mtc0_status(cpu_env, arg); 8007 /* DISAS_STOP isn't good enough here, hflags may have changed. */ 8008 gen_save_pc(ctx->base.pc_next + 4); 8009 ctx->base.is_jmp = DISAS_EXIT; 8010 register_name = "Status"; 8011 break; 8012 case CP0_REG12__INTCTL: 8013 check_insn(ctx, ISA_MIPS_R2); 8014 gen_helper_mtc0_intctl(cpu_env, arg); 8015 /* Stop translation as we may have switched the execution mode */ 8016 ctx->base.is_jmp = DISAS_STOP; 8017 register_name = "IntCtl"; 8018 break; 8019 case CP0_REG12__SRSCTL: 8020 check_insn(ctx, ISA_MIPS_R2); 8021 gen_helper_mtc0_srsctl(cpu_env, arg); 8022 /* Stop translation as we may have switched the execution mode */ 8023 ctx->base.is_jmp = DISAS_STOP; 8024 register_name = "SRSCtl"; 8025 break; 8026 case CP0_REG12__SRSMAP: 8027 check_insn(ctx, ISA_MIPS_R2); 8028 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); 8029 /* Stop translation as we may have switched the execution mode */ 8030 ctx->base.is_jmp = DISAS_STOP; 8031 register_name = "SRSMap"; 8032 break; 8033 default: 8034 goto cp0_unimplemented; 8035 } 8036 break; 8037 case CP0_REGISTER_13: 8038 switch (sel) { 8039 case CP0_REG13__CAUSE: 8040 save_cpu_state(ctx, 1); 8041 gen_helper_mtc0_cause(cpu_env, arg); 8042 /* 8043 * Stop translation as we may have triggered an interrupt. 8044 * DISAS_STOP isn't sufficient, we need to ensure we break out of 8045 * translated code to check for pending interrupts. 8046 */ 8047 gen_save_pc(ctx->base.pc_next + 4); 8048 ctx->base.is_jmp = DISAS_EXIT; 8049 register_name = "Cause"; 8050 break; 8051 default: 8052 goto cp0_unimplemented; 8053 } 8054 break; 8055 case CP0_REGISTER_14: 8056 switch (sel) { 8057 case CP0_REG14__EPC: 8058 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC)); 8059 register_name = "EPC"; 8060 break; 8061 default: 8062 goto cp0_unimplemented; 8063 } 8064 break; 8065 case CP0_REGISTER_15: 8066 switch (sel) { 8067 case CP0_REG15__PRID: 8068 /* ignored */ 8069 register_name = "PRid"; 8070 break; 8071 case CP0_REG15__EBASE: 8072 check_insn(ctx, ISA_MIPS_R2); 8073 gen_helper_mtc0_ebase(cpu_env, arg); 8074 register_name = "EBase"; 8075 break; 8076 default: 8077 goto cp0_unimplemented; 8078 } 8079 break; 8080 case CP0_REGISTER_16: 8081 switch (sel) { 8082 case CP0_REG16__CONFIG: 8083 gen_helper_mtc0_config0(cpu_env, arg); 8084 register_name = "Config"; 8085 /* Stop translation as we may have switched the execution mode */ 8086 ctx->base.is_jmp = DISAS_STOP; 8087 break; 8088 case CP0_REG16__CONFIG1: 8089 /* ignored, read only */ 8090 register_name = "Config1"; 8091 break; 8092 case CP0_REG16__CONFIG2: 8093 gen_helper_mtc0_config2(cpu_env, arg); 8094 register_name = "Config2"; 8095 /* Stop translation as we may have switched the execution mode */ 8096 ctx->base.is_jmp = DISAS_STOP; 8097 break; 8098 case CP0_REG16__CONFIG3: 8099 gen_helper_mtc0_config3(cpu_env, arg); 8100 register_name = "Config3"; 8101 /* Stop translation as we may have switched the execution mode */ 8102 ctx->base.is_jmp = DISAS_STOP; 8103 break; 8104 case CP0_REG16__CONFIG4: 8105 /* currently ignored */ 8106 register_name = "Config4"; 8107 break; 8108 case CP0_REG16__CONFIG5: 8109 gen_helper_mtc0_config5(cpu_env, arg); 8110 register_name = "Config5"; 8111 /* Stop translation as we may have switched the execution mode */ 8112 ctx->base.is_jmp = DISAS_STOP; 8113 break; 8114 /* 6,7 are implementation dependent */ 8115 default: 8116 register_name = "Invalid config selector"; 8117 goto cp0_unimplemented; 8118 } 8119 break; 8120 case CP0_REGISTER_17: 8121 switch (sel) { 8122 case CP0_REG17__LLADDR: 8123 gen_helper_mtc0_lladdr(cpu_env, arg); 8124 register_name = "LLAddr"; 8125 break; 8126 case CP0_REG17__MAAR: 8127 CP0_CHECK(ctx->mrp); 8128 gen_helper_mtc0_maar(cpu_env, arg); 8129 register_name = "MAAR"; 8130 break; 8131 case CP0_REG17__MAARI: 8132 CP0_CHECK(ctx->mrp); 8133 gen_helper_mtc0_maari(cpu_env, arg); 8134 register_name = "MAARI"; 8135 break; 8136 default: 8137 goto cp0_unimplemented; 8138 } 8139 break; 8140 case CP0_REGISTER_18: 8141 switch (sel) { 8142 case CP0_REG18__WATCHLO0: 8143 case CP0_REG18__WATCHLO1: 8144 case CP0_REG18__WATCHLO2: 8145 case CP0_REG18__WATCHLO3: 8146 case CP0_REG18__WATCHLO4: 8147 case CP0_REG18__WATCHLO5: 8148 case CP0_REG18__WATCHLO6: 8149 case CP0_REG18__WATCHLO7: 8150 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 8151 gen_helper_0e1i(mtc0_watchlo, arg, sel); 8152 register_name = "WatchLo"; 8153 break; 8154 default: 8155 goto cp0_unimplemented; 8156 } 8157 break; 8158 case CP0_REGISTER_19: 8159 switch (sel) { 8160 case CP0_REG19__WATCHHI0: 8161 case CP0_REG19__WATCHHI1: 8162 case CP0_REG19__WATCHHI2: 8163 case CP0_REG19__WATCHHI3: 8164 case CP0_REG19__WATCHHI4: 8165 case CP0_REG19__WATCHHI5: 8166 case CP0_REG19__WATCHHI6: 8167 case CP0_REG19__WATCHHI7: 8168 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 8169 gen_helper_0e1i(mtc0_watchhi, arg, sel); 8170 register_name = "WatchHi"; 8171 break; 8172 default: 8173 goto cp0_unimplemented; 8174 } 8175 break; 8176 case CP0_REGISTER_20: 8177 switch (sel) { 8178 case CP0_REG20__XCONTEXT: 8179 check_insn(ctx, ISA_MIPS3); 8180 gen_helper_mtc0_xcontext(cpu_env, arg); 8181 register_name = "XContext"; 8182 break; 8183 default: 8184 goto cp0_unimplemented; 8185 } 8186 break; 8187 case CP0_REGISTER_21: 8188 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 8189 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 8190 switch (sel) { 8191 case 0: 8192 gen_helper_mtc0_framemask(cpu_env, arg); 8193 register_name = "Framemask"; 8194 break; 8195 default: 8196 goto cp0_unimplemented; 8197 } 8198 break; 8199 case CP0_REGISTER_22: 8200 /* ignored */ 8201 register_name = "Diagnostic"; /* implementation dependent */ 8202 break; 8203 case CP0_REGISTER_23: 8204 switch (sel) { 8205 case CP0_REG23__DEBUG: 8206 gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */ 8207 /* DISAS_STOP isn't good enough here, hflags may have changed. */ 8208 gen_save_pc(ctx->base.pc_next + 4); 8209 ctx->base.is_jmp = DISAS_EXIT; 8210 register_name = "Debug"; 8211 break; 8212 case CP0_REG23__TRACECONTROL: 8213 /* PDtrace support */ 8214 /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */ 8215 /* Stop translation as we may have switched the execution mode */ 8216 ctx->base.is_jmp = DISAS_STOP; 8217 register_name = "TraceControl"; 8218 goto cp0_unimplemented; 8219 case CP0_REG23__TRACECONTROL2: 8220 /* PDtrace support */ 8221 /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */ 8222 /* Stop translation as we may have switched the execution mode */ 8223 ctx->base.is_jmp = DISAS_STOP; 8224 register_name = "TraceControl2"; 8225 goto cp0_unimplemented; 8226 case CP0_REG23__USERTRACEDATA1: 8227 /* PDtrace support */ 8228 /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/ 8229 /* Stop translation as we may have switched the execution mode */ 8230 ctx->base.is_jmp = DISAS_STOP; 8231 register_name = "UserTraceData1"; 8232 goto cp0_unimplemented; 8233 case CP0_REG23__TRACEIBPC: 8234 /* PDtrace support */ 8235 /* gen_helper_mtc0_traceibpc(cpu_env, arg); */ 8236 /* Stop translation as we may have switched the execution mode */ 8237 ctx->base.is_jmp = DISAS_STOP; 8238 register_name = "TraceIBPC"; 8239 goto cp0_unimplemented; 8240 case CP0_REG23__TRACEDBPC: 8241 /* PDtrace support */ 8242 /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */ 8243 /* Stop translation as we may have switched the execution mode */ 8244 ctx->base.is_jmp = DISAS_STOP; 8245 register_name = "TraceDBPC"; 8246 goto cp0_unimplemented; 8247 default: 8248 goto cp0_unimplemented; 8249 } 8250 break; 8251 case CP0_REGISTER_24: 8252 switch (sel) { 8253 case CP0_REG24__DEPC: 8254 /* EJTAG support */ 8255 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC)); 8256 register_name = "DEPC"; 8257 break; 8258 default: 8259 goto cp0_unimplemented; 8260 } 8261 break; 8262 case CP0_REGISTER_25: 8263 switch (sel) { 8264 case CP0_REG25__PERFCTL0: 8265 gen_helper_mtc0_performance0(cpu_env, arg); 8266 register_name = "Performance0"; 8267 break; 8268 case CP0_REG25__PERFCNT0: 8269 /* gen_helper_mtc0_performance1(cpu_env, arg); */ 8270 register_name = "Performance1"; 8271 goto cp0_unimplemented; 8272 case CP0_REG25__PERFCTL1: 8273 /* gen_helper_mtc0_performance2(cpu_env, arg); */ 8274 register_name = "Performance2"; 8275 goto cp0_unimplemented; 8276 case CP0_REG25__PERFCNT1: 8277 /* gen_helper_mtc0_performance3(cpu_env, arg); */ 8278 register_name = "Performance3"; 8279 goto cp0_unimplemented; 8280 case CP0_REG25__PERFCTL2: 8281 /* gen_helper_mtc0_performance4(cpu_env, arg); */ 8282 register_name = "Performance4"; 8283 goto cp0_unimplemented; 8284 case CP0_REG25__PERFCNT2: 8285 /* gen_helper_mtc0_performance5(cpu_env, arg); */ 8286 register_name = "Performance5"; 8287 goto cp0_unimplemented; 8288 case CP0_REG25__PERFCTL3: 8289 /* gen_helper_mtc0_performance6(cpu_env, arg); */ 8290 register_name = "Performance6"; 8291 goto cp0_unimplemented; 8292 case CP0_REG25__PERFCNT3: 8293 /* gen_helper_mtc0_performance7(cpu_env, arg); */ 8294 register_name = "Performance7"; 8295 goto cp0_unimplemented; 8296 default: 8297 goto cp0_unimplemented; 8298 } 8299 break; 8300 case CP0_REGISTER_26: 8301 switch (sel) { 8302 case CP0_REG26__ERRCTL: 8303 gen_helper_mtc0_errctl(cpu_env, arg); 8304 ctx->base.is_jmp = DISAS_STOP; 8305 register_name = "ErrCtl"; 8306 break; 8307 default: 8308 goto cp0_unimplemented; 8309 } 8310 break; 8311 case CP0_REGISTER_27: 8312 switch (sel) { 8313 case CP0_REG27__CACHERR: 8314 /* ignored */ 8315 register_name = "CacheErr"; 8316 break; 8317 default: 8318 goto cp0_unimplemented; 8319 } 8320 break; 8321 case CP0_REGISTER_28: 8322 switch (sel) { 8323 case CP0_REG28__TAGLO: 8324 case CP0_REG28__TAGLO1: 8325 case CP0_REG28__TAGLO2: 8326 case CP0_REG28__TAGLO3: 8327 gen_helper_mtc0_taglo(cpu_env, arg); 8328 register_name = "TagLo"; 8329 break; 8330 case CP0_REG28__DATALO: 8331 case CP0_REG28__DATALO1: 8332 case CP0_REG28__DATALO2: 8333 case CP0_REG28__DATALO3: 8334 gen_helper_mtc0_datalo(cpu_env, arg); 8335 register_name = "DataLo"; 8336 break; 8337 default: 8338 goto cp0_unimplemented; 8339 } 8340 break; 8341 case CP0_REGISTER_29: 8342 switch (sel) { 8343 case CP0_REG29__TAGHI: 8344 case CP0_REG29__TAGHI1: 8345 case CP0_REG29__TAGHI2: 8346 case CP0_REG29__TAGHI3: 8347 gen_helper_mtc0_taghi(cpu_env, arg); 8348 register_name = "TagHi"; 8349 break; 8350 case CP0_REG29__DATAHI: 8351 case CP0_REG29__DATAHI1: 8352 case CP0_REG29__DATAHI2: 8353 case CP0_REG29__DATAHI3: 8354 gen_helper_mtc0_datahi(cpu_env, arg); 8355 register_name = "DataHi"; 8356 break; 8357 default: 8358 register_name = "invalid sel"; 8359 goto cp0_unimplemented; 8360 } 8361 break; 8362 case CP0_REGISTER_30: 8363 switch (sel) { 8364 case CP0_REG30__ERROREPC: 8365 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); 8366 register_name = "ErrorEPC"; 8367 break; 8368 default: 8369 goto cp0_unimplemented; 8370 } 8371 break; 8372 case CP0_REGISTER_31: 8373 switch (sel) { 8374 case CP0_REG31__DESAVE: 8375 /* EJTAG support */ 8376 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); 8377 register_name = "DESAVE"; 8378 break; 8379 case CP0_REG31__KSCRATCH1: 8380 case CP0_REG31__KSCRATCH2: 8381 case CP0_REG31__KSCRATCH3: 8382 case CP0_REG31__KSCRATCH4: 8383 case CP0_REG31__KSCRATCH5: 8384 case CP0_REG31__KSCRATCH6: 8385 CP0_CHECK(ctx->kscrexist & (1 << sel)); 8386 tcg_gen_st_tl(arg, cpu_env, 8387 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); 8388 register_name = "KScratch"; 8389 break; 8390 default: 8391 goto cp0_unimplemented; 8392 } 8393 break; 8394 default: 8395 goto cp0_unimplemented; 8396 } 8397 trace_mips_translate_c0("dmtc0", register_name, reg, sel); 8398 8399 /* For simplicity assume that all writes can cause interrupts. */ 8400 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 8401 /* 8402 * DISAS_STOP isn't sufficient, we need to ensure we break out of 8403 * translated code to check for pending interrupts. 8404 */ 8405 gen_save_pc(ctx->base.pc_next + 4); 8406 ctx->base.is_jmp = DISAS_EXIT; 8407 } 8408 return; 8409 8410 cp0_unimplemented: 8411 qemu_log_mask(LOG_UNIMP, "dmtc0 %s (reg %d sel %d)\n", 8412 register_name, reg, sel); 8413 } 8414 #endif /* TARGET_MIPS64 */ 8415 8416 static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, 8417 int u, int sel, int h) 8418 { 8419 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 8420 TCGv t0 = tcg_temp_new(); 8421 8422 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && 8423 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != 8424 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) { 8425 tcg_gen_movi_tl(t0, -1); 8426 } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > 8427 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) { 8428 tcg_gen_movi_tl(t0, -1); 8429 } else if (u == 0) { 8430 switch (rt) { 8431 case 1: 8432 switch (sel) { 8433 case 1: 8434 gen_helper_mftc0_vpecontrol(t0, cpu_env); 8435 break; 8436 case 2: 8437 gen_helper_mftc0_vpeconf0(t0, cpu_env); 8438 break; 8439 default: 8440 goto die; 8441 break; 8442 } 8443 break; 8444 case 2: 8445 switch (sel) { 8446 case 1: 8447 gen_helper_mftc0_tcstatus(t0, cpu_env); 8448 break; 8449 case 2: 8450 gen_helper_mftc0_tcbind(t0, cpu_env); 8451 break; 8452 case 3: 8453 gen_helper_mftc0_tcrestart(t0, cpu_env); 8454 break; 8455 case 4: 8456 gen_helper_mftc0_tchalt(t0, cpu_env); 8457 break; 8458 case 5: 8459 gen_helper_mftc0_tccontext(t0, cpu_env); 8460 break; 8461 case 6: 8462 gen_helper_mftc0_tcschedule(t0, cpu_env); 8463 break; 8464 case 7: 8465 gen_helper_mftc0_tcschefback(t0, cpu_env); 8466 break; 8467 default: 8468 gen_mfc0(ctx, t0, rt, sel); 8469 break; 8470 } 8471 break; 8472 case 10: 8473 switch (sel) { 8474 case 0: 8475 gen_helper_mftc0_entryhi(t0, cpu_env); 8476 break; 8477 default: 8478 gen_mfc0(ctx, t0, rt, sel); 8479 break; 8480 } 8481 break; 8482 case 12: 8483 switch (sel) { 8484 case 0: 8485 gen_helper_mftc0_status(t0, cpu_env); 8486 break; 8487 default: 8488 gen_mfc0(ctx, t0, rt, sel); 8489 break; 8490 } 8491 break; 8492 case 13: 8493 switch (sel) { 8494 case 0: 8495 gen_helper_mftc0_cause(t0, cpu_env); 8496 break; 8497 default: 8498 goto die; 8499 break; 8500 } 8501 break; 8502 case 14: 8503 switch (sel) { 8504 case 0: 8505 gen_helper_mftc0_epc(t0, cpu_env); 8506 break; 8507 default: 8508 goto die; 8509 break; 8510 } 8511 break; 8512 case 15: 8513 switch (sel) { 8514 case 1: 8515 gen_helper_mftc0_ebase(t0, cpu_env); 8516 break; 8517 default: 8518 goto die; 8519 break; 8520 } 8521 break; 8522 case 16: 8523 switch (sel) { 8524 case 0: 8525 case 1: 8526 case 2: 8527 case 3: 8528 case 4: 8529 case 5: 8530 case 6: 8531 case 7: 8532 gen_helper_mftc0_configx(t0, cpu_env, tcg_const_tl(sel)); 8533 break; 8534 default: 8535 goto die; 8536 break; 8537 } 8538 break; 8539 case 23: 8540 switch (sel) { 8541 case 0: 8542 gen_helper_mftc0_debug(t0, cpu_env); 8543 break; 8544 default: 8545 gen_mfc0(ctx, t0, rt, sel); 8546 break; 8547 } 8548 break; 8549 default: 8550 gen_mfc0(ctx, t0, rt, sel); 8551 } 8552 } else { 8553 switch (sel) { 8554 /* GPR registers. */ 8555 case 0: 8556 gen_helper_1e0i(mftgpr, t0, rt); 8557 break; 8558 /* Auxiliary CPU registers */ 8559 case 1: 8560 switch (rt) { 8561 case 0: 8562 gen_helper_1e0i(mftlo, t0, 0); 8563 break; 8564 case 1: 8565 gen_helper_1e0i(mfthi, t0, 0); 8566 break; 8567 case 2: 8568 gen_helper_1e0i(mftacx, t0, 0); 8569 break; 8570 case 4: 8571 gen_helper_1e0i(mftlo, t0, 1); 8572 break; 8573 case 5: 8574 gen_helper_1e0i(mfthi, t0, 1); 8575 break; 8576 case 6: 8577 gen_helper_1e0i(mftacx, t0, 1); 8578 break; 8579 case 8: 8580 gen_helper_1e0i(mftlo, t0, 2); 8581 break; 8582 case 9: 8583 gen_helper_1e0i(mfthi, t0, 2); 8584 break; 8585 case 10: 8586 gen_helper_1e0i(mftacx, t0, 2); 8587 break; 8588 case 12: 8589 gen_helper_1e0i(mftlo, t0, 3); 8590 break; 8591 case 13: 8592 gen_helper_1e0i(mfthi, t0, 3); 8593 break; 8594 case 14: 8595 gen_helper_1e0i(mftacx, t0, 3); 8596 break; 8597 case 16: 8598 gen_helper_mftdsp(t0, cpu_env); 8599 break; 8600 default: 8601 goto die; 8602 } 8603 break; 8604 /* Floating point (COP1). */ 8605 case 2: 8606 /* XXX: For now we support only a single FPU context. */ 8607 if (h == 0) { 8608 TCGv_i32 fp0 = tcg_temp_new_i32(); 8609 8610 gen_load_fpr32(ctx, fp0, rt); 8611 tcg_gen_ext_i32_tl(t0, fp0); 8612 } else { 8613 TCGv_i32 fp0 = tcg_temp_new_i32(); 8614 8615 gen_load_fpr32h(ctx, fp0, rt); 8616 tcg_gen_ext_i32_tl(t0, fp0); 8617 } 8618 break; 8619 case 3: 8620 /* XXX: For now we support only a single FPU context. */ 8621 gen_helper_1e0i(cfc1, t0, rt); 8622 break; 8623 /* COP2: Not implemented. */ 8624 case 4: 8625 case 5: 8626 /* fall through */ 8627 default: 8628 goto die; 8629 } 8630 } 8631 trace_mips_translate_tr("mftr", rt, u, sel, h); 8632 gen_store_gpr(t0, rd); 8633 return; 8634 8635 die: 8636 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h); 8637 gen_reserved_instruction(ctx); 8638 } 8639 8640 static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, 8641 int u, int sel, int h) 8642 { 8643 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 8644 TCGv t0 = tcg_temp_new(); 8645 8646 gen_load_gpr(t0, rt); 8647 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && 8648 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != 8649 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) { 8650 /* NOP */ 8651 ; 8652 } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > 8653 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) { 8654 /* NOP */ 8655 ; 8656 } else if (u == 0) { 8657 switch (rd) { 8658 case 1: 8659 switch (sel) { 8660 case 1: 8661 gen_helper_mttc0_vpecontrol(cpu_env, t0); 8662 break; 8663 case 2: 8664 gen_helper_mttc0_vpeconf0(cpu_env, t0); 8665 break; 8666 default: 8667 goto die; 8668 break; 8669 } 8670 break; 8671 case 2: 8672 switch (sel) { 8673 case 1: 8674 gen_helper_mttc0_tcstatus(cpu_env, t0); 8675 break; 8676 case 2: 8677 gen_helper_mttc0_tcbind(cpu_env, t0); 8678 break; 8679 case 3: 8680 gen_helper_mttc0_tcrestart(cpu_env, t0); 8681 break; 8682 case 4: 8683 gen_helper_mttc0_tchalt(cpu_env, t0); 8684 break; 8685 case 5: 8686 gen_helper_mttc0_tccontext(cpu_env, t0); 8687 break; 8688 case 6: 8689 gen_helper_mttc0_tcschedule(cpu_env, t0); 8690 break; 8691 case 7: 8692 gen_helper_mttc0_tcschefback(cpu_env, t0); 8693 break; 8694 default: 8695 gen_mtc0(ctx, t0, rd, sel); 8696 break; 8697 } 8698 break; 8699 case 10: 8700 switch (sel) { 8701 case 0: 8702 gen_helper_mttc0_entryhi(cpu_env, t0); 8703 break; 8704 default: 8705 gen_mtc0(ctx, t0, rd, sel); 8706 break; 8707 } 8708 break; 8709 case 12: 8710 switch (sel) { 8711 case 0: 8712 gen_helper_mttc0_status(cpu_env, t0); 8713 break; 8714 default: 8715 gen_mtc0(ctx, t0, rd, sel); 8716 break; 8717 } 8718 break; 8719 case 13: 8720 switch (sel) { 8721 case 0: 8722 gen_helper_mttc0_cause(cpu_env, t0); 8723 break; 8724 default: 8725 goto die; 8726 break; 8727 } 8728 break; 8729 case 15: 8730 switch (sel) { 8731 case 1: 8732 gen_helper_mttc0_ebase(cpu_env, t0); 8733 break; 8734 default: 8735 goto die; 8736 break; 8737 } 8738 break; 8739 case 23: 8740 switch (sel) { 8741 case 0: 8742 gen_helper_mttc0_debug(cpu_env, t0); 8743 break; 8744 default: 8745 gen_mtc0(ctx, t0, rd, sel); 8746 break; 8747 } 8748 break; 8749 default: 8750 gen_mtc0(ctx, t0, rd, sel); 8751 } 8752 } else { 8753 switch (sel) { 8754 /* GPR registers. */ 8755 case 0: 8756 gen_helper_0e1i(mttgpr, t0, rd); 8757 break; 8758 /* Auxiliary CPU registers */ 8759 case 1: 8760 switch (rd) { 8761 case 0: 8762 gen_helper_0e1i(mttlo, t0, 0); 8763 break; 8764 case 1: 8765 gen_helper_0e1i(mtthi, t0, 0); 8766 break; 8767 case 2: 8768 gen_helper_0e1i(mttacx, t0, 0); 8769 break; 8770 case 4: 8771 gen_helper_0e1i(mttlo, t0, 1); 8772 break; 8773 case 5: 8774 gen_helper_0e1i(mtthi, t0, 1); 8775 break; 8776 case 6: 8777 gen_helper_0e1i(mttacx, t0, 1); 8778 break; 8779 case 8: 8780 gen_helper_0e1i(mttlo, t0, 2); 8781 break; 8782 case 9: 8783 gen_helper_0e1i(mtthi, t0, 2); 8784 break; 8785 case 10: 8786 gen_helper_0e1i(mttacx, t0, 2); 8787 break; 8788 case 12: 8789 gen_helper_0e1i(mttlo, t0, 3); 8790 break; 8791 case 13: 8792 gen_helper_0e1i(mtthi, t0, 3); 8793 break; 8794 case 14: 8795 gen_helper_0e1i(mttacx, t0, 3); 8796 break; 8797 case 16: 8798 gen_helper_mttdsp(cpu_env, t0); 8799 break; 8800 default: 8801 goto die; 8802 } 8803 break; 8804 /* Floating point (COP1). */ 8805 case 2: 8806 /* XXX: For now we support only a single FPU context. */ 8807 if (h == 0) { 8808 TCGv_i32 fp0 = tcg_temp_new_i32(); 8809 8810 tcg_gen_trunc_tl_i32(fp0, t0); 8811 gen_store_fpr32(ctx, fp0, rd); 8812 } else { 8813 TCGv_i32 fp0 = tcg_temp_new_i32(); 8814 8815 tcg_gen_trunc_tl_i32(fp0, t0); 8816 gen_store_fpr32h(ctx, fp0, rd); 8817 } 8818 break; 8819 case 3: 8820 /* XXX: For now we support only a single FPU context. */ 8821 gen_helper_0e2i(ctc1, t0, tcg_constant_i32(rd), rt); 8822 /* Stop translation as we may have changed hflags */ 8823 ctx->base.is_jmp = DISAS_STOP; 8824 break; 8825 /* COP2: Not implemented. */ 8826 case 4: 8827 case 5: 8828 /* fall through */ 8829 default: 8830 goto die; 8831 } 8832 } 8833 trace_mips_translate_tr("mttr", rd, u, sel, h); 8834 return; 8835 8836 die: 8837 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h); 8838 gen_reserved_instruction(ctx); 8839 } 8840 8841 static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, 8842 int rt, int rd) 8843 { 8844 const char *opn = "ldst"; 8845 8846 check_cp0_enabled(ctx); 8847 switch (opc) { 8848 case OPC_MFC0: 8849 if (rt == 0) { 8850 /* Treat as NOP. */ 8851 return; 8852 } 8853 gen_mfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); 8854 opn = "mfc0"; 8855 break; 8856 case OPC_MTC0: 8857 { 8858 TCGv t0 = tcg_temp_new(); 8859 8860 gen_load_gpr(t0, rt); 8861 gen_mtc0(ctx, t0, rd, ctx->opcode & 0x7); 8862 } 8863 opn = "mtc0"; 8864 break; 8865 #if defined(TARGET_MIPS64) 8866 case OPC_DMFC0: 8867 check_insn(ctx, ISA_MIPS3); 8868 if (rt == 0) { 8869 /* Treat as NOP. */ 8870 return; 8871 } 8872 gen_dmfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); 8873 opn = "dmfc0"; 8874 break; 8875 case OPC_DMTC0: 8876 check_insn(ctx, ISA_MIPS3); 8877 { 8878 TCGv t0 = tcg_temp_new(); 8879 8880 gen_load_gpr(t0, rt); 8881 gen_dmtc0(ctx, t0, rd, ctx->opcode & 0x7); 8882 } 8883 opn = "dmtc0"; 8884 break; 8885 #endif 8886 case OPC_MFHC0: 8887 check_mvh(ctx); 8888 if (rt == 0) { 8889 /* Treat as NOP. */ 8890 return; 8891 } 8892 gen_mfhc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); 8893 opn = "mfhc0"; 8894 break; 8895 case OPC_MTHC0: 8896 check_mvh(ctx); 8897 { 8898 TCGv t0 = tcg_temp_new(); 8899 gen_load_gpr(t0, rt); 8900 gen_mthc0(ctx, t0, rd, ctx->opcode & 0x7); 8901 } 8902 opn = "mthc0"; 8903 break; 8904 case OPC_MFTR: 8905 check_cp0_enabled(ctx); 8906 if (rd == 0) { 8907 /* Treat as NOP. */ 8908 return; 8909 } 8910 gen_mftr(env, ctx, rt, rd, (ctx->opcode >> 5) & 1, 8911 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); 8912 opn = "mftr"; 8913 break; 8914 case OPC_MTTR: 8915 check_cp0_enabled(ctx); 8916 gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1, 8917 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); 8918 opn = "mttr"; 8919 break; 8920 case OPC_TLBWI: 8921 opn = "tlbwi"; 8922 if (!env->tlb->helper_tlbwi) { 8923 goto die; 8924 } 8925 gen_helper_tlbwi(cpu_env); 8926 break; 8927 case OPC_TLBINV: 8928 opn = "tlbinv"; 8929 if (ctx->ie >= 2) { 8930 if (!env->tlb->helper_tlbinv) { 8931 goto die; 8932 } 8933 gen_helper_tlbinv(cpu_env); 8934 } /* treat as nop if TLBINV not supported */ 8935 break; 8936 case OPC_TLBINVF: 8937 opn = "tlbinvf"; 8938 if (ctx->ie >= 2) { 8939 if (!env->tlb->helper_tlbinvf) { 8940 goto die; 8941 } 8942 gen_helper_tlbinvf(cpu_env); 8943 } /* treat as nop if TLBINV not supported */ 8944 break; 8945 case OPC_TLBWR: 8946 opn = "tlbwr"; 8947 if (!env->tlb->helper_tlbwr) { 8948 goto die; 8949 } 8950 gen_helper_tlbwr(cpu_env); 8951 break; 8952 case OPC_TLBP: 8953 opn = "tlbp"; 8954 if (!env->tlb->helper_tlbp) { 8955 goto die; 8956 } 8957 gen_helper_tlbp(cpu_env); 8958 break; 8959 case OPC_TLBR: 8960 opn = "tlbr"; 8961 if (!env->tlb->helper_tlbr) { 8962 goto die; 8963 } 8964 gen_helper_tlbr(cpu_env); 8965 break; 8966 case OPC_ERET: /* OPC_ERETNC */ 8967 if ((ctx->insn_flags & ISA_MIPS_R6) && 8968 (ctx->hflags & MIPS_HFLAG_BMASK)) { 8969 goto die; 8970 } else { 8971 int bit_shift = (ctx->hflags & MIPS_HFLAG_M16) ? 16 : 6; 8972 if (ctx->opcode & (1 << bit_shift)) { 8973 /* OPC_ERETNC */ 8974 opn = "eretnc"; 8975 check_insn(ctx, ISA_MIPS_R5); 8976 gen_helper_eretnc(cpu_env); 8977 } else { 8978 /* OPC_ERET */ 8979 opn = "eret"; 8980 check_insn(ctx, ISA_MIPS2); 8981 gen_helper_eret(cpu_env); 8982 } 8983 ctx->base.is_jmp = DISAS_EXIT; 8984 } 8985 break; 8986 case OPC_DERET: 8987 opn = "deret"; 8988 check_insn(ctx, ISA_MIPS_R1); 8989 if ((ctx->insn_flags & ISA_MIPS_R6) && 8990 (ctx->hflags & MIPS_HFLAG_BMASK)) { 8991 goto die; 8992 } 8993 if (!(ctx->hflags & MIPS_HFLAG_DM)) { 8994 MIPS_INVAL(opn); 8995 gen_reserved_instruction(ctx); 8996 } else { 8997 gen_helper_deret(cpu_env); 8998 ctx->base.is_jmp = DISAS_EXIT; 8999 } 9000 break; 9001 case OPC_WAIT: 9002 opn = "wait"; 9003 check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); 9004 if ((ctx->insn_flags & ISA_MIPS_R6) && 9005 (ctx->hflags & MIPS_HFLAG_BMASK)) { 9006 goto die; 9007 } 9008 /* If we get an exception, we want to restart at next instruction */ 9009 ctx->base.pc_next += 4; 9010 save_cpu_state(ctx, 1); 9011 ctx->base.pc_next -= 4; 9012 gen_helper_wait(cpu_env); 9013 ctx->base.is_jmp = DISAS_NORETURN; 9014 break; 9015 default: 9016 die: 9017 MIPS_INVAL(opn); 9018 gen_reserved_instruction(ctx); 9019 return; 9020 } 9021 (void)opn; /* avoid a compiler warning */ 9022 } 9023 #endif /* !CONFIG_USER_ONLY */ 9024 9025 /* CP1 Branches (before delay slot) */ 9026 static void gen_compute_branch1(DisasContext *ctx, uint32_t op, 9027 int32_t cc, int32_t offset) 9028 { 9029 target_ulong btarget; 9030 TCGv_i32 t0 = tcg_temp_new_i32(); 9031 9032 if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { 9033 gen_reserved_instruction(ctx); 9034 return; 9035 } 9036 9037 if (cc != 0) { 9038 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); 9039 } 9040 9041 btarget = ctx->base.pc_next + 4 + offset; 9042 9043 switch (op) { 9044 case OPC_BC1F: 9045 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 9046 tcg_gen_not_i32(t0, t0); 9047 tcg_gen_andi_i32(t0, t0, 1); 9048 tcg_gen_extu_i32_tl(bcond, t0); 9049 goto not_likely; 9050 case OPC_BC1FL: 9051 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 9052 tcg_gen_not_i32(t0, t0); 9053 tcg_gen_andi_i32(t0, t0, 1); 9054 tcg_gen_extu_i32_tl(bcond, t0); 9055 goto likely; 9056 case OPC_BC1T: 9057 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 9058 tcg_gen_andi_i32(t0, t0, 1); 9059 tcg_gen_extu_i32_tl(bcond, t0); 9060 goto not_likely; 9061 case OPC_BC1TL: 9062 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 9063 tcg_gen_andi_i32(t0, t0, 1); 9064 tcg_gen_extu_i32_tl(bcond, t0); 9065 likely: 9066 ctx->hflags |= MIPS_HFLAG_BL; 9067 break; 9068 case OPC_BC1FANY2: 9069 { 9070 TCGv_i32 t1 = tcg_temp_new_i32(); 9071 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 9072 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); 9073 tcg_gen_nand_i32(t0, t0, t1); 9074 tcg_gen_andi_i32(t0, t0, 1); 9075 tcg_gen_extu_i32_tl(bcond, t0); 9076 } 9077 goto not_likely; 9078 case OPC_BC1TANY2: 9079 { 9080 TCGv_i32 t1 = tcg_temp_new_i32(); 9081 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 9082 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); 9083 tcg_gen_or_i32(t0, t0, t1); 9084 tcg_gen_andi_i32(t0, t0, 1); 9085 tcg_gen_extu_i32_tl(bcond, t0); 9086 } 9087 goto not_likely; 9088 case OPC_BC1FANY4: 9089 { 9090 TCGv_i32 t1 = tcg_temp_new_i32(); 9091 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 9092 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); 9093 tcg_gen_and_i32(t0, t0, t1); 9094 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 2)); 9095 tcg_gen_and_i32(t0, t0, t1); 9096 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3)); 9097 tcg_gen_nand_i32(t0, t0, t1); 9098 tcg_gen_andi_i32(t0, t0, 1); 9099 tcg_gen_extu_i32_tl(bcond, t0); 9100 } 9101 goto not_likely; 9102 case OPC_BC1TANY4: 9103 { 9104 TCGv_i32 t1 = tcg_temp_new_i32(); 9105 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 9106 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); 9107 tcg_gen_or_i32(t0, t0, t1); 9108 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 2)); 9109 tcg_gen_or_i32(t0, t0, t1); 9110 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3)); 9111 tcg_gen_or_i32(t0, t0, t1); 9112 tcg_gen_andi_i32(t0, t0, 1); 9113 tcg_gen_extu_i32_tl(bcond, t0); 9114 } 9115 not_likely: 9116 ctx->hflags |= MIPS_HFLAG_BC; 9117 break; 9118 default: 9119 MIPS_INVAL("cp1 cond branch"); 9120 gen_reserved_instruction(ctx); 9121 return; 9122 } 9123 ctx->btarget = btarget; 9124 ctx->hflags |= MIPS_HFLAG_BDS32; 9125 } 9126 9127 /* R6 CP1 Branches */ 9128 static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op, 9129 int32_t ft, int32_t offset, 9130 int delayslot_size) 9131 { 9132 target_ulong btarget; 9133 TCGv_i64 t0 = tcg_temp_new_i64(); 9134 9135 if (ctx->hflags & MIPS_HFLAG_BMASK) { 9136 #ifdef MIPS_DEBUG_DISAS 9137 LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx 9138 "\n", ctx->base.pc_next); 9139 #endif 9140 gen_reserved_instruction(ctx); 9141 return; 9142 } 9143 9144 gen_load_fpr64(ctx, t0, ft); 9145 tcg_gen_andi_i64(t0, t0, 1); 9146 9147 btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 9148 9149 switch (op) { 9150 case OPC_BC1EQZ: 9151 tcg_gen_xori_i64(t0, t0, 1); 9152 ctx->hflags |= MIPS_HFLAG_BC; 9153 break; 9154 case OPC_BC1NEZ: 9155 /* t0 already set */ 9156 ctx->hflags |= MIPS_HFLAG_BC; 9157 break; 9158 default: 9159 MIPS_INVAL("cp1 cond branch"); 9160 gen_reserved_instruction(ctx); 9161 return; 9162 } 9163 9164 tcg_gen_trunc_i64_tl(bcond, t0); 9165 9166 ctx->btarget = btarget; 9167 9168 switch (delayslot_size) { 9169 case 2: 9170 ctx->hflags |= MIPS_HFLAG_BDS16; 9171 break; 9172 case 4: 9173 ctx->hflags |= MIPS_HFLAG_BDS32; 9174 break; 9175 } 9176 } 9177 9178 /* Coprocessor 1 (FPU) */ 9179 9180 #define FOP(func, fmt) (((fmt) << 21) | (func)) 9181 9182 enum fopcode { 9183 OPC_ADD_S = FOP(0, FMT_S), 9184 OPC_SUB_S = FOP(1, FMT_S), 9185 OPC_MUL_S = FOP(2, FMT_S), 9186 OPC_DIV_S = FOP(3, FMT_S), 9187 OPC_SQRT_S = FOP(4, FMT_S), 9188 OPC_ABS_S = FOP(5, FMT_S), 9189 OPC_MOV_S = FOP(6, FMT_S), 9190 OPC_NEG_S = FOP(7, FMT_S), 9191 OPC_ROUND_L_S = FOP(8, FMT_S), 9192 OPC_TRUNC_L_S = FOP(9, FMT_S), 9193 OPC_CEIL_L_S = FOP(10, FMT_S), 9194 OPC_FLOOR_L_S = FOP(11, FMT_S), 9195 OPC_ROUND_W_S = FOP(12, FMT_S), 9196 OPC_TRUNC_W_S = FOP(13, FMT_S), 9197 OPC_CEIL_W_S = FOP(14, FMT_S), 9198 OPC_FLOOR_W_S = FOP(15, FMT_S), 9199 OPC_SEL_S = FOP(16, FMT_S), 9200 OPC_MOVCF_S = FOP(17, FMT_S), 9201 OPC_MOVZ_S = FOP(18, FMT_S), 9202 OPC_MOVN_S = FOP(19, FMT_S), 9203 OPC_SELEQZ_S = FOP(20, FMT_S), 9204 OPC_RECIP_S = FOP(21, FMT_S), 9205 OPC_RSQRT_S = FOP(22, FMT_S), 9206 OPC_SELNEZ_S = FOP(23, FMT_S), 9207 OPC_MADDF_S = FOP(24, FMT_S), 9208 OPC_MSUBF_S = FOP(25, FMT_S), 9209 OPC_RINT_S = FOP(26, FMT_S), 9210 OPC_CLASS_S = FOP(27, FMT_S), 9211 OPC_MIN_S = FOP(28, FMT_S), 9212 OPC_RECIP2_S = FOP(28, FMT_S), 9213 OPC_MINA_S = FOP(29, FMT_S), 9214 OPC_RECIP1_S = FOP(29, FMT_S), 9215 OPC_MAX_S = FOP(30, FMT_S), 9216 OPC_RSQRT1_S = FOP(30, FMT_S), 9217 OPC_MAXA_S = FOP(31, FMT_S), 9218 OPC_RSQRT2_S = FOP(31, FMT_S), 9219 OPC_CVT_D_S = FOP(33, FMT_S), 9220 OPC_CVT_W_S = FOP(36, FMT_S), 9221 OPC_CVT_L_S = FOP(37, FMT_S), 9222 OPC_CVT_PS_S = FOP(38, FMT_S), 9223 OPC_CMP_F_S = FOP(48, FMT_S), 9224 OPC_CMP_UN_S = FOP(49, FMT_S), 9225 OPC_CMP_EQ_S = FOP(50, FMT_S), 9226 OPC_CMP_UEQ_S = FOP(51, FMT_S), 9227 OPC_CMP_OLT_S = FOP(52, FMT_S), 9228 OPC_CMP_ULT_S = FOP(53, FMT_S), 9229 OPC_CMP_OLE_S = FOP(54, FMT_S), 9230 OPC_CMP_ULE_S = FOP(55, FMT_S), 9231 OPC_CMP_SF_S = FOP(56, FMT_S), 9232 OPC_CMP_NGLE_S = FOP(57, FMT_S), 9233 OPC_CMP_SEQ_S = FOP(58, FMT_S), 9234 OPC_CMP_NGL_S = FOP(59, FMT_S), 9235 OPC_CMP_LT_S = FOP(60, FMT_S), 9236 OPC_CMP_NGE_S = FOP(61, FMT_S), 9237 OPC_CMP_LE_S = FOP(62, FMT_S), 9238 OPC_CMP_NGT_S = FOP(63, FMT_S), 9239 9240 OPC_ADD_D = FOP(0, FMT_D), 9241 OPC_SUB_D = FOP(1, FMT_D), 9242 OPC_MUL_D = FOP(2, FMT_D), 9243 OPC_DIV_D = FOP(3, FMT_D), 9244 OPC_SQRT_D = FOP(4, FMT_D), 9245 OPC_ABS_D = FOP(5, FMT_D), 9246 OPC_MOV_D = FOP(6, FMT_D), 9247 OPC_NEG_D = FOP(7, FMT_D), 9248 OPC_ROUND_L_D = FOP(8, FMT_D), 9249 OPC_TRUNC_L_D = FOP(9, FMT_D), 9250 OPC_CEIL_L_D = FOP(10, FMT_D), 9251 OPC_FLOOR_L_D = FOP(11, FMT_D), 9252 OPC_ROUND_W_D = FOP(12, FMT_D), 9253 OPC_TRUNC_W_D = FOP(13, FMT_D), 9254 OPC_CEIL_W_D = FOP(14, FMT_D), 9255 OPC_FLOOR_W_D = FOP(15, FMT_D), 9256 OPC_SEL_D = FOP(16, FMT_D), 9257 OPC_MOVCF_D = FOP(17, FMT_D), 9258 OPC_MOVZ_D = FOP(18, FMT_D), 9259 OPC_MOVN_D = FOP(19, FMT_D), 9260 OPC_SELEQZ_D = FOP(20, FMT_D), 9261 OPC_RECIP_D = FOP(21, FMT_D), 9262 OPC_RSQRT_D = FOP(22, FMT_D), 9263 OPC_SELNEZ_D = FOP(23, FMT_D), 9264 OPC_MADDF_D = FOP(24, FMT_D), 9265 OPC_MSUBF_D = FOP(25, FMT_D), 9266 OPC_RINT_D = FOP(26, FMT_D), 9267 OPC_CLASS_D = FOP(27, FMT_D), 9268 OPC_MIN_D = FOP(28, FMT_D), 9269 OPC_RECIP2_D = FOP(28, FMT_D), 9270 OPC_MINA_D = FOP(29, FMT_D), 9271 OPC_RECIP1_D = FOP(29, FMT_D), 9272 OPC_MAX_D = FOP(30, FMT_D), 9273 OPC_RSQRT1_D = FOP(30, FMT_D), 9274 OPC_MAXA_D = FOP(31, FMT_D), 9275 OPC_RSQRT2_D = FOP(31, FMT_D), 9276 OPC_CVT_S_D = FOP(32, FMT_D), 9277 OPC_CVT_W_D = FOP(36, FMT_D), 9278 OPC_CVT_L_D = FOP(37, FMT_D), 9279 OPC_CMP_F_D = FOP(48, FMT_D), 9280 OPC_CMP_UN_D = FOP(49, FMT_D), 9281 OPC_CMP_EQ_D = FOP(50, FMT_D), 9282 OPC_CMP_UEQ_D = FOP(51, FMT_D), 9283 OPC_CMP_OLT_D = FOP(52, FMT_D), 9284 OPC_CMP_ULT_D = FOP(53, FMT_D), 9285 OPC_CMP_OLE_D = FOP(54, FMT_D), 9286 OPC_CMP_ULE_D = FOP(55, FMT_D), 9287 OPC_CMP_SF_D = FOP(56, FMT_D), 9288 OPC_CMP_NGLE_D = FOP(57, FMT_D), 9289 OPC_CMP_SEQ_D = FOP(58, FMT_D), 9290 OPC_CMP_NGL_D = FOP(59, FMT_D), 9291 OPC_CMP_LT_D = FOP(60, FMT_D), 9292 OPC_CMP_NGE_D = FOP(61, FMT_D), 9293 OPC_CMP_LE_D = FOP(62, FMT_D), 9294 OPC_CMP_NGT_D = FOP(63, FMT_D), 9295 9296 OPC_CVT_S_W = FOP(32, FMT_W), 9297 OPC_CVT_D_W = FOP(33, FMT_W), 9298 OPC_CVT_S_L = FOP(32, FMT_L), 9299 OPC_CVT_D_L = FOP(33, FMT_L), 9300 OPC_CVT_PS_PW = FOP(38, FMT_W), 9301 9302 OPC_ADD_PS = FOP(0, FMT_PS), 9303 OPC_SUB_PS = FOP(1, FMT_PS), 9304 OPC_MUL_PS = FOP(2, FMT_PS), 9305 OPC_DIV_PS = FOP(3, FMT_PS), 9306 OPC_ABS_PS = FOP(5, FMT_PS), 9307 OPC_MOV_PS = FOP(6, FMT_PS), 9308 OPC_NEG_PS = FOP(7, FMT_PS), 9309 OPC_MOVCF_PS = FOP(17, FMT_PS), 9310 OPC_MOVZ_PS = FOP(18, FMT_PS), 9311 OPC_MOVN_PS = FOP(19, FMT_PS), 9312 OPC_ADDR_PS = FOP(24, FMT_PS), 9313 OPC_MULR_PS = FOP(26, FMT_PS), 9314 OPC_RECIP2_PS = FOP(28, FMT_PS), 9315 OPC_RECIP1_PS = FOP(29, FMT_PS), 9316 OPC_RSQRT1_PS = FOP(30, FMT_PS), 9317 OPC_RSQRT2_PS = FOP(31, FMT_PS), 9318 9319 OPC_CVT_S_PU = FOP(32, FMT_PS), 9320 OPC_CVT_PW_PS = FOP(36, FMT_PS), 9321 OPC_CVT_S_PL = FOP(40, FMT_PS), 9322 OPC_PLL_PS = FOP(44, FMT_PS), 9323 OPC_PLU_PS = FOP(45, FMT_PS), 9324 OPC_PUL_PS = FOP(46, FMT_PS), 9325 OPC_PUU_PS = FOP(47, FMT_PS), 9326 OPC_CMP_F_PS = FOP(48, FMT_PS), 9327 OPC_CMP_UN_PS = FOP(49, FMT_PS), 9328 OPC_CMP_EQ_PS = FOP(50, FMT_PS), 9329 OPC_CMP_UEQ_PS = FOP(51, FMT_PS), 9330 OPC_CMP_OLT_PS = FOP(52, FMT_PS), 9331 OPC_CMP_ULT_PS = FOP(53, FMT_PS), 9332 OPC_CMP_OLE_PS = FOP(54, FMT_PS), 9333 OPC_CMP_ULE_PS = FOP(55, FMT_PS), 9334 OPC_CMP_SF_PS = FOP(56, FMT_PS), 9335 OPC_CMP_NGLE_PS = FOP(57, FMT_PS), 9336 OPC_CMP_SEQ_PS = FOP(58, FMT_PS), 9337 OPC_CMP_NGL_PS = FOP(59, FMT_PS), 9338 OPC_CMP_LT_PS = FOP(60, FMT_PS), 9339 OPC_CMP_NGE_PS = FOP(61, FMT_PS), 9340 OPC_CMP_LE_PS = FOP(62, FMT_PS), 9341 OPC_CMP_NGT_PS = FOP(63, FMT_PS), 9342 }; 9343 9344 enum r6_f_cmp_op { 9345 R6_OPC_CMP_AF_S = FOP(0, FMT_W), 9346 R6_OPC_CMP_UN_S = FOP(1, FMT_W), 9347 R6_OPC_CMP_EQ_S = FOP(2, FMT_W), 9348 R6_OPC_CMP_UEQ_S = FOP(3, FMT_W), 9349 R6_OPC_CMP_LT_S = FOP(4, FMT_W), 9350 R6_OPC_CMP_ULT_S = FOP(5, FMT_W), 9351 R6_OPC_CMP_LE_S = FOP(6, FMT_W), 9352 R6_OPC_CMP_ULE_S = FOP(7, FMT_W), 9353 R6_OPC_CMP_SAF_S = FOP(8, FMT_W), 9354 R6_OPC_CMP_SUN_S = FOP(9, FMT_W), 9355 R6_OPC_CMP_SEQ_S = FOP(10, FMT_W), 9356 R6_OPC_CMP_SEUQ_S = FOP(11, FMT_W), 9357 R6_OPC_CMP_SLT_S = FOP(12, FMT_W), 9358 R6_OPC_CMP_SULT_S = FOP(13, FMT_W), 9359 R6_OPC_CMP_SLE_S = FOP(14, FMT_W), 9360 R6_OPC_CMP_SULE_S = FOP(15, FMT_W), 9361 R6_OPC_CMP_OR_S = FOP(17, FMT_W), 9362 R6_OPC_CMP_UNE_S = FOP(18, FMT_W), 9363 R6_OPC_CMP_NE_S = FOP(19, FMT_W), 9364 R6_OPC_CMP_SOR_S = FOP(25, FMT_W), 9365 R6_OPC_CMP_SUNE_S = FOP(26, FMT_W), 9366 R6_OPC_CMP_SNE_S = FOP(27, FMT_W), 9367 9368 R6_OPC_CMP_AF_D = FOP(0, FMT_L), 9369 R6_OPC_CMP_UN_D = FOP(1, FMT_L), 9370 R6_OPC_CMP_EQ_D = FOP(2, FMT_L), 9371 R6_OPC_CMP_UEQ_D = FOP(3, FMT_L), 9372 R6_OPC_CMP_LT_D = FOP(4, FMT_L), 9373 R6_OPC_CMP_ULT_D = FOP(5, FMT_L), 9374 R6_OPC_CMP_LE_D = FOP(6, FMT_L), 9375 R6_OPC_CMP_ULE_D = FOP(7, FMT_L), 9376 R6_OPC_CMP_SAF_D = FOP(8, FMT_L), 9377 R6_OPC_CMP_SUN_D = FOP(9, FMT_L), 9378 R6_OPC_CMP_SEQ_D = FOP(10, FMT_L), 9379 R6_OPC_CMP_SEUQ_D = FOP(11, FMT_L), 9380 R6_OPC_CMP_SLT_D = FOP(12, FMT_L), 9381 R6_OPC_CMP_SULT_D = FOP(13, FMT_L), 9382 R6_OPC_CMP_SLE_D = FOP(14, FMT_L), 9383 R6_OPC_CMP_SULE_D = FOP(15, FMT_L), 9384 R6_OPC_CMP_OR_D = FOP(17, FMT_L), 9385 R6_OPC_CMP_UNE_D = FOP(18, FMT_L), 9386 R6_OPC_CMP_NE_D = FOP(19, FMT_L), 9387 R6_OPC_CMP_SOR_D = FOP(25, FMT_L), 9388 R6_OPC_CMP_SUNE_D = FOP(26, FMT_L), 9389 R6_OPC_CMP_SNE_D = FOP(27, FMT_L), 9390 }; 9391 9392 static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs) 9393 { 9394 TCGv t0 = tcg_temp_new(); 9395 9396 switch (opc) { 9397 case OPC_MFC1: 9398 { 9399 TCGv_i32 fp0 = tcg_temp_new_i32(); 9400 9401 gen_load_fpr32(ctx, fp0, fs); 9402 tcg_gen_ext_i32_tl(t0, fp0); 9403 } 9404 gen_store_gpr(t0, rt); 9405 break; 9406 case OPC_MTC1: 9407 gen_load_gpr(t0, rt); 9408 { 9409 TCGv_i32 fp0 = tcg_temp_new_i32(); 9410 9411 tcg_gen_trunc_tl_i32(fp0, t0); 9412 gen_store_fpr32(ctx, fp0, fs); 9413 } 9414 break; 9415 case OPC_CFC1: 9416 gen_helper_1e0i(cfc1, t0, fs); 9417 gen_store_gpr(t0, rt); 9418 break; 9419 case OPC_CTC1: 9420 gen_load_gpr(t0, rt); 9421 save_cpu_state(ctx, 0); 9422 gen_helper_0e2i(ctc1, t0, tcg_constant_i32(fs), rt); 9423 /* Stop translation as we may have changed hflags */ 9424 ctx->base.is_jmp = DISAS_STOP; 9425 break; 9426 #if defined(TARGET_MIPS64) 9427 case OPC_DMFC1: 9428 gen_load_fpr64(ctx, t0, fs); 9429 gen_store_gpr(t0, rt); 9430 break; 9431 case OPC_DMTC1: 9432 gen_load_gpr(t0, rt); 9433 gen_store_fpr64(ctx, t0, fs); 9434 break; 9435 #endif 9436 case OPC_MFHC1: 9437 { 9438 TCGv_i32 fp0 = tcg_temp_new_i32(); 9439 9440 gen_load_fpr32h(ctx, fp0, fs); 9441 tcg_gen_ext_i32_tl(t0, fp0); 9442 } 9443 gen_store_gpr(t0, rt); 9444 break; 9445 case OPC_MTHC1: 9446 gen_load_gpr(t0, rt); 9447 { 9448 TCGv_i32 fp0 = tcg_temp_new_i32(); 9449 9450 tcg_gen_trunc_tl_i32(fp0, t0); 9451 gen_store_fpr32h(ctx, fp0, fs); 9452 } 9453 break; 9454 default: 9455 MIPS_INVAL("cp1 move"); 9456 gen_reserved_instruction(ctx); 9457 return; 9458 } 9459 } 9460 9461 static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf) 9462 { 9463 TCGLabel *l1; 9464 TCGCond cond; 9465 TCGv_i32 t0; 9466 9467 if (rd == 0) { 9468 /* Treat as NOP. */ 9469 return; 9470 } 9471 9472 if (tf) { 9473 cond = TCG_COND_EQ; 9474 } else { 9475 cond = TCG_COND_NE; 9476 } 9477 9478 l1 = gen_new_label(); 9479 t0 = tcg_temp_new_i32(); 9480 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); 9481 tcg_gen_brcondi_i32(cond, t0, 0, l1); 9482 gen_load_gpr(cpu_gpr[rd], rs); 9483 gen_set_label(l1); 9484 } 9485 9486 static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc, 9487 int tf) 9488 { 9489 int cond; 9490 TCGv_i32 t0 = tcg_temp_new_i32(); 9491 TCGLabel *l1 = gen_new_label(); 9492 9493 if (tf) { 9494 cond = TCG_COND_EQ; 9495 } else { 9496 cond = TCG_COND_NE; 9497 } 9498 9499 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); 9500 tcg_gen_brcondi_i32(cond, t0, 0, l1); 9501 gen_load_fpr32(ctx, t0, fs); 9502 gen_store_fpr32(ctx, t0, fd); 9503 gen_set_label(l1); 9504 } 9505 9506 static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc, 9507 int tf) 9508 { 9509 int cond; 9510 TCGv_i32 t0 = tcg_temp_new_i32(); 9511 TCGv_i64 fp0; 9512 TCGLabel *l1 = gen_new_label(); 9513 9514 if (tf) { 9515 cond = TCG_COND_EQ; 9516 } else { 9517 cond = TCG_COND_NE; 9518 } 9519 9520 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); 9521 tcg_gen_brcondi_i32(cond, t0, 0, l1); 9522 fp0 = tcg_temp_new_i64(); 9523 gen_load_fpr64(ctx, fp0, fs); 9524 gen_store_fpr64(ctx, fp0, fd); 9525 gen_set_label(l1); 9526 } 9527 9528 static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd, 9529 int cc, int tf) 9530 { 9531 int cond; 9532 TCGv_i32 t0 = tcg_temp_new_i32(); 9533 TCGLabel *l1 = gen_new_label(); 9534 TCGLabel *l2 = gen_new_label(); 9535 9536 if (tf) { 9537 cond = TCG_COND_EQ; 9538 } else { 9539 cond = TCG_COND_NE; 9540 } 9541 9542 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); 9543 tcg_gen_brcondi_i32(cond, t0, 0, l1); 9544 gen_load_fpr32(ctx, t0, fs); 9545 gen_store_fpr32(ctx, t0, fd); 9546 gen_set_label(l1); 9547 9548 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc + 1)); 9549 tcg_gen_brcondi_i32(cond, t0, 0, l2); 9550 gen_load_fpr32h(ctx, t0, fs); 9551 gen_store_fpr32h(ctx, t0, fd); 9552 gen_set_label(l2); 9553 } 9554 9555 static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft, 9556 int fs) 9557 { 9558 TCGv_i32 t1 = tcg_const_i32(0); 9559 TCGv_i32 fp0 = tcg_temp_new_i32(); 9560 TCGv_i32 fp1 = tcg_temp_new_i32(); 9561 TCGv_i32 fp2 = tcg_temp_new_i32(); 9562 gen_load_fpr32(ctx, fp0, fd); 9563 gen_load_fpr32(ctx, fp1, ft); 9564 gen_load_fpr32(ctx, fp2, fs); 9565 9566 switch (op1) { 9567 case OPC_SEL_S: 9568 tcg_gen_andi_i32(fp0, fp0, 1); 9569 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp0, t1, fp1, fp2); 9570 break; 9571 case OPC_SELEQZ_S: 9572 tcg_gen_andi_i32(fp1, fp1, 1); 9573 tcg_gen_movcond_i32(TCG_COND_EQ, fp0, fp1, t1, fp2, t1); 9574 break; 9575 case OPC_SELNEZ_S: 9576 tcg_gen_andi_i32(fp1, fp1, 1); 9577 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp1, t1, fp2, t1); 9578 break; 9579 default: 9580 MIPS_INVAL("gen_sel_s"); 9581 gen_reserved_instruction(ctx); 9582 break; 9583 } 9584 9585 gen_store_fpr32(ctx, fp0, fd); 9586 } 9587 9588 static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft, 9589 int fs) 9590 { 9591 TCGv_i64 t1 = tcg_const_i64(0); 9592 TCGv_i64 fp0 = tcg_temp_new_i64(); 9593 TCGv_i64 fp1 = tcg_temp_new_i64(); 9594 TCGv_i64 fp2 = tcg_temp_new_i64(); 9595 gen_load_fpr64(ctx, fp0, fd); 9596 gen_load_fpr64(ctx, fp1, ft); 9597 gen_load_fpr64(ctx, fp2, fs); 9598 9599 switch (op1) { 9600 case OPC_SEL_D: 9601 tcg_gen_andi_i64(fp0, fp0, 1); 9602 tcg_gen_movcond_i64(TCG_COND_NE, fp0, fp0, t1, fp1, fp2); 9603 break; 9604 case OPC_SELEQZ_D: 9605 tcg_gen_andi_i64(fp1, fp1, 1); 9606 tcg_gen_movcond_i64(TCG_COND_EQ, fp0, fp1, t1, fp2, t1); 9607 break; 9608 case OPC_SELNEZ_D: 9609 tcg_gen_andi_i64(fp1, fp1, 1); 9610 tcg_gen_movcond_i64(TCG_COND_NE, fp0, fp1, t1, fp2, t1); 9611 break; 9612 default: 9613 MIPS_INVAL("gen_sel_d"); 9614 gen_reserved_instruction(ctx); 9615 break; 9616 } 9617 9618 gen_store_fpr64(ctx, fp0, fd); 9619 } 9620 9621 static void gen_farith(DisasContext *ctx, enum fopcode op1, 9622 int ft, int fs, int fd, int cc) 9623 { 9624 uint32_t func = ctx->opcode & 0x3f; 9625 switch (op1) { 9626 case OPC_ADD_S: 9627 { 9628 TCGv_i32 fp0 = tcg_temp_new_i32(); 9629 TCGv_i32 fp1 = tcg_temp_new_i32(); 9630 9631 gen_load_fpr32(ctx, fp0, fs); 9632 gen_load_fpr32(ctx, fp1, ft); 9633 gen_helper_float_add_s(fp0, cpu_env, fp0, fp1); 9634 gen_store_fpr32(ctx, fp0, fd); 9635 } 9636 break; 9637 case OPC_SUB_S: 9638 { 9639 TCGv_i32 fp0 = tcg_temp_new_i32(); 9640 TCGv_i32 fp1 = tcg_temp_new_i32(); 9641 9642 gen_load_fpr32(ctx, fp0, fs); 9643 gen_load_fpr32(ctx, fp1, ft); 9644 gen_helper_float_sub_s(fp0, cpu_env, fp0, fp1); 9645 gen_store_fpr32(ctx, fp0, fd); 9646 } 9647 break; 9648 case OPC_MUL_S: 9649 { 9650 TCGv_i32 fp0 = tcg_temp_new_i32(); 9651 TCGv_i32 fp1 = tcg_temp_new_i32(); 9652 9653 gen_load_fpr32(ctx, fp0, fs); 9654 gen_load_fpr32(ctx, fp1, ft); 9655 gen_helper_float_mul_s(fp0, cpu_env, fp0, fp1); 9656 gen_store_fpr32(ctx, fp0, fd); 9657 } 9658 break; 9659 case OPC_DIV_S: 9660 { 9661 TCGv_i32 fp0 = tcg_temp_new_i32(); 9662 TCGv_i32 fp1 = tcg_temp_new_i32(); 9663 9664 gen_load_fpr32(ctx, fp0, fs); 9665 gen_load_fpr32(ctx, fp1, ft); 9666 gen_helper_float_div_s(fp0, cpu_env, fp0, fp1); 9667 gen_store_fpr32(ctx, fp0, fd); 9668 } 9669 break; 9670 case OPC_SQRT_S: 9671 { 9672 TCGv_i32 fp0 = tcg_temp_new_i32(); 9673 9674 gen_load_fpr32(ctx, fp0, fs); 9675 gen_helper_float_sqrt_s(fp0, cpu_env, fp0); 9676 gen_store_fpr32(ctx, fp0, fd); 9677 } 9678 break; 9679 case OPC_ABS_S: 9680 { 9681 TCGv_i32 fp0 = tcg_temp_new_i32(); 9682 9683 gen_load_fpr32(ctx, fp0, fs); 9684 if (ctx->abs2008) { 9685 tcg_gen_andi_i32(fp0, fp0, 0x7fffffffUL); 9686 } else { 9687 gen_helper_float_abs_s(fp0, fp0); 9688 } 9689 gen_store_fpr32(ctx, fp0, fd); 9690 } 9691 break; 9692 case OPC_MOV_S: 9693 { 9694 TCGv_i32 fp0 = tcg_temp_new_i32(); 9695 9696 gen_load_fpr32(ctx, fp0, fs); 9697 gen_store_fpr32(ctx, fp0, fd); 9698 } 9699 break; 9700 case OPC_NEG_S: 9701 { 9702 TCGv_i32 fp0 = tcg_temp_new_i32(); 9703 9704 gen_load_fpr32(ctx, fp0, fs); 9705 if (ctx->abs2008) { 9706 tcg_gen_xori_i32(fp0, fp0, 1UL << 31); 9707 } else { 9708 gen_helper_float_chs_s(fp0, fp0); 9709 } 9710 gen_store_fpr32(ctx, fp0, fd); 9711 } 9712 break; 9713 case OPC_ROUND_L_S: 9714 check_cp1_64bitmode(ctx); 9715 { 9716 TCGv_i32 fp32 = tcg_temp_new_i32(); 9717 TCGv_i64 fp64 = tcg_temp_new_i64(); 9718 9719 gen_load_fpr32(ctx, fp32, fs); 9720 if (ctx->nan2008) { 9721 gen_helper_float_round_2008_l_s(fp64, cpu_env, fp32); 9722 } else { 9723 gen_helper_float_round_l_s(fp64, cpu_env, fp32); 9724 } 9725 gen_store_fpr64(ctx, fp64, fd); 9726 } 9727 break; 9728 case OPC_TRUNC_L_S: 9729 check_cp1_64bitmode(ctx); 9730 { 9731 TCGv_i32 fp32 = tcg_temp_new_i32(); 9732 TCGv_i64 fp64 = tcg_temp_new_i64(); 9733 9734 gen_load_fpr32(ctx, fp32, fs); 9735 if (ctx->nan2008) { 9736 gen_helper_float_trunc_2008_l_s(fp64, cpu_env, fp32); 9737 } else { 9738 gen_helper_float_trunc_l_s(fp64, cpu_env, fp32); 9739 } 9740 gen_store_fpr64(ctx, fp64, fd); 9741 } 9742 break; 9743 case OPC_CEIL_L_S: 9744 check_cp1_64bitmode(ctx); 9745 { 9746 TCGv_i32 fp32 = tcg_temp_new_i32(); 9747 TCGv_i64 fp64 = tcg_temp_new_i64(); 9748 9749 gen_load_fpr32(ctx, fp32, fs); 9750 if (ctx->nan2008) { 9751 gen_helper_float_ceil_2008_l_s(fp64, cpu_env, fp32); 9752 } else { 9753 gen_helper_float_ceil_l_s(fp64, cpu_env, fp32); 9754 } 9755 gen_store_fpr64(ctx, fp64, fd); 9756 } 9757 break; 9758 case OPC_FLOOR_L_S: 9759 check_cp1_64bitmode(ctx); 9760 { 9761 TCGv_i32 fp32 = tcg_temp_new_i32(); 9762 TCGv_i64 fp64 = tcg_temp_new_i64(); 9763 9764 gen_load_fpr32(ctx, fp32, fs); 9765 if (ctx->nan2008) { 9766 gen_helper_float_floor_2008_l_s(fp64, cpu_env, fp32); 9767 } else { 9768 gen_helper_float_floor_l_s(fp64, cpu_env, fp32); 9769 } 9770 gen_store_fpr64(ctx, fp64, fd); 9771 } 9772 break; 9773 case OPC_ROUND_W_S: 9774 { 9775 TCGv_i32 fp0 = tcg_temp_new_i32(); 9776 9777 gen_load_fpr32(ctx, fp0, fs); 9778 if (ctx->nan2008) { 9779 gen_helper_float_round_2008_w_s(fp0, cpu_env, fp0); 9780 } else { 9781 gen_helper_float_round_w_s(fp0, cpu_env, fp0); 9782 } 9783 gen_store_fpr32(ctx, fp0, fd); 9784 } 9785 break; 9786 case OPC_TRUNC_W_S: 9787 { 9788 TCGv_i32 fp0 = tcg_temp_new_i32(); 9789 9790 gen_load_fpr32(ctx, fp0, fs); 9791 if (ctx->nan2008) { 9792 gen_helper_float_trunc_2008_w_s(fp0, cpu_env, fp0); 9793 } else { 9794 gen_helper_float_trunc_w_s(fp0, cpu_env, fp0); 9795 } 9796 gen_store_fpr32(ctx, fp0, fd); 9797 } 9798 break; 9799 case OPC_CEIL_W_S: 9800 { 9801 TCGv_i32 fp0 = tcg_temp_new_i32(); 9802 9803 gen_load_fpr32(ctx, fp0, fs); 9804 if (ctx->nan2008) { 9805 gen_helper_float_ceil_2008_w_s(fp0, cpu_env, fp0); 9806 } else { 9807 gen_helper_float_ceil_w_s(fp0, cpu_env, fp0); 9808 } 9809 gen_store_fpr32(ctx, fp0, fd); 9810 } 9811 break; 9812 case OPC_FLOOR_W_S: 9813 { 9814 TCGv_i32 fp0 = tcg_temp_new_i32(); 9815 9816 gen_load_fpr32(ctx, fp0, fs); 9817 if (ctx->nan2008) { 9818 gen_helper_float_floor_2008_w_s(fp0, cpu_env, fp0); 9819 } else { 9820 gen_helper_float_floor_w_s(fp0, cpu_env, fp0); 9821 } 9822 gen_store_fpr32(ctx, fp0, fd); 9823 } 9824 break; 9825 case OPC_SEL_S: 9826 check_insn(ctx, ISA_MIPS_R6); 9827 gen_sel_s(ctx, op1, fd, ft, fs); 9828 break; 9829 case OPC_SELEQZ_S: 9830 check_insn(ctx, ISA_MIPS_R6); 9831 gen_sel_s(ctx, op1, fd, ft, fs); 9832 break; 9833 case OPC_SELNEZ_S: 9834 check_insn(ctx, ISA_MIPS_R6); 9835 gen_sel_s(ctx, op1, fd, ft, fs); 9836 break; 9837 case OPC_MOVCF_S: 9838 check_insn_opc_removed(ctx, ISA_MIPS_R6); 9839 gen_movcf_s(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); 9840 break; 9841 case OPC_MOVZ_S: 9842 check_insn_opc_removed(ctx, ISA_MIPS_R6); 9843 { 9844 TCGLabel *l1 = gen_new_label(); 9845 TCGv_i32 fp0; 9846 9847 if (ft != 0) { 9848 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); 9849 } 9850 fp0 = tcg_temp_new_i32(); 9851 gen_load_fpr32(ctx, fp0, fs); 9852 gen_store_fpr32(ctx, fp0, fd); 9853 gen_set_label(l1); 9854 } 9855 break; 9856 case OPC_MOVN_S: 9857 check_insn_opc_removed(ctx, ISA_MIPS_R6); 9858 { 9859 TCGLabel *l1 = gen_new_label(); 9860 TCGv_i32 fp0; 9861 9862 if (ft != 0) { 9863 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); 9864 fp0 = tcg_temp_new_i32(); 9865 gen_load_fpr32(ctx, fp0, fs); 9866 gen_store_fpr32(ctx, fp0, fd); 9867 gen_set_label(l1); 9868 } 9869 } 9870 break; 9871 case OPC_RECIP_S: 9872 { 9873 TCGv_i32 fp0 = tcg_temp_new_i32(); 9874 9875 gen_load_fpr32(ctx, fp0, fs); 9876 gen_helper_float_recip_s(fp0, cpu_env, fp0); 9877 gen_store_fpr32(ctx, fp0, fd); 9878 } 9879 break; 9880 case OPC_RSQRT_S: 9881 { 9882 TCGv_i32 fp0 = tcg_temp_new_i32(); 9883 9884 gen_load_fpr32(ctx, fp0, fs); 9885 gen_helper_float_rsqrt_s(fp0, cpu_env, fp0); 9886 gen_store_fpr32(ctx, fp0, fd); 9887 } 9888 break; 9889 case OPC_MADDF_S: 9890 check_insn(ctx, ISA_MIPS_R6); 9891 { 9892 TCGv_i32 fp0 = tcg_temp_new_i32(); 9893 TCGv_i32 fp1 = tcg_temp_new_i32(); 9894 TCGv_i32 fp2 = tcg_temp_new_i32(); 9895 gen_load_fpr32(ctx, fp0, fs); 9896 gen_load_fpr32(ctx, fp1, ft); 9897 gen_load_fpr32(ctx, fp2, fd); 9898 gen_helper_float_maddf_s(fp2, cpu_env, fp0, fp1, fp2); 9899 gen_store_fpr32(ctx, fp2, fd); 9900 } 9901 break; 9902 case OPC_MSUBF_S: 9903 check_insn(ctx, ISA_MIPS_R6); 9904 { 9905 TCGv_i32 fp0 = tcg_temp_new_i32(); 9906 TCGv_i32 fp1 = tcg_temp_new_i32(); 9907 TCGv_i32 fp2 = tcg_temp_new_i32(); 9908 gen_load_fpr32(ctx, fp0, fs); 9909 gen_load_fpr32(ctx, fp1, ft); 9910 gen_load_fpr32(ctx, fp2, fd); 9911 gen_helper_float_msubf_s(fp2, cpu_env, fp0, fp1, fp2); 9912 gen_store_fpr32(ctx, fp2, fd); 9913 } 9914 break; 9915 case OPC_RINT_S: 9916 check_insn(ctx, ISA_MIPS_R6); 9917 { 9918 TCGv_i32 fp0 = tcg_temp_new_i32(); 9919 gen_load_fpr32(ctx, fp0, fs); 9920 gen_helper_float_rint_s(fp0, cpu_env, fp0); 9921 gen_store_fpr32(ctx, fp0, fd); 9922 } 9923 break; 9924 case OPC_CLASS_S: 9925 check_insn(ctx, ISA_MIPS_R6); 9926 { 9927 TCGv_i32 fp0 = tcg_temp_new_i32(); 9928 gen_load_fpr32(ctx, fp0, fs); 9929 gen_helper_float_class_s(fp0, cpu_env, fp0); 9930 gen_store_fpr32(ctx, fp0, fd); 9931 } 9932 break; 9933 case OPC_MIN_S: /* OPC_RECIP2_S */ 9934 if (ctx->insn_flags & ISA_MIPS_R6) { 9935 /* OPC_MIN_S */ 9936 TCGv_i32 fp0 = tcg_temp_new_i32(); 9937 TCGv_i32 fp1 = tcg_temp_new_i32(); 9938 TCGv_i32 fp2 = tcg_temp_new_i32(); 9939 gen_load_fpr32(ctx, fp0, fs); 9940 gen_load_fpr32(ctx, fp1, ft); 9941 gen_helper_float_min_s(fp2, cpu_env, fp0, fp1); 9942 gen_store_fpr32(ctx, fp2, fd); 9943 } else { 9944 /* OPC_RECIP2_S */ 9945 check_cp1_64bitmode(ctx); 9946 { 9947 TCGv_i32 fp0 = tcg_temp_new_i32(); 9948 TCGv_i32 fp1 = tcg_temp_new_i32(); 9949 9950 gen_load_fpr32(ctx, fp0, fs); 9951 gen_load_fpr32(ctx, fp1, ft); 9952 gen_helper_float_recip2_s(fp0, cpu_env, fp0, fp1); 9953 gen_store_fpr32(ctx, fp0, fd); 9954 } 9955 } 9956 break; 9957 case OPC_MINA_S: /* OPC_RECIP1_S */ 9958 if (ctx->insn_flags & ISA_MIPS_R6) { 9959 /* OPC_MINA_S */ 9960 TCGv_i32 fp0 = tcg_temp_new_i32(); 9961 TCGv_i32 fp1 = tcg_temp_new_i32(); 9962 TCGv_i32 fp2 = tcg_temp_new_i32(); 9963 gen_load_fpr32(ctx, fp0, fs); 9964 gen_load_fpr32(ctx, fp1, ft); 9965 gen_helper_float_mina_s(fp2, cpu_env, fp0, fp1); 9966 gen_store_fpr32(ctx, fp2, fd); 9967 } else { 9968 /* OPC_RECIP1_S */ 9969 check_cp1_64bitmode(ctx); 9970 { 9971 TCGv_i32 fp0 = tcg_temp_new_i32(); 9972 9973 gen_load_fpr32(ctx, fp0, fs); 9974 gen_helper_float_recip1_s(fp0, cpu_env, fp0); 9975 gen_store_fpr32(ctx, fp0, fd); 9976 } 9977 } 9978 break; 9979 case OPC_MAX_S: /* OPC_RSQRT1_S */ 9980 if (ctx->insn_flags & ISA_MIPS_R6) { 9981 /* OPC_MAX_S */ 9982 TCGv_i32 fp0 = tcg_temp_new_i32(); 9983 TCGv_i32 fp1 = tcg_temp_new_i32(); 9984 gen_load_fpr32(ctx, fp0, fs); 9985 gen_load_fpr32(ctx, fp1, ft); 9986 gen_helper_float_max_s(fp1, cpu_env, fp0, fp1); 9987 gen_store_fpr32(ctx, fp1, fd); 9988 } else { 9989 /* OPC_RSQRT1_S */ 9990 check_cp1_64bitmode(ctx); 9991 { 9992 TCGv_i32 fp0 = tcg_temp_new_i32(); 9993 9994 gen_load_fpr32(ctx, fp0, fs); 9995 gen_helper_float_rsqrt1_s(fp0, cpu_env, fp0); 9996 gen_store_fpr32(ctx, fp0, fd); 9997 } 9998 } 9999 break; 10000 case OPC_MAXA_S: /* OPC_RSQRT2_S */ 10001 if (ctx->insn_flags & ISA_MIPS_R6) { 10002 /* OPC_MAXA_S */ 10003 TCGv_i32 fp0 = tcg_temp_new_i32(); 10004 TCGv_i32 fp1 = tcg_temp_new_i32(); 10005 gen_load_fpr32(ctx, fp0, fs); 10006 gen_load_fpr32(ctx, fp1, ft); 10007 gen_helper_float_maxa_s(fp1, cpu_env, fp0, fp1); 10008 gen_store_fpr32(ctx, fp1, fd); 10009 } else { 10010 /* OPC_RSQRT2_S */ 10011 check_cp1_64bitmode(ctx); 10012 { 10013 TCGv_i32 fp0 = tcg_temp_new_i32(); 10014 TCGv_i32 fp1 = tcg_temp_new_i32(); 10015 10016 gen_load_fpr32(ctx, fp0, fs); 10017 gen_load_fpr32(ctx, fp1, ft); 10018 gen_helper_float_rsqrt2_s(fp0, cpu_env, fp0, fp1); 10019 gen_store_fpr32(ctx, fp0, fd); 10020 } 10021 } 10022 break; 10023 case OPC_CVT_D_S: 10024 check_cp1_registers(ctx, fd); 10025 { 10026 TCGv_i32 fp32 = tcg_temp_new_i32(); 10027 TCGv_i64 fp64 = tcg_temp_new_i64(); 10028 10029 gen_load_fpr32(ctx, fp32, fs); 10030 gen_helper_float_cvtd_s(fp64, cpu_env, fp32); 10031 gen_store_fpr64(ctx, fp64, fd); 10032 } 10033 break; 10034 case OPC_CVT_W_S: 10035 { 10036 TCGv_i32 fp0 = tcg_temp_new_i32(); 10037 10038 gen_load_fpr32(ctx, fp0, fs); 10039 if (ctx->nan2008) { 10040 gen_helper_float_cvt_2008_w_s(fp0, cpu_env, fp0); 10041 } else { 10042 gen_helper_float_cvt_w_s(fp0, cpu_env, fp0); 10043 } 10044 gen_store_fpr32(ctx, fp0, fd); 10045 } 10046 break; 10047 case OPC_CVT_L_S: 10048 check_cp1_64bitmode(ctx); 10049 { 10050 TCGv_i32 fp32 = tcg_temp_new_i32(); 10051 TCGv_i64 fp64 = tcg_temp_new_i64(); 10052 10053 gen_load_fpr32(ctx, fp32, fs); 10054 if (ctx->nan2008) { 10055 gen_helper_float_cvt_2008_l_s(fp64, cpu_env, fp32); 10056 } else { 10057 gen_helper_float_cvt_l_s(fp64, cpu_env, fp32); 10058 } 10059 gen_store_fpr64(ctx, fp64, fd); 10060 } 10061 break; 10062 case OPC_CVT_PS_S: 10063 check_ps(ctx); 10064 { 10065 TCGv_i64 fp64 = tcg_temp_new_i64(); 10066 TCGv_i32 fp32_0 = tcg_temp_new_i32(); 10067 TCGv_i32 fp32_1 = tcg_temp_new_i32(); 10068 10069 gen_load_fpr32(ctx, fp32_0, fs); 10070 gen_load_fpr32(ctx, fp32_1, ft); 10071 tcg_gen_concat_i32_i64(fp64, fp32_1, fp32_0); 10072 gen_store_fpr64(ctx, fp64, fd); 10073 } 10074 break; 10075 case OPC_CMP_F_S: 10076 case OPC_CMP_UN_S: 10077 case OPC_CMP_EQ_S: 10078 case OPC_CMP_UEQ_S: 10079 case OPC_CMP_OLT_S: 10080 case OPC_CMP_ULT_S: 10081 case OPC_CMP_OLE_S: 10082 case OPC_CMP_ULE_S: 10083 case OPC_CMP_SF_S: 10084 case OPC_CMP_NGLE_S: 10085 case OPC_CMP_SEQ_S: 10086 case OPC_CMP_NGL_S: 10087 case OPC_CMP_LT_S: 10088 case OPC_CMP_NGE_S: 10089 case OPC_CMP_LE_S: 10090 case OPC_CMP_NGT_S: 10091 check_insn_opc_removed(ctx, ISA_MIPS_R6); 10092 if (ctx->opcode & (1 << 6)) { 10093 gen_cmpabs_s(ctx, func - 48, ft, fs, cc); 10094 } else { 10095 gen_cmp_s(ctx, func - 48, ft, fs, cc); 10096 } 10097 break; 10098 case OPC_ADD_D: 10099 check_cp1_registers(ctx, fs | ft | fd); 10100 { 10101 TCGv_i64 fp0 = tcg_temp_new_i64(); 10102 TCGv_i64 fp1 = tcg_temp_new_i64(); 10103 10104 gen_load_fpr64(ctx, fp0, fs); 10105 gen_load_fpr64(ctx, fp1, ft); 10106 gen_helper_float_add_d(fp0, cpu_env, fp0, fp1); 10107 gen_store_fpr64(ctx, fp0, fd); 10108 } 10109 break; 10110 case OPC_SUB_D: 10111 check_cp1_registers(ctx, fs | ft | fd); 10112 { 10113 TCGv_i64 fp0 = tcg_temp_new_i64(); 10114 TCGv_i64 fp1 = tcg_temp_new_i64(); 10115 10116 gen_load_fpr64(ctx, fp0, fs); 10117 gen_load_fpr64(ctx, fp1, ft); 10118 gen_helper_float_sub_d(fp0, cpu_env, fp0, fp1); 10119 gen_store_fpr64(ctx, fp0, fd); 10120 } 10121 break; 10122 case OPC_MUL_D: 10123 check_cp1_registers(ctx, fs | ft | fd); 10124 { 10125 TCGv_i64 fp0 = tcg_temp_new_i64(); 10126 TCGv_i64 fp1 = tcg_temp_new_i64(); 10127 10128 gen_load_fpr64(ctx, fp0, fs); 10129 gen_load_fpr64(ctx, fp1, ft); 10130 gen_helper_float_mul_d(fp0, cpu_env, fp0, fp1); 10131 gen_store_fpr64(ctx, fp0, fd); 10132 } 10133 break; 10134 case OPC_DIV_D: 10135 check_cp1_registers(ctx, fs | ft | fd); 10136 { 10137 TCGv_i64 fp0 = tcg_temp_new_i64(); 10138 TCGv_i64 fp1 = tcg_temp_new_i64(); 10139 10140 gen_load_fpr64(ctx, fp0, fs); 10141 gen_load_fpr64(ctx, fp1, ft); 10142 gen_helper_float_div_d(fp0, cpu_env, fp0, fp1); 10143 gen_store_fpr64(ctx, fp0, fd); 10144 } 10145 break; 10146 case OPC_SQRT_D: 10147 check_cp1_registers(ctx, fs | fd); 10148 { 10149 TCGv_i64 fp0 = tcg_temp_new_i64(); 10150 10151 gen_load_fpr64(ctx, fp0, fs); 10152 gen_helper_float_sqrt_d(fp0, cpu_env, fp0); 10153 gen_store_fpr64(ctx, fp0, fd); 10154 } 10155 break; 10156 case OPC_ABS_D: 10157 check_cp1_registers(ctx, fs | fd); 10158 { 10159 TCGv_i64 fp0 = tcg_temp_new_i64(); 10160 10161 gen_load_fpr64(ctx, fp0, fs); 10162 if (ctx->abs2008) { 10163 tcg_gen_andi_i64(fp0, fp0, 0x7fffffffffffffffULL); 10164 } else { 10165 gen_helper_float_abs_d(fp0, fp0); 10166 } 10167 gen_store_fpr64(ctx, fp0, fd); 10168 } 10169 break; 10170 case OPC_MOV_D: 10171 check_cp1_registers(ctx, fs | fd); 10172 { 10173 TCGv_i64 fp0 = tcg_temp_new_i64(); 10174 10175 gen_load_fpr64(ctx, fp0, fs); 10176 gen_store_fpr64(ctx, fp0, fd); 10177 } 10178 break; 10179 case OPC_NEG_D: 10180 check_cp1_registers(ctx, fs | fd); 10181 { 10182 TCGv_i64 fp0 = tcg_temp_new_i64(); 10183 10184 gen_load_fpr64(ctx, fp0, fs); 10185 if (ctx->abs2008) { 10186 tcg_gen_xori_i64(fp0, fp0, 1ULL << 63); 10187 } else { 10188 gen_helper_float_chs_d(fp0, fp0); 10189 } 10190 gen_store_fpr64(ctx, fp0, fd); 10191 } 10192 break; 10193 case OPC_ROUND_L_D: 10194 check_cp1_64bitmode(ctx); 10195 { 10196 TCGv_i64 fp0 = tcg_temp_new_i64(); 10197 10198 gen_load_fpr64(ctx, fp0, fs); 10199 if (ctx->nan2008) { 10200 gen_helper_float_round_2008_l_d(fp0, cpu_env, fp0); 10201 } else { 10202 gen_helper_float_round_l_d(fp0, cpu_env, fp0); 10203 } 10204 gen_store_fpr64(ctx, fp0, fd); 10205 } 10206 break; 10207 case OPC_TRUNC_L_D: 10208 check_cp1_64bitmode(ctx); 10209 { 10210 TCGv_i64 fp0 = tcg_temp_new_i64(); 10211 10212 gen_load_fpr64(ctx, fp0, fs); 10213 if (ctx->nan2008) { 10214 gen_helper_float_trunc_2008_l_d(fp0, cpu_env, fp0); 10215 } else { 10216 gen_helper_float_trunc_l_d(fp0, cpu_env, fp0); 10217 } 10218 gen_store_fpr64(ctx, fp0, fd); 10219 } 10220 break; 10221 case OPC_CEIL_L_D: 10222 check_cp1_64bitmode(ctx); 10223 { 10224 TCGv_i64 fp0 = tcg_temp_new_i64(); 10225 10226 gen_load_fpr64(ctx, fp0, fs); 10227 if (ctx->nan2008) { 10228 gen_helper_float_ceil_2008_l_d(fp0, cpu_env, fp0); 10229 } else { 10230 gen_helper_float_ceil_l_d(fp0, cpu_env, fp0); 10231 } 10232 gen_store_fpr64(ctx, fp0, fd); 10233 } 10234 break; 10235 case OPC_FLOOR_L_D: 10236 check_cp1_64bitmode(ctx); 10237 { 10238 TCGv_i64 fp0 = tcg_temp_new_i64(); 10239 10240 gen_load_fpr64(ctx, fp0, fs); 10241 if (ctx->nan2008) { 10242 gen_helper_float_floor_2008_l_d(fp0, cpu_env, fp0); 10243 } else { 10244 gen_helper_float_floor_l_d(fp0, cpu_env, fp0); 10245 } 10246 gen_store_fpr64(ctx, fp0, fd); 10247 } 10248 break; 10249 case OPC_ROUND_W_D: 10250 check_cp1_registers(ctx, fs); 10251 { 10252 TCGv_i32 fp32 = tcg_temp_new_i32(); 10253 TCGv_i64 fp64 = tcg_temp_new_i64(); 10254 10255 gen_load_fpr64(ctx, fp64, fs); 10256 if (ctx->nan2008) { 10257 gen_helper_float_round_2008_w_d(fp32, cpu_env, fp64); 10258 } else { 10259 gen_helper_float_round_w_d(fp32, cpu_env, fp64); 10260 } 10261 gen_store_fpr32(ctx, fp32, fd); 10262 } 10263 break; 10264 case OPC_TRUNC_W_D: 10265 check_cp1_registers(ctx, fs); 10266 { 10267 TCGv_i32 fp32 = tcg_temp_new_i32(); 10268 TCGv_i64 fp64 = tcg_temp_new_i64(); 10269 10270 gen_load_fpr64(ctx, fp64, fs); 10271 if (ctx->nan2008) { 10272 gen_helper_float_trunc_2008_w_d(fp32, cpu_env, fp64); 10273 } else { 10274 gen_helper_float_trunc_w_d(fp32, cpu_env, fp64); 10275 } 10276 gen_store_fpr32(ctx, fp32, fd); 10277 } 10278 break; 10279 case OPC_CEIL_W_D: 10280 check_cp1_registers(ctx, fs); 10281 { 10282 TCGv_i32 fp32 = tcg_temp_new_i32(); 10283 TCGv_i64 fp64 = tcg_temp_new_i64(); 10284 10285 gen_load_fpr64(ctx, fp64, fs); 10286 if (ctx->nan2008) { 10287 gen_helper_float_ceil_2008_w_d(fp32, cpu_env, fp64); 10288 } else { 10289 gen_helper_float_ceil_w_d(fp32, cpu_env, fp64); 10290 } 10291 gen_store_fpr32(ctx, fp32, fd); 10292 } 10293 break; 10294 case OPC_FLOOR_W_D: 10295 check_cp1_registers(ctx, fs); 10296 { 10297 TCGv_i32 fp32 = tcg_temp_new_i32(); 10298 TCGv_i64 fp64 = tcg_temp_new_i64(); 10299 10300 gen_load_fpr64(ctx, fp64, fs); 10301 if (ctx->nan2008) { 10302 gen_helper_float_floor_2008_w_d(fp32, cpu_env, fp64); 10303 } else { 10304 gen_helper_float_floor_w_d(fp32, cpu_env, fp64); 10305 } 10306 gen_store_fpr32(ctx, fp32, fd); 10307 } 10308 break; 10309 case OPC_SEL_D: 10310 check_insn(ctx, ISA_MIPS_R6); 10311 gen_sel_d(ctx, op1, fd, ft, fs); 10312 break; 10313 case OPC_SELEQZ_D: 10314 check_insn(ctx, ISA_MIPS_R6); 10315 gen_sel_d(ctx, op1, fd, ft, fs); 10316 break; 10317 case OPC_SELNEZ_D: 10318 check_insn(ctx, ISA_MIPS_R6); 10319 gen_sel_d(ctx, op1, fd, ft, fs); 10320 break; 10321 case OPC_MOVCF_D: 10322 check_insn_opc_removed(ctx, ISA_MIPS_R6); 10323 gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); 10324 break; 10325 case OPC_MOVZ_D: 10326 check_insn_opc_removed(ctx, ISA_MIPS_R6); 10327 { 10328 TCGLabel *l1 = gen_new_label(); 10329 TCGv_i64 fp0; 10330 10331 if (ft != 0) { 10332 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); 10333 } 10334 fp0 = tcg_temp_new_i64(); 10335 gen_load_fpr64(ctx, fp0, fs); 10336 gen_store_fpr64(ctx, fp0, fd); 10337 gen_set_label(l1); 10338 } 10339 break; 10340 case OPC_MOVN_D: 10341 check_insn_opc_removed(ctx, ISA_MIPS_R6); 10342 { 10343 TCGLabel *l1 = gen_new_label(); 10344 TCGv_i64 fp0; 10345 10346 if (ft != 0) { 10347 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); 10348 fp0 = tcg_temp_new_i64(); 10349 gen_load_fpr64(ctx, fp0, fs); 10350 gen_store_fpr64(ctx, fp0, fd); 10351 gen_set_label(l1); 10352 } 10353 } 10354 break; 10355 case OPC_RECIP_D: 10356 check_cp1_registers(ctx, fs | fd); 10357 { 10358 TCGv_i64 fp0 = tcg_temp_new_i64(); 10359 10360 gen_load_fpr64(ctx, fp0, fs); 10361 gen_helper_float_recip_d(fp0, cpu_env, fp0); 10362 gen_store_fpr64(ctx, fp0, fd); 10363 } 10364 break; 10365 case OPC_RSQRT_D: 10366 check_cp1_registers(ctx, fs | fd); 10367 { 10368 TCGv_i64 fp0 = tcg_temp_new_i64(); 10369 10370 gen_load_fpr64(ctx, fp0, fs); 10371 gen_helper_float_rsqrt_d(fp0, cpu_env, fp0); 10372 gen_store_fpr64(ctx, fp0, fd); 10373 } 10374 break; 10375 case OPC_MADDF_D: 10376 check_insn(ctx, ISA_MIPS_R6); 10377 { 10378 TCGv_i64 fp0 = tcg_temp_new_i64(); 10379 TCGv_i64 fp1 = tcg_temp_new_i64(); 10380 TCGv_i64 fp2 = tcg_temp_new_i64(); 10381 gen_load_fpr64(ctx, fp0, fs); 10382 gen_load_fpr64(ctx, fp1, ft); 10383 gen_load_fpr64(ctx, fp2, fd); 10384 gen_helper_float_maddf_d(fp2, cpu_env, fp0, fp1, fp2); 10385 gen_store_fpr64(ctx, fp2, fd); 10386 } 10387 break; 10388 case OPC_MSUBF_D: 10389 check_insn(ctx, ISA_MIPS_R6); 10390 { 10391 TCGv_i64 fp0 = tcg_temp_new_i64(); 10392 TCGv_i64 fp1 = tcg_temp_new_i64(); 10393 TCGv_i64 fp2 = tcg_temp_new_i64(); 10394 gen_load_fpr64(ctx, fp0, fs); 10395 gen_load_fpr64(ctx, fp1, ft); 10396 gen_load_fpr64(ctx, fp2, fd); 10397 gen_helper_float_msubf_d(fp2, cpu_env, fp0, fp1, fp2); 10398 gen_store_fpr64(ctx, fp2, fd); 10399 } 10400 break; 10401 case OPC_RINT_D: 10402 check_insn(ctx, ISA_MIPS_R6); 10403 { 10404 TCGv_i64 fp0 = tcg_temp_new_i64(); 10405 gen_load_fpr64(ctx, fp0, fs); 10406 gen_helper_float_rint_d(fp0, cpu_env, fp0); 10407 gen_store_fpr64(ctx, fp0, fd); 10408 } 10409 break; 10410 case OPC_CLASS_D: 10411 check_insn(ctx, ISA_MIPS_R6); 10412 { 10413 TCGv_i64 fp0 = tcg_temp_new_i64(); 10414 gen_load_fpr64(ctx, fp0, fs); 10415 gen_helper_float_class_d(fp0, cpu_env, fp0); 10416 gen_store_fpr64(ctx, fp0, fd); 10417 } 10418 break; 10419 case OPC_MIN_D: /* OPC_RECIP2_D */ 10420 if (ctx->insn_flags & ISA_MIPS_R6) { 10421 /* OPC_MIN_D */ 10422 TCGv_i64 fp0 = tcg_temp_new_i64(); 10423 TCGv_i64 fp1 = tcg_temp_new_i64(); 10424 gen_load_fpr64(ctx, fp0, fs); 10425 gen_load_fpr64(ctx, fp1, ft); 10426 gen_helper_float_min_d(fp1, cpu_env, fp0, fp1); 10427 gen_store_fpr64(ctx, fp1, fd); 10428 } else { 10429 /* OPC_RECIP2_D */ 10430 check_cp1_64bitmode(ctx); 10431 { 10432 TCGv_i64 fp0 = tcg_temp_new_i64(); 10433 TCGv_i64 fp1 = tcg_temp_new_i64(); 10434 10435 gen_load_fpr64(ctx, fp0, fs); 10436 gen_load_fpr64(ctx, fp1, ft); 10437 gen_helper_float_recip2_d(fp0, cpu_env, fp0, fp1); 10438 gen_store_fpr64(ctx, fp0, fd); 10439 } 10440 } 10441 break; 10442 case OPC_MINA_D: /* OPC_RECIP1_D */ 10443 if (ctx->insn_flags & ISA_MIPS_R6) { 10444 /* OPC_MINA_D */ 10445 TCGv_i64 fp0 = tcg_temp_new_i64(); 10446 TCGv_i64 fp1 = tcg_temp_new_i64(); 10447 gen_load_fpr64(ctx, fp0, fs); 10448 gen_load_fpr64(ctx, fp1, ft); 10449 gen_helper_float_mina_d(fp1, cpu_env, fp0, fp1); 10450 gen_store_fpr64(ctx, fp1, fd); 10451 } else { 10452 /* OPC_RECIP1_D */ 10453 check_cp1_64bitmode(ctx); 10454 { 10455 TCGv_i64 fp0 = tcg_temp_new_i64(); 10456 10457 gen_load_fpr64(ctx, fp0, fs); 10458 gen_helper_float_recip1_d(fp0, cpu_env, fp0); 10459 gen_store_fpr64(ctx, fp0, fd); 10460 } 10461 } 10462 break; 10463 case OPC_MAX_D: /* OPC_RSQRT1_D */ 10464 if (ctx->insn_flags & ISA_MIPS_R6) { 10465 /* OPC_MAX_D */ 10466 TCGv_i64 fp0 = tcg_temp_new_i64(); 10467 TCGv_i64 fp1 = tcg_temp_new_i64(); 10468 gen_load_fpr64(ctx, fp0, fs); 10469 gen_load_fpr64(ctx, fp1, ft); 10470 gen_helper_float_max_d(fp1, cpu_env, fp0, fp1); 10471 gen_store_fpr64(ctx, fp1, fd); 10472 } else { 10473 /* OPC_RSQRT1_D */ 10474 check_cp1_64bitmode(ctx); 10475 { 10476 TCGv_i64 fp0 = tcg_temp_new_i64(); 10477 10478 gen_load_fpr64(ctx, fp0, fs); 10479 gen_helper_float_rsqrt1_d(fp0, cpu_env, fp0); 10480 gen_store_fpr64(ctx, fp0, fd); 10481 } 10482 } 10483 break; 10484 case OPC_MAXA_D: /* OPC_RSQRT2_D */ 10485 if (ctx->insn_flags & ISA_MIPS_R6) { 10486 /* OPC_MAXA_D */ 10487 TCGv_i64 fp0 = tcg_temp_new_i64(); 10488 TCGv_i64 fp1 = tcg_temp_new_i64(); 10489 gen_load_fpr64(ctx, fp0, fs); 10490 gen_load_fpr64(ctx, fp1, ft); 10491 gen_helper_float_maxa_d(fp1, cpu_env, fp0, fp1); 10492 gen_store_fpr64(ctx, fp1, fd); 10493 } else { 10494 /* OPC_RSQRT2_D */ 10495 check_cp1_64bitmode(ctx); 10496 { 10497 TCGv_i64 fp0 = tcg_temp_new_i64(); 10498 TCGv_i64 fp1 = tcg_temp_new_i64(); 10499 10500 gen_load_fpr64(ctx, fp0, fs); 10501 gen_load_fpr64(ctx, fp1, ft); 10502 gen_helper_float_rsqrt2_d(fp0, cpu_env, fp0, fp1); 10503 gen_store_fpr64(ctx, fp0, fd); 10504 } 10505 } 10506 break; 10507 case OPC_CMP_F_D: 10508 case OPC_CMP_UN_D: 10509 case OPC_CMP_EQ_D: 10510 case OPC_CMP_UEQ_D: 10511 case OPC_CMP_OLT_D: 10512 case OPC_CMP_ULT_D: 10513 case OPC_CMP_OLE_D: 10514 case OPC_CMP_ULE_D: 10515 case OPC_CMP_SF_D: 10516 case OPC_CMP_NGLE_D: 10517 case OPC_CMP_SEQ_D: 10518 case OPC_CMP_NGL_D: 10519 case OPC_CMP_LT_D: 10520 case OPC_CMP_NGE_D: 10521 case OPC_CMP_LE_D: 10522 case OPC_CMP_NGT_D: 10523 check_insn_opc_removed(ctx, ISA_MIPS_R6); 10524 if (ctx->opcode & (1 << 6)) { 10525 gen_cmpabs_d(ctx, func - 48, ft, fs, cc); 10526 } else { 10527 gen_cmp_d(ctx, func - 48, ft, fs, cc); 10528 } 10529 break; 10530 case OPC_CVT_S_D: 10531 check_cp1_registers(ctx, fs); 10532 { 10533 TCGv_i32 fp32 = tcg_temp_new_i32(); 10534 TCGv_i64 fp64 = tcg_temp_new_i64(); 10535 10536 gen_load_fpr64(ctx, fp64, fs); 10537 gen_helper_float_cvts_d(fp32, cpu_env, fp64); 10538 gen_store_fpr32(ctx, fp32, fd); 10539 } 10540 break; 10541 case OPC_CVT_W_D: 10542 check_cp1_registers(ctx, fs); 10543 { 10544 TCGv_i32 fp32 = tcg_temp_new_i32(); 10545 TCGv_i64 fp64 = tcg_temp_new_i64(); 10546 10547 gen_load_fpr64(ctx, fp64, fs); 10548 if (ctx->nan2008) { 10549 gen_helper_float_cvt_2008_w_d(fp32, cpu_env, fp64); 10550 } else { 10551 gen_helper_float_cvt_w_d(fp32, cpu_env, fp64); 10552 } 10553 gen_store_fpr32(ctx, fp32, fd); 10554 } 10555 break; 10556 case OPC_CVT_L_D: 10557 check_cp1_64bitmode(ctx); 10558 { 10559 TCGv_i64 fp0 = tcg_temp_new_i64(); 10560 10561 gen_load_fpr64(ctx, fp0, fs); 10562 if (ctx->nan2008) { 10563 gen_helper_float_cvt_2008_l_d(fp0, cpu_env, fp0); 10564 } else { 10565 gen_helper_float_cvt_l_d(fp0, cpu_env, fp0); 10566 } 10567 gen_store_fpr64(ctx, fp0, fd); 10568 } 10569 break; 10570 case OPC_CVT_S_W: 10571 { 10572 TCGv_i32 fp0 = tcg_temp_new_i32(); 10573 10574 gen_load_fpr32(ctx, fp0, fs); 10575 gen_helper_float_cvts_w(fp0, cpu_env, fp0); 10576 gen_store_fpr32(ctx, fp0, fd); 10577 } 10578 break; 10579 case OPC_CVT_D_W: 10580 check_cp1_registers(ctx, fd); 10581 { 10582 TCGv_i32 fp32 = tcg_temp_new_i32(); 10583 TCGv_i64 fp64 = tcg_temp_new_i64(); 10584 10585 gen_load_fpr32(ctx, fp32, fs); 10586 gen_helper_float_cvtd_w(fp64, cpu_env, fp32); 10587 gen_store_fpr64(ctx, fp64, fd); 10588 } 10589 break; 10590 case OPC_CVT_S_L: 10591 check_cp1_64bitmode(ctx); 10592 { 10593 TCGv_i32 fp32 = tcg_temp_new_i32(); 10594 TCGv_i64 fp64 = tcg_temp_new_i64(); 10595 10596 gen_load_fpr64(ctx, fp64, fs); 10597 gen_helper_float_cvts_l(fp32, cpu_env, fp64); 10598 gen_store_fpr32(ctx, fp32, fd); 10599 } 10600 break; 10601 case OPC_CVT_D_L: 10602 check_cp1_64bitmode(ctx); 10603 { 10604 TCGv_i64 fp0 = tcg_temp_new_i64(); 10605 10606 gen_load_fpr64(ctx, fp0, fs); 10607 gen_helper_float_cvtd_l(fp0, cpu_env, fp0); 10608 gen_store_fpr64(ctx, fp0, fd); 10609 } 10610 break; 10611 case OPC_CVT_PS_PW: 10612 check_ps(ctx); 10613 { 10614 TCGv_i64 fp0 = tcg_temp_new_i64(); 10615 10616 gen_load_fpr64(ctx, fp0, fs); 10617 gen_helper_float_cvtps_pw(fp0, cpu_env, fp0); 10618 gen_store_fpr64(ctx, fp0, fd); 10619 } 10620 break; 10621 case OPC_ADD_PS: 10622 check_ps(ctx); 10623 { 10624 TCGv_i64 fp0 = tcg_temp_new_i64(); 10625 TCGv_i64 fp1 = tcg_temp_new_i64(); 10626 10627 gen_load_fpr64(ctx, fp0, fs); 10628 gen_load_fpr64(ctx, fp1, ft); 10629 gen_helper_float_add_ps(fp0, cpu_env, fp0, fp1); 10630 gen_store_fpr64(ctx, fp0, fd); 10631 } 10632 break; 10633 case OPC_SUB_PS: 10634 check_ps(ctx); 10635 { 10636 TCGv_i64 fp0 = tcg_temp_new_i64(); 10637 TCGv_i64 fp1 = tcg_temp_new_i64(); 10638 10639 gen_load_fpr64(ctx, fp0, fs); 10640 gen_load_fpr64(ctx, fp1, ft); 10641 gen_helper_float_sub_ps(fp0, cpu_env, fp0, fp1); 10642 gen_store_fpr64(ctx, fp0, fd); 10643 } 10644 break; 10645 case OPC_MUL_PS: 10646 check_ps(ctx); 10647 { 10648 TCGv_i64 fp0 = tcg_temp_new_i64(); 10649 TCGv_i64 fp1 = tcg_temp_new_i64(); 10650 10651 gen_load_fpr64(ctx, fp0, fs); 10652 gen_load_fpr64(ctx, fp1, ft); 10653 gen_helper_float_mul_ps(fp0, cpu_env, fp0, fp1); 10654 gen_store_fpr64(ctx, fp0, fd); 10655 } 10656 break; 10657 case OPC_ABS_PS: 10658 check_ps(ctx); 10659 { 10660 TCGv_i64 fp0 = tcg_temp_new_i64(); 10661 10662 gen_load_fpr64(ctx, fp0, fs); 10663 gen_helper_float_abs_ps(fp0, fp0); 10664 gen_store_fpr64(ctx, fp0, fd); 10665 } 10666 break; 10667 case OPC_MOV_PS: 10668 check_ps(ctx); 10669 { 10670 TCGv_i64 fp0 = tcg_temp_new_i64(); 10671 10672 gen_load_fpr64(ctx, fp0, fs); 10673 gen_store_fpr64(ctx, fp0, fd); 10674 } 10675 break; 10676 case OPC_NEG_PS: 10677 check_ps(ctx); 10678 { 10679 TCGv_i64 fp0 = tcg_temp_new_i64(); 10680 10681 gen_load_fpr64(ctx, fp0, fs); 10682 gen_helper_float_chs_ps(fp0, fp0); 10683 gen_store_fpr64(ctx, fp0, fd); 10684 } 10685 break; 10686 case OPC_MOVCF_PS: 10687 check_ps(ctx); 10688 gen_movcf_ps(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); 10689 break; 10690 case OPC_MOVZ_PS: 10691 check_ps(ctx); 10692 { 10693 TCGLabel *l1 = gen_new_label(); 10694 TCGv_i64 fp0; 10695 10696 if (ft != 0) { 10697 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); 10698 } 10699 fp0 = tcg_temp_new_i64(); 10700 gen_load_fpr64(ctx, fp0, fs); 10701 gen_store_fpr64(ctx, fp0, fd); 10702 gen_set_label(l1); 10703 } 10704 break; 10705 case OPC_MOVN_PS: 10706 check_ps(ctx); 10707 { 10708 TCGLabel *l1 = gen_new_label(); 10709 TCGv_i64 fp0; 10710 10711 if (ft != 0) { 10712 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); 10713 fp0 = tcg_temp_new_i64(); 10714 gen_load_fpr64(ctx, fp0, fs); 10715 gen_store_fpr64(ctx, fp0, fd); 10716 gen_set_label(l1); 10717 } 10718 } 10719 break; 10720 case OPC_ADDR_PS: 10721 check_ps(ctx); 10722 { 10723 TCGv_i64 fp0 = tcg_temp_new_i64(); 10724 TCGv_i64 fp1 = tcg_temp_new_i64(); 10725 10726 gen_load_fpr64(ctx, fp0, ft); 10727 gen_load_fpr64(ctx, fp1, fs); 10728 gen_helper_float_addr_ps(fp0, cpu_env, fp0, fp1); 10729 gen_store_fpr64(ctx, fp0, fd); 10730 } 10731 break; 10732 case OPC_MULR_PS: 10733 check_ps(ctx); 10734 { 10735 TCGv_i64 fp0 = tcg_temp_new_i64(); 10736 TCGv_i64 fp1 = tcg_temp_new_i64(); 10737 10738 gen_load_fpr64(ctx, fp0, ft); 10739 gen_load_fpr64(ctx, fp1, fs); 10740 gen_helper_float_mulr_ps(fp0, cpu_env, fp0, fp1); 10741 gen_store_fpr64(ctx, fp0, fd); 10742 } 10743 break; 10744 case OPC_RECIP2_PS: 10745 check_ps(ctx); 10746 { 10747 TCGv_i64 fp0 = tcg_temp_new_i64(); 10748 TCGv_i64 fp1 = tcg_temp_new_i64(); 10749 10750 gen_load_fpr64(ctx, fp0, fs); 10751 gen_load_fpr64(ctx, fp1, ft); 10752 gen_helper_float_recip2_ps(fp0, cpu_env, fp0, fp1); 10753 gen_store_fpr64(ctx, fp0, fd); 10754 } 10755 break; 10756 case OPC_RECIP1_PS: 10757 check_ps(ctx); 10758 { 10759 TCGv_i64 fp0 = tcg_temp_new_i64(); 10760 10761 gen_load_fpr64(ctx, fp0, fs); 10762 gen_helper_float_recip1_ps(fp0, cpu_env, fp0); 10763 gen_store_fpr64(ctx, fp0, fd); 10764 } 10765 break; 10766 case OPC_RSQRT1_PS: 10767 check_ps(ctx); 10768 { 10769 TCGv_i64 fp0 = tcg_temp_new_i64(); 10770 10771 gen_load_fpr64(ctx, fp0, fs); 10772 gen_helper_float_rsqrt1_ps(fp0, cpu_env, fp0); 10773 gen_store_fpr64(ctx, fp0, fd); 10774 } 10775 break; 10776 case OPC_RSQRT2_PS: 10777 check_ps(ctx); 10778 { 10779 TCGv_i64 fp0 = tcg_temp_new_i64(); 10780 TCGv_i64 fp1 = tcg_temp_new_i64(); 10781 10782 gen_load_fpr64(ctx, fp0, fs); 10783 gen_load_fpr64(ctx, fp1, ft); 10784 gen_helper_float_rsqrt2_ps(fp0, cpu_env, fp0, fp1); 10785 gen_store_fpr64(ctx, fp0, fd); 10786 } 10787 break; 10788 case OPC_CVT_S_PU: 10789 check_cp1_64bitmode(ctx); 10790 { 10791 TCGv_i32 fp0 = tcg_temp_new_i32(); 10792 10793 gen_load_fpr32h(ctx, fp0, fs); 10794 gen_helper_float_cvts_pu(fp0, cpu_env, fp0); 10795 gen_store_fpr32(ctx, fp0, fd); 10796 } 10797 break; 10798 case OPC_CVT_PW_PS: 10799 check_ps(ctx); 10800 { 10801 TCGv_i64 fp0 = tcg_temp_new_i64(); 10802 10803 gen_load_fpr64(ctx, fp0, fs); 10804 gen_helper_float_cvtpw_ps(fp0, cpu_env, fp0); 10805 gen_store_fpr64(ctx, fp0, fd); 10806 } 10807 break; 10808 case OPC_CVT_S_PL: 10809 check_cp1_64bitmode(ctx); 10810 { 10811 TCGv_i32 fp0 = tcg_temp_new_i32(); 10812 10813 gen_load_fpr32(ctx, fp0, fs); 10814 gen_helper_float_cvts_pl(fp0, cpu_env, fp0); 10815 gen_store_fpr32(ctx, fp0, fd); 10816 } 10817 break; 10818 case OPC_PLL_PS: 10819 check_ps(ctx); 10820 { 10821 TCGv_i32 fp0 = tcg_temp_new_i32(); 10822 TCGv_i32 fp1 = tcg_temp_new_i32(); 10823 10824 gen_load_fpr32(ctx, fp0, fs); 10825 gen_load_fpr32(ctx, fp1, ft); 10826 gen_store_fpr32h(ctx, fp0, fd); 10827 gen_store_fpr32(ctx, fp1, fd); 10828 } 10829 break; 10830 case OPC_PLU_PS: 10831 check_ps(ctx); 10832 { 10833 TCGv_i32 fp0 = tcg_temp_new_i32(); 10834 TCGv_i32 fp1 = tcg_temp_new_i32(); 10835 10836 gen_load_fpr32(ctx, fp0, fs); 10837 gen_load_fpr32h(ctx, fp1, ft); 10838 gen_store_fpr32(ctx, fp1, fd); 10839 gen_store_fpr32h(ctx, fp0, fd); 10840 } 10841 break; 10842 case OPC_PUL_PS: 10843 check_ps(ctx); 10844 { 10845 TCGv_i32 fp0 = tcg_temp_new_i32(); 10846 TCGv_i32 fp1 = tcg_temp_new_i32(); 10847 10848 gen_load_fpr32h(ctx, fp0, fs); 10849 gen_load_fpr32(ctx, fp1, ft); 10850 gen_store_fpr32(ctx, fp1, fd); 10851 gen_store_fpr32h(ctx, fp0, fd); 10852 } 10853 break; 10854 case OPC_PUU_PS: 10855 check_ps(ctx); 10856 { 10857 TCGv_i32 fp0 = tcg_temp_new_i32(); 10858 TCGv_i32 fp1 = tcg_temp_new_i32(); 10859 10860 gen_load_fpr32h(ctx, fp0, fs); 10861 gen_load_fpr32h(ctx, fp1, ft); 10862 gen_store_fpr32(ctx, fp1, fd); 10863 gen_store_fpr32h(ctx, fp0, fd); 10864 } 10865 break; 10866 case OPC_CMP_F_PS: 10867 case OPC_CMP_UN_PS: 10868 case OPC_CMP_EQ_PS: 10869 case OPC_CMP_UEQ_PS: 10870 case OPC_CMP_OLT_PS: 10871 case OPC_CMP_ULT_PS: 10872 case OPC_CMP_OLE_PS: 10873 case OPC_CMP_ULE_PS: 10874 case OPC_CMP_SF_PS: 10875 case OPC_CMP_NGLE_PS: 10876 case OPC_CMP_SEQ_PS: 10877 case OPC_CMP_NGL_PS: 10878 case OPC_CMP_LT_PS: 10879 case OPC_CMP_NGE_PS: 10880 case OPC_CMP_LE_PS: 10881 case OPC_CMP_NGT_PS: 10882 if (ctx->opcode & (1 << 6)) { 10883 gen_cmpabs_ps(ctx, func - 48, ft, fs, cc); 10884 } else { 10885 gen_cmp_ps(ctx, func - 48, ft, fs, cc); 10886 } 10887 break; 10888 default: 10889 MIPS_INVAL("farith"); 10890 gen_reserved_instruction(ctx); 10891 return; 10892 } 10893 } 10894 10895 /* Coprocessor 3 (FPU) */ 10896 static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, 10897 int fd, int fs, int base, int index) 10898 { 10899 TCGv t0 = tcg_temp_new(); 10900 10901 if (base == 0) { 10902 gen_load_gpr(t0, index); 10903 } else if (index == 0) { 10904 gen_load_gpr(t0, base); 10905 } else { 10906 gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]); 10907 } 10908 /* 10909 * Don't do NOP if destination is zero: we must perform the actual 10910 * memory access. 10911 */ 10912 switch (opc) { 10913 case OPC_LWXC1: 10914 check_cop1x(ctx); 10915 { 10916 TCGv_i32 fp0 = tcg_temp_new_i32(); 10917 10918 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL); 10919 tcg_gen_trunc_tl_i32(fp0, t0); 10920 gen_store_fpr32(ctx, fp0, fd); 10921 } 10922 break; 10923 case OPC_LDXC1: 10924 check_cop1x(ctx); 10925 check_cp1_registers(ctx, fd); 10926 { 10927 TCGv_i64 fp0 = tcg_temp_new_i64(); 10928 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); 10929 gen_store_fpr64(ctx, fp0, fd); 10930 } 10931 break; 10932 case OPC_LUXC1: 10933 check_cp1_64bitmode(ctx); 10934 tcg_gen_andi_tl(t0, t0, ~0x7); 10935 { 10936 TCGv_i64 fp0 = tcg_temp_new_i64(); 10937 10938 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); 10939 gen_store_fpr64(ctx, fp0, fd); 10940 } 10941 break; 10942 case OPC_SWXC1: 10943 check_cop1x(ctx); 10944 { 10945 TCGv_i32 fp0 = tcg_temp_new_i32(); 10946 gen_load_fpr32(ctx, fp0, fs); 10947 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL); 10948 } 10949 break; 10950 case OPC_SDXC1: 10951 check_cop1x(ctx); 10952 check_cp1_registers(ctx, fs); 10953 { 10954 TCGv_i64 fp0 = tcg_temp_new_i64(); 10955 gen_load_fpr64(ctx, fp0, fs); 10956 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); 10957 } 10958 break; 10959 case OPC_SUXC1: 10960 check_cp1_64bitmode(ctx); 10961 tcg_gen_andi_tl(t0, t0, ~0x7); 10962 { 10963 TCGv_i64 fp0 = tcg_temp_new_i64(); 10964 gen_load_fpr64(ctx, fp0, fs); 10965 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); 10966 } 10967 break; 10968 } 10969 } 10970 10971 static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, 10972 int fd, int fr, int fs, int ft) 10973 { 10974 switch (opc) { 10975 case OPC_ALNV_PS: 10976 check_ps(ctx); 10977 { 10978 TCGv t0 = tcg_temp_new(); 10979 TCGv_i32 fp = tcg_temp_new_i32(); 10980 TCGv_i32 fph = tcg_temp_new_i32(); 10981 TCGLabel *l1 = gen_new_label(); 10982 TCGLabel *l2 = gen_new_label(); 10983 10984 gen_load_gpr(t0, fr); 10985 tcg_gen_andi_tl(t0, t0, 0x7); 10986 10987 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1); 10988 gen_load_fpr32(ctx, fp, fs); 10989 gen_load_fpr32h(ctx, fph, fs); 10990 gen_store_fpr32(ctx, fp, fd); 10991 gen_store_fpr32h(ctx, fph, fd); 10992 tcg_gen_br(l2); 10993 gen_set_label(l1); 10994 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2); 10995 if (cpu_is_bigendian(ctx)) { 10996 gen_load_fpr32(ctx, fp, fs); 10997 gen_load_fpr32h(ctx, fph, ft); 10998 gen_store_fpr32h(ctx, fp, fd); 10999 gen_store_fpr32(ctx, fph, fd); 11000 } else { 11001 gen_load_fpr32h(ctx, fph, fs); 11002 gen_load_fpr32(ctx, fp, ft); 11003 gen_store_fpr32(ctx, fph, fd); 11004 gen_store_fpr32h(ctx, fp, fd); 11005 } 11006 gen_set_label(l2); 11007 } 11008 break; 11009 case OPC_MADD_S: 11010 check_cop1x(ctx); 11011 { 11012 TCGv_i32 fp0 = tcg_temp_new_i32(); 11013 TCGv_i32 fp1 = tcg_temp_new_i32(); 11014 TCGv_i32 fp2 = tcg_temp_new_i32(); 11015 11016 gen_load_fpr32(ctx, fp0, fs); 11017 gen_load_fpr32(ctx, fp1, ft); 11018 gen_load_fpr32(ctx, fp2, fr); 11019 gen_helper_float_madd_s(fp2, cpu_env, fp0, fp1, fp2); 11020 gen_store_fpr32(ctx, fp2, fd); 11021 } 11022 break; 11023 case OPC_MADD_D: 11024 check_cop1x(ctx); 11025 check_cp1_registers(ctx, fd | fs | ft | fr); 11026 { 11027 TCGv_i64 fp0 = tcg_temp_new_i64(); 11028 TCGv_i64 fp1 = tcg_temp_new_i64(); 11029 TCGv_i64 fp2 = tcg_temp_new_i64(); 11030 11031 gen_load_fpr64(ctx, fp0, fs); 11032 gen_load_fpr64(ctx, fp1, ft); 11033 gen_load_fpr64(ctx, fp2, fr); 11034 gen_helper_float_madd_d(fp2, cpu_env, fp0, fp1, fp2); 11035 gen_store_fpr64(ctx, fp2, fd); 11036 } 11037 break; 11038 case OPC_MADD_PS: 11039 check_ps(ctx); 11040 { 11041 TCGv_i64 fp0 = tcg_temp_new_i64(); 11042 TCGv_i64 fp1 = tcg_temp_new_i64(); 11043 TCGv_i64 fp2 = tcg_temp_new_i64(); 11044 11045 gen_load_fpr64(ctx, fp0, fs); 11046 gen_load_fpr64(ctx, fp1, ft); 11047 gen_load_fpr64(ctx, fp2, fr); 11048 gen_helper_float_madd_ps(fp2, cpu_env, fp0, fp1, fp2); 11049 gen_store_fpr64(ctx, fp2, fd); 11050 } 11051 break; 11052 case OPC_MSUB_S: 11053 check_cop1x(ctx); 11054 { 11055 TCGv_i32 fp0 = tcg_temp_new_i32(); 11056 TCGv_i32 fp1 = tcg_temp_new_i32(); 11057 TCGv_i32 fp2 = tcg_temp_new_i32(); 11058 11059 gen_load_fpr32(ctx, fp0, fs); 11060 gen_load_fpr32(ctx, fp1, ft); 11061 gen_load_fpr32(ctx, fp2, fr); 11062 gen_helper_float_msub_s(fp2, cpu_env, fp0, fp1, fp2); 11063 gen_store_fpr32(ctx, fp2, fd); 11064 } 11065 break; 11066 case OPC_MSUB_D: 11067 check_cop1x(ctx); 11068 check_cp1_registers(ctx, fd | fs | ft | fr); 11069 { 11070 TCGv_i64 fp0 = tcg_temp_new_i64(); 11071 TCGv_i64 fp1 = tcg_temp_new_i64(); 11072 TCGv_i64 fp2 = tcg_temp_new_i64(); 11073 11074 gen_load_fpr64(ctx, fp0, fs); 11075 gen_load_fpr64(ctx, fp1, ft); 11076 gen_load_fpr64(ctx, fp2, fr); 11077 gen_helper_float_msub_d(fp2, cpu_env, fp0, fp1, fp2); 11078 gen_store_fpr64(ctx, fp2, fd); 11079 } 11080 break; 11081 case OPC_MSUB_PS: 11082 check_ps(ctx); 11083 { 11084 TCGv_i64 fp0 = tcg_temp_new_i64(); 11085 TCGv_i64 fp1 = tcg_temp_new_i64(); 11086 TCGv_i64 fp2 = tcg_temp_new_i64(); 11087 11088 gen_load_fpr64(ctx, fp0, fs); 11089 gen_load_fpr64(ctx, fp1, ft); 11090 gen_load_fpr64(ctx, fp2, fr); 11091 gen_helper_float_msub_ps(fp2, cpu_env, fp0, fp1, fp2); 11092 gen_store_fpr64(ctx, fp2, fd); 11093 } 11094 break; 11095 case OPC_NMADD_S: 11096 check_cop1x(ctx); 11097 { 11098 TCGv_i32 fp0 = tcg_temp_new_i32(); 11099 TCGv_i32 fp1 = tcg_temp_new_i32(); 11100 TCGv_i32 fp2 = tcg_temp_new_i32(); 11101 11102 gen_load_fpr32(ctx, fp0, fs); 11103 gen_load_fpr32(ctx, fp1, ft); 11104 gen_load_fpr32(ctx, fp2, fr); 11105 gen_helper_float_nmadd_s(fp2, cpu_env, fp0, fp1, fp2); 11106 gen_store_fpr32(ctx, fp2, fd); 11107 } 11108 break; 11109 case OPC_NMADD_D: 11110 check_cop1x(ctx); 11111 check_cp1_registers(ctx, fd | fs | ft | fr); 11112 { 11113 TCGv_i64 fp0 = tcg_temp_new_i64(); 11114 TCGv_i64 fp1 = tcg_temp_new_i64(); 11115 TCGv_i64 fp2 = tcg_temp_new_i64(); 11116 11117 gen_load_fpr64(ctx, fp0, fs); 11118 gen_load_fpr64(ctx, fp1, ft); 11119 gen_load_fpr64(ctx, fp2, fr); 11120 gen_helper_float_nmadd_d(fp2, cpu_env, fp0, fp1, fp2); 11121 gen_store_fpr64(ctx, fp2, fd); 11122 } 11123 break; 11124 case OPC_NMADD_PS: 11125 check_ps(ctx); 11126 { 11127 TCGv_i64 fp0 = tcg_temp_new_i64(); 11128 TCGv_i64 fp1 = tcg_temp_new_i64(); 11129 TCGv_i64 fp2 = tcg_temp_new_i64(); 11130 11131 gen_load_fpr64(ctx, fp0, fs); 11132 gen_load_fpr64(ctx, fp1, ft); 11133 gen_load_fpr64(ctx, fp2, fr); 11134 gen_helper_float_nmadd_ps(fp2, cpu_env, fp0, fp1, fp2); 11135 gen_store_fpr64(ctx, fp2, fd); 11136 } 11137 break; 11138 case OPC_NMSUB_S: 11139 check_cop1x(ctx); 11140 { 11141 TCGv_i32 fp0 = tcg_temp_new_i32(); 11142 TCGv_i32 fp1 = tcg_temp_new_i32(); 11143 TCGv_i32 fp2 = tcg_temp_new_i32(); 11144 11145 gen_load_fpr32(ctx, fp0, fs); 11146 gen_load_fpr32(ctx, fp1, ft); 11147 gen_load_fpr32(ctx, fp2, fr); 11148 gen_helper_float_nmsub_s(fp2, cpu_env, fp0, fp1, fp2); 11149 gen_store_fpr32(ctx, fp2, fd); 11150 } 11151 break; 11152 case OPC_NMSUB_D: 11153 check_cop1x(ctx); 11154 check_cp1_registers(ctx, fd | fs | ft | fr); 11155 { 11156 TCGv_i64 fp0 = tcg_temp_new_i64(); 11157 TCGv_i64 fp1 = tcg_temp_new_i64(); 11158 TCGv_i64 fp2 = tcg_temp_new_i64(); 11159 11160 gen_load_fpr64(ctx, fp0, fs); 11161 gen_load_fpr64(ctx, fp1, ft); 11162 gen_load_fpr64(ctx, fp2, fr); 11163 gen_helper_float_nmsub_d(fp2, cpu_env, fp0, fp1, fp2); 11164 gen_store_fpr64(ctx, fp2, fd); 11165 } 11166 break; 11167 case OPC_NMSUB_PS: 11168 check_ps(ctx); 11169 { 11170 TCGv_i64 fp0 = tcg_temp_new_i64(); 11171 TCGv_i64 fp1 = tcg_temp_new_i64(); 11172 TCGv_i64 fp2 = tcg_temp_new_i64(); 11173 11174 gen_load_fpr64(ctx, fp0, fs); 11175 gen_load_fpr64(ctx, fp1, ft); 11176 gen_load_fpr64(ctx, fp2, fr); 11177 gen_helper_float_nmsub_ps(fp2, cpu_env, fp0, fp1, fp2); 11178 gen_store_fpr64(ctx, fp2, fd); 11179 } 11180 break; 11181 default: 11182 MIPS_INVAL("flt3_arith"); 11183 gen_reserved_instruction(ctx); 11184 return; 11185 } 11186 } 11187 11188 void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel) 11189 { 11190 TCGv t0; 11191 11192 #if !defined(CONFIG_USER_ONLY) 11193 /* 11194 * The Linux kernel will emulate rdhwr if it's not supported natively. 11195 * Therefore only check the ISA in system mode. 11196 */ 11197 check_insn(ctx, ISA_MIPS_R2); 11198 #endif 11199 t0 = tcg_temp_new(); 11200 11201 switch (rd) { 11202 case 0: 11203 gen_helper_rdhwr_cpunum(t0, cpu_env); 11204 gen_store_gpr(t0, rt); 11205 break; 11206 case 1: 11207 gen_helper_rdhwr_synci_step(t0, cpu_env); 11208 gen_store_gpr(t0, rt); 11209 break; 11210 case 2: 11211 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 11212 gen_io_start(); 11213 } 11214 gen_helper_rdhwr_cc(t0, cpu_env); 11215 gen_store_gpr(t0, rt); 11216 /* 11217 * Break the TB to be able to take timer interrupts immediately 11218 * after reading count. DISAS_STOP isn't sufficient, we need to ensure 11219 * we break completely out of translated code. 11220 */ 11221 gen_save_pc(ctx->base.pc_next + 4); 11222 ctx->base.is_jmp = DISAS_EXIT; 11223 break; 11224 case 3: 11225 gen_helper_rdhwr_ccres(t0, cpu_env); 11226 gen_store_gpr(t0, rt); 11227 break; 11228 case 4: 11229 check_insn(ctx, ISA_MIPS_R6); 11230 if (sel != 0) { 11231 /* 11232 * Performance counter registers are not implemented other than 11233 * control register 0. 11234 */ 11235 generate_exception(ctx, EXCP_RI); 11236 } 11237 gen_helper_rdhwr_performance(t0, cpu_env); 11238 gen_store_gpr(t0, rt); 11239 break; 11240 case 5: 11241 check_insn(ctx, ISA_MIPS_R6); 11242 gen_helper_rdhwr_xnp(t0, cpu_env); 11243 gen_store_gpr(t0, rt); 11244 break; 11245 case 29: 11246 #if defined(CONFIG_USER_ONLY) 11247 tcg_gen_ld_tl(t0, cpu_env, 11248 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 11249 gen_store_gpr(t0, rt); 11250 break; 11251 #else 11252 if ((ctx->hflags & MIPS_HFLAG_CP0) || 11253 (ctx->hflags & MIPS_HFLAG_HWRENA_ULR)) { 11254 tcg_gen_ld_tl(t0, cpu_env, 11255 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 11256 gen_store_gpr(t0, rt); 11257 } else { 11258 gen_reserved_instruction(ctx); 11259 } 11260 break; 11261 #endif 11262 default: /* Invalid */ 11263 MIPS_INVAL("rdhwr"); 11264 gen_reserved_instruction(ctx); 11265 break; 11266 } 11267 } 11268 11269 static inline void clear_branch_hflags(DisasContext *ctx) 11270 { 11271 ctx->hflags &= ~MIPS_HFLAG_BMASK; 11272 if (ctx->base.is_jmp == DISAS_NEXT) { 11273 save_cpu_state(ctx, 0); 11274 } else { 11275 /* 11276 * It is not safe to save ctx->hflags as hflags may be changed 11277 * in execution time by the instruction in delay / forbidden slot. 11278 */ 11279 tcg_gen_andi_i32(hflags, hflags, ~MIPS_HFLAG_BMASK); 11280 } 11281 } 11282 11283 static void gen_branch(DisasContext *ctx, int insn_bytes) 11284 { 11285 if (ctx->hflags & MIPS_HFLAG_BMASK) { 11286 int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK; 11287 /* Branches completion */ 11288 clear_branch_hflags(ctx); 11289 ctx->base.is_jmp = DISAS_NORETURN; 11290 /* FIXME: Need to clear can_do_io. */ 11291 switch (proc_hflags & MIPS_HFLAG_BMASK_BASE) { 11292 case MIPS_HFLAG_FBNSLOT: 11293 gen_goto_tb(ctx, 0, ctx->base.pc_next + insn_bytes); 11294 break; 11295 case MIPS_HFLAG_B: 11296 /* unconditional branch */ 11297 if (proc_hflags & MIPS_HFLAG_BX) { 11298 tcg_gen_xori_i32(hflags, hflags, MIPS_HFLAG_M16); 11299 } 11300 gen_goto_tb(ctx, 0, ctx->btarget); 11301 break; 11302 case MIPS_HFLAG_BL: 11303 /* blikely taken case */ 11304 gen_goto_tb(ctx, 0, ctx->btarget); 11305 break; 11306 case MIPS_HFLAG_BC: 11307 /* Conditional branch */ 11308 { 11309 TCGLabel *l1 = gen_new_label(); 11310 11311 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); 11312 gen_goto_tb(ctx, 1, ctx->base.pc_next + insn_bytes); 11313 gen_set_label(l1); 11314 gen_goto_tb(ctx, 0, ctx->btarget); 11315 } 11316 break; 11317 case MIPS_HFLAG_BR: 11318 /* unconditional branch to register */ 11319 if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) { 11320 TCGv t0 = tcg_temp_new(); 11321 TCGv_i32 t1 = tcg_temp_new_i32(); 11322 11323 tcg_gen_andi_tl(t0, btarget, 0x1); 11324 tcg_gen_trunc_tl_i32(t1, t0); 11325 tcg_gen_andi_i32(hflags, hflags, ~(uint32_t)MIPS_HFLAG_M16); 11326 tcg_gen_shli_i32(t1, t1, MIPS_HFLAG_M16_SHIFT); 11327 tcg_gen_or_i32(hflags, hflags, t1); 11328 11329 tcg_gen_andi_tl(cpu_PC, btarget, ~(target_ulong)0x1); 11330 } else { 11331 tcg_gen_mov_tl(cpu_PC, btarget); 11332 } 11333 tcg_gen_lookup_and_goto_ptr(); 11334 break; 11335 default: 11336 LOG_DISAS("unknown branch 0x%x\n", proc_hflags); 11337 gen_reserved_instruction(ctx); 11338 } 11339 } 11340 } 11341 11342 /* Compact Branches */ 11343 static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, 11344 int rs, int rt, int32_t offset) 11345 { 11346 int bcond_compute = 0; 11347 TCGv t0 = tcg_temp_new(); 11348 TCGv t1 = tcg_temp_new(); 11349 int m16_lowbit = (ctx->hflags & MIPS_HFLAG_M16) != 0; 11350 11351 if (ctx->hflags & MIPS_HFLAG_BMASK) { 11352 #ifdef MIPS_DEBUG_DISAS 11353 LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx 11354 "\n", ctx->base.pc_next); 11355 #endif 11356 gen_reserved_instruction(ctx); 11357 return; 11358 } 11359 11360 /* Load needed operands and calculate btarget */ 11361 switch (opc) { 11362 /* compact branch */ 11363 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */ 11364 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */ 11365 gen_load_gpr(t0, rs); 11366 gen_load_gpr(t1, rt); 11367 bcond_compute = 1; 11368 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 11369 if (rs <= rt && rs == 0) { 11370 /* OPC_BEQZALC, OPC_BNEZALC */ 11371 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); 11372 } 11373 break; 11374 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */ 11375 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */ 11376 gen_load_gpr(t0, rs); 11377 gen_load_gpr(t1, rt); 11378 bcond_compute = 1; 11379 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 11380 break; 11381 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */ 11382 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */ 11383 if (rs == 0 || rs == rt) { 11384 /* OPC_BLEZALC, OPC_BGEZALC */ 11385 /* OPC_BGTZALC, OPC_BLTZALC */ 11386 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); 11387 } 11388 gen_load_gpr(t0, rs); 11389 gen_load_gpr(t1, rt); 11390 bcond_compute = 1; 11391 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 11392 break; 11393 case OPC_BC: 11394 case OPC_BALC: 11395 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 11396 break; 11397 case OPC_BEQZC: 11398 case OPC_BNEZC: 11399 if (rs != 0) { 11400 /* OPC_BEQZC, OPC_BNEZC */ 11401 gen_load_gpr(t0, rs); 11402 bcond_compute = 1; 11403 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 11404 } else { 11405 /* OPC_JIC, OPC_JIALC */ 11406 TCGv tbase = tcg_temp_new(); 11407 TCGv toffset = tcg_constant_tl(offset); 11408 11409 gen_load_gpr(tbase, rt); 11410 gen_op_addr_add(ctx, btarget, tbase, toffset); 11411 } 11412 break; 11413 default: 11414 MIPS_INVAL("Compact branch/jump"); 11415 gen_reserved_instruction(ctx); 11416 return; 11417 } 11418 11419 if (bcond_compute == 0) { 11420 /* Unconditional compact branch */ 11421 switch (opc) { 11422 case OPC_JIALC: 11423 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); 11424 /* Fallthrough */ 11425 case OPC_JIC: 11426 ctx->hflags |= MIPS_HFLAG_BR; 11427 break; 11428 case OPC_BALC: 11429 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); 11430 /* Fallthrough */ 11431 case OPC_BC: 11432 ctx->hflags |= MIPS_HFLAG_B; 11433 break; 11434 default: 11435 MIPS_INVAL("Compact branch/jump"); 11436 gen_reserved_instruction(ctx); 11437 return; 11438 } 11439 11440 /* Generating branch here as compact branches don't have delay slot */ 11441 gen_branch(ctx, 4); 11442 } else { 11443 /* Conditional compact branch */ 11444 TCGLabel *fs = gen_new_label(); 11445 save_cpu_state(ctx, 0); 11446 11447 switch (opc) { 11448 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */ 11449 if (rs == 0 && rt != 0) { 11450 /* OPC_BLEZALC */ 11451 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs); 11452 } else if (rs != 0 && rt != 0 && rs == rt) { 11453 /* OPC_BGEZALC */ 11454 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs); 11455 } else { 11456 /* OPC_BGEUC */ 11457 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU), t0, t1, fs); 11458 } 11459 break; 11460 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */ 11461 if (rs == 0 && rt != 0) { 11462 /* OPC_BGTZALC */ 11463 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs); 11464 } else if (rs != 0 && rt != 0 && rs == rt) { 11465 /* OPC_BLTZALC */ 11466 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs); 11467 } else { 11468 /* OPC_BLTUC */ 11469 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU), t0, t1, fs); 11470 } 11471 break; 11472 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */ 11473 if (rs == 0 && rt != 0) { 11474 /* OPC_BLEZC */ 11475 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs); 11476 } else if (rs != 0 && rt != 0 && rs == rt) { 11477 /* OPC_BGEZC */ 11478 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs); 11479 } else { 11480 /* OPC_BGEC */ 11481 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE), t0, t1, fs); 11482 } 11483 break; 11484 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */ 11485 if (rs == 0 && rt != 0) { 11486 /* OPC_BGTZC */ 11487 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs); 11488 } else if (rs != 0 && rt != 0 && rs == rt) { 11489 /* OPC_BLTZC */ 11490 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs); 11491 } else { 11492 /* OPC_BLTC */ 11493 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT), t0, t1, fs); 11494 } 11495 break; 11496 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */ 11497 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */ 11498 if (rs >= rt) { 11499 /* OPC_BOVC, OPC_BNVC */ 11500 TCGv t2 = tcg_temp_new(); 11501 TCGv t3 = tcg_temp_new(); 11502 TCGv t4 = tcg_temp_new(); 11503 TCGv input_overflow = tcg_temp_new(); 11504 11505 gen_load_gpr(t0, rs); 11506 gen_load_gpr(t1, rt); 11507 tcg_gen_ext32s_tl(t2, t0); 11508 tcg_gen_setcond_tl(TCG_COND_NE, input_overflow, t2, t0); 11509 tcg_gen_ext32s_tl(t3, t1); 11510 tcg_gen_setcond_tl(TCG_COND_NE, t4, t3, t1); 11511 tcg_gen_or_tl(input_overflow, input_overflow, t4); 11512 11513 tcg_gen_add_tl(t4, t2, t3); 11514 tcg_gen_ext32s_tl(t4, t4); 11515 tcg_gen_xor_tl(t2, t2, t3); 11516 tcg_gen_xor_tl(t3, t4, t3); 11517 tcg_gen_andc_tl(t2, t3, t2); 11518 tcg_gen_setcondi_tl(TCG_COND_LT, t4, t2, 0); 11519 tcg_gen_or_tl(t4, t4, input_overflow); 11520 if (opc == OPC_BOVC) { 11521 /* OPC_BOVC */ 11522 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t4, 0, fs); 11523 } else { 11524 /* OPC_BNVC */ 11525 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t4, 0, fs); 11526 } 11527 } else if (rs < rt && rs == 0) { 11528 /* OPC_BEQZALC, OPC_BNEZALC */ 11529 if (opc == OPC_BEQZALC) { 11530 /* OPC_BEQZALC */ 11531 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t1, 0, fs); 11532 } else { 11533 /* OPC_BNEZALC */ 11534 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t1, 0, fs); 11535 } 11536 } else { 11537 /* OPC_BEQC, OPC_BNEC */ 11538 if (opc == OPC_BEQC) { 11539 /* OPC_BEQC */ 11540 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ), t0, t1, fs); 11541 } else { 11542 /* OPC_BNEC */ 11543 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE), t0, t1, fs); 11544 } 11545 } 11546 break; 11547 case OPC_BEQZC: 11548 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t0, 0, fs); 11549 break; 11550 case OPC_BNEZC: 11551 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t0, 0, fs); 11552 break; 11553 default: 11554 MIPS_INVAL("Compact conditional branch/jump"); 11555 gen_reserved_instruction(ctx); 11556 return; 11557 } 11558 11559 /* Generating branch here as compact branches don't have delay slot */ 11560 gen_goto_tb(ctx, 1, ctx->btarget); 11561 gen_set_label(fs); 11562 11563 ctx->hflags |= MIPS_HFLAG_FBNSLOT; 11564 } 11565 } 11566 11567 void gen_addiupc(DisasContext *ctx, int rx, int imm, 11568 int is_64_bit, int extended) 11569 { 11570 TCGv t0; 11571 11572 if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) { 11573 gen_reserved_instruction(ctx); 11574 return; 11575 } 11576 11577 t0 = tcg_temp_new(); 11578 11579 tcg_gen_movi_tl(t0, pc_relative_pc(ctx)); 11580 tcg_gen_addi_tl(cpu_gpr[rx], t0, imm); 11581 if (!is_64_bit) { 11582 tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]); 11583 } 11584 } 11585 11586 static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base, 11587 int16_t offset) 11588 { 11589 TCGv_i32 t0 = tcg_const_i32(op); 11590 TCGv t1 = tcg_temp_new(); 11591 gen_base_offset_addr(ctx, t1, base, offset); 11592 gen_helper_cache(cpu_env, t1, t0); 11593 } 11594 11595 static inline bool is_uhi(DisasContext *ctx, int sdbbp_code) 11596 { 11597 #ifdef CONFIG_USER_ONLY 11598 return false; 11599 #else 11600 bool is_user = (ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM; 11601 return semihosting_enabled(is_user) && sdbbp_code == 1; 11602 #endif 11603 } 11604 11605 void gen_ldxs(DisasContext *ctx, int base, int index, int rd) 11606 { 11607 TCGv t0 = tcg_temp_new(); 11608 TCGv t1 = tcg_temp_new(); 11609 11610 gen_load_gpr(t0, base); 11611 11612 if (index != 0) { 11613 gen_load_gpr(t1, index); 11614 tcg_gen_shli_tl(t1, t1, 2); 11615 gen_op_addr_add(ctx, t0, t1, t0); 11616 } 11617 11618 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); 11619 gen_store_gpr(t1, rd); 11620 } 11621 11622 static void gen_sync(int stype) 11623 { 11624 TCGBar tcg_mo = TCG_BAR_SC; 11625 11626 switch (stype) { 11627 case 0x4: /* SYNC_WMB */ 11628 tcg_mo |= TCG_MO_ST_ST; 11629 break; 11630 case 0x10: /* SYNC_MB */ 11631 tcg_mo |= TCG_MO_ALL; 11632 break; 11633 case 0x11: /* SYNC_ACQUIRE */ 11634 tcg_mo |= TCG_MO_LD_LD | TCG_MO_LD_ST; 11635 break; 11636 case 0x12: /* SYNC_RELEASE */ 11637 tcg_mo |= TCG_MO_ST_ST | TCG_MO_LD_ST; 11638 break; 11639 case 0x13: /* SYNC_RMB */ 11640 tcg_mo |= TCG_MO_LD_LD; 11641 break; 11642 default: 11643 tcg_mo |= TCG_MO_ALL; 11644 break; 11645 } 11646 11647 tcg_gen_mb(tcg_mo); 11648 } 11649 11650 /* ISA extensions (ASEs) */ 11651 11652 /* MIPS16 extension to MIPS32 */ 11653 #include "mips16e_translate.c.inc" 11654 11655 /* microMIPS extension to MIPS32/MIPS64 */ 11656 11657 /* 11658 * Values for microMIPS fmt field. Variable-width, depending on which 11659 * formats the instruction supports. 11660 */ 11661 enum { 11662 FMT_SD_S = 0, 11663 FMT_SD_D = 1, 11664 11665 FMT_SDPS_S = 0, 11666 FMT_SDPS_D = 1, 11667 FMT_SDPS_PS = 2, 11668 11669 FMT_SWL_S = 0, 11670 FMT_SWL_W = 1, 11671 FMT_SWL_L = 2, 11672 11673 FMT_DWL_D = 0, 11674 FMT_DWL_W = 1, 11675 FMT_DWL_L = 2 11676 }; 11677 11678 #include "micromips_translate.c.inc" 11679 11680 #include "nanomips_translate.c.inc" 11681 11682 /* MIPSDSP functions. */ 11683 11684 /* Indexed load is not for DSP only */ 11685 static void gen_mips_lx(DisasContext *ctx, uint32_t opc, 11686 int rd, int base, int offset) 11687 { 11688 TCGv t0; 11689 11690 if (!(ctx->insn_flags & INSN_OCTEON)) { 11691 check_dsp(ctx); 11692 } 11693 t0 = tcg_temp_new(); 11694 11695 if (base == 0) { 11696 gen_load_gpr(t0, offset); 11697 } else if (offset == 0) { 11698 gen_load_gpr(t0, base); 11699 } else { 11700 gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]); 11701 } 11702 11703 switch (opc) { 11704 case OPC_LBUX: 11705 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB); 11706 gen_store_gpr(t0, rd); 11707 break; 11708 case OPC_LHX: 11709 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW); 11710 gen_store_gpr(t0, rd); 11711 break; 11712 case OPC_LWX: 11713 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL); 11714 gen_store_gpr(t0, rd); 11715 break; 11716 #if defined(TARGET_MIPS64) 11717 case OPC_LDX: 11718 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ); 11719 gen_store_gpr(t0, rd); 11720 break; 11721 #endif 11722 } 11723 } 11724 11725 static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2, 11726 int ret, int v1, int v2) 11727 { 11728 TCGv v1_t; 11729 TCGv v2_t; 11730 11731 if (ret == 0) { 11732 /* Treat as NOP. */ 11733 return; 11734 } 11735 11736 v1_t = tcg_temp_new(); 11737 v2_t = tcg_temp_new(); 11738 11739 gen_load_gpr(v1_t, v1); 11740 gen_load_gpr(v2_t, v2); 11741 11742 switch (op1) { 11743 /* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */ 11744 case OPC_MULT_G_2E: 11745 check_dsp_r2(ctx); 11746 switch (op2) { 11747 case OPC_ADDUH_QB: 11748 gen_helper_adduh_qb(cpu_gpr[ret], v1_t, v2_t); 11749 break; 11750 case OPC_ADDUH_R_QB: 11751 gen_helper_adduh_r_qb(cpu_gpr[ret], v1_t, v2_t); 11752 break; 11753 case OPC_ADDQH_PH: 11754 gen_helper_addqh_ph(cpu_gpr[ret], v1_t, v2_t); 11755 break; 11756 case OPC_ADDQH_R_PH: 11757 gen_helper_addqh_r_ph(cpu_gpr[ret], v1_t, v2_t); 11758 break; 11759 case OPC_ADDQH_W: 11760 gen_helper_addqh_w(cpu_gpr[ret], v1_t, v2_t); 11761 break; 11762 case OPC_ADDQH_R_W: 11763 gen_helper_addqh_r_w(cpu_gpr[ret], v1_t, v2_t); 11764 break; 11765 case OPC_SUBUH_QB: 11766 gen_helper_subuh_qb(cpu_gpr[ret], v1_t, v2_t); 11767 break; 11768 case OPC_SUBUH_R_QB: 11769 gen_helper_subuh_r_qb(cpu_gpr[ret], v1_t, v2_t); 11770 break; 11771 case OPC_SUBQH_PH: 11772 gen_helper_subqh_ph(cpu_gpr[ret], v1_t, v2_t); 11773 break; 11774 case OPC_SUBQH_R_PH: 11775 gen_helper_subqh_r_ph(cpu_gpr[ret], v1_t, v2_t); 11776 break; 11777 case OPC_SUBQH_W: 11778 gen_helper_subqh_w(cpu_gpr[ret], v1_t, v2_t); 11779 break; 11780 case OPC_SUBQH_R_W: 11781 gen_helper_subqh_r_w(cpu_gpr[ret], v1_t, v2_t); 11782 break; 11783 } 11784 break; 11785 case OPC_ABSQ_S_PH_DSP: 11786 switch (op2) { 11787 case OPC_ABSQ_S_QB: 11788 check_dsp_r2(ctx); 11789 gen_helper_absq_s_qb(cpu_gpr[ret], v2_t, cpu_env); 11790 break; 11791 case OPC_ABSQ_S_PH: 11792 check_dsp(ctx); 11793 gen_helper_absq_s_ph(cpu_gpr[ret], v2_t, cpu_env); 11794 break; 11795 case OPC_ABSQ_S_W: 11796 check_dsp(ctx); 11797 gen_helper_absq_s_w(cpu_gpr[ret], v2_t, cpu_env); 11798 break; 11799 case OPC_PRECEQ_W_PHL: 11800 check_dsp(ctx); 11801 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFF0000); 11802 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); 11803 break; 11804 case OPC_PRECEQ_W_PHR: 11805 check_dsp(ctx); 11806 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0x0000FFFF); 11807 tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 16); 11808 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); 11809 break; 11810 case OPC_PRECEQU_PH_QBL: 11811 check_dsp(ctx); 11812 gen_helper_precequ_ph_qbl(cpu_gpr[ret], v2_t); 11813 break; 11814 case OPC_PRECEQU_PH_QBR: 11815 check_dsp(ctx); 11816 gen_helper_precequ_ph_qbr(cpu_gpr[ret], v2_t); 11817 break; 11818 case OPC_PRECEQU_PH_QBLA: 11819 check_dsp(ctx); 11820 gen_helper_precequ_ph_qbla(cpu_gpr[ret], v2_t); 11821 break; 11822 case OPC_PRECEQU_PH_QBRA: 11823 check_dsp(ctx); 11824 gen_helper_precequ_ph_qbra(cpu_gpr[ret], v2_t); 11825 break; 11826 case OPC_PRECEU_PH_QBL: 11827 check_dsp(ctx); 11828 gen_helper_preceu_ph_qbl(cpu_gpr[ret], v2_t); 11829 break; 11830 case OPC_PRECEU_PH_QBR: 11831 check_dsp(ctx); 11832 gen_helper_preceu_ph_qbr(cpu_gpr[ret], v2_t); 11833 break; 11834 case OPC_PRECEU_PH_QBLA: 11835 check_dsp(ctx); 11836 gen_helper_preceu_ph_qbla(cpu_gpr[ret], v2_t); 11837 break; 11838 case OPC_PRECEU_PH_QBRA: 11839 check_dsp(ctx); 11840 gen_helper_preceu_ph_qbra(cpu_gpr[ret], v2_t); 11841 break; 11842 } 11843 break; 11844 case OPC_ADDU_QB_DSP: 11845 switch (op2) { 11846 case OPC_ADDQ_PH: 11847 check_dsp(ctx); 11848 gen_helper_addq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11849 break; 11850 case OPC_ADDQ_S_PH: 11851 check_dsp(ctx); 11852 gen_helper_addq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11853 break; 11854 case OPC_ADDQ_S_W: 11855 check_dsp(ctx); 11856 gen_helper_addq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11857 break; 11858 case OPC_ADDU_QB: 11859 check_dsp(ctx); 11860 gen_helper_addu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11861 break; 11862 case OPC_ADDU_S_QB: 11863 check_dsp(ctx); 11864 gen_helper_addu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11865 break; 11866 case OPC_ADDU_PH: 11867 check_dsp_r2(ctx); 11868 gen_helper_addu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11869 break; 11870 case OPC_ADDU_S_PH: 11871 check_dsp_r2(ctx); 11872 gen_helper_addu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11873 break; 11874 case OPC_SUBQ_PH: 11875 check_dsp(ctx); 11876 gen_helper_subq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11877 break; 11878 case OPC_SUBQ_S_PH: 11879 check_dsp(ctx); 11880 gen_helper_subq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11881 break; 11882 case OPC_SUBQ_S_W: 11883 check_dsp(ctx); 11884 gen_helper_subq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11885 break; 11886 case OPC_SUBU_QB: 11887 check_dsp(ctx); 11888 gen_helper_subu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11889 break; 11890 case OPC_SUBU_S_QB: 11891 check_dsp(ctx); 11892 gen_helper_subu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11893 break; 11894 case OPC_SUBU_PH: 11895 check_dsp_r2(ctx); 11896 gen_helper_subu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11897 break; 11898 case OPC_SUBU_S_PH: 11899 check_dsp_r2(ctx); 11900 gen_helper_subu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11901 break; 11902 case OPC_ADDSC: 11903 check_dsp(ctx); 11904 gen_helper_addsc(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11905 break; 11906 case OPC_ADDWC: 11907 check_dsp(ctx); 11908 gen_helper_addwc(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11909 break; 11910 case OPC_MODSUB: 11911 check_dsp(ctx); 11912 gen_helper_modsub(cpu_gpr[ret], v1_t, v2_t); 11913 break; 11914 case OPC_RADDU_W_QB: 11915 check_dsp(ctx); 11916 gen_helper_raddu_w_qb(cpu_gpr[ret], v1_t); 11917 break; 11918 } 11919 break; 11920 case OPC_CMPU_EQ_QB_DSP: 11921 switch (op2) { 11922 case OPC_PRECR_QB_PH: 11923 check_dsp_r2(ctx); 11924 gen_helper_precr_qb_ph(cpu_gpr[ret], v1_t, v2_t); 11925 break; 11926 case OPC_PRECRQ_QB_PH: 11927 check_dsp(ctx); 11928 gen_helper_precrq_qb_ph(cpu_gpr[ret], v1_t, v2_t); 11929 break; 11930 case OPC_PRECR_SRA_PH_W: 11931 check_dsp_r2(ctx); 11932 { 11933 TCGv_i32 sa_t = tcg_const_i32(v2); 11934 gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t, v1_t, 11935 cpu_gpr[ret]); 11936 break; 11937 } 11938 case OPC_PRECR_SRA_R_PH_W: 11939 check_dsp_r2(ctx); 11940 { 11941 TCGv_i32 sa_t = tcg_const_i32(v2); 11942 gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t, v1_t, 11943 cpu_gpr[ret]); 11944 break; 11945 } 11946 case OPC_PRECRQ_PH_W: 11947 check_dsp(ctx); 11948 gen_helper_precrq_ph_w(cpu_gpr[ret], v1_t, v2_t); 11949 break; 11950 case OPC_PRECRQ_RS_PH_W: 11951 check_dsp(ctx); 11952 gen_helper_precrq_rs_ph_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11953 break; 11954 case OPC_PRECRQU_S_QB_PH: 11955 check_dsp(ctx); 11956 gen_helper_precrqu_s_qb_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 11957 break; 11958 } 11959 break; 11960 #ifdef TARGET_MIPS64 11961 case OPC_ABSQ_S_QH_DSP: 11962 switch (op2) { 11963 case OPC_PRECEQ_L_PWL: 11964 check_dsp(ctx); 11965 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFFFFFF00000000ull); 11966 break; 11967 case OPC_PRECEQ_L_PWR: 11968 check_dsp(ctx); 11969 tcg_gen_shli_tl(cpu_gpr[ret], v2_t, 32); 11970 break; 11971 case OPC_PRECEQ_PW_QHL: 11972 check_dsp(ctx); 11973 gen_helper_preceq_pw_qhl(cpu_gpr[ret], v2_t); 11974 break; 11975 case OPC_PRECEQ_PW_QHR: 11976 check_dsp(ctx); 11977 gen_helper_preceq_pw_qhr(cpu_gpr[ret], v2_t); 11978 break; 11979 case OPC_PRECEQ_PW_QHLA: 11980 check_dsp(ctx); 11981 gen_helper_preceq_pw_qhla(cpu_gpr[ret], v2_t); 11982 break; 11983 case OPC_PRECEQ_PW_QHRA: 11984 check_dsp(ctx); 11985 gen_helper_preceq_pw_qhra(cpu_gpr[ret], v2_t); 11986 break; 11987 case OPC_PRECEQU_QH_OBL: 11988 check_dsp(ctx); 11989 gen_helper_precequ_qh_obl(cpu_gpr[ret], v2_t); 11990 break; 11991 case OPC_PRECEQU_QH_OBR: 11992 check_dsp(ctx); 11993 gen_helper_precequ_qh_obr(cpu_gpr[ret], v2_t); 11994 break; 11995 case OPC_PRECEQU_QH_OBLA: 11996 check_dsp(ctx); 11997 gen_helper_precequ_qh_obla(cpu_gpr[ret], v2_t); 11998 break; 11999 case OPC_PRECEQU_QH_OBRA: 12000 check_dsp(ctx); 12001 gen_helper_precequ_qh_obra(cpu_gpr[ret], v2_t); 12002 break; 12003 case OPC_PRECEU_QH_OBL: 12004 check_dsp(ctx); 12005 gen_helper_preceu_qh_obl(cpu_gpr[ret], v2_t); 12006 break; 12007 case OPC_PRECEU_QH_OBR: 12008 check_dsp(ctx); 12009 gen_helper_preceu_qh_obr(cpu_gpr[ret], v2_t); 12010 break; 12011 case OPC_PRECEU_QH_OBLA: 12012 check_dsp(ctx); 12013 gen_helper_preceu_qh_obla(cpu_gpr[ret], v2_t); 12014 break; 12015 case OPC_PRECEU_QH_OBRA: 12016 check_dsp(ctx); 12017 gen_helper_preceu_qh_obra(cpu_gpr[ret], v2_t); 12018 break; 12019 case OPC_ABSQ_S_OB: 12020 check_dsp_r2(ctx); 12021 gen_helper_absq_s_ob(cpu_gpr[ret], v2_t, cpu_env); 12022 break; 12023 case OPC_ABSQ_S_PW: 12024 check_dsp(ctx); 12025 gen_helper_absq_s_pw(cpu_gpr[ret], v2_t, cpu_env); 12026 break; 12027 case OPC_ABSQ_S_QH: 12028 check_dsp(ctx); 12029 gen_helper_absq_s_qh(cpu_gpr[ret], v2_t, cpu_env); 12030 break; 12031 } 12032 break; 12033 case OPC_ADDU_OB_DSP: 12034 switch (op2) { 12035 case OPC_RADDU_L_OB: 12036 check_dsp(ctx); 12037 gen_helper_raddu_l_ob(cpu_gpr[ret], v1_t); 12038 break; 12039 case OPC_SUBQ_PW: 12040 check_dsp(ctx); 12041 gen_helper_subq_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12042 break; 12043 case OPC_SUBQ_S_PW: 12044 check_dsp(ctx); 12045 gen_helper_subq_s_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12046 break; 12047 case OPC_SUBQ_QH: 12048 check_dsp(ctx); 12049 gen_helper_subq_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12050 break; 12051 case OPC_SUBQ_S_QH: 12052 check_dsp(ctx); 12053 gen_helper_subq_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12054 break; 12055 case OPC_SUBU_OB: 12056 check_dsp(ctx); 12057 gen_helper_subu_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12058 break; 12059 case OPC_SUBU_S_OB: 12060 check_dsp(ctx); 12061 gen_helper_subu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12062 break; 12063 case OPC_SUBU_QH: 12064 check_dsp_r2(ctx); 12065 gen_helper_subu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12066 break; 12067 case OPC_SUBU_S_QH: 12068 check_dsp_r2(ctx); 12069 gen_helper_subu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12070 break; 12071 case OPC_SUBUH_OB: 12072 check_dsp_r2(ctx); 12073 gen_helper_subuh_ob(cpu_gpr[ret], v1_t, v2_t); 12074 break; 12075 case OPC_SUBUH_R_OB: 12076 check_dsp_r2(ctx); 12077 gen_helper_subuh_r_ob(cpu_gpr[ret], v1_t, v2_t); 12078 break; 12079 case OPC_ADDQ_PW: 12080 check_dsp(ctx); 12081 gen_helper_addq_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12082 break; 12083 case OPC_ADDQ_S_PW: 12084 check_dsp(ctx); 12085 gen_helper_addq_s_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12086 break; 12087 case OPC_ADDQ_QH: 12088 check_dsp(ctx); 12089 gen_helper_addq_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12090 break; 12091 case OPC_ADDQ_S_QH: 12092 check_dsp(ctx); 12093 gen_helper_addq_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12094 break; 12095 case OPC_ADDU_OB: 12096 check_dsp(ctx); 12097 gen_helper_addu_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12098 break; 12099 case OPC_ADDU_S_OB: 12100 check_dsp(ctx); 12101 gen_helper_addu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12102 break; 12103 case OPC_ADDU_QH: 12104 check_dsp_r2(ctx); 12105 gen_helper_addu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12106 break; 12107 case OPC_ADDU_S_QH: 12108 check_dsp_r2(ctx); 12109 gen_helper_addu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12110 break; 12111 case OPC_ADDUH_OB: 12112 check_dsp_r2(ctx); 12113 gen_helper_adduh_ob(cpu_gpr[ret], v1_t, v2_t); 12114 break; 12115 case OPC_ADDUH_R_OB: 12116 check_dsp_r2(ctx); 12117 gen_helper_adduh_r_ob(cpu_gpr[ret], v1_t, v2_t); 12118 break; 12119 } 12120 break; 12121 case OPC_CMPU_EQ_OB_DSP: 12122 switch (op2) { 12123 case OPC_PRECR_OB_QH: 12124 check_dsp_r2(ctx); 12125 gen_helper_precr_ob_qh(cpu_gpr[ret], v1_t, v2_t); 12126 break; 12127 case OPC_PRECR_SRA_QH_PW: 12128 check_dsp_r2(ctx); 12129 { 12130 TCGv_i32 ret_t = tcg_const_i32(ret); 12131 gen_helper_precr_sra_qh_pw(v2_t, v1_t, v2_t, ret_t); 12132 break; 12133 } 12134 case OPC_PRECR_SRA_R_QH_PW: 12135 check_dsp_r2(ctx); 12136 { 12137 TCGv_i32 sa_v = tcg_const_i32(ret); 12138 gen_helper_precr_sra_r_qh_pw(v2_t, v1_t, v2_t, sa_v); 12139 break; 12140 } 12141 case OPC_PRECRQ_OB_QH: 12142 check_dsp(ctx); 12143 gen_helper_precrq_ob_qh(cpu_gpr[ret], v1_t, v2_t); 12144 break; 12145 case OPC_PRECRQ_PW_L: 12146 check_dsp(ctx); 12147 gen_helper_precrq_pw_l(cpu_gpr[ret], v1_t, v2_t); 12148 break; 12149 case OPC_PRECRQ_QH_PW: 12150 check_dsp(ctx); 12151 gen_helper_precrq_qh_pw(cpu_gpr[ret], v1_t, v2_t); 12152 break; 12153 case OPC_PRECRQ_RS_QH_PW: 12154 check_dsp(ctx); 12155 gen_helper_precrq_rs_qh_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12156 break; 12157 case OPC_PRECRQU_S_OB_QH: 12158 check_dsp(ctx); 12159 gen_helper_precrqu_s_ob_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12160 break; 12161 } 12162 break; 12163 #endif 12164 } 12165 } 12166 12167 static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc, 12168 int ret, int v1, int v2) 12169 { 12170 uint32_t op2; 12171 TCGv t0; 12172 TCGv v1_t; 12173 TCGv v2_t; 12174 12175 if (ret == 0) { 12176 /* Treat as NOP. */ 12177 return; 12178 } 12179 12180 t0 = tcg_temp_new(); 12181 v1_t = tcg_temp_new(); 12182 v2_t = tcg_temp_new(); 12183 12184 tcg_gen_movi_tl(t0, v1); 12185 gen_load_gpr(v1_t, v1); 12186 gen_load_gpr(v2_t, v2); 12187 12188 switch (opc) { 12189 case OPC_SHLL_QB_DSP: 12190 { 12191 op2 = MASK_SHLL_QB(ctx->opcode); 12192 switch (op2) { 12193 case OPC_SHLL_QB: 12194 check_dsp(ctx); 12195 gen_helper_shll_qb(cpu_gpr[ret], t0, v2_t, cpu_env); 12196 break; 12197 case OPC_SHLLV_QB: 12198 check_dsp(ctx); 12199 gen_helper_shll_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12200 break; 12201 case OPC_SHLL_PH: 12202 check_dsp(ctx); 12203 gen_helper_shll_ph(cpu_gpr[ret], t0, v2_t, cpu_env); 12204 break; 12205 case OPC_SHLLV_PH: 12206 check_dsp(ctx); 12207 gen_helper_shll_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12208 break; 12209 case OPC_SHLL_S_PH: 12210 check_dsp(ctx); 12211 gen_helper_shll_s_ph(cpu_gpr[ret], t0, v2_t, cpu_env); 12212 break; 12213 case OPC_SHLLV_S_PH: 12214 check_dsp(ctx); 12215 gen_helper_shll_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12216 break; 12217 case OPC_SHLL_S_W: 12218 check_dsp(ctx); 12219 gen_helper_shll_s_w(cpu_gpr[ret], t0, v2_t, cpu_env); 12220 break; 12221 case OPC_SHLLV_S_W: 12222 check_dsp(ctx); 12223 gen_helper_shll_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12224 break; 12225 case OPC_SHRL_QB: 12226 check_dsp(ctx); 12227 gen_helper_shrl_qb(cpu_gpr[ret], t0, v2_t); 12228 break; 12229 case OPC_SHRLV_QB: 12230 check_dsp(ctx); 12231 gen_helper_shrl_qb(cpu_gpr[ret], v1_t, v2_t); 12232 break; 12233 case OPC_SHRL_PH: 12234 check_dsp_r2(ctx); 12235 gen_helper_shrl_ph(cpu_gpr[ret], t0, v2_t); 12236 break; 12237 case OPC_SHRLV_PH: 12238 check_dsp_r2(ctx); 12239 gen_helper_shrl_ph(cpu_gpr[ret], v1_t, v2_t); 12240 break; 12241 case OPC_SHRA_QB: 12242 check_dsp_r2(ctx); 12243 gen_helper_shra_qb(cpu_gpr[ret], t0, v2_t); 12244 break; 12245 case OPC_SHRA_R_QB: 12246 check_dsp_r2(ctx); 12247 gen_helper_shra_r_qb(cpu_gpr[ret], t0, v2_t); 12248 break; 12249 case OPC_SHRAV_QB: 12250 check_dsp_r2(ctx); 12251 gen_helper_shra_qb(cpu_gpr[ret], v1_t, v2_t); 12252 break; 12253 case OPC_SHRAV_R_QB: 12254 check_dsp_r2(ctx); 12255 gen_helper_shra_r_qb(cpu_gpr[ret], v1_t, v2_t); 12256 break; 12257 case OPC_SHRA_PH: 12258 check_dsp(ctx); 12259 gen_helper_shra_ph(cpu_gpr[ret], t0, v2_t); 12260 break; 12261 case OPC_SHRA_R_PH: 12262 check_dsp(ctx); 12263 gen_helper_shra_r_ph(cpu_gpr[ret], t0, v2_t); 12264 break; 12265 case OPC_SHRAV_PH: 12266 check_dsp(ctx); 12267 gen_helper_shra_ph(cpu_gpr[ret], v1_t, v2_t); 12268 break; 12269 case OPC_SHRAV_R_PH: 12270 check_dsp(ctx); 12271 gen_helper_shra_r_ph(cpu_gpr[ret], v1_t, v2_t); 12272 break; 12273 case OPC_SHRA_R_W: 12274 check_dsp(ctx); 12275 gen_helper_shra_r_w(cpu_gpr[ret], t0, v2_t); 12276 break; 12277 case OPC_SHRAV_R_W: 12278 check_dsp(ctx); 12279 gen_helper_shra_r_w(cpu_gpr[ret], v1_t, v2_t); 12280 break; 12281 default: /* Invalid */ 12282 MIPS_INVAL("MASK SHLL.QB"); 12283 gen_reserved_instruction(ctx); 12284 break; 12285 } 12286 break; 12287 } 12288 #ifdef TARGET_MIPS64 12289 case OPC_SHLL_OB_DSP: 12290 op2 = MASK_SHLL_OB(ctx->opcode); 12291 switch (op2) { 12292 case OPC_SHLL_PW: 12293 check_dsp(ctx); 12294 gen_helper_shll_pw(cpu_gpr[ret], v2_t, t0, cpu_env); 12295 break; 12296 case OPC_SHLLV_PW: 12297 check_dsp(ctx); 12298 gen_helper_shll_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env); 12299 break; 12300 case OPC_SHLL_S_PW: 12301 check_dsp(ctx); 12302 gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, t0, cpu_env); 12303 break; 12304 case OPC_SHLLV_S_PW: 12305 check_dsp(ctx); 12306 gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env); 12307 break; 12308 case OPC_SHLL_OB: 12309 check_dsp(ctx); 12310 gen_helper_shll_ob(cpu_gpr[ret], v2_t, t0, cpu_env); 12311 break; 12312 case OPC_SHLLV_OB: 12313 check_dsp(ctx); 12314 gen_helper_shll_ob(cpu_gpr[ret], v2_t, v1_t, cpu_env); 12315 break; 12316 case OPC_SHLL_QH: 12317 check_dsp(ctx); 12318 gen_helper_shll_qh(cpu_gpr[ret], v2_t, t0, cpu_env); 12319 break; 12320 case OPC_SHLLV_QH: 12321 check_dsp(ctx); 12322 gen_helper_shll_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env); 12323 break; 12324 case OPC_SHLL_S_QH: 12325 check_dsp(ctx); 12326 gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, t0, cpu_env); 12327 break; 12328 case OPC_SHLLV_S_QH: 12329 check_dsp(ctx); 12330 gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env); 12331 break; 12332 case OPC_SHRA_OB: 12333 check_dsp_r2(ctx); 12334 gen_helper_shra_ob(cpu_gpr[ret], v2_t, t0); 12335 break; 12336 case OPC_SHRAV_OB: 12337 check_dsp_r2(ctx); 12338 gen_helper_shra_ob(cpu_gpr[ret], v2_t, v1_t); 12339 break; 12340 case OPC_SHRA_R_OB: 12341 check_dsp_r2(ctx); 12342 gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, t0); 12343 break; 12344 case OPC_SHRAV_R_OB: 12345 check_dsp_r2(ctx); 12346 gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, v1_t); 12347 break; 12348 case OPC_SHRA_PW: 12349 check_dsp(ctx); 12350 gen_helper_shra_pw(cpu_gpr[ret], v2_t, t0); 12351 break; 12352 case OPC_SHRAV_PW: 12353 check_dsp(ctx); 12354 gen_helper_shra_pw(cpu_gpr[ret], v2_t, v1_t); 12355 break; 12356 case OPC_SHRA_R_PW: 12357 check_dsp(ctx); 12358 gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, t0); 12359 break; 12360 case OPC_SHRAV_R_PW: 12361 check_dsp(ctx); 12362 gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, v1_t); 12363 break; 12364 case OPC_SHRA_QH: 12365 check_dsp(ctx); 12366 gen_helper_shra_qh(cpu_gpr[ret], v2_t, t0); 12367 break; 12368 case OPC_SHRAV_QH: 12369 check_dsp(ctx); 12370 gen_helper_shra_qh(cpu_gpr[ret], v2_t, v1_t); 12371 break; 12372 case OPC_SHRA_R_QH: 12373 check_dsp(ctx); 12374 gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, t0); 12375 break; 12376 case OPC_SHRAV_R_QH: 12377 check_dsp(ctx); 12378 gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, v1_t); 12379 break; 12380 case OPC_SHRL_OB: 12381 check_dsp(ctx); 12382 gen_helper_shrl_ob(cpu_gpr[ret], v2_t, t0); 12383 break; 12384 case OPC_SHRLV_OB: 12385 check_dsp(ctx); 12386 gen_helper_shrl_ob(cpu_gpr[ret], v2_t, v1_t); 12387 break; 12388 case OPC_SHRL_QH: 12389 check_dsp_r2(ctx); 12390 gen_helper_shrl_qh(cpu_gpr[ret], v2_t, t0); 12391 break; 12392 case OPC_SHRLV_QH: 12393 check_dsp_r2(ctx); 12394 gen_helper_shrl_qh(cpu_gpr[ret], v2_t, v1_t); 12395 break; 12396 default: /* Invalid */ 12397 MIPS_INVAL("MASK SHLL.OB"); 12398 gen_reserved_instruction(ctx); 12399 break; 12400 } 12401 break; 12402 #endif 12403 } 12404 } 12405 12406 static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2, 12407 int ret, int v1, int v2, int check_ret) 12408 { 12409 TCGv_i32 t0; 12410 TCGv v1_t; 12411 TCGv v2_t; 12412 12413 if ((ret == 0) && (check_ret == 1)) { 12414 /* Treat as NOP. */ 12415 return; 12416 } 12417 12418 t0 = tcg_temp_new_i32(); 12419 v1_t = tcg_temp_new(); 12420 v2_t = tcg_temp_new(); 12421 12422 tcg_gen_movi_i32(t0, ret); 12423 gen_load_gpr(v1_t, v1); 12424 gen_load_gpr(v2_t, v2); 12425 12426 switch (op1) { 12427 /* 12428 * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have 12429 * the same mask and op1. 12430 */ 12431 case OPC_MULT_G_2E: 12432 check_dsp_r2(ctx); 12433 switch (op2) { 12434 case OPC_MUL_PH: 12435 gen_helper_mul_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12436 break; 12437 case OPC_MUL_S_PH: 12438 gen_helper_mul_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12439 break; 12440 case OPC_MULQ_S_W: 12441 gen_helper_mulq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12442 break; 12443 case OPC_MULQ_RS_W: 12444 gen_helper_mulq_rs_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12445 break; 12446 } 12447 break; 12448 case OPC_DPA_W_PH_DSP: 12449 switch (op2) { 12450 case OPC_DPAU_H_QBL: 12451 check_dsp(ctx); 12452 gen_helper_dpau_h_qbl(t0, v1_t, v2_t, cpu_env); 12453 break; 12454 case OPC_DPAU_H_QBR: 12455 check_dsp(ctx); 12456 gen_helper_dpau_h_qbr(t0, v1_t, v2_t, cpu_env); 12457 break; 12458 case OPC_DPSU_H_QBL: 12459 check_dsp(ctx); 12460 gen_helper_dpsu_h_qbl(t0, v1_t, v2_t, cpu_env); 12461 break; 12462 case OPC_DPSU_H_QBR: 12463 check_dsp(ctx); 12464 gen_helper_dpsu_h_qbr(t0, v1_t, v2_t, cpu_env); 12465 break; 12466 case OPC_DPA_W_PH: 12467 check_dsp_r2(ctx); 12468 gen_helper_dpa_w_ph(t0, v1_t, v2_t, cpu_env); 12469 break; 12470 case OPC_DPAX_W_PH: 12471 check_dsp_r2(ctx); 12472 gen_helper_dpax_w_ph(t0, v1_t, v2_t, cpu_env); 12473 break; 12474 case OPC_DPAQ_S_W_PH: 12475 check_dsp(ctx); 12476 gen_helper_dpaq_s_w_ph(t0, v1_t, v2_t, cpu_env); 12477 break; 12478 case OPC_DPAQX_S_W_PH: 12479 check_dsp_r2(ctx); 12480 gen_helper_dpaqx_s_w_ph(t0, v1_t, v2_t, cpu_env); 12481 break; 12482 case OPC_DPAQX_SA_W_PH: 12483 check_dsp_r2(ctx); 12484 gen_helper_dpaqx_sa_w_ph(t0, v1_t, v2_t, cpu_env); 12485 break; 12486 case OPC_DPS_W_PH: 12487 check_dsp_r2(ctx); 12488 gen_helper_dps_w_ph(t0, v1_t, v2_t, cpu_env); 12489 break; 12490 case OPC_DPSX_W_PH: 12491 check_dsp_r2(ctx); 12492 gen_helper_dpsx_w_ph(t0, v1_t, v2_t, cpu_env); 12493 break; 12494 case OPC_DPSQ_S_W_PH: 12495 check_dsp(ctx); 12496 gen_helper_dpsq_s_w_ph(t0, v1_t, v2_t, cpu_env); 12497 break; 12498 case OPC_DPSQX_S_W_PH: 12499 check_dsp_r2(ctx); 12500 gen_helper_dpsqx_s_w_ph(t0, v1_t, v2_t, cpu_env); 12501 break; 12502 case OPC_DPSQX_SA_W_PH: 12503 check_dsp_r2(ctx); 12504 gen_helper_dpsqx_sa_w_ph(t0, v1_t, v2_t, cpu_env); 12505 break; 12506 case OPC_MULSAQ_S_W_PH: 12507 check_dsp(ctx); 12508 gen_helper_mulsaq_s_w_ph(t0, v1_t, v2_t, cpu_env); 12509 break; 12510 case OPC_DPAQ_SA_L_W: 12511 check_dsp(ctx); 12512 gen_helper_dpaq_sa_l_w(t0, v1_t, v2_t, cpu_env); 12513 break; 12514 case OPC_DPSQ_SA_L_W: 12515 check_dsp(ctx); 12516 gen_helper_dpsq_sa_l_w(t0, v1_t, v2_t, cpu_env); 12517 break; 12518 case OPC_MAQ_S_W_PHL: 12519 check_dsp(ctx); 12520 gen_helper_maq_s_w_phl(t0, v1_t, v2_t, cpu_env); 12521 break; 12522 case OPC_MAQ_S_W_PHR: 12523 check_dsp(ctx); 12524 gen_helper_maq_s_w_phr(t0, v1_t, v2_t, cpu_env); 12525 break; 12526 case OPC_MAQ_SA_W_PHL: 12527 check_dsp(ctx); 12528 gen_helper_maq_sa_w_phl(t0, v1_t, v2_t, cpu_env); 12529 break; 12530 case OPC_MAQ_SA_W_PHR: 12531 check_dsp(ctx); 12532 gen_helper_maq_sa_w_phr(t0, v1_t, v2_t, cpu_env); 12533 break; 12534 case OPC_MULSA_W_PH: 12535 check_dsp_r2(ctx); 12536 gen_helper_mulsa_w_ph(t0, v1_t, v2_t, cpu_env); 12537 break; 12538 } 12539 break; 12540 #ifdef TARGET_MIPS64 12541 case OPC_DPAQ_W_QH_DSP: 12542 { 12543 int ac = ret & 0x03; 12544 tcg_gen_movi_i32(t0, ac); 12545 12546 switch (op2) { 12547 case OPC_DMADD: 12548 check_dsp(ctx); 12549 gen_helper_dmadd(v1_t, v2_t, t0, cpu_env); 12550 break; 12551 case OPC_DMADDU: 12552 check_dsp(ctx); 12553 gen_helper_dmaddu(v1_t, v2_t, t0, cpu_env); 12554 break; 12555 case OPC_DMSUB: 12556 check_dsp(ctx); 12557 gen_helper_dmsub(v1_t, v2_t, t0, cpu_env); 12558 break; 12559 case OPC_DMSUBU: 12560 check_dsp(ctx); 12561 gen_helper_dmsubu(v1_t, v2_t, t0, cpu_env); 12562 break; 12563 case OPC_DPA_W_QH: 12564 check_dsp_r2(ctx); 12565 gen_helper_dpa_w_qh(v1_t, v2_t, t0, cpu_env); 12566 break; 12567 case OPC_DPAQ_S_W_QH: 12568 check_dsp(ctx); 12569 gen_helper_dpaq_s_w_qh(v1_t, v2_t, t0, cpu_env); 12570 break; 12571 case OPC_DPAQ_SA_L_PW: 12572 check_dsp(ctx); 12573 gen_helper_dpaq_sa_l_pw(v1_t, v2_t, t0, cpu_env); 12574 break; 12575 case OPC_DPAU_H_OBL: 12576 check_dsp(ctx); 12577 gen_helper_dpau_h_obl(v1_t, v2_t, t0, cpu_env); 12578 break; 12579 case OPC_DPAU_H_OBR: 12580 check_dsp(ctx); 12581 gen_helper_dpau_h_obr(v1_t, v2_t, t0, cpu_env); 12582 break; 12583 case OPC_DPS_W_QH: 12584 check_dsp_r2(ctx); 12585 gen_helper_dps_w_qh(v1_t, v2_t, t0, cpu_env); 12586 break; 12587 case OPC_DPSQ_S_W_QH: 12588 check_dsp(ctx); 12589 gen_helper_dpsq_s_w_qh(v1_t, v2_t, t0, cpu_env); 12590 break; 12591 case OPC_DPSQ_SA_L_PW: 12592 check_dsp(ctx); 12593 gen_helper_dpsq_sa_l_pw(v1_t, v2_t, t0, cpu_env); 12594 break; 12595 case OPC_DPSU_H_OBL: 12596 check_dsp(ctx); 12597 gen_helper_dpsu_h_obl(v1_t, v2_t, t0, cpu_env); 12598 break; 12599 case OPC_DPSU_H_OBR: 12600 check_dsp(ctx); 12601 gen_helper_dpsu_h_obr(v1_t, v2_t, t0, cpu_env); 12602 break; 12603 case OPC_MAQ_S_L_PWL: 12604 check_dsp(ctx); 12605 gen_helper_maq_s_l_pwl(v1_t, v2_t, t0, cpu_env); 12606 break; 12607 case OPC_MAQ_S_L_PWR: 12608 check_dsp(ctx); 12609 gen_helper_maq_s_l_pwr(v1_t, v2_t, t0, cpu_env); 12610 break; 12611 case OPC_MAQ_S_W_QHLL: 12612 check_dsp(ctx); 12613 gen_helper_maq_s_w_qhll(v1_t, v2_t, t0, cpu_env); 12614 break; 12615 case OPC_MAQ_SA_W_QHLL: 12616 check_dsp(ctx); 12617 gen_helper_maq_sa_w_qhll(v1_t, v2_t, t0, cpu_env); 12618 break; 12619 case OPC_MAQ_S_W_QHLR: 12620 check_dsp(ctx); 12621 gen_helper_maq_s_w_qhlr(v1_t, v2_t, t0, cpu_env); 12622 break; 12623 case OPC_MAQ_SA_W_QHLR: 12624 check_dsp(ctx); 12625 gen_helper_maq_sa_w_qhlr(v1_t, v2_t, t0, cpu_env); 12626 break; 12627 case OPC_MAQ_S_W_QHRL: 12628 check_dsp(ctx); 12629 gen_helper_maq_s_w_qhrl(v1_t, v2_t, t0, cpu_env); 12630 break; 12631 case OPC_MAQ_SA_W_QHRL: 12632 check_dsp(ctx); 12633 gen_helper_maq_sa_w_qhrl(v1_t, v2_t, t0, cpu_env); 12634 break; 12635 case OPC_MAQ_S_W_QHRR: 12636 check_dsp(ctx); 12637 gen_helper_maq_s_w_qhrr(v1_t, v2_t, t0, cpu_env); 12638 break; 12639 case OPC_MAQ_SA_W_QHRR: 12640 check_dsp(ctx); 12641 gen_helper_maq_sa_w_qhrr(v1_t, v2_t, t0, cpu_env); 12642 break; 12643 case OPC_MULSAQ_S_L_PW: 12644 check_dsp(ctx); 12645 gen_helper_mulsaq_s_l_pw(v1_t, v2_t, t0, cpu_env); 12646 break; 12647 case OPC_MULSAQ_S_W_QH: 12648 check_dsp(ctx); 12649 gen_helper_mulsaq_s_w_qh(v1_t, v2_t, t0, cpu_env); 12650 break; 12651 } 12652 } 12653 break; 12654 #endif 12655 case OPC_ADDU_QB_DSP: 12656 switch (op2) { 12657 case OPC_MULEU_S_PH_QBL: 12658 check_dsp(ctx); 12659 gen_helper_muleu_s_ph_qbl(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12660 break; 12661 case OPC_MULEU_S_PH_QBR: 12662 check_dsp(ctx); 12663 gen_helper_muleu_s_ph_qbr(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12664 break; 12665 case OPC_MULQ_RS_PH: 12666 check_dsp(ctx); 12667 gen_helper_mulq_rs_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12668 break; 12669 case OPC_MULEQ_S_W_PHL: 12670 check_dsp(ctx); 12671 gen_helper_muleq_s_w_phl(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12672 break; 12673 case OPC_MULEQ_S_W_PHR: 12674 check_dsp(ctx); 12675 gen_helper_muleq_s_w_phr(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12676 break; 12677 case OPC_MULQ_S_PH: 12678 check_dsp_r2(ctx); 12679 gen_helper_mulq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12680 break; 12681 } 12682 break; 12683 #ifdef TARGET_MIPS64 12684 case OPC_ADDU_OB_DSP: 12685 switch (op2) { 12686 case OPC_MULEQ_S_PW_QHL: 12687 check_dsp(ctx); 12688 gen_helper_muleq_s_pw_qhl(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12689 break; 12690 case OPC_MULEQ_S_PW_QHR: 12691 check_dsp(ctx); 12692 gen_helper_muleq_s_pw_qhr(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12693 break; 12694 case OPC_MULEU_S_QH_OBL: 12695 check_dsp(ctx); 12696 gen_helper_muleu_s_qh_obl(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12697 break; 12698 case OPC_MULEU_S_QH_OBR: 12699 check_dsp(ctx); 12700 gen_helper_muleu_s_qh_obr(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12701 break; 12702 case OPC_MULQ_RS_QH: 12703 check_dsp(ctx); 12704 gen_helper_mulq_rs_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12705 break; 12706 } 12707 break; 12708 #endif 12709 } 12710 } 12711 12712 static void gen_mipsdsp_bitinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, 12713 int ret, int val) 12714 { 12715 int16_t imm; 12716 TCGv t0; 12717 TCGv val_t; 12718 12719 if (ret == 0) { 12720 /* Treat as NOP. */ 12721 return; 12722 } 12723 12724 t0 = tcg_temp_new(); 12725 val_t = tcg_temp_new(); 12726 gen_load_gpr(val_t, val); 12727 12728 switch (op1) { 12729 case OPC_ABSQ_S_PH_DSP: 12730 switch (op2) { 12731 case OPC_BITREV: 12732 check_dsp(ctx); 12733 gen_helper_bitrev(cpu_gpr[ret], val_t); 12734 break; 12735 case OPC_REPL_QB: 12736 check_dsp(ctx); 12737 { 12738 target_long result; 12739 imm = (ctx->opcode >> 16) & 0xFF; 12740 result = (uint32_t)imm << 24 | 12741 (uint32_t)imm << 16 | 12742 (uint32_t)imm << 8 | 12743 (uint32_t)imm; 12744 result = (int32_t)result; 12745 tcg_gen_movi_tl(cpu_gpr[ret], result); 12746 } 12747 break; 12748 case OPC_REPLV_QB: 12749 check_dsp(ctx); 12750 tcg_gen_ext8u_tl(cpu_gpr[ret], val_t); 12751 tcg_gen_shli_tl(t0, cpu_gpr[ret], 8); 12752 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12753 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); 12754 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12755 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); 12756 break; 12757 case OPC_REPL_PH: 12758 check_dsp(ctx); 12759 { 12760 imm = (ctx->opcode >> 16) & 0x03FF; 12761 imm = (int16_t)(imm << 6) >> 6; 12762 tcg_gen_movi_tl(cpu_gpr[ret], \ 12763 (target_long)((int32_t)imm << 16 | \ 12764 (uint16_t)imm)); 12765 } 12766 break; 12767 case OPC_REPLV_PH: 12768 check_dsp(ctx); 12769 tcg_gen_ext16u_tl(cpu_gpr[ret], val_t); 12770 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); 12771 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12772 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); 12773 break; 12774 } 12775 break; 12776 #ifdef TARGET_MIPS64 12777 case OPC_ABSQ_S_QH_DSP: 12778 switch (op2) { 12779 case OPC_REPL_OB: 12780 check_dsp(ctx); 12781 { 12782 target_long temp; 12783 12784 imm = (ctx->opcode >> 16) & 0xFF; 12785 temp = ((uint64_t)imm << 8) | (uint64_t)imm; 12786 temp = (temp << 16) | temp; 12787 temp = (temp << 32) | temp; 12788 tcg_gen_movi_tl(cpu_gpr[ret], temp); 12789 break; 12790 } 12791 case OPC_REPL_PW: 12792 check_dsp(ctx); 12793 { 12794 target_long temp; 12795 12796 imm = (ctx->opcode >> 16) & 0x03FF; 12797 imm = (int16_t)(imm << 6) >> 6; 12798 temp = ((target_long)imm << 32) \ 12799 | ((target_long)imm & 0xFFFFFFFF); 12800 tcg_gen_movi_tl(cpu_gpr[ret], temp); 12801 break; 12802 } 12803 case OPC_REPL_QH: 12804 check_dsp(ctx); 12805 { 12806 target_long temp; 12807 12808 imm = (ctx->opcode >> 16) & 0x03FF; 12809 imm = (int16_t)(imm << 6) >> 6; 12810 12811 temp = ((uint64_t)(uint16_t)imm << 48) | 12812 ((uint64_t)(uint16_t)imm << 32) | 12813 ((uint64_t)(uint16_t)imm << 16) | 12814 (uint64_t)(uint16_t)imm; 12815 tcg_gen_movi_tl(cpu_gpr[ret], temp); 12816 break; 12817 } 12818 case OPC_REPLV_OB: 12819 check_dsp(ctx); 12820 tcg_gen_ext8u_tl(cpu_gpr[ret], val_t); 12821 tcg_gen_shli_tl(t0, cpu_gpr[ret], 8); 12822 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12823 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); 12824 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12825 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32); 12826 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12827 break; 12828 case OPC_REPLV_PW: 12829 check_dsp(ctx); 12830 tcg_gen_ext32u_i64(cpu_gpr[ret], val_t); 12831 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32); 12832 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12833 break; 12834 case OPC_REPLV_QH: 12835 check_dsp(ctx); 12836 tcg_gen_ext16u_tl(cpu_gpr[ret], val_t); 12837 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); 12838 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12839 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32); 12840 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12841 break; 12842 } 12843 break; 12844 #endif 12845 } 12846 } 12847 12848 static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx, 12849 uint32_t op1, uint32_t op2, 12850 int ret, int v1, int v2, int check_ret) 12851 { 12852 TCGv t1; 12853 TCGv v1_t; 12854 TCGv v2_t; 12855 12856 if ((ret == 0) && (check_ret == 1)) { 12857 /* Treat as NOP. */ 12858 return; 12859 } 12860 12861 t1 = tcg_temp_new(); 12862 v1_t = tcg_temp_new(); 12863 v2_t = tcg_temp_new(); 12864 12865 gen_load_gpr(v1_t, v1); 12866 gen_load_gpr(v2_t, v2); 12867 12868 switch (op1) { 12869 case OPC_CMPU_EQ_QB_DSP: 12870 switch (op2) { 12871 case OPC_CMPU_EQ_QB: 12872 check_dsp(ctx); 12873 gen_helper_cmpu_eq_qb(v1_t, v2_t, cpu_env); 12874 break; 12875 case OPC_CMPU_LT_QB: 12876 check_dsp(ctx); 12877 gen_helper_cmpu_lt_qb(v1_t, v2_t, cpu_env); 12878 break; 12879 case OPC_CMPU_LE_QB: 12880 check_dsp(ctx); 12881 gen_helper_cmpu_le_qb(v1_t, v2_t, cpu_env); 12882 break; 12883 case OPC_CMPGU_EQ_QB: 12884 check_dsp(ctx); 12885 gen_helper_cmpgu_eq_qb(cpu_gpr[ret], v1_t, v2_t); 12886 break; 12887 case OPC_CMPGU_LT_QB: 12888 check_dsp(ctx); 12889 gen_helper_cmpgu_lt_qb(cpu_gpr[ret], v1_t, v2_t); 12890 break; 12891 case OPC_CMPGU_LE_QB: 12892 check_dsp(ctx); 12893 gen_helper_cmpgu_le_qb(cpu_gpr[ret], v1_t, v2_t); 12894 break; 12895 case OPC_CMPGDU_EQ_QB: 12896 check_dsp_r2(ctx); 12897 gen_helper_cmpgu_eq_qb(t1, v1_t, v2_t); 12898 tcg_gen_mov_tl(cpu_gpr[ret], t1); 12899 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); 12900 tcg_gen_shli_tl(t1, t1, 24); 12901 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); 12902 break; 12903 case OPC_CMPGDU_LT_QB: 12904 check_dsp_r2(ctx); 12905 gen_helper_cmpgu_lt_qb(t1, v1_t, v2_t); 12906 tcg_gen_mov_tl(cpu_gpr[ret], t1); 12907 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); 12908 tcg_gen_shli_tl(t1, t1, 24); 12909 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); 12910 break; 12911 case OPC_CMPGDU_LE_QB: 12912 check_dsp_r2(ctx); 12913 gen_helper_cmpgu_le_qb(t1, v1_t, v2_t); 12914 tcg_gen_mov_tl(cpu_gpr[ret], t1); 12915 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); 12916 tcg_gen_shli_tl(t1, t1, 24); 12917 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); 12918 break; 12919 case OPC_CMP_EQ_PH: 12920 check_dsp(ctx); 12921 gen_helper_cmp_eq_ph(v1_t, v2_t, cpu_env); 12922 break; 12923 case OPC_CMP_LT_PH: 12924 check_dsp(ctx); 12925 gen_helper_cmp_lt_ph(v1_t, v2_t, cpu_env); 12926 break; 12927 case OPC_CMP_LE_PH: 12928 check_dsp(ctx); 12929 gen_helper_cmp_le_ph(v1_t, v2_t, cpu_env); 12930 break; 12931 case OPC_PICK_QB: 12932 check_dsp(ctx); 12933 gen_helper_pick_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12934 break; 12935 case OPC_PICK_PH: 12936 check_dsp(ctx); 12937 gen_helper_pick_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12938 break; 12939 case OPC_PACKRL_PH: 12940 check_dsp(ctx); 12941 gen_helper_packrl_ph(cpu_gpr[ret], v1_t, v2_t); 12942 break; 12943 } 12944 break; 12945 #ifdef TARGET_MIPS64 12946 case OPC_CMPU_EQ_OB_DSP: 12947 switch (op2) { 12948 case OPC_CMP_EQ_PW: 12949 check_dsp(ctx); 12950 gen_helper_cmp_eq_pw(v1_t, v2_t, cpu_env); 12951 break; 12952 case OPC_CMP_LT_PW: 12953 check_dsp(ctx); 12954 gen_helper_cmp_lt_pw(v1_t, v2_t, cpu_env); 12955 break; 12956 case OPC_CMP_LE_PW: 12957 check_dsp(ctx); 12958 gen_helper_cmp_le_pw(v1_t, v2_t, cpu_env); 12959 break; 12960 case OPC_CMP_EQ_QH: 12961 check_dsp(ctx); 12962 gen_helper_cmp_eq_qh(v1_t, v2_t, cpu_env); 12963 break; 12964 case OPC_CMP_LT_QH: 12965 check_dsp(ctx); 12966 gen_helper_cmp_lt_qh(v1_t, v2_t, cpu_env); 12967 break; 12968 case OPC_CMP_LE_QH: 12969 check_dsp(ctx); 12970 gen_helper_cmp_le_qh(v1_t, v2_t, cpu_env); 12971 break; 12972 case OPC_CMPGDU_EQ_OB: 12973 check_dsp_r2(ctx); 12974 gen_helper_cmpgdu_eq_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12975 break; 12976 case OPC_CMPGDU_LT_OB: 12977 check_dsp_r2(ctx); 12978 gen_helper_cmpgdu_lt_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12979 break; 12980 case OPC_CMPGDU_LE_OB: 12981 check_dsp_r2(ctx); 12982 gen_helper_cmpgdu_le_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); 12983 break; 12984 case OPC_CMPGU_EQ_OB: 12985 check_dsp(ctx); 12986 gen_helper_cmpgu_eq_ob(cpu_gpr[ret], v1_t, v2_t); 12987 break; 12988 case OPC_CMPGU_LT_OB: 12989 check_dsp(ctx); 12990 gen_helper_cmpgu_lt_ob(cpu_gpr[ret], v1_t, v2_t); 12991 break; 12992 case OPC_CMPGU_LE_OB: 12993 check_dsp(ctx); 12994 gen_helper_cmpgu_le_ob(cpu_gpr[ret], v1_t, v2_t); 12995 break; 12996 case OPC_CMPU_EQ_OB: 12997 check_dsp(ctx); 12998 gen_helper_cmpu_eq_ob(v1_t, v2_t, cpu_env); 12999 break; 13000 case OPC_CMPU_LT_OB: 13001 check_dsp(ctx); 13002 gen_helper_cmpu_lt_ob(v1_t, v2_t, cpu_env); 13003 break; 13004 case OPC_CMPU_LE_OB: 13005 check_dsp(ctx); 13006 gen_helper_cmpu_le_ob(v1_t, v2_t, cpu_env); 13007 break; 13008 case OPC_PACKRL_PW: 13009 check_dsp(ctx); 13010 gen_helper_packrl_pw(cpu_gpr[ret], v1_t, v2_t); 13011 break; 13012 case OPC_PICK_OB: 13013 check_dsp(ctx); 13014 gen_helper_pick_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); 13015 break; 13016 case OPC_PICK_PW: 13017 check_dsp(ctx); 13018 gen_helper_pick_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); 13019 break; 13020 case OPC_PICK_QH: 13021 check_dsp(ctx); 13022 gen_helper_pick_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); 13023 break; 13024 } 13025 break; 13026 #endif 13027 } 13028 } 13029 13030 static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx, 13031 uint32_t op1, int rt, int rs, int sa) 13032 { 13033 TCGv t0; 13034 13035 check_dsp_r2(ctx); 13036 13037 if (rt == 0) { 13038 /* Treat as NOP. */ 13039 return; 13040 } 13041 13042 t0 = tcg_temp_new(); 13043 gen_load_gpr(t0, rs); 13044 13045 switch (op1) { 13046 case OPC_APPEND_DSP: 13047 switch (MASK_APPEND(ctx->opcode)) { 13048 case OPC_APPEND: 13049 if (sa != 0) { 13050 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 32 - sa); 13051 } 13052 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 13053 break; 13054 case OPC_PREPEND: 13055 if (sa != 0) { 13056 tcg_gen_ext32u_tl(cpu_gpr[rt], cpu_gpr[rt]); 13057 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], sa); 13058 tcg_gen_shli_tl(t0, t0, 32 - sa); 13059 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); 13060 } 13061 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 13062 break; 13063 case OPC_BALIGN: 13064 sa &= 3; 13065 if (sa != 0 && sa != 2) { 13066 tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa); 13067 tcg_gen_ext32u_tl(t0, t0); 13068 tcg_gen_shri_tl(t0, t0, 8 * (4 - sa)); 13069 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); 13070 } 13071 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 13072 break; 13073 default: /* Invalid */ 13074 MIPS_INVAL("MASK APPEND"); 13075 gen_reserved_instruction(ctx); 13076 break; 13077 } 13078 break; 13079 #ifdef TARGET_MIPS64 13080 case OPC_DAPPEND_DSP: 13081 switch (MASK_DAPPEND(ctx->opcode)) { 13082 case OPC_DAPPEND: 13083 if (sa != 0) { 13084 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 64 - sa); 13085 } 13086 break; 13087 case OPC_PREPENDD: 13088 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], 0x20 | sa); 13089 tcg_gen_shli_tl(t0, t0, 64 - (0x20 | sa)); 13090 tcg_gen_or_tl(cpu_gpr[rt], t0, t0); 13091 break; 13092 case OPC_PREPENDW: 13093 if (sa != 0) { 13094 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], sa); 13095 tcg_gen_shli_tl(t0, t0, 64 - sa); 13096 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); 13097 } 13098 break; 13099 case OPC_DBALIGN: 13100 sa &= 7; 13101 if (sa != 0 && sa != 2 && sa != 4) { 13102 tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa); 13103 tcg_gen_shri_tl(t0, t0, 8 * (8 - sa)); 13104 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); 13105 } 13106 break; 13107 default: /* Invalid */ 13108 MIPS_INVAL("MASK DAPPEND"); 13109 gen_reserved_instruction(ctx); 13110 break; 13111 } 13112 break; 13113 #endif 13114 } 13115 } 13116 13117 static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, 13118 int ret, int v1, int v2, int check_ret) 13119 13120 { 13121 TCGv t0; 13122 TCGv t1; 13123 TCGv v1_t; 13124 int16_t imm; 13125 13126 if ((ret == 0) && (check_ret == 1)) { 13127 /* Treat as NOP. */ 13128 return; 13129 } 13130 13131 t0 = tcg_temp_new(); 13132 t1 = tcg_temp_new(); 13133 v1_t = tcg_temp_new(); 13134 13135 gen_load_gpr(v1_t, v1); 13136 13137 switch (op1) { 13138 case OPC_EXTR_W_DSP: 13139 check_dsp(ctx); 13140 switch (op2) { 13141 case OPC_EXTR_W: 13142 tcg_gen_movi_tl(t0, v2); 13143 tcg_gen_movi_tl(t1, v1); 13144 gen_helper_extr_w(cpu_gpr[ret], t0, t1, cpu_env); 13145 break; 13146 case OPC_EXTR_R_W: 13147 tcg_gen_movi_tl(t0, v2); 13148 tcg_gen_movi_tl(t1, v1); 13149 gen_helper_extr_r_w(cpu_gpr[ret], t0, t1, cpu_env); 13150 break; 13151 case OPC_EXTR_RS_W: 13152 tcg_gen_movi_tl(t0, v2); 13153 tcg_gen_movi_tl(t1, v1); 13154 gen_helper_extr_rs_w(cpu_gpr[ret], t0, t1, cpu_env); 13155 break; 13156 case OPC_EXTR_S_H: 13157 tcg_gen_movi_tl(t0, v2); 13158 tcg_gen_movi_tl(t1, v1); 13159 gen_helper_extr_s_h(cpu_gpr[ret], t0, t1, cpu_env); 13160 break; 13161 case OPC_EXTRV_S_H: 13162 tcg_gen_movi_tl(t0, v2); 13163 gen_helper_extr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env); 13164 break; 13165 case OPC_EXTRV_W: 13166 tcg_gen_movi_tl(t0, v2); 13167 gen_helper_extr_w(cpu_gpr[ret], t0, v1_t, cpu_env); 13168 break; 13169 case OPC_EXTRV_R_W: 13170 tcg_gen_movi_tl(t0, v2); 13171 gen_helper_extr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env); 13172 break; 13173 case OPC_EXTRV_RS_W: 13174 tcg_gen_movi_tl(t0, v2); 13175 gen_helper_extr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env); 13176 break; 13177 case OPC_EXTP: 13178 tcg_gen_movi_tl(t0, v2); 13179 tcg_gen_movi_tl(t1, v1); 13180 gen_helper_extp(cpu_gpr[ret], t0, t1, cpu_env); 13181 break; 13182 case OPC_EXTPV: 13183 tcg_gen_movi_tl(t0, v2); 13184 gen_helper_extp(cpu_gpr[ret], t0, v1_t, cpu_env); 13185 break; 13186 case OPC_EXTPDP: 13187 tcg_gen_movi_tl(t0, v2); 13188 tcg_gen_movi_tl(t1, v1); 13189 gen_helper_extpdp(cpu_gpr[ret], t0, t1, cpu_env); 13190 break; 13191 case OPC_EXTPDPV: 13192 tcg_gen_movi_tl(t0, v2); 13193 gen_helper_extpdp(cpu_gpr[ret], t0, v1_t, cpu_env); 13194 break; 13195 case OPC_SHILO: 13196 imm = (ctx->opcode >> 20) & 0x3F; 13197 tcg_gen_movi_tl(t0, ret); 13198 tcg_gen_movi_tl(t1, imm); 13199 gen_helper_shilo(t0, t1, cpu_env); 13200 break; 13201 case OPC_SHILOV: 13202 tcg_gen_movi_tl(t0, ret); 13203 gen_helper_shilo(t0, v1_t, cpu_env); 13204 break; 13205 case OPC_MTHLIP: 13206 tcg_gen_movi_tl(t0, ret); 13207 gen_helper_mthlip(t0, v1_t, cpu_env); 13208 break; 13209 case OPC_WRDSP: 13210 imm = (ctx->opcode >> 11) & 0x3FF; 13211 tcg_gen_movi_tl(t0, imm); 13212 gen_helper_wrdsp(v1_t, t0, cpu_env); 13213 break; 13214 case OPC_RDDSP: 13215 imm = (ctx->opcode >> 16) & 0x03FF; 13216 tcg_gen_movi_tl(t0, imm); 13217 gen_helper_rddsp(cpu_gpr[ret], t0, cpu_env); 13218 break; 13219 } 13220 break; 13221 #ifdef TARGET_MIPS64 13222 case OPC_DEXTR_W_DSP: 13223 check_dsp(ctx); 13224 switch (op2) { 13225 case OPC_DMTHLIP: 13226 tcg_gen_movi_tl(t0, ret); 13227 gen_helper_dmthlip(v1_t, t0, cpu_env); 13228 break; 13229 case OPC_DSHILO: 13230 { 13231 int shift = (ctx->opcode >> 19) & 0x7F; 13232 int ac = (ctx->opcode >> 11) & 0x03; 13233 tcg_gen_movi_tl(t0, shift); 13234 tcg_gen_movi_tl(t1, ac); 13235 gen_helper_dshilo(t0, t1, cpu_env); 13236 break; 13237 } 13238 case OPC_DSHILOV: 13239 { 13240 int ac = (ctx->opcode >> 11) & 0x03; 13241 tcg_gen_movi_tl(t0, ac); 13242 gen_helper_dshilo(v1_t, t0, cpu_env); 13243 break; 13244 } 13245 case OPC_DEXTP: 13246 tcg_gen_movi_tl(t0, v2); 13247 tcg_gen_movi_tl(t1, v1); 13248 13249 gen_helper_dextp(cpu_gpr[ret], t0, t1, cpu_env); 13250 break; 13251 case OPC_DEXTPV: 13252 tcg_gen_movi_tl(t0, v2); 13253 gen_helper_dextp(cpu_gpr[ret], t0, v1_t, cpu_env); 13254 break; 13255 case OPC_DEXTPDP: 13256 tcg_gen_movi_tl(t0, v2); 13257 tcg_gen_movi_tl(t1, v1); 13258 gen_helper_dextpdp(cpu_gpr[ret], t0, t1, cpu_env); 13259 break; 13260 case OPC_DEXTPDPV: 13261 tcg_gen_movi_tl(t0, v2); 13262 gen_helper_dextpdp(cpu_gpr[ret], t0, v1_t, cpu_env); 13263 break; 13264 case OPC_DEXTR_L: 13265 tcg_gen_movi_tl(t0, v2); 13266 tcg_gen_movi_tl(t1, v1); 13267 gen_helper_dextr_l(cpu_gpr[ret], t0, t1, cpu_env); 13268 break; 13269 case OPC_DEXTR_R_L: 13270 tcg_gen_movi_tl(t0, v2); 13271 tcg_gen_movi_tl(t1, v1); 13272 gen_helper_dextr_r_l(cpu_gpr[ret], t0, t1, cpu_env); 13273 break; 13274 case OPC_DEXTR_RS_L: 13275 tcg_gen_movi_tl(t0, v2); 13276 tcg_gen_movi_tl(t1, v1); 13277 gen_helper_dextr_rs_l(cpu_gpr[ret], t0, t1, cpu_env); 13278 break; 13279 case OPC_DEXTR_W: 13280 tcg_gen_movi_tl(t0, v2); 13281 tcg_gen_movi_tl(t1, v1); 13282 gen_helper_dextr_w(cpu_gpr[ret], t0, t1, cpu_env); 13283 break; 13284 case OPC_DEXTR_R_W: 13285 tcg_gen_movi_tl(t0, v2); 13286 tcg_gen_movi_tl(t1, v1); 13287 gen_helper_dextr_r_w(cpu_gpr[ret], t0, t1, cpu_env); 13288 break; 13289 case OPC_DEXTR_RS_W: 13290 tcg_gen_movi_tl(t0, v2); 13291 tcg_gen_movi_tl(t1, v1); 13292 gen_helper_dextr_rs_w(cpu_gpr[ret], t0, t1, cpu_env); 13293 break; 13294 case OPC_DEXTR_S_H: 13295 tcg_gen_movi_tl(t0, v2); 13296 tcg_gen_movi_tl(t1, v1); 13297 gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env); 13298 break; 13299 case OPC_DEXTRV_S_H: 13300 tcg_gen_movi_tl(t0, v2); 13301 gen_helper_dextr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env); 13302 break; 13303 case OPC_DEXTRV_L: 13304 tcg_gen_movi_tl(t0, v2); 13305 gen_helper_dextr_l(cpu_gpr[ret], t0, v1_t, cpu_env); 13306 break; 13307 case OPC_DEXTRV_R_L: 13308 tcg_gen_movi_tl(t0, v2); 13309 gen_helper_dextr_r_l(cpu_gpr[ret], t0, v1_t, cpu_env); 13310 break; 13311 case OPC_DEXTRV_RS_L: 13312 tcg_gen_movi_tl(t0, v2); 13313 gen_helper_dextr_rs_l(cpu_gpr[ret], t0, v1_t, cpu_env); 13314 break; 13315 case OPC_DEXTRV_W: 13316 tcg_gen_movi_tl(t0, v2); 13317 gen_helper_dextr_w(cpu_gpr[ret], t0, v1_t, cpu_env); 13318 break; 13319 case OPC_DEXTRV_R_W: 13320 tcg_gen_movi_tl(t0, v2); 13321 gen_helper_dextr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env); 13322 break; 13323 case OPC_DEXTRV_RS_W: 13324 tcg_gen_movi_tl(t0, v2); 13325 gen_helper_dextr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env); 13326 break; 13327 } 13328 break; 13329 #endif 13330 } 13331 } 13332 13333 /* End MIPSDSP functions. */ 13334 13335 static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) 13336 { 13337 int rs, rt, rd, sa; 13338 uint32_t op1, op2; 13339 13340 rs = (ctx->opcode >> 21) & 0x1f; 13341 rt = (ctx->opcode >> 16) & 0x1f; 13342 rd = (ctx->opcode >> 11) & 0x1f; 13343 sa = (ctx->opcode >> 6) & 0x1f; 13344 13345 op1 = MASK_SPECIAL(ctx->opcode); 13346 switch (op1) { 13347 case OPC_MULT: 13348 case OPC_MULTU: 13349 case OPC_DIV: 13350 case OPC_DIVU: 13351 op2 = MASK_R6_MULDIV(ctx->opcode); 13352 switch (op2) { 13353 case R6_OPC_MUL: 13354 case R6_OPC_MUH: 13355 case R6_OPC_MULU: 13356 case R6_OPC_MUHU: 13357 case R6_OPC_DIV: 13358 case R6_OPC_MOD: 13359 case R6_OPC_DIVU: 13360 case R6_OPC_MODU: 13361 gen_r6_muldiv(ctx, op2, rd, rs, rt); 13362 break; 13363 default: 13364 MIPS_INVAL("special_r6 muldiv"); 13365 gen_reserved_instruction(ctx); 13366 break; 13367 } 13368 break; 13369 case OPC_SELEQZ: 13370 case OPC_SELNEZ: 13371 gen_cond_move(ctx, op1, rd, rs, rt); 13372 break; 13373 case R6_OPC_CLO: 13374 case R6_OPC_CLZ: 13375 if (rt == 0 && sa == 1) { 13376 /* 13377 * Major opcode and function field is shared with preR6 MFHI/MTHI. 13378 * We need additionally to check other fields. 13379 */ 13380 gen_cl(ctx, op1, rd, rs); 13381 } else { 13382 gen_reserved_instruction(ctx); 13383 } 13384 break; 13385 case R6_OPC_SDBBP: 13386 if (is_uhi(ctx, extract32(ctx->opcode, 6, 20))) { 13387 ctx->base.is_jmp = DISAS_SEMIHOST; 13388 } else { 13389 if (ctx->hflags & MIPS_HFLAG_SBRI) { 13390 gen_reserved_instruction(ctx); 13391 } else { 13392 generate_exception_end(ctx, EXCP_DBp); 13393 } 13394 } 13395 break; 13396 #if defined(TARGET_MIPS64) 13397 case R6_OPC_DCLO: 13398 case R6_OPC_DCLZ: 13399 if (rt == 0 && sa == 1) { 13400 /* 13401 * Major opcode and function field is shared with preR6 MFHI/MTHI. 13402 * We need additionally to check other fields. 13403 */ 13404 check_mips_64(ctx); 13405 gen_cl(ctx, op1, rd, rs); 13406 } else { 13407 gen_reserved_instruction(ctx); 13408 } 13409 break; 13410 case OPC_DMULT: 13411 case OPC_DMULTU: 13412 case OPC_DDIV: 13413 case OPC_DDIVU: 13414 13415 op2 = MASK_R6_MULDIV(ctx->opcode); 13416 switch (op2) { 13417 case R6_OPC_DMUL: 13418 case R6_OPC_DMUH: 13419 case R6_OPC_DMULU: 13420 case R6_OPC_DMUHU: 13421 case R6_OPC_DDIV: 13422 case R6_OPC_DMOD: 13423 case R6_OPC_DDIVU: 13424 case R6_OPC_DMODU: 13425 check_mips_64(ctx); 13426 gen_r6_muldiv(ctx, op2, rd, rs, rt); 13427 break; 13428 default: 13429 MIPS_INVAL("special_r6 muldiv"); 13430 gen_reserved_instruction(ctx); 13431 break; 13432 } 13433 break; 13434 #endif 13435 default: /* Invalid */ 13436 MIPS_INVAL("special_r6"); 13437 gen_reserved_instruction(ctx); 13438 break; 13439 } 13440 } 13441 13442 static void decode_opc_special_tx79(CPUMIPSState *env, DisasContext *ctx) 13443 { 13444 int rs = extract32(ctx->opcode, 21, 5); 13445 int rt = extract32(ctx->opcode, 16, 5); 13446 int rd = extract32(ctx->opcode, 11, 5); 13447 uint32_t op1 = MASK_SPECIAL(ctx->opcode); 13448 13449 switch (op1) { 13450 case OPC_MOVN: /* Conditional move */ 13451 case OPC_MOVZ: 13452 gen_cond_move(ctx, op1, rd, rs, rt); 13453 break; 13454 case OPC_MFHI: /* Move from HI/LO */ 13455 case OPC_MFLO: 13456 gen_HILO(ctx, op1, 0, rd); 13457 break; 13458 case OPC_MTHI: 13459 case OPC_MTLO: /* Move to HI/LO */ 13460 gen_HILO(ctx, op1, 0, rs); 13461 break; 13462 case OPC_MULT: 13463 case OPC_MULTU: 13464 gen_mul_txx9(ctx, op1, rd, rs, rt); 13465 break; 13466 case OPC_DIV: 13467 case OPC_DIVU: 13468 gen_muldiv(ctx, op1, 0, rs, rt); 13469 break; 13470 #if defined(TARGET_MIPS64) 13471 case OPC_DMULT: 13472 case OPC_DMULTU: 13473 case OPC_DDIV: 13474 case OPC_DDIVU: 13475 check_insn_opc_user_only(ctx, INSN_R5900); 13476 gen_muldiv(ctx, op1, 0, rs, rt); 13477 break; 13478 #endif 13479 case OPC_JR: 13480 gen_compute_branch(ctx, op1, 4, rs, 0, 0, 4); 13481 break; 13482 default: /* Invalid */ 13483 MIPS_INVAL("special_tx79"); 13484 gen_reserved_instruction(ctx); 13485 break; 13486 } 13487 } 13488 13489 static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) 13490 { 13491 int rs, rt, rd; 13492 uint32_t op1; 13493 13494 rs = (ctx->opcode >> 21) & 0x1f; 13495 rt = (ctx->opcode >> 16) & 0x1f; 13496 rd = (ctx->opcode >> 11) & 0x1f; 13497 13498 op1 = MASK_SPECIAL(ctx->opcode); 13499 switch (op1) { 13500 case OPC_MOVN: /* Conditional move */ 13501 case OPC_MOVZ: 13502 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | 13503 INSN_LOONGSON2E | INSN_LOONGSON2F); 13504 gen_cond_move(ctx, op1, rd, rs, rt); 13505 break; 13506 case OPC_MFHI: /* Move from HI/LO */ 13507 case OPC_MFLO: 13508 gen_HILO(ctx, op1, rs & 3, rd); 13509 break; 13510 case OPC_MTHI: 13511 case OPC_MTLO: /* Move to HI/LO */ 13512 gen_HILO(ctx, op1, rd & 3, rs); 13513 break; 13514 case OPC_MOVCI: 13515 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); 13516 if (env->CP0_Config1 & (1 << CP0C1_FP)) { 13517 check_cp1_enabled(ctx); 13518 gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7, 13519 (ctx->opcode >> 16) & 1); 13520 } else { 13521 generate_exception_err(ctx, EXCP_CpU, 1); 13522 } 13523 break; 13524 case OPC_MULT: 13525 case OPC_MULTU: 13526 gen_muldiv(ctx, op1, rd & 3, rs, rt); 13527 break; 13528 case OPC_DIV: 13529 case OPC_DIVU: 13530 gen_muldiv(ctx, op1, 0, rs, rt); 13531 break; 13532 #if defined(TARGET_MIPS64) 13533 case OPC_DMULT: 13534 case OPC_DMULTU: 13535 case OPC_DDIV: 13536 case OPC_DDIVU: 13537 check_insn(ctx, ISA_MIPS3); 13538 check_mips_64(ctx); 13539 gen_muldiv(ctx, op1, 0, rs, rt); 13540 break; 13541 #endif 13542 case OPC_JR: 13543 gen_compute_branch(ctx, op1, 4, rs, 0, 0, 4); 13544 break; 13545 case OPC_SPIM: 13546 #ifdef MIPS_STRICT_STANDARD 13547 MIPS_INVAL("SPIM"); 13548 gen_reserved_instruction(ctx); 13549 #else 13550 /* Implemented as RI exception for now. */ 13551 MIPS_INVAL("spim (unofficial)"); 13552 gen_reserved_instruction(ctx); 13553 #endif 13554 break; 13555 default: /* Invalid */ 13556 MIPS_INVAL("special_legacy"); 13557 gen_reserved_instruction(ctx); 13558 break; 13559 } 13560 } 13561 13562 static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) 13563 { 13564 int rs, rt, rd, sa; 13565 uint32_t op1; 13566 13567 rs = (ctx->opcode >> 21) & 0x1f; 13568 rt = (ctx->opcode >> 16) & 0x1f; 13569 rd = (ctx->opcode >> 11) & 0x1f; 13570 sa = (ctx->opcode >> 6) & 0x1f; 13571 13572 op1 = MASK_SPECIAL(ctx->opcode); 13573 switch (op1) { 13574 case OPC_SLL: /* Shift with immediate */ 13575 if (sa == 5 && rd == 0 && 13576 rs == 0 && rt == 0) { /* PAUSE */ 13577 if ((ctx->insn_flags & ISA_MIPS_R6) && 13578 (ctx->hflags & MIPS_HFLAG_BMASK)) { 13579 gen_reserved_instruction(ctx); 13580 break; 13581 } 13582 } 13583 /* Fallthrough */ 13584 case OPC_SRA: 13585 gen_shift_imm(ctx, op1, rd, rt, sa); 13586 break; 13587 case OPC_SRL: 13588 switch ((ctx->opcode >> 21) & 0x1f) { 13589 case 1: 13590 /* rotr is decoded as srl on non-R2 CPUs */ 13591 if (ctx->insn_flags & ISA_MIPS_R2) { 13592 op1 = OPC_ROTR; 13593 } 13594 /* Fallthrough */ 13595 case 0: 13596 gen_shift_imm(ctx, op1, rd, rt, sa); 13597 break; 13598 default: 13599 gen_reserved_instruction(ctx); 13600 break; 13601 } 13602 break; 13603 case OPC_ADD: 13604 case OPC_ADDU: 13605 case OPC_SUB: 13606 case OPC_SUBU: 13607 gen_arith(ctx, op1, rd, rs, rt); 13608 break; 13609 case OPC_SLLV: /* Shifts */ 13610 case OPC_SRAV: 13611 gen_shift(ctx, op1, rd, rs, rt); 13612 break; 13613 case OPC_SRLV: 13614 switch ((ctx->opcode >> 6) & 0x1f) { 13615 case 1: 13616 /* rotrv is decoded as srlv on non-R2 CPUs */ 13617 if (ctx->insn_flags & ISA_MIPS_R2) { 13618 op1 = OPC_ROTRV; 13619 } 13620 /* Fallthrough */ 13621 case 0: 13622 gen_shift(ctx, op1, rd, rs, rt); 13623 break; 13624 default: 13625 gen_reserved_instruction(ctx); 13626 break; 13627 } 13628 break; 13629 case OPC_SLT: /* Set on less than */ 13630 case OPC_SLTU: 13631 gen_slt(ctx, op1, rd, rs, rt); 13632 break; 13633 case OPC_AND: /* Logic*/ 13634 case OPC_OR: 13635 case OPC_NOR: 13636 case OPC_XOR: 13637 gen_logic(ctx, op1, rd, rs, rt); 13638 break; 13639 case OPC_JALR: 13640 gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4); 13641 break; 13642 case OPC_TGE: /* Traps */ 13643 case OPC_TGEU: 13644 case OPC_TLT: 13645 case OPC_TLTU: 13646 case OPC_TEQ: 13647 case OPC_TNE: 13648 check_insn(ctx, ISA_MIPS2); 13649 gen_trap(ctx, op1, rs, rt, -1, extract32(ctx->opcode, 6, 10)); 13650 break; 13651 case OPC_PMON: 13652 /* Pmon entry point, also R4010 selsl */ 13653 #ifdef MIPS_STRICT_STANDARD 13654 MIPS_INVAL("PMON / selsl"); 13655 gen_reserved_instruction(ctx); 13656 #else 13657 gen_helper_pmon(cpu_env, tcg_constant_i32(sa)); 13658 #endif 13659 break; 13660 case OPC_SYSCALL: 13661 generate_exception_end(ctx, EXCP_SYSCALL); 13662 break; 13663 case OPC_BREAK: 13664 generate_exception_break(ctx, extract32(ctx->opcode, 6, 20)); 13665 break; 13666 case OPC_SYNC: 13667 check_insn(ctx, ISA_MIPS2); 13668 gen_sync(extract32(ctx->opcode, 6, 5)); 13669 break; 13670 13671 #if defined(TARGET_MIPS64) 13672 /* MIPS64 specific opcodes */ 13673 case OPC_DSLL: 13674 case OPC_DSRA: 13675 case OPC_DSLL32: 13676 case OPC_DSRA32: 13677 check_insn(ctx, ISA_MIPS3); 13678 check_mips_64(ctx); 13679 gen_shift_imm(ctx, op1, rd, rt, sa); 13680 break; 13681 case OPC_DSRL: 13682 switch ((ctx->opcode >> 21) & 0x1f) { 13683 case 1: 13684 /* drotr is decoded as dsrl on non-R2 CPUs */ 13685 if (ctx->insn_flags & ISA_MIPS_R2) { 13686 op1 = OPC_DROTR; 13687 } 13688 /* Fallthrough */ 13689 case 0: 13690 check_insn(ctx, ISA_MIPS3); 13691 check_mips_64(ctx); 13692 gen_shift_imm(ctx, op1, rd, rt, sa); 13693 break; 13694 default: 13695 gen_reserved_instruction(ctx); 13696 break; 13697 } 13698 break; 13699 case OPC_DSRL32: 13700 switch ((ctx->opcode >> 21) & 0x1f) { 13701 case 1: 13702 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */ 13703 if (ctx->insn_flags & ISA_MIPS_R2) { 13704 op1 = OPC_DROTR32; 13705 } 13706 /* Fallthrough */ 13707 case 0: 13708 check_insn(ctx, ISA_MIPS3); 13709 check_mips_64(ctx); 13710 gen_shift_imm(ctx, op1, rd, rt, sa); 13711 break; 13712 default: 13713 gen_reserved_instruction(ctx); 13714 break; 13715 } 13716 break; 13717 case OPC_DADD: 13718 case OPC_DADDU: 13719 case OPC_DSUB: 13720 case OPC_DSUBU: 13721 check_insn(ctx, ISA_MIPS3); 13722 check_mips_64(ctx); 13723 gen_arith(ctx, op1, rd, rs, rt); 13724 break; 13725 case OPC_DSLLV: 13726 case OPC_DSRAV: 13727 check_insn(ctx, ISA_MIPS3); 13728 check_mips_64(ctx); 13729 gen_shift(ctx, op1, rd, rs, rt); 13730 break; 13731 case OPC_DSRLV: 13732 switch ((ctx->opcode >> 6) & 0x1f) { 13733 case 1: 13734 /* drotrv is decoded as dsrlv on non-R2 CPUs */ 13735 if (ctx->insn_flags & ISA_MIPS_R2) { 13736 op1 = OPC_DROTRV; 13737 } 13738 /* Fallthrough */ 13739 case 0: 13740 check_insn(ctx, ISA_MIPS3); 13741 check_mips_64(ctx); 13742 gen_shift(ctx, op1, rd, rs, rt); 13743 break; 13744 default: 13745 gen_reserved_instruction(ctx); 13746 break; 13747 } 13748 break; 13749 #endif 13750 default: 13751 if (ctx->insn_flags & ISA_MIPS_R6) { 13752 decode_opc_special_r6(env, ctx); 13753 } else if (ctx->insn_flags & INSN_R5900) { 13754 decode_opc_special_tx79(env, ctx); 13755 } else { 13756 decode_opc_special_legacy(env, ctx); 13757 } 13758 } 13759 } 13760 13761 13762 static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) 13763 { 13764 int rs, rt, rd; 13765 uint32_t op1; 13766 13767 rs = (ctx->opcode >> 21) & 0x1f; 13768 rt = (ctx->opcode >> 16) & 0x1f; 13769 rd = (ctx->opcode >> 11) & 0x1f; 13770 13771 op1 = MASK_SPECIAL2(ctx->opcode); 13772 switch (op1) { 13773 case OPC_MADD: /* Multiply and add/sub */ 13774 case OPC_MADDU: 13775 case OPC_MSUB: 13776 case OPC_MSUBU: 13777 check_insn(ctx, ISA_MIPS_R1); 13778 gen_muldiv(ctx, op1, rd & 3, rs, rt); 13779 break; 13780 case OPC_MUL: 13781 gen_arith(ctx, op1, rd, rs, rt); 13782 break; 13783 case OPC_DIV_G_2F: 13784 case OPC_DIVU_G_2F: 13785 case OPC_MULT_G_2F: 13786 case OPC_MULTU_G_2F: 13787 case OPC_MOD_G_2F: 13788 case OPC_MODU_G_2F: 13789 check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); 13790 gen_loongson_integer(ctx, op1, rd, rs, rt); 13791 break; 13792 case OPC_CLO: 13793 case OPC_CLZ: 13794 check_insn(ctx, ISA_MIPS_R1); 13795 gen_cl(ctx, op1, rd, rs); 13796 break; 13797 case OPC_SDBBP: 13798 if (is_uhi(ctx, extract32(ctx->opcode, 6, 20))) { 13799 ctx->base.is_jmp = DISAS_SEMIHOST; 13800 } else { 13801 /* 13802 * XXX: not clear which exception should be raised 13803 * when in debug mode... 13804 */ 13805 check_insn(ctx, ISA_MIPS_R1); 13806 generate_exception_end(ctx, EXCP_DBp); 13807 } 13808 break; 13809 #if defined(TARGET_MIPS64) 13810 case OPC_DCLO: 13811 case OPC_DCLZ: 13812 check_insn(ctx, ISA_MIPS_R1); 13813 check_mips_64(ctx); 13814 gen_cl(ctx, op1, rd, rs); 13815 break; 13816 case OPC_DMULT_G_2F: 13817 case OPC_DMULTU_G_2F: 13818 case OPC_DDIV_G_2F: 13819 case OPC_DDIVU_G_2F: 13820 case OPC_DMOD_G_2F: 13821 case OPC_DMODU_G_2F: 13822 check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); 13823 gen_loongson_integer(ctx, op1, rd, rs, rt); 13824 break; 13825 #endif 13826 default: /* Invalid */ 13827 MIPS_INVAL("special2_legacy"); 13828 gen_reserved_instruction(ctx); 13829 break; 13830 } 13831 } 13832 13833 static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) 13834 { 13835 int rs, rt, rd, sa; 13836 uint32_t op1, op2; 13837 int16_t imm; 13838 13839 rs = (ctx->opcode >> 21) & 0x1f; 13840 rt = (ctx->opcode >> 16) & 0x1f; 13841 rd = (ctx->opcode >> 11) & 0x1f; 13842 sa = (ctx->opcode >> 6) & 0x1f; 13843 imm = (int16_t)ctx->opcode >> 7; 13844 13845 op1 = MASK_SPECIAL3(ctx->opcode); 13846 switch (op1) { 13847 case R6_OPC_PREF: 13848 if (rt >= 24) { 13849 /* hint codes 24-31 are reserved and signal RI */ 13850 gen_reserved_instruction(ctx); 13851 } 13852 /* Treat as NOP. */ 13853 break; 13854 case R6_OPC_CACHE: 13855 check_cp0_enabled(ctx); 13856 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { 13857 gen_cache_operation(ctx, rt, rs, imm); 13858 } 13859 break; 13860 case R6_OPC_SC: 13861 gen_st_cond(ctx, rt, rs, imm, MO_TESL, false); 13862 break; 13863 case R6_OPC_LL: 13864 gen_ld(ctx, op1, rt, rs, imm); 13865 break; 13866 case OPC_BSHFL: 13867 { 13868 if (rd == 0) { 13869 /* Treat as NOP. */ 13870 break; 13871 } 13872 op2 = MASK_BSHFL(ctx->opcode); 13873 switch (op2) { 13874 case OPC_ALIGN: 13875 case OPC_ALIGN_1: 13876 case OPC_ALIGN_2: 13877 case OPC_ALIGN_3: 13878 gen_align(ctx, 32, rd, rs, rt, sa & 3); 13879 break; 13880 case OPC_BITSWAP: 13881 gen_bitswap(ctx, op2, rd, rt); 13882 break; 13883 } 13884 } 13885 break; 13886 #ifndef CONFIG_USER_ONLY 13887 case OPC_GINV: 13888 if (unlikely(ctx->gi <= 1)) { 13889 gen_reserved_instruction(ctx); 13890 } 13891 check_cp0_enabled(ctx); 13892 switch ((ctx->opcode >> 6) & 3) { 13893 case 0: /* GINVI */ 13894 /* Treat as NOP. */ 13895 break; 13896 case 2: /* GINVT */ 13897 gen_helper_0e1i(ginvt, cpu_gpr[rs], extract32(ctx->opcode, 8, 2)); 13898 break; 13899 default: 13900 gen_reserved_instruction(ctx); 13901 break; 13902 } 13903 break; 13904 #endif 13905 #if defined(TARGET_MIPS64) 13906 case R6_OPC_SCD: 13907 gen_st_cond(ctx, rt, rs, imm, MO_TEUQ, false); 13908 break; 13909 case R6_OPC_LLD: 13910 gen_ld(ctx, op1, rt, rs, imm); 13911 break; 13912 case OPC_DBSHFL: 13913 check_mips_64(ctx); 13914 { 13915 if (rd == 0) { 13916 /* Treat as NOP. */ 13917 break; 13918 } 13919 op2 = MASK_DBSHFL(ctx->opcode); 13920 switch (op2) { 13921 case OPC_DALIGN: 13922 case OPC_DALIGN_1: 13923 case OPC_DALIGN_2: 13924 case OPC_DALIGN_3: 13925 case OPC_DALIGN_4: 13926 case OPC_DALIGN_5: 13927 case OPC_DALIGN_6: 13928 case OPC_DALIGN_7: 13929 gen_align(ctx, 64, rd, rs, rt, sa & 7); 13930 break; 13931 case OPC_DBITSWAP: 13932 gen_bitswap(ctx, op2, rd, rt); 13933 break; 13934 } 13935 13936 } 13937 break; 13938 #endif 13939 default: /* Invalid */ 13940 MIPS_INVAL("special3_r6"); 13941 gen_reserved_instruction(ctx); 13942 break; 13943 } 13944 } 13945 13946 static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) 13947 { 13948 int rs, rt, rd; 13949 uint32_t op1, op2; 13950 13951 rs = (ctx->opcode >> 21) & 0x1f; 13952 rt = (ctx->opcode >> 16) & 0x1f; 13953 rd = (ctx->opcode >> 11) & 0x1f; 13954 13955 op1 = MASK_SPECIAL3(ctx->opcode); 13956 switch (op1) { 13957 case OPC_DIV_G_2E: 13958 case OPC_DIVU_G_2E: 13959 case OPC_MOD_G_2E: 13960 case OPC_MODU_G_2E: 13961 case OPC_MULT_G_2E: 13962 case OPC_MULTU_G_2E: 13963 /* 13964 * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have 13965 * the same mask and op1. 13966 */ 13967 if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MULT_G_2E)) { 13968 op2 = MASK_ADDUH_QB(ctx->opcode); 13969 switch (op2) { 13970 case OPC_ADDUH_QB: 13971 case OPC_ADDUH_R_QB: 13972 case OPC_ADDQH_PH: 13973 case OPC_ADDQH_R_PH: 13974 case OPC_ADDQH_W: 13975 case OPC_ADDQH_R_W: 13976 case OPC_SUBUH_QB: 13977 case OPC_SUBUH_R_QB: 13978 case OPC_SUBQH_PH: 13979 case OPC_SUBQH_R_PH: 13980 case OPC_SUBQH_W: 13981 case OPC_SUBQH_R_W: 13982 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 13983 break; 13984 case OPC_MUL_PH: 13985 case OPC_MUL_S_PH: 13986 case OPC_MULQ_S_W: 13987 case OPC_MULQ_RS_W: 13988 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1); 13989 break; 13990 default: 13991 MIPS_INVAL("MASK ADDUH.QB"); 13992 gen_reserved_instruction(ctx); 13993 break; 13994 } 13995 } else if (ctx->insn_flags & INSN_LOONGSON2E) { 13996 gen_loongson_integer(ctx, op1, rd, rs, rt); 13997 } else { 13998 gen_reserved_instruction(ctx); 13999 } 14000 break; 14001 case OPC_LX_DSP: 14002 op2 = MASK_LX(ctx->opcode); 14003 switch (op2) { 14004 #if defined(TARGET_MIPS64) 14005 case OPC_LDX: 14006 #endif 14007 case OPC_LBUX: 14008 case OPC_LHX: 14009 case OPC_LWX: 14010 gen_mips_lx(ctx, op2, rd, rs, rt); 14011 break; 14012 default: /* Invalid */ 14013 MIPS_INVAL("MASK LX"); 14014 gen_reserved_instruction(ctx); 14015 break; 14016 } 14017 break; 14018 case OPC_ABSQ_S_PH_DSP: 14019 op2 = MASK_ABSQ_S_PH(ctx->opcode); 14020 switch (op2) { 14021 case OPC_ABSQ_S_QB: 14022 case OPC_ABSQ_S_PH: 14023 case OPC_ABSQ_S_W: 14024 case OPC_PRECEQ_W_PHL: 14025 case OPC_PRECEQ_W_PHR: 14026 case OPC_PRECEQU_PH_QBL: 14027 case OPC_PRECEQU_PH_QBR: 14028 case OPC_PRECEQU_PH_QBLA: 14029 case OPC_PRECEQU_PH_QBRA: 14030 case OPC_PRECEU_PH_QBL: 14031 case OPC_PRECEU_PH_QBR: 14032 case OPC_PRECEU_PH_QBLA: 14033 case OPC_PRECEU_PH_QBRA: 14034 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 14035 break; 14036 case OPC_BITREV: 14037 case OPC_REPL_QB: 14038 case OPC_REPLV_QB: 14039 case OPC_REPL_PH: 14040 case OPC_REPLV_PH: 14041 gen_mipsdsp_bitinsn(ctx, op1, op2, rd, rt); 14042 break; 14043 default: 14044 MIPS_INVAL("MASK ABSQ_S.PH"); 14045 gen_reserved_instruction(ctx); 14046 break; 14047 } 14048 break; 14049 case OPC_ADDU_QB_DSP: 14050 op2 = MASK_ADDU_QB(ctx->opcode); 14051 switch (op2) { 14052 case OPC_ADDQ_PH: 14053 case OPC_ADDQ_S_PH: 14054 case OPC_ADDQ_S_W: 14055 case OPC_ADDU_QB: 14056 case OPC_ADDU_S_QB: 14057 case OPC_ADDU_PH: 14058 case OPC_ADDU_S_PH: 14059 case OPC_SUBQ_PH: 14060 case OPC_SUBQ_S_PH: 14061 case OPC_SUBQ_S_W: 14062 case OPC_SUBU_QB: 14063 case OPC_SUBU_S_QB: 14064 case OPC_SUBU_PH: 14065 case OPC_SUBU_S_PH: 14066 case OPC_ADDSC: 14067 case OPC_ADDWC: 14068 case OPC_MODSUB: 14069 case OPC_RADDU_W_QB: 14070 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 14071 break; 14072 case OPC_MULEU_S_PH_QBL: 14073 case OPC_MULEU_S_PH_QBR: 14074 case OPC_MULQ_RS_PH: 14075 case OPC_MULEQ_S_W_PHL: 14076 case OPC_MULEQ_S_W_PHR: 14077 case OPC_MULQ_S_PH: 14078 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1); 14079 break; 14080 default: /* Invalid */ 14081 MIPS_INVAL("MASK ADDU.QB"); 14082 gen_reserved_instruction(ctx); 14083 break; 14084 14085 } 14086 break; 14087 case OPC_CMPU_EQ_QB_DSP: 14088 op2 = MASK_CMPU_EQ_QB(ctx->opcode); 14089 switch (op2) { 14090 case OPC_PRECR_SRA_PH_W: 14091 case OPC_PRECR_SRA_R_PH_W: 14092 gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd); 14093 break; 14094 case OPC_PRECR_QB_PH: 14095 case OPC_PRECRQ_QB_PH: 14096 case OPC_PRECRQ_PH_W: 14097 case OPC_PRECRQ_RS_PH_W: 14098 case OPC_PRECRQU_S_QB_PH: 14099 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 14100 break; 14101 case OPC_CMPU_EQ_QB: 14102 case OPC_CMPU_LT_QB: 14103 case OPC_CMPU_LE_QB: 14104 case OPC_CMP_EQ_PH: 14105 case OPC_CMP_LT_PH: 14106 case OPC_CMP_LE_PH: 14107 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0); 14108 break; 14109 case OPC_CMPGU_EQ_QB: 14110 case OPC_CMPGU_LT_QB: 14111 case OPC_CMPGU_LE_QB: 14112 case OPC_CMPGDU_EQ_QB: 14113 case OPC_CMPGDU_LT_QB: 14114 case OPC_CMPGDU_LE_QB: 14115 case OPC_PICK_QB: 14116 case OPC_PICK_PH: 14117 case OPC_PACKRL_PH: 14118 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1); 14119 break; 14120 default: /* Invalid */ 14121 MIPS_INVAL("MASK CMPU.EQ.QB"); 14122 gen_reserved_instruction(ctx); 14123 break; 14124 } 14125 break; 14126 case OPC_SHLL_QB_DSP: 14127 gen_mipsdsp_shift(ctx, op1, rd, rs, rt); 14128 break; 14129 case OPC_DPA_W_PH_DSP: 14130 op2 = MASK_DPA_W_PH(ctx->opcode); 14131 switch (op2) { 14132 case OPC_DPAU_H_QBL: 14133 case OPC_DPAU_H_QBR: 14134 case OPC_DPSU_H_QBL: 14135 case OPC_DPSU_H_QBR: 14136 case OPC_DPA_W_PH: 14137 case OPC_DPAX_W_PH: 14138 case OPC_DPAQ_S_W_PH: 14139 case OPC_DPAQX_S_W_PH: 14140 case OPC_DPAQX_SA_W_PH: 14141 case OPC_DPS_W_PH: 14142 case OPC_DPSX_W_PH: 14143 case OPC_DPSQ_S_W_PH: 14144 case OPC_DPSQX_S_W_PH: 14145 case OPC_DPSQX_SA_W_PH: 14146 case OPC_MULSAQ_S_W_PH: 14147 case OPC_DPAQ_SA_L_W: 14148 case OPC_DPSQ_SA_L_W: 14149 case OPC_MAQ_S_W_PHL: 14150 case OPC_MAQ_S_W_PHR: 14151 case OPC_MAQ_SA_W_PHL: 14152 case OPC_MAQ_SA_W_PHR: 14153 case OPC_MULSA_W_PH: 14154 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0); 14155 break; 14156 default: /* Invalid */ 14157 MIPS_INVAL("MASK DPAW.PH"); 14158 gen_reserved_instruction(ctx); 14159 break; 14160 } 14161 break; 14162 case OPC_INSV_DSP: 14163 op2 = MASK_INSV(ctx->opcode); 14164 switch (op2) { 14165 case OPC_INSV: 14166 check_dsp(ctx); 14167 { 14168 TCGv t0, t1; 14169 14170 if (rt == 0) { 14171 break; 14172 } 14173 14174 t0 = tcg_temp_new(); 14175 t1 = tcg_temp_new(); 14176 14177 gen_load_gpr(t0, rt); 14178 gen_load_gpr(t1, rs); 14179 14180 gen_helper_insv(cpu_gpr[rt], cpu_env, t1, t0); 14181 break; 14182 } 14183 default: /* Invalid */ 14184 MIPS_INVAL("MASK INSV"); 14185 gen_reserved_instruction(ctx); 14186 break; 14187 } 14188 break; 14189 case OPC_APPEND_DSP: 14190 gen_mipsdsp_append(env, ctx, op1, rt, rs, rd); 14191 break; 14192 case OPC_EXTR_W_DSP: 14193 op2 = MASK_EXTR_W(ctx->opcode); 14194 switch (op2) { 14195 case OPC_EXTR_W: 14196 case OPC_EXTR_R_W: 14197 case OPC_EXTR_RS_W: 14198 case OPC_EXTR_S_H: 14199 case OPC_EXTRV_S_H: 14200 case OPC_EXTRV_W: 14201 case OPC_EXTRV_R_W: 14202 case OPC_EXTRV_RS_W: 14203 case OPC_EXTP: 14204 case OPC_EXTPV: 14205 case OPC_EXTPDP: 14206 case OPC_EXTPDPV: 14207 gen_mipsdsp_accinsn(ctx, op1, op2, rt, rs, rd, 1); 14208 break; 14209 case OPC_RDDSP: 14210 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 1); 14211 break; 14212 case OPC_SHILO: 14213 case OPC_SHILOV: 14214 case OPC_MTHLIP: 14215 case OPC_WRDSP: 14216 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 0); 14217 break; 14218 default: /* Invalid */ 14219 MIPS_INVAL("MASK EXTR.W"); 14220 gen_reserved_instruction(ctx); 14221 break; 14222 } 14223 break; 14224 #if defined(TARGET_MIPS64) 14225 case OPC_DDIV_G_2E: 14226 case OPC_DDIVU_G_2E: 14227 case OPC_DMULT_G_2E: 14228 case OPC_DMULTU_G_2E: 14229 case OPC_DMOD_G_2E: 14230 case OPC_DMODU_G_2E: 14231 check_insn(ctx, INSN_LOONGSON2E); 14232 gen_loongson_integer(ctx, op1, rd, rs, rt); 14233 break; 14234 case OPC_ABSQ_S_QH_DSP: 14235 op2 = MASK_ABSQ_S_QH(ctx->opcode); 14236 switch (op2) { 14237 case OPC_PRECEQ_L_PWL: 14238 case OPC_PRECEQ_L_PWR: 14239 case OPC_PRECEQ_PW_QHL: 14240 case OPC_PRECEQ_PW_QHR: 14241 case OPC_PRECEQ_PW_QHLA: 14242 case OPC_PRECEQ_PW_QHRA: 14243 case OPC_PRECEQU_QH_OBL: 14244 case OPC_PRECEQU_QH_OBR: 14245 case OPC_PRECEQU_QH_OBLA: 14246 case OPC_PRECEQU_QH_OBRA: 14247 case OPC_PRECEU_QH_OBL: 14248 case OPC_PRECEU_QH_OBR: 14249 case OPC_PRECEU_QH_OBLA: 14250 case OPC_PRECEU_QH_OBRA: 14251 case OPC_ABSQ_S_OB: 14252 case OPC_ABSQ_S_PW: 14253 case OPC_ABSQ_S_QH: 14254 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 14255 break; 14256 case OPC_REPL_OB: 14257 case OPC_REPL_PW: 14258 case OPC_REPL_QH: 14259 case OPC_REPLV_OB: 14260 case OPC_REPLV_PW: 14261 case OPC_REPLV_QH: 14262 gen_mipsdsp_bitinsn(ctx, op1, op2, rd, rt); 14263 break; 14264 default: /* Invalid */ 14265 MIPS_INVAL("MASK ABSQ_S.QH"); 14266 gen_reserved_instruction(ctx); 14267 break; 14268 } 14269 break; 14270 case OPC_ADDU_OB_DSP: 14271 op2 = MASK_ADDU_OB(ctx->opcode); 14272 switch (op2) { 14273 case OPC_RADDU_L_OB: 14274 case OPC_SUBQ_PW: 14275 case OPC_SUBQ_S_PW: 14276 case OPC_SUBQ_QH: 14277 case OPC_SUBQ_S_QH: 14278 case OPC_SUBU_OB: 14279 case OPC_SUBU_S_OB: 14280 case OPC_SUBU_QH: 14281 case OPC_SUBU_S_QH: 14282 case OPC_SUBUH_OB: 14283 case OPC_SUBUH_R_OB: 14284 case OPC_ADDQ_PW: 14285 case OPC_ADDQ_S_PW: 14286 case OPC_ADDQ_QH: 14287 case OPC_ADDQ_S_QH: 14288 case OPC_ADDU_OB: 14289 case OPC_ADDU_S_OB: 14290 case OPC_ADDU_QH: 14291 case OPC_ADDU_S_QH: 14292 case OPC_ADDUH_OB: 14293 case OPC_ADDUH_R_OB: 14294 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 14295 break; 14296 case OPC_MULEQ_S_PW_QHL: 14297 case OPC_MULEQ_S_PW_QHR: 14298 case OPC_MULEU_S_QH_OBL: 14299 case OPC_MULEU_S_QH_OBR: 14300 case OPC_MULQ_RS_QH: 14301 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1); 14302 break; 14303 default: /* Invalid */ 14304 MIPS_INVAL("MASK ADDU.OB"); 14305 gen_reserved_instruction(ctx); 14306 break; 14307 } 14308 break; 14309 case OPC_CMPU_EQ_OB_DSP: 14310 op2 = MASK_CMPU_EQ_OB(ctx->opcode); 14311 switch (op2) { 14312 case OPC_PRECR_SRA_QH_PW: 14313 case OPC_PRECR_SRA_R_QH_PW: 14314 /* Return value is rt. */ 14315 gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd); 14316 break; 14317 case OPC_PRECR_OB_QH: 14318 case OPC_PRECRQ_OB_QH: 14319 case OPC_PRECRQ_PW_L: 14320 case OPC_PRECRQ_QH_PW: 14321 case OPC_PRECRQ_RS_QH_PW: 14322 case OPC_PRECRQU_S_OB_QH: 14323 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 14324 break; 14325 case OPC_CMPU_EQ_OB: 14326 case OPC_CMPU_LT_OB: 14327 case OPC_CMPU_LE_OB: 14328 case OPC_CMP_EQ_QH: 14329 case OPC_CMP_LT_QH: 14330 case OPC_CMP_LE_QH: 14331 case OPC_CMP_EQ_PW: 14332 case OPC_CMP_LT_PW: 14333 case OPC_CMP_LE_PW: 14334 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0); 14335 break; 14336 case OPC_CMPGDU_EQ_OB: 14337 case OPC_CMPGDU_LT_OB: 14338 case OPC_CMPGDU_LE_OB: 14339 case OPC_CMPGU_EQ_OB: 14340 case OPC_CMPGU_LT_OB: 14341 case OPC_CMPGU_LE_OB: 14342 case OPC_PACKRL_PW: 14343 case OPC_PICK_OB: 14344 case OPC_PICK_PW: 14345 case OPC_PICK_QH: 14346 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1); 14347 break; 14348 default: /* Invalid */ 14349 MIPS_INVAL("MASK CMPU_EQ.OB"); 14350 gen_reserved_instruction(ctx); 14351 break; 14352 } 14353 break; 14354 case OPC_DAPPEND_DSP: 14355 gen_mipsdsp_append(env, ctx, op1, rt, rs, rd); 14356 break; 14357 case OPC_DEXTR_W_DSP: 14358 op2 = MASK_DEXTR_W(ctx->opcode); 14359 switch (op2) { 14360 case OPC_DEXTP: 14361 case OPC_DEXTPDP: 14362 case OPC_DEXTPDPV: 14363 case OPC_DEXTPV: 14364 case OPC_DEXTR_L: 14365 case OPC_DEXTR_R_L: 14366 case OPC_DEXTR_RS_L: 14367 case OPC_DEXTR_W: 14368 case OPC_DEXTR_R_W: 14369 case OPC_DEXTR_RS_W: 14370 case OPC_DEXTR_S_H: 14371 case OPC_DEXTRV_L: 14372 case OPC_DEXTRV_R_L: 14373 case OPC_DEXTRV_RS_L: 14374 case OPC_DEXTRV_S_H: 14375 case OPC_DEXTRV_W: 14376 case OPC_DEXTRV_R_W: 14377 case OPC_DEXTRV_RS_W: 14378 gen_mipsdsp_accinsn(ctx, op1, op2, rt, rs, rd, 1); 14379 break; 14380 case OPC_DMTHLIP: 14381 case OPC_DSHILO: 14382 case OPC_DSHILOV: 14383 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 0); 14384 break; 14385 default: /* Invalid */ 14386 MIPS_INVAL("MASK EXTR.W"); 14387 gen_reserved_instruction(ctx); 14388 break; 14389 } 14390 break; 14391 case OPC_DPAQ_W_QH_DSP: 14392 op2 = MASK_DPAQ_W_QH(ctx->opcode); 14393 switch (op2) { 14394 case OPC_DPAU_H_OBL: 14395 case OPC_DPAU_H_OBR: 14396 case OPC_DPSU_H_OBL: 14397 case OPC_DPSU_H_OBR: 14398 case OPC_DPA_W_QH: 14399 case OPC_DPAQ_S_W_QH: 14400 case OPC_DPS_W_QH: 14401 case OPC_DPSQ_S_W_QH: 14402 case OPC_MULSAQ_S_W_QH: 14403 case OPC_DPAQ_SA_L_PW: 14404 case OPC_DPSQ_SA_L_PW: 14405 case OPC_MULSAQ_S_L_PW: 14406 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0); 14407 break; 14408 case OPC_MAQ_S_W_QHLL: 14409 case OPC_MAQ_S_W_QHLR: 14410 case OPC_MAQ_S_W_QHRL: 14411 case OPC_MAQ_S_W_QHRR: 14412 case OPC_MAQ_SA_W_QHLL: 14413 case OPC_MAQ_SA_W_QHLR: 14414 case OPC_MAQ_SA_W_QHRL: 14415 case OPC_MAQ_SA_W_QHRR: 14416 case OPC_MAQ_S_L_PWL: 14417 case OPC_MAQ_S_L_PWR: 14418 case OPC_DMADD: 14419 case OPC_DMADDU: 14420 case OPC_DMSUB: 14421 case OPC_DMSUBU: 14422 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0); 14423 break; 14424 default: /* Invalid */ 14425 MIPS_INVAL("MASK DPAQ.W.QH"); 14426 gen_reserved_instruction(ctx); 14427 break; 14428 } 14429 break; 14430 case OPC_DINSV_DSP: 14431 op2 = MASK_INSV(ctx->opcode); 14432 switch (op2) { 14433 case OPC_DINSV: 14434 { 14435 TCGv t0, t1; 14436 14437 check_dsp(ctx); 14438 14439 if (rt == 0) { 14440 break; 14441 } 14442 14443 t0 = tcg_temp_new(); 14444 t1 = tcg_temp_new(); 14445 14446 gen_load_gpr(t0, rt); 14447 gen_load_gpr(t1, rs); 14448 14449 gen_helper_dinsv(cpu_gpr[rt], cpu_env, t1, t0); 14450 break; 14451 } 14452 default: /* Invalid */ 14453 MIPS_INVAL("MASK DINSV"); 14454 gen_reserved_instruction(ctx); 14455 break; 14456 } 14457 break; 14458 case OPC_SHLL_OB_DSP: 14459 gen_mipsdsp_shift(ctx, op1, rd, rs, rt); 14460 break; 14461 #endif 14462 default: /* Invalid */ 14463 MIPS_INVAL("special3_legacy"); 14464 gen_reserved_instruction(ctx); 14465 break; 14466 } 14467 } 14468 14469 14470 #if defined(TARGET_MIPS64) 14471 14472 static void decode_mmi(CPUMIPSState *env, DisasContext *ctx) 14473 { 14474 uint32_t opc = MASK_MMI(ctx->opcode); 14475 int rs = extract32(ctx->opcode, 21, 5); 14476 int rt = extract32(ctx->opcode, 16, 5); 14477 int rd = extract32(ctx->opcode, 11, 5); 14478 14479 switch (opc) { 14480 case MMI_OPC_MULT1: 14481 case MMI_OPC_MULTU1: 14482 case MMI_OPC_MADD: 14483 case MMI_OPC_MADDU: 14484 case MMI_OPC_MADD1: 14485 case MMI_OPC_MADDU1: 14486 gen_mul_txx9(ctx, opc, rd, rs, rt); 14487 break; 14488 case MMI_OPC_DIV1: 14489 case MMI_OPC_DIVU1: 14490 gen_div1_tx79(ctx, opc, rs, rt); 14491 break; 14492 default: 14493 MIPS_INVAL("TX79 MMI class"); 14494 gen_reserved_instruction(ctx); 14495 break; 14496 } 14497 } 14498 14499 static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset) 14500 { 14501 gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */ 14502 } 14503 14504 /* 14505 * The TX79-specific instruction Store Quadword 14506 * 14507 * +--------+-------+-------+------------------------+ 14508 * | 011111 | base | rt | offset | SQ 14509 * +--------+-------+-------+------------------------+ 14510 * 6 5 5 16 14511 * 14512 * has the same opcode as the Read Hardware Register instruction 14513 * 14514 * +--------+-------+-------+-------+-------+--------+ 14515 * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR 14516 * +--------+-------+-------+-------+-------+--------+ 14517 * 6 5 5 5 5 6 14518 * 14519 * that is required, trapped and emulated by the Linux kernel. However, all 14520 * RDHWR encodings yield address error exceptions on the TX79 since the SQ 14521 * offset is odd. Therefore all valid SQ instructions can execute normally. 14522 * In user mode, QEMU must verify the upper and lower 11 bits to distinguish 14523 * between SQ and RDHWR, as the Linux kernel does. 14524 */ 14525 static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx) 14526 { 14527 int base = extract32(ctx->opcode, 21, 5); 14528 int rt = extract32(ctx->opcode, 16, 5); 14529 int offset = extract32(ctx->opcode, 0, 16); 14530 14531 #ifdef CONFIG_USER_ONLY 14532 uint32_t op1 = MASK_SPECIAL3(ctx->opcode); 14533 uint32_t op2 = extract32(ctx->opcode, 6, 5); 14534 14535 if (base == 0 && op2 == 0 && op1 == OPC_RDHWR) { 14536 int rd = extract32(ctx->opcode, 11, 5); 14537 14538 gen_rdhwr(ctx, rt, rd, 0); 14539 return; 14540 } 14541 #endif 14542 14543 gen_mmi_sq(ctx, base, rt, offset); 14544 } 14545 14546 #endif 14547 14548 static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) 14549 { 14550 int rs, rt, rd, sa; 14551 uint32_t op1, op2; 14552 int16_t imm; 14553 14554 rs = (ctx->opcode >> 21) & 0x1f; 14555 rt = (ctx->opcode >> 16) & 0x1f; 14556 rd = (ctx->opcode >> 11) & 0x1f; 14557 sa = (ctx->opcode >> 6) & 0x1f; 14558 imm = sextract32(ctx->opcode, 7, 9); 14559 14560 op1 = MASK_SPECIAL3(ctx->opcode); 14561 14562 /* 14563 * EVA loads and stores overlap Loongson 2E instructions decoded by 14564 * decode_opc_special3_legacy(), so be careful to allow their decoding when 14565 * EVA is absent. 14566 */ 14567 if (ctx->eva) { 14568 switch (op1) { 14569 case OPC_LWLE: 14570 case OPC_LWRE: 14571 case OPC_LBUE: 14572 case OPC_LHUE: 14573 case OPC_LBE: 14574 case OPC_LHE: 14575 case OPC_LLE: 14576 case OPC_LWE: 14577 check_cp0_enabled(ctx); 14578 gen_ld(ctx, op1, rt, rs, imm); 14579 return; 14580 case OPC_SWLE: 14581 case OPC_SWRE: 14582 case OPC_SBE: 14583 case OPC_SHE: 14584 case OPC_SWE: 14585 check_cp0_enabled(ctx); 14586 gen_st(ctx, op1, rt, rs, imm); 14587 return; 14588 case OPC_SCE: 14589 check_cp0_enabled(ctx); 14590 gen_st_cond(ctx, rt, rs, imm, MO_TESL, true); 14591 return; 14592 case OPC_CACHEE: 14593 check_eva(ctx); 14594 check_cp0_enabled(ctx); 14595 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { 14596 gen_cache_operation(ctx, rt, rs, imm); 14597 } 14598 return; 14599 case OPC_PREFE: 14600 check_cp0_enabled(ctx); 14601 /* Treat as NOP. */ 14602 return; 14603 } 14604 } 14605 14606 switch (op1) { 14607 case OPC_EXT: 14608 case OPC_INS: 14609 check_insn(ctx, ISA_MIPS_R2); 14610 gen_bitops(ctx, op1, rt, rs, sa, rd); 14611 break; 14612 case OPC_BSHFL: 14613 op2 = MASK_BSHFL(ctx->opcode); 14614 switch (op2) { 14615 case OPC_ALIGN: 14616 case OPC_ALIGN_1: 14617 case OPC_ALIGN_2: 14618 case OPC_ALIGN_3: 14619 case OPC_BITSWAP: 14620 check_insn(ctx, ISA_MIPS_R6); 14621 decode_opc_special3_r6(env, ctx); 14622 break; 14623 default: 14624 check_insn(ctx, ISA_MIPS_R2); 14625 gen_bshfl(ctx, op2, rt, rd); 14626 break; 14627 } 14628 break; 14629 #if defined(TARGET_MIPS64) 14630 case OPC_DEXTM: 14631 case OPC_DEXTU: 14632 case OPC_DEXT: 14633 case OPC_DINSM: 14634 case OPC_DINSU: 14635 case OPC_DINS: 14636 check_insn(ctx, ISA_MIPS_R2); 14637 check_mips_64(ctx); 14638 gen_bitops(ctx, op1, rt, rs, sa, rd); 14639 break; 14640 case OPC_DBSHFL: 14641 op2 = MASK_DBSHFL(ctx->opcode); 14642 switch (op2) { 14643 case OPC_DALIGN: 14644 case OPC_DALIGN_1: 14645 case OPC_DALIGN_2: 14646 case OPC_DALIGN_3: 14647 case OPC_DALIGN_4: 14648 case OPC_DALIGN_5: 14649 case OPC_DALIGN_6: 14650 case OPC_DALIGN_7: 14651 case OPC_DBITSWAP: 14652 check_insn(ctx, ISA_MIPS_R6); 14653 decode_opc_special3_r6(env, ctx); 14654 break; 14655 default: 14656 check_insn(ctx, ISA_MIPS_R2); 14657 check_mips_64(ctx); 14658 op2 = MASK_DBSHFL(ctx->opcode); 14659 gen_bshfl(ctx, op2, rt, rd); 14660 break; 14661 } 14662 break; 14663 #endif 14664 case OPC_RDHWR: 14665 gen_rdhwr(ctx, rt, rd, extract32(ctx->opcode, 6, 3)); 14666 break; 14667 case OPC_FORK: 14668 check_mt(ctx); 14669 { 14670 TCGv t0 = tcg_temp_new(); 14671 TCGv t1 = tcg_temp_new(); 14672 14673 gen_load_gpr(t0, rt); 14674 gen_load_gpr(t1, rs); 14675 gen_helper_fork(t0, t1); 14676 } 14677 break; 14678 case OPC_YIELD: 14679 check_mt(ctx); 14680 { 14681 TCGv t0 = tcg_temp_new(); 14682 14683 gen_load_gpr(t0, rs); 14684 gen_helper_yield(t0, cpu_env, t0); 14685 gen_store_gpr(t0, rd); 14686 } 14687 break; 14688 default: 14689 if (ctx->insn_flags & ISA_MIPS_R6) { 14690 decode_opc_special3_r6(env, ctx); 14691 } else { 14692 decode_opc_special3_legacy(env, ctx); 14693 } 14694 } 14695 } 14696 14697 static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) 14698 { 14699 int32_t offset; 14700 int rs, rt, rd, sa; 14701 uint32_t op, op1; 14702 int16_t imm; 14703 14704 op = MASK_OP_MAJOR(ctx->opcode); 14705 rs = (ctx->opcode >> 21) & 0x1f; 14706 rt = (ctx->opcode >> 16) & 0x1f; 14707 rd = (ctx->opcode >> 11) & 0x1f; 14708 sa = (ctx->opcode >> 6) & 0x1f; 14709 imm = (int16_t)ctx->opcode; 14710 switch (op) { 14711 case OPC_SPECIAL: 14712 decode_opc_special(env, ctx); 14713 break; 14714 case OPC_SPECIAL2: 14715 #if defined(TARGET_MIPS64) 14716 if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) { 14717 decode_mmi(env, ctx); 14718 break; 14719 } 14720 #endif 14721 if (TARGET_LONG_BITS == 32 && (ctx->insn_flags & ASE_MXU)) { 14722 if (MASK_SPECIAL2(ctx->opcode) == OPC_MUL) { 14723 gen_arith(ctx, OPC_MUL, rd, rs, rt); 14724 } else { 14725 decode_ase_mxu(ctx, ctx->opcode); 14726 } 14727 break; 14728 } 14729 decode_opc_special2_legacy(env, ctx); 14730 break; 14731 case OPC_SPECIAL3: 14732 #if defined(TARGET_MIPS64) 14733 if (ctx->insn_flags & INSN_R5900) { 14734 decode_mmi_sq(env, ctx); /* MMI_OPC_SQ */ 14735 } else { 14736 decode_opc_special3(env, ctx); 14737 } 14738 #else 14739 decode_opc_special3(env, ctx); 14740 #endif 14741 break; 14742 case OPC_REGIMM: 14743 op1 = MASK_REGIMM(ctx->opcode); 14744 switch (op1) { 14745 case OPC_BLTZL: /* REGIMM branches */ 14746 case OPC_BGEZL: 14747 case OPC_BLTZALL: 14748 case OPC_BGEZALL: 14749 check_insn(ctx, ISA_MIPS2); 14750 check_insn_opc_removed(ctx, ISA_MIPS_R6); 14751 /* Fallthrough */ 14752 case OPC_BLTZ: 14753 case OPC_BGEZ: 14754 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); 14755 break; 14756 case OPC_BLTZAL: 14757 case OPC_BGEZAL: 14758 if (ctx->insn_flags & ISA_MIPS_R6) { 14759 if (rs == 0) { 14760 /* OPC_NAL, OPC_BAL */ 14761 gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4); 14762 } else { 14763 gen_reserved_instruction(ctx); 14764 } 14765 } else { 14766 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); 14767 } 14768 break; 14769 case OPC_TGEI: /* REGIMM traps */ 14770 case OPC_TGEIU: 14771 case OPC_TLTI: 14772 case OPC_TLTIU: 14773 case OPC_TEQI: 14774 case OPC_TNEI: 14775 check_insn(ctx, ISA_MIPS2); 14776 check_insn_opc_removed(ctx, ISA_MIPS_R6); 14777 gen_trap(ctx, op1, rs, -1, imm, 0); 14778 break; 14779 case OPC_SIGRIE: 14780 check_insn(ctx, ISA_MIPS_R6); 14781 gen_reserved_instruction(ctx); 14782 break; 14783 case OPC_SYNCI: 14784 check_insn(ctx, ISA_MIPS_R2); 14785 /* 14786 * Break the TB to be able to sync copied instructions 14787 * immediately. 14788 */ 14789 ctx->base.is_jmp = DISAS_STOP; 14790 break; 14791 case OPC_BPOSGE32: /* MIPS DSP branch */ 14792 #if defined(TARGET_MIPS64) 14793 case OPC_BPOSGE64: 14794 #endif 14795 check_dsp(ctx); 14796 gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2, 4); 14797 break; 14798 #if defined(TARGET_MIPS64) 14799 case OPC_DAHI: 14800 check_insn(ctx, ISA_MIPS_R6); 14801 check_mips_64(ctx); 14802 if (rs != 0) { 14803 tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 32); 14804 } 14805 break; 14806 case OPC_DATI: 14807 check_insn(ctx, ISA_MIPS_R6); 14808 check_mips_64(ctx); 14809 if (rs != 0) { 14810 tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 48); 14811 } 14812 break; 14813 #endif 14814 default: /* Invalid */ 14815 MIPS_INVAL("regimm"); 14816 gen_reserved_instruction(ctx); 14817 break; 14818 } 14819 break; 14820 case OPC_CP0: 14821 check_cp0_enabled(ctx); 14822 op1 = MASK_CP0(ctx->opcode); 14823 switch (op1) { 14824 case OPC_MFC0: 14825 case OPC_MTC0: 14826 case OPC_MFTR: 14827 case OPC_MTTR: 14828 case OPC_MFHC0: 14829 case OPC_MTHC0: 14830 #if defined(TARGET_MIPS64) 14831 case OPC_DMFC0: 14832 case OPC_DMTC0: 14833 #endif 14834 #ifndef CONFIG_USER_ONLY 14835 gen_cp0(env, ctx, op1, rt, rd); 14836 #endif /* !CONFIG_USER_ONLY */ 14837 break; 14838 case OPC_C0: 14839 case OPC_C0_1: 14840 case OPC_C0_2: 14841 case OPC_C0_3: 14842 case OPC_C0_4: 14843 case OPC_C0_5: 14844 case OPC_C0_6: 14845 case OPC_C0_7: 14846 case OPC_C0_8: 14847 case OPC_C0_9: 14848 case OPC_C0_A: 14849 case OPC_C0_B: 14850 case OPC_C0_C: 14851 case OPC_C0_D: 14852 case OPC_C0_E: 14853 case OPC_C0_F: 14854 #ifndef CONFIG_USER_ONLY 14855 gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd); 14856 #endif /* !CONFIG_USER_ONLY */ 14857 break; 14858 case OPC_MFMC0: 14859 #ifndef CONFIG_USER_ONLY 14860 { 14861 uint32_t op2; 14862 TCGv t0 = tcg_temp_new(); 14863 14864 op2 = MASK_MFMC0(ctx->opcode); 14865 switch (op2) { 14866 case OPC_DMT: 14867 check_cp0_mt(ctx); 14868 gen_helper_dmt(t0); 14869 gen_store_gpr(t0, rt); 14870 break; 14871 case OPC_EMT: 14872 check_cp0_mt(ctx); 14873 gen_helper_emt(t0); 14874 gen_store_gpr(t0, rt); 14875 break; 14876 case OPC_DVPE: 14877 check_cp0_mt(ctx); 14878 gen_helper_dvpe(t0, cpu_env); 14879 gen_store_gpr(t0, rt); 14880 break; 14881 case OPC_EVPE: 14882 check_cp0_mt(ctx); 14883 gen_helper_evpe(t0, cpu_env); 14884 gen_store_gpr(t0, rt); 14885 break; 14886 case OPC_DVP: 14887 check_insn(ctx, ISA_MIPS_R6); 14888 if (ctx->vp) { 14889 gen_helper_dvp(t0, cpu_env); 14890 gen_store_gpr(t0, rt); 14891 } 14892 break; 14893 case OPC_EVP: 14894 check_insn(ctx, ISA_MIPS_R6); 14895 if (ctx->vp) { 14896 gen_helper_evp(t0, cpu_env); 14897 gen_store_gpr(t0, rt); 14898 } 14899 break; 14900 case OPC_DI: 14901 check_insn(ctx, ISA_MIPS_R2); 14902 save_cpu_state(ctx, 1); 14903 gen_helper_di(t0, cpu_env); 14904 gen_store_gpr(t0, rt); 14905 /* 14906 * Stop translation as we may have switched 14907 * the execution mode. 14908 */ 14909 ctx->base.is_jmp = DISAS_STOP; 14910 break; 14911 case OPC_EI: 14912 check_insn(ctx, ISA_MIPS_R2); 14913 save_cpu_state(ctx, 1); 14914 gen_helper_ei(t0, cpu_env); 14915 gen_store_gpr(t0, rt); 14916 /* 14917 * DISAS_STOP isn't sufficient, we need to ensure we break 14918 * out of translated code to check for pending interrupts. 14919 */ 14920 gen_save_pc(ctx->base.pc_next + 4); 14921 ctx->base.is_jmp = DISAS_EXIT; 14922 break; 14923 default: /* Invalid */ 14924 MIPS_INVAL("mfmc0"); 14925 gen_reserved_instruction(ctx); 14926 break; 14927 } 14928 } 14929 #endif /* !CONFIG_USER_ONLY */ 14930 break; 14931 case OPC_RDPGPR: 14932 check_insn(ctx, ISA_MIPS_R2); 14933 gen_load_srsgpr(rt, rd); 14934 break; 14935 case OPC_WRPGPR: 14936 check_insn(ctx, ISA_MIPS_R2); 14937 gen_store_srsgpr(rt, rd); 14938 break; 14939 default: 14940 MIPS_INVAL("cp0"); 14941 gen_reserved_instruction(ctx); 14942 break; 14943 } 14944 break; 14945 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC, OPC_ADDI */ 14946 if (ctx->insn_flags & ISA_MIPS_R6) { 14947 /* OPC_BOVC, OPC_BEQZALC, OPC_BEQC */ 14948 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 14949 } else { 14950 /* OPC_ADDI */ 14951 /* Arithmetic with immediate opcode */ 14952 gen_arith_imm(ctx, op, rt, rs, imm); 14953 } 14954 break; 14955 case OPC_ADDIU: 14956 gen_arith_imm(ctx, op, rt, rs, imm); 14957 break; 14958 case OPC_SLTI: /* Set on less than with immediate opcode */ 14959 case OPC_SLTIU: 14960 gen_slt_imm(ctx, op, rt, rs, imm); 14961 break; 14962 case OPC_ANDI: /* Arithmetic with immediate opcode */ 14963 case OPC_LUI: /* OPC_AUI */ 14964 case OPC_ORI: 14965 case OPC_XORI: 14966 gen_logic_imm(ctx, op, rt, rs, imm); 14967 break; 14968 case OPC_J: /* Jump */ 14969 case OPC_JAL: 14970 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; 14971 gen_compute_branch(ctx, op, 4, rs, rt, offset, 4); 14972 break; 14973 /* Branch */ 14974 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */ 14975 if (ctx->insn_flags & ISA_MIPS_R6) { 14976 if (rt == 0) { 14977 gen_reserved_instruction(ctx); 14978 break; 14979 } 14980 /* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */ 14981 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 14982 } else { 14983 /* OPC_BLEZL */ 14984 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); 14985 } 14986 break; 14987 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */ 14988 if (ctx->insn_flags & ISA_MIPS_R6) { 14989 if (rt == 0) { 14990 gen_reserved_instruction(ctx); 14991 break; 14992 } 14993 /* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */ 14994 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 14995 } else { 14996 /* OPC_BGTZL */ 14997 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); 14998 } 14999 break; 15000 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC, OPC_BLEZ */ 15001 if (rt == 0) { 15002 /* OPC_BLEZ */ 15003 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); 15004 } else { 15005 check_insn(ctx, ISA_MIPS_R6); 15006 /* OPC_BLEZALC, OPC_BGEZALC, OPC_BGEUC */ 15007 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 15008 } 15009 break; 15010 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC, OPC_BGTZ */ 15011 if (rt == 0) { 15012 /* OPC_BGTZ */ 15013 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); 15014 } else { 15015 check_insn(ctx, ISA_MIPS_R6); 15016 /* OPC_BGTZALC, OPC_BLTZALC, OPC_BLTUC */ 15017 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 15018 } 15019 break; 15020 case OPC_BEQL: 15021 case OPC_BNEL: 15022 check_insn(ctx, ISA_MIPS2); 15023 check_insn_opc_removed(ctx, ISA_MIPS_R6); 15024 /* Fallthrough */ 15025 case OPC_BEQ: 15026 case OPC_BNE: 15027 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); 15028 break; 15029 case OPC_LL: /* Load and stores */ 15030 check_insn(ctx, ISA_MIPS2); 15031 if (ctx->insn_flags & INSN_R5900) { 15032 check_insn_opc_user_only(ctx, INSN_R5900); 15033 } 15034 /* Fallthrough */ 15035 case OPC_LWL: 15036 case OPC_LWR: 15037 case OPC_LB: 15038 case OPC_LH: 15039 case OPC_LW: 15040 case OPC_LWPC: 15041 case OPC_LBU: 15042 case OPC_LHU: 15043 gen_ld(ctx, op, rt, rs, imm); 15044 break; 15045 case OPC_SWL: 15046 case OPC_SWR: 15047 case OPC_SB: 15048 case OPC_SH: 15049 case OPC_SW: 15050 gen_st(ctx, op, rt, rs, imm); 15051 break; 15052 case OPC_SC: 15053 check_insn(ctx, ISA_MIPS2); 15054 if (ctx->insn_flags & INSN_R5900) { 15055 check_insn_opc_user_only(ctx, INSN_R5900); 15056 } 15057 gen_st_cond(ctx, rt, rs, imm, MO_TESL, false); 15058 break; 15059 case OPC_CACHE: 15060 check_cp0_enabled(ctx); 15061 check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); 15062 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { 15063 gen_cache_operation(ctx, rt, rs, imm); 15064 } 15065 /* Treat as NOP. */ 15066 break; 15067 case OPC_PREF: 15068 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | INSN_R5900); 15069 /* Treat as NOP. */ 15070 break; 15071 15072 /* Floating point (COP1). */ 15073 case OPC_LWC1: 15074 case OPC_LDC1: 15075 case OPC_SWC1: 15076 case OPC_SDC1: 15077 gen_cop1_ldst(ctx, op, rt, rs, imm); 15078 break; 15079 15080 case OPC_CP1: 15081 op1 = MASK_CP1(ctx->opcode); 15082 15083 switch (op1) { 15084 case OPC_MFHC1: 15085 case OPC_MTHC1: 15086 check_cp1_enabled(ctx); 15087 check_insn(ctx, ISA_MIPS_R2); 15088 /* fall through */ 15089 case OPC_MFC1: 15090 case OPC_CFC1: 15091 case OPC_MTC1: 15092 case OPC_CTC1: 15093 check_cp1_enabled(ctx); 15094 gen_cp1(ctx, op1, rt, rd); 15095 break; 15096 #if defined(TARGET_MIPS64) 15097 case OPC_DMFC1: 15098 case OPC_DMTC1: 15099 check_cp1_enabled(ctx); 15100 check_insn(ctx, ISA_MIPS3); 15101 check_mips_64(ctx); 15102 gen_cp1(ctx, op1, rt, rd); 15103 break; 15104 #endif 15105 case OPC_BC1EQZ: /* OPC_BC1ANY2 */ 15106 check_cp1_enabled(ctx); 15107 if (ctx->insn_flags & ISA_MIPS_R6) { 15108 /* OPC_BC1EQZ */ 15109 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), 15110 rt, imm << 2, 4); 15111 } else { 15112 /* OPC_BC1ANY2 */ 15113 check_cop1x(ctx); 15114 check_insn(ctx, ASE_MIPS3D); 15115 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), 15116 (rt >> 2) & 0x7, imm << 2); 15117 } 15118 break; 15119 case OPC_BC1NEZ: 15120 check_cp1_enabled(ctx); 15121 check_insn(ctx, ISA_MIPS_R6); 15122 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), 15123 rt, imm << 2, 4); 15124 break; 15125 case OPC_BC1ANY4: 15126 check_cp1_enabled(ctx); 15127 check_insn_opc_removed(ctx, ISA_MIPS_R6); 15128 check_cop1x(ctx); 15129 check_insn(ctx, ASE_MIPS3D); 15130 /* fall through */ 15131 case OPC_BC1: 15132 check_cp1_enabled(ctx); 15133 check_insn_opc_removed(ctx, ISA_MIPS_R6); 15134 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), 15135 (rt >> 2) & 0x7, imm << 2); 15136 break; 15137 case OPC_PS_FMT: 15138 check_ps(ctx); 15139 /* fall through */ 15140 case OPC_S_FMT: 15141 case OPC_D_FMT: 15142 check_cp1_enabled(ctx); 15143 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa, 15144 (imm >> 8) & 0x7); 15145 break; 15146 case OPC_W_FMT: 15147 case OPC_L_FMT: 15148 { 15149 int r6_op = ctx->opcode & FOP(0x3f, 0x1f); 15150 check_cp1_enabled(ctx); 15151 if (ctx->insn_flags & ISA_MIPS_R6) { 15152 switch (r6_op) { 15153 case R6_OPC_CMP_AF_S: 15154 case R6_OPC_CMP_UN_S: 15155 case R6_OPC_CMP_EQ_S: 15156 case R6_OPC_CMP_UEQ_S: 15157 case R6_OPC_CMP_LT_S: 15158 case R6_OPC_CMP_ULT_S: 15159 case R6_OPC_CMP_LE_S: 15160 case R6_OPC_CMP_ULE_S: 15161 case R6_OPC_CMP_SAF_S: 15162 case R6_OPC_CMP_SUN_S: 15163 case R6_OPC_CMP_SEQ_S: 15164 case R6_OPC_CMP_SEUQ_S: 15165 case R6_OPC_CMP_SLT_S: 15166 case R6_OPC_CMP_SULT_S: 15167 case R6_OPC_CMP_SLE_S: 15168 case R6_OPC_CMP_SULE_S: 15169 case R6_OPC_CMP_OR_S: 15170 case R6_OPC_CMP_UNE_S: 15171 case R6_OPC_CMP_NE_S: 15172 case R6_OPC_CMP_SOR_S: 15173 case R6_OPC_CMP_SUNE_S: 15174 case R6_OPC_CMP_SNE_S: 15175 gen_r6_cmp_s(ctx, ctx->opcode & 0x1f, rt, rd, sa); 15176 break; 15177 case R6_OPC_CMP_AF_D: 15178 case R6_OPC_CMP_UN_D: 15179 case R6_OPC_CMP_EQ_D: 15180 case R6_OPC_CMP_UEQ_D: 15181 case R6_OPC_CMP_LT_D: 15182 case R6_OPC_CMP_ULT_D: 15183 case R6_OPC_CMP_LE_D: 15184 case R6_OPC_CMP_ULE_D: 15185 case R6_OPC_CMP_SAF_D: 15186 case R6_OPC_CMP_SUN_D: 15187 case R6_OPC_CMP_SEQ_D: 15188 case R6_OPC_CMP_SEUQ_D: 15189 case R6_OPC_CMP_SLT_D: 15190 case R6_OPC_CMP_SULT_D: 15191 case R6_OPC_CMP_SLE_D: 15192 case R6_OPC_CMP_SULE_D: 15193 case R6_OPC_CMP_OR_D: 15194 case R6_OPC_CMP_UNE_D: 15195 case R6_OPC_CMP_NE_D: 15196 case R6_OPC_CMP_SOR_D: 15197 case R6_OPC_CMP_SUNE_D: 15198 case R6_OPC_CMP_SNE_D: 15199 gen_r6_cmp_d(ctx, ctx->opcode & 0x1f, rt, rd, sa); 15200 break; 15201 default: 15202 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), 15203 rt, rd, sa, (imm >> 8) & 0x7); 15204 15205 break; 15206 } 15207 } else { 15208 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa, 15209 (imm >> 8) & 0x7); 15210 } 15211 break; 15212 } 15213 default: 15214 MIPS_INVAL("cp1"); 15215 gen_reserved_instruction(ctx); 15216 break; 15217 } 15218 break; 15219 15220 /* Compact branches [R6] and COP2 [non-R6] */ 15221 case OPC_BC: /* OPC_LWC2 */ 15222 case OPC_BALC: /* OPC_SWC2 */ 15223 if (ctx->insn_flags & ISA_MIPS_R6) { 15224 /* OPC_BC, OPC_BALC */ 15225 gen_compute_compact_branch(ctx, op, 0, 0, 15226 sextract32(ctx->opcode << 2, 0, 28)); 15227 } else if (ctx->insn_flags & ASE_LEXT) { 15228 gen_loongson_lswc2(ctx, rt, rs, rd); 15229 } else { 15230 /* OPC_LWC2, OPC_SWC2 */ 15231 /* COP2: Not implemented. */ 15232 generate_exception_err(ctx, EXCP_CpU, 2); 15233 } 15234 break; 15235 case OPC_BEQZC: /* OPC_JIC, OPC_LDC2 */ 15236 case OPC_BNEZC: /* OPC_JIALC, OPC_SDC2 */ 15237 if (ctx->insn_flags & ISA_MIPS_R6) { 15238 if (rs != 0) { 15239 /* OPC_BEQZC, OPC_BNEZC */ 15240 gen_compute_compact_branch(ctx, op, rs, 0, 15241 sextract32(ctx->opcode << 2, 0, 23)); 15242 } else { 15243 /* OPC_JIC, OPC_JIALC */ 15244 gen_compute_compact_branch(ctx, op, 0, rt, imm); 15245 } 15246 } else if (ctx->insn_flags & ASE_LEXT) { 15247 gen_loongson_lsdc2(ctx, rt, rs, rd); 15248 } else { 15249 /* OPC_LWC2, OPC_SWC2 */ 15250 /* COP2: Not implemented. */ 15251 generate_exception_err(ctx, EXCP_CpU, 2); 15252 } 15253 break; 15254 case OPC_CP2: 15255 check_insn(ctx, ASE_LMMI); 15256 /* Note that these instructions use different fields. */ 15257 gen_loongson_multimedia(ctx, sa, rd, rt); 15258 break; 15259 15260 case OPC_CP3: 15261 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { 15262 check_cp1_enabled(ctx); 15263 op1 = MASK_CP3(ctx->opcode); 15264 switch (op1) { 15265 case OPC_LUXC1: 15266 case OPC_SUXC1: 15267 check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2); 15268 /* Fallthrough */ 15269 case OPC_LWXC1: 15270 case OPC_LDXC1: 15271 case OPC_SWXC1: 15272 case OPC_SDXC1: 15273 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); 15274 gen_flt3_ldst(ctx, op1, sa, rd, rs, rt); 15275 break; 15276 case OPC_PREFX: 15277 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); 15278 /* Treat as NOP. */ 15279 break; 15280 case OPC_ALNV_PS: 15281 check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2); 15282 /* Fallthrough */ 15283 case OPC_MADD_S: 15284 case OPC_MADD_D: 15285 case OPC_MADD_PS: 15286 case OPC_MSUB_S: 15287 case OPC_MSUB_D: 15288 case OPC_MSUB_PS: 15289 case OPC_NMADD_S: 15290 case OPC_NMADD_D: 15291 case OPC_NMADD_PS: 15292 case OPC_NMSUB_S: 15293 case OPC_NMSUB_D: 15294 case OPC_NMSUB_PS: 15295 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); 15296 gen_flt3_arith(ctx, op1, sa, rs, rd, rt); 15297 break; 15298 default: 15299 MIPS_INVAL("cp3"); 15300 gen_reserved_instruction(ctx); 15301 break; 15302 } 15303 } else { 15304 generate_exception_err(ctx, EXCP_CpU, 1); 15305 } 15306 break; 15307 15308 #if defined(TARGET_MIPS64) 15309 /* MIPS64 opcodes */ 15310 case OPC_LLD: 15311 if (ctx->insn_flags & INSN_R5900) { 15312 check_insn_opc_user_only(ctx, INSN_R5900); 15313 } 15314 /* fall through */ 15315 case OPC_LDL: 15316 case OPC_LDR: 15317 case OPC_LWU: 15318 case OPC_LD: 15319 check_insn(ctx, ISA_MIPS3); 15320 check_mips_64(ctx); 15321 gen_ld(ctx, op, rt, rs, imm); 15322 break; 15323 case OPC_SDL: 15324 case OPC_SDR: 15325 case OPC_SD: 15326 check_insn(ctx, ISA_MIPS3); 15327 check_mips_64(ctx); 15328 gen_st(ctx, op, rt, rs, imm); 15329 break; 15330 case OPC_SCD: 15331 check_insn(ctx, ISA_MIPS3); 15332 if (ctx->insn_flags & INSN_R5900) { 15333 check_insn_opc_user_only(ctx, INSN_R5900); 15334 } 15335 check_mips_64(ctx); 15336 gen_st_cond(ctx, rt, rs, imm, MO_TEUQ, false); 15337 break; 15338 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */ 15339 if (ctx->insn_flags & ISA_MIPS_R6) { 15340 /* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */ 15341 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 15342 } else { 15343 /* OPC_DADDI */ 15344 check_insn(ctx, ISA_MIPS3); 15345 check_mips_64(ctx); 15346 gen_arith_imm(ctx, op, rt, rs, imm); 15347 } 15348 break; 15349 case OPC_DADDIU: 15350 check_insn(ctx, ISA_MIPS3); 15351 check_mips_64(ctx); 15352 gen_arith_imm(ctx, op, rt, rs, imm); 15353 break; 15354 #else 15355 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */ 15356 if (ctx->insn_flags & ISA_MIPS_R6) { 15357 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 15358 } else { 15359 MIPS_INVAL("major opcode"); 15360 gen_reserved_instruction(ctx); 15361 } 15362 break; 15363 #endif 15364 case OPC_DAUI: /* OPC_JALX */ 15365 if (ctx->insn_flags & ISA_MIPS_R6) { 15366 #if defined(TARGET_MIPS64) 15367 /* OPC_DAUI */ 15368 check_mips_64(ctx); 15369 if (rs == 0) { 15370 generate_exception(ctx, EXCP_RI); 15371 } else if (rt != 0) { 15372 TCGv t0 = tcg_temp_new(); 15373 gen_load_gpr(t0, rs); 15374 tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16); 15375 } 15376 #else 15377 gen_reserved_instruction(ctx); 15378 MIPS_INVAL("major opcode"); 15379 #endif 15380 } else { 15381 /* OPC_JALX */ 15382 check_insn(ctx, ASE_MIPS16 | ASE_MICROMIPS); 15383 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; 15384 gen_compute_branch(ctx, op, 4, rs, rt, offset, 4); 15385 } 15386 break; 15387 case OPC_MDMX: 15388 /* MDMX: Not implemented. */ 15389 break; 15390 case OPC_PCREL: 15391 check_insn(ctx, ISA_MIPS_R6); 15392 gen_pcrel(ctx, ctx->opcode, ctx->base.pc_next, rs); 15393 break; 15394 default: /* Invalid */ 15395 MIPS_INVAL("major opcode"); 15396 return false; 15397 } 15398 return true; 15399 } 15400 15401 static void decode_opc(CPUMIPSState *env, DisasContext *ctx) 15402 { 15403 /* make sure instructions are on a word boundary */ 15404 if (ctx->base.pc_next & 0x3) { 15405 env->CP0_BadVAddr = ctx->base.pc_next; 15406 generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL); 15407 return; 15408 } 15409 15410 /* Handle blikely not taken case */ 15411 if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) { 15412 TCGLabel *l1 = gen_new_label(); 15413 15414 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); 15415 tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK); 15416 gen_goto_tb(ctx, 1, ctx->base.pc_next + 4); 15417 gen_set_label(l1); 15418 } 15419 15420 /* Transition to the auto-generated decoder. */ 15421 15422 /* Vendor specific extensions */ 15423 if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opcode)) { 15424 return; 15425 } 15426 if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) { 15427 return; 15428 } 15429 #if defined(TARGET_MIPS64) 15430 if (cpu_supports_isa(env, INSN_OCTEON) && decode_ext_octeon(ctx, ctx->opcode)) { 15431 return; 15432 } 15433 #endif 15434 15435 /* ISA extensions */ 15436 if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) { 15437 return; 15438 } 15439 15440 /* ISA (from latest to oldest) */ 15441 if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->opcode)) { 15442 return; 15443 } 15444 15445 if (decode_opc_legacy(env, ctx)) { 15446 return; 15447 } 15448 15449 gen_reserved_instruction(ctx); 15450 } 15451 15452 static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 15453 { 15454 DisasContext *ctx = container_of(dcbase, DisasContext, base); 15455 CPUMIPSState *env = cs->env_ptr; 15456 15457 ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 15458 ctx->saved_pc = -1; 15459 ctx->insn_flags = env->insn_flags; 15460 ctx->CP0_Config0 = env->CP0_Config0; 15461 ctx->CP0_Config1 = env->CP0_Config1; 15462 ctx->CP0_Config2 = env->CP0_Config2; 15463 ctx->CP0_Config3 = env->CP0_Config3; 15464 ctx->CP0_Config5 = env->CP0_Config5; 15465 ctx->btarget = 0; 15466 ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; 15467 ctx->rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1; 15468 ctx->ie = (env->CP0_Config4 >> CP0C4_IE) & 3; 15469 ctx->bi = (env->CP0_Config3 >> CP0C3_BI) & 1; 15470 ctx->bp = (env->CP0_Config3 >> CP0C3_BP) & 1; 15471 ctx->PAMask = env->PAMask; 15472 ctx->mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1; 15473 ctx->eva = (env->CP0_Config5 >> CP0C5_EVA) & 1; 15474 ctx->sc = (env->CP0_Config3 >> CP0C3_SC) & 1; 15475 ctx->CP0_LLAddr_shift = env->CP0_LLAddr_shift; 15476 ctx->cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1; 15477 /* Restore delay slot state from the tb context. */ 15478 ctx->hflags = (uint32_t)ctx->base.tb->flags; /* FIXME: maybe use 64 bits? */ 15479 ctx->ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1; 15480 ctx->ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) || 15481 (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)); 15482 ctx->vp = (env->CP0_Config5 >> CP0C5_VP) & 1; 15483 ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1; 15484 ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; 15485 ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; 15486 ctx->mi = (env->CP0_Config5 >> CP0C5_MI) & 1; 15487 ctx->gi = (env->CP0_Config5 >> CP0C5_GI) & 3; 15488 restore_cpu_state(env, ctx); 15489 #ifdef CONFIG_USER_ONLY 15490 ctx->mem_idx = MIPS_HFLAG_UM; 15491 #else 15492 ctx->mem_idx = hflags_mmu_index(ctx->hflags); 15493 #endif 15494 ctx->default_tcg_memop_mask = (!(ctx->insn_flags & ISA_NANOMIPS32) && 15495 (ctx->insn_flags & (ISA_MIPS_R6 | 15496 INSN_LOONGSON3A))) ? MO_UNALN : MO_ALIGN; 15497 15498 /* 15499 * Execute a branch and its delay slot as a single instruction. 15500 * This is what GDB expects and is consistent with what the 15501 * hardware does (e.g. if a delay slot instruction faults, the 15502 * reported PC is the PC of the branch). 15503 */ 15504 if (ctx->base.singlestep_enabled && (ctx->hflags & MIPS_HFLAG_BMASK)) { 15505 ctx->base.max_insns = 2; 15506 } 15507 15508 LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, 15509 ctx->hflags); 15510 } 15511 15512 static void mips_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) 15513 { 15514 } 15515 15516 static void mips_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 15517 { 15518 DisasContext *ctx = container_of(dcbase, DisasContext, base); 15519 15520 tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMASK, 15521 ctx->btarget); 15522 } 15523 15524 static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 15525 { 15526 CPUMIPSState *env = cs->env_ptr; 15527 DisasContext *ctx = container_of(dcbase, DisasContext, base); 15528 int insn_bytes; 15529 int is_slot; 15530 15531 is_slot = ctx->hflags & MIPS_HFLAG_BMASK; 15532 if (ctx->insn_flags & ISA_NANOMIPS32) { 15533 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); 15534 insn_bytes = decode_isa_nanomips(env, ctx); 15535 } else if (!(ctx->hflags & MIPS_HFLAG_M16)) { 15536 ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next); 15537 insn_bytes = 4; 15538 decode_opc(env, ctx); 15539 } else if (ctx->insn_flags & ASE_MICROMIPS) { 15540 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); 15541 insn_bytes = decode_isa_micromips(env, ctx); 15542 } else if (ctx->insn_flags & ASE_MIPS16) { 15543 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); 15544 insn_bytes = decode_ase_mips16e(env, ctx); 15545 } else { 15546 gen_reserved_instruction(ctx); 15547 g_assert(ctx->base.is_jmp == DISAS_NORETURN); 15548 return; 15549 } 15550 15551 if (ctx->hflags & MIPS_HFLAG_BMASK) { 15552 if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 | 15553 MIPS_HFLAG_FBNSLOT))) { 15554 /* 15555 * Force to generate branch as there is neither delay nor 15556 * forbidden slot. 15557 */ 15558 is_slot = 1; 15559 } 15560 if ((ctx->hflags & MIPS_HFLAG_M16) && 15561 (ctx->hflags & MIPS_HFLAG_FBNSLOT)) { 15562 /* 15563 * Force to generate branch as microMIPS R6 doesn't restrict 15564 * branches in the forbidden slot. 15565 */ 15566 is_slot = 1; 15567 } 15568 } 15569 if (is_slot) { 15570 gen_branch(ctx, insn_bytes); 15571 } 15572 if (ctx->base.is_jmp == DISAS_SEMIHOST) { 15573 generate_exception_err(ctx, EXCP_SEMIHOST, insn_bytes); 15574 } 15575 ctx->base.pc_next += insn_bytes; 15576 15577 if (ctx->base.is_jmp != DISAS_NEXT) { 15578 return; 15579 } 15580 15581 /* 15582 * End the TB on (most) page crossings. 15583 * See mips_tr_init_disas_context about single-stepping a branch 15584 * together with its delay slot. 15585 */ 15586 if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE 15587 && !ctx->base.singlestep_enabled) { 15588 ctx->base.is_jmp = DISAS_TOO_MANY; 15589 } 15590 } 15591 15592 static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 15593 { 15594 DisasContext *ctx = container_of(dcbase, DisasContext, base); 15595 15596 switch (ctx->base.is_jmp) { 15597 case DISAS_STOP: 15598 gen_save_pc(ctx->base.pc_next); 15599 tcg_gen_lookup_and_goto_ptr(); 15600 break; 15601 case DISAS_NEXT: 15602 case DISAS_TOO_MANY: 15603 save_cpu_state(ctx, 0); 15604 gen_goto_tb(ctx, 0, ctx->base.pc_next); 15605 break; 15606 case DISAS_EXIT: 15607 tcg_gen_exit_tb(NULL, 0); 15608 break; 15609 case DISAS_NORETURN: 15610 break; 15611 default: 15612 g_assert_not_reached(); 15613 } 15614 } 15615 15616 static void mips_tr_disas_log(const DisasContextBase *dcbase, 15617 CPUState *cs, FILE *logfile) 15618 { 15619 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 15620 target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 15621 } 15622 15623 static const TranslatorOps mips_tr_ops = { 15624 .init_disas_context = mips_tr_init_disas_context, 15625 .tb_start = mips_tr_tb_start, 15626 .insn_start = mips_tr_insn_start, 15627 .translate_insn = mips_tr_translate_insn, 15628 .tb_stop = mips_tr_tb_stop, 15629 .disas_log = mips_tr_disas_log, 15630 }; 15631 15632 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 15633 target_ulong pc, void *host_pc) 15634 { 15635 DisasContext ctx; 15636 15637 translator_loop(cs, tb, max_insns, pc, host_pc, &mips_tr_ops, &ctx.base); 15638 } 15639 15640 void mips_tcg_init(void) 15641 { 15642 int i; 15643 15644 cpu_gpr[0] = NULL; 15645 for (i = 1; i < 32; i++) 15646 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 15647 offsetof(CPUMIPSState, 15648 active_tc.gpr[i]), 15649 regnames[i]); 15650 #if defined(TARGET_MIPS64) 15651 cpu_gpr_hi[0] = NULL; 15652 15653 for (unsigned i = 1; i < 32; i++) { 15654 g_autofree char *rname = g_strdup_printf("%s[hi]", regnames[i]); 15655 15656 cpu_gpr_hi[i] = tcg_global_mem_new_i64(cpu_env, 15657 offsetof(CPUMIPSState, 15658 active_tc.gpr_hi[i]), 15659 rname); 15660 } 15661 #endif /* !TARGET_MIPS64 */ 15662 for (i = 0; i < 32; i++) { 15663 int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); 15664 15665 fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]); 15666 } 15667 msa_translate_init(); 15668 cpu_PC = tcg_global_mem_new(cpu_env, 15669 offsetof(CPUMIPSState, active_tc.PC), "PC"); 15670 for (i = 0; i < MIPS_DSP_ACC; i++) { 15671 cpu_HI[i] = tcg_global_mem_new(cpu_env, 15672 offsetof(CPUMIPSState, active_tc.HI[i]), 15673 regnames_HI[i]); 15674 cpu_LO[i] = tcg_global_mem_new(cpu_env, 15675 offsetof(CPUMIPSState, active_tc.LO[i]), 15676 regnames_LO[i]); 15677 } 15678 cpu_dspctrl = tcg_global_mem_new(cpu_env, 15679 offsetof(CPUMIPSState, 15680 active_tc.DSPControl), 15681 "DSPControl"); 15682 bcond = tcg_global_mem_new(cpu_env, 15683 offsetof(CPUMIPSState, bcond), "bcond"); 15684 btarget = tcg_global_mem_new(cpu_env, 15685 offsetof(CPUMIPSState, btarget), "btarget"); 15686 hflags = tcg_global_mem_new_i32(cpu_env, 15687 offsetof(CPUMIPSState, hflags), "hflags"); 15688 15689 fpu_fcr0 = tcg_global_mem_new_i32(cpu_env, 15690 offsetof(CPUMIPSState, active_fpu.fcr0), 15691 "fcr0"); 15692 fpu_fcr31 = tcg_global_mem_new_i32(cpu_env, 15693 offsetof(CPUMIPSState, active_fpu.fcr31), 15694 "fcr31"); 15695 cpu_lladdr = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, lladdr), 15696 "lladdr"); 15697 cpu_llval = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval), 15698 "llval"); 15699 15700 if (TARGET_LONG_BITS == 32) { 15701 mxu_translate_init(); 15702 } 15703 } 15704 15705 void mips_restore_state_to_opc(CPUState *cs, 15706 const TranslationBlock *tb, 15707 const uint64_t *data) 15708 { 15709 MIPSCPU *cpu = MIPS_CPU(cs); 15710 CPUMIPSState *env = &cpu->env; 15711 15712 env->active_tc.PC = data[0]; 15713 env->hflags &= ~MIPS_HFLAG_BMASK; 15714 env->hflags |= data[1]; 15715 switch (env->hflags & MIPS_HFLAG_BMASK_BASE) { 15716 case MIPS_HFLAG_BR: 15717 break; 15718 case MIPS_HFLAG_BC: 15719 case MIPS_HFLAG_BL: 15720 case MIPS_HFLAG_B: 15721 env->btarget = data[2]; 15722 break; 15723 } 15724 } 15725