1 /* 2 * MIPS emulation for QEMU - main translation routines 3 * 4 * Copyright (c) 2004-2005 Jocelyn Mayer 5 * Copyright (c) 2006 Marius Groeger (FPU operations) 6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) 7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) 8 * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) 9 * Copyright (c) 2020 Philippe Mathieu-Daudé 10 * 11 * This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU Lesser General Public 13 * License as published by the Free Software Foundation; either 14 * version 2.1 of the License, or (at your option) any later version. 15 * 16 * This library is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * Lesser General Public License for more details. 20 * 21 * You should have received a copy of the GNU Lesser General Public 22 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "translate.h" 27 #include "internal.h" 28 #include "exec/helper-proto.h" 29 #include "exec/translation-block.h" 30 #include "semihosting/semihost.h" 31 #include "trace.h" 32 #include "fpu_helper.h" 33 34 #define HELPER_H "helper.h" 35 #include "exec/helper-info.c.inc" 36 #undef HELPER_H 37 38 39 /* 40 * Many sysemu-only helpers are not reachable for user-only. 41 * Define stub generators here, so that we need not either sprinkle 42 * ifdefs through the translator, nor provide the helper function. 43 */ 44 #define STUB_HELPER(NAME, ...) \ 45 static inline void gen_helper_##NAME(__VA_ARGS__) \ 46 { g_assert_not_reached(); } 47 48 #ifdef CONFIG_USER_ONLY 49 STUB_HELPER(cache, TCGv_env env, TCGv val, TCGv_i32 reg) 50 #endif 51 52 enum { 53 /* indirect opcode tables */ 54 OPC_SPECIAL = (0x00 << 26), 55 OPC_REGIMM = (0x01 << 26), 56 OPC_CP0 = (0x10 << 26), 57 OPC_CP2 = (0x12 << 26), 58 OPC_CP3 = (0x13 << 26), 59 OPC_SPECIAL2 = (0x1C << 26), 60 OPC_SPECIAL3 = (0x1F << 26), 61 /* arithmetic with immediate */ 62 OPC_ADDI = (0x08 << 26), 63 OPC_ADDIU = (0x09 << 26), 64 OPC_SLTI = (0x0A << 26), 65 OPC_SLTIU = (0x0B << 26), 66 /* logic with immediate */ 67 OPC_ANDI = (0x0C << 26), 68 OPC_ORI = (0x0D << 26), 69 OPC_XORI = (0x0E << 26), 70 OPC_LUI = (0x0F << 26), 71 /* arithmetic with immediate */ 72 OPC_DADDI = (0x18 << 26), 73 OPC_DADDIU = (0x19 << 26), 74 /* Jump and branches */ 75 OPC_J = (0x02 << 26), 76 OPC_JAL = (0x03 << 26), 77 OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */ 78 OPC_BEQL = (0x14 << 26), 79 OPC_BNE = (0x05 << 26), 80 OPC_BNEL = (0x15 << 26), 81 OPC_BLEZ = (0x06 << 26), 82 OPC_BLEZL = (0x16 << 26), 83 OPC_BGTZ = (0x07 << 26), 84 OPC_BGTZL = (0x17 << 26), 85 OPC_JALX = (0x1D << 26), 86 OPC_DAUI = (0x1D << 26), 87 /* Load and stores */ 88 OPC_LDL = (0x1A << 26), 89 OPC_LDR = (0x1B << 26), 90 OPC_LB = (0x20 << 26), 91 OPC_LH = (0x21 << 26), 92 OPC_LWL = (0x22 << 26), 93 OPC_LW = (0x23 << 26), 94 OPC_LWPC = OPC_LW | 0x5, 95 OPC_LBU = (0x24 << 26), 96 OPC_LHU = (0x25 << 26), 97 OPC_LWR = (0x26 << 26), 98 OPC_LWU = (0x27 << 26), 99 OPC_SB = (0x28 << 26), 100 OPC_SH = (0x29 << 26), 101 OPC_SWL = (0x2A << 26), 102 OPC_SW = (0x2B << 26), 103 OPC_SDL = (0x2C << 26), 104 OPC_SDR = (0x2D << 26), 105 OPC_SWR = (0x2E << 26), 106 OPC_LL = (0x30 << 26), 107 OPC_LLD = (0x34 << 26), 108 OPC_LD = (0x37 << 26), 109 OPC_LDPC = OPC_LD | 0x5, 110 OPC_SC = (0x38 << 26), 111 OPC_SCD = (0x3C << 26), 112 OPC_SD = (0x3F << 26), 113 /* Floating point load/store */ 114 OPC_LWC1 = (0x31 << 26), 115 OPC_LWC2 = (0x32 << 26), 116 OPC_LDC1 = (0x35 << 26), 117 OPC_LDC2 = (0x36 << 26), 118 OPC_SWC1 = (0x39 << 26), 119 OPC_SWC2 = (0x3A << 26), 120 OPC_SDC1 = (0x3D << 26), 121 OPC_SDC2 = (0x3E << 26), 122 /* Compact Branches */ 123 OPC_BLEZALC = (0x06 << 26), 124 OPC_BGEZALC = (0x06 << 26), 125 OPC_BGEUC = (0x06 << 26), 126 OPC_BGTZALC = (0x07 << 26), 127 OPC_BLTZALC = (0x07 << 26), 128 OPC_BLTUC = (0x07 << 26), 129 OPC_BOVC = (0x08 << 26), 130 OPC_BEQZALC = (0x08 << 26), 131 OPC_BEQC = (0x08 << 26), 132 OPC_BLEZC = (0x16 << 26), 133 OPC_BGEZC = (0x16 << 26), 134 OPC_BGEC = (0x16 << 26), 135 OPC_BGTZC = (0x17 << 26), 136 OPC_BLTZC = (0x17 << 26), 137 OPC_BLTC = (0x17 << 26), 138 OPC_BNVC = (0x18 << 26), 139 OPC_BNEZALC = (0x18 << 26), 140 OPC_BNEC = (0x18 << 26), 141 OPC_BC = (0x32 << 26), 142 OPC_BEQZC = (0x36 << 26), 143 OPC_JIC = (0x36 << 26), 144 OPC_BALC = (0x3A << 26), 145 OPC_BNEZC = (0x3E << 26), 146 OPC_JIALC = (0x3E << 26), 147 /* MDMX ASE specific */ 148 OPC_MDMX = (0x1E << 26), 149 /* Cache and prefetch */ 150 OPC_CACHE = (0x2F << 26), 151 OPC_PREF = (0x33 << 26), 152 /* PC-relative address computation / loads */ 153 OPC_PCREL = (0x3B << 26), 154 }; 155 156 /* PC-relative address computation / loads */ 157 #define MASK_OPC_PCREL_TOP2BITS(op) (MASK_OP_MAJOR(op) | (op & (3 << 19))) 158 #define MASK_OPC_PCREL_TOP5BITS(op) (MASK_OP_MAJOR(op) | (op & (0x1f << 16))) 159 enum { 160 /* Instructions determined by bits 19 and 20 */ 161 OPC_ADDIUPC = OPC_PCREL | (0 << 19), 162 R6_OPC_LWPC = OPC_PCREL | (1 << 19), 163 OPC_LWUPC = OPC_PCREL | (2 << 19), 164 165 /* Instructions determined by bits 16 ... 20 */ 166 OPC_AUIPC = OPC_PCREL | (0x1e << 16), 167 OPC_ALUIPC = OPC_PCREL | (0x1f << 16), 168 169 /* Other */ 170 R6_OPC_LDPC = OPC_PCREL | (6 << 18), 171 }; 172 173 /* MIPS special opcodes */ 174 #define MASK_SPECIAL(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) 175 176 enum { 177 /* Shifts */ 178 OPC_SLL = 0x00 | OPC_SPECIAL, 179 /* NOP is SLL r0, r0, 0 */ 180 /* SSNOP is SLL r0, r0, 1 */ 181 /* EHB is SLL r0, r0, 3 */ 182 OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */ 183 OPC_ROTR = OPC_SRL | (1 << 21), 184 OPC_SRA = 0x03 | OPC_SPECIAL, 185 OPC_SLLV = 0x04 | OPC_SPECIAL, 186 OPC_SRLV = 0x06 | OPC_SPECIAL, /* also ROTRV */ 187 OPC_ROTRV = OPC_SRLV | (1 << 6), 188 OPC_SRAV = 0x07 | OPC_SPECIAL, 189 OPC_DSLLV = 0x14 | OPC_SPECIAL, 190 OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */ 191 OPC_DROTRV = OPC_DSRLV | (1 << 6), 192 OPC_DSRAV = 0x17 | OPC_SPECIAL, 193 OPC_DSLL = 0x38 | OPC_SPECIAL, 194 OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */ 195 OPC_DROTR = OPC_DSRL | (1 << 21), 196 OPC_DSRA = 0x3B | OPC_SPECIAL, 197 OPC_DSLL32 = 0x3C | OPC_SPECIAL, 198 OPC_DSRL32 = 0x3E | OPC_SPECIAL, /* also DROTR32 */ 199 OPC_DROTR32 = OPC_DSRL32 | (1 << 21), 200 OPC_DSRA32 = 0x3F | OPC_SPECIAL, 201 /* Multiplication / division */ 202 OPC_MULT = 0x18 | OPC_SPECIAL, 203 OPC_MULTU = 0x19 | OPC_SPECIAL, 204 OPC_DIV = 0x1A | OPC_SPECIAL, 205 OPC_DIVU = 0x1B | OPC_SPECIAL, 206 OPC_DMULT = 0x1C | OPC_SPECIAL, 207 OPC_DMULTU = 0x1D | OPC_SPECIAL, 208 OPC_DDIV = 0x1E | OPC_SPECIAL, 209 OPC_DDIVU = 0x1F | OPC_SPECIAL, 210 211 /* 2 registers arithmetic / logic */ 212 OPC_ADD = 0x20 | OPC_SPECIAL, 213 OPC_ADDU = 0x21 | OPC_SPECIAL, 214 OPC_SUB = 0x22 | OPC_SPECIAL, 215 OPC_SUBU = 0x23 | OPC_SPECIAL, 216 OPC_AND = 0x24 | OPC_SPECIAL, 217 OPC_OR = 0x25 | OPC_SPECIAL, 218 OPC_XOR = 0x26 | OPC_SPECIAL, 219 OPC_NOR = 0x27 | OPC_SPECIAL, 220 OPC_SLT = 0x2A | OPC_SPECIAL, 221 OPC_SLTU = 0x2B | OPC_SPECIAL, 222 OPC_DADD = 0x2C | OPC_SPECIAL, 223 OPC_DADDU = 0x2D | OPC_SPECIAL, 224 OPC_DSUB = 0x2E | OPC_SPECIAL, 225 OPC_DSUBU = 0x2F | OPC_SPECIAL, 226 /* Jumps */ 227 OPC_JR = 0x08 | OPC_SPECIAL, /* Also JR.HB */ 228 OPC_JALR = 0x09 | OPC_SPECIAL, /* Also JALR.HB */ 229 /* Traps */ 230 OPC_TGE = 0x30 | OPC_SPECIAL, 231 OPC_TGEU = 0x31 | OPC_SPECIAL, 232 OPC_TLT = 0x32 | OPC_SPECIAL, 233 OPC_TLTU = 0x33 | OPC_SPECIAL, 234 OPC_TEQ = 0x34 | OPC_SPECIAL, 235 OPC_TNE = 0x36 | OPC_SPECIAL, 236 /* HI / LO registers load & stores */ 237 OPC_MFHI = 0x10 | OPC_SPECIAL, 238 OPC_MTHI = 0x11 | OPC_SPECIAL, 239 OPC_MFLO = 0x12 | OPC_SPECIAL, 240 OPC_MTLO = 0x13 | OPC_SPECIAL, 241 /* Conditional moves */ 242 OPC_MOVZ = 0x0A | OPC_SPECIAL, 243 OPC_MOVN = 0x0B | OPC_SPECIAL, 244 245 OPC_SELEQZ = 0x35 | OPC_SPECIAL, 246 OPC_SELNEZ = 0x37 | OPC_SPECIAL, 247 248 OPC_MOVCI = 0x01 | OPC_SPECIAL, 249 250 /* Special */ 251 OPC_PMON = 0x05 | OPC_SPECIAL, /* unofficial */ 252 OPC_SYSCALL = 0x0C | OPC_SPECIAL, 253 OPC_BREAK = 0x0D | OPC_SPECIAL, 254 OPC_SPIM = 0x0E | OPC_SPECIAL, /* unofficial */ 255 OPC_SYNC = 0x0F | OPC_SPECIAL, 256 257 OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL, 258 OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL, 259 OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL, 260 OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL, 261 }; 262 263 /* 264 * R6 Multiply and Divide instructions have the same opcode 265 * and function field as legacy OPC_MULT[U]/OPC_DIV[U] 266 */ 267 #define MASK_R6_MULDIV(op) (MASK_SPECIAL(op) | (op & (0x7ff))) 268 269 enum { 270 R6_OPC_MUL = OPC_MULT | (2 << 6), 271 R6_OPC_MUH = OPC_MULT | (3 << 6), 272 R6_OPC_MULU = OPC_MULTU | (2 << 6), 273 R6_OPC_MUHU = OPC_MULTU | (3 << 6), 274 R6_OPC_DIV = OPC_DIV | (2 << 6), 275 R6_OPC_MOD = OPC_DIV | (3 << 6), 276 R6_OPC_DIVU = OPC_DIVU | (2 << 6), 277 R6_OPC_MODU = OPC_DIVU | (3 << 6), 278 279 R6_OPC_DMUL = OPC_DMULT | (2 << 6), 280 R6_OPC_DMUH = OPC_DMULT | (3 << 6), 281 R6_OPC_DMULU = OPC_DMULTU | (2 << 6), 282 R6_OPC_DMUHU = OPC_DMULTU | (3 << 6), 283 R6_OPC_DDIV = OPC_DDIV | (2 << 6), 284 R6_OPC_DMOD = OPC_DDIV | (3 << 6), 285 R6_OPC_DDIVU = OPC_DDIVU | (2 << 6), 286 R6_OPC_DMODU = OPC_DDIVU | (3 << 6), 287 288 R6_OPC_CLZ = 0x10 | OPC_SPECIAL, 289 R6_OPC_CLO = 0x11 | OPC_SPECIAL, 290 R6_OPC_DCLZ = 0x12 | OPC_SPECIAL, 291 R6_OPC_DCLO = 0x13 | OPC_SPECIAL, 292 R6_OPC_SDBBP = 0x0e | OPC_SPECIAL, 293 }; 294 295 /* REGIMM (rt field) opcodes */ 296 #define MASK_REGIMM(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 16))) 297 298 enum { 299 OPC_BLTZ = (0x00 << 16) | OPC_REGIMM, 300 OPC_BLTZL = (0x02 << 16) | OPC_REGIMM, 301 OPC_BGEZ = (0x01 << 16) | OPC_REGIMM, 302 OPC_BGEZL = (0x03 << 16) | OPC_REGIMM, 303 OPC_BLTZAL = (0x10 << 16) | OPC_REGIMM, 304 OPC_BLTZALL = (0x12 << 16) | OPC_REGIMM, 305 OPC_BGEZAL = (0x11 << 16) | OPC_REGIMM, 306 OPC_BGEZALL = (0x13 << 16) | OPC_REGIMM, 307 OPC_TGEI = (0x08 << 16) | OPC_REGIMM, 308 OPC_TGEIU = (0x09 << 16) | OPC_REGIMM, 309 OPC_TLTI = (0x0A << 16) | OPC_REGIMM, 310 OPC_TLTIU = (0x0B << 16) | OPC_REGIMM, 311 OPC_TEQI = (0x0C << 16) | OPC_REGIMM, 312 OPC_TNEI = (0x0E << 16) | OPC_REGIMM, 313 OPC_SIGRIE = (0x17 << 16) | OPC_REGIMM, 314 OPC_SYNCI = (0x1F << 16) | OPC_REGIMM, 315 316 OPC_DAHI = (0x06 << 16) | OPC_REGIMM, 317 OPC_DATI = (0x1e << 16) | OPC_REGIMM, 318 }; 319 320 /* Special2 opcodes */ 321 #define MASK_SPECIAL2(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) 322 323 enum { 324 /* Multiply & xxx operations */ 325 OPC_MADD = 0x00 | OPC_SPECIAL2, 326 OPC_MADDU = 0x01 | OPC_SPECIAL2, 327 OPC_MUL = 0x02 | OPC_SPECIAL2, 328 OPC_MSUB = 0x04 | OPC_SPECIAL2, 329 OPC_MSUBU = 0x05 | OPC_SPECIAL2, 330 /* Loongson 2F */ 331 OPC_MULT_G_2F = 0x10 | OPC_SPECIAL2, 332 OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2, 333 OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2, 334 OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2, 335 OPC_DIV_G_2F = 0x14 | OPC_SPECIAL2, 336 OPC_DDIV_G_2F = 0x15 | OPC_SPECIAL2, 337 OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2, 338 OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2, 339 OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2, 340 OPC_DMOD_G_2F = 0x1d | OPC_SPECIAL2, 341 OPC_MODU_G_2F = 0x1e | OPC_SPECIAL2, 342 OPC_DMODU_G_2F = 0x1f | OPC_SPECIAL2, 343 /* Misc */ 344 OPC_CLZ = 0x20 | OPC_SPECIAL2, 345 OPC_CLO = 0x21 | OPC_SPECIAL2, 346 OPC_DCLZ = 0x24 | OPC_SPECIAL2, 347 OPC_DCLO = 0x25 | OPC_SPECIAL2, 348 /* Special */ 349 OPC_SDBBP = 0x3F | OPC_SPECIAL2, 350 }; 351 352 /* Special3 opcodes */ 353 #define MASK_SPECIAL3(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) 354 355 enum { 356 OPC_EXT = 0x00 | OPC_SPECIAL3, 357 OPC_DEXTM = 0x01 | OPC_SPECIAL3, 358 OPC_DEXTU = 0x02 | OPC_SPECIAL3, 359 OPC_DEXT = 0x03 | OPC_SPECIAL3, 360 OPC_INS = 0x04 | OPC_SPECIAL3, 361 OPC_DINSM = 0x05 | OPC_SPECIAL3, 362 OPC_DINSU = 0x06 | OPC_SPECIAL3, 363 OPC_DINS = 0x07 | OPC_SPECIAL3, 364 OPC_FORK = 0x08 | OPC_SPECIAL3, 365 OPC_YIELD = 0x09 | OPC_SPECIAL3, 366 OPC_BSHFL = 0x20 | OPC_SPECIAL3, 367 OPC_DBSHFL = 0x24 | OPC_SPECIAL3, 368 OPC_RDHWR = 0x3B | OPC_SPECIAL3, 369 OPC_GINV = 0x3D | OPC_SPECIAL3, 370 371 /* Loongson 2E */ 372 OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3, 373 OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3, 374 OPC_DIV_G_2E = 0x1A | OPC_SPECIAL3, 375 OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3, 376 OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3, 377 OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3, 378 OPC_DDIV_G_2E = 0x1E | OPC_SPECIAL3, 379 OPC_DDIVU_G_2E = 0x1F | OPC_SPECIAL3, 380 OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3, 381 OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3, 382 OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3, 383 OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3, 384 385 /* MIPS DSP Load */ 386 OPC_LX_DSP = 0x0A | OPC_SPECIAL3, 387 /* MIPS DSP Arithmetic */ 388 OPC_ADDU_QB_DSP = 0x10 | OPC_SPECIAL3, 389 OPC_ADDU_OB_DSP = 0x14 | OPC_SPECIAL3, 390 OPC_ABSQ_S_PH_DSP = 0x12 | OPC_SPECIAL3, 391 OPC_ABSQ_S_QH_DSP = 0x16 | OPC_SPECIAL3, 392 OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, 393 OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3, 394 OPC_CMPU_EQ_OB_DSP = 0x15 | OPC_SPECIAL3, 395 /* MIPS DSP GPR-Based Shift Sub-class */ 396 OPC_SHLL_QB_DSP = 0x13 | OPC_SPECIAL3, 397 OPC_SHLL_OB_DSP = 0x17 | OPC_SPECIAL3, 398 /* MIPS DSP Multiply Sub-class insns */ 399 OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, 400 OPC_DPA_W_PH_DSP = 0x30 | OPC_SPECIAL3, 401 OPC_DPAQ_W_QH_DSP = 0x34 | OPC_SPECIAL3, 402 /* DSP Bit/Manipulation Sub-class */ 403 OPC_INSV_DSP = 0x0C | OPC_SPECIAL3, 404 OPC_DINSV_DSP = 0x0D | OPC_SPECIAL3, 405 /* MIPS DSP Append Sub-class */ 406 OPC_APPEND_DSP = 0x31 | OPC_SPECIAL3, 407 OPC_DAPPEND_DSP = 0x35 | OPC_SPECIAL3, 408 /* MIPS DSP Accumulator and DSPControl Access Sub-class */ 409 OPC_EXTR_W_DSP = 0x38 | OPC_SPECIAL3, 410 OPC_DEXTR_W_DSP = 0x3C | OPC_SPECIAL3, 411 412 /* EVA */ 413 OPC_LWLE = 0x19 | OPC_SPECIAL3, 414 OPC_LWRE = 0x1A | OPC_SPECIAL3, 415 OPC_CACHEE = 0x1B | OPC_SPECIAL3, 416 OPC_SBE = 0x1C | OPC_SPECIAL3, 417 OPC_SHE = 0x1D | OPC_SPECIAL3, 418 OPC_SCE = 0x1E | OPC_SPECIAL3, 419 OPC_SWE = 0x1F | OPC_SPECIAL3, 420 OPC_SWLE = 0x21 | OPC_SPECIAL3, 421 OPC_SWRE = 0x22 | OPC_SPECIAL3, 422 OPC_PREFE = 0x23 | OPC_SPECIAL3, 423 OPC_LBUE = 0x28 | OPC_SPECIAL3, 424 OPC_LHUE = 0x29 | OPC_SPECIAL3, 425 OPC_LBE = 0x2C | OPC_SPECIAL3, 426 OPC_LHE = 0x2D | OPC_SPECIAL3, 427 OPC_LLE = 0x2E | OPC_SPECIAL3, 428 OPC_LWE = 0x2F | OPC_SPECIAL3, 429 430 /* R6 */ 431 R6_OPC_PREF = 0x35 | OPC_SPECIAL3, 432 R6_OPC_CACHE = 0x25 | OPC_SPECIAL3, 433 R6_OPC_LL = 0x36 | OPC_SPECIAL3, 434 R6_OPC_SC = 0x26 | OPC_SPECIAL3, 435 R6_OPC_LLD = 0x37 | OPC_SPECIAL3, 436 R6_OPC_SCD = 0x27 | OPC_SPECIAL3, 437 }; 438 439 /* Loongson EXT load/store quad word opcodes */ 440 #define MASK_LOONGSON_GSLSQ(op) (MASK_OP_MAJOR(op) | (op & 0x8020)) 441 enum { 442 OPC_GSLQ = 0x0020 | OPC_LWC2, 443 OPC_GSLQC1 = 0x8020 | OPC_LWC2, 444 OPC_GSSHFL = OPC_LWC2, 445 OPC_GSSQ = 0x0020 | OPC_SWC2, 446 OPC_GSSQC1 = 0x8020 | OPC_SWC2, 447 OPC_GSSHFS = OPC_SWC2, 448 }; 449 450 /* Loongson EXT shifted load/store opcodes */ 451 #define MASK_LOONGSON_GSSHFLS(op) (MASK_OP_MAJOR(op) | (op & 0xc03f)) 452 enum { 453 OPC_GSLWLC1 = 0x4 | OPC_GSSHFL, 454 OPC_GSLWRC1 = 0x5 | OPC_GSSHFL, 455 OPC_GSLDLC1 = 0x6 | OPC_GSSHFL, 456 OPC_GSLDRC1 = 0x7 | OPC_GSSHFL, 457 OPC_GSSWLC1 = 0x4 | OPC_GSSHFS, 458 OPC_GSSWRC1 = 0x5 | OPC_GSSHFS, 459 OPC_GSSDLC1 = 0x6 | OPC_GSSHFS, 460 OPC_GSSDRC1 = 0x7 | OPC_GSSHFS, 461 }; 462 463 /* Loongson EXT LDC2/SDC2 opcodes */ 464 #define MASK_LOONGSON_LSDC2(op) (MASK_OP_MAJOR(op) | (op & 0x7)) 465 466 enum { 467 OPC_GSLBX = 0x0 | OPC_LDC2, 468 OPC_GSLHX = 0x1 | OPC_LDC2, 469 OPC_GSLWX = 0x2 | OPC_LDC2, 470 OPC_GSLDX = 0x3 | OPC_LDC2, 471 OPC_GSLWXC1 = 0x6 | OPC_LDC2, 472 OPC_GSLDXC1 = 0x7 | OPC_LDC2, 473 OPC_GSSBX = 0x0 | OPC_SDC2, 474 OPC_GSSHX = 0x1 | OPC_SDC2, 475 OPC_GSSWX = 0x2 | OPC_SDC2, 476 OPC_GSSDX = 0x3 | OPC_SDC2, 477 OPC_GSSWXC1 = 0x6 | OPC_SDC2, 478 OPC_GSSDXC1 = 0x7 | OPC_SDC2, 479 }; 480 481 /* BSHFL opcodes */ 482 #define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 483 484 enum { 485 OPC_WSBH = (0x02 << 6) | OPC_BSHFL, 486 OPC_SEB = (0x10 << 6) | OPC_BSHFL, 487 OPC_SEH = (0x18 << 6) | OPC_BSHFL, 488 OPC_ALIGN = (0x08 << 6) | OPC_BSHFL, /* 010.bp (010.00 to 010.11) */ 489 OPC_ALIGN_1 = (0x09 << 6) | OPC_BSHFL, 490 OPC_ALIGN_2 = (0x0A << 6) | OPC_BSHFL, 491 OPC_ALIGN_3 = (0x0B << 6) | OPC_BSHFL, 492 OPC_BITSWAP = (0x00 << 6) | OPC_BSHFL /* 00000 */ 493 }; 494 495 /* DBSHFL opcodes */ 496 #define MASK_DBSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 497 498 enum { 499 OPC_DSBH = (0x02 << 6) | OPC_DBSHFL, 500 OPC_DSHD = (0x05 << 6) | OPC_DBSHFL, 501 OPC_DALIGN = (0x08 << 6) | OPC_DBSHFL, /* 01.bp (01.000 to 01.111) */ 502 OPC_DALIGN_1 = (0x09 << 6) | OPC_DBSHFL, 503 OPC_DALIGN_2 = (0x0A << 6) | OPC_DBSHFL, 504 OPC_DALIGN_3 = (0x0B << 6) | OPC_DBSHFL, 505 OPC_DALIGN_4 = (0x0C << 6) | OPC_DBSHFL, 506 OPC_DALIGN_5 = (0x0D << 6) | OPC_DBSHFL, 507 OPC_DALIGN_6 = (0x0E << 6) | OPC_DBSHFL, 508 OPC_DALIGN_7 = (0x0F << 6) | OPC_DBSHFL, 509 OPC_DBITSWAP = (0x00 << 6) | OPC_DBSHFL, /* 00000 */ 510 }; 511 512 /* MIPS DSP REGIMM opcodes */ 513 enum { 514 OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM, 515 OPC_BPOSGE64 = (0x1D << 16) | OPC_REGIMM, 516 }; 517 518 #define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 519 /* MIPS DSP Load */ 520 enum { 521 OPC_LBUX = (0x06 << 6) | OPC_LX_DSP, 522 OPC_LHX = (0x04 << 6) | OPC_LX_DSP, 523 OPC_LWX = (0x00 << 6) | OPC_LX_DSP, 524 OPC_LDX = (0x08 << 6) | OPC_LX_DSP, 525 }; 526 527 #define MASK_ADDU_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 528 enum { 529 /* MIPS DSP Arithmetic Sub-class */ 530 OPC_ADDQ_PH = (0x0A << 6) | OPC_ADDU_QB_DSP, 531 OPC_ADDQ_S_PH = (0x0E << 6) | OPC_ADDU_QB_DSP, 532 OPC_ADDQ_S_W = (0x16 << 6) | OPC_ADDU_QB_DSP, 533 OPC_ADDU_QB = (0x00 << 6) | OPC_ADDU_QB_DSP, 534 OPC_ADDU_S_QB = (0x04 << 6) | OPC_ADDU_QB_DSP, 535 OPC_ADDU_PH = (0x08 << 6) | OPC_ADDU_QB_DSP, 536 OPC_ADDU_S_PH = (0x0C << 6) | OPC_ADDU_QB_DSP, 537 OPC_SUBQ_PH = (0x0B << 6) | OPC_ADDU_QB_DSP, 538 OPC_SUBQ_S_PH = (0x0F << 6) | OPC_ADDU_QB_DSP, 539 OPC_SUBQ_S_W = (0x17 << 6) | OPC_ADDU_QB_DSP, 540 OPC_SUBU_QB = (0x01 << 6) | OPC_ADDU_QB_DSP, 541 OPC_SUBU_S_QB = (0x05 << 6) | OPC_ADDU_QB_DSP, 542 OPC_SUBU_PH = (0x09 << 6) | OPC_ADDU_QB_DSP, 543 OPC_SUBU_S_PH = (0x0D << 6) | OPC_ADDU_QB_DSP, 544 OPC_ADDSC = (0x10 << 6) | OPC_ADDU_QB_DSP, 545 OPC_ADDWC = (0x11 << 6) | OPC_ADDU_QB_DSP, 546 OPC_MODSUB = (0x12 << 6) | OPC_ADDU_QB_DSP, 547 OPC_RADDU_W_QB = (0x14 << 6) | OPC_ADDU_QB_DSP, 548 /* MIPS DSP Multiply Sub-class insns */ 549 OPC_MULEU_S_PH_QBL = (0x06 << 6) | OPC_ADDU_QB_DSP, 550 OPC_MULEU_S_PH_QBR = (0x07 << 6) | OPC_ADDU_QB_DSP, 551 OPC_MULQ_RS_PH = (0x1F << 6) | OPC_ADDU_QB_DSP, 552 OPC_MULEQ_S_W_PHL = (0x1C << 6) | OPC_ADDU_QB_DSP, 553 OPC_MULEQ_S_W_PHR = (0x1D << 6) | OPC_ADDU_QB_DSP, 554 OPC_MULQ_S_PH = (0x1E << 6) | OPC_ADDU_QB_DSP, 555 }; 556 557 #define MASK_ADDUH_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 558 enum { 559 /* MIPS DSP Arithmetic Sub-class */ 560 OPC_ADDUH_QB = (0x00 << 6) | OPC_ADDUH_QB_DSP, 561 OPC_ADDUH_R_QB = (0x02 << 6) | OPC_ADDUH_QB_DSP, 562 OPC_ADDQH_PH = (0x08 << 6) | OPC_ADDUH_QB_DSP, 563 OPC_ADDQH_R_PH = (0x0A << 6) | OPC_ADDUH_QB_DSP, 564 OPC_ADDQH_W = (0x10 << 6) | OPC_ADDUH_QB_DSP, 565 OPC_ADDQH_R_W = (0x12 << 6) | OPC_ADDUH_QB_DSP, 566 OPC_SUBUH_QB = (0x01 << 6) | OPC_ADDUH_QB_DSP, 567 OPC_SUBUH_R_QB = (0x03 << 6) | OPC_ADDUH_QB_DSP, 568 OPC_SUBQH_PH = (0x09 << 6) | OPC_ADDUH_QB_DSP, 569 OPC_SUBQH_R_PH = (0x0B << 6) | OPC_ADDUH_QB_DSP, 570 OPC_SUBQH_W = (0x11 << 6) | OPC_ADDUH_QB_DSP, 571 OPC_SUBQH_R_W = (0x13 << 6) | OPC_ADDUH_QB_DSP, 572 /* MIPS DSP Multiply Sub-class insns */ 573 OPC_MUL_PH = (0x0C << 6) | OPC_ADDUH_QB_DSP, 574 OPC_MUL_S_PH = (0x0E << 6) | OPC_ADDUH_QB_DSP, 575 OPC_MULQ_S_W = (0x16 << 6) | OPC_ADDUH_QB_DSP, 576 OPC_MULQ_RS_W = (0x17 << 6) | OPC_ADDUH_QB_DSP, 577 }; 578 579 #define MASK_ABSQ_S_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 580 enum { 581 /* MIPS DSP Arithmetic Sub-class */ 582 OPC_ABSQ_S_QB = (0x01 << 6) | OPC_ABSQ_S_PH_DSP, 583 OPC_ABSQ_S_PH = (0x09 << 6) | OPC_ABSQ_S_PH_DSP, 584 OPC_ABSQ_S_W = (0x11 << 6) | OPC_ABSQ_S_PH_DSP, 585 OPC_PRECEQ_W_PHL = (0x0C << 6) | OPC_ABSQ_S_PH_DSP, 586 OPC_PRECEQ_W_PHR = (0x0D << 6) | OPC_ABSQ_S_PH_DSP, 587 OPC_PRECEQU_PH_QBL = (0x04 << 6) | OPC_ABSQ_S_PH_DSP, 588 OPC_PRECEQU_PH_QBR = (0x05 << 6) | OPC_ABSQ_S_PH_DSP, 589 OPC_PRECEQU_PH_QBLA = (0x06 << 6) | OPC_ABSQ_S_PH_DSP, 590 OPC_PRECEQU_PH_QBRA = (0x07 << 6) | OPC_ABSQ_S_PH_DSP, 591 OPC_PRECEU_PH_QBL = (0x1C << 6) | OPC_ABSQ_S_PH_DSP, 592 OPC_PRECEU_PH_QBR = (0x1D << 6) | OPC_ABSQ_S_PH_DSP, 593 OPC_PRECEU_PH_QBLA = (0x1E << 6) | OPC_ABSQ_S_PH_DSP, 594 OPC_PRECEU_PH_QBRA = (0x1F << 6) | OPC_ABSQ_S_PH_DSP, 595 /* DSP Bit/Manipulation Sub-class */ 596 OPC_BITREV = (0x1B << 6) | OPC_ABSQ_S_PH_DSP, 597 OPC_REPL_QB = (0x02 << 6) | OPC_ABSQ_S_PH_DSP, 598 OPC_REPLV_QB = (0x03 << 6) | OPC_ABSQ_S_PH_DSP, 599 OPC_REPL_PH = (0x0A << 6) | OPC_ABSQ_S_PH_DSP, 600 OPC_REPLV_PH = (0x0B << 6) | OPC_ABSQ_S_PH_DSP, 601 }; 602 603 #define MASK_CMPU_EQ_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 604 enum { 605 /* MIPS DSP Arithmetic Sub-class */ 606 OPC_PRECR_QB_PH = (0x0D << 6) | OPC_CMPU_EQ_QB_DSP, 607 OPC_PRECRQ_QB_PH = (0x0C << 6) | OPC_CMPU_EQ_QB_DSP, 608 OPC_PRECR_SRA_PH_W = (0x1E << 6) | OPC_CMPU_EQ_QB_DSP, 609 OPC_PRECR_SRA_R_PH_W = (0x1F << 6) | OPC_CMPU_EQ_QB_DSP, 610 OPC_PRECRQ_PH_W = (0x14 << 6) | OPC_CMPU_EQ_QB_DSP, 611 OPC_PRECRQ_RS_PH_W = (0x15 << 6) | OPC_CMPU_EQ_QB_DSP, 612 OPC_PRECRQU_S_QB_PH = (0x0F << 6) | OPC_CMPU_EQ_QB_DSP, 613 /* DSP Compare-Pick Sub-class */ 614 OPC_CMPU_EQ_QB = (0x00 << 6) | OPC_CMPU_EQ_QB_DSP, 615 OPC_CMPU_LT_QB = (0x01 << 6) | OPC_CMPU_EQ_QB_DSP, 616 OPC_CMPU_LE_QB = (0x02 << 6) | OPC_CMPU_EQ_QB_DSP, 617 OPC_CMPGU_EQ_QB = (0x04 << 6) | OPC_CMPU_EQ_QB_DSP, 618 OPC_CMPGU_LT_QB = (0x05 << 6) | OPC_CMPU_EQ_QB_DSP, 619 OPC_CMPGU_LE_QB = (0x06 << 6) | OPC_CMPU_EQ_QB_DSP, 620 OPC_CMPGDU_EQ_QB = (0x18 << 6) | OPC_CMPU_EQ_QB_DSP, 621 OPC_CMPGDU_LT_QB = (0x19 << 6) | OPC_CMPU_EQ_QB_DSP, 622 OPC_CMPGDU_LE_QB = (0x1A << 6) | OPC_CMPU_EQ_QB_DSP, 623 OPC_CMP_EQ_PH = (0x08 << 6) | OPC_CMPU_EQ_QB_DSP, 624 OPC_CMP_LT_PH = (0x09 << 6) | OPC_CMPU_EQ_QB_DSP, 625 OPC_CMP_LE_PH = (0x0A << 6) | OPC_CMPU_EQ_QB_DSP, 626 OPC_PICK_QB = (0x03 << 6) | OPC_CMPU_EQ_QB_DSP, 627 OPC_PICK_PH = (0x0B << 6) | OPC_CMPU_EQ_QB_DSP, 628 OPC_PACKRL_PH = (0x0E << 6) | OPC_CMPU_EQ_QB_DSP, 629 }; 630 631 #define MASK_SHLL_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 632 enum { 633 /* MIPS DSP GPR-Based Shift Sub-class */ 634 OPC_SHLL_QB = (0x00 << 6) | OPC_SHLL_QB_DSP, 635 OPC_SHLLV_QB = (0x02 << 6) | OPC_SHLL_QB_DSP, 636 OPC_SHLL_PH = (0x08 << 6) | OPC_SHLL_QB_DSP, 637 OPC_SHLLV_PH = (0x0A << 6) | OPC_SHLL_QB_DSP, 638 OPC_SHLL_S_PH = (0x0C << 6) | OPC_SHLL_QB_DSP, 639 OPC_SHLLV_S_PH = (0x0E << 6) | OPC_SHLL_QB_DSP, 640 OPC_SHLL_S_W = (0x14 << 6) | OPC_SHLL_QB_DSP, 641 OPC_SHLLV_S_W = (0x16 << 6) | OPC_SHLL_QB_DSP, 642 OPC_SHRL_QB = (0x01 << 6) | OPC_SHLL_QB_DSP, 643 OPC_SHRLV_QB = (0x03 << 6) | OPC_SHLL_QB_DSP, 644 OPC_SHRL_PH = (0x19 << 6) | OPC_SHLL_QB_DSP, 645 OPC_SHRLV_PH = (0x1B << 6) | OPC_SHLL_QB_DSP, 646 OPC_SHRA_QB = (0x04 << 6) | OPC_SHLL_QB_DSP, 647 OPC_SHRA_R_QB = (0x05 << 6) | OPC_SHLL_QB_DSP, 648 OPC_SHRAV_QB = (0x06 << 6) | OPC_SHLL_QB_DSP, 649 OPC_SHRAV_R_QB = (0x07 << 6) | OPC_SHLL_QB_DSP, 650 OPC_SHRA_PH = (0x09 << 6) | OPC_SHLL_QB_DSP, 651 OPC_SHRAV_PH = (0x0B << 6) | OPC_SHLL_QB_DSP, 652 OPC_SHRA_R_PH = (0x0D << 6) | OPC_SHLL_QB_DSP, 653 OPC_SHRAV_R_PH = (0x0F << 6) | OPC_SHLL_QB_DSP, 654 OPC_SHRA_R_W = (0x15 << 6) | OPC_SHLL_QB_DSP, 655 OPC_SHRAV_R_W = (0x17 << 6) | OPC_SHLL_QB_DSP, 656 }; 657 658 #define MASK_DPA_W_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 659 enum { 660 /* MIPS DSP Multiply Sub-class insns */ 661 OPC_DPAU_H_QBL = (0x03 << 6) | OPC_DPA_W_PH_DSP, 662 OPC_DPAU_H_QBR = (0x07 << 6) | OPC_DPA_W_PH_DSP, 663 OPC_DPSU_H_QBL = (0x0B << 6) | OPC_DPA_W_PH_DSP, 664 OPC_DPSU_H_QBR = (0x0F << 6) | OPC_DPA_W_PH_DSP, 665 OPC_DPA_W_PH = (0x00 << 6) | OPC_DPA_W_PH_DSP, 666 OPC_DPAX_W_PH = (0x08 << 6) | OPC_DPA_W_PH_DSP, 667 OPC_DPAQ_S_W_PH = (0x04 << 6) | OPC_DPA_W_PH_DSP, 668 OPC_DPAQX_S_W_PH = (0x18 << 6) | OPC_DPA_W_PH_DSP, 669 OPC_DPAQX_SA_W_PH = (0x1A << 6) | OPC_DPA_W_PH_DSP, 670 OPC_DPS_W_PH = (0x01 << 6) | OPC_DPA_W_PH_DSP, 671 OPC_DPSX_W_PH = (0x09 << 6) | OPC_DPA_W_PH_DSP, 672 OPC_DPSQ_S_W_PH = (0x05 << 6) | OPC_DPA_W_PH_DSP, 673 OPC_DPSQX_S_W_PH = (0x19 << 6) | OPC_DPA_W_PH_DSP, 674 OPC_DPSQX_SA_W_PH = (0x1B << 6) | OPC_DPA_W_PH_DSP, 675 OPC_MULSAQ_S_W_PH = (0x06 << 6) | OPC_DPA_W_PH_DSP, 676 OPC_DPAQ_SA_L_W = (0x0C << 6) | OPC_DPA_W_PH_DSP, 677 OPC_DPSQ_SA_L_W = (0x0D << 6) | OPC_DPA_W_PH_DSP, 678 OPC_MAQ_S_W_PHL = (0x14 << 6) | OPC_DPA_W_PH_DSP, 679 OPC_MAQ_S_W_PHR = (0x16 << 6) | OPC_DPA_W_PH_DSP, 680 OPC_MAQ_SA_W_PHL = (0x10 << 6) | OPC_DPA_W_PH_DSP, 681 OPC_MAQ_SA_W_PHR = (0x12 << 6) | OPC_DPA_W_PH_DSP, 682 OPC_MULSA_W_PH = (0x02 << 6) | OPC_DPA_W_PH_DSP, 683 }; 684 685 #define MASK_INSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 686 enum { 687 /* DSP Bit/Manipulation Sub-class */ 688 OPC_INSV = (0x00 << 6) | OPC_INSV_DSP, 689 }; 690 691 #define MASK_APPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 692 enum { 693 /* MIPS DSP Append Sub-class */ 694 OPC_APPEND = (0x00 << 6) | OPC_APPEND_DSP, 695 OPC_PREPEND = (0x01 << 6) | OPC_APPEND_DSP, 696 OPC_BALIGN = (0x10 << 6) | OPC_APPEND_DSP, 697 }; 698 699 #define MASK_EXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 700 enum { 701 /* MIPS DSP Accumulator and DSPControl Access Sub-class */ 702 OPC_EXTR_W = (0x00 << 6) | OPC_EXTR_W_DSP, 703 OPC_EXTR_R_W = (0x04 << 6) | OPC_EXTR_W_DSP, 704 OPC_EXTR_RS_W = (0x06 << 6) | OPC_EXTR_W_DSP, 705 OPC_EXTR_S_H = (0x0E << 6) | OPC_EXTR_W_DSP, 706 OPC_EXTRV_S_H = (0x0F << 6) | OPC_EXTR_W_DSP, 707 OPC_EXTRV_W = (0x01 << 6) | OPC_EXTR_W_DSP, 708 OPC_EXTRV_R_W = (0x05 << 6) | OPC_EXTR_W_DSP, 709 OPC_EXTRV_RS_W = (0x07 << 6) | OPC_EXTR_W_DSP, 710 OPC_EXTP = (0x02 << 6) | OPC_EXTR_W_DSP, 711 OPC_EXTPV = (0x03 << 6) | OPC_EXTR_W_DSP, 712 OPC_EXTPDP = (0x0A << 6) | OPC_EXTR_W_DSP, 713 OPC_EXTPDPV = (0x0B << 6) | OPC_EXTR_W_DSP, 714 OPC_SHILO = (0x1A << 6) | OPC_EXTR_W_DSP, 715 OPC_SHILOV = (0x1B << 6) | OPC_EXTR_W_DSP, 716 OPC_MTHLIP = (0x1F << 6) | OPC_EXTR_W_DSP, 717 OPC_WRDSP = (0x13 << 6) | OPC_EXTR_W_DSP, 718 OPC_RDDSP = (0x12 << 6) | OPC_EXTR_W_DSP, 719 }; 720 721 #define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 722 enum { 723 /* MIPS DSP Arithmetic Sub-class */ 724 OPC_PRECEQ_L_PWL = (0x14 << 6) | OPC_ABSQ_S_QH_DSP, 725 OPC_PRECEQ_L_PWR = (0x15 << 6) | OPC_ABSQ_S_QH_DSP, 726 OPC_PRECEQ_PW_QHL = (0x0C << 6) | OPC_ABSQ_S_QH_DSP, 727 OPC_PRECEQ_PW_QHR = (0x0D << 6) | OPC_ABSQ_S_QH_DSP, 728 OPC_PRECEQ_PW_QHLA = (0x0E << 6) | OPC_ABSQ_S_QH_DSP, 729 OPC_PRECEQ_PW_QHRA = (0x0F << 6) | OPC_ABSQ_S_QH_DSP, 730 OPC_PRECEQU_QH_OBL = (0x04 << 6) | OPC_ABSQ_S_QH_DSP, 731 OPC_PRECEQU_QH_OBR = (0x05 << 6) | OPC_ABSQ_S_QH_DSP, 732 OPC_PRECEQU_QH_OBLA = (0x06 << 6) | OPC_ABSQ_S_QH_DSP, 733 OPC_PRECEQU_QH_OBRA = (0x07 << 6) | OPC_ABSQ_S_QH_DSP, 734 OPC_PRECEU_QH_OBL = (0x1C << 6) | OPC_ABSQ_S_QH_DSP, 735 OPC_PRECEU_QH_OBR = (0x1D << 6) | OPC_ABSQ_S_QH_DSP, 736 OPC_PRECEU_QH_OBLA = (0x1E << 6) | OPC_ABSQ_S_QH_DSP, 737 OPC_PRECEU_QH_OBRA = (0x1F << 6) | OPC_ABSQ_S_QH_DSP, 738 OPC_ABSQ_S_OB = (0x01 << 6) | OPC_ABSQ_S_QH_DSP, 739 OPC_ABSQ_S_PW = (0x11 << 6) | OPC_ABSQ_S_QH_DSP, 740 OPC_ABSQ_S_QH = (0x09 << 6) | OPC_ABSQ_S_QH_DSP, 741 /* DSP Bit/Manipulation Sub-class */ 742 OPC_REPL_OB = (0x02 << 6) | OPC_ABSQ_S_QH_DSP, 743 OPC_REPL_PW = (0x12 << 6) | OPC_ABSQ_S_QH_DSP, 744 OPC_REPL_QH = (0x0A << 6) | OPC_ABSQ_S_QH_DSP, 745 OPC_REPLV_OB = (0x03 << 6) | OPC_ABSQ_S_QH_DSP, 746 OPC_REPLV_PW = (0x13 << 6) | OPC_ABSQ_S_QH_DSP, 747 OPC_REPLV_QH = (0x0B << 6) | OPC_ABSQ_S_QH_DSP, 748 }; 749 750 #define MASK_ADDU_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 751 enum { 752 /* MIPS DSP Multiply Sub-class insns */ 753 OPC_MULEQ_S_PW_QHL = (0x1C << 6) | OPC_ADDU_OB_DSP, 754 OPC_MULEQ_S_PW_QHR = (0x1D << 6) | OPC_ADDU_OB_DSP, 755 OPC_MULEU_S_QH_OBL = (0x06 << 6) | OPC_ADDU_OB_DSP, 756 OPC_MULEU_S_QH_OBR = (0x07 << 6) | OPC_ADDU_OB_DSP, 757 OPC_MULQ_RS_QH = (0x1F << 6) | OPC_ADDU_OB_DSP, 758 /* MIPS DSP Arithmetic Sub-class */ 759 OPC_RADDU_L_OB = (0x14 << 6) | OPC_ADDU_OB_DSP, 760 OPC_SUBQ_PW = (0x13 << 6) | OPC_ADDU_OB_DSP, 761 OPC_SUBQ_S_PW = (0x17 << 6) | OPC_ADDU_OB_DSP, 762 OPC_SUBQ_QH = (0x0B << 6) | OPC_ADDU_OB_DSP, 763 OPC_SUBQ_S_QH = (0x0F << 6) | OPC_ADDU_OB_DSP, 764 OPC_SUBU_OB = (0x01 << 6) | OPC_ADDU_OB_DSP, 765 OPC_SUBU_S_OB = (0x05 << 6) | OPC_ADDU_OB_DSP, 766 OPC_SUBU_QH = (0x09 << 6) | OPC_ADDU_OB_DSP, 767 OPC_SUBU_S_QH = (0x0D << 6) | OPC_ADDU_OB_DSP, 768 OPC_SUBUH_OB = (0x19 << 6) | OPC_ADDU_OB_DSP, 769 OPC_SUBUH_R_OB = (0x1B << 6) | OPC_ADDU_OB_DSP, 770 OPC_ADDQ_PW = (0x12 << 6) | OPC_ADDU_OB_DSP, 771 OPC_ADDQ_S_PW = (0x16 << 6) | OPC_ADDU_OB_DSP, 772 OPC_ADDQ_QH = (0x0A << 6) | OPC_ADDU_OB_DSP, 773 OPC_ADDQ_S_QH = (0x0E << 6) | OPC_ADDU_OB_DSP, 774 OPC_ADDU_OB = (0x00 << 6) | OPC_ADDU_OB_DSP, 775 OPC_ADDU_S_OB = (0x04 << 6) | OPC_ADDU_OB_DSP, 776 OPC_ADDU_QH = (0x08 << 6) | OPC_ADDU_OB_DSP, 777 OPC_ADDU_S_QH = (0x0C << 6) | OPC_ADDU_OB_DSP, 778 OPC_ADDUH_OB = (0x18 << 6) | OPC_ADDU_OB_DSP, 779 OPC_ADDUH_R_OB = (0x1A << 6) | OPC_ADDU_OB_DSP, 780 }; 781 782 #define MASK_CMPU_EQ_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 783 enum { 784 /* DSP Compare-Pick Sub-class */ 785 OPC_CMP_EQ_PW = (0x10 << 6) | OPC_CMPU_EQ_OB_DSP, 786 OPC_CMP_LT_PW = (0x11 << 6) | OPC_CMPU_EQ_OB_DSP, 787 OPC_CMP_LE_PW = (0x12 << 6) | OPC_CMPU_EQ_OB_DSP, 788 OPC_CMP_EQ_QH = (0x08 << 6) | OPC_CMPU_EQ_OB_DSP, 789 OPC_CMP_LT_QH = (0x09 << 6) | OPC_CMPU_EQ_OB_DSP, 790 OPC_CMP_LE_QH = (0x0A << 6) | OPC_CMPU_EQ_OB_DSP, 791 OPC_CMPGDU_EQ_OB = (0x18 << 6) | OPC_CMPU_EQ_OB_DSP, 792 OPC_CMPGDU_LT_OB = (0x19 << 6) | OPC_CMPU_EQ_OB_DSP, 793 OPC_CMPGDU_LE_OB = (0x1A << 6) | OPC_CMPU_EQ_OB_DSP, 794 OPC_CMPGU_EQ_OB = (0x04 << 6) | OPC_CMPU_EQ_OB_DSP, 795 OPC_CMPGU_LT_OB = (0x05 << 6) | OPC_CMPU_EQ_OB_DSP, 796 OPC_CMPGU_LE_OB = (0x06 << 6) | OPC_CMPU_EQ_OB_DSP, 797 OPC_CMPU_EQ_OB = (0x00 << 6) | OPC_CMPU_EQ_OB_DSP, 798 OPC_CMPU_LT_OB = (0x01 << 6) | OPC_CMPU_EQ_OB_DSP, 799 OPC_CMPU_LE_OB = (0x02 << 6) | OPC_CMPU_EQ_OB_DSP, 800 OPC_PACKRL_PW = (0x0E << 6) | OPC_CMPU_EQ_OB_DSP, 801 OPC_PICK_OB = (0x03 << 6) | OPC_CMPU_EQ_OB_DSP, 802 OPC_PICK_PW = (0x13 << 6) | OPC_CMPU_EQ_OB_DSP, 803 OPC_PICK_QH = (0x0B << 6) | OPC_CMPU_EQ_OB_DSP, 804 /* MIPS DSP Arithmetic Sub-class */ 805 OPC_PRECR_OB_QH = (0x0D << 6) | OPC_CMPU_EQ_OB_DSP, 806 OPC_PRECR_SRA_QH_PW = (0x1E << 6) | OPC_CMPU_EQ_OB_DSP, 807 OPC_PRECR_SRA_R_QH_PW = (0x1F << 6) | OPC_CMPU_EQ_OB_DSP, 808 OPC_PRECRQ_OB_QH = (0x0C << 6) | OPC_CMPU_EQ_OB_DSP, 809 OPC_PRECRQ_PW_L = (0x1C << 6) | OPC_CMPU_EQ_OB_DSP, 810 OPC_PRECRQ_QH_PW = (0x14 << 6) | OPC_CMPU_EQ_OB_DSP, 811 OPC_PRECRQ_RS_QH_PW = (0x15 << 6) | OPC_CMPU_EQ_OB_DSP, 812 OPC_PRECRQU_S_OB_QH = (0x0F << 6) | OPC_CMPU_EQ_OB_DSP, 813 }; 814 815 #define MASK_DAPPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 816 enum { 817 /* DSP Append Sub-class */ 818 OPC_DAPPEND = (0x00 << 6) | OPC_DAPPEND_DSP, 819 OPC_PREPENDD = (0x03 << 6) | OPC_DAPPEND_DSP, 820 OPC_PREPENDW = (0x01 << 6) | OPC_DAPPEND_DSP, 821 OPC_DBALIGN = (0x10 << 6) | OPC_DAPPEND_DSP, 822 }; 823 824 #define MASK_DEXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 825 enum { 826 /* MIPS DSP Accumulator and DSPControl Access Sub-class */ 827 OPC_DMTHLIP = (0x1F << 6) | OPC_DEXTR_W_DSP, 828 OPC_DSHILO = (0x1A << 6) | OPC_DEXTR_W_DSP, 829 OPC_DEXTP = (0x02 << 6) | OPC_DEXTR_W_DSP, 830 OPC_DEXTPDP = (0x0A << 6) | OPC_DEXTR_W_DSP, 831 OPC_DEXTPDPV = (0x0B << 6) | OPC_DEXTR_W_DSP, 832 OPC_DEXTPV = (0x03 << 6) | OPC_DEXTR_W_DSP, 833 OPC_DEXTR_L = (0x10 << 6) | OPC_DEXTR_W_DSP, 834 OPC_DEXTR_R_L = (0x14 << 6) | OPC_DEXTR_W_DSP, 835 OPC_DEXTR_RS_L = (0x16 << 6) | OPC_DEXTR_W_DSP, 836 OPC_DEXTR_W = (0x00 << 6) | OPC_DEXTR_W_DSP, 837 OPC_DEXTR_R_W = (0x04 << 6) | OPC_DEXTR_W_DSP, 838 OPC_DEXTR_RS_W = (0x06 << 6) | OPC_DEXTR_W_DSP, 839 OPC_DEXTR_S_H = (0x0E << 6) | OPC_DEXTR_W_DSP, 840 OPC_DEXTRV_L = (0x11 << 6) | OPC_DEXTR_W_DSP, 841 OPC_DEXTRV_R_L = (0x15 << 6) | OPC_DEXTR_W_DSP, 842 OPC_DEXTRV_RS_L = (0x17 << 6) | OPC_DEXTR_W_DSP, 843 OPC_DEXTRV_S_H = (0x0F << 6) | OPC_DEXTR_W_DSP, 844 OPC_DEXTRV_W = (0x01 << 6) | OPC_DEXTR_W_DSP, 845 OPC_DEXTRV_R_W = (0x05 << 6) | OPC_DEXTR_W_DSP, 846 OPC_DEXTRV_RS_W = (0x07 << 6) | OPC_DEXTR_W_DSP, 847 OPC_DSHILOV = (0x1B << 6) | OPC_DEXTR_W_DSP, 848 }; 849 850 #define MASK_DINSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 851 enum { 852 /* DSP Bit/Manipulation Sub-class */ 853 OPC_DINSV = (0x00 << 6) | OPC_DINSV_DSP, 854 }; 855 856 #define MASK_DPAQ_W_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 857 enum { 858 /* MIPS DSP Multiply Sub-class insns */ 859 OPC_DMADD = (0x19 << 6) | OPC_DPAQ_W_QH_DSP, 860 OPC_DMADDU = (0x1D << 6) | OPC_DPAQ_W_QH_DSP, 861 OPC_DMSUB = (0x1B << 6) | OPC_DPAQ_W_QH_DSP, 862 OPC_DMSUBU = (0x1F << 6) | OPC_DPAQ_W_QH_DSP, 863 OPC_DPA_W_QH = (0x00 << 6) | OPC_DPAQ_W_QH_DSP, 864 OPC_DPAQ_S_W_QH = (0x04 << 6) | OPC_DPAQ_W_QH_DSP, 865 OPC_DPAQ_SA_L_PW = (0x0C << 6) | OPC_DPAQ_W_QH_DSP, 866 OPC_DPAU_H_OBL = (0x03 << 6) | OPC_DPAQ_W_QH_DSP, 867 OPC_DPAU_H_OBR = (0x07 << 6) | OPC_DPAQ_W_QH_DSP, 868 OPC_DPS_W_QH = (0x01 << 6) | OPC_DPAQ_W_QH_DSP, 869 OPC_DPSQ_S_W_QH = (0x05 << 6) | OPC_DPAQ_W_QH_DSP, 870 OPC_DPSQ_SA_L_PW = (0x0D << 6) | OPC_DPAQ_W_QH_DSP, 871 OPC_DPSU_H_OBL = (0x0B << 6) | OPC_DPAQ_W_QH_DSP, 872 OPC_DPSU_H_OBR = (0x0F << 6) | OPC_DPAQ_W_QH_DSP, 873 OPC_MAQ_S_L_PWL = (0x1C << 6) | OPC_DPAQ_W_QH_DSP, 874 OPC_MAQ_S_L_PWR = (0x1E << 6) | OPC_DPAQ_W_QH_DSP, 875 OPC_MAQ_S_W_QHLL = (0x14 << 6) | OPC_DPAQ_W_QH_DSP, 876 OPC_MAQ_SA_W_QHLL = (0x10 << 6) | OPC_DPAQ_W_QH_DSP, 877 OPC_MAQ_S_W_QHLR = (0x15 << 6) | OPC_DPAQ_W_QH_DSP, 878 OPC_MAQ_SA_W_QHLR = (0x11 << 6) | OPC_DPAQ_W_QH_DSP, 879 OPC_MAQ_S_W_QHRL = (0x16 << 6) | OPC_DPAQ_W_QH_DSP, 880 OPC_MAQ_SA_W_QHRL = (0x12 << 6) | OPC_DPAQ_W_QH_DSP, 881 OPC_MAQ_S_W_QHRR = (0x17 << 6) | OPC_DPAQ_W_QH_DSP, 882 OPC_MAQ_SA_W_QHRR = (0x13 << 6) | OPC_DPAQ_W_QH_DSP, 883 OPC_MULSAQ_S_L_PW = (0x0E << 6) | OPC_DPAQ_W_QH_DSP, 884 OPC_MULSAQ_S_W_QH = (0x06 << 6) | OPC_DPAQ_W_QH_DSP, 885 }; 886 887 #define MASK_SHLL_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 888 enum { 889 /* MIPS DSP GPR-Based Shift Sub-class */ 890 OPC_SHLL_PW = (0x10 << 6) | OPC_SHLL_OB_DSP, 891 OPC_SHLL_S_PW = (0x14 << 6) | OPC_SHLL_OB_DSP, 892 OPC_SHLLV_OB = (0x02 << 6) | OPC_SHLL_OB_DSP, 893 OPC_SHLLV_PW = (0x12 << 6) | OPC_SHLL_OB_DSP, 894 OPC_SHLLV_S_PW = (0x16 << 6) | OPC_SHLL_OB_DSP, 895 OPC_SHLLV_QH = (0x0A << 6) | OPC_SHLL_OB_DSP, 896 OPC_SHLLV_S_QH = (0x0E << 6) | OPC_SHLL_OB_DSP, 897 OPC_SHRA_PW = (0x11 << 6) | OPC_SHLL_OB_DSP, 898 OPC_SHRA_R_PW = (0x15 << 6) | OPC_SHLL_OB_DSP, 899 OPC_SHRAV_OB = (0x06 << 6) | OPC_SHLL_OB_DSP, 900 OPC_SHRAV_R_OB = (0x07 << 6) | OPC_SHLL_OB_DSP, 901 OPC_SHRAV_PW = (0x13 << 6) | OPC_SHLL_OB_DSP, 902 OPC_SHRAV_R_PW = (0x17 << 6) | OPC_SHLL_OB_DSP, 903 OPC_SHRAV_QH = (0x0B << 6) | OPC_SHLL_OB_DSP, 904 OPC_SHRAV_R_QH = (0x0F << 6) | OPC_SHLL_OB_DSP, 905 OPC_SHRLV_OB = (0x03 << 6) | OPC_SHLL_OB_DSP, 906 OPC_SHRLV_QH = (0x1B << 6) | OPC_SHLL_OB_DSP, 907 OPC_SHLL_OB = (0x00 << 6) | OPC_SHLL_OB_DSP, 908 OPC_SHLL_QH = (0x08 << 6) | OPC_SHLL_OB_DSP, 909 OPC_SHLL_S_QH = (0x0C << 6) | OPC_SHLL_OB_DSP, 910 OPC_SHRA_OB = (0x04 << 6) | OPC_SHLL_OB_DSP, 911 OPC_SHRA_R_OB = (0x05 << 6) | OPC_SHLL_OB_DSP, 912 OPC_SHRA_QH = (0x09 << 6) | OPC_SHLL_OB_DSP, 913 OPC_SHRA_R_QH = (0x0D << 6) | OPC_SHLL_OB_DSP, 914 OPC_SHRL_OB = (0x01 << 6) | OPC_SHLL_OB_DSP, 915 OPC_SHRL_QH = (0x19 << 6) | OPC_SHLL_OB_DSP, 916 }; 917 918 /* Coprocessor 0 (rs field) */ 919 #define MASK_CP0(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21))) 920 921 enum { 922 OPC_MFC0 = (0x00 << 21) | OPC_CP0, 923 OPC_DMFC0 = (0x01 << 21) | OPC_CP0, 924 OPC_MFHC0 = (0x02 << 21) | OPC_CP0, 925 OPC_MTC0 = (0x04 << 21) | OPC_CP0, 926 OPC_DMTC0 = (0x05 << 21) | OPC_CP0, 927 OPC_MTHC0 = (0x06 << 21) | OPC_CP0, 928 OPC_MFTR = (0x08 << 21) | OPC_CP0, 929 OPC_RDPGPR = (0x0A << 21) | OPC_CP0, 930 OPC_MFMC0 = (0x0B << 21) | OPC_CP0, 931 OPC_MTTR = (0x0C << 21) | OPC_CP0, 932 OPC_WRPGPR = (0x0E << 21) | OPC_CP0, 933 OPC_C0 = (0x10 << 21) | OPC_CP0, 934 OPC_C0_1 = (0x11 << 21) | OPC_CP0, 935 OPC_C0_2 = (0x12 << 21) | OPC_CP0, 936 OPC_C0_3 = (0x13 << 21) | OPC_CP0, 937 OPC_C0_4 = (0x14 << 21) | OPC_CP0, 938 OPC_C0_5 = (0x15 << 21) | OPC_CP0, 939 OPC_C0_6 = (0x16 << 21) | OPC_CP0, 940 OPC_C0_7 = (0x17 << 21) | OPC_CP0, 941 OPC_C0_8 = (0x18 << 21) | OPC_CP0, 942 OPC_C0_9 = (0x19 << 21) | OPC_CP0, 943 OPC_C0_A = (0x1A << 21) | OPC_CP0, 944 OPC_C0_B = (0x1B << 21) | OPC_CP0, 945 OPC_C0_C = (0x1C << 21) | OPC_CP0, 946 OPC_C0_D = (0x1D << 21) | OPC_CP0, 947 OPC_C0_E = (0x1E << 21) | OPC_CP0, 948 OPC_C0_F = (0x1F << 21) | OPC_CP0, 949 }; 950 951 /* MFMC0 opcodes */ 952 #define MASK_MFMC0(op) (MASK_CP0(op) | (op & 0xFFFF)) 953 954 enum { 955 OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0, 956 OPC_EMT = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0, 957 OPC_DVPE = 0x01 | (0 << 5) | OPC_MFMC0, 958 OPC_EVPE = 0x01 | (1 << 5) | OPC_MFMC0, 959 OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0, 960 OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0, 961 OPC_DVP = 0x04 | (0 << 3) | (1 << 5) | (0 << 11) | OPC_MFMC0, 962 OPC_EVP = 0x04 | (0 << 3) | (0 << 5) | (0 << 11) | OPC_MFMC0, 963 }; 964 965 /* Coprocessor 0 (with rs == C0) */ 966 #define MASK_C0(op) (MASK_CP0(op) | (op & 0x3F)) 967 968 enum { 969 OPC_TLBR = 0x01 | OPC_C0, 970 OPC_TLBWI = 0x02 | OPC_C0, 971 OPC_TLBINV = 0x03 | OPC_C0, 972 OPC_TLBINVF = 0x04 | OPC_C0, 973 OPC_TLBWR = 0x06 | OPC_C0, 974 OPC_TLBP = 0x08 | OPC_C0, 975 OPC_RFE = 0x10 | OPC_C0, 976 OPC_ERET = 0x18 | OPC_C0, 977 OPC_DERET = 0x1F | OPC_C0, 978 OPC_WAIT = 0x20 | OPC_C0, 979 }; 980 981 #define MASK_CP2(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21))) 982 983 enum { 984 OPC_MFC2 = (0x00 << 21) | OPC_CP2, 985 OPC_DMFC2 = (0x01 << 21) | OPC_CP2, 986 OPC_CFC2 = (0x02 << 21) | OPC_CP2, 987 OPC_MFHC2 = (0x03 << 21) | OPC_CP2, 988 OPC_MTC2 = (0x04 << 21) | OPC_CP2, 989 OPC_DMTC2 = (0x05 << 21) | OPC_CP2, 990 OPC_CTC2 = (0x06 << 21) | OPC_CP2, 991 OPC_MTHC2 = (0x07 << 21) | OPC_CP2, 992 OPC_BC2 = (0x08 << 21) | OPC_CP2, 993 OPC_BC2EQZ = (0x09 << 21) | OPC_CP2, 994 OPC_BC2NEZ = (0x0D << 21) | OPC_CP2, 995 }; 996 997 #define MASK_LMMI(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F)) 998 999 enum { 1000 OPC_PADDSH = (24 << 21) | (0x00) | OPC_CP2, 1001 OPC_PADDUSH = (25 << 21) | (0x00) | OPC_CP2, 1002 OPC_PADDH = (26 << 21) | (0x00) | OPC_CP2, 1003 OPC_PADDW = (27 << 21) | (0x00) | OPC_CP2, 1004 OPC_PADDSB = (28 << 21) | (0x00) | OPC_CP2, 1005 OPC_PADDUSB = (29 << 21) | (0x00) | OPC_CP2, 1006 OPC_PADDB = (30 << 21) | (0x00) | OPC_CP2, 1007 OPC_PADDD = (31 << 21) | (0x00) | OPC_CP2, 1008 1009 OPC_PSUBSH = (24 << 21) | (0x01) | OPC_CP2, 1010 OPC_PSUBUSH = (25 << 21) | (0x01) | OPC_CP2, 1011 OPC_PSUBH = (26 << 21) | (0x01) | OPC_CP2, 1012 OPC_PSUBW = (27 << 21) | (0x01) | OPC_CP2, 1013 OPC_PSUBSB = (28 << 21) | (0x01) | OPC_CP2, 1014 OPC_PSUBUSB = (29 << 21) | (0x01) | OPC_CP2, 1015 OPC_PSUBB = (30 << 21) | (0x01) | OPC_CP2, 1016 OPC_PSUBD = (31 << 21) | (0x01) | OPC_CP2, 1017 1018 OPC_PSHUFH = (24 << 21) | (0x02) | OPC_CP2, 1019 OPC_PACKSSWH = (25 << 21) | (0x02) | OPC_CP2, 1020 OPC_PACKSSHB = (26 << 21) | (0x02) | OPC_CP2, 1021 OPC_PACKUSHB = (27 << 21) | (0x02) | OPC_CP2, 1022 OPC_XOR_CP2 = (28 << 21) | (0x02) | OPC_CP2, 1023 OPC_NOR_CP2 = (29 << 21) | (0x02) | OPC_CP2, 1024 OPC_AND_CP2 = (30 << 21) | (0x02) | OPC_CP2, 1025 OPC_PANDN = (31 << 21) | (0x02) | OPC_CP2, 1026 1027 OPC_PUNPCKLHW = (24 << 21) | (0x03) | OPC_CP2, 1028 OPC_PUNPCKHHW = (25 << 21) | (0x03) | OPC_CP2, 1029 OPC_PUNPCKLBH = (26 << 21) | (0x03) | OPC_CP2, 1030 OPC_PUNPCKHBH = (27 << 21) | (0x03) | OPC_CP2, 1031 OPC_PINSRH_0 = (28 << 21) | (0x03) | OPC_CP2, 1032 OPC_PINSRH_1 = (29 << 21) | (0x03) | OPC_CP2, 1033 OPC_PINSRH_2 = (30 << 21) | (0x03) | OPC_CP2, 1034 OPC_PINSRH_3 = (31 << 21) | (0x03) | OPC_CP2, 1035 1036 OPC_PAVGH = (24 << 21) | (0x08) | OPC_CP2, 1037 OPC_PAVGB = (25 << 21) | (0x08) | OPC_CP2, 1038 OPC_PMAXSH = (26 << 21) | (0x08) | OPC_CP2, 1039 OPC_PMINSH = (27 << 21) | (0x08) | OPC_CP2, 1040 OPC_PMAXUB = (28 << 21) | (0x08) | OPC_CP2, 1041 OPC_PMINUB = (29 << 21) | (0x08) | OPC_CP2, 1042 1043 OPC_PCMPEQW = (24 << 21) | (0x09) | OPC_CP2, 1044 OPC_PCMPGTW = (25 << 21) | (0x09) | OPC_CP2, 1045 OPC_PCMPEQH = (26 << 21) | (0x09) | OPC_CP2, 1046 OPC_PCMPGTH = (27 << 21) | (0x09) | OPC_CP2, 1047 OPC_PCMPEQB = (28 << 21) | (0x09) | OPC_CP2, 1048 OPC_PCMPGTB = (29 << 21) | (0x09) | OPC_CP2, 1049 1050 OPC_PSLLW = (24 << 21) | (0x0A) | OPC_CP2, 1051 OPC_PSLLH = (25 << 21) | (0x0A) | OPC_CP2, 1052 OPC_PMULLH = (26 << 21) | (0x0A) | OPC_CP2, 1053 OPC_PMULHH = (27 << 21) | (0x0A) | OPC_CP2, 1054 OPC_PMULUW = (28 << 21) | (0x0A) | OPC_CP2, 1055 OPC_PMULHUH = (29 << 21) | (0x0A) | OPC_CP2, 1056 1057 OPC_PSRLW = (24 << 21) | (0x0B) | OPC_CP2, 1058 OPC_PSRLH = (25 << 21) | (0x0B) | OPC_CP2, 1059 OPC_PSRAW = (26 << 21) | (0x0B) | OPC_CP2, 1060 OPC_PSRAH = (27 << 21) | (0x0B) | OPC_CP2, 1061 OPC_PUNPCKLWD = (28 << 21) | (0x0B) | OPC_CP2, 1062 OPC_PUNPCKHWD = (29 << 21) | (0x0B) | OPC_CP2, 1063 1064 OPC_ADDU_CP2 = (24 << 21) | (0x0C) | OPC_CP2, 1065 OPC_OR_CP2 = (25 << 21) | (0x0C) | OPC_CP2, 1066 OPC_ADD_CP2 = (26 << 21) | (0x0C) | OPC_CP2, 1067 OPC_DADD_CP2 = (27 << 21) | (0x0C) | OPC_CP2, 1068 OPC_SEQU_CP2 = (28 << 21) | (0x0C) | OPC_CP2, 1069 OPC_SEQ_CP2 = (29 << 21) | (0x0C) | OPC_CP2, 1070 1071 OPC_SUBU_CP2 = (24 << 21) | (0x0D) | OPC_CP2, 1072 OPC_PASUBUB = (25 << 21) | (0x0D) | OPC_CP2, 1073 OPC_SUB_CP2 = (26 << 21) | (0x0D) | OPC_CP2, 1074 OPC_DSUB_CP2 = (27 << 21) | (0x0D) | OPC_CP2, 1075 OPC_SLTU_CP2 = (28 << 21) | (0x0D) | OPC_CP2, 1076 OPC_SLT_CP2 = (29 << 21) | (0x0D) | OPC_CP2, 1077 1078 OPC_SLL_CP2 = (24 << 21) | (0x0E) | OPC_CP2, 1079 OPC_DSLL_CP2 = (25 << 21) | (0x0E) | OPC_CP2, 1080 OPC_PEXTRH = (26 << 21) | (0x0E) | OPC_CP2, 1081 OPC_PMADDHW = (27 << 21) | (0x0E) | OPC_CP2, 1082 OPC_SLEU_CP2 = (28 << 21) | (0x0E) | OPC_CP2, 1083 OPC_SLE_CP2 = (29 << 21) | (0x0E) | OPC_CP2, 1084 1085 OPC_SRL_CP2 = (24 << 21) | (0x0F) | OPC_CP2, 1086 OPC_DSRL_CP2 = (25 << 21) | (0x0F) | OPC_CP2, 1087 OPC_SRA_CP2 = (26 << 21) | (0x0F) | OPC_CP2, 1088 OPC_DSRA_CP2 = (27 << 21) | (0x0F) | OPC_CP2, 1089 OPC_BIADD = (28 << 21) | (0x0F) | OPC_CP2, 1090 OPC_PMOVMSKB = (29 << 21) | (0x0F) | OPC_CP2, 1091 }; 1092 1093 1094 #define MASK_CP3(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) 1095 1096 enum { 1097 OPC_LWXC1 = 0x00 | OPC_CP3, 1098 OPC_LDXC1 = 0x01 | OPC_CP3, 1099 OPC_LUXC1 = 0x05 | OPC_CP3, 1100 OPC_SWXC1 = 0x08 | OPC_CP3, 1101 OPC_SDXC1 = 0x09 | OPC_CP3, 1102 OPC_SUXC1 = 0x0D | OPC_CP3, 1103 OPC_PREFX = 0x0F | OPC_CP3, 1104 OPC_ALNV_PS = 0x1E | OPC_CP3, 1105 OPC_MADD_S = 0x20 | OPC_CP3, 1106 OPC_MADD_D = 0x21 | OPC_CP3, 1107 OPC_MADD_PS = 0x26 | OPC_CP3, 1108 OPC_MSUB_S = 0x28 | OPC_CP3, 1109 OPC_MSUB_D = 0x29 | OPC_CP3, 1110 OPC_MSUB_PS = 0x2E | OPC_CP3, 1111 OPC_NMADD_S = 0x30 | OPC_CP3, 1112 OPC_NMADD_D = 0x31 | OPC_CP3, 1113 OPC_NMADD_PS = 0x36 | OPC_CP3, 1114 OPC_NMSUB_S = 0x38 | OPC_CP3, 1115 OPC_NMSUB_D = 0x39 | OPC_CP3, 1116 OPC_NMSUB_PS = 0x3E | OPC_CP3, 1117 }; 1118 1119 /* 1120 * MMI (MultiMedia Instruction) encodings 1121 * ====================================== 1122 * 1123 * MMI instructions encoding table keys: 1124 * 1125 * * This code is reserved for future use. An attempt to execute it 1126 * causes a Reserved Instruction exception. 1127 * % This code indicates an instruction class. The instruction word 1128 * must be further decoded by examining additional tables that show 1129 * the values for other instruction fields. 1130 * # This code is reserved for the unsupported instructions DMULT, 1131 * DMULTU, DDIV, DDIVU, LL, LLD, SC, SCD, LWC2 and SWC2. An attempt 1132 * to execute it causes a Reserved Instruction exception. 1133 * 1134 * MMI instructions encoded by opcode field (MMI, LQ, SQ): 1135 * 1136 * 31 26 0 1137 * +--------+----------------------------------------+ 1138 * | opcode | | 1139 * +--------+----------------------------------------+ 1140 * 1141 * opcode bits 28..26 1142 * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 1143 * 31..29 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 1144 * -------+-------+-------+-------+-------+-------+-------+-------+------- 1145 * 0 000 |SPECIAL| REGIMM| J | JAL | BEQ | BNE | BLEZ | BGTZ 1146 * 1 001 | ADDI | ADDIU | SLTI | SLTIU | ANDI | ORI | XORI | LUI 1147 * 2 010 | COP0 | COP1 | * | * | BEQL | BNEL | BLEZL | BGTZL 1148 * 3 011 | DADDI | DADDIU| LDL | LDR | MMI% | * | LQ | SQ 1149 * 4 100 | LB | LH | LWL | LW | LBU | LHU | LWR | LWU 1150 * 5 101 | SB | SH | SWL | SW | SDL | SDR | SWR | CACHE 1151 * 6 110 | # | LWC1 | # | PREF | # | LDC1 | # | LD 1152 * 7 111 | # | SWC1 | # | * | # | SDC1 | # | SD 1153 */ 1154 1155 enum { 1156 MMI_OPC_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */ 1157 MMI_OPC_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */ 1158 }; 1159 1160 /* 1161 * MMI instructions with opcode field = MMI: 1162 * 1163 * 31 26 5 0 1164 * +--------+-------------------------------+--------+ 1165 * | MMI | |function| 1166 * +--------+-------------------------------+--------+ 1167 * 1168 * function bits 2..0 1169 * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 1170 * 5..3 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 1171 * -------+-------+-------+-------+-------+-------+-------+-------+------- 1172 * 0 000 | MADD | MADDU | * | * | PLZCW | * | * | * 1173 * 1 001 | MMI0% | MMI2% | * | * | * | * | * | * 1174 * 2 010 | MFHI1 | MTHI1 | MFLO1 | MTLO1 | * | * | * | * 1175 * 3 011 | MULT1 | MULTU1| DIV1 | DIVU1 | * | * | * | * 1176 * 4 100 | MADD1 | MADDU1| * | * | * | * | * | * 1177 * 5 101 | MMI1% | MMI3% | * | * | * | * | * | * 1178 * 6 110 | PMFHL | PMTHL | * | * | PSLLH | * | PSRLH | PSRAH 1179 * 7 111 | * | * | * | * | PSLLW | * | PSRLW | PSRAW 1180 */ 1181 1182 #define MASK_MMI(op) (MASK_OP_MAJOR(op) | ((op) & 0x3F)) 1183 enum { 1184 MMI_OPC_MADD = 0x00 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADD */ 1185 MMI_OPC_MADDU = 0x01 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADDU */ 1186 MMI_OPC_MULT1 = 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MULT */ 1187 MMI_OPC_MULTU1 = 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_MULTU */ 1188 MMI_OPC_DIV1 = 0x1A | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIV */ 1189 MMI_OPC_DIVU1 = 0x1B | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIVU */ 1190 MMI_OPC_MADD1 = 0x20 | MMI_OPC_CLASS_MMI, 1191 MMI_OPC_MADDU1 = 0x21 | MMI_OPC_CLASS_MMI, 1192 }; 1193 1194 /* global register indices */ 1195 TCGv cpu_gpr[32], cpu_PC; 1196 /* 1197 * For CPUs using 128-bit GPR registers, we put the lower halves in cpu_gpr[]) 1198 * and the upper halves in cpu_gpr_hi[]. 1199 */ 1200 TCGv_i64 cpu_gpr_hi[32]; 1201 TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; 1202 static TCGv cpu_dspctrl, btarget; 1203 TCGv bcond; 1204 static TCGv cpu_lladdr, cpu_llval; 1205 static TCGv_i32 hflags; 1206 TCGv_i32 fpu_fcr0, fpu_fcr31; 1207 TCGv_i64 fpu_f64[32]; 1208 1209 static const char regnames_HI[][4] = { 1210 "HI0", "HI1", "HI2", "HI3", 1211 }; 1212 1213 static const char regnames_LO[][4] = { 1214 "LO0", "LO1", "LO2", "LO3", 1215 }; 1216 1217 /* General purpose registers moves. */ 1218 void gen_load_gpr(TCGv t, int reg) 1219 { 1220 assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr)); 1221 if (reg == 0) { 1222 tcg_gen_movi_tl(t, 0); 1223 } else { 1224 tcg_gen_mov_tl(t, cpu_gpr[reg]); 1225 } 1226 } 1227 1228 void gen_store_gpr(TCGv t, int reg) 1229 { 1230 assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr)); 1231 if (reg != 0) { 1232 tcg_gen_mov_tl(cpu_gpr[reg], t); 1233 } 1234 } 1235 1236 #if defined(TARGET_MIPS64) 1237 void gen_load_gpr_hi(TCGv_i64 t, int reg) 1238 { 1239 assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr_hi)); 1240 if (reg == 0) { 1241 tcg_gen_movi_i64(t, 0); 1242 } else { 1243 tcg_gen_mov_i64(t, cpu_gpr_hi[reg]); 1244 } 1245 } 1246 1247 void gen_store_gpr_hi(TCGv_i64 t, int reg) 1248 { 1249 assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr_hi)); 1250 if (reg != 0) { 1251 tcg_gen_mov_i64(cpu_gpr_hi[reg], t); 1252 } 1253 } 1254 #endif /* TARGET_MIPS64 */ 1255 1256 /* Moves to/from shadow registers. */ 1257 static inline void gen_load_srsgpr(int from, int to) 1258 { 1259 TCGv t0 = tcg_temp_new(); 1260 1261 if (from == 0) { 1262 tcg_gen_movi_tl(t0, 0); 1263 } else { 1264 TCGv_i32 t2 = tcg_temp_new_i32(); 1265 TCGv_ptr addr = tcg_temp_new_ptr(); 1266 1267 tcg_gen_ld_i32(t2, tcg_env, offsetof(CPUMIPSState, CP0_SRSCtl)); 1268 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); 1269 tcg_gen_andi_i32(t2, t2, 0xf); 1270 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32); 1271 tcg_gen_ext_i32_ptr(addr, t2); 1272 tcg_gen_add_ptr(addr, tcg_env, addr); 1273 1274 tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from); 1275 } 1276 gen_store_gpr(t0, to); 1277 } 1278 1279 static inline void gen_store_srsgpr(int from, int to) 1280 { 1281 if (to != 0) { 1282 TCGv t0 = tcg_temp_new(); 1283 TCGv_i32 t2 = tcg_temp_new_i32(); 1284 TCGv_ptr addr = tcg_temp_new_ptr(); 1285 1286 gen_load_gpr(t0, from); 1287 tcg_gen_ld_i32(t2, tcg_env, offsetof(CPUMIPSState, CP0_SRSCtl)); 1288 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); 1289 tcg_gen_andi_i32(t2, t2, 0xf); 1290 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32); 1291 tcg_gen_ext_i32_ptr(addr, t2); 1292 tcg_gen_add_ptr(addr, tcg_env, addr); 1293 1294 tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to); 1295 } 1296 } 1297 1298 /* Tests */ 1299 static inline void gen_save_pc(target_ulong pc) 1300 { 1301 tcg_gen_movi_tl(cpu_PC, pc); 1302 } 1303 1304 static inline void save_cpu_state(DisasContext *ctx, int do_save_pc) 1305 { 1306 LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags); 1307 if (do_save_pc && ctx->base.pc_next != ctx->saved_pc) { 1308 gen_save_pc(ctx->base.pc_next); 1309 ctx->saved_pc = ctx->base.pc_next; 1310 } 1311 if (ctx->hflags != ctx->saved_hflags) { 1312 tcg_gen_movi_i32(hflags, ctx->hflags); 1313 ctx->saved_hflags = ctx->hflags; 1314 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) { 1315 case MIPS_HFLAG_BR: 1316 break; 1317 case MIPS_HFLAG_BC: 1318 case MIPS_HFLAG_BL: 1319 case MIPS_HFLAG_B: 1320 tcg_gen_movi_tl(btarget, ctx->btarget); 1321 break; 1322 } 1323 } 1324 } 1325 1326 static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx) 1327 { 1328 ctx->saved_hflags = ctx->hflags; 1329 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) { 1330 case MIPS_HFLAG_BR: 1331 break; 1332 case MIPS_HFLAG_BC: 1333 case MIPS_HFLAG_BL: 1334 case MIPS_HFLAG_B: 1335 ctx->btarget = env->btarget; 1336 break; 1337 } 1338 } 1339 1340 void generate_exception_err(DisasContext *ctx, int excp, int err) 1341 { 1342 save_cpu_state(ctx, 1); 1343 gen_helper_raise_exception_err(tcg_env, tcg_constant_i32(excp), 1344 tcg_constant_i32(err)); 1345 ctx->base.is_jmp = DISAS_NORETURN; 1346 } 1347 1348 void generate_exception(DisasContext *ctx, int excp) 1349 { 1350 gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); 1351 } 1352 1353 void generate_exception_end(DisasContext *ctx, int excp) 1354 { 1355 generate_exception_err(ctx, excp, 0); 1356 } 1357 1358 void generate_exception_break(DisasContext *ctx, int code) 1359 { 1360 #ifdef CONFIG_USER_ONLY 1361 /* Pass the break code along to cpu_loop. */ 1362 tcg_gen_st_i32(tcg_constant_i32(code), tcg_env, 1363 offsetof(CPUMIPSState, error_code)); 1364 #endif 1365 generate_exception_end(ctx, EXCP_BREAK); 1366 } 1367 1368 void gen_reserved_instruction(DisasContext *ctx) 1369 { 1370 generate_exception_end(ctx, EXCP_RI); 1371 } 1372 1373 /* Floating point register moves. */ 1374 void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) 1375 { 1376 if (ctx->hflags & MIPS_HFLAG_FRE) { 1377 generate_exception(ctx, EXCP_RI); 1378 } 1379 tcg_gen_extrl_i64_i32(t, fpu_f64[reg]); 1380 } 1381 1382 void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) 1383 { 1384 TCGv_i64 t64; 1385 if (ctx->hflags & MIPS_HFLAG_FRE) { 1386 generate_exception(ctx, EXCP_RI); 1387 } 1388 t64 = tcg_temp_new_i64(); 1389 tcg_gen_extu_i32_i64(t64, t); 1390 tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 0, 32); 1391 } 1392 1393 static void gen_load_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg) 1394 { 1395 if (ctx->hflags & MIPS_HFLAG_F64) { 1396 tcg_gen_extrh_i64_i32(t, fpu_f64[reg]); 1397 } else { 1398 gen_load_fpr32(ctx, t, reg | 1); 1399 } 1400 } 1401 1402 static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg) 1403 { 1404 if (ctx->hflags & MIPS_HFLAG_F64) { 1405 TCGv_i64 t64 = tcg_temp_new_i64(); 1406 tcg_gen_extu_i32_i64(t64, t); 1407 tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 32, 32); 1408 } else { 1409 gen_store_fpr32(ctx, t, reg | 1); 1410 } 1411 } 1412 1413 void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) 1414 { 1415 if (ctx->hflags & MIPS_HFLAG_F64) { 1416 tcg_gen_mov_i64(t, fpu_f64[reg]); 1417 } else { 1418 tcg_gen_concat32_i64(t, fpu_f64[reg & ~1], fpu_f64[reg | 1]); 1419 } 1420 } 1421 1422 void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) 1423 { 1424 if (ctx->hflags & MIPS_HFLAG_F64) { 1425 tcg_gen_mov_i64(fpu_f64[reg], t); 1426 } else { 1427 TCGv_i64 t0; 1428 tcg_gen_deposit_i64(fpu_f64[reg & ~1], fpu_f64[reg & ~1], t, 0, 32); 1429 t0 = tcg_temp_new_i64(); 1430 tcg_gen_shri_i64(t0, t, 32); 1431 tcg_gen_deposit_i64(fpu_f64[reg | 1], fpu_f64[reg | 1], t0, 0, 32); 1432 } 1433 } 1434 1435 int get_fp_bit(int cc) 1436 { 1437 if (cc) { 1438 return 24 + cc; 1439 } else { 1440 return 23; 1441 } 1442 } 1443 1444 /* Addresses computation */ 1445 void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1) 1446 { 1447 tcg_gen_add_tl(ret, arg0, arg1); 1448 1449 #if defined(TARGET_MIPS64) 1450 if (ctx->hflags & MIPS_HFLAG_AWRAP) { 1451 tcg_gen_ext32s_i64(ret, ret); 1452 } 1453 #endif 1454 } 1455 1456 void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base, target_long ofs) 1457 { 1458 tcg_gen_addi_tl(ret, base, ofs); 1459 1460 #if defined(TARGET_MIPS64) 1461 if (ctx->hflags & MIPS_HFLAG_AWRAP) { 1462 tcg_gen_ext32s_i64(ret, ret); 1463 } 1464 #endif 1465 } 1466 1467 /* Addresses computation (translation time) */ 1468 static target_long addr_add(DisasContext *ctx, target_long base, 1469 target_long offset) 1470 { 1471 target_long sum = base + offset; 1472 1473 #if defined(TARGET_MIPS64) 1474 if (ctx->hflags & MIPS_HFLAG_AWRAP) { 1475 sum = (int32_t)sum; 1476 } 1477 #endif 1478 return sum; 1479 } 1480 1481 /* Sign-extract the low 32-bits to a target_long. */ 1482 void gen_move_low32(TCGv ret, TCGv_i64 arg) 1483 { 1484 #if defined(TARGET_MIPS64) 1485 tcg_gen_ext32s_i64(ret, arg); 1486 #else 1487 tcg_gen_extrl_i64_i32(ret, arg); 1488 #endif 1489 } 1490 1491 /* Sign-extract the high 32-bits to a target_long. */ 1492 void gen_move_high32(TCGv ret, TCGv_i64 arg) 1493 { 1494 #if defined(TARGET_MIPS64) 1495 tcg_gen_sari_i64(ret, arg, 32); 1496 #else 1497 tcg_gen_extrh_i64_i32(ret, arg); 1498 #endif 1499 } 1500 1501 bool check_cp0_enabled(DisasContext *ctx) 1502 { 1503 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { 1504 generate_exception_end(ctx, EXCP_CpU); 1505 return false; 1506 } 1507 return true; 1508 } 1509 1510 void check_cp1_enabled(DisasContext *ctx) 1511 { 1512 if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) { 1513 generate_exception_err(ctx, EXCP_CpU, 1); 1514 } 1515 } 1516 1517 /* 1518 * Verify that the processor is running with COP1X instructions enabled. 1519 * This is associated with the nabla symbol in the MIPS32 and MIPS64 1520 * opcode tables. 1521 */ 1522 void check_cop1x(DisasContext *ctx) 1523 { 1524 if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) { 1525 gen_reserved_instruction(ctx); 1526 } 1527 } 1528 1529 /* 1530 * Verify that the processor is running with 64-bit floating-point 1531 * operations enabled. 1532 */ 1533 void check_cp1_64bitmode(DisasContext *ctx) 1534 { 1535 if (unlikely(~ctx->hflags & MIPS_HFLAG_F64)) { 1536 gen_reserved_instruction(ctx); 1537 } 1538 } 1539 1540 /* 1541 * Verify if floating point register is valid; an operation is not defined 1542 * if bit 0 of any register specification is set and the FR bit in the 1543 * Status register equals zero, since the register numbers specify an 1544 * even-odd pair of adjacent coprocessor general registers. When the FR bit 1545 * in the Status register equals one, both even and odd register numbers 1546 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers. 1547 * 1548 * Multiple 64 bit wide registers can be checked by calling 1549 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN); 1550 */ 1551 void check_cp1_registers(DisasContext *ctx, int regs) 1552 { 1553 if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) { 1554 gen_reserved_instruction(ctx); 1555 } 1556 } 1557 1558 /* 1559 * Verify that the processor is running with DSP instructions enabled. 1560 * This is enabled by CP0 Status register MX(24) bit. 1561 */ 1562 static inline void check_dsp(DisasContext *ctx) 1563 { 1564 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) { 1565 if (ctx->insn_flags & ASE_DSP) { 1566 generate_exception_end(ctx, EXCP_DSPDIS); 1567 } else { 1568 gen_reserved_instruction(ctx); 1569 } 1570 } 1571 } 1572 1573 static inline void check_dsp_r2(DisasContext *ctx) 1574 { 1575 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R2))) { 1576 if (ctx->insn_flags & ASE_DSP) { 1577 generate_exception_end(ctx, EXCP_DSPDIS); 1578 } else { 1579 gen_reserved_instruction(ctx); 1580 } 1581 } 1582 } 1583 1584 static inline void check_dsp_r3(DisasContext *ctx) 1585 { 1586 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R3))) { 1587 if (ctx->insn_flags & ASE_DSP) { 1588 generate_exception_end(ctx, EXCP_DSPDIS); 1589 } else { 1590 gen_reserved_instruction(ctx); 1591 } 1592 } 1593 } 1594 1595 /* 1596 * This code generates a "reserved instruction" exception if the 1597 * CPU does not support the instruction set corresponding to flags. 1598 */ 1599 void check_insn(DisasContext *ctx, uint64_t flags) 1600 { 1601 if (unlikely(!(ctx->insn_flags & flags))) { 1602 gen_reserved_instruction(ctx); 1603 } 1604 } 1605 1606 /* 1607 * This code generates a "reserved instruction" exception if the 1608 * CPU has corresponding flag set which indicates that the instruction 1609 * has been removed. 1610 */ 1611 static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags) 1612 { 1613 if (unlikely(ctx->insn_flags & flags)) { 1614 gen_reserved_instruction(ctx); 1615 } 1616 } 1617 1618 /* 1619 * The Linux kernel traps certain reserved instruction exceptions to 1620 * emulate the corresponding instructions. QEMU is the kernel in user 1621 * mode, so those traps are emulated by accepting the instructions. 1622 * 1623 * A reserved instruction exception is generated for flagged CPUs if 1624 * QEMU runs in system mode. 1625 */ 1626 static inline void check_insn_opc_user_only(DisasContext *ctx, uint64_t flags) 1627 { 1628 #ifndef CONFIG_USER_ONLY 1629 check_insn_opc_removed(ctx, flags); 1630 #endif 1631 } 1632 1633 /* 1634 * This code generates a "reserved instruction" exception if the 1635 * CPU does not support 64-bit paired-single (PS) floating point data type. 1636 */ 1637 static inline void check_ps(DisasContext *ctx) 1638 { 1639 if (unlikely(!ctx->ps)) { 1640 generate_exception(ctx, EXCP_RI); 1641 } 1642 check_cp1_64bitmode(ctx); 1643 } 1644 1645 bool decode_64bit_enabled(DisasContext *ctx) 1646 { 1647 return ctx->hflags & MIPS_HFLAG_64; 1648 } 1649 1650 /* 1651 * This code generates a "reserved instruction" exception if cpu is not 1652 * 64-bit or 64-bit instructions are not enabled. 1653 */ 1654 void check_mips_64(DisasContext *ctx) 1655 { 1656 if (unlikely((TARGET_LONG_BITS != 64) || !decode_64bit_enabled(ctx))) { 1657 gen_reserved_instruction(ctx); 1658 } 1659 } 1660 1661 #ifndef CONFIG_USER_ONLY 1662 static inline void check_mvh(DisasContext *ctx) 1663 { 1664 if (unlikely(!ctx->mvh)) { 1665 generate_exception(ctx, EXCP_RI); 1666 } 1667 } 1668 #endif 1669 1670 /* 1671 * This code generates a "reserved instruction" exception if the 1672 * Config5 XNP bit is set. 1673 */ 1674 static inline void check_xnp(DisasContext *ctx) 1675 { 1676 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) { 1677 gen_reserved_instruction(ctx); 1678 } 1679 } 1680 1681 #ifndef CONFIG_USER_ONLY 1682 /* 1683 * This code generates a "reserved instruction" exception if the 1684 * Config3 PW bit is NOT set. 1685 */ 1686 static inline void check_pw(DisasContext *ctx) 1687 { 1688 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_PW)))) { 1689 gen_reserved_instruction(ctx); 1690 } 1691 } 1692 #endif 1693 1694 /* 1695 * This code generates a "reserved instruction" exception if the 1696 * Config3 MT bit is NOT set. 1697 */ 1698 static inline void check_mt(DisasContext *ctx) 1699 { 1700 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { 1701 gen_reserved_instruction(ctx); 1702 } 1703 } 1704 1705 #ifndef CONFIG_USER_ONLY 1706 /* 1707 * This code generates a "coprocessor unusable" exception if CP0 is not 1708 * available, and, if that is not the case, generates a "reserved instruction" 1709 * exception if the Config5 MT bit is NOT set. This is needed for availability 1710 * control of some of MT ASE instructions. 1711 */ 1712 static inline void check_cp0_mt(DisasContext *ctx) 1713 { 1714 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { 1715 generate_exception_end(ctx, EXCP_CpU); 1716 } else { 1717 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { 1718 gen_reserved_instruction(ctx); 1719 } 1720 } 1721 } 1722 #endif 1723 1724 /* 1725 * This code generates a "reserved instruction" exception if the 1726 * Config5 NMS bit is set. 1727 */ 1728 static inline void check_nms(DisasContext *ctx) 1729 { 1730 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) { 1731 gen_reserved_instruction(ctx); 1732 } 1733 } 1734 1735 /* 1736 * This code generates a "reserved instruction" exception if the 1737 * Config5 NMS bit is set, and Config1 DL, Config1 IL, Config2 SL, 1738 * Config2 TL, and Config5 L2C are unset. 1739 */ 1740 static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx) 1741 { 1742 if (unlikely((ctx->CP0_Config5 & (1 << CP0C5_NMS)) && 1743 !(ctx->CP0_Config1 & (1 << CP0C1_DL)) && 1744 !(ctx->CP0_Config1 & (1 << CP0C1_IL)) && 1745 !(ctx->CP0_Config2 & (1 << CP0C2_SL)) && 1746 !(ctx->CP0_Config2 & (1 << CP0C2_TL)) && 1747 !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) { 1748 gen_reserved_instruction(ctx); 1749 } 1750 } 1751 1752 /* 1753 * This code generates a "reserved instruction" exception if the 1754 * Config5 EVA bit is NOT set. 1755 */ 1756 static inline void check_eva(DisasContext *ctx) 1757 { 1758 if (unlikely(!(ctx->CP0_Config5 & (1 << CP0C5_EVA)))) { 1759 gen_reserved_instruction(ctx); 1760 } 1761 } 1762 1763 1764 /* 1765 * Define small wrappers for gen_load_fpr* so that we have a uniform 1766 * calling interface for 32 and 64-bit FPRs. No sense in changing 1767 * all callers for gen_load_fpr32 when we need the CTX parameter for 1768 * this one use. 1769 */ 1770 #define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(ctx, x, y) 1771 #define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y) 1772 #define FOP_CONDS(type, abs, fmt, ifmt, bits) \ 1773 static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \ 1774 int ft, int fs, int cc) \ 1775 { \ 1776 TCGv_i##bits fp0 = tcg_temp_new_i##bits(); \ 1777 TCGv_i##bits fp1 = tcg_temp_new_i##bits(); \ 1778 switch (ifmt) { \ 1779 case FMT_PS: \ 1780 check_ps(ctx); \ 1781 break; \ 1782 case FMT_D: \ 1783 if (abs) { \ 1784 check_cop1x(ctx); \ 1785 } \ 1786 check_cp1_registers(ctx, fs | ft); \ 1787 break; \ 1788 case FMT_S: \ 1789 if (abs) { \ 1790 check_cop1x(ctx); \ 1791 } \ 1792 break; \ 1793 } \ 1794 gen_ldcmp_fpr##bits(ctx, fp0, fs); \ 1795 gen_ldcmp_fpr##bits(ctx, fp1, ft); \ 1796 switch (n) { \ 1797 case 0: \ 1798 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); \ 1799 break; \ 1800 case 1: \ 1801 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); \ 1802 break; \ 1803 case 2: \ 1804 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); \ 1805 break; \ 1806 case 3: \ 1807 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); \ 1808 break; \ 1809 case 4: \ 1810 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); \ 1811 break; \ 1812 case 5: \ 1813 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); \ 1814 break; \ 1815 case 6: \ 1816 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); \ 1817 break; \ 1818 case 7: \ 1819 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); \ 1820 break; \ 1821 case 8: \ 1822 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); \ 1823 break; \ 1824 case 9: \ 1825 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); \ 1826 break; \ 1827 case 10: \ 1828 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); \ 1829 break; \ 1830 case 11: \ 1831 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); \ 1832 break; \ 1833 case 12: \ 1834 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); \ 1835 break; \ 1836 case 13: \ 1837 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); \ 1838 break; \ 1839 case 14: \ 1840 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); \ 1841 break; \ 1842 case 15: \ 1843 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); \ 1844 break; \ 1845 default: \ 1846 abort(); \ 1847 } \ 1848 } 1849 1850 FOP_CONDS(, 0, d, FMT_D, 64) 1851 FOP_CONDS(abs, 1, d, FMT_D, 64) 1852 FOP_CONDS(, 0, s, FMT_S, 32) 1853 FOP_CONDS(abs, 1, s, FMT_S, 32) 1854 FOP_CONDS(, 0, ps, FMT_PS, 64) 1855 FOP_CONDS(abs, 1, ps, FMT_PS, 64) 1856 #undef FOP_CONDS 1857 1858 #define FOP_CONDNS(fmt, ifmt, bits, STORE) \ 1859 static inline void gen_r6_cmp_ ## fmt(DisasContext *ctx, int n, \ 1860 int ft, int fs, int fd) \ 1861 { \ 1862 TCGv_i ## bits fp0 = tcg_temp_new_i ## bits(); \ 1863 TCGv_i ## bits fp1 = tcg_temp_new_i ## bits(); \ 1864 if (ifmt == FMT_D) { \ 1865 check_cp1_registers(ctx, fs | ft | fd); \ 1866 } \ 1867 gen_ldcmp_fpr ## bits(ctx, fp0, fs); \ 1868 gen_ldcmp_fpr ## bits(ctx, fp1, ft); \ 1869 switch (n) { \ 1870 case 0: \ 1871 gen_helper_r6_cmp_ ## fmt ## _af(fp0, tcg_env, fp0, fp1); \ 1872 break; \ 1873 case 1: \ 1874 gen_helper_r6_cmp_ ## fmt ## _un(fp0, tcg_env, fp0, fp1); \ 1875 break; \ 1876 case 2: \ 1877 gen_helper_r6_cmp_ ## fmt ## _eq(fp0, tcg_env, fp0, fp1); \ 1878 break; \ 1879 case 3: \ 1880 gen_helper_r6_cmp_ ## fmt ## _ueq(fp0, tcg_env, fp0, fp1); \ 1881 break; \ 1882 case 4: \ 1883 gen_helper_r6_cmp_ ## fmt ## _lt(fp0, tcg_env, fp0, fp1); \ 1884 break; \ 1885 case 5: \ 1886 gen_helper_r6_cmp_ ## fmt ## _ult(fp0, tcg_env, fp0, fp1); \ 1887 break; \ 1888 case 6: \ 1889 gen_helper_r6_cmp_ ## fmt ## _le(fp0, tcg_env, fp0, fp1); \ 1890 break; \ 1891 case 7: \ 1892 gen_helper_r6_cmp_ ## fmt ## _ule(fp0, tcg_env, fp0, fp1); \ 1893 break; \ 1894 case 8: \ 1895 gen_helper_r6_cmp_ ## fmt ## _saf(fp0, tcg_env, fp0, fp1); \ 1896 break; \ 1897 case 9: \ 1898 gen_helper_r6_cmp_ ## fmt ## _sun(fp0, tcg_env, fp0, fp1); \ 1899 break; \ 1900 case 10: \ 1901 gen_helper_r6_cmp_ ## fmt ## _seq(fp0, tcg_env, fp0, fp1); \ 1902 break; \ 1903 case 11: \ 1904 gen_helper_r6_cmp_ ## fmt ## _sueq(fp0, tcg_env, fp0, fp1); \ 1905 break; \ 1906 case 12: \ 1907 gen_helper_r6_cmp_ ## fmt ## _slt(fp0, tcg_env, fp0, fp1); \ 1908 break; \ 1909 case 13: \ 1910 gen_helper_r6_cmp_ ## fmt ## _sult(fp0, tcg_env, fp0, fp1); \ 1911 break; \ 1912 case 14: \ 1913 gen_helper_r6_cmp_ ## fmt ## _sle(fp0, tcg_env, fp0, fp1); \ 1914 break; \ 1915 case 15: \ 1916 gen_helper_r6_cmp_ ## fmt ## _sule(fp0, tcg_env, fp0, fp1); \ 1917 break; \ 1918 case 17: \ 1919 gen_helper_r6_cmp_ ## fmt ## _or(fp0, tcg_env, fp0, fp1); \ 1920 break; \ 1921 case 18: \ 1922 gen_helper_r6_cmp_ ## fmt ## _une(fp0, tcg_env, fp0, fp1); \ 1923 break; \ 1924 case 19: \ 1925 gen_helper_r6_cmp_ ## fmt ## _ne(fp0, tcg_env, fp0, fp1); \ 1926 break; \ 1927 case 25: \ 1928 gen_helper_r6_cmp_ ## fmt ## _sor(fp0, tcg_env, fp0, fp1); \ 1929 break; \ 1930 case 26: \ 1931 gen_helper_r6_cmp_ ## fmt ## _sune(fp0, tcg_env, fp0, fp1); \ 1932 break; \ 1933 case 27: \ 1934 gen_helper_r6_cmp_ ## fmt ## _sne(fp0, tcg_env, fp0, fp1); \ 1935 break; \ 1936 default: \ 1937 abort(); \ 1938 } \ 1939 STORE; \ 1940 } 1941 1942 FOP_CONDNS(d, FMT_D, 64, gen_store_fpr64(ctx, fp0, fd)) 1943 FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, fd)) 1944 #undef FOP_CONDNS 1945 #undef gen_ldcmp_fpr32 1946 #undef gen_ldcmp_fpr64 1947 1948 /* load/store instructions. */ 1949 #ifdef CONFIG_USER_ONLY 1950 #define OP_LD_ATOMIC(insn, memop) \ 1951 static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \ 1952 DisasContext *ctx) \ 1953 { \ 1954 TCGv t0 = tcg_temp_new(); \ 1955 tcg_gen_mov_tl(t0, arg1); \ 1956 tcg_gen_qemu_ld_tl(ret, arg1, ctx->mem_idx, memop); \ 1957 tcg_gen_st_tl(t0, tcg_env, offsetof(CPUMIPSState, lladdr)); \ 1958 tcg_gen_st_tl(ret, tcg_env, offsetof(CPUMIPSState, llval)); \ 1959 } 1960 #else 1961 #define OP_LD_ATOMIC(insn, ignored_memop) \ 1962 static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \ 1963 DisasContext *ctx) \ 1964 { \ 1965 gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(mem_idx)); \ 1966 } 1967 #endif 1968 OP_LD_ATOMIC(ll, mo_endian(ctx) | MO_SL); 1969 #if defined(TARGET_MIPS64) 1970 OP_LD_ATOMIC(lld, mo_endian(ctx) | MO_UQ); 1971 #endif 1972 #undef OP_LD_ATOMIC 1973 1974 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset) 1975 { 1976 if (base == 0) { 1977 tcg_gen_movi_tl(addr, offset); 1978 } else if (offset == 0) { 1979 gen_load_gpr(addr, base); 1980 } else { 1981 tcg_gen_movi_tl(addr, offset); 1982 gen_op_addr_add(ctx, addr, cpu_gpr[base], addr); 1983 } 1984 } 1985 1986 static target_ulong pc_relative_pc(DisasContext *ctx) 1987 { 1988 target_ulong pc = ctx->base.pc_next; 1989 1990 if (ctx->hflags & MIPS_HFLAG_BMASK) { 1991 int branch_bytes = ctx->hflags & MIPS_HFLAG_BDS16 ? 2 : 4; 1992 1993 pc -= branch_bytes; 1994 } 1995 1996 pc &= ~(target_ulong)3; 1997 return pc; 1998 } 1999 2000 /* LWL or LDL, depending on MemOp. */ 2001 static void gen_lxl(DisasContext *ctx, TCGv reg, TCGv addr, 2002 int mem_idx, MemOp mop) 2003 { 2004 int sizem1 = memop_size(mop) - 1; 2005 TCGv t0 = tcg_temp_new(); 2006 TCGv t1 = tcg_temp_new(); 2007 2008 /* 2009 * Do a byte access to possibly trigger a page 2010 * fault with the unaligned address. 2011 */ 2012 tcg_gen_qemu_ld_tl(t1, addr, mem_idx, MO_UB); 2013 tcg_gen_andi_tl(t1, addr, sizem1); 2014 if (!disas_is_bigendian(ctx)) { 2015 tcg_gen_xori_tl(t1, t1, sizem1); 2016 } 2017 tcg_gen_shli_tl(t1, t1, 3); 2018 tcg_gen_andi_tl(t0, addr, ~sizem1); 2019 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mop); 2020 tcg_gen_shl_tl(t0, t0, t1); 2021 tcg_gen_shl_tl(t1, tcg_constant_tl(-1), t1); 2022 tcg_gen_andc_tl(t1, reg, t1); 2023 tcg_gen_or_tl(reg, t0, t1); 2024 } 2025 2026 /* LWR or LDR, depending on MemOp. */ 2027 static void gen_lxr(DisasContext *ctx, TCGv reg, TCGv addr, 2028 int mem_idx, MemOp mop) 2029 { 2030 int size = memop_size(mop); 2031 int sizem1 = size - 1; 2032 TCGv t0 = tcg_temp_new(); 2033 TCGv t1 = tcg_temp_new(); 2034 2035 /* 2036 * Do a byte access to possibly trigger a page 2037 * fault with the unaligned address. 2038 */ 2039 tcg_gen_qemu_ld_tl(t1, addr, mem_idx, MO_UB); 2040 tcg_gen_andi_tl(t1, addr, sizem1); 2041 if (disas_is_bigendian(ctx)) { 2042 tcg_gen_xori_tl(t1, t1, sizem1); 2043 } 2044 tcg_gen_shli_tl(t1, t1, 3); 2045 tcg_gen_andi_tl(t0, addr, ~sizem1); 2046 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mop); 2047 tcg_gen_shr_tl(t0, t0, t1); 2048 tcg_gen_xori_tl(t1, t1, size * 8 - 1); 2049 tcg_gen_shl_tl(t1, tcg_constant_tl(~1), t1); 2050 tcg_gen_and_tl(t1, reg, t1); 2051 tcg_gen_or_tl(reg, t0, t1); 2052 } 2053 2054 /* Load */ 2055 static void gen_ld(DisasContext *ctx, uint32_t opc, 2056 int rt, int base, int offset) 2057 { 2058 TCGv t0, t1; 2059 int mem_idx = ctx->mem_idx; 2060 2061 if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F | 2062 INSN_LOONGSON3A)) { 2063 /* 2064 * Loongson CPU uses a load to zero register for prefetch. 2065 * We emulate it as a NOP. On other CPU we must perform the 2066 * actual memory access. 2067 */ 2068 return; 2069 } 2070 2071 t0 = tcg_temp_new(); 2072 gen_base_offset_addr(ctx, t0, base, offset); 2073 2074 switch (opc) { 2075 #if defined(TARGET_MIPS64) 2076 case OPC_LWU: 2077 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UL | 2078 ctx->default_tcg_memop_mask); 2079 gen_store_gpr(t0, rt); 2080 break; 2081 case OPC_LD: 2082 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UQ | 2083 ctx->default_tcg_memop_mask); 2084 gen_store_gpr(t0, rt); 2085 break; 2086 case OPC_LLD: 2087 case R6_OPC_LLD: 2088 op_ld_lld(t0, t0, mem_idx, ctx); 2089 gen_store_gpr(t0, rt); 2090 break; 2091 case OPC_LDL: 2092 t1 = tcg_temp_new(); 2093 gen_load_gpr(t1, rt); 2094 gen_lxl(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UQ); 2095 gen_store_gpr(t1, rt); 2096 break; 2097 case OPC_LDR: 2098 t1 = tcg_temp_new(); 2099 gen_load_gpr(t1, rt); 2100 gen_lxr(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UQ); 2101 gen_store_gpr(t1, rt); 2102 break; 2103 case OPC_LDPC: 2104 t1 = tcg_constant_tl(pc_relative_pc(ctx)); 2105 gen_op_addr_add(ctx, t0, t0, t1); 2106 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UQ); 2107 gen_store_gpr(t0, rt); 2108 break; 2109 #endif 2110 case OPC_LWPC: 2111 t1 = tcg_constant_tl(pc_relative_pc(ctx)); 2112 gen_op_addr_add(ctx, t0, t0, t1); 2113 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SL); 2114 gen_store_gpr(t0, rt); 2115 break; 2116 case OPC_LWE: 2117 mem_idx = MIPS_HFLAG_UM; 2118 /* fall through */ 2119 case OPC_LW: 2120 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SL | 2121 ctx->default_tcg_memop_mask); 2122 gen_store_gpr(t0, rt); 2123 break; 2124 case OPC_LHE: 2125 mem_idx = MIPS_HFLAG_UM; 2126 /* fall through */ 2127 case OPC_LH: 2128 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SW | 2129 ctx->default_tcg_memop_mask); 2130 gen_store_gpr(t0, rt); 2131 break; 2132 case OPC_LHUE: 2133 mem_idx = MIPS_HFLAG_UM; 2134 /* fall through */ 2135 case OPC_LHU: 2136 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UW | 2137 ctx->default_tcg_memop_mask); 2138 gen_store_gpr(t0, rt); 2139 break; 2140 case OPC_LBE: 2141 mem_idx = MIPS_HFLAG_UM; 2142 /* fall through */ 2143 case OPC_LB: 2144 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_SB); 2145 gen_store_gpr(t0, rt); 2146 break; 2147 case OPC_LBUE: 2148 mem_idx = MIPS_HFLAG_UM; 2149 /* fall through */ 2150 case OPC_LBU: 2151 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_UB); 2152 gen_store_gpr(t0, rt); 2153 break; 2154 case OPC_LWLE: 2155 mem_idx = MIPS_HFLAG_UM; 2156 /* fall through */ 2157 case OPC_LWL: 2158 t1 = tcg_temp_new(); 2159 gen_load_gpr(t1, rt); 2160 gen_lxl(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UL); 2161 tcg_gen_ext32s_tl(t1, t1); 2162 gen_store_gpr(t1, rt); 2163 break; 2164 case OPC_LWRE: 2165 mem_idx = MIPS_HFLAG_UM; 2166 /* fall through */ 2167 case OPC_LWR: 2168 t1 = tcg_temp_new(); 2169 gen_load_gpr(t1, rt); 2170 gen_lxr(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UL); 2171 tcg_gen_ext32s_tl(t1, t1); 2172 gen_store_gpr(t1, rt); 2173 break; 2174 case OPC_LLE: 2175 mem_idx = MIPS_HFLAG_UM; 2176 /* fall through */ 2177 case OPC_LL: 2178 case R6_OPC_LL: 2179 op_ld_ll(t0, t0, mem_idx, ctx); 2180 gen_store_gpr(t0, rt); 2181 break; 2182 } 2183 } 2184 2185 /* Store */ 2186 static void gen_st(DisasContext *ctx, uint32_t opc, int rt, 2187 int base, int offset) 2188 { 2189 TCGv t0 = tcg_temp_new(); 2190 TCGv t1 = tcg_temp_new(); 2191 int mem_idx = ctx->mem_idx; 2192 2193 gen_base_offset_addr(ctx, t0, base, offset); 2194 gen_load_gpr(t1, rt); 2195 switch (opc) { 2196 #if defined(TARGET_MIPS64) 2197 case OPC_SD: 2198 tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UQ | 2199 ctx->default_tcg_memop_mask); 2200 break; 2201 case OPC_SDL: 2202 gen_helper_0e2i(sdl, t1, t0, mem_idx); 2203 break; 2204 case OPC_SDR: 2205 gen_helper_0e2i(sdr, t1, t0, mem_idx); 2206 break; 2207 #endif 2208 case OPC_SWE: 2209 mem_idx = MIPS_HFLAG_UM; 2210 /* fall through */ 2211 case OPC_SW: 2212 tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UL | 2213 ctx->default_tcg_memop_mask); 2214 break; 2215 case OPC_SHE: 2216 mem_idx = MIPS_HFLAG_UM; 2217 /* fall through */ 2218 case OPC_SH: 2219 tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UW | 2220 ctx->default_tcg_memop_mask); 2221 break; 2222 case OPC_SBE: 2223 mem_idx = MIPS_HFLAG_UM; 2224 /* fall through */ 2225 case OPC_SB: 2226 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_8); 2227 break; 2228 case OPC_SWLE: 2229 mem_idx = MIPS_HFLAG_UM; 2230 /* fall through */ 2231 case OPC_SWL: 2232 gen_helper_0e2i(swl, t1, t0, mem_idx); 2233 break; 2234 case OPC_SWRE: 2235 mem_idx = MIPS_HFLAG_UM; 2236 /* fall through */ 2237 case OPC_SWR: 2238 gen_helper_0e2i(swr, t1, t0, mem_idx); 2239 break; 2240 } 2241 } 2242 2243 2244 /* Store conditional */ 2245 static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset, 2246 MemOp tcg_mo, bool eva) 2247 { 2248 TCGv addr, t0, val; 2249 TCGLabel *l1 = gen_new_label(); 2250 TCGLabel *done = gen_new_label(); 2251 2252 t0 = tcg_temp_new(); 2253 addr = tcg_temp_new(); 2254 /* compare the address against that of the preceding LL */ 2255 gen_base_offset_addr(ctx, addr, base, offset); 2256 tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1); 2257 gen_store_gpr(tcg_constant_tl(0), rt); 2258 tcg_gen_br(done); 2259 2260 gen_set_label(l1); 2261 /* generate cmpxchg */ 2262 val = tcg_temp_new(); 2263 gen_load_gpr(val, rt); 2264 tcg_gen_atomic_cmpxchg_tl(t0, cpu_lladdr, cpu_llval, val, 2265 eva ? MIPS_HFLAG_UM : ctx->mem_idx, tcg_mo); 2266 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_llval); 2267 gen_store_gpr(t0, rt); 2268 2269 gen_set_label(done); 2270 } 2271 2272 /* Load and store */ 2273 static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft, 2274 TCGv t0) 2275 { 2276 /* 2277 * Don't do NOP if destination is zero: we must perform the actual 2278 * memory access. 2279 */ 2280 switch (opc) { 2281 case OPC_LWC1: 2282 { 2283 TCGv_i32 fp0 = tcg_temp_new_i32(); 2284 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | 2285 ctx->default_tcg_memop_mask); 2286 gen_store_fpr32(ctx, fp0, ft); 2287 } 2288 break; 2289 case OPC_SWC1: 2290 { 2291 TCGv_i32 fp0 = tcg_temp_new_i32(); 2292 gen_load_fpr32(ctx, fp0, ft); 2293 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | 2294 ctx->default_tcg_memop_mask); 2295 } 2296 break; 2297 case OPC_LDC1: 2298 { 2299 TCGv_i64 fp0 = tcg_temp_new_i64(); 2300 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | 2301 ctx->default_tcg_memop_mask); 2302 gen_store_fpr64(ctx, fp0, ft); 2303 } 2304 break; 2305 case OPC_SDC1: 2306 { 2307 TCGv_i64 fp0 = tcg_temp_new_i64(); 2308 gen_load_fpr64(ctx, fp0, ft); 2309 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | 2310 ctx->default_tcg_memop_mask); 2311 } 2312 break; 2313 default: 2314 MIPS_INVAL("flt_ldst"); 2315 gen_reserved_instruction(ctx); 2316 break; 2317 } 2318 } 2319 2320 static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt, 2321 int rs, int16_t imm) 2322 { 2323 TCGv t0 = tcg_temp_new(); 2324 2325 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { 2326 check_cp1_enabled(ctx); 2327 switch (op) { 2328 case OPC_LDC1: 2329 case OPC_SDC1: 2330 check_insn(ctx, ISA_MIPS2); 2331 /* Fallthrough */ 2332 default: 2333 gen_base_offset_addr(ctx, t0, rs, imm); 2334 gen_flt_ldst(ctx, op, rt, t0); 2335 } 2336 } else { 2337 generate_exception_err(ctx, EXCP_CpU, 1); 2338 } 2339 } 2340 2341 /* Arithmetic with immediate operand */ 2342 static void gen_arith_imm(DisasContext *ctx, uint32_t opc, 2343 int rt, int rs, int imm) 2344 { 2345 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ 2346 2347 if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) { 2348 /* 2349 * If no destination, treat it as a NOP. 2350 * For addi, we must generate the overflow exception when needed. 2351 */ 2352 return; 2353 } 2354 switch (opc) { 2355 case OPC_ADDI: 2356 { 2357 TCGv t0 = tcg_temp_new(); 2358 TCGv t1 = tcg_temp_new(); 2359 TCGv t2 = tcg_temp_new(); 2360 TCGLabel *l1 = gen_new_label(); 2361 2362 gen_load_gpr(t1, rs); 2363 tcg_gen_addi_tl(t0, t1, uimm); 2364 tcg_gen_ext32s_tl(t0, t0); 2365 2366 tcg_gen_xori_tl(t1, t1, ~uimm); 2367 tcg_gen_xori_tl(t2, t0, uimm); 2368 tcg_gen_and_tl(t1, t1, t2); 2369 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2370 /* operands of same sign, result different sign */ 2371 generate_exception(ctx, EXCP_OVERFLOW); 2372 gen_set_label(l1); 2373 tcg_gen_ext32s_tl(t0, t0); 2374 gen_store_gpr(t0, rt); 2375 } 2376 break; 2377 case OPC_ADDIU: 2378 if (rs != 0) { 2379 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); 2380 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 2381 } else { 2382 tcg_gen_movi_tl(cpu_gpr[rt], uimm); 2383 } 2384 break; 2385 #if defined(TARGET_MIPS64) 2386 case OPC_DADDI: 2387 { 2388 TCGv t0 = tcg_temp_new(); 2389 TCGv t1 = tcg_temp_new(); 2390 TCGv t2 = tcg_temp_new(); 2391 TCGLabel *l1 = gen_new_label(); 2392 2393 gen_load_gpr(t1, rs); 2394 tcg_gen_addi_tl(t0, t1, uimm); 2395 2396 tcg_gen_xori_tl(t1, t1, ~uimm); 2397 tcg_gen_xori_tl(t2, t0, uimm); 2398 tcg_gen_and_tl(t1, t1, t2); 2399 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2400 /* operands of same sign, result different sign */ 2401 generate_exception(ctx, EXCP_OVERFLOW); 2402 gen_set_label(l1); 2403 gen_store_gpr(t0, rt); 2404 } 2405 break; 2406 case OPC_DADDIU: 2407 if (rs != 0) { 2408 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); 2409 } else { 2410 tcg_gen_movi_tl(cpu_gpr[rt], uimm); 2411 } 2412 break; 2413 #endif 2414 } 2415 } 2416 2417 /* Logic with immediate operand */ 2418 static void gen_logic_imm(DisasContext *ctx, uint32_t opc, 2419 int rt, int rs, int16_t imm) 2420 { 2421 target_ulong uimm; 2422 2423 if (rt == 0) { 2424 /* If no destination, treat it as a NOP. */ 2425 return; 2426 } 2427 uimm = (uint16_t)imm; 2428 switch (opc) { 2429 case OPC_ANDI: 2430 if (likely(rs != 0)) { 2431 tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); 2432 } else { 2433 tcg_gen_movi_tl(cpu_gpr[rt], 0); 2434 } 2435 break; 2436 case OPC_ORI: 2437 if (rs != 0) { 2438 tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); 2439 } else { 2440 tcg_gen_movi_tl(cpu_gpr[rt], uimm); 2441 } 2442 break; 2443 case OPC_XORI: 2444 if (likely(rs != 0)) { 2445 tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); 2446 } else { 2447 tcg_gen_movi_tl(cpu_gpr[rt], uimm); 2448 } 2449 break; 2450 case OPC_LUI: 2451 if (rs != 0 && (ctx->insn_flags & ISA_MIPS_R6)) { 2452 /* OPC_AUI */ 2453 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm << 16); 2454 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 2455 } else { 2456 tcg_gen_movi_tl(cpu_gpr[rt], imm << 16); 2457 } 2458 break; 2459 2460 default: 2461 break; 2462 } 2463 } 2464 2465 /* Set on less than with immediate operand */ 2466 static void gen_slt_imm(DisasContext *ctx, uint32_t opc, 2467 int rt, int rs, int16_t imm) 2468 { 2469 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ 2470 TCGv t0; 2471 2472 if (rt == 0) { 2473 /* If no destination, treat it as a NOP. */ 2474 return; 2475 } 2476 t0 = tcg_temp_new(); 2477 gen_load_gpr(t0, rs); 2478 switch (opc) { 2479 case OPC_SLTI: 2480 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr[rt], t0, uimm); 2481 break; 2482 case OPC_SLTIU: 2483 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rt], t0, uimm); 2484 break; 2485 } 2486 } 2487 2488 /* Shifts with immediate operand */ 2489 static void gen_shift_imm(DisasContext *ctx, uint32_t opc, 2490 int rt, int rs, int16_t imm) 2491 { 2492 target_ulong uimm = ((uint16_t)imm) & 0x1f; 2493 TCGv t0; 2494 2495 if (rt == 0) { 2496 /* If no destination, treat it as a NOP. */ 2497 return; 2498 } 2499 2500 t0 = tcg_temp_new(); 2501 gen_load_gpr(t0, rs); 2502 switch (opc) { 2503 case OPC_SLL: 2504 tcg_gen_shli_tl(t0, t0, uimm); 2505 tcg_gen_ext32s_tl(cpu_gpr[rt], t0); 2506 break; 2507 case OPC_SRA: 2508 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm); 2509 break; 2510 case OPC_SRL: 2511 if (uimm != 0) { 2512 tcg_gen_ext32u_tl(t0, t0); 2513 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm); 2514 } else { 2515 tcg_gen_ext32s_tl(cpu_gpr[rt], t0); 2516 } 2517 break; 2518 case OPC_ROTR: 2519 if (uimm != 0) { 2520 TCGv_i32 t1 = tcg_temp_new_i32(); 2521 2522 tcg_gen_trunc_tl_i32(t1, t0); 2523 tcg_gen_rotri_i32(t1, t1, uimm); 2524 tcg_gen_ext_i32_tl(cpu_gpr[rt], t1); 2525 } else { 2526 tcg_gen_ext32s_tl(cpu_gpr[rt], t0); 2527 } 2528 break; 2529 #if defined(TARGET_MIPS64) 2530 case OPC_DSLL: 2531 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm); 2532 break; 2533 case OPC_DSRA: 2534 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm); 2535 break; 2536 case OPC_DSRL: 2537 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm); 2538 break; 2539 case OPC_DROTR: 2540 if (uimm != 0) { 2541 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm); 2542 } else { 2543 tcg_gen_mov_tl(cpu_gpr[rt], t0); 2544 } 2545 break; 2546 case OPC_DSLL32: 2547 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm + 32); 2548 break; 2549 case OPC_DSRA32: 2550 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm + 32); 2551 break; 2552 case OPC_DSRL32: 2553 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32); 2554 break; 2555 case OPC_DROTR32: 2556 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm + 32); 2557 break; 2558 #endif 2559 } 2560 } 2561 2562 /* Arithmetic */ 2563 static void gen_arith(DisasContext *ctx, uint32_t opc, 2564 int rd, int rs, int rt) 2565 { 2566 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB 2567 && opc != OPC_DADD && opc != OPC_DSUB) { 2568 /* 2569 * If no destination, treat it as a NOP. 2570 * For add & sub, we must generate the overflow exception when needed. 2571 */ 2572 return; 2573 } 2574 2575 switch (opc) { 2576 case OPC_ADD: 2577 { 2578 TCGv t0 = tcg_temp_new(); 2579 TCGv t1 = tcg_temp_new(); 2580 TCGv t2 = tcg_temp_new(); 2581 TCGLabel *l1 = gen_new_label(); 2582 2583 gen_load_gpr(t1, rs); 2584 gen_load_gpr(t2, rt); 2585 tcg_gen_add_tl(t0, t1, t2); 2586 tcg_gen_ext32s_tl(t0, t0); 2587 tcg_gen_xor_tl(t1, t1, t2); 2588 tcg_gen_xor_tl(t2, t0, t2); 2589 tcg_gen_andc_tl(t1, t2, t1); 2590 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2591 /* operands of same sign, result different sign */ 2592 generate_exception(ctx, EXCP_OVERFLOW); 2593 gen_set_label(l1); 2594 gen_store_gpr(t0, rd); 2595 } 2596 break; 2597 case OPC_ADDU: 2598 if (rs != 0 && rt != 0) { 2599 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2600 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 2601 } else if (rs == 0 && rt != 0) { 2602 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); 2603 } else if (rs != 0 && rt == 0) { 2604 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2605 } else { 2606 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2607 } 2608 break; 2609 case OPC_SUB: 2610 { 2611 TCGv t0 = tcg_temp_new(); 2612 TCGv t1 = tcg_temp_new(); 2613 TCGv t2 = tcg_temp_new(); 2614 TCGLabel *l1 = gen_new_label(); 2615 2616 gen_load_gpr(t1, rs); 2617 gen_load_gpr(t2, rt); 2618 tcg_gen_sub_tl(t0, t1, t2); 2619 tcg_gen_ext32s_tl(t0, t0); 2620 tcg_gen_xor_tl(t2, t1, t2); 2621 tcg_gen_xor_tl(t1, t0, t1); 2622 tcg_gen_and_tl(t1, t1, t2); 2623 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2624 /* 2625 * operands of different sign, first operand and the result 2626 * of different sign 2627 */ 2628 generate_exception(ctx, EXCP_OVERFLOW); 2629 gen_set_label(l1); 2630 gen_store_gpr(t0, rd); 2631 } 2632 break; 2633 case OPC_SUBU: 2634 if (rs != 0 && rt != 0) { 2635 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2636 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 2637 } else if (rs == 0 && rt != 0) { 2638 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]); 2639 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 2640 } else if (rs != 0 && rt == 0) { 2641 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2642 } else { 2643 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2644 } 2645 break; 2646 #if defined(TARGET_MIPS64) 2647 case OPC_DADD: 2648 { 2649 TCGv t0 = tcg_temp_new(); 2650 TCGv t1 = tcg_temp_new(); 2651 TCGv t2 = tcg_temp_new(); 2652 TCGLabel *l1 = gen_new_label(); 2653 2654 gen_load_gpr(t1, rs); 2655 gen_load_gpr(t2, rt); 2656 tcg_gen_add_tl(t0, t1, t2); 2657 tcg_gen_xor_tl(t1, t1, t2); 2658 tcg_gen_xor_tl(t2, t0, t2); 2659 tcg_gen_andc_tl(t1, t2, t1); 2660 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2661 /* operands of same sign, result different sign */ 2662 generate_exception(ctx, EXCP_OVERFLOW); 2663 gen_set_label(l1); 2664 gen_store_gpr(t0, rd); 2665 } 2666 break; 2667 case OPC_DADDU: 2668 if (rs != 0 && rt != 0) { 2669 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2670 } else if (rs == 0 && rt != 0) { 2671 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); 2672 } else if (rs != 0 && rt == 0) { 2673 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2674 } else { 2675 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2676 } 2677 break; 2678 case OPC_DSUB: 2679 { 2680 TCGv t0 = tcg_temp_new(); 2681 TCGv t1 = tcg_temp_new(); 2682 TCGv t2 = tcg_temp_new(); 2683 TCGLabel *l1 = gen_new_label(); 2684 2685 gen_load_gpr(t1, rs); 2686 gen_load_gpr(t2, rt); 2687 tcg_gen_sub_tl(t0, t1, t2); 2688 tcg_gen_xor_tl(t2, t1, t2); 2689 tcg_gen_xor_tl(t1, t0, t1); 2690 tcg_gen_and_tl(t1, t1, t2); 2691 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2692 /* 2693 * Operands of different sign, first operand and result different 2694 * sign. 2695 */ 2696 generate_exception(ctx, EXCP_OVERFLOW); 2697 gen_set_label(l1); 2698 gen_store_gpr(t0, rd); 2699 } 2700 break; 2701 case OPC_DSUBU: 2702 if (rs != 0 && rt != 0) { 2703 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2704 } else if (rs == 0 && rt != 0) { 2705 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]); 2706 } else if (rs != 0 && rt == 0) { 2707 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2708 } else { 2709 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2710 } 2711 break; 2712 #endif 2713 case OPC_MUL: 2714 if (likely(rs != 0 && rt != 0)) { 2715 tcg_gen_mul_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2716 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 2717 } else { 2718 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2719 } 2720 break; 2721 } 2722 } 2723 2724 /* Conditional move */ 2725 static void gen_cond_move(DisasContext *ctx, uint32_t opc, 2726 int rd, int rs, int rt) 2727 { 2728 TCGv t0, t1, t2; 2729 2730 if (rd == 0) { 2731 /* If no destination, treat it as a NOP. */ 2732 return; 2733 } 2734 2735 t0 = tcg_temp_new(); 2736 gen_load_gpr(t0, rt); 2737 t1 = tcg_constant_tl(0); 2738 t2 = tcg_temp_new(); 2739 gen_load_gpr(t2, rs); 2740 switch (opc) { 2741 case OPC_MOVN: 2742 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]); 2743 break; 2744 case OPC_MOVZ: 2745 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]); 2746 break; 2747 case OPC_SELNEZ: 2748 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, t1); 2749 break; 2750 case OPC_SELEQZ: 2751 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, t1); 2752 break; 2753 } 2754 } 2755 2756 /* Logic */ 2757 static void gen_logic(DisasContext *ctx, uint32_t opc, 2758 int rd, int rs, int rt) 2759 { 2760 if (rd == 0) { 2761 /* If no destination, treat it as a NOP. */ 2762 return; 2763 } 2764 2765 switch (opc) { 2766 case OPC_AND: 2767 if (likely(rs != 0 && rt != 0)) { 2768 tcg_gen_and_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2769 } else { 2770 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2771 } 2772 break; 2773 case OPC_NOR: 2774 if (rs != 0 && rt != 0) { 2775 tcg_gen_nor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2776 } else if (rs == 0 && rt != 0) { 2777 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rt]); 2778 } else if (rs != 0 && rt == 0) { 2779 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rs]); 2780 } else { 2781 tcg_gen_movi_tl(cpu_gpr[rd], ~((target_ulong)0)); 2782 } 2783 break; 2784 case OPC_OR: 2785 if (likely(rs != 0 && rt != 0)) { 2786 tcg_gen_or_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2787 } else if (rs == 0 && rt != 0) { 2788 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); 2789 } else if (rs != 0 && rt == 0) { 2790 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2791 } else { 2792 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2793 } 2794 break; 2795 case OPC_XOR: 2796 if (likely(rs != 0 && rt != 0)) { 2797 tcg_gen_xor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2798 } else if (rs == 0 && rt != 0) { 2799 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); 2800 } else if (rs != 0 && rt == 0) { 2801 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2802 } else { 2803 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2804 } 2805 break; 2806 } 2807 } 2808 2809 /* Set on lower than */ 2810 static void gen_slt(DisasContext *ctx, uint32_t opc, 2811 int rd, int rs, int rt) 2812 { 2813 TCGv t0, t1; 2814 2815 if (rd == 0) { 2816 /* If no destination, treat it as a NOP. */ 2817 return; 2818 } 2819 2820 t0 = tcg_temp_new(); 2821 t1 = tcg_temp_new(); 2822 gen_load_gpr(t0, rs); 2823 gen_load_gpr(t1, rt); 2824 switch (opc) { 2825 case OPC_SLT: 2826 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr[rd], t0, t1); 2827 break; 2828 case OPC_SLTU: 2829 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr[rd], t0, t1); 2830 break; 2831 } 2832 } 2833 2834 /* Shifts */ 2835 static void gen_shift(DisasContext *ctx, uint32_t opc, 2836 int rd, int rs, int rt) 2837 { 2838 TCGv t0, t1; 2839 2840 if (rd == 0) { 2841 /* 2842 * If no destination, treat it as a NOP. 2843 * For add & sub, we must generate the overflow exception when needed. 2844 */ 2845 return; 2846 } 2847 2848 t0 = tcg_temp_new(); 2849 t1 = tcg_temp_new(); 2850 gen_load_gpr(t0, rs); 2851 gen_load_gpr(t1, rt); 2852 switch (opc) { 2853 case OPC_SLLV: 2854 tcg_gen_andi_tl(t0, t0, 0x1f); 2855 tcg_gen_shl_tl(t0, t1, t0); 2856 tcg_gen_ext32s_tl(cpu_gpr[rd], t0); 2857 break; 2858 case OPC_SRAV: 2859 tcg_gen_andi_tl(t0, t0, 0x1f); 2860 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0); 2861 break; 2862 case OPC_SRLV: 2863 tcg_gen_ext32u_tl(t1, t1); 2864 tcg_gen_andi_tl(t0, t0, 0x1f); 2865 tcg_gen_shr_tl(t0, t1, t0); 2866 tcg_gen_ext32s_tl(cpu_gpr[rd], t0); 2867 break; 2868 case OPC_ROTRV: 2869 { 2870 TCGv_i32 t2 = tcg_temp_new_i32(); 2871 TCGv_i32 t3 = tcg_temp_new_i32(); 2872 2873 tcg_gen_trunc_tl_i32(t2, t0); 2874 tcg_gen_trunc_tl_i32(t3, t1); 2875 tcg_gen_andi_i32(t2, t2, 0x1f); 2876 tcg_gen_rotr_i32(t2, t3, t2); 2877 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); 2878 } 2879 break; 2880 #if defined(TARGET_MIPS64) 2881 case OPC_DSLLV: 2882 tcg_gen_andi_tl(t0, t0, 0x3f); 2883 tcg_gen_shl_tl(cpu_gpr[rd], t1, t0); 2884 break; 2885 case OPC_DSRAV: 2886 tcg_gen_andi_tl(t0, t0, 0x3f); 2887 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0); 2888 break; 2889 case OPC_DSRLV: 2890 tcg_gen_andi_tl(t0, t0, 0x3f); 2891 tcg_gen_shr_tl(cpu_gpr[rd], t1, t0); 2892 break; 2893 case OPC_DROTRV: 2894 tcg_gen_andi_tl(t0, t0, 0x3f); 2895 tcg_gen_rotr_tl(cpu_gpr[rd], t1, t0); 2896 break; 2897 #endif 2898 } 2899 } 2900 2901 /* Arithmetic on HI/LO registers */ 2902 static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) 2903 { 2904 if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) { 2905 /* Treat as NOP. */ 2906 return; 2907 } 2908 2909 if (acc != 0) { 2910 check_dsp(ctx); 2911 } 2912 2913 switch (opc) { 2914 case OPC_MFHI: 2915 #if defined(TARGET_MIPS64) 2916 if (acc != 0) { 2917 tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]); 2918 } else 2919 #endif 2920 { 2921 tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[acc]); 2922 } 2923 break; 2924 case OPC_MFLO: 2925 #if defined(TARGET_MIPS64) 2926 if (acc != 0) { 2927 tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]); 2928 } else 2929 #endif 2930 { 2931 tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[acc]); 2932 } 2933 break; 2934 case OPC_MTHI: 2935 if (reg != 0) { 2936 #if defined(TARGET_MIPS64) 2937 if (acc != 0) { 2938 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_gpr[reg]); 2939 } else 2940 #endif 2941 { 2942 tcg_gen_mov_tl(cpu_HI[acc], cpu_gpr[reg]); 2943 } 2944 } else { 2945 tcg_gen_movi_tl(cpu_HI[acc], 0); 2946 } 2947 break; 2948 case OPC_MTLO: 2949 if (reg != 0) { 2950 #if defined(TARGET_MIPS64) 2951 if (acc != 0) { 2952 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_gpr[reg]); 2953 } else 2954 #endif 2955 { 2956 tcg_gen_mov_tl(cpu_LO[acc], cpu_gpr[reg]); 2957 } 2958 } else { 2959 tcg_gen_movi_tl(cpu_LO[acc], 0); 2960 } 2961 break; 2962 } 2963 } 2964 2965 static inline void gen_r6_ld(target_long addr, int reg, int memidx, 2966 MemOp memop) 2967 { 2968 TCGv t0 = tcg_temp_new(); 2969 tcg_gen_qemu_ld_tl(t0, tcg_constant_tl(addr), memidx, memop); 2970 gen_store_gpr(t0, reg); 2971 } 2972 2973 static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc, 2974 int rs) 2975 { 2976 target_long offset; 2977 target_long addr; 2978 2979 switch (MASK_OPC_PCREL_TOP2BITS(opc)) { 2980 case OPC_ADDIUPC: 2981 if (rs != 0) { 2982 offset = sextract32(ctx->opcode << 2, 0, 21); 2983 addr = addr_add(ctx, pc, offset); 2984 tcg_gen_movi_tl(cpu_gpr[rs], addr); 2985 } 2986 break; 2987 case R6_OPC_LWPC: 2988 offset = sextract32(ctx->opcode << 2, 0, 21); 2989 addr = addr_add(ctx, pc, offset); 2990 gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_SL); 2991 break; 2992 #if defined(TARGET_MIPS64) 2993 case OPC_LWUPC: 2994 check_mips_64(ctx); 2995 offset = sextract32(ctx->opcode << 2, 0, 21); 2996 addr = addr_add(ctx, pc, offset); 2997 gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_UL); 2998 break; 2999 #endif 3000 default: 3001 switch (MASK_OPC_PCREL_TOP5BITS(opc)) { 3002 case OPC_AUIPC: 3003 if (rs != 0) { 3004 offset = sextract32(ctx->opcode, 0, 16) << 16; 3005 addr = addr_add(ctx, pc, offset); 3006 tcg_gen_movi_tl(cpu_gpr[rs], addr); 3007 } 3008 break; 3009 case OPC_ALUIPC: 3010 if (rs != 0) { 3011 offset = sextract32(ctx->opcode, 0, 16) << 16; 3012 addr = ~0xFFFF & addr_add(ctx, pc, offset); 3013 tcg_gen_movi_tl(cpu_gpr[rs], addr); 3014 } 3015 break; 3016 #if defined(TARGET_MIPS64) 3017 case R6_OPC_LDPC: /* bits 16 and 17 are part of immediate */ 3018 case R6_OPC_LDPC + (1 << 16): 3019 case R6_OPC_LDPC + (2 << 16): 3020 case R6_OPC_LDPC + (3 << 16): 3021 check_mips_64(ctx); 3022 offset = sextract32(ctx->opcode << 3, 0, 21); 3023 addr = addr_add(ctx, (pc & ~0x7), offset); 3024 gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_UQ); 3025 break; 3026 #endif 3027 default: 3028 MIPS_INVAL("OPC_PCREL"); 3029 gen_reserved_instruction(ctx); 3030 break; 3031 } 3032 break; 3033 } 3034 } 3035 3036 static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) 3037 { 3038 TCGv t0, t1; 3039 3040 if (rd == 0) { 3041 /* Treat as NOP. */ 3042 return; 3043 } 3044 3045 t0 = tcg_temp_new(); 3046 t1 = tcg_temp_new(); 3047 3048 gen_load_gpr(t0, rs); 3049 gen_load_gpr(t1, rt); 3050 3051 switch (opc) { 3052 case R6_OPC_DIV: 3053 { 3054 TCGv t2 = tcg_temp_new(); 3055 TCGv t3 = tcg_temp_new(); 3056 tcg_gen_ext32s_tl(t0, t0); 3057 tcg_gen_ext32s_tl(t1, t1); 3058 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); 3059 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); 3060 tcg_gen_and_tl(t2, t2, t3); 3061 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3062 tcg_gen_or_tl(t2, t2, t3); 3063 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1); 3064 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); 3065 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3066 } 3067 break; 3068 case R6_OPC_MOD: 3069 { 3070 TCGv t2 = tcg_temp_new(); 3071 TCGv t3 = tcg_temp_new(); 3072 tcg_gen_ext32s_tl(t0, t0); 3073 tcg_gen_ext32s_tl(t1, t1); 3074 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); 3075 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); 3076 tcg_gen_and_tl(t2, t2, t3); 3077 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3078 tcg_gen_or_tl(t2, t2, t3); 3079 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1); 3080 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); 3081 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3082 } 3083 break; 3084 case R6_OPC_DIVU: 3085 { 3086 tcg_gen_ext32u_tl(t0, t0); 3087 tcg_gen_ext32u_tl(t1, t1); 3088 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, 3089 tcg_constant_tl(0), tcg_constant_tl(1), t1); 3090 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); 3091 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3092 } 3093 break; 3094 case R6_OPC_MODU: 3095 { 3096 tcg_gen_ext32u_tl(t0, t0); 3097 tcg_gen_ext32u_tl(t1, t1); 3098 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, 3099 tcg_constant_tl(0), tcg_constant_tl(1), t1); 3100 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); 3101 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3102 } 3103 break; 3104 case R6_OPC_MUL: 3105 { 3106 TCGv_i32 t2 = tcg_temp_new_i32(); 3107 TCGv_i32 t3 = tcg_temp_new_i32(); 3108 tcg_gen_trunc_tl_i32(t2, t0); 3109 tcg_gen_trunc_tl_i32(t3, t1); 3110 tcg_gen_mul_i32(t2, t2, t3); 3111 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); 3112 } 3113 break; 3114 case R6_OPC_MUH: 3115 { 3116 TCGv_i32 t2 = tcg_temp_new_i32(); 3117 TCGv_i32 t3 = tcg_temp_new_i32(); 3118 tcg_gen_trunc_tl_i32(t2, t0); 3119 tcg_gen_trunc_tl_i32(t3, t1); 3120 tcg_gen_muls2_i32(t2, t3, t2, t3); 3121 tcg_gen_ext_i32_tl(cpu_gpr[rd], t3); 3122 } 3123 break; 3124 case R6_OPC_MULU: 3125 { 3126 TCGv_i32 t2 = tcg_temp_new_i32(); 3127 TCGv_i32 t3 = tcg_temp_new_i32(); 3128 tcg_gen_trunc_tl_i32(t2, t0); 3129 tcg_gen_trunc_tl_i32(t3, t1); 3130 tcg_gen_mul_i32(t2, t2, t3); 3131 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); 3132 } 3133 break; 3134 case R6_OPC_MUHU: 3135 { 3136 TCGv_i32 t2 = tcg_temp_new_i32(); 3137 TCGv_i32 t3 = tcg_temp_new_i32(); 3138 tcg_gen_trunc_tl_i32(t2, t0); 3139 tcg_gen_trunc_tl_i32(t3, t1); 3140 tcg_gen_mulu2_i32(t2, t3, t2, t3); 3141 tcg_gen_ext_i32_tl(cpu_gpr[rd], t3); 3142 } 3143 break; 3144 #if defined(TARGET_MIPS64) 3145 case R6_OPC_DDIV: 3146 { 3147 TCGv t2 = tcg_temp_new(); 3148 TCGv t3 = tcg_temp_new(); 3149 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); 3150 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); 3151 tcg_gen_and_tl(t2, t2, t3); 3152 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3153 tcg_gen_or_tl(t2, t2, t3); 3154 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1); 3155 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); 3156 } 3157 break; 3158 case R6_OPC_DMOD: 3159 { 3160 TCGv t2 = tcg_temp_new(); 3161 TCGv t3 = tcg_temp_new(); 3162 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); 3163 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); 3164 tcg_gen_and_tl(t2, t2, t3); 3165 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3166 tcg_gen_or_tl(t2, t2, t3); 3167 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1); 3168 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); 3169 } 3170 break; 3171 case R6_OPC_DDIVU: 3172 { 3173 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, 3174 tcg_constant_tl(0), tcg_constant_tl(1), t1); 3175 tcg_gen_divu_i64(cpu_gpr[rd], t0, t1); 3176 } 3177 break; 3178 case R6_OPC_DMODU: 3179 { 3180 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, 3181 tcg_constant_tl(0), tcg_constant_tl(1), t1); 3182 tcg_gen_remu_i64(cpu_gpr[rd], t0, t1); 3183 } 3184 break; 3185 case R6_OPC_DMUL: 3186 tcg_gen_mul_i64(cpu_gpr[rd], t0, t1); 3187 break; 3188 case R6_OPC_DMUH: 3189 { 3190 TCGv t2 = tcg_temp_new(); 3191 tcg_gen_muls2_i64(t2, cpu_gpr[rd], t0, t1); 3192 } 3193 break; 3194 case R6_OPC_DMULU: 3195 tcg_gen_mul_i64(cpu_gpr[rd], t0, t1); 3196 break; 3197 case R6_OPC_DMUHU: 3198 { 3199 TCGv t2 = tcg_temp_new(); 3200 tcg_gen_mulu2_i64(t2, cpu_gpr[rd], t0, t1); 3201 } 3202 break; 3203 #endif 3204 default: 3205 MIPS_INVAL("r6 mul/div"); 3206 gen_reserved_instruction(ctx); 3207 break; 3208 } 3209 } 3210 3211 #if defined(TARGET_MIPS64) 3212 static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt) 3213 { 3214 TCGv t0, t1; 3215 3216 t0 = tcg_temp_new(); 3217 t1 = tcg_temp_new(); 3218 3219 gen_load_gpr(t0, rs); 3220 gen_load_gpr(t1, rt); 3221 3222 switch (opc) { 3223 case MMI_OPC_DIV1: 3224 { 3225 TCGv t2 = tcg_temp_new(); 3226 TCGv t3 = tcg_temp_new(); 3227 tcg_gen_ext32s_tl(t0, t0); 3228 tcg_gen_ext32s_tl(t1, t1); 3229 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); 3230 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); 3231 tcg_gen_and_tl(t2, t2, t3); 3232 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3233 tcg_gen_or_tl(t2, t2, t3); 3234 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1); 3235 tcg_gen_div_tl(cpu_LO[1], t0, t1); 3236 tcg_gen_rem_tl(cpu_HI[1], t0, t1); 3237 tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]); 3238 tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]); 3239 } 3240 break; 3241 case MMI_OPC_DIVU1: 3242 { 3243 TCGv t2 = tcg_constant_tl(0); 3244 TCGv t3 = tcg_constant_tl(1); 3245 tcg_gen_ext32u_tl(t0, t0); 3246 tcg_gen_ext32u_tl(t1, t1); 3247 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3248 tcg_gen_divu_tl(cpu_LO[1], t0, t1); 3249 tcg_gen_remu_tl(cpu_HI[1], t0, t1); 3250 tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]); 3251 tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]); 3252 } 3253 break; 3254 default: 3255 MIPS_INVAL("div1 TX79"); 3256 gen_reserved_instruction(ctx); 3257 break; 3258 } 3259 } 3260 #endif 3261 3262 static void gen_muldiv(DisasContext *ctx, uint32_t opc, 3263 int acc, int rs, int rt) 3264 { 3265 TCGv t0, t1; 3266 3267 t0 = tcg_temp_new(); 3268 t1 = tcg_temp_new(); 3269 3270 gen_load_gpr(t0, rs); 3271 gen_load_gpr(t1, rt); 3272 3273 if (acc != 0) { 3274 check_dsp(ctx); 3275 } 3276 3277 switch (opc) { 3278 case OPC_DIV: 3279 { 3280 TCGv t2 = tcg_temp_new(); 3281 TCGv t3 = tcg_temp_new(); 3282 tcg_gen_ext32s_tl(t0, t0); 3283 tcg_gen_ext32s_tl(t1, t1); 3284 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); 3285 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); 3286 tcg_gen_and_tl(t2, t2, t3); 3287 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3288 tcg_gen_or_tl(t2, t2, t3); 3289 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1); 3290 tcg_gen_div_tl(cpu_LO[acc], t0, t1); 3291 tcg_gen_rem_tl(cpu_HI[acc], t0, t1); 3292 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]); 3293 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]); 3294 } 3295 break; 3296 case OPC_DIVU: 3297 { 3298 TCGv t2 = tcg_constant_tl(0); 3299 TCGv t3 = tcg_constant_tl(1); 3300 tcg_gen_ext32u_tl(t0, t0); 3301 tcg_gen_ext32u_tl(t1, t1); 3302 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3303 tcg_gen_divu_tl(cpu_LO[acc], t0, t1); 3304 tcg_gen_remu_tl(cpu_HI[acc], t0, t1); 3305 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]); 3306 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]); 3307 } 3308 break; 3309 case OPC_MULT: 3310 { 3311 TCGv_i32 t2 = tcg_temp_new_i32(); 3312 TCGv_i32 t3 = tcg_temp_new_i32(); 3313 tcg_gen_trunc_tl_i32(t2, t0); 3314 tcg_gen_trunc_tl_i32(t3, t1); 3315 tcg_gen_muls2_i32(t2, t3, t2, t3); 3316 tcg_gen_ext_i32_tl(cpu_LO[acc], t2); 3317 tcg_gen_ext_i32_tl(cpu_HI[acc], t3); 3318 } 3319 break; 3320 case OPC_MULTU: 3321 { 3322 TCGv_i32 t2 = tcg_temp_new_i32(); 3323 TCGv_i32 t3 = tcg_temp_new_i32(); 3324 tcg_gen_trunc_tl_i32(t2, t0); 3325 tcg_gen_trunc_tl_i32(t3, t1); 3326 tcg_gen_mulu2_i32(t2, t3, t2, t3); 3327 tcg_gen_ext_i32_tl(cpu_LO[acc], t2); 3328 tcg_gen_ext_i32_tl(cpu_HI[acc], t3); 3329 } 3330 break; 3331 #if defined(TARGET_MIPS64) 3332 case OPC_DDIV: 3333 { 3334 TCGv t2 = tcg_temp_new(); 3335 TCGv t3 = tcg_temp_new(); 3336 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); 3337 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); 3338 tcg_gen_and_tl(t2, t2, t3); 3339 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3340 tcg_gen_or_tl(t2, t2, t3); 3341 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1); 3342 tcg_gen_div_tl(cpu_LO[acc], t0, t1); 3343 tcg_gen_rem_tl(cpu_HI[acc], t0, t1); 3344 } 3345 break; 3346 case OPC_DDIVU: 3347 { 3348 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, 3349 tcg_constant_tl(0), tcg_constant_tl(1), t1); 3350 tcg_gen_divu_i64(cpu_LO[acc], t0, t1); 3351 tcg_gen_remu_i64(cpu_HI[acc], t0, t1); 3352 } 3353 break; 3354 case OPC_DMULT: 3355 tcg_gen_muls2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1); 3356 break; 3357 case OPC_DMULTU: 3358 tcg_gen_mulu2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1); 3359 break; 3360 #endif 3361 case OPC_MADD: 3362 { 3363 TCGv_i64 t2 = tcg_temp_new_i64(); 3364 TCGv_i64 t3 = tcg_temp_new_i64(); 3365 3366 tcg_gen_ext_tl_i64(t2, t0); 3367 tcg_gen_ext_tl_i64(t3, t1); 3368 tcg_gen_mul_i64(t2, t2, t3); 3369 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3370 tcg_gen_add_i64(t2, t2, t3); 3371 gen_move_low32(cpu_LO[acc], t2); 3372 gen_move_high32(cpu_HI[acc], t2); 3373 } 3374 break; 3375 case OPC_MADDU: 3376 { 3377 TCGv_i64 t2 = tcg_temp_new_i64(); 3378 TCGv_i64 t3 = tcg_temp_new_i64(); 3379 3380 tcg_gen_ext32u_tl(t0, t0); 3381 tcg_gen_ext32u_tl(t1, t1); 3382 tcg_gen_extu_tl_i64(t2, t0); 3383 tcg_gen_extu_tl_i64(t3, t1); 3384 tcg_gen_mul_i64(t2, t2, t3); 3385 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3386 tcg_gen_add_i64(t2, t2, t3); 3387 gen_move_low32(cpu_LO[acc], t2); 3388 gen_move_high32(cpu_HI[acc], t2); 3389 } 3390 break; 3391 case OPC_MSUB: 3392 { 3393 TCGv_i64 t2 = tcg_temp_new_i64(); 3394 TCGv_i64 t3 = tcg_temp_new_i64(); 3395 3396 tcg_gen_ext_tl_i64(t2, t0); 3397 tcg_gen_ext_tl_i64(t3, t1); 3398 tcg_gen_mul_i64(t2, t2, t3); 3399 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3400 tcg_gen_sub_i64(t2, t3, t2); 3401 gen_move_low32(cpu_LO[acc], t2); 3402 gen_move_high32(cpu_HI[acc], t2); 3403 } 3404 break; 3405 case OPC_MSUBU: 3406 { 3407 TCGv_i64 t2 = tcg_temp_new_i64(); 3408 TCGv_i64 t3 = tcg_temp_new_i64(); 3409 3410 tcg_gen_ext32u_tl(t0, t0); 3411 tcg_gen_ext32u_tl(t1, t1); 3412 tcg_gen_extu_tl_i64(t2, t0); 3413 tcg_gen_extu_tl_i64(t3, t1); 3414 tcg_gen_mul_i64(t2, t2, t3); 3415 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3416 tcg_gen_sub_i64(t2, t3, t2); 3417 gen_move_low32(cpu_LO[acc], t2); 3418 gen_move_high32(cpu_HI[acc], t2); 3419 } 3420 break; 3421 default: 3422 MIPS_INVAL("mul/div"); 3423 gen_reserved_instruction(ctx); 3424 break; 3425 } 3426 } 3427 3428 /* 3429 * These MULT[U] and MADD[U] instructions implemented in for example 3430 * the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core 3431 * architectures are special three-operand variants with the syntax 3432 * 3433 * MULT[U][1] rd, rs, rt 3434 * 3435 * such that 3436 * 3437 * (rd, LO, HI) <- rs * rt 3438 * 3439 * and 3440 * 3441 * MADD[U][1] rd, rs, rt 3442 * 3443 * such that 3444 * 3445 * (rd, LO, HI) <- (LO, HI) + rs * rt 3446 * 3447 * where the low-order 32-bits of the result is placed into both the 3448 * GPR rd and the special register LO. The high-order 32-bits of the 3449 * result is placed into the special register HI. 3450 * 3451 * If the GPR rd is omitted in assembly language, it is taken to be 0, 3452 * which is the zero register that always reads as 0. 3453 */ 3454 static void gen_mul_txx9(DisasContext *ctx, uint32_t opc, 3455 int rd, int rs, int rt) 3456 { 3457 TCGv t0 = tcg_temp_new(); 3458 TCGv t1 = tcg_temp_new(); 3459 int acc = 0; 3460 3461 gen_load_gpr(t0, rs); 3462 gen_load_gpr(t1, rt); 3463 3464 switch (opc) { 3465 case MMI_OPC_MULT1: 3466 acc = 1; 3467 /* Fall through */ 3468 case OPC_MULT: 3469 { 3470 TCGv_i32 t2 = tcg_temp_new_i32(); 3471 TCGv_i32 t3 = tcg_temp_new_i32(); 3472 tcg_gen_trunc_tl_i32(t2, t0); 3473 tcg_gen_trunc_tl_i32(t3, t1); 3474 tcg_gen_muls2_i32(t2, t3, t2, t3); 3475 if (rd) { 3476 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); 3477 } 3478 tcg_gen_ext_i32_tl(cpu_LO[acc], t2); 3479 tcg_gen_ext_i32_tl(cpu_HI[acc], t3); 3480 } 3481 break; 3482 case MMI_OPC_MULTU1: 3483 acc = 1; 3484 /* Fall through */ 3485 case OPC_MULTU: 3486 { 3487 TCGv_i32 t2 = tcg_temp_new_i32(); 3488 TCGv_i32 t3 = tcg_temp_new_i32(); 3489 tcg_gen_trunc_tl_i32(t2, t0); 3490 tcg_gen_trunc_tl_i32(t3, t1); 3491 tcg_gen_mulu2_i32(t2, t3, t2, t3); 3492 if (rd) { 3493 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); 3494 } 3495 tcg_gen_ext_i32_tl(cpu_LO[acc], t2); 3496 tcg_gen_ext_i32_tl(cpu_HI[acc], t3); 3497 } 3498 break; 3499 case MMI_OPC_MADD1: 3500 acc = 1; 3501 /* Fall through */ 3502 case MMI_OPC_MADD: 3503 { 3504 TCGv_i64 t2 = tcg_temp_new_i64(); 3505 TCGv_i64 t3 = tcg_temp_new_i64(); 3506 3507 tcg_gen_ext_tl_i64(t2, t0); 3508 tcg_gen_ext_tl_i64(t3, t1); 3509 tcg_gen_mul_i64(t2, t2, t3); 3510 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3511 tcg_gen_add_i64(t2, t2, t3); 3512 gen_move_low32(cpu_LO[acc], t2); 3513 gen_move_high32(cpu_HI[acc], t2); 3514 if (rd) { 3515 gen_move_low32(cpu_gpr[rd], t2); 3516 } 3517 } 3518 break; 3519 case MMI_OPC_MADDU1: 3520 acc = 1; 3521 /* Fall through */ 3522 case MMI_OPC_MADDU: 3523 { 3524 TCGv_i64 t2 = tcg_temp_new_i64(); 3525 TCGv_i64 t3 = tcg_temp_new_i64(); 3526 3527 tcg_gen_ext32u_tl(t0, t0); 3528 tcg_gen_ext32u_tl(t1, t1); 3529 tcg_gen_extu_tl_i64(t2, t0); 3530 tcg_gen_extu_tl_i64(t3, t1); 3531 tcg_gen_mul_i64(t2, t2, t3); 3532 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3533 tcg_gen_add_i64(t2, t2, t3); 3534 gen_move_low32(cpu_LO[acc], t2); 3535 gen_move_high32(cpu_HI[acc], t2); 3536 if (rd) { 3537 gen_move_low32(cpu_gpr[rd], t2); 3538 } 3539 } 3540 break; 3541 default: 3542 MIPS_INVAL("mul/madd TXx9"); 3543 gen_reserved_instruction(ctx); 3544 break; 3545 } 3546 } 3547 3548 static void gen_cl(DisasContext *ctx, uint32_t opc, 3549 int rd, int rs) 3550 { 3551 TCGv t0; 3552 3553 if (rd == 0) { 3554 /* Treat as NOP. */ 3555 return; 3556 } 3557 t0 = cpu_gpr[rd]; 3558 gen_load_gpr(t0, rs); 3559 3560 switch (opc) { 3561 case OPC_CLO: 3562 case R6_OPC_CLO: 3563 #if defined(TARGET_MIPS64) 3564 case OPC_DCLO: 3565 case R6_OPC_DCLO: 3566 #endif 3567 tcg_gen_not_tl(t0, t0); 3568 break; 3569 } 3570 3571 switch (opc) { 3572 case OPC_CLO: 3573 case R6_OPC_CLO: 3574 case OPC_CLZ: 3575 case R6_OPC_CLZ: 3576 tcg_gen_ext32u_tl(t0, t0); 3577 tcg_gen_clzi_tl(t0, t0, TARGET_LONG_BITS); 3578 tcg_gen_subi_tl(t0, t0, TARGET_LONG_BITS - 32); 3579 break; 3580 #if defined(TARGET_MIPS64) 3581 case OPC_DCLO: 3582 case R6_OPC_DCLO: 3583 case OPC_DCLZ: 3584 case R6_OPC_DCLZ: 3585 tcg_gen_clzi_i64(t0, t0, 64); 3586 break; 3587 #endif 3588 } 3589 } 3590 3591 /* Godson integer instructions */ 3592 static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, 3593 int rd, int rs, int rt) 3594 { 3595 TCGv t0, t1; 3596 3597 if (rd == 0) { 3598 /* Treat as NOP. */ 3599 return; 3600 } 3601 3602 t0 = tcg_temp_new(); 3603 t1 = tcg_temp_new(); 3604 gen_load_gpr(t0, rs); 3605 gen_load_gpr(t1, rt); 3606 3607 switch (opc) { 3608 case OPC_MULT_G_2E: 3609 case OPC_MULT_G_2F: 3610 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); 3611 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3612 break; 3613 case OPC_MULTU_G_2E: 3614 case OPC_MULTU_G_2F: 3615 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); 3616 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3617 break; 3618 case OPC_DIV_G_2E: 3619 case OPC_DIV_G_2F: 3620 { 3621 TCGLabel *l1 = gen_new_label(); 3622 TCGLabel *l2 = gen_new_label(); 3623 TCGLabel *l3 = gen_new_label(); 3624 tcg_gen_ext32s_tl(t0, t0); 3625 tcg_gen_ext32s_tl(t1, t1); 3626 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3627 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3628 tcg_gen_br(l3); 3629 gen_set_label(l1); 3630 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2); 3631 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2); 3632 tcg_gen_mov_tl(cpu_gpr[rd], t0); 3633 tcg_gen_br(l3); 3634 gen_set_label(l2); 3635 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); 3636 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3637 gen_set_label(l3); 3638 } 3639 break; 3640 case OPC_DIVU_G_2E: 3641 case OPC_DIVU_G_2F: 3642 { 3643 TCGLabel *l1 = gen_new_label(); 3644 TCGLabel *l2 = gen_new_label(); 3645 tcg_gen_ext32u_tl(t0, t0); 3646 tcg_gen_ext32u_tl(t1, t1); 3647 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3648 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3649 tcg_gen_br(l2); 3650 gen_set_label(l1); 3651 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); 3652 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3653 gen_set_label(l2); 3654 } 3655 break; 3656 case OPC_MOD_G_2E: 3657 case OPC_MOD_G_2F: 3658 { 3659 TCGLabel *l1 = gen_new_label(); 3660 TCGLabel *l2 = gen_new_label(); 3661 TCGLabel *l3 = gen_new_label(); 3662 tcg_gen_ext32u_tl(t0, t0); 3663 tcg_gen_ext32u_tl(t1, t1); 3664 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 3665 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2); 3666 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2); 3667 gen_set_label(l1); 3668 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3669 tcg_gen_br(l3); 3670 gen_set_label(l2); 3671 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); 3672 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3673 gen_set_label(l3); 3674 } 3675 break; 3676 case OPC_MODU_G_2E: 3677 case OPC_MODU_G_2F: 3678 { 3679 TCGLabel *l1 = gen_new_label(); 3680 TCGLabel *l2 = gen_new_label(); 3681 tcg_gen_ext32u_tl(t0, t0); 3682 tcg_gen_ext32u_tl(t1, t1); 3683 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3684 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3685 tcg_gen_br(l2); 3686 gen_set_label(l1); 3687 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); 3688 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3689 gen_set_label(l2); 3690 } 3691 break; 3692 #if defined(TARGET_MIPS64) 3693 case OPC_DMULT_G_2E: 3694 case OPC_DMULT_G_2F: 3695 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); 3696 break; 3697 case OPC_DMULTU_G_2E: 3698 case OPC_DMULTU_G_2F: 3699 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); 3700 break; 3701 case OPC_DDIV_G_2E: 3702 case OPC_DDIV_G_2F: 3703 { 3704 TCGLabel *l1 = gen_new_label(); 3705 TCGLabel *l2 = gen_new_label(); 3706 TCGLabel *l3 = gen_new_label(); 3707 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3708 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3709 tcg_gen_br(l3); 3710 gen_set_label(l1); 3711 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); 3712 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); 3713 tcg_gen_mov_tl(cpu_gpr[rd], t0); 3714 tcg_gen_br(l3); 3715 gen_set_label(l2); 3716 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); 3717 gen_set_label(l3); 3718 } 3719 break; 3720 case OPC_DDIVU_G_2E: 3721 case OPC_DDIVU_G_2F: 3722 { 3723 TCGLabel *l1 = gen_new_label(); 3724 TCGLabel *l2 = gen_new_label(); 3725 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3726 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3727 tcg_gen_br(l2); 3728 gen_set_label(l1); 3729 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); 3730 gen_set_label(l2); 3731 } 3732 break; 3733 case OPC_DMOD_G_2E: 3734 case OPC_DMOD_G_2F: 3735 { 3736 TCGLabel *l1 = gen_new_label(); 3737 TCGLabel *l2 = gen_new_label(); 3738 TCGLabel *l3 = gen_new_label(); 3739 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 3740 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); 3741 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); 3742 gen_set_label(l1); 3743 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3744 tcg_gen_br(l3); 3745 gen_set_label(l2); 3746 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); 3747 gen_set_label(l3); 3748 } 3749 break; 3750 case OPC_DMODU_G_2E: 3751 case OPC_DMODU_G_2F: 3752 { 3753 TCGLabel *l1 = gen_new_label(); 3754 TCGLabel *l2 = gen_new_label(); 3755 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3756 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3757 tcg_gen_br(l2); 3758 gen_set_label(l1); 3759 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); 3760 gen_set_label(l2); 3761 } 3762 break; 3763 #endif 3764 } 3765 } 3766 3767 /* Loongson multimedia instructions */ 3768 static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) 3769 { 3770 uint32_t opc, shift_max; 3771 TCGv_i64 t0, t1; 3772 TCGCond cond; 3773 3774 opc = MASK_LMMI(ctx->opcode); 3775 check_cp1_enabled(ctx); 3776 3777 t0 = tcg_temp_new_i64(); 3778 t1 = tcg_temp_new_i64(); 3779 gen_load_fpr64(ctx, t0, rs); 3780 gen_load_fpr64(ctx, t1, rt); 3781 3782 switch (opc) { 3783 case OPC_PADDSH: 3784 gen_helper_paddsh(t0, t0, t1); 3785 break; 3786 case OPC_PADDUSH: 3787 gen_helper_paddush(t0, t0, t1); 3788 break; 3789 case OPC_PADDH: 3790 gen_helper_paddh(t0, t0, t1); 3791 break; 3792 case OPC_PADDW: 3793 gen_helper_paddw(t0, t0, t1); 3794 break; 3795 case OPC_PADDSB: 3796 gen_helper_paddsb(t0, t0, t1); 3797 break; 3798 case OPC_PADDUSB: 3799 gen_helper_paddusb(t0, t0, t1); 3800 break; 3801 case OPC_PADDB: 3802 gen_helper_paddb(t0, t0, t1); 3803 break; 3804 3805 case OPC_PSUBSH: 3806 gen_helper_psubsh(t0, t0, t1); 3807 break; 3808 case OPC_PSUBUSH: 3809 gen_helper_psubush(t0, t0, t1); 3810 break; 3811 case OPC_PSUBH: 3812 gen_helper_psubh(t0, t0, t1); 3813 break; 3814 case OPC_PSUBW: 3815 gen_helper_psubw(t0, t0, t1); 3816 break; 3817 case OPC_PSUBSB: 3818 gen_helper_psubsb(t0, t0, t1); 3819 break; 3820 case OPC_PSUBUSB: 3821 gen_helper_psubusb(t0, t0, t1); 3822 break; 3823 case OPC_PSUBB: 3824 gen_helper_psubb(t0, t0, t1); 3825 break; 3826 3827 case OPC_PSHUFH: 3828 gen_helper_pshufh(t0, t0, t1); 3829 break; 3830 case OPC_PACKSSWH: 3831 gen_helper_packsswh(t0, t0, t1); 3832 break; 3833 case OPC_PACKSSHB: 3834 gen_helper_packsshb(t0, t0, t1); 3835 break; 3836 case OPC_PACKUSHB: 3837 gen_helper_packushb(t0, t0, t1); 3838 break; 3839 3840 case OPC_PUNPCKLHW: 3841 gen_helper_punpcklhw(t0, t0, t1); 3842 break; 3843 case OPC_PUNPCKHHW: 3844 gen_helper_punpckhhw(t0, t0, t1); 3845 break; 3846 case OPC_PUNPCKLBH: 3847 gen_helper_punpcklbh(t0, t0, t1); 3848 break; 3849 case OPC_PUNPCKHBH: 3850 gen_helper_punpckhbh(t0, t0, t1); 3851 break; 3852 case OPC_PUNPCKLWD: 3853 gen_helper_punpcklwd(t0, t0, t1); 3854 break; 3855 case OPC_PUNPCKHWD: 3856 gen_helper_punpckhwd(t0, t0, t1); 3857 break; 3858 3859 case OPC_PAVGH: 3860 gen_helper_pavgh(t0, t0, t1); 3861 break; 3862 case OPC_PAVGB: 3863 gen_helper_pavgb(t0, t0, t1); 3864 break; 3865 case OPC_PMAXSH: 3866 gen_helper_pmaxsh(t0, t0, t1); 3867 break; 3868 case OPC_PMINSH: 3869 gen_helper_pminsh(t0, t0, t1); 3870 break; 3871 case OPC_PMAXUB: 3872 gen_helper_pmaxub(t0, t0, t1); 3873 break; 3874 case OPC_PMINUB: 3875 gen_helper_pminub(t0, t0, t1); 3876 break; 3877 3878 case OPC_PCMPEQW: 3879 gen_helper_pcmpeqw(t0, t0, t1); 3880 break; 3881 case OPC_PCMPGTW: 3882 gen_helper_pcmpgtw(t0, t0, t1); 3883 break; 3884 case OPC_PCMPEQH: 3885 gen_helper_pcmpeqh(t0, t0, t1); 3886 break; 3887 case OPC_PCMPGTH: 3888 gen_helper_pcmpgth(t0, t0, t1); 3889 break; 3890 case OPC_PCMPEQB: 3891 gen_helper_pcmpeqb(t0, t0, t1); 3892 break; 3893 case OPC_PCMPGTB: 3894 gen_helper_pcmpgtb(t0, t0, t1); 3895 break; 3896 3897 case OPC_PSLLW: 3898 gen_helper_psllw(t0, t0, t1); 3899 break; 3900 case OPC_PSLLH: 3901 gen_helper_psllh(t0, t0, t1); 3902 break; 3903 case OPC_PSRLW: 3904 gen_helper_psrlw(t0, t0, t1); 3905 break; 3906 case OPC_PSRLH: 3907 gen_helper_psrlh(t0, t0, t1); 3908 break; 3909 case OPC_PSRAW: 3910 gen_helper_psraw(t0, t0, t1); 3911 break; 3912 case OPC_PSRAH: 3913 gen_helper_psrah(t0, t0, t1); 3914 break; 3915 3916 case OPC_PMULLH: 3917 gen_helper_pmullh(t0, t0, t1); 3918 break; 3919 case OPC_PMULHH: 3920 gen_helper_pmulhh(t0, t0, t1); 3921 break; 3922 case OPC_PMULHUH: 3923 gen_helper_pmulhuh(t0, t0, t1); 3924 break; 3925 case OPC_PMADDHW: 3926 gen_helper_pmaddhw(t0, t0, t1); 3927 break; 3928 3929 case OPC_PASUBUB: 3930 gen_helper_pasubub(t0, t0, t1); 3931 break; 3932 case OPC_BIADD: 3933 gen_helper_biadd(t0, t0); 3934 break; 3935 case OPC_PMOVMSKB: 3936 gen_helper_pmovmskb(t0, t0); 3937 break; 3938 3939 case OPC_PADDD: 3940 tcg_gen_add_i64(t0, t0, t1); 3941 break; 3942 case OPC_PSUBD: 3943 tcg_gen_sub_i64(t0, t0, t1); 3944 break; 3945 case OPC_XOR_CP2: 3946 tcg_gen_xor_i64(t0, t0, t1); 3947 break; 3948 case OPC_NOR_CP2: 3949 tcg_gen_nor_i64(t0, t0, t1); 3950 break; 3951 case OPC_AND_CP2: 3952 tcg_gen_and_i64(t0, t0, t1); 3953 break; 3954 case OPC_OR_CP2: 3955 tcg_gen_or_i64(t0, t0, t1); 3956 break; 3957 3958 case OPC_PANDN: 3959 tcg_gen_andc_i64(t0, t1, t0); 3960 break; 3961 3962 case OPC_PINSRH_0: 3963 tcg_gen_deposit_i64(t0, t0, t1, 0, 16); 3964 break; 3965 case OPC_PINSRH_1: 3966 tcg_gen_deposit_i64(t0, t0, t1, 16, 16); 3967 break; 3968 case OPC_PINSRH_2: 3969 tcg_gen_deposit_i64(t0, t0, t1, 32, 16); 3970 break; 3971 case OPC_PINSRH_3: 3972 tcg_gen_deposit_i64(t0, t0, t1, 48, 16); 3973 break; 3974 3975 case OPC_PEXTRH: 3976 tcg_gen_andi_i64(t1, t1, 3); 3977 tcg_gen_shli_i64(t1, t1, 4); 3978 tcg_gen_shr_i64(t0, t0, t1); 3979 tcg_gen_ext16u_i64(t0, t0); 3980 break; 3981 3982 case OPC_ADDU_CP2: 3983 tcg_gen_add_i64(t0, t0, t1); 3984 tcg_gen_ext32s_i64(t0, t0); 3985 break; 3986 case OPC_SUBU_CP2: 3987 tcg_gen_sub_i64(t0, t0, t1); 3988 tcg_gen_ext32s_i64(t0, t0); 3989 break; 3990 3991 case OPC_SLL_CP2: 3992 shift_max = 32; 3993 goto do_shift; 3994 case OPC_SRL_CP2: 3995 shift_max = 32; 3996 goto do_shift; 3997 case OPC_SRA_CP2: 3998 shift_max = 32; 3999 goto do_shift; 4000 case OPC_DSLL_CP2: 4001 shift_max = 64; 4002 goto do_shift; 4003 case OPC_DSRL_CP2: 4004 shift_max = 64; 4005 goto do_shift; 4006 case OPC_DSRA_CP2: 4007 shift_max = 64; 4008 goto do_shift; 4009 do_shift: 4010 /* Make sure shift count isn't TCG undefined behaviour. */ 4011 tcg_gen_andi_i64(t1, t1, shift_max - 1); 4012 4013 switch (opc) { 4014 case OPC_SLL_CP2: 4015 case OPC_DSLL_CP2: 4016 tcg_gen_shl_i64(t0, t0, t1); 4017 break; 4018 case OPC_SRA_CP2: 4019 case OPC_DSRA_CP2: 4020 /* 4021 * Since SRA is UndefinedResult without sign-extended inputs, 4022 * we can treat SRA and DSRA the same. 4023 */ 4024 tcg_gen_sar_i64(t0, t0, t1); 4025 break; 4026 case OPC_SRL_CP2: 4027 /* We want to shift in zeros for SRL; zero-extend first. */ 4028 tcg_gen_ext32u_i64(t0, t0); 4029 /* FALLTHRU */ 4030 case OPC_DSRL_CP2: 4031 tcg_gen_shr_i64(t0, t0, t1); 4032 break; 4033 } 4034 4035 if (shift_max == 32) { 4036 tcg_gen_ext32s_i64(t0, t0); 4037 } 4038 4039 /* Shifts larger than MAX produce zero. */ 4040 tcg_gen_setcondi_i64(TCG_COND_LTU, t1, t1, shift_max); 4041 tcg_gen_neg_i64(t1, t1); 4042 tcg_gen_and_i64(t0, t0, t1); 4043 break; 4044 4045 case OPC_ADD_CP2: 4046 case OPC_DADD_CP2: 4047 { 4048 TCGv_i64 t2 = tcg_temp_new_i64(); 4049 TCGLabel *lab = gen_new_label(); 4050 4051 tcg_gen_mov_i64(t2, t0); 4052 tcg_gen_add_i64(t0, t1, t2); 4053 if (opc == OPC_ADD_CP2) { 4054 tcg_gen_ext32s_i64(t0, t0); 4055 } 4056 tcg_gen_xor_i64(t1, t1, t2); 4057 tcg_gen_xor_i64(t2, t2, t0); 4058 tcg_gen_andc_i64(t1, t2, t1); 4059 tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab); 4060 generate_exception(ctx, EXCP_OVERFLOW); 4061 gen_set_label(lab); 4062 break; 4063 } 4064 4065 case OPC_SUB_CP2: 4066 case OPC_DSUB_CP2: 4067 { 4068 TCGv_i64 t2 = tcg_temp_new_i64(); 4069 TCGLabel *lab = gen_new_label(); 4070 4071 tcg_gen_mov_i64(t2, t0); 4072 tcg_gen_sub_i64(t0, t1, t2); 4073 if (opc == OPC_SUB_CP2) { 4074 tcg_gen_ext32s_i64(t0, t0); 4075 } 4076 tcg_gen_xor_i64(t1, t1, t2); 4077 tcg_gen_xor_i64(t2, t2, t0); 4078 tcg_gen_and_i64(t1, t1, t2); 4079 tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab); 4080 generate_exception(ctx, EXCP_OVERFLOW); 4081 gen_set_label(lab); 4082 break; 4083 } 4084 4085 case OPC_PMULUW: 4086 tcg_gen_ext32u_i64(t0, t0); 4087 tcg_gen_ext32u_i64(t1, t1); 4088 tcg_gen_mul_i64(t0, t0, t1); 4089 break; 4090 4091 case OPC_SEQU_CP2: 4092 case OPC_SEQ_CP2: 4093 cond = TCG_COND_EQ; 4094 goto do_cc_cond; 4095 break; 4096 case OPC_SLTU_CP2: 4097 cond = TCG_COND_LTU; 4098 goto do_cc_cond; 4099 break; 4100 case OPC_SLT_CP2: 4101 cond = TCG_COND_LT; 4102 goto do_cc_cond; 4103 break; 4104 case OPC_SLEU_CP2: 4105 cond = TCG_COND_LEU; 4106 goto do_cc_cond; 4107 break; 4108 case OPC_SLE_CP2: 4109 cond = TCG_COND_LE; 4110 do_cc_cond: 4111 { 4112 int cc = (ctx->opcode >> 8) & 0x7; 4113 TCGv_i64 t64 = tcg_temp_new_i64(); 4114 TCGv_i32 t32 = tcg_temp_new_i32(); 4115 4116 tcg_gen_setcond_i64(cond, t64, t0, t1); 4117 tcg_gen_extrl_i64_i32(t32, t64); 4118 tcg_gen_deposit_i32(fpu_fcr31, fpu_fcr31, t32, 4119 get_fp_bit(cc), 1); 4120 } 4121 return; 4122 default: 4123 MIPS_INVAL("loongson_cp2"); 4124 gen_reserved_instruction(ctx); 4125 return; 4126 } 4127 4128 gen_store_fpr64(ctx, t0, rd); 4129 } 4130 4131 static void gen_loongson_lswc2(DisasContext *ctx, int rt, 4132 int rs, int rd) 4133 { 4134 TCGv t0, t1; 4135 TCGv_i32 fp0; 4136 #if defined(TARGET_MIPS64) 4137 int lsq_rt1 = ctx->opcode & 0x1f; 4138 int lsq_offset = sextract32(ctx->opcode, 6, 9) << 4; 4139 #endif 4140 int shf_offset = sextract32(ctx->opcode, 6, 8); 4141 4142 t0 = tcg_temp_new(); 4143 4144 switch (MASK_LOONGSON_GSLSQ(ctx->opcode)) { 4145 #if defined(TARGET_MIPS64) 4146 case OPC_GSLQ: 4147 t1 = tcg_temp_new(); 4148 gen_base_offset_addr(ctx, t0, rs, lsq_offset); 4149 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | 4150 ctx->default_tcg_memop_mask); 4151 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); 4152 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | 4153 ctx->default_tcg_memop_mask); 4154 gen_store_gpr(t1, rt); 4155 gen_store_gpr(t0, lsq_rt1); 4156 break; 4157 case OPC_GSLQC1: 4158 check_cp1_enabled(ctx); 4159 t1 = tcg_temp_new(); 4160 gen_base_offset_addr(ctx, t0, rs, lsq_offset); 4161 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | 4162 ctx->default_tcg_memop_mask); 4163 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); 4164 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | 4165 ctx->default_tcg_memop_mask); 4166 gen_store_fpr64(ctx, t1, rt); 4167 gen_store_fpr64(ctx, t0, lsq_rt1); 4168 break; 4169 case OPC_GSSQ: 4170 t1 = tcg_temp_new(); 4171 gen_base_offset_addr(ctx, t0, rs, lsq_offset); 4172 gen_load_gpr(t1, rt); 4173 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | 4174 ctx->default_tcg_memop_mask); 4175 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); 4176 gen_load_gpr(t1, lsq_rt1); 4177 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | 4178 ctx->default_tcg_memop_mask); 4179 break; 4180 case OPC_GSSQC1: 4181 check_cp1_enabled(ctx); 4182 t1 = tcg_temp_new(); 4183 gen_base_offset_addr(ctx, t0, rs, lsq_offset); 4184 gen_load_fpr64(ctx, t1, rt); 4185 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | 4186 ctx->default_tcg_memop_mask); 4187 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); 4188 gen_load_fpr64(ctx, t1, lsq_rt1); 4189 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | 4190 ctx->default_tcg_memop_mask); 4191 break; 4192 #endif 4193 case OPC_GSSHFL: 4194 switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) { 4195 case OPC_GSLWLC1: 4196 check_cp1_enabled(ctx); 4197 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4198 fp0 = tcg_temp_new_i32(); 4199 gen_load_fpr32(ctx, fp0, rt); 4200 t1 = tcg_temp_new(); 4201 tcg_gen_ext_i32_tl(t1, fp0); 4202 gen_lxl(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL); 4203 tcg_gen_trunc_tl_i32(fp0, t1); 4204 gen_store_fpr32(ctx, fp0, rt); 4205 break; 4206 case OPC_GSLWRC1: 4207 check_cp1_enabled(ctx); 4208 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4209 fp0 = tcg_temp_new_i32(); 4210 gen_load_fpr32(ctx, fp0, rt); 4211 t1 = tcg_temp_new(); 4212 tcg_gen_ext_i32_tl(t1, fp0); 4213 gen_lxr(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL); 4214 tcg_gen_trunc_tl_i32(fp0, t1); 4215 gen_store_fpr32(ctx, fp0, rt); 4216 break; 4217 #if defined(TARGET_MIPS64) 4218 case OPC_GSLDLC1: 4219 check_cp1_enabled(ctx); 4220 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4221 t1 = tcg_temp_new(); 4222 gen_load_fpr64(ctx, t1, rt); 4223 gen_lxl(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); 4224 gen_store_fpr64(ctx, t1, rt); 4225 break; 4226 case OPC_GSLDRC1: 4227 check_cp1_enabled(ctx); 4228 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4229 t1 = tcg_temp_new(); 4230 gen_load_fpr64(ctx, t1, rt); 4231 gen_lxr(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); 4232 gen_store_fpr64(ctx, t1, rt); 4233 break; 4234 #endif 4235 default: 4236 MIPS_INVAL("loongson_gsshfl"); 4237 gen_reserved_instruction(ctx); 4238 break; 4239 } 4240 break; 4241 case OPC_GSSHFS: 4242 switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) { 4243 case OPC_GSSWLC1: 4244 check_cp1_enabled(ctx); 4245 t1 = tcg_temp_new(); 4246 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4247 fp0 = tcg_temp_new_i32(); 4248 gen_load_fpr32(ctx, fp0, rt); 4249 tcg_gen_ext_i32_tl(t1, fp0); 4250 gen_helper_0e2i(swl, t1, t0, ctx->mem_idx); 4251 break; 4252 case OPC_GSSWRC1: 4253 check_cp1_enabled(ctx); 4254 t1 = tcg_temp_new(); 4255 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4256 fp0 = tcg_temp_new_i32(); 4257 gen_load_fpr32(ctx, fp0, rt); 4258 tcg_gen_ext_i32_tl(t1, fp0); 4259 gen_helper_0e2i(swr, t1, t0, ctx->mem_idx); 4260 break; 4261 #if defined(TARGET_MIPS64) 4262 case OPC_GSSDLC1: 4263 check_cp1_enabled(ctx); 4264 t1 = tcg_temp_new(); 4265 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4266 gen_load_fpr64(ctx, t1, rt); 4267 gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx); 4268 break; 4269 case OPC_GSSDRC1: 4270 check_cp1_enabled(ctx); 4271 t1 = tcg_temp_new(); 4272 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4273 gen_load_fpr64(ctx, t1, rt); 4274 gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx); 4275 break; 4276 #endif 4277 default: 4278 MIPS_INVAL("loongson_gsshfs"); 4279 gen_reserved_instruction(ctx); 4280 break; 4281 } 4282 break; 4283 default: 4284 MIPS_INVAL("loongson_gslsq"); 4285 gen_reserved_instruction(ctx); 4286 break; 4287 } 4288 } 4289 4290 /* Loongson EXT LDC2/SDC2 */ 4291 static void gen_loongson_lsdc2(DisasContext *ctx, int rt, 4292 int rs, int rd) 4293 { 4294 int offset = sextract32(ctx->opcode, 3, 8); 4295 uint32_t opc = MASK_LOONGSON_LSDC2(ctx->opcode); 4296 TCGv t0, t1; 4297 TCGv_i32 fp0; 4298 4299 /* Pre-conditions */ 4300 switch (opc) { 4301 case OPC_GSLBX: 4302 case OPC_GSLHX: 4303 case OPC_GSLWX: 4304 case OPC_GSLDX: 4305 /* prefetch, implement as NOP */ 4306 if (rt == 0) { 4307 return; 4308 } 4309 break; 4310 case OPC_GSSBX: 4311 case OPC_GSSHX: 4312 case OPC_GSSWX: 4313 case OPC_GSSDX: 4314 break; 4315 case OPC_GSLWXC1: 4316 #if defined(TARGET_MIPS64) 4317 case OPC_GSLDXC1: 4318 #endif 4319 check_cp1_enabled(ctx); 4320 /* prefetch, implement as NOP */ 4321 if (rt == 0) { 4322 return; 4323 } 4324 break; 4325 case OPC_GSSWXC1: 4326 #if defined(TARGET_MIPS64) 4327 case OPC_GSSDXC1: 4328 #endif 4329 check_cp1_enabled(ctx); 4330 break; 4331 default: 4332 MIPS_INVAL("loongson_lsdc2"); 4333 gen_reserved_instruction(ctx); 4334 return; 4335 break; 4336 } 4337 4338 t0 = tcg_temp_new(); 4339 4340 gen_base_offset_addr(ctx, t0, rs, offset); 4341 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); 4342 4343 switch (opc) { 4344 case OPC_GSLBX: 4345 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB); 4346 gen_store_gpr(t0, rt); 4347 break; 4348 case OPC_GSLHX: 4349 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW | 4350 ctx->default_tcg_memop_mask); 4351 gen_store_gpr(t0, rt); 4352 break; 4353 case OPC_GSLWX: 4354 gen_base_offset_addr(ctx, t0, rs, offset); 4355 if (rd) { 4356 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); 4357 } 4358 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | 4359 ctx->default_tcg_memop_mask); 4360 gen_store_gpr(t0, rt); 4361 break; 4362 #if defined(TARGET_MIPS64) 4363 case OPC_GSLDX: 4364 gen_base_offset_addr(ctx, t0, rs, offset); 4365 if (rd) { 4366 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); 4367 } 4368 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | 4369 ctx->default_tcg_memop_mask); 4370 gen_store_gpr(t0, rt); 4371 break; 4372 #endif 4373 case OPC_GSLWXC1: 4374 gen_base_offset_addr(ctx, t0, rs, offset); 4375 if (rd) { 4376 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); 4377 } 4378 fp0 = tcg_temp_new_i32(); 4379 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | 4380 ctx->default_tcg_memop_mask); 4381 gen_store_fpr32(ctx, fp0, rt); 4382 break; 4383 #if defined(TARGET_MIPS64) 4384 case OPC_GSLDXC1: 4385 gen_base_offset_addr(ctx, t0, rs, offset); 4386 if (rd) { 4387 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); 4388 } 4389 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | 4390 ctx->default_tcg_memop_mask); 4391 gen_store_fpr64(ctx, t0, rt); 4392 break; 4393 #endif 4394 case OPC_GSSBX: 4395 t1 = tcg_temp_new(); 4396 gen_load_gpr(t1, rt); 4397 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_SB); 4398 break; 4399 case OPC_GSSHX: 4400 t1 = tcg_temp_new(); 4401 gen_load_gpr(t1, rt); 4402 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UW | 4403 ctx->default_tcg_memop_mask); 4404 break; 4405 case OPC_GSSWX: 4406 t1 = tcg_temp_new(); 4407 gen_load_gpr(t1, rt); 4408 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | 4409 ctx->default_tcg_memop_mask); 4410 break; 4411 #if defined(TARGET_MIPS64) 4412 case OPC_GSSDX: 4413 t1 = tcg_temp_new(); 4414 gen_load_gpr(t1, rt); 4415 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | 4416 ctx->default_tcg_memop_mask); 4417 break; 4418 #endif 4419 case OPC_GSSWXC1: 4420 fp0 = tcg_temp_new_i32(); 4421 gen_load_fpr32(ctx, fp0, rt); 4422 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | 4423 ctx->default_tcg_memop_mask); 4424 break; 4425 #if defined(TARGET_MIPS64) 4426 case OPC_GSSDXC1: 4427 t1 = tcg_temp_new(); 4428 gen_load_fpr64(ctx, t1, rt); 4429 tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | 4430 ctx->default_tcg_memop_mask); 4431 break; 4432 #endif 4433 default: 4434 break; 4435 } 4436 } 4437 4438 /* Traps */ 4439 static void gen_trap(DisasContext *ctx, uint32_t opc, 4440 int rs, int rt, int16_t imm, int code) 4441 { 4442 int cond; 4443 TCGv t0 = tcg_temp_new(); 4444 TCGv t1 = tcg_temp_new(); 4445 4446 cond = 0; 4447 /* Load needed operands */ 4448 switch (opc) { 4449 case OPC_TEQ: 4450 case OPC_TGE: 4451 case OPC_TGEU: 4452 case OPC_TLT: 4453 case OPC_TLTU: 4454 case OPC_TNE: 4455 /* Compare two registers */ 4456 if (rs != rt) { 4457 gen_load_gpr(t0, rs); 4458 gen_load_gpr(t1, rt); 4459 cond = 1; 4460 } 4461 break; 4462 case OPC_TEQI: 4463 case OPC_TGEI: 4464 case OPC_TGEIU: 4465 case OPC_TLTI: 4466 case OPC_TLTIU: 4467 case OPC_TNEI: 4468 /* Compare register to immediate */ 4469 if (rs != 0 || imm != 0) { 4470 gen_load_gpr(t0, rs); 4471 tcg_gen_movi_tl(t1, (int32_t)imm); 4472 cond = 1; 4473 } 4474 break; 4475 } 4476 if (cond == 0) { 4477 switch (opc) { 4478 case OPC_TEQ: /* rs == rs */ 4479 case OPC_TEQI: /* r0 == 0 */ 4480 case OPC_TGE: /* rs >= rs */ 4481 case OPC_TGEI: /* r0 >= 0 */ 4482 case OPC_TGEU: /* rs >= rs unsigned */ 4483 case OPC_TGEIU: /* r0 >= 0 unsigned */ 4484 /* Always trap */ 4485 #ifdef CONFIG_USER_ONLY 4486 /* Pass the break code along to cpu_loop. */ 4487 tcg_gen_st_i32(tcg_constant_i32(code), tcg_env, 4488 offsetof(CPUMIPSState, error_code)); 4489 #endif 4490 generate_exception_end(ctx, EXCP_TRAP); 4491 break; 4492 case OPC_TLT: /* rs < rs */ 4493 case OPC_TLTI: /* r0 < 0 */ 4494 case OPC_TLTU: /* rs < rs unsigned */ 4495 case OPC_TLTIU: /* r0 < 0 unsigned */ 4496 case OPC_TNE: /* rs != rs */ 4497 case OPC_TNEI: /* r0 != 0 */ 4498 /* Never trap: treat as NOP. */ 4499 break; 4500 } 4501 } else { 4502 TCGLabel *l1 = gen_new_label(); 4503 4504 switch (opc) { 4505 case OPC_TEQ: 4506 case OPC_TEQI: 4507 tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1); 4508 break; 4509 case OPC_TGE: 4510 case OPC_TGEI: 4511 tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1); 4512 break; 4513 case OPC_TGEU: 4514 case OPC_TGEIU: 4515 tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1); 4516 break; 4517 case OPC_TLT: 4518 case OPC_TLTI: 4519 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 4520 break; 4521 case OPC_TLTU: 4522 case OPC_TLTIU: 4523 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 4524 break; 4525 case OPC_TNE: 4526 case OPC_TNEI: 4527 tcg_gen_brcond_tl(TCG_COND_EQ, t0, t1, l1); 4528 break; 4529 } 4530 #ifdef CONFIG_USER_ONLY 4531 /* Pass the break code along to cpu_loop. */ 4532 tcg_gen_st_i32(tcg_constant_i32(code), tcg_env, 4533 offsetof(CPUMIPSState, error_code)); 4534 #endif 4535 /* Like save_cpu_state, only don't update saved values. */ 4536 if (ctx->base.pc_next != ctx->saved_pc) { 4537 gen_save_pc(ctx->base.pc_next); 4538 } 4539 if (ctx->hflags != ctx->saved_hflags) { 4540 tcg_gen_movi_i32(hflags, ctx->hflags); 4541 } 4542 generate_exception(ctx, EXCP_TRAP); 4543 gen_set_label(l1); 4544 } 4545 } 4546 4547 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4548 { 4549 if (translator_use_goto_tb(&ctx->base, dest)) { 4550 tcg_gen_goto_tb(n); 4551 gen_save_pc(dest); 4552 tcg_gen_exit_tb(ctx->base.tb, n); 4553 } else { 4554 gen_save_pc(dest); 4555 tcg_gen_lookup_and_goto_ptr(); 4556 } 4557 } 4558 4559 /* Branches (before delay slot) */ 4560 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, 4561 int insn_bytes, 4562 int rs, int rt, int32_t offset, 4563 int delayslot_size) 4564 { 4565 target_ulong btgt = -1; 4566 int blink = 0; 4567 int bcond_compute = 0; 4568 TCGv t0 = tcg_temp_new(); 4569 TCGv t1 = tcg_temp_new(); 4570 4571 if (ctx->hflags & MIPS_HFLAG_BMASK) { 4572 #ifdef MIPS_DEBUG_DISAS 4573 LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016" 4574 VADDR_PRIx "\n", ctx->base.pc_next); 4575 #endif 4576 gen_reserved_instruction(ctx); 4577 goto out; 4578 } 4579 4580 /* Load needed operands */ 4581 switch (opc) { 4582 case OPC_BEQ: 4583 case OPC_BEQL: 4584 case OPC_BNE: 4585 case OPC_BNEL: 4586 /* Compare two registers */ 4587 if (rs != rt) { 4588 gen_load_gpr(t0, rs); 4589 gen_load_gpr(t1, rt); 4590 bcond_compute = 1; 4591 } 4592 btgt = ctx->base.pc_next + insn_bytes + offset; 4593 break; 4594 case OPC_BGEZ: 4595 case OPC_BGEZAL: 4596 case OPC_BGEZALL: 4597 case OPC_BGEZL: 4598 case OPC_BGTZ: 4599 case OPC_BGTZL: 4600 case OPC_BLEZ: 4601 case OPC_BLEZL: 4602 case OPC_BLTZ: 4603 case OPC_BLTZAL: 4604 case OPC_BLTZALL: 4605 case OPC_BLTZL: 4606 /* Compare to zero */ 4607 if (rs != 0) { 4608 gen_load_gpr(t0, rs); 4609 bcond_compute = 1; 4610 } 4611 btgt = ctx->base.pc_next + insn_bytes + offset; 4612 break; 4613 case OPC_BPOSGE32: 4614 #if defined(TARGET_MIPS64) 4615 case OPC_BPOSGE64: 4616 tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F); 4617 #else 4618 tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F); 4619 #endif 4620 bcond_compute = 1; 4621 btgt = ctx->base.pc_next + insn_bytes + offset; 4622 break; 4623 case OPC_J: 4624 case OPC_JAL: 4625 { 4626 /* Jump to immediate */ 4627 int jal_mask = ctx->hflags & MIPS_HFLAG_M16 ? 0xF8000000 4628 : 0xF0000000; 4629 btgt = ((ctx->base.pc_next + insn_bytes) & jal_mask) 4630 | (uint32_t)offset; 4631 break; 4632 } 4633 case OPC_JALX: 4634 /* Jump to immediate */ 4635 btgt = ((ctx->base.pc_next + insn_bytes) & (int32_t)0xF0000000) | 4636 (uint32_t)offset; 4637 break; 4638 case OPC_JR: 4639 case OPC_JALR: 4640 /* Jump to register */ 4641 if (offset != 0 && offset != 16) { 4642 /* 4643 * Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the 4644 * others are reserved. 4645 */ 4646 MIPS_INVAL("jump hint"); 4647 gen_reserved_instruction(ctx); 4648 goto out; 4649 } 4650 gen_load_gpr(btarget, rs); 4651 break; 4652 default: 4653 MIPS_INVAL("branch/jump"); 4654 gen_reserved_instruction(ctx); 4655 goto out; 4656 } 4657 if (bcond_compute == 0) { 4658 /* No condition to be computed */ 4659 switch (opc) { 4660 case OPC_BEQ: /* rx == rx */ 4661 case OPC_BEQL: /* rx == rx likely */ 4662 case OPC_BGEZ: /* 0 >= 0 */ 4663 case OPC_BGEZL: /* 0 >= 0 likely */ 4664 case OPC_BLEZ: /* 0 <= 0 */ 4665 case OPC_BLEZL: /* 0 <= 0 likely */ 4666 /* Always take */ 4667 ctx->hflags |= MIPS_HFLAG_B; 4668 break; 4669 case OPC_BGEZAL: /* 0 >= 0 */ 4670 case OPC_BGEZALL: /* 0 >= 0 likely */ 4671 /* Always take and link */ 4672 blink = 31; 4673 ctx->hflags |= MIPS_HFLAG_B; 4674 break; 4675 case OPC_BNE: /* rx != rx */ 4676 case OPC_BGTZ: /* 0 > 0 */ 4677 case OPC_BLTZ: /* 0 < 0 */ 4678 /* Treat as NOP. */ 4679 goto out; 4680 case OPC_BLTZAL: /* 0 < 0 */ 4681 /* 4682 * Handle as an unconditional branch to get correct delay 4683 * slot checking. 4684 */ 4685 blink = 31; 4686 btgt = ctx->base.pc_next + insn_bytes + delayslot_size; 4687 ctx->hflags |= MIPS_HFLAG_B; 4688 break; 4689 case OPC_BLTZALL: /* 0 < 0 likely */ 4690 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 8); 4691 /* Skip the instruction in the delay slot */ 4692 ctx->base.pc_next += 4; 4693 goto out; 4694 case OPC_BNEL: /* rx != rx likely */ 4695 case OPC_BGTZL: /* 0 > 0 likely */ 4696 case OPC_BLTZL: /* 0 < 0 likely */ 4697 /* Skip the instruction in the delay slot */ 4698 ctx->base.pc_next += 4; 4699 goto out; 4700 case OPC_J: 4701 ctx->hflags |= MIPS_HFLAG_B; 4702 break; 4703 case OPC_JALX: 4704 ctx->hflags |= MIPS_HFLAG_BX; 4705 /* Fallthrough */ 4706 case OPC_JAL: 4707 blink = 31; 4708 ctx->hflags |= MIPS_HFLAG_B; 4709 break; 4710 case OPC_JR: 4711 ctx->hflags |= MIPS_HFLAG_BR; 4712 break; 4713 case OPC_JALR: 4714 blink = rt; 4715 ctx->hflags |= MIPS_HFLAG_BR; 4716 break; 4717 default: 4718 MIPS_INVAL("branch/jump"); 4719 gen_reserved_instruction(ctx); 4720 goto out; 4721 } 4722 } else { 4723 switch (opc) { 4724 case OPC_BEQ: 4725 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1); 4726 goto not_likely; 4727 case OPC_BEQL: 4728 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1); 4729 goto likely; 4730 case OPC_BNE: 4731 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1); 4732 goto not_likely; 4733 case OPC_BNEL: 4734 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1); 4735 goto likely; 4736 case OPC_BGEZ: 4737 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); 4738 goto not_likely; 4739 case OPC_BGEZL: 4740 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); 4741 goto likely; 4742 case OPC_BGEZAL: 4743 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); 4744 blink = 31; 4745 goto not_likely; 4746 case OPC_BGEZALL: 4747 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); 4748 blink = 31; 4749 goto likely; 4750 case OPC_BGTZ: 4751 tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0); 4752 goto not_likely; 4753 case OPC_BGTZL: 4754 tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0); 4755 goto likely; 4756 case OPC_BLEZ: 4757 tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0); 4758 goto not_likely; 4759 case OPC_BLEZL: 4760 tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0); 4761 goto likely; 4762 case OPC_BLTZ: 4763 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); 4764 goto not_likely; 4765 case OPC_BLTZL: 4766 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); 4767 goto likely; 4768 case OPC_BPOSGE32: 4769 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32); 4770 goto not_likely; 4771 #if defined(TARGET_MIPS64) 4772 case OPC_BPOSGE64: 4773 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 64); 4774 goto not_likely; 4775 #endif 4776 case OPC_BLTZAL: 4777 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); 4778 blink = 31; 4779 not_likely: 4780 ctx->hflags |= MIPS_HFLAG_BC; 4781 break; 4782 case OPC_BLTZALL: 4783 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); 4784 blink = 31; 4785 likely: 4786 ctx->hflags |= MIPS_HFLAG_BL; 4787 break; 4788 default: 4789 MIPS_INVAL("conditional branch/jump"); 4790 gen_reserved_instruction(ctx); 4791 goto out; 4792 } 4793 } 4794 4795 ctx->btarget = btgt; 4796 4797 switch (delayslot_size) { 4798 case 2: 4799 ctx->hflags |= MIPS_HFLAG_BDS16; 4800 break; 4801 case 4: 4802 ctx->hflags |= MIPS_HFLAG_BDS32; 4803 break; 4804 } 4805 4806 if (blink > 0) { 4807 int post_delay = insn_bytes + delayslot_size; 4808 int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16); 4809 4810 tcg_gen_movi_tl(cpu_gpr[blink], 4811 ctx->base.pc_next + post_delay + lowbit); 4812 } 4813 4814 out: 4815 if (insn_bytes == 2) { 4816 ctx->hflags |= MIPS_HFLAG_B16; 4817 } 4818 } 4819 4820 4821 /* special3 bitfield operations */ 4822 static void gen_bitops(DisasContext *ctx, uint32_t opc, int rt, 4823 int rs, int lsb, int msb) 4824 { 4825 TCGv t0 = tcg_temp_new(); 4826 TCGv t1 = tcg_temp_new(); 4827 4828 gen_load_gpr(t1, rs); 4829 switch (opc) { 4830 case OPC_EXT: 4831 if (lsb + msb > 31) { 4832 goto fail; 4833 } 4834 if (msb != 31) { 4835 tcg_gen_extract_tl(t0, t1, lsb, msb + 1); 4836 } else { 4837 /* 4838 * The two checks together imply that lsb == 0, 4839 * so this is a simple sign-extension. 4840 */ 4841 tcg_gen_ext32s_tl(t0, t1); 4842 } 4843 break; 4844 #if defined(TARGET_MIPS64) 4845 case OPC_DEXTU: 4846 lsb += 32; 4847 goto do_dext; 4848 case OPC_DEXTM: 4849 msb += 32; 4850 goto do_dext; 4851 case OPC_DEXT: 4852 do_dext: 4853 if (lsb + msb > 63) { 4854 goto fail; 4855 } 4856 tcg_gen_extract_tl(t0, t1, lsb, msb + 1); 4857 break; 4858 #endif 4859 case OPC_INS: 4860 if (lsb > msb) { 4861 goto fail; 4862 } 4863 gen_load_gpr(t0, rt); 4864 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); 4865 tcg_gen_ext32s_tl(t0, t0); 4866 break; 4867 #if defined(TARGET_MIPS64) 4868 case OPC_DINSU: 4869 lsb += 32; 4870 /* FALLTHRU */ 4871 case OPC_DINSM: 4872 msb += 32; 4873 /* FALLTHRU */ 4874 case OPC_DINS: 4875 if (lsb > msb) { 4876 goto fail; 4877 } 4878 gen_load_gpr(t0, rt); 4879 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); 4880 break; 4881 #endif 4882 default: 4883 fail: 4884 MIPS_INVAL("bitops"); 4885 gen_reserved_instruction(ctx); 4886 return; 4887 } 4888 gen_store_gpr(t0, rt); 4889 } 4890 4891 static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd) 4892 { 4893 TCGv t0; 4894 4895 if (rd == 0) { 4896 /* If no destination, treat it as a NOP. */ 4897 return; 4898 } 4899 4900 t0 = tcg_temp_new(); 4901 gen_load_gpr(t0, rt); 4902 switch (op2) { 4903 case OPC_WSBH: 4904 { 4905 TCGv t1 = tcg_temp_new(); 4906 TCGv t2 = tcg_constant_tl(0x00FF00FF); 4907 4908 tcg_gen_shri_tl(t1, t0, 8); 4909 tcg_gen_and_tl(t1, t1, t2); 4910 tcg_gen_and_tl(t0, t0, t2); 4911 tcg_gen_shli_tl(t0, t0, 8); 4912 tcg_gen_or_tl(t0, t0, t1); 4913 tcg_gen_ext32s_tl(cpu_gpr[rd], t0); 4914 } 4915 break; 4916 case OPC_SEB: 4917 tcg_gen_ext8s_tl(cpu_gpr[rd], t0); 4918 break; 4919 case OPC_SEH: 4920 tcg_gen_ext16s_tl(cpu_gpr[rd], t0); 4921 break; 4922 #if defined(TARGET_MIPS64) 4923 case OPC_DSBH: 4924 { 4925 TCGv t1 = tcg_temp_new(); 4926 TCGv t2 = tcg_constant_tl(0x00FF00FF00FF00FFULL); 4927 4928 tcg_gen_shri_tl(t1, t0, 8); 4929 tcg_gen_and_tl(t1, t1, t2); 4930 tcg_gen_and_tl(t0, t0, t2); 4931 tcg_gen_shli_tl(t0, t0, 8); 4932 tcg_gen_or_tl(cpu_gpr[rd], t0, t1); 4933 } 4934 break; 4935 case OPC_DSHD: 4936 { 4937 TCGv t1 = tcg_temp_new(); 4938 TCGv t2 = tcg_constant_tl(0x0000FFFF0000FFFFULL); 4939 4940 tcg_gen_shri_tl(t1, t0, 16); 4941 tcg_gen_and_tl(t1, t1, t2); 4942 tcg_gen_and_tl(t0, t0, t2); 4943 tcg_gen_shli_tl(t0, t0, 16); 4944 tcg_gen_or_tl(t0, t0, t1); 4945 tcg_gen_shri_tl(t1, t0, 32); 4946 tcg_gen_shli_tl(t0, t0, 32); 4947 tcg_gen_or_tl(cpu_gpr[rd], t0, t1); 4948 } 4949 break; 4950 #endif 4951 default: 4952 MIPS_INVAL("bsfhl"); 4953 gen_reserved_instruction(ctx); 4954 return; 4955 } 4956 } 4957 4958 static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs, 4959 int rt, int bits) 4960 { 4961 TCGv t0; 4962 if (rd == 0) { 4963 /* Treat as NOP. */ 4964 return; 4965 } 4966 t0 = tcg_temp_new(); 4967 if (bits == 0 || bits == wordsz) { 4968 if (bits == 0) { 4969 gen_load_gpr(t0, rt); 4970 } else { 4971 gen_load_gpr(t0, rs); 4972 } 4973 switch (wordsz) { 4974 case 32: 4975 tcg_gen_ext32s_tl(cpu_gpr[rd], t0); 4976 break; 4977 #if defined(TARGET_MIPS64) 4978 case 64: 4979 tcg_gen_mov_tl(cpu_gpr[rd], t0); 4980 break; 4981 #endif 4982 } 4983 } else { 4984 TCGv t1 = tcg_temp_new(); 4985 gen_load_gpr(t0, rt); 4986 gen_load_gpr(t1, rs); 4987 switch (wordsz) { 4988 case 32: 4989 { 4990 TCGv_i64 t2 = tcg_temp_new_i64(); 4991 tcg_gen_concat_tl_i64(t2, t1, t0); 4992 tcg_gen_shri_i64(t2, t2, 32 - bits); 4993 gen_move_low32(cpu_gpr[rd], t2); 4994 } 4995 break; 4996 #if defined(TARGET_MIPS64) 4997 case 64: 4998 tcg_gen_shli_tl(t0, t0, bits); 4999 tcg_gen_shri_tl(t1, t1, 64 - bits); 5000 tcg_gen_or_tl(cpu_gpr[rd], t1, t0); 5001 break; 5002 #endif 5003 } 5004 } 5005 } 5006 5007 void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int bp) 5008 { 5009 gen_align_bits(ctx, wordsz, rd, rs, rt, bp * 8); 5010 } 5011 5012 static void gen_bitswap(DisasContext *ctx, int opc, int rd, int rt) 5013 { 5014 TCGv t0; 5015 if (rd == 0) { 5016 /* Treat as NOP. */ 5017 return; 5018 } 5019 t0 = tcg_temp_new(); 5020 gen_load_gpr(t0, rt); 5021 switch (opc) { 5022 case OPC_BITSWAP: 5023 gen_helper_bitswap(cpu_gpr[rd], t0); 5024 break; 5025 #if defined(TARGET_MIPS64) 5026 case OPC_DBITSWAP: 5027 gen_helper_dbitswap(cpu_gpr[rd], t0); 5028 break; 5029 #endif 5030 } 5031 } 5032 5033 #ifndef CONFIG_USER_ONLY 5034 /* CP0 (MMU and control) */ 5035 static inline void gen_mthc0_entrylo(TCGv arg, target_ulong off) 5036 { 5037 TCGv_i64 t0 = tcg_temp_new_i64(); 5038 TCGv_i64 t1 = tcg_temp_new_i64(); 5039 5040 tcg_gen_ext_tl_i64(t0, arg); 5041 tcg_gen_ld_i64(t1, tcg_env, off); 5042 #if defined(TARGET_MIPS64) 5043 tcg_gen_deposit_i64(t1, t1, t0, 30, 32); 5044 #else 5045 tcg_gen_concat32_i64(t1, t1, t0); 5046 #endif 5047 tcg_gen_st_i64(t1, tcg_env, off); 5048 } 5049 5050 static inline void gen_mthc0_store64(TCGv arg, target_ulong off) 5051 { 5052 TCGv_i64 t0 = tcg_temp_new_i64(); 5053 TCGv_i64 t1 = tcg_temp_new_i64(); 5054 5055 tcg_gen_ext_tl_i64(t0, arg); 5056 tcg_gen_ld_i64(t1, tcg_env, off); 5057 tcg_gen_concat32_i64(t1, t1, t0); 5058 tcg_gen_st_i64(t1, tcg_env, off); 5059 } 5060 5061 static inline void gen_mfhc0_entrylo(TCGv arg, target_ulong off) 5062 { 5063 TCGv_i64 t0 = tcg_temp_new_i64(); 5064 5065 tcg_gen_ld_i64(t0, tcg_env, off); 5066 #if defined(TARGET_MIPS64) 5067 tcg_gen_shri_i64(t0, t0, 30); 5068 #else 5069 tcg_gen_shri_i64(t0, t0, 32); 5070 #endif 5071 gen_move_low32(arg, t0); 5072 } 5073 5074 static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift) 5075 { 5076 TCGv_i64 t0 = tcg_temp_new_i64(); 5077 5078 tcg_gen_ld_i64(t0, tcg_env, off); 5079 tcg_gen_shri_i64(t0, t0, 32 + shift); 5080 gen_move_low32(arg, t0); 5081 } 5082 5083 static inline void gen_mfc0_load32(TCGv arg, target_ulong off) 5084 { 5085 TCGv_i32 t0 = tcg_temp_new_i32(); 5086 5087 tcg_gen_ld_i32(t0, tcg_env, off); 5088 tcg_gen_ext_i32_tl(arg, t0); 5089 } 5090 5091 static inline void gen_mfc0_load64(TCGv arg, target_ulong off) 5092 { 5093 tcg_gen_ld_tl(arg, tcg_env, off); 5094 tcg_gen_ext32s_tl(arg, arg); 5095 } 5096 5097 static inline void gen_mtc0_store32(TCGv arg, target_ulong off) 5098 { 5099 TCGv_i32 t0 = tcg_temp_new_i32(); 5100 5101 tcg_gen_trunc_tl_i32(t0, arg); 5102 tcg_gen_st_i32(t0, tcg_env, off); 5103 } 5104 5105 #define CP0_CHECK(c) \ 5106 do { \ 5107 if (!(c)) { \ 5108 goto cp0_unimplemented; \ 5109 } \ 5110 } while (0) 5111 5112 static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel) 5113 { 5114 const char *register_name = "invalid"; 5115 5116 switch (reg) { 5117 case CP0_REGISTER_02: 5118 switch (sel) { 5119 case 0: 5120 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); 5121 gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0)); 5122 register_name = "EntryLo0"; 5123 break; 5124 default: 5125 goto cp0_unimplemented; 5126 } 5127 break; 5128 case CP0_REGISTER_03: 5129 switch (sel) { 5130 case CP0_REG03__ENTRYLO1: 5131 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); 5132 gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1)); 5133 register_name = "EntryLo1"; 5134 break; 5135 default: 5136 goto cp0_unimplemented; 5137 } 5138 break; 5139 case CP0_REGISTER_17: 5140 switch (sel) { 5141 case CP0_REG17__LLADDR: 5142 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_LLAddr), 5143 ctx->CP0_LLAddr_shift); 5144 register_name = "LLAddr"; 5145 break; 5146 case CP0_REG17__MAAR: 5147 CP0_CHECK(ctx->mrp); 5148 gen_helper_mfhc0_maar(arg, tcg_env); 5149 register_name = "MAAR"; 5150 break; 5151 default: 5152 goto cp0_unimplemented; 5153 } 5154 break; 5155 case CP0_REGISTER_19: 5156 switch (sel) { 5157 case CP0_REG19__WATCHHI0: 5158 case CP0_REG19__WATCHHI1: 5159 case CP0_REG19__WATCHHI2: 5160 case CP0_REG19__WATCHHI3: 5161 case CP0_REG19__WATCHHI4: 5162 case CP0_REG19__WATCHHI5: 5163 case CP0_REG19__WATCHHI6: 5164 case CP0_REG19__WATCHHI7: 5165 /* upper 32 bits are only available when Config5MI != 0 */ 5166 CP0_CHECK(ctx->mi); 5167 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_WatchHi[sel]), 0); 5168 register_name = "WatchHi"; 5169 break; 5170 default: 5171 goto cp0_unimplemented; 5172 } 5173 break; 5174 case CP0_REGISTER_28: 5175 switch (sel) { 5176 case 0: 5177 case 2: 5178 case 4: 5179 case 6: 5180 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_TagLo), 0); 5181 register_name = "TagLo"; 5182 break; 5183 default: 5184 goto cp0_unimplemented; 5185 } 5186 break; 5187 default: 5188 goto cp0_unimplemented; 5189 } 5190 trace_mips_translate_c0("mfhc0", register_name, reg, sel); 5191 return; 5192 5193 cp0_unimplemented: 5194 qemu_log_mask(LOG_UNIMP, "mfhc0 %s (reg %d sel %d)\n", 5195 register_name, reg, sel); 5196 tcg_gen_movi_tl(arg, 0); 5197 } 5198 5199 static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel) 5200 { 5201 const char *register_name = "invalid"; 5202 uint64_t mask = ctx->PAMask >> 36; 5203 5204 switch (reg) { 5205 case CP0_REGISTER_02: 5206 switch (sel) { 5207 case 0: 5208 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); 5209 tcg_gen_andi_tl(arg, arg, mask); 5210 gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0)); 5211 register_name = "EntryLo0"; 5212 break; 5213 default: 5214 goto cp0_unimplemented; 5215 } 5216 break; 5217 case CP0_REGISTER_03: 5218 switch (sel) { 5219 case CP0_REG03__ENTRYLO1: 5220 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); 5221 tcg_gen_andi_tl(arg, arg, mask); 5222 gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1)); 5223 register_name = "EntryLo1"; 5224 break; 5225 default: 5226 goto cp0_unimplemented; 5227 } 5228 break; 5229 case CP0_REGISTER_17: 5230 switch (sel) { 5231 case CP0_REG17__LLADDR: 5232 /* 5233 * LLAddr is read-only (the only exception is bit 0 if LLB is 5234 * supported); the CP0_LLAddr_rw_bitmask does not seem to be 5235 * relevant for modern MIPS cores supporting MTHC0, therefore 5236 * treating MTHC0 to LLAddr as NOP. 5237 */ 5238 register_name = "LLAddr"; 5239 break; 5240 case CP0_REG17__MAAR: 5241 CP0_CHECK(ctx->mrp); 5242 gen_helper_mthc0_maar(tcg_env, arg); 5243 register_name = "MAAR"; 5244 break; 5245 default: 5246 goto cp0_unimplemented; 5247 } 5248 break; 5249 case CP0_REGISTER_19: 5250 switch (sel) { 5251 case CP0_REG19__WATCHHI0: 5252 case CP0_REG19__WATCHHI1: 5253 case CP0_REG19__WATCHHI2: 5254 case CP0_REG19__WATCHHI3: 5255 case CP0_REG19__WATCHHI4: 5256 case CP0_REG19__WATCHHI5: 5257 case CP0_REG19__WATCHHI6: 5258 case CP0_REG19__WATCHHI7: 5259 /* upper 32 bits are only available when Config5MI != 0 */ 5260 CP0_CHECK(ctx->mi); 5261 gen_helper_0e1i(mthc0_watchhi, arg, sel); 5262 register_name = "WatchHi"; 5263 break; 5264 default: 5265 goto cp0_unimplemented; 5266 } 5267 break; 5268 case CP0_REGISTER_28: 5269 switch (sel) { 5270 case 0: 5271 case 2: 5272 case 4: 5273 case 6: 5274 tcg_gen_andi_tl(arg, arg, mask); 5275 gen_mthc0_store64(arg, offsetof(CPUMIPSState, CP0_TagLo)); 5276 register_name = "TagLo"; 5277 break; 5278 default: 5279 goto cp0_unimplemented; 5280 } 5281 break; 5282 default: 5283 goto cp0_unimplemented; 5284 } 5285 trace_mips_translate_c0("mthc0", register_name, reg, sel); 5286 return; 5287 5288 cp0_unimplemented: 5289 qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n", 5290 register_name, reg, sel); 5291 } 5292 5293 static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg) 5294 { 5295 if (ctx->insn_flags & ISA_MIPS_R6) { 5296 tcg_gen_movi_tl(arg, 0); 5297 } else { 5298 tcg_gen_movi_tl(arg, ~0); 5299 } 5300 } 5301 5302 static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) 5303 { 5304 const char *register_name = "invalid"; 5305 5306 if (sel != 0) { 5307 check_insn(ctx, ISA_MIPS_R1); 5308 } 5309 5310 switch (reg) { 5311 case CP0_REGISTER_00: 5312 switch (sel) { 5313 case CP0_REG00__INDEX: 5314 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index)); 5315 register_name = "Index"; 5316 break; 5317 case CP0_REG00__MVPCONTROL: 5318 CP0_CHECK(ctx->insn_flags & ASE_MT); 5319 gen_helper_mfc0_mvpcontrol(arg, tcg_env); 5320 register_name = "MVPControl"; 5321 break; 5322 case CP0_REG00__MVPCONF0: 5323 CP0_CHECK(ctx->insn_flags & ASE_MT); 5324 gen_helper_mfc0_mvpconf0(arg, tcg_env); 5325 register_name = "MVPConf0"; 5326 break; 5327 case CP0_REG00__MVPCONF1: 5328 CP0_CHECK(ctx->insn_flags & ASE_MT); 5329 gen_helper_mfc0_mvpconf1(arg, tcg_env); 5330 register_name = "MVPConf1"; 5331 break; 5332 case CP0_REG00__VPCONTROL: 5333 CP0_CHECK(ctx->vp); 5334 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl)); 5335 register_name = "VPControl"; 5336 break; 5337 default: 5338 goto cp0_unimplemented; 5339 } 5340 break; 5341 case CP0_REGISTER_01: 5342 switch (sel) { 5343 case CP0_REG01__RANDOM: 5344 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 5345 gen_helper_mfc0_random(arg, tcg_env); 5346 register_name = "Random"; 5347 break; 5348 case CP0_REG01__VPECONTROL: 5349 CP0_CHECK(ctx->insn_flags & ASE_MT); 5350 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl)); 5351 register_name = "VPEControl"; 5352 break; 5353 case CP0_REG01__VPECONF0: 5354 CP0_CHECK(ctx->insn_flags & ASE_MT); 5355 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0)); 5356 register_name = "VPEConf0"; 5357 break; 5358 case CP0_REG01__VPECONF1: 5359 CP0_CHECK(ctx->insn_flags & ASE_MT); 5360 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1)); 5361 register_name = "VPEConf1"; 5362 break; 5363 case CP0_REG01__YQMASK: 5364 CP0_CHECK(ctx->insn_flags & ASE_MT); 5365 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask)); 5366 register_name = "YQMask"; 5367 break; 5368 case CP0_REG01__VPESCHEDULE: 5369 CP0_CHECK(ctx->insn_flags & ASE_MT); 5370 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule)); 5371 register_name = "VPESchedule"; 5372 break; 5373 case CP0_REG01__VPESCHEFBACK: 5374 CP0_CHECK(ctx->insn_flags & ASE_MT); 5375 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack)); 5376 register_name = "VPEScheFBack"; 5377 break; 5378 case CP0_REG01__VPEOPT: 5379 CP0_CHECK(ctx->insn_flags & ASE_MT); 5380 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt)); 5381 register_name = "VPEOpt"; 5382 break; 5383 default: 5384 goto cp0_unimplemented; 5385 } 5386 break; 5387 case CP0_REGISTER_02: 5388 switch (sel) { 5389 case CP0_REG02__ENTRYLO0: 5390 { 5391 TCGv_i64 tmp = tcg_temp_new_i64(); 5392 tcg_gen_ld_i64(tmp, tcg_env, 5393 offsetof(CPUMIPSState, CP0_EntryLo0)); 5394 #if defined(TARGET_MIPS64) 5395 if (ctx->rxi) { 5396 /* Move RI/XI fields to bits 31:30 */ 5397 tcg_gen_shri_tl(arg, tmp, CP0EnLo_XI); 5398 tcg_gen_deposit_tl(tmp, tmp, arg, 30, 2); 5399 } 5400 #endif 5401 gen_move_low32(arg, tmp); 5402 } 5403 register_name = "EntryLo0"; 5404 break; 5405 case CP0_REG02__TCSTATUS: 5406 CP0_CHECK(ctx->insn_flags & ASE_MT); 5407 gen_helper_mfc0_tcstatus(arg, tcg_env); 5408 register_name = "TCStatus"; 5409 break; 5410 case CP0_REG02__TCBIND: 5411 CP0_CHECK(ctx->insn_flags & ASE_MT); 5412 gen_helper_mfc0_tcbind(arg, tcg_env); 5413 register_name = "TCBind"; 5414 break; 5415 case CP0_REG02__TCRESTART: 5416 CP0_CHECK(ctx->insn_flags & ASE_MT); 5417 gen_helper_mfc0_tcrestart(arg, tcg_env); 5418 register_name = "TCRestart"; 5419 break; 5420 case CP0_REG02__TCHALT: 5421 CP0_CHECK(ctx->insn_flags & ASE_MT); 5422 gen_helper_mfc0_tchalt(arg, tcg_env); 5423 register_name = "TCHalt"; 5424 break; 5425 case CP0_REG02__TCCONTEXT: 5426 CP0_CHECK(ctx->insn_flags & ASE_MT); 5427 gen_helper_mfc0_tccontext(arg, tcg_env); 5428 register_name = "TCContext"; 5429 break; 5430 case CP0_REG02__TCSCHEDULE: 5431 CP0_CHECK(ctx->insn_flags & ASE_MT); 5432 gen_helper_mfc0_tcschedule(arg, tcg_env); 5433 register_name = "TCSchedule"; 5434 break; 5435 case CP0_REG02__TCSCHEFBACK: 5436 CP0_CHECK(ctx->insn_flags & ASE_MT); 5437 gen_helper_mfc0_tcschefback(arg, tcg_env); 5438 register_name = "TCScheFBack"; 5439 break; 5440 default: 5441 goto cp0_unimplemented; 5442 } 5443 break; 5444 case CP0_REGISTER_03: 5445 switch (sel) { 5446 case CP0_REG03__ENTRYLO1: 5447 { 5448 TCGv_i64 tmp = tcg_temp_new_i64(); 5449 tcg_gen_ld_i64(tmp, tcg_env, 5450 offsetof(CPUMIPSState, CP0_EntryLo1)); 5451 #if defined(TARGET_MIPS64) 5452 if (ctx->rxi) { 5453 /* Move RI/XI fields to bits 31:30 */ 5454 tcg_gen_shri_tl(arg, tmp, CP0EnLo_XI); 5455 tcg_gen_deposit_tl(tmp, tmp, arg, 30, 2); 5456 } 5457 #endif 5458 gen_move_low32(arg, tmp); 5459 } 5460 register_name = "EntryLo1"; 5461 break; 5462 case CP0_REG03__GLOBALNUM: 5463 CP0_CHECK(ctx->vp); 5464 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber)); 5465 register_name = "GlobalNumber"; 5466 break; 5467 default: 5468 goto cp0_unimplemented; 5469 } 5470 break; 5471 case CP0_REGISTER_04: 5472 switch (sel) { 5473 case CP0_REG04__CONTEXT: 5474 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_Context)); 5475 tcg_gen_ext32s_tl(arg, arg); 5476 register_name = "Context"; 5477 break; 5478 case CP0_REG04__CONTEXTCONFIG: 5479 /* SmartMIPS ASE */ 5480 /* gen_helper_mfc0_contextconfig(arg); */ 5481 register_name = "ContextConfig"; 5482 goto cp0_unimplemented; 5483 case CP0_REG04__USERLOCAL: 5484 CP0_CHECK(ctx->ulri); 5485 tcg_gen_ld_tl(arg, tcg_env, 5486 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 5487 tcg_gen_ext32s_tl(arg, arg); 5488 register_name = "UserLocal"; 5489 break; 5490 case CP0_REG04__MMID: 5491 CP0_CHECK(ctx->mi); 5492 gen_helper_mtc0_memorymapid(tcg_env, arg); 5493 register_name = "MMID"; 5494 break; 5495 default: 5496 goto cp0_unimplemented; 5497 } 5498 break; 5499 case CP0_REGISTER_05: 5500 switch (sel) { 5501 case CP0_REG05__PAGEMASK: 5502 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask)); 5503 register_name = "PageMask"; 5504 break; 5505 case CP0_REG05__PAGEGRAIN: 5506 check_insn(ctx, ISA_MIPS_R2); 5507 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); 5508 register_name = "PageGrain"; 5509 break; 5510 case CP0_REG05__SEGCTL0: 5511 CP0_CHECK(ctx->sc); 5512 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl0)); 5513 tcg_gen_ext32s_tl(arg, arg); 5514 register_name = "SegCtl0"; 5515 break; 5516 case CP0_REG05__SEGCTL1: 5517 CP0_CHECK(ctx->sc); 5518 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl1)); 5519 tcg_gen_ext32s_tl(arg, arg); 5520 register_name = "SegCtl1"; 5521 break; 5522 case CP0_REG05__SEGCTL2: 5523 CP0_CHECK(ctx->sc); 5524 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl2)); 5525 tcg_gen_ext32s_tl(arg, arg); 5526 register_name = "SegCtl2"; 5527 break; 5528 case CP0_REG05__PWBASE: 5529 check_pw(ctx); 5530 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase)); 5531 register_name = "PWBase"; 5532 break; 5533 case CP0_REG05__PWFIELD: 5534 check_pw(ctx); 5535 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField)); 5536 register_name = "PWField"; 5537 break; 5538 case CP0_REG05__PWSIZE: 5539 check_pw(ctx); 5540 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize)); 5541 register_name = "PWSize"; 5542 break; 5543 default: 5544 goto cp0_unimplemented; 5545 } 5546 break; 5547 case CP0_REGISTER_06: 5548 switch (sel) { 5549 case CP0_REG06__WIRED: 5550 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired)); 5551 register_name = "Wired"; 5552 break; 5553 case CP0_REG06__SRSCONF0: 5554 check_insn(ctx, ISA_MIPS_R2); 5555 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); 5556 register_name = "SRSConf0"; 5557 break; 5558 case CP0_REG06__SRSCONF1: 5559 check_insn(ctx, ISA_MIPS_R2); 5560 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); 5561 register_name = "SRSConf1"; 5562 break; 5563 case CP0_REG06__SRSCONF2: 5564 check_insn(ctx, ISA_MIPS_R2); 5565 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); 5566 register_name = "SRSConf2"; 5567 break; 5568 case CP0_REG06__SRSCONF3: 5569 check_insn(ctx, ISA_MIPS_R2); 5570 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); 5571 register_name = "SRSConf3"; 5572 break; 5573 case CP0_REG06__SRSCONF4: 5574 check_insn(ctx, ISA_MIPS_R2); 5575 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); 5576 register_name = "SRSConf4"; 5577 break; 5578 case CP0_REG06__PWCTL: 5579 check_pw(ctx); 5580 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl)); 5581 register_name = "PWCtl"; 5582 break; 5583 default: 5584 goto cp0_unimplemented; 5585 } 5586 break; 5587 case CP0_REGISTER_07: 5588 switch (sel) { 5589 case CP0_REG07__HWRENA: 5590 check_insn(ctx, ISA_MIPS_R2); 5591 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); 5592 register_name = "HWREna"; 5593 break; 5594 default: 5595 goto cp0_unimplemented; 5596 } 5597 break; 5598 case CP0_REGISTER_08: 5599 switch (sel) { 5600 case CP0_REG08__BADVADDR: 5601 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_BadVAddr)); 5602 tcg_gen_ext32s_tl(arg, arg); 5603 register_name = "BadVAddr"; 5604 break; 5605 case CP0_REG08__BADINSTR: 5606 CP0_CHECK(ctx->bi); 5607 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr)); 5608 register_name = "BadInstr"; 5609 break; 5610 case CP0_REG08__BADINSTRP: 5611 CP0_CHECK(ctx->bp); 5612 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP)); 5613 register_name = "BadInstrP"; 5614 break; 5615 case CP0_REG08__BADINSTRX: 5616 CP0_CHECK(ctx->bi); 5617 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX)); 5618 tcg_gen_andi_tl(arg, arg, ~0xffff); 5619 register_name = "BadInstrX"; 5620 break; 5621 default: 5622 goto cp0_unimplemented; 5623 } 5624 break; 5625 case CP0_REGISTER_09: 5626 switch (sel) { 5627 case CP0_REG09__COUNT: 5628 /* Mark as an IO operation because we read the time. */ 5629 translator_io_start(&ctx->base); 5630 5631 gen_helper_mfc0_count(arg, tcg_env); 5632 /* 5633 * Break the TB to be able to take timer interrupts immediately 5634 * after reading count. DISAS_STOP isn't sufficient, we need to 5635 * ensure we break completely out of translated code. 5636 */ 5637 gen_save_pc(ctx->base.pc_next + 4); 5638 ctx->base.is_jmp = DISAS_EXIT; 5639 register_name = "Count"; 5640 break; 5641 default: 5642 goto cp0_unimplemented; 5643 } 5644 break; 5645 case CP0_REGISTER_10: 5646 switch (sel) { 5647 case CP0_REG10__ENTRYHI: 5648 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EntryHi)); 5649 tcg_gen_ext32s_tl(arg, arg); 5650 register_name = "EntryHi"; 5651 break; 5652 default: 5653 goto cp0_unimplemented; 5654 } 5655 break; 5656 case CP0_REGISTER_11: 5657 switch (sel) { 5658 case CP0_REG11__COMPARE: 5659 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare)); 5660 register_name = "Compare"; 5661 break; 5662 /* 6,7 are implementation dependent */ 5663 default: 5664 goto cp0_unimplemented; 5665 } 5666 break; 5667 case CP0_REGISTER_12: 5668 switch (sel) { 5669 case CP0_REG12__STATUS: 5670 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status)); 5671 register_name = "Status"; 5672 break; 5673 case CP0_REG12__INTCTL: 5674 check_insn(ctx, ISA_MIPS_R2); 5675 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); 5676 register_name = "IntCtl"; 5677 break; 5678 case CP0_REG12__SRSCTL: 5679 check_insn(ctx, ISA_MIPS_R2); 5680 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); 5681 register_name = "SRSCtl"; 5682 break; 5683 case CP0_REG12__SRSMAP: 5684 check_insn(ctx, ISA_MIPS_R2); 5685 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); 5686 register_name = "SRSMap"; 5687 break; 5688 default: 5689 goto cp0_unimplemented; 5690 } 5691 break; 5692 case CP0_REGISTER_13: 5693 switch (sel) { 5694 case CP0_REG13__CAUSE: 5695 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause)); 5696 register_name = "Cause"; 5697 break; 5698 default: 5699 goto cp0_unimplemented; 5700 } 5701 break; 5702 case CP0_REGISTER_14: 5703 switch (sel) { 5704 case CP0_REG14__EPC: 5705 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC)); 5706 tcg_gen_ext32s_tl(arg, arg); 5707 register_name = "EPC"; 5708 break; 5709 default: 5710 goto cp0_unimplemented; 5711 } 5712 break; 5713 case CP0_REGISTER_15: 5714 switch (sel) { 5715 case CP0_REG15__PRID: 5716 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid)); 5717 register_name = "PRid"; 5718 break; 5719 case CP0_REG15__EBASE: 5720 check_insn(ctx, ISA_MIPS_R2); 5721 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EBase)); 5722 tcg_gen_ext32s_tl(arg, arg); 5723 register_name = "EBase"; 5724 break; 5725 case CP0_REG15__CMGCRBASE: 5726 check_insn(ctx, ISA_MIPS_R2); 5727 CP0_CHECK(ctx->cmgcr); 5728 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_CMGCRBase)); 5729 tcg_gen_ext32s_tl(arg, arg); 5730 register_name = "CMGCRBase"; 5731 break; 5732 default: 5733 goto cp0_unimplemented; 5734 } 5735 break; 5736 case CP0_REGISTER_16: 5737 switch (sel) { 5738 case CP0_REG16__CONFIG: 5739 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0)); 5740 register_name = "Config"; 5741 break; 5742 case CP0_REG16__CONFIG1: 5743 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1)); 5744 register_name = "Config1"; 5745 break; 5746 case CP0_REG16__CONFIG2: 5747 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2)); 5748 register_name = "Config2"; 5749 break; 5750 case CP0_REG16__CONFIG3: 5751 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3)); 5752 register_name = "Config3"; 5753 break; 5754 case CP0_REG16__CONFIG4: 5755 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4)); 5756 register_name = "Config4"; 5757 break; 5758 case CP0_REG16__CONFIG5: 5759 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5)); 5760 register_name = "Config5"; 5761 break; 5762 /* 6,7 are implementation dependent */ 5763 case CP0_REG16__CONFIG6: 5764 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6)); 5765 register_name = "Config6"; 5766 break; 5767 case CP0_REG16__CONFIG7: 5768 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7)); 5769 register_name = "Config7"; 5770 break; 5771 default: 5772 goto cp0_unimplemented; 5773 } 5774 break; 5775 case CP0_REGISTER_17: 5776 switch (sel) { 5777 case CP0_REG17__LLADDR: 5778 gen_helper_mfc0_lladdr(arg, tcg_env); 5779 register_name = "LLAddr"; 5780 break; 5781 case CP0_REG17__MAAR: 5782 CP0_CHECK(ctx->mrp); 5783 gen_helper_mfc0_maar(arg, tcg_env); 5784 register_name = "MAAR"; 5785 break; 5786 case CP0_REG17__MAARI: 5787 CP0_CHECK(ctx->mrp); 5788 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI)); 5789 register_name = "MAARI"; 5790 break; 5791 default: 5792 goto cp0_unimplemented; 5793 } 5794 break; 5795 case CP0_REGISTER_18: 5796 switch (sel) { 5797 case CP0_REG18__WATCHLO0: 5798 case CP0_REG18__WATCHLO1: 5799 case CP0_REG18__WATCHLO2: 5800 case CP0_REG18__WATCHLO3: 5801 case CP0_REG18__WATCHLO4: 5802 case CP0_REG18__WATCHLO5: 5803 case CP0_REG18__WATCHLO6: 5804 case CP0_REG18__WATCHLO7: 5805 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 5806 gen_helper_1e0i(mfc0_watchlo, arg, sel); 5807 register_name = "WatchLo"; 5808 break; 5809 default: 5810 goto cp0_unimplemented; 5811 } 5812 break; 5813 case CP0_REGISTER_19: 5814 switch (sel) { 5815 case CP0_REG19__WATCHHI0: 5816 case CP0_REG19__WATCHHI1: 5817 case CP0_REG19__WATCHHI2: 5818 case CP0_REG19__WATCHHI3: 5819 case CP0_REG19__WATCHHI4: 5820 case CP0_REG19__WATCHHI5: 5821 case CP0_REG19__WATCHHI6: 5822 case CP0_REG19__WATCHHI7: 5823 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 5824 gen_helper_1e0i(mfc0_watchhi, arg, sel); 5825 register_name = "WatchHi"; 5826 break; 5827 default: 5828 goto cp0_unimplemented; 5829 } 5830 break; 5831 case CP0_REGISTER_20: 5832 switch (sel) { 5833 case CP0_REG20__XCONTEXT: 5834 #if defined(TARGET_MIPS64) 5835 check_insn(ctx, ISA_MIPS3); 5836 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_XContext)); 5837 tcg_gen_ext32s_tl(arg, arg); 5838 register_name = "XContext"; 5839 break; 5840 #endif 5841 default: 5842 goto cp0_unimplemented; 5843 } 5844 break; 5845 case CP0_REGISTER_21: 5846 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 5847 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 5848 switch (sel) { 5849 case 0: 5850 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask)); 5851 register_name = "Framemask"; 5852 break; 5853 default: 5854 goto cp0_unimplemented; 5855 } 5856 break; 5857 case CP0_REGISTER_22: 5858 tcg_gen_movi_tl(arg, 0); /* unimplemented */ 5859 register_name = "'Diagnostic"; /* implementation dependent */ 5860 break; 5861 case CP0_REGISTER_23: 5862 switch (sel) { 5863 case CP0_REG23__DEBUG: 5864 gen_helper_mfc0_debug(arg, tcg_env); /* EJTAG support */ 5865 register_name = "Debug"; 5866 break; 5867 case CP0_REG23__TRACECONTROL: 5868 /* PDtrace support */ 5869 /* gen_helper_mfc0_tracecontrol(arg); */ 5870 register_name = "TraceControl"; 5871 goto cp0_unimplemented; 5872 case CP0_REG23__TRACECONTROL2: 5873 /* PDtrace support */ 5874 /* gen_helper_mfc0_tracecontrol2(arg); */ 5875 register_name = "TraceControl2"; 5876 goto cp0_unimplemented; 5877 case CP0_REG23__USERTRACEDATA1: 5878 /* PDtrace support */ 5879 /* gen_helper_mfc0_usertracedata1(arg);*/ 5880 register_name = "UserTraceData1"; 5881 goto cp0_unimplemented; 5882 case CP0_REG23__TRACEIBPC: 5883 /* PDtrace support */ 5884 /* gen_helper_mfc0_traceibpc(arg); */ 5885 register_name = "TraceIBPC"; 5886 goto cp0_unimplemented; 5887 case CP0_REG23__TRACEDBPC: 5888 /* PDtrace support */ 5889 /* gen_helper_mfc0_tracedbpc(arg); */ 5890 register_name = "TraceDBPC"; 5891 goto cp0_unimplemented; 5892 default: 5893 goto cp0_unimplemented; 5894 } 5895 break; 5896 case CP0_REGISTER_24: 5897 switch (sel) { 5898 case CP0_REG24__DEPC: 5899 /* EJTAG support */ 5900 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC)); 5901 tcg_gen_ext32s_tl(arg, arg); 5902 register_name = "DEPC"; 5903 break; 5904 default: 5905 goto cp0_unimplemented; 5906 } 5907 break; 5908 case CP0_REGISTER_25: 5909 switch (sel) { 5910 case CP0_REG25__PERFCTL0: 5911 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0)); 5912 register_name = "Performance0"; 5913 break; 5914 case CP0_REG25__PERFCNT0: 5915 /* gen_helper_mfc0_performance1(arg); */ 5916 register_name = "Performance1"; 5917 goto cp0_unimplemented; 5918 case CP0_REG25__PERFCTL1: 5919 /* gen_helper_mfc0_performance2(arg); */ 5920 register_name = "Performance2"; 5921 goto cp0_unimplemented; 5922 case CP0_REG25__PERFCNT1: 5923 /* gen_helper_mfc0_performance3(arg); */ 5924 register_name = "Performance3"; 5925 goto cp0_unimplemented; 5926 case CP0_REG25__PERFCTL2: 5927 /* gen_helper_mfc0_performance4(arg); */ 5928 register_name = "Performance4"; 5929 goto cp0_unimplemented; 5930 case CP0_REG25__PERFCNT2: 5931 /* gen_helper_mfc0_performance5(arg); */ 5932 register_name = "Performance5"; 5933 goto cp0_unimplemented; 5934 case CP0_REG25__PERFCTL3: 5935 /* gen_helper_mfc0_performance6(arg); */ 5936 register_name = "Performance6"; 5937 goto cp0_unimplemented; 5938 case CP0_REG25__PERFCNT3: 5939 /* gen_helper_mfc0_performance7(arg); */ 5940 register_name = "Performance7"; 5941 goto cp0_unimplemented; 5942 default: 5943 goto cp0_unimplemented; 5944 } 5945 break; 5946 case CP0_REGISTER_26: 5947 switch (sel) { 5948 case CP0_REG26__ERRCTL: 5949 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl)); 5950 register_name = "ErrCtl"; 5951 break; 5952 default: 5953 goto cp0_unimplemented; 5954 } 5955 break; 5956 case CP0_REGISTER_27: 5957 switch (sel) { 5958 case CP0_REG27__CACHERR: 5959 tcg_gen_movi_tl(arg, 0); /* unimplemented */ 5960 register_name = "CacheErr"; 5961 break; 5962 default: 5963 goto cp0_unimplemented; 5964 } 5965 break; 5966 case CP0_REGISTER_28: 5967 switch (sel) { 5968 case CP0_REG28__TAGLO: 5969 case CP0_REG28__TAGLO1: 5970 case CP0_REG28__TAGLO2: 5971 case CP0_REG28__TAGLO3: 5972 { 5973 TCGv_i64 tmp = tcg_temp_new_i64(); 5974 tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUMIPSState, CP0_TagLo)); 5975 gen_move_low32(arg, tmp); 5976 } 5977 register_name = "TagLo"; 5978 break; 5979 case CP0_REG28__DATALO: 5980 case CP0_REG28__DATALO1: 5981 case CP0_REG28__DATALO2: 5982 case CP0_REG28__DATALO3: 5983 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo)); 5984 register_name = "DataLo"; 5985 break; 5986 default: 5987 goto cp0_unimplemented; 5988 } 5989 break; 5990 case CP0_REGISTER_29: 5991 switch (sel) { 5992 case CP0_REG29__TAGHI: 5993 case CP0_REG29__TAGHI1: 5994 case CP0_REG29__TAGHI2: 5995 case CP0_REG29__TAGHI3: 5996 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi)); 5997 register_name = "TagHi"; 5998 break; 5999 case CP0_REG29__DATAHI: 6000 case CP0_REG29__DATAHI1: 6001 case CP0_REG29__DATAHI2: 6002 case CP0_REG29__DATAHI3: 6003 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi)); 6004 register_name = "DataHi"; 6005 break; 6006 default: 6007 goto cp0_unimplemented; 6008 } 6009 break; 6010 case CP0_REGISTER_30: 6011 switch (sel) { 6012 case CP0_REG30__ERROREPC: 6013 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); 6014 tcg_gen_ext32s_tl(arg, arg); 6015 register_name = "ErrorEPC"; 6016 break; 6017 default: 6018 goto cp0_unimplemented; 6019 } 6020 break; 6021 case CP0_REGISTER_31: 6022 switch (sel) { 6023 case CP0_REG31__DESAVE: 6024 /* EJTAG support */ 6025 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); 6026 register_name = "DESAVE"; 6027 break; 6028 case CP0_REG31__KSCRATCH1: 6029 case CP0_REG31__KSCRATCH2: 6030 case CP0_REG31__KSCRATCH3: 6031 case CP0_REG31__KSCRATCH4: 6032 case CP0_REG31__KSCRATCH5: 6033 case CP0_REG31__KSCRATCH6: 6034 CP0_CHECK(ctx->kscrexist & (1 << sel)); 6035 tcg_gen_ld_tl(arg, tcg_env, 6036 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); 6037 tcg_gen_ext32s_tl(arg, arg); 6038 register_name = "KScratch"; 6039 break; 6040 default: 6041 goto cp0_unimplemented; 6042 } 6043 break; 6044 default: 6045 goto cp0_unimplemented; 6046 } 6047 trace_mips_translate_c0("mfc0", register_name, reg, sel); 6048 return; 6049 6050 cp0_unimplemented: 6051 qemu_log_mask(LOG_UNIMP, "mfc0 %s (reg %d sel %d)\n", 6052 register_name, reg, sel); 6053 gen_mfc0_unimplemented(ctx, arg); 6054 } 6055 6056 static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) 6057 { 6058 const char *register_name = "invalid"; 6059 bool icount; 6060 6061 if (sel != 0) { 6062 check_insn(ctx, ISA_MIPS_R1); 6063 } 6064 6065 icount = translator_io_start(&ctx->base); 6066 6067 switch (reg) { 6068 case CP0_REGISTER_00: 6069 switch (sel) { 6070 case CP0_REG00__INDEX: 6071 gen_helper_mtc0_index(tcg_env, arg); 6072 register_name = "Index"; 6073 break; 6074 case CP0_REG00__MVPCONTROL: 6075 CP0_CHECK(ctx->insn_flags & ASE_MT); 6076 gen_helper_mtc0_mvpcontrol(tcg_env, arg); 6077 register_name = "MVPControl"; 6078 break; 6079 case CP0_REG00__MVPCONF0: 6080 CP0_CHECK(ctx->insn_flags & ASE_MT); 6081 /* ignored */ 6082 register_name = "MVPConf0"; 6083 break; 6084 case CP0_REG00__MVPCONF1: 6085 CP0_CHECK(ctx->insn_flags & ASE_MT); 6086 /* ignored */ 6087 register_name = "MVPConf1"; 6088 break; 6089 case CP0_REG00__VPCONTROL: 6090 CP0_CHECK(ctx->vp); 6091 /* ignored */ 6092 register_name = "VPControl"; 6093 break; 6094 default: 6095 goto cp0_unimplemented; 6096 } 6097 break; 6098 case CP0_REGISTER_01: 6099 switch (sel) { 6100 case CP0_REG01__RANDOM: 6101 /* ignored */ 6102 register_name = "Random"; 6103 break; 6104 case CP0_REG01__VPECONTROL: 6105 CP0_CHECK(ctx->insn_flags & ASE_MT); 6106 gen_helper_mtc0_vpecontrol(tcg_env, arg); 6107 register_name = "VPEControl"; 6108 break; 6109 case CP0_REG01__VPECONF0: 6110 CP0_CHECK(ctx->insn_flags & ASE_MT); 6111 gen_helper_mtc0_vpeconf0(tcg_env, arg); 6112 register_name = "VPEConf0"; 6113 break; 6114 case CP0_REG01__VPECONF1: 6115 CP0_CHECK(ctx->insn_flags & ASE_MT); 6116 gen_helper_mtc0_vpeconf1(tcg_env, arg); 6117 register_name = "VPEConf1"; 6118 break; 6119 case CP0_REG01__YQMASK: 6120 CP0_CHECK(ctx->insn_flags & ASE_MT); 6121 gen_helper_mtc0_yqmask(tcg_env, arg); 6122 register_name = "YQMask"; 6123 break; 6124 case CP0_REG01__VPESCHEDULE: 6125 CP0_CHECK(ctx->insn_flags & ASE_MT); 6126 tcg_gen_st_tl(arg, tcg_env, 6127 offsetof(CPUMIPSState, CP0_VPESchedule)); 6128 register_name = "VPESchedule"; 6129 break; 6130 case CP0_REG01__VPESCHEFBACK: 6131 CP0_CHECK(ctx->insn_flags & ASE_MT); 6132 tcg_gen_st_tl(arg, tcg_env, 6133 offsetof(CPUMIPSState, CP0_VPEScheFBack)); 6134 register_name = "VPEScheFBack"; 6135 break; 6136 case CP0_REG01__VPEOPT: 6137 CP0_CHECK(ctx->insn_flags & ASE_MT); 6138 gen_helper_mtc0_vpeopt(tcg_env, arg); 6139 register_name = "VPEOpt"; 6140 break; 6141 default: 6142 goto cp0_unimplemented; 6143 } 6144 break; 6145 case CP0_REGISTER_02: 6146 switch (sel) { 6147 case CP0_REG02__ENTRYLO0: 6148 gen_helper_mtc0_entrylo0(tcg_env, arg); 6149 register_name = "EntryLo0"; 6150 break; 6151 case CP0_REG02__TCSTATUS: 6152 CP0_CHECK(ctx->insn_flags & ASE_MT); 6153 gen_helper_mtc0_tcstatus(tcg_env, arg); 6154 register_name = "TCStatus"; 6155 break; 6156 case CP0_REG02__TCBIND: 6157 CP0_CHECK(ctx->insn_flags & ASE_MT); 6158 gen_helper_mtc0_tcbind(tcg_env, arg); 6159 register_name = "TCBind"; 6160 break; 6161 case CP0_REG02__TCRESTART: 6162 CP0_CHECK(ctx->insn_flags & ASE_MT); 6163 gen_helper_mtc0_tcrestart(tcg_env, arg); 6164 register_name = "TCRestart"; 6165 break; 6166 case CP0_REG02__TCHALT: 6167 CP0_CHECK(ctx->insn_flags & ASE_MT); 6168 gen_helper_mtc0_tchalt(tcg_env, arg); 6169 register_name = "TCHalt"; 6170 break; 6171 case CP0_REG02__TCCONTEXT: 6172 CP0_CHECK(ctx->insn_flags & ASE_MT); 6173 gen_helper_mtc0_tccontext(tcg_env, arg); 6174 register_name = "TCContext"; 6175 break; 6176 case CP0_REG02__TCSCHEDULE: 6177 CP0_CHECK(ctx->insn_flags & ASE_MT); 6178 gen_helper_mtc0_tcschedule(tcg_env, arg); 6179 register_name = "TCSchedule"; 6180 break; 6181 case CP0_REG02__TCSCHEFBACK: 6182 CP0_CHECK(ctx->insn_flags & ASE_MT); 6183 gen_helper_mtc0_tcschefback(tcg_env, arg); 6184 register_name = "TCScheFBack"; 6185 break; 6186 default: 6187 goto cp0_unimplemented; 6188 } 6189 break; 6190 case CP0_REGISTER_03: 6191 switch (sel) { 6192 case CP0_REG03__ENTRYLO1: 6193 gen_helper_mtc0_entrylo1(tcg_env, arg); 6194 register_name = "EntryLo1"; 6195 break; 6196 case CP0_REG03__GLOBALNUM: 6197 CP0_CHECK(ctx->vp); 6198 /* ignored */ 6199 register_name = "GlobalNumber"; 6200 break; 6201 default: 6202 goto cp0_unimplemented; 6203 } 6204 break; 6205 case CP0_REGISTER_04: 6206 switch (sel) { 6207 case CP0_REG04__CONTEXT: 6208 gen_helper_mtc0_context(tcg_env, arg); 6209 register_name = "Context"; 6210 break; 6211 case CP0_REG04__CONTEXTCONFIG: 6212 /* SmartMIPS ASE */ 6213 /* gen_helper_mtc0_contextconfig(arg); */ 6214 register_name = "ContextConfig"; 6215 goto cp0_unimplemented; 6216 case CP0_REG04__USERLOCAL: 6217 CP0_CHECK(ctx->ulri); 6218 tcg_gen_st_tl(arg, tcg_env, 6219 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 6220 register_name = "UserLocal"; 6221 break; 6222 case CP0_REG04__MMID: 6223 CP0_CHECK(ctx->mi); 6224 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MemoryMapID)); 6225 register_name = "MMID"; 6226 break; 6227 default: 6228 goto cp0_unimplemented; 6229 } 6230 break; 6231 case CP0_REGISTER_05: 6232 switch (sel) { 6233 case CP0_REG05__PAGEMASK: 6234 gen_helper_mtc0_pagemask(tcg_env, arg); 6235 register_name = "PageMask"; 6236 break; 6237 case CP0_REG05__PAGEGRAIN: 6238 check_insn(ctx, ISA_MIPS_R2); 6239 gen_helper_mtc0_pagegrain(tcg_env, arg); 6240 register_name = "PageGrain"; 6241 ctx->base.is_jmp = DISAS_STOP; 6242 break; 6243 case CP0_REG05__SEGCTL0: 6244 CP0_CHECK(ctx->sc); 6245 gen_helper_mtc0_segctl0(tcg_env, arg); 6246 register_name = "SegCtl0"; 6247 break; 6248 case CP0_REG05__SEGCTL1: 6249 CP0_CHECK(ctx->sc); 6250 gen_helper_mtc0_segctl1(tcg_env, arg); 6251 register_name = "SegCtl1"; 6252 break; 6253 case CP0_REG05__SEGCTL2: 6254 CP0_CHECK(ctx->sc); 6255 gen_helper_mtc0_segctl2(tcg_env, arg); 6256 register_name = "SegCtl2"; 6257 break; 6258 case CP0_REG05__PWBASE: 6259 check_pw(ctx); 6260 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase)); 6261 register_name = "PWBase"; 6262 break; 6263 case CP0_REG05__PWFIELD: 6264 check_pw(ctx); 6265 gen_helper_mtc0_pwfield(tcg_env, arg); 6266 register_name = "PWField"; 6267 break; 6268 case CP0_REG05__PWSIZE: 6269 check_pw(ctx); 6270 gen_helper_mtc0_pwsize(tcg_env, arg); 6271 register_name = "PWSize"; 6272 break; 6273 default: 6274 goto cp0_unimplemented; 6275 } 6276 break; 6277 case CP0_REGISTER_06: 6278 switch (sel) { 6279 case CP0_REG06__WIRED: 6280 gen_helper_mtc0_wired(tcg_env, arg); 6281 register_name = "Wired"; 6282 break; 6283 case CP0_REG06__SRSCONF0: 6284 check_insn(ctx, ISA_MIPS_R2); 6285 gen_helper_mtc0_srsconf0(tcg_env, arg); 6286 register_name = "SRSConf0"; 6287 break; 6288 case CP0_REG06__SRSCONF1: 6289 check_insn(ctx, ISA_MIPS_R2); 6290 gen_helper_mtc0_srsconf1(tcg_env, arg); 6291 register_name = "SRSConf1"; 6292 break; 6293 case CP0_REG06__SRSCONF2: 6294 check_insn(ctx, ISA_MIPS_R2); 6295 gen_helper_mtc0_srsconf2(tcg_env, arg); 6296 register_name = "SRSConf2"; 6297 break; 6298 case CP0_REG06__SRSCONF3: 6299 check_insn(ctx, ISA_MIPS_R2); 6300 gen_helper_mtc0_srsconf3(tcg_env, arg); 6301 register_name = "SRSConf3"; 6302 break; 6303 case CP0_REG06__SRSCONF4: 6304 check_insn(ctx, ISA_MIPS_R2); 6305 gen_helper_mtc0_srsconf4(tcg_env, arg); 6306 register_name = "SRSConf4"; 6307 break; 6308 case CP0_REG06__PWCTL: 6309 check_pw(ctx); 6310 gen_helper_mtc0_pwctl(tcg_env, arg); 6311 register_name = "PWCtl"; 6312 break; 6313 default: 6314 goto cp0_unimplemented; 6315 } 6316 break; 6317 case CP0_REGISTER_07: 6318 switch (sel) { 6319 case CP0_REG07__HWRENA: 6320 check_insn(ctx, ISA_MIPS_R2); 6321 gen_helper_mtc0_hwrena(tcg_env, arg); 6322 ctx->base.is_jmp = DISAS_STOP; 6323 register_name = "HWREna"; 6324 break; 6325 default: 6326 goto cp0_unimplemented; 6327 } 6328 break; 6329 case CP0_REGISTER_08: 6330 switch (sel) { 6331 case CP0_REG08__BADVADDR: 6332 /* ignored */ 6333 register_name = "BadVAddr"; 6334 break; 6335 case CP0_REG08__BADINSTR: 6336 /* ignored */ 6337 register_name = "BadInstr"; 6338 break; 6339 case CP0_REG08__BADINSTRP: 6340 /* ignored */ 6341 register_name = "BadInstrP"; 6342 break; 6343 case CP0_REG08__BADINSTRX: 6344 /* ignored */ 6345 register_name = "BadInstrX"; 6346 break; 6347 default: 6348 goto cp0_unimplemented; 6349 } 6350 break; 6351 case CP0_REGISTER_09: 6352 switch (sel) { 6353 case CP0_REG09__COUNT: 6354 gen_helper_mtc0_count(tcg_env, arg); 6355 register_name = "Count"; 6356 break; 6357 default: 6358 goto cp0_unimplemented; 6359 } 6360 break; 6361 case CP0_REGISTER_10: 6362 switch (sel) { 6363 case CP0_REG10__ENTRYHI: 6364 gen_helper_mtc0_entryhi(tcg_env, arg); 6365 register_name = "EntryHi"; 6366 break; 6367 default: 6368 goto cp0_unimplemented; 6369 } 6370 break; 6371 case CP0_REGISTER_11: 6372 switch (sel) { 6373 case CP0_REG11__COMPARE: 6374 gen_helper_mtc0_compare(tcg_env, arg); 6375 register_name = "Compare"; 6376 break; 6377 /* 6,7 are implementation dependent */ 6378 default: 6379 goto cp0_unimplemented; 6380 } 6381 break; 6382 case CP0_REGISTER_12: 6383 switch (sel) { 6384 case CP0_REG12__STATUS: 6385 save_cpu_state(ctx, 1); 6386 gen_helper_mtc0_status(tcg_env, arg); 6387 /* DISAS_STOP isn't good enough here, hflags may have changed. */ 6388 gen_save_pc(ctx->base.pc_next + 4); 6389 ctx->base.is_jmp = DISAS_EXIT; 6390 register_name = "Status"; 6391 break; 6392 case CP0_REG12__INTCTL: 6393 check_insn(ctx, ISA_MIPS_R2); 6394 gen_helper_mtc0_intctl(tcg_env, arg); 6395 /* Stop translation as we may have switched the execution mode */ 6396 ctx->base.is_jmp = DISAS_STOP; 6397 register_name = "IntCtl"; 6398 break; 6399 case CP0_REG12__SRSCTL: 6400 check_insn(ctx, ISA_MIPS_R2); 6401 gen_helper_mtc0_srsctl(tcg_env, arg); 6402 /* Stop translation as we may have switched the execution mode */ 6403 ctx->base.is_jmp = DISAS_STOP; 6404 register_name = "SRSCtl"; 6405 break; 6406 case CP0_REG12__SRSMAP: 6407 check_insn(ctx, ISA_MIPS_R2); 6408 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); 6409 /* Stop translation as we may have switched the execution mode */ 6410 ctx->base.is_jmp = DISAS_STOP; 6411 register_name = "SRSMap"; 6412 break; 6413 default: 6414 goto cp0_unimplemented; 6415 } 6416 break; 6417 case CP0_REGISTER_13: 6418 switch (sel) { 6419 case CP0_REG13__CAUSE: 6420 save_cpu_state(ctx, 1); 6421 gen_helper_mtc0_cause(tcg_env, arg); 6422 /* 6423 * Stop translation as we may have triggered an interrupt. 6424 * DISAS_STOP isn't sufficient, we need to ensure we break out of 6425 * translated code to check for pending interrupts. 6426 */ 6427 gen_save_pc(ctx->base.pc_next + 4); 6428 ctx->base.is_jmp = DISAS_EXIT; 6429 register_name = "Cause"; 6430 break; 6431 default: 6432 goto cp0_unimplemented; 6433 } 6434 break; 6435 case CP0_REGISTER_14: 6436 switch (sel) { 6437 case CP0_REG14__EPC: 6438 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC)); 6439 register_name = "EPC"; 6440 break; 6441 default: 6442 goto cp0_unimplemented; 6443 } 6444 break; 6445 case CP0_REGISTER_15: 6446 switch (sel) { 6447 case CP0_REG15__PRID: 6448 /* ignored */ 6449 register_name = "PRid"; 6450 break; 6451 case CP0_REG15__EBASE: 6452 check_insn(ctx, ISA_MIPS_R2); 6453 gen_helper_mtc0_ebase(tcg_env, arg); 6454 register_name = "EBase"; 6455 break; 6456 default: 6457 goto cp0_unimplemented; 6458 } 6459 break; 6460 case CP0_REGISTER_16: 6461 switch (sel) { 6462 case CP0_REG16__CONFIG: 6463 gen_helper_mtc0_config0(tcg_env, arg); 6464 register_name = "Config"; 6465 /* Stop translation as we may have switched the execution mode */ 6466 ctx->base.is_jmp = DISAS_STOP; 6467 break; 6468 case CP0_REG16__CONFIG1: 6469 /* ignored, read only */ 6470 register_name = "Config1"; 6471 break; 6472 case CP0_REG16__CONFIG2: 6473 gen_helper_mtc0_config2(tcg_env, arg); 6474 register_name = "Config2"; 6475 /* Stop translation as we may have switched the execution mode */ 6476 ctx->base.is_jmp = DISAS_STOP; 6477 break; 6478 case CP0_REG16__CONFIG3: 6479 gen_helper_mtc0_config3(tcg_env, arg); 6480 register_name = "Config3"; 6481 /* Stop translation as we may have switched the execution mode */ 6482 ctx->base.is_jmp = DISAS_STOP; 6483 break; 6484 case CP0_REG16__CONFIG4: 6485 gen_helper_mtc0_config4(tcg_env, arg); 6486 register_name = "Config4"; 6487 ctx->base.is_jmp = DISAS_STOP; 6488 break; 6489 case CP0_REG16__CONFIG5: 6490 gen_helper_mtc0_config5(tcg_env, arg); 6491 register_name = "Config5"; 6492 /* Stop translation as we may have switched the execution mode */ 6493 ctx->base.is_jmp = DISAS_STOP; 6494 break; 6495 /* 6,7 are implementation dependent */ 6496 case CP0_REG16__CONFIG6: 6497 /* ignored */ 6498 register_name = "Config6"; 6499 break; 6500 case CP0_REG16__CONFIG7: 6501 /* ignored */ 6502 register_name = "Config7"; 6503 break; 6504 default: 6505 register_name = "Invalid config selector"; 6506 goto cp0_unimplemented; 6507 } 6508 break; 6509 case CP0_REGISTER_17: 6510 switch (sel) { 6511 case CP0_REG17__LLADDR: 6512 gen_helper_mtc0_lladdr(tcg_env, arg); 6513 register_name = "LLAddr"; 6514 break; 6515 case CP0_REG17__MAAR: 6516 CP0_CHECK(ctx->mrp); 6517 gen_helper_mtc0_maar(tcg_env, arg); 6518 register_name = "MAAR"; 6519 break; 6520 case CP0_REG17__MAARI: 6521 CP0_CHECK(ctx->mrp); 6522 gen_helper_mtc0_maari(tcg_env, arg); 6523 register_name = "MAARI"; 6524 break; 6525 default: 6526 goto cp0_unimplemented; 6527 } 6528 break; 6529 case CP0_REGISTER_18: 6530 switch (sel) { 6531 case CP0_REG18__WATCHLO0: 6532 case CP0_REG18__WATCHLO1: 6533 case CP0_REG18__WATCHLO2: 6534 case CP0_REG18__WATCHLO3: 6535 case CP0_REG18__WATCHLO4: 6536 case CP0_REG18__WATCHLO5: 6537 case CP0_REG18__WATCHLO6: 6538 case CP0_REG18__WATCHLO7: 6539 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 6540 gen_helper_0e1i(mtc0_watchlo, arg, sel); 6541 register_name = "WatchLo"; 6542 break; 6543 default: 6544 goto cp0_unimplemented; 6545 } 6546 break; 6547 case CP0_REGISTER_19: 6548 switch (sel) { 6549 case CP0_REG19__WATCHHI0: 6550 case CP0_REG19__WATCHHI1: 6551 case CP0_REG19__WATCHHI2: 6552 case CP0_REG19__WATCHHI3: 6553 case CP0_REG19__WATCHHI4: 6554 case CP0_REG19__WATCHHI5: 6555 case CP0_REG19__WATCHHI6: 6556 case CP0_REG19__WATCHHI7: 6557 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 6558 gen_helper_0e1i(mtc0_watchhi, arg, sel); 6559 register_name = "WatchHi"; 6560 break; 6561 default: 6562 goto cp0_unimplemented; 6563 } 6564 break; 6565 case CP0_REGISTER_20: 6566 switch (sel) { 6567 case CP0_REG20__XCONTEXT: 6568 #if defined(TARGET_MIPS64) 6569 check_insn(ctx, ISA_MIPS3); 6570 gen_helper_mtc0_xcontext(tcg_env, arg); 6571 register_name = "XContext"; 6572 break; 6573 #endif 6574 default: 6575 goto cp0_unimplemented; 6576 } 6577 break; 6578 case CP0_REGISTER_21: 6579 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 6580 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 6581 switch (sel) { 6582 case 0: 6583 gen_helper_mtc0_framemask(tcg_env, arg); 6584 register_name = "Framemask"; 6585 break; 6586 default: 6587 goto cp0_unimplemented; 6588 } 6589 break; 6590 case CP0_REGISTER_22: 6591 /* ignored */ 6592 register_name = "Diagnostic"; /* implementation dependent */ 6593 break; 6594 case CP0_REGISTER_23: 6595 switch (sel) { 6596 case CP0_REG23__DEBUG: 6597 gen_helper_mtc0_debug(tcg_env, arg); /* EJTAG support */ 6598 /* DISAS_STOP isn't good enough here, hflags may have changed. */ 6599 gen_save_pc(ctx->base.pc_next + 4); 6600 ctx->base.is_jmp = DISAS_EXIT; 6601 register_name = "Debug"; 6602 break; 6603 case CP0_REG23__TRACECONTROL: 6604 /* PDtrace support */ 6605 /* gen_helper_mtc0_tracecontrol(tcg_env, arg); */ 6606 register_name = "TraceControl"; 6607 /* Stop translation as we may have switched the execution mode */ 6608 ctx->base.is_jmp = DISAS_STOP; 6609 goto cp0_unimplemented; 6610 case CP0_REG23__TRACECONTROL2: 6611 /* PDtrace support */ 6612 /* gen_helper_mtc0_tracecontrol2(tcg_env, arg); */ 6613 register_name = "TraceControl2"; 6614 /* Stop translation as we may have switched the execution mode */ 6615 ctx->base.is_jmp = DISAS_STOP; 6616 goto cp0_unimplemented; 6617 case CP0_REG23__USERTRACEDATA1: 6618 /* Stop translation as we may have switched the execution mode */ 6619 ctx->base.is_jmp = DISAS_STOP; 6620 /* PDtrace support */ 6621 /* gen_helper_mtc0_usertracedata1(tcg_env, arg);*/ 6622 register_name = "UserTraceData"; 6623 /* Stop translation as we may have switched the execution mode */ 6624 ctx->base.is_jmp = DISAS_STOP; 6625 goto cp0_unimplemented; 6626 case CP0_REG23__TRACEIBPC: 6627 /* PDtrace support */ 6628 /* gen_helper_mtc0_traceibpc(tcg_env, arg); */ 6629 /* Stop translation as we may have switched the execution mode */ 6630 ctx->base.is_jmp = DISAS_STOP; 6631 register_name = "TraceIBPC"; 6632 goto cp0_unimplemented; 6633 case CP0_REG23__TRACEDBPC: 6634 /* PDtrace support */ 6635 /* gen_helper_mtc0_tracedbpc(tcg_env, arg); */ 6636 /* Stop translation as we may have switched the execution mode */ 6637 ctx->base.is_jmp = DISAS_STOP; 6638 register_name = "TraceDBPC"; 6639 goto cp0_unimplemented; 6640 default: 6641 goto cp0_unimplemented; 6642 } 6643 break; 6644 case CP0_REGISTER_24: 6645 switch (sel) { 6646 case CP0_REG24__DEPC: 6647 /* EJTAG support */ 6648 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC)); 6649 register_name = "DEPC"; 6650 break; 6651 default: 6652 goto cp0_unimplemented; 6653 } 6654 break; 6655 case CP0_REGISTER_25: 6656 switch (sel) { 6657 case CP0_REG25__PERFCTL0: 6658 gen_helper_mtc0_performance0(tcg_env, arg); 6659 register_name = "Performance0"; 6660 break; 6661 case CP0_REG25__PERFCNT0: 6662 /* gen_helper_mtc0_performance1(arg); */ 6663 register_name = "Performance1"; 6664 goto cp0_unimplemented; 6665 case CP0_REG25__PERFCTL1: 6666 /* gen_helper_mtc0_performance2(arg); */ 6667 register_name = "Performance2"; 6668 goto cp0_unimplemented; 6669 case CP0_REG25__PERFCNT1: 6670 /* gen_helper_mtc0_performance3(arg); */ 6671 register_name = "Performance3"; 6672 goto cp0_unimplemented; 6673 case CP0_REG25__PERFCTL2: 6674 /* gen_helper_mtc0_performance4(arg); */ 6675 register_name = "Performance4"; 6676 goto cp0_unimplemented; 6677 case CP0_REG25__PERFCNT2: 6678 /* gen_helper_mtc0_performance5(arg); */ 6679 register_name = "Performance5"; 6680 goto cp0_unimplemented; 6681 case CP0_REG25__PERFCTL3: 6682 /* gen_helper_mtc0_performance6(arg); */ 6683 register_name = "Performance6"; 6684 goto cp0_unimplemented; 6685 case CP0_REG25__PERFCNT3: 6686 /* gen_helper_mtc0_performance7(arg); */ 6687 register_name = "Performance7"; 6688 goto cp0_unimplemented; 6689 default: 6690 goto cp0_unimplemented; 6691 } 6692 break; 6693 case CP0_REGISTER_26: 6694 switch (sel) { 6695 case CP0_REG26__ERRCTL: 6696 gen_helper_mtc0_errctl(tcg_env, arg); 6697 ctx->base.is_jmp = DISAS_STOP; 6698 register_name = "ErrCtl"; 6699 break; 6700 default: 6701 goto cp0_unimplemented; 6702 } 6703 break; 6704 case CP0_REGISTER_27: 6705 switch (sel) { 6706 case CP0_REG27__CACHERR: 6707 /* ignored */ 6708 register_name = "CacheErr"; 6709 break; 6710 default: 6711 goto cp0_unimplemented; 6712 } 6713 break; 6714 case CP0_REGISTER_28: 6715 switch (sel) { 6716 case CP0_REG28__TAGLO: 6717 case CP0_REG28__TAGLO1: 6718 case CP0_REG28__TAGLO2: 6719 case CP0_REG28__TAGLO3: 6720 gen_helper_mtc0_taglo(tcg_env, arg); 6721 register_name = "TagLo"; 6722 break; 6723 case CP0_REG28__DATALO: 6724 case CP0_REG28__DATALO1: 6725 case CP0_REG28__DATALO2: 6726 case CP0_REG28__DATALO3: 6727 gen_helper_mtc0_datalo(tcg_env, arg); 6728 register_name = "DataLo"; 6729 break; 6730 default: 6731 goto cp0_unimplemented; 6732 } 6733 break; 6734 case CP0_REGISTER_29: 6735 switch (sel) { 6736 case CP0_REG29__TAGHI: 6737 case CP0_REG29__TAGHI1: 6738 case CP0_REG29__TAGHI2: 6739 case CP0_REG29__TAGHI3: 6740 gen_helper_mtc0_taghi(tcg_env, arg); 6741 register_name = "TagHi"; 6742 break; 6743 case CP0_REG29__DATAHI: 6744 case CP0_REG29__DATAHI1: 6745 case CP0_REG29__DATAHI2: 6746 case CP0_REG29__DATAHI3: 6747 gen_helper_mtc0_datahi(tcg_env, arg); 6748 register_name = "DataHi"; 6749 break; 6750 default: 6751 register_name = "invalid sel"; 6752 goto cp0_unimplemented; 6753 } 6754 break; 6755 case CP0_REGISTER_30: 6756 switch (sel) { 6757 case CP0_REG30__ERROREPC: 6758 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); 6759 register_name = "ErrorEPC"; 6760 break; 6761 default: 6762 goto cp0_unimplemented; 6763 } 6764 break; 6765 case CP0_REGISTER_31: 6766 switch (sel) { 6767 case CP0_REG31__DESAVE: 6768 /* EJTAG support */ 6769 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); 6770 register_name = "DESAVE"; 6771 break; 6772 case CP0_REG31__KSCRATCH1: 6773 case CP0_REG31__KSCRATCH2: 6774 case CP0_REG31__KSCRATCH3: 6775 case CP0_REG31__KSCRATCH4: 6776 case CP0_REG31__KSCRATCH5: 6777 case CP0_REG31__KSCRATCH6: 6778 CP0_CHECK(ctx->kscrexist & (1 << sel)); 6779 tcg_gen_st_tl(arg, tcg_env, 6780 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); 6781 register_name = "KScratch"; 6782 break; 6783 default: 6784 goto cp0_unimplemented; 6785 } 6786 break; 6787 default: 6788 goto cp0_unimplemented; 6789 } 6790 trace_mips_translate_c0("mtc0", register_name, reg, sel); 6791 6792 /* For simplicity assume that all writes can cause interrupts. */ 6793 if (icount) { 6794 /* 6795 * DISAS_STOP isn't sufficient, we need to ensure we break out of 6796 * translated code to check for pending interrupts. 6797 */ 6798 gen_save_pc(ctx->base.pc_next + 4); 6799 ctx->base.is_jmp = DISAS_EXIT; 6800 } 6801 return; 6802 6803 cp0_unimplemented: 6804 qemu_log_mask(LOG_UNIMP, "mtc0 %s (reg %d sel %d)\n", 6805 register_name, reg, sel); 6806 } 6807 6808 #if defined(TARGET_MIPS64) 6809 static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) 6810 { 6811 const char *register_name = "invalid"; 6812 6813 if (sel != 0) { 6814 check_insn(ctx, ISA_MIPS_R1); 6815 } 6816 6817 switch (reg) { 6818 case CP0_REGISTER_00: 6819 switch (sel) { 6820 case CP0_REG00__INDEX: 6821 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index)); 6822 register_name = "Index"; 6823 break; 6824 case CP0_REG00__MVPCONTROL: 6825 CP0_CHECK(ctx->insn_flags & ASE_MT); 6826 gen_helper_mfc0_mvpcontrol(arg, tcg_env); 6827 register_name = "MVPControl"; 6828 break; 6829 case CP0_REG00__MVPCONF0: 6830 CP0_CHECK(ctx->insn_flags & ASE_MT); 6831 gen_helper_mfc0_mvpconf0(arg, tcg_env); 6832 register_name = "MVPConf0"; 6833 break; 6834 case CP0_REG00__MVPCONF1: 6835 CP0_CHECK(ctx->insn_flags & ASE_MT); 6836 gen_helper_mfc0_mvpconf1(arg, tcg_env); 6837 register_name = "MVPConf1"; 6838 break; 6839 case CP0_REG00__VPCONTROL: 6840 CP0_CHECK(ctx->vp); 6841 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl)); 6842 register_name = "VPControl"; 6843 break; 6844 default: 6845 goto cp0_unimplemented; 6846 } 6847 break; 6848 case CP0_REGISTER_01: 6849 switch (sel) { 6850 case CP0_REG01__RANDOM: 6851 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 6852 gen_helper_mfc0_random(arg, tcg_env); 6853 register_name = "Random"; 6854 break; 6855 case CP0_REG01__VPECONTROL: 6856 CP0_CHECK(ctx->insn_flags & ASE_MT); 6857 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl)); 6858 register_name = "VPEControl"; 6859 break; 6860 case CP0_REG01__VPECONF0: 6861 CP0_CHECK(ctx->insn_flags & ASE_MT); 6862 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0)); 6863 register_name = "VPEConf0"; 6864 break; 6865 case CP0_REG01__VPECONF1: 6866 CP0_CHECK(ctx->insn_flags & ASE_MT); 6867 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1)); 6868 register_name = "VPEConf1"; 6869 break; 6870 case CP0_REG01__YQMASK: 6871 CP0_CHECK(ctx->insn_flags & ASE_MT); 6872 tcg_gen_ld_tl(arg, tcg_env, 6873 offsetof(CPUMIPSState, CP0_YQMask)); 6874 register_name = "YQMask"; 6875 break; 6876 case CP0_REG01__VPESCHEDULE: 6877 CP0_CHECK(ctx->insn_flags & ASE_MT); 6878 tcg_gen_ld_tl(arg, tcg_env, 6879 offsetof(CPUMIPSState, CP0_VPESchedule)); 6880 register_name = "VPESchedule"; 6881 break; 6882 case CP0_REG01__VPESCHEFBACK: 6883 CP0_CHECK(ctx->insn_flags & ASE_MT); 6884 tcg_gen_ld_tl(arg, tcg_env, 6885 offsetof(CPUMIPSState, CP0_VPEScheFBack)); 6886 register_name = "VPEScheFBack"; 6887 break; 6888 case CP0_REG01__VPEOPT: 6889 CP0_CHECK(ctx->insn_flags & ASE_MT); 6890 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt)); 6891 register_name = "VPEOpt"; 6892 break; 6893 default: 6894 goto cp0_unimplemented; 6895 } 6896 break; 6897 case CP0_REGISTER_02: 6898 switch (sel) { 6899 case CP0_REG02__ENTRYLO0: 6900 tcg_gen_ld_tl(arg, tcg_env, 6901 offsetof(CPUMIPSState, CP0_EntryLo0)); 6902 register_name = "EntryLo0"; 6903 break; 6904 case CP0_REG02__TCSTATUS: 6905 CP0_CHECK(ctx->insn_flags & ASE_MT); 6906 gen_helper_mfc0_tcstatus(arg, tcg_env); 6907 register_name = "TCStatus"; 6908 break; 6909 case CP0_REG02__TCBIND: 6910 CP0_CHECK(ctx->insn_flags & ASE_MT); 6911 gen_helper_mfc0_tcbind(arg, tcg_env); 6912 register_name = "TCBind"; 6913 break; 6914 case CP0_REG02__TCRESTART: 6915 CP0_CHECK(ctx->insn_flags & ASE_MT); 6916 gen_helper_dmfc0_tcrestart(arg, tcg_env); 6917 register_name = "TCRestart"; 6918 break; 6919 case CP0_REG02__TCHALT: 6920 CP0_CHECK(ctx->insn_flags & ASE_MT); 6921 gen_helper_dmfc0_tchalt(arg, tcg_env); 6922 register_name = "TCHalt"; 6923 break; 6924 case CP0_REG02__TCCONTEXT: 6925 CP0_CHECK(ctx->insn_flags & ASE_MT); 6926 gen_helper_dmfc0_tccontext(arg, tcg_env); 6927 register_name = "TCContext"; 6928 break; 6929 case CP0_REG02__TCSCHEDULE: 6930 CP0_CHECK(ctx->insn_flags & ASE_MT); 6931 gen_helper_dmfc0_tcschedule(arg, tcg_env); 6932 register_name = "TCSchedule"; 6933 break; 6934 case CP0_REG02__TCSCHEFBACK: 6935 CP0_CHECK(ctx->insn_flags & ASE_MT); 6936 gen_helper_dmfc0_tcschefback(arg, tcg_env); 6937 register_name = "TCScheFBack"; 6938 break; 6939 default: 6940 goto cp0_unimplemented; 6941 } 6942 break; 6943 case CP0_REGISTER_03: 6944 switch (sel) { 6945 case CP0_REG03__ENTRYLO1: 6946 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EntryLo1)); 6947 register_name = "EntryLo1"; 6948 break; 6949 case CP0_REG03__GLOBALNUM: 6950 CP0_CHECK(ctx->vp); 6951 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber)); 6952 register_name = "GlobalNumber"; 6953 break; 6954 default: 6955 goto cp0_unimplemented; 6956 } 6957 break; 6958 case CP0_REGISTER_04: 6959 switch (sel) { 6960 case CP0_REG04__CONTEXT: 6961 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_Context)); 6962 register_name = "Context"; 6963 break; 6964 case CP0_REG04__CONTEXTCONFIG: 6965 /* SmartMIPS ASE */ 6966 /* gen_helper_dmfc0_contextconfig(arg); */ 6967 register_name = "ContextConfig"; 6968 goto cp0_unimplemented; 6969 case CP0_REG04__USERLOCAL: 6970 CP0_CHECK(ctx->ulri); 6971 tcg_gen_ld_tl(arg, tcg_env, 6972 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 6973 register_name = "UserLocal"; 6974 break; 6975 case CP0_REG04__MMID: 6976 CP0_CHECK(ctx->mi); 6977 gen_helper_mtc0_memorymapid(tcg_env, arg); 6978 register_name = "MMID"; 6979 break; 6980 default: 6981 goto cp0_unimplemented; 6982 } 6983 break; 6984 case CP0_REGISTER_05: 6985 switch (sel) { 6986 case CP0_REG05__PAGEMASK: 6987 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask)); 6988 register_name = "PageMask"; 6989 break; 6990 case CP0_REG05__PAGEGRAIN: 6991 check_insn(ctx, ISA_MIPS_R2); 6992 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); 6993 register_name = "PageGrain"; 6994 break; 6995 case CP0_REG05__SEGCTL0: 6996 CP0_CHECK(ctx->sc); 6997 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl0)); 6998 register_name = "SegCtl0"; 6999 break; 7000 case CP0_REG05__SEGCTL1: 7001 CP0_CHECK(ctx->sc); 7002 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl1)); 7003 register_name = "SegCtl1"; 7004 break; 7005 case CP0_REG05__SEGCTL2: 7006 CP0_CHECK(ctx->sc); 7007 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl2)); 7008 register_name = "SegCtl2"; 7009 break; 7010 case CP0_REG05__PWBASE: 7011 check_pw(ctx); 7012 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWBase)); 7013 register_name = "PWBase"; 7014 break; 7015 case CP0_REG05__PWFIELD: 7016 check_pw(ctx); 7017 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWField)); 7018 register_name = "PWField"; 7019 break; 7020 case CP0_REG05__PWSIZE: 7021 check_pw(ctx); 7022 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWSize)); 7023 register_name = "PWSize"; 7024 break; 7025 default: 7026 goto cp0_unimplemented; 7027 } 7028 break; 7029 case CP0_REGISTER_06: 7030 switch (sel) { 7031 case CP0_REG06__WIRED: 7032 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired)); 7033 register_name = "Wired"; 7034 break; 7035 case CP0_REG06__SRSCONF0: 7036 check_insn(ctx, ISA_MIPS_R2); 7037 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); 7038 register_name = "SRSConf0"; 7039 break; 7040 case CP0_REG06__SRSCONF1: 7041 check_insn(ctx, ISA_MIPS_R2); 7042 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); 7043 register_name = "SRSConf1"; 7044 break; 7045 case CP0_REG06__SRSCONF2: 7046 check_insn(ctx, ISA_MIPS_R2); 7047 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); 7048 register_name = "SRSConf2"; 7049 break; 7050 case CP0_REG06__SRSCONF3: 7051 check_insn(ctx, ISA_MIPS_R2); 7052 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); 7053 register_name = "SRSConf3"; 7054 break; 7055 case CP0_REG06__SRSCONF4: 7056 check_insn(ctx, ISA_MIPS_R2); 7057 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); 7058 register_name = "SRSConf4"; 7059 break; 7060 case CP0_REG06__PWCTL: 7061 check_pw(ctx); 7062 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl)); 7063 register_name = "PWCtl"; 7064 break; 7065 default: 7066 goto cp0_unimplemented; 7067 } 7068 break; 7069 case CP0_REGISTER_07: 7070 switch (sel) { 7071 case CP0_REG07__HWRENA: 7072 check_insn(ctx, ISA_MIPS_R2); 7073 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); 7074 register_name = "HWREna"; 7075 break; 7076 default: 7077 goto cp0_unimplemented; 7078 } 7079 break; 7080 case CP0_REGISTER_08: 7081 switch (sel) { 7082 case CP0_REG08__BADVADDR: 7083 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_BadVAddr)); 7084 register_name = "BadVAddr"; 7085 break; 7086 case CP0_REG08__BADINSTR: 7087 CP0_CHECK(ctx->bi); 7088 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr)); 7089 register_name = "BadInstr"; 7090 break; 7091 case CP0_REG08__BADINSTRP: 7092 CP0_CHECK(ctx->bp); 7093 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP)); 7094 register_name = "BadInstrP"; 7095 break; 7096 case CP0_REG08__BADINSTRX: 7097 CP0_CHECK(ctx->bi); 7098 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX)); 7099 tcg_gen_andi_tl(arg, arg, ~0xffff); 7100 register_name = "BadInstrX"; 7101 break; 7102 default: 7103 goto cp0_unimplemented; 7104 } 7105 break; 7106 case CP0_REGISTER_09: 7107 switch (sel) { 7108 case CP0_REG09__COUNT: 7109 /* Mark as an IO operation because we read the time. */ 7110 translator_io_start(&ctx->base); 7111 gen_helper_mfc0_count(arg, tcg_env); 7112 /* 7113 * Break the TB to be able to take timer interrupts immediately 7114 * after reading count. DISAS_STOP isn't sufficient, we need to 7115 * ensure we break completely out of translated code. 7116 */ 7117 gen_save_pc(ctx->base.pc_next + 4); 7118 ctx->base.is_jmp = DISAS_EXIT; 7119 register_name = "Count"; 7120 break; 7121 default: 7122 goto cp0_unimplemented; 7123 } 7124 break; 7125 case CP0_REGISTER_10: 7126 switch (sel) { 7127 case CP0_REG10__ENTRYHI: 7128 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EntryHi)); 7129 register_name = "EntryHi"; 7130 break; 7131 default: 7132 goto cp0_unimplemented; 7133 } 7134 break; 7135 case CP0_REGISTER_11: 7136 switch (sel) { 7137 case CP0_REG11__COMPARE: 7138 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare)); 7139 register_name = "Compare"; 7140 break; 7141 /* 6,7 are implementation dependent */ 7142 default: 7143 goto cp0_unimplemented; 7144 } 7145 break; 7146 case CP0_REGISTER_12: 7147 switch (sel) { 7148 case CP0_REG12__STATUS: 7149 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status)); 7150 register_name = "Status"; 7151 break; 7152 case CP0_REG12__INTCTL: 7153 check_insn(ctx, ISA_MIPS_R2); 7154 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); 7155 register_name = "IntCtl"; 7156 break; 7157 case CP0_REG12__SRSCTL: 7158 check_insn(ctx, ISA_MIPS_R2); 7159 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); 7160 register_name = "SRSCtl"; 7161 break; 7162 case CP0_REG12__SRSMAP: 7163 check_insn(ctx, ISA_MIPS_R2); 7164 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); 7165 register_name = "SRSMap"; 7166 break; 7167 default: 7168 goto cp0_unimplemented; 7169 } 7170 break; 7171 case CP0_REGISTER_13: 7172 switch (sel) { 7173 case CP0_REG13__CAUSE: 7174 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause)); 7175 register_name = "Cause"; 7176 break; 7177 default: 7178 goto cp0_unimplemented; 7179 } 7180 break; 7181 case CP0_REGISTER_14: 7182 switch (sel) { 7183 case CP0_REG14__EPC: 7184 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC)); 7185 register_name = "EPC"; 7186 break; 7187 default: 7188 goto cp0_unimplemented; 7189 } 7190 break; 7191 case CP0_REGISTER_15: 7192 switch (sel) { 7193 case CP0_REG15__PRID: 7194 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid)); 7195 register_name = "PRid"; 7196 break; 7197 case CP0_REG15__EBASE: 7198 check_insn(ctx, ISA_MIPS_R2); 7199 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EBase)); 7200 register_name = "EBase"; 7201 break; 7202 case CP0_REG15__CMGCRBASE: 7203 check_insn(ctx, ISA_MIPS_R2); 7204 CP0_CHECK(ctx->cmgcr); 7205 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_CMGCRBase)); 7206 register_name = "CMGCRBase"; 7207 break; 7208 default: 7209 goto cp0_unimplemented; 7210 } 7211 break; 7212 case CP0_REGISTER_16: 7213 switch (sel) { 7214 case CP0_REG16__CONFIG: 7215 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0)); 7216 register_name = "Config"; 7217 break; 7218 case CP0_REG16__CONFIG1: 7219 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1)); 7220 register_name = "Config1"; 7221 break; 7222 case CP0_REG16__CONFIG2: 7223 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2)); 7224 register_name = "Config2"; 7225 break; 7226 case CP0_REG16__CONFIG3: 7227 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3)); 7228 register_name = "Config3"; 7229 break; 7230 case CP0_REG16__CONFIG4: 7231 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4)); 7232 register_name = "Config4"; 7233 break; 7234 case CP0_REG16__CONFIG5: 7235 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5)); 7236 register_name = "Config5"; 7237 break; 7238 /* 6,7 are implementation dependent */ 7239 case CP0_REG16__CONFIG6: 7240 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6)); 7241 register_name = "Config6"; 7242 break; 7243 case CP0_REG16__CONFIG7: 7244 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7)); 7245 register_name = "Config7"; 7246 break; 7247 default: 7248 goto cp0_unimplemented; 7249 } 7250 break; 7251 case CP0_REGISTER_17: 7252 switch (sel) { 7253 case CP0_REG17__LLADDR: 7254 gen_helper_dmfc0_lladdr(arg, tcg_env); 7255 register_name = "LLAddr"; 7256 break; 7257 case CP0_REG17__MAAR: 7258 CP0_CHECK(ctx->mrp); 7259 gen_helper_dmfc0_maar(arg, tcg_env); 7260 register_name = "MAAR"; 7261 break; 7262 case CP0_REG17__MAARI: 7263 CP0_CHECK(ctx->mrp); 7264 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI)); 7265 register_name = "MAARI"; 7266 break; 7267 default: 7268 goto cp0_unimplemented; 7269 } 7270 break; 7271 case CP0_REGISTER_18: 7272 switch (sel) { 7273 case CP0_REG18__WATCHLO0: 7274 case CP0_REG18__WATCHLO1: 7275 case CP0_REG18__WATCHLO2: 7276 case CP0_REG18__WATCHLO3: 7277 case CP0_REG18__WATCHLO4: 7278 case CP0_REG18__WATCHLO5: 7279 case CP0_REG18__WATCHLO6: 7280 case CP0_REG18__WATCHLO7: 7281 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 7282 gen_helper_1e0i(dmfc0_watchlo, arg, sel); 7283 register_name = "WatchLo"; 7284 break; 7285 default: 7286 goto cp0_unimplemented; 7287 } 7288 break; 7289 case CP0_REGISTER_19: 7290 switch (sel) { 7291 case CP0_REG19__WATCHHI0: 7292 case CP0_REG19__WATCHHI1: 7293 case CP0_REG19__WATCHHI2: 7294 case CP0_REG19__WATCHHI3: 7295 case CP0_REG19__WATCHHI4: 7296 case CP0_REG19__WATCHHI5: 7297 case CP0_REG19__WATCHHI6: 7298 case CP0_REG19__WATCHHI7: 7299 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 7300 gen_helper_1e0i(dmfc0_watchhi, arg, sel); 7301 register_name = "WatchHi"; 7302 break; 7303 default: 7304 goto cp0_unimplemented; 7305 } 7306 break; 7307 case CP0_REGISTER_20: 7308 switch (sel) { 7309 case CP0_REG20__XCONTEXT: 7310 check_insn(ctx, ISA_MIPS3); 7311 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_XContext)); 7312 register_name = "XContext"; 7313 break; 7314 default: 7315 goto cp0_unimplemented; 7316 } 7317 break; 7318 case CP0_REGISTER_21: 7319 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 7320 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 7321 switch (sel) { 7322 case 0: 7323 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask)); 7324 register_name = "Framemask"; 7325 break; 7326 default: 7327 goto cp0_unimplemented; 7328 } 7329 break; 7330 case CP0_REGISTER_22: 7331 tcg_gen_movi_tl(arg, 0); /* unimplemented */ 7332 register_name = "'Diagnostic"; /* implementation dependent */ 7333 break; 7334 case CP0_REGISTER_23: 7335 switch (sel) { 7336 case CP0_REG23__DEBUG: 7337 gen_helper_mfc0_debug(arg, tcg_env); /* EJTAG support */ 7338 register_name = "Debug"; 7339 break; 7340 case CP0_REG23__TRACECONTROL: 7341 /* PDtrace support */ 7342 /* gen_helper_dmfc0_tracecontrol(arg, tcg_env); */ 7343 register_name = "TraceControl"; 7344 goto cp0_unimplemented; 7345 case CP0_REG23__TRACECONTROL2: 7346 /* PDtrace support */ 7347 /* gen_helper_dmfc0_tracecontrol2(arg, tcg_env); */ 7348 register_name = "TraceControl2"; 7349 goto cp0_unimplemented; 7350 case CP0_REG23__USERTRACEDATA1: 7351 /* PDtrace support */ 7352 /* gen_helper_dmfc0_usertracedata1(arg, tcg_env);*/ 7353 register_name = "UserTraceData1"; 7354 goto cp0_unimplemented; 7355 case CP0_REG23__TRACEIBPC: 7356 /* PDtrace support */ 7357 /* gen_helper_dmfc0_traceibpc(arg, tcg_env); */ 7358 register_name = "TraceIBPC"; 7359 goto cp0_unimplemented; 7360 case CP0_REG23__TRACEDBPC: 7361 /* PDtrace support */ 7362 /* gen_helper_dmfc0_tracedbpc(arg, tcg_env); */ 7363 register_name = "TraceDBPC"; 7364 goto cp0_unimplemented; 7365 default: 7366 goto cp0_unimplemented; 7367 } 7368 break; 7369 case CP0_REGISTER_24: 7370 switch (sel) { 7371 case CP0_REG24__DEPC: 7372 /* EJTAG support */ 7373 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC)); 7374 register_name = "DEPC"; 7375 break; 7376 default: 7377 goto cp0_unimplemented; 7378 } 7379 break; 7380 case CP0_REGISTER_25: 7381 switch (sel) { 7382 case CP0_REG25__PERFCTL0: 7383 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0)); 7384 register_name = "Performance0"; 7385 break; 7386 case CP0_REG25__PERFCNT0: 7387 /* gen_helper_dmfc0_performance1(arg); */ 7388 register_name = "Performance1"; 7389 goto cp0_unimplemented; 7390 case CP0_REG25__PERFCTL1: 7391 /* gen_helper_dmfc0_performance2(arg); */ 7392 register_name = "Performance2"; 7393 goto cp0_unimplemented; 7394 case CP0_REG25__PERFCNT1: 7395 /* gen_helper_dmfc0_performance3(arg); */ 7396 register_name = "Performance3"; 7397 goto cp0_unimplemented; 7398 case CP0_REG25__PERFCTL2: 7399 /* gen_helper_dmfc0_performance4(arg); */ 7400 register_name = "Performance4"; 7401 goto cp0_unimplemented; 7402 case CP0_REG25__PERFCNT2: 7403 /* gen_helper_dmfc0_performance5(arg); */ 7404 register_name = "Performance5"; 7405 goto cp0_unimplemented; 7406 case CP0_REG25__PERFCTL3: 7407 /* gen_helper_dmfc0_performance6(arg); */ 7408 register_name = "Performance6"; 7409 goto cp0_unimplemented; 7410 case CP0_REG25__PERFCNT3: 7411 /* gen_helper_dmfc0_performance7(arg); */ 7412 register_name = "Performance7"; 7413 goto cp0_unimplemented; 7414 default: 7415 goto cp0_unimplemented; 7416 } 7417 break; 7418 case CP0_REGISTER_26: 7419 switch (sel) { 7420 case CP0_REG26__ERRCTL: 7421 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl)); 7422 register_name = "ErrCtl"; 7423 break; 7424 default: 7425 goto cp0_unimplemented; 7426 } 7427 break; 7428 case CP0_REGISTER_27: 7429 switch (sel) { 7430 /* ignored */ 7431 case CP0_REG27__CACHERR: 7432 tcg_gen_movi_tl(arg, 0); /* unimplemented */ 7433 register_name = "CacheErr"; 7434 break; 7435 default: 7436 goto cp0_unimplemented; 7437 } 7438 break; 7439 case CP0_REGISTER_28: 7440 switch (sel) { 7441 case CP0_REG28__TAGLO: 7442 case CP0_REG28__TAGLO1: 7443 case CP0_REG28__TAGLO2: 7444 case CP0_REG28__TAGLO3: 7445 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo)); 7446 register_name = "TagLo"; 7447 break; 7448 case CP0_REG28__DATALO: 7449 case CP0_REG28__DATALO1: 7450 case CP0_REG28__DATALO2: 7451 case CP0_REG28__DATALO3: 7452 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo)); 7453 register_name = "DataLo"; 7454 break; 7455 default: 7456 goto cp0_unimplemented; 7457 } 7458 break; 7459 case CP0_REGISTER_29: 7460 switch (sel) { 7461 case CP0_REG29__TAGHI: 7462 case CP0_REG29__TAGHI1: 7463 case CP0_REG29__TAGHI2: 7464 case CP0_REG29__TAGHI3: 7465 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi)); 7466 register_name = "TagHi"; 7467 break; 7468 case CP0_REG29__DATAHI: 7469 case CP0_REG29__DATAHI1: 7470 case CP0_REG29__DATAHI2: 7471 case CP0_REG29__DATAHI3: 7472 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi)); 7473 register_name = "DataHi"; 7474 break; 7475 default: 7476 goto cp0_unimplemented; 7477 } 7478 break; 7479 case CP0_REGISTER_30: 7480 switch (sel) { 7481 case CP0_REG30__ERROREPC: 7482 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); 7483 register_name = "ErrorEPC"; 7484 break; 7485 default: 7486 goto cp0_unimplemented; 7487 } 7488 break; 7489 case CP0_REGISTER_31: 7490 switch (sel) { 7491 case CP0_REG31__DESAVE: 7492 /* EJTAG support */ 7493 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); 7494 register_name = "DESAVE"; 7495 break; 7496 case CP0_REG31__KSCRATCH1: 7497 case CP0_REG31__KSCRATCH2: 7498 case CP0_REG31__KSCRATCH3: 7499 case CP0_REG31__KSCRATCH4: 7500 case CP0_REG31__KSCRATCH5: 7501 case CP0_REG31__KSCRATCH6: 7502 CP0_CHECK(ctx->kscrexist & (1 << sel)); 7503 tcg_gen_ld_tl(arg, tcg_env, 7504 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); 7505 register_name = "KScratch"; 7506 break; 7507 default: 7508 goto cp0_unimplemented; 7509 } 7510 break; 7511 default: 7512 goto cp0_unimplemented; 7513 } 7514 trace_mips_translate_c0("dmfc0", register_name, reg, sel); 7515 return; 7516 7517 cp0_unimplemented: 7518 qemu_log_mask(LOG_UNIMP, "dmfc0 %s (reg %d sel %d)\n", 7519 register_name, reg, sel); 7520 gen_mfc0_unimplemented(ctx, arg); 7521 } 7522 7523 static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) 7524 { 7525 const char *register_name = "invalid"; 7526 bool icount; 7527 7528 if (sel != 0) { 7529 check_insn(ctx, ISA_MIPS_R1); 7530 } 7531 7532 icount = translator_io_start(&ctx->base); 7533 7534 switch (reg) { 7535 case CP0_REGISTER_00: 7536 switch (sel) { 7537 case CP0_REG00__INDEX: 7538 gen_helper_mtc0_index(tcg_env, arg); 7539 register_name = "Index"; 7540 break; 7541 case CP0_REG00__MVPCONTROL: 7542 CP0_CHECK(ctx->insn_flags & ASE_MT); 7543 gen_helper_mtc0_mvpcontrol(tcg_env, arg); 7544 register_name = "MVPControl"; 7545 break; 7546 case CP0_REG00__MVPCONF0: 7547 CP0_CHECK(ctx->insn_flags & ASE_MT); 7548 /* ignored */ 7549 register_name = "MVPConf0"; 7550 break; 7551 case CP0_REG00__MVPCONF1: 7552 CP0_CHECK(ctx->insn_flags & ASE_MT); 7553 /* ignored */ 7554 register_name = "MVPConf1"; 7555 break; 7556 case CP0_REG00__VPCONTROL: 7557 CP0_CHECK(ctx->vp); 7558 /* ignored */ 7559 register_name = "VPControl"; 7560 break; 7561 default: 7562 goto cp0_unimplemented; 7563 } 7564 break; 7565 case CP0_REGISTER_01: 7566 switch (sel) { 7567 case CP0_REG01__RANDOM: 7568 /* ignored */ 7569 register_name = "Random"; 7570 break; 7571 case CP0_REG01__VPECONTROL: 7572 CP0_CHECK(ctx->insn_flags & ASE_MT); 7573 gen_helper_mtc0_vpecontrol(tcg_env, arg); 7574 register_name = "VPEControl"; 7575 break; 7576 case CP0_REG01__VPECONF0: 7577 CP0_CHECK(ctx->insn_flags & ASE_MT); 7578 gen_helper_mtc0_vpeconf0(tcg_env, arg); 7579 register_name = "VPEConf0"; 7580 break; 7581 case CP0_REG01__VPECONF1: 7582 CP0_CHECK(ctx->insn_flags & ASE_MT); 7583 gen_helper_mtc0_vpeconf1(tcg_env, arg); 7584 register_name = "VPEConf1"; 7585 break; 7586 case CP0_REG01__YQMASK: 7587 CP0_CHECK(ctx->insn_flags & ASE_MT); 7588 gen_helper_mtc0_yqmask(tcg_env, arg); 7589 register_name = "YQMask"; 7590 break; 7591 case CP0_REG01__VPESCHEDULE: 7592 CP0_CHECK(ctx->insn_flags & ASE_MT); 7593 tcg_gen_st_tl(arg, tcg_env, 7594 offsetof(CPUMIPSState, CP0_VPESchedule)); 7595 register_name = "VPESchedule"; 7596 break; 7597 case CP0_REG01__VPESCHEFBACK: 7598 CP0_CHECK(ctx->insn_flags & ASE_MT); 7599 tcg_gen_st_tl(arg, tcg_env, 7600 offsetof(CPUMIPSState, CP0_VPEScheFBack)); 7601 register_name = "VPEScheFBack"; 7602 break; 7603 case CP0_REG01__VPEOPT: 7604 CP0_CHECK(ctx->insn_flags & ASE_MT); 7605 gen_helper_mtc0_vpeopt(tcg_env, arg); 7606 register_name = "VPEOpt"; 7607 break; 7608 default: 7609 goto cp0_unimplemented; 7610 } 7611 break; 7612 case CP0_REGISTER_02: 7613 switch (sel) { 7614 case CP0_REG02__ENTRYLO0: 7615 gen_helper_dmtc0_entrylo0(tcg_env, arg); 7616 register_name = "EntryLo0"; 7617 break; 7618 case CP0_REG02__TCSTATUS: 7619 CP0_CHECK(ctx->insn_flags & ASE_MT); 7620 gen_helper_mtc0_tcstatus(tcg_env, arg); 7621 register_name = "TCStatus"; 7622 break; 7623 case CP0_REG02__TCBIND: 7624 CP0_CHECK(ctx->insn_flags & ASE_MT); 7625 gen_helper_mtc0_tcbind(tcg_env, arg); 7626 register_name = "TCBind"; 7627 break; 7628 case CP0_REG02__TCRESTART: 7629 CP0_CHECK(ctx->insn_flags & ASE_MT); 7630 gen_helper_mtc0_tcrestart(tcg_env, arg); 7631 register_name = "TCRestart"; 7632 break; 7633 case CP0_REG02__TCHALT: 7634 CP0_CHECK(ctx->insn_flags & ASE_MT); 7635 gen_helper_mtc0_tchalt(tcg_env, arg); 7636 register_name = "TCHalt"; 7637 break; 7638 case CP0_REG02__TCCONTEXT: 7639 CP0_CHECK(ctx->insn_flags & ASE_MT); 7640 gen_helper_mtc0_tccontext(tcg_env, arg); 7641 register_name = "TCContext"; 7642 break; 7643 case CP0_REG02__TCSCHEDULE: 7644 CP0_CHECK(ctx->insn_flags & ASE_MT); 7645 gen_helper_mtc0_tcschedule(tcg_env, arg); 7646 register_name = "TCSchedule"; 7647 break; 7648 case CP0_REG02__TCSCHEFBACK: 7649 CP0_CHECK(ctx->insn_flags & ASE_MT); 7650 gen_helper_mtc0_tcschefback(tcg_env, arg); 7651 register_name = "TCScheFBack"; 7652 break; 7653 default: 7654 goto cp0_unimplemented; 7655 } 7656 break; 7657 case CP0_REGISTER_03: 7658 switch (sel) { 7659 case CP0_REG03__ENTRYLO1: 7660 gen_helper_dmtc0_entrylo1(tcg_env, arg); 7661 register_name = "EntryLo1"; 7662 break; 7663 case CP0_REG03__GLOBALNUM: 7664 CP0_CHECK(ctx->vp); 7665 /* ignored */ 7666 register_name = "GlobalNumber"; 7667 break; 7668 default: 7669 goto cp0_unimplemented; 7670 } 7671 break; 7672 case CP0_REGISTER_04: 7673 switch (sel) { 7674 case CP0_REG04__CONTEXT: 7675 gen_helper_mtc0_context(tcg_env, arg); 7676 register_name = "Context"; 7677 break; 7678 case CP0_REG04__CONTEXTCONFIG: 7679 /* SmartMIPS ASE */ 7680 /* gen_helper_dmtc0_contextconfig(arg); */ 7681 register_name = "ContextConfig"; 7682 goto cp0_unimplemented; 7683 case CP0_REG04__USERLOCAL: 7684 CP0_CHECK(ctx->ulri); 7685 tcg_gen_st_tl(arg, tcg_env, 7686 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 7687 register_name = "UserLocal"; 7688 break; 7689 case CP0_REG04__MMID: 7690 CP0_CHECK(ctx->mi); 7691 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MemoryMapID)); 7692 register_name = "MMID"; 7693 break; 7694 default: 7695 goto cp0_unimplemented; 7696 } 7697 break; 7698 case CP0_REGISTER_05: 7699 switch (sel) { 7700 case CP0_REG05__PAGEMASK: 7701 gen_helper_mtc0_pagemask(tcg_env, arg); 7702 register_name = "PageMask"; 7703 break; 7704 case CP0_REG05__PAGEGRAIN: 7705 check_insn(ctx, ISA_MIPS_R2); 7706 gen_helper_mtc0_pagegrain(tcg_env, arg); 7707 register_name = "PageGrain"; 7708 break; 7709 case CP0_REG05__SEGCTL0: 7710 CP0_CHECK(ctx->sc); 7711 gen_helper_mtc0_segctl0(tcg_env, arg); 7712 register_name = "SegCtl0"; 7713 break; 7714 case CP0_REG05__SEGCTL1: 7715 CP0_CHECK(ctx->sc); 7716 gen_helper_mtc0_segctl1(tcg_env, arg); 7717 register_name = "SegCtl1"; 7718 break; 7719 case CP0_REG05__SEGCTL2: 7720 CP0_CHECK(ctx->sc); 7721 gen_helper_mtc0_segctl2(tcg_env, arg); 7722 register_name = "SegCtl2"; 7723 break; 7724 case CP0_REG05__PWBASE: 7725 check_pw(ctx); 7726 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWBase)); 7727 register_name = "PWBase"; 7728 break; 7729 case CP0_REG05__PWFIELD: 7730 check_pw(ctx); 7731 gen_helper_mtc0_pwfield(tcg_env, arg); 7732 register_name = "PWField"; 7733 break; 7734 case CP0_REG05__PWSIZE: 7735 check_pw(ctx); 7736 gen_helper_mtc0_pwsize(tcg_env, arg); 7737 register_name = "PWSize"; 7738 break; 7739 default: 7740 goto cp0_unimplemented; 7741 } 7742 break; 7743 case CP0_REGISTER_06: 7744 switch (sel) { 7745 case CP0_REG06__WIRED: 7746 gen_helper_mtc0_wired(tcg_env, arg); 7747 register_name = "Wired"; 7748 break; 7749 case CP0_REG06__SRSCONF0: 7750 check_insn(ctx, ISA_MIPS_R2); 7751 gen_helper_mtc0_srsconf0(tcg_env, arg); 7752 register_name = "SRSConf0"; 7753 break; 7754 case CP0_REG06__SRSCONF1: 7755 check_insn(ctx, ISA_MIPS_R2); 7756 gen_helper_mtc0_srsconf1(tcg_env, arg); 7757 register_name = "SRSConf1"; 7758 break; 7759 case CP0_REG06__SRSCONF2: 7760 check_insn(ctx, ISA_MIPS_R2); 7761 gen_helper_mtc0_srsconf2(tcg_env, arg); 7762 register_name = "SRSConf2"; 7763 break; 7764 case CP0_REG06__SRSCONF3: 7765 check_insn(ctx, ISA_MIPS_R2); 7766 gen_helper_mtc0_srsconf3(tcg_env, arg); 7767 register_name = "SRSConf3"; 7768 break; 7769 case CP0_REG06__SRSCONF4: 7770 check_insn(ctx, ISA_MIPS_R2); 7771 gen_helper_mtc0_srsconf4(tcg_env, arg); 7772 register_name = "SRSConf4"; 7773 break; 7774 case CP0_REG06__PWCTL: 7775 check_pw(ctx); 7776 gen_helper_mtc0_pwctl(tcg_env, arg); 7777 register_name = "PWCtl"; 7778 break; 7779 default: 7780 goto cp0_unimplemented; 7781 } 7782 break; 7783 case CP0_REGISTER_07: 7784 switch (sel) { 7785 case CP0_REG07__HWRENA: 7786 check_insn(ctx, ISA_MIPS_R2); 7787 gen_helper_mtc0_hwrena(tcg_env, arg); 7788 ctx->base.is_jmp = DISAS_STOP; 7789 register_name = "HWREna"; 7790 break; 7791 default: 7792 goto cp0_unimplemented; 7793 } 7794 break; 7795 case CP0_REGISTER_08: 7796 switch (sel) { 7797 case CP0_REG08__BADVADDR: 7798 /* ignored */ 7799 register_name = "BadVAddr"; 7800 break; 7801 case CP0_REG08__BADINSTR: 7802 /* ignored */ 7803 register_name = "BadInstr"; 7804 break; 7805 case CP0_REG08__BADINSTRP: 7806 /* ignored */ 7807 register_name = "BadInstrP"; 7808 break; 7809 case CP0_REG08__BADINSTRX: 7810 /* ignored */ 7811 register_name = "BadInstrX"; 7812 break; 7813 default: 7814 goto cp0_unimplemented; 7815 } 7816 break; 7817 case CP0_REGISTER_09: 7818 switch (sel) { 7819 case CP0_REG09__COUNT: 7820 gen_helper_mtc0_count(tcg_env, arg); 7821 register_name = "Count"; 7822 break; 7823 default: 7824 goto cp0_unimplemented; 7825 } 7826 /* Stop translation as we may have switched the execution mode */ 7827 ctx->base.is_jmp = DISAS_STOP; 7828 break; 7829 case CP0_REGISTER_10: 7830 switch (sel) { 7831 case CP0_REG10__ENTRYHI: 7832 gen_helper_mtc0_entryhi(tcg_env, arg); 7833 register_name = "EntryHi"; 7834 break; 7835 default: 7836 goto cp0_unimplemented; 7837 } 7838 break; 7839 case CP0_REGISTER_11: 7840 switch (sel) { 7841 case CP0_REG11__COMPARE: 7842 gen_helper_mtc0_compare(tcg_env, arg); 7843 register_name = "Compare"; 7844 break; 7845 /* 6,7 are implementation dependent */ 7846 default: 7847 goto cp0_unimplemented; 7848 } 7849 /* Stop translation as we may have switched the execution mode */ 7850 ctx->base.is_jmp = DISAS_STOP; 7851 break; 7852 case CP0_REGISTER_12: 7853 switch (sel) { 7854 case CP0_REG12__STATUS: 7855 save_cpu_state(ctx, 1); 7856 gen_helper_mtc0_status(tcg_env, arg); 7857 /* DISAS_STOP isn't good enough here, hflags may have changed. */ 7858 gen_save_pc(ctx->base.pc_next + 4); 7859 ctx->base.is_jmp = DISAS_EXIT; 7860 register_name = "Status"; 7861 break; 7862 case CP0_REG12__INTCTL: 7863 check_insn(ctx, ISA_MIPS_R2); 7864 gen_helper_mtc0_intctl(tcg_env, arg); 7865 /* Stop translation as we may have switched the execution mode */ 7866 ctx->base.is_jmp = DISAS_STOP; 7867 register_name = "IntCtl"; 7868 break; 7869 case CP0_REG12__SRSCTL: 7870 check_insn(ctx, ISA_MIPS_R2); 7871 gen_helper_mtc0_srsctl(tcg_env, arg); 7872 /* Stop translation as we may have switched the execution mode */ 7873 ctx->base.is_jmp = DISAS_STOP; 7874 register_name = "SRSCtl"; 7875 break; 7876 case CP0_REG12__SRSMAP: 7877 check_insn(ctx, ISA_MIPS_R2); 7878 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); 7879 /* Stop translation as we may have switched the execution mode */ 7880 ctx->base.is_jmp = DISAS_STOP; 7881 register_name = "SRSMap"; 7882 break; 7883 default: 7884 goto cp0_unimplemented; 7885 } 7886 break; 7887 case CP0_REGISTER_13: 7888 switch (sel) { 7889 case CP0_REG13__CAUSE: 7890 save_cpu_state(ctx, 1); 7891 gen_helper_mtc0_cause(tcg_env, arg); 7892 /* 7893 * Stop translation as we may have triggered an interrupt. 7894 * DISAS_STOP isn't sufficient, we need to ensure we break out of 7895 * translated code to check for pending interrupts. 7896 */ 7897 gen_save_pc(ctx->base.pc_next + 4); 7898 ctx->base.is_jmp = DISAS_EXIT; 7899 register_name = "Cause"; 7900 break; 7901 default: 7902 goto cp0_unimplemented; 7903 } 7904 break; 7905 case CP0_REGISTER_14: 7906 switch (sel) { 7907 case CP0_REG14__EPC: 7908 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC)); 7909 register_name = "EPC"; 7910 break; 7911 default: 7912 goto cp0_unimplemented; 7913 } 7914 break; 7915 case CP0_REGISTER_15: 7916 switch (sel) { 7917 case CP0_REG15__PRID: 7918 /* ignored */ 7919 register_name = "PRid"; 7920 break; 7921 case CP0_REG15__EBASE: 7922 check_insn(ctx, ISA_MIPS_R2); 7923 gen_helper_mtc0_ebase(tcg_env, arg); 7924 register_name = "EBase"; 7925 break; 7926 default: 7927 goto cp0_unimplemented; 7928 } 7929 break; 7930 case CP0_REGISTER_16: 7931 switch (sel) { 7932 case CP0_REG16__CONFIG: 7933 gen_helper_mtc0_config0(tcg_env, arg); 7934 register_name = "Config"; 7935 /* Stop translation as we may have switched the execution mode */ 7936 ctx->base.is_jmp = DISAS_STOP; 7937 break; 7938 case CP0_REG16__CONFIG1: 7939 /* ignored, read only */ 7940 register_name = "Config1"; 7941 break; 7942 case CP0_REG16__CONFIG2: 7943 gen_helper_mtc0_config2(tcg_env, arg); 7944 register_name = "Config2"; 7945 /* Stop translation as we may have switched the execution mode */ 7946 ctx->base.is_jmp = DISAS_STOP; 7947 break; 7948 case CP0_REG16__CONFIG3: 7949 gen_helper_mtc0_config3(tcg_env, arg); 7950 register_name = "Config3"; 7951 /* Stop translation as we may have switched the execution mode */ 7952 ctx->base.is_jmp = DISAS_STOP; 7953 break; 7954 case CP0_REG16__CONFIG4: 7955 /* currently ignored */ 7956 register_name = "Config4"; 7957 break; 7958 case CP0_REG16__CONFIG5: 7959 gen_helper_mtc0_config5(tcg_env, arg); 7960 register_name = "Config5"; 7961 /* Stop translation as we may have switched the execution mode */ 7962 ctx->base.is_jmp = DISAS_STOP; 7963 break; 7964 /* 6,7 are implementation dependent */ 7965 default: 7966 register_name = "Invalid config selector"; 7967 goto cp0_unimplemented; 7968 } 7969 break; 7970 case CP0_REGISTER_17: 7971 switch (sel) { 7972 case CP0_REG17__LLADDR: 7973 gen_helper_mtc0_lladdr(tcg_env, arg); 7974 register_name = "LLAddr"; 7975 break; 7976 case CP0_REG17__MAAR: 7977 CP0_CHECK(ctx->mrp); 7978 gen_helper_mtc0_maar(tcg_env, arg); 7979 register_name = "MAAR"; 7980 break; 7981 case CP0_REG17__MAARI: 7982 CP0_CHECK(ctx->mrp); 7983 gen_helper_mtc0_maari(tcg_env, arg); 7984 register_name = "MAARI"; 7985 break; 7986 default: 7987 goto cp0_unimplemented; 7988 } 7989 break; 7990 case CP0_REGISTER_18: 7991 switch (sel) { 7992 case CP0_REG18__WATCHLO0: 7993 case CP0_REG18__WATCHLO1: 7994 case CP0_REG18__WATCHLO2: 7995 case CP0_REG18__WATCHLO3: 7996 case CP0_REG18__WATCHLO4: 7997 case CP0_REG18__WATCHLO5: 7998 case CP0_REG18__WATCHLO6: 7999 case CP0_REG18__WATCHLO7: 8000 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 8001 gen_helper_0e1i(mtc0_watchlo, arg, sel); 8002 register_name = "WatchLo"; 8003 break; 8004 default: 8005 goto cp0_unimplemented; 8006 } 8007 break; 8008 case CP0_REGISTER_19: 8009 switch (sel) { 8010 case CP0_REG19__WATCHHI0: 8011 case CP0_REG19__WATCHHI1: 8012 case CP0_REG19__WATCHHI2: 8013 case CP0_REG19__WATCHHI3: 8014 case CP0_REG19__WATCHHI4: 8015 case CP0_REG19__WATCHHI5: 8016 case CP0_REG19__WATCHHI6: 8017 case CP0_REG19__WATCHHI7: 8018 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 8019 gen_helper_0e1i(mtc0_watchhi, arg, sel); 8020 register_name = "WatchHi"; 8021 break; 8022 default: 8023 goto cp0_unimplemented; 8024 } 8025 break; 8026 case CP0_REGISTER_20: 8027 switch (sel) { 8028 case CP0_REG20__XCONTEXT: 8029 check_insn(ctx, ISA_MIPS3); 8030 gen_helper_mtc0_xcontext(tcg_env, arg); 8031 register_name = "XContext"; 8032 break; 8033 default: 8034 goto cp0_unimplemented; 8035 } 8036 break; 8037 case CP0_REGISTER_21: 8038 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 8039 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 8040 switch (sel) { 8041 case 0: 8042 gen_helper_mtc0_framemask(tcg_env, arg); 8043 register_name = "Framemask"; 8044 break; 8045 default: 8046 goto cp0_unimplemented; 8047 } 8048 break; 8049 case CP0_REGISTER_22: 8050 /* ignored */ 8051 register_name = "Diagnostic"; /* implementation dependent */ 8052 break; 8053 case CP0_REGISTER_23: 8054 switch (sel) { 8055 case CP0_REG23__DEBUG: 8056 gen_helper_mtc0_debug(tcg_env, arg); /* EJTAG support */ 8057 /* DISAS_STOP isn't good enough here, hflags may have changed. */ 8058 gen_save_pc(ctx->base.pc_next + 4); 8059 ctx->base.is_jmp = DISAS_EXIT; 8060 register_name = "Debug"; 8061 break; 8062 case CP0_REG23__TRACECONTROL: 8063 /* PDtrace support */ 8064 /* gen_helper_mtc0_tracecontrol(tcg_env, arg); */ 8065 /* Stop translation as we may have switched the execution mode */ 8066 ctx->base.is_jmp = DISAS_STOP; 8067 register_name = "TraceControl"; 8068 goto cp0_unimplemented; 8069 case CP0_REG23__TRACECONTROL2: 8070 /* PDtrace support */ 8071 /* gen_helper_mtc0_tracecontrol2(tcg_env, arg); */ 8072 /* Stop translation as we may have switched the execution mode */ 8073 ctx->base.is_jmp = DISAS_STOP; 8074 register_name = "TraceControl2"; 8075 goto cp0_unimplemented; 8076 case CP0_REG23__USERTRACEDATA1: 8077 /* PDtrace support */ 8078 /* gen_helper_mtc0_usertracedata1(tcg_env, arg);*/ 8079 /* Stop translation as we may have switched the execution mode */ 8080 ctx->base.is_jmp = DISAS_STOP; 8081 register_name = "UserTraceData1"; 8082 goto cp0_unimplemented; 8083 case CP0_REG23__TRACEIBPC: 8084 /* PDtrace support */ 8085 /* gen_helper_mtc0_traceibpc(tcg_env, arg); */ 8086 /* Stop translation as we may have switched the execution mode */ 8087 ctx->base.is_jmp = DISAS_STOP; 8088 register_name = "TraceIBPC"; 8089 goto cp0_unimplemented; 8090 case CP0_REG23__TRACEDBPC: 8091 /* PDtrace support */ 8092 /* gen_helper_mtc0_tracedbpc(tcg_env, arg); */ 8093 /* Stop translation as we may have switched the execution mode */ 8094 ctx->base.is_jmp = DISAS_STOP; 8095 register_name = "TraceDBPC"; 8096 goto cp0_unimplemented; 8097 default: 8098 goto cp0_unimplemented; 8099 } 8100 break; 8101 case CP0_REGISTER_24: 8102 switch (sel) { 8103 case CP0_REG24__DEPC: 8104 /* EJTAG support */ 8105 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC)); 8106 register_name = "DEPC"; 8107 break; 8108 default: 8109 goto cp0_unimplemented; 8110 } 8111 break; 8112 case CP0_REGISTER_25: 8113 switch (sel) { 8114 case CP0_REG25__PERFCTL0: 8115 gen_helper_mtc0_performance0(tcg_env, arg); 8116 register_name = "Performance0"; 8117 break; 8118 case CP0_REG25__PERFCNT0: 8119 /* gen_helper_mtc0_performance1(tcg_env, arg); */ 8120 register_name = "Performance1"; 8121 goto cp0_unimplemented; 8122 case CP0_REG25__PERFCTL1: 8123 /* gen_helper_mtc0_performance2(tcg_env, arg); */ 8124 register_name = "Performance2"; 8125 goto cp0_unimplemented; 8126 case CP0_REG25__PERFCNT1: 8127 /* gen_helper_mtc0_performance3(tcg_env, arg); */ 8128 register_name = "Performance3"; 8129 goto cp0_unimplemented; 8130 case CP0_REG25__PERFCTL2: 8131 /* gen_helper_mtc0_performance4(tcg_env, arg); */ 8132 register_name = "Performance4"; 8133 goto cp0_unimplemented; 8134 case CP0_REG25__PERFCNT2: 8135 /* gen_helper_mtc0_performance5(tcg_env, arg); */ 8136 register_name = "Performance5"; 8137 goto cp0_unimplemented; 8138 case CP0_REG25__PERFCTL3: 8139 /* gen_helper_mtc0_performance6(tcg_env, arg); */ 8140 register_name = "Performance6"; 8141 goto cp0_unimplemented; 8142 case CP0_REG25__PERFCNT3: 8143 /* gen_helper_mtc0_performance7(tcg_env, arg); */ 8144 register_name = "Performance7"; 8145 goto cp0_unimplemented; 8146 default: 8147 goto cp0_unimplemented; 8148 } 8149 break; 8150 case CP0_REGISTER_26: 8151 switch (sel) { 8152 case CP0_REG26__ERRCTL: 8153 gen_helper_mtc0_errctl(tcg_env, arg); 8154 ctx->base.is_jmp = DISAS_STOP; 8155 register_name = "ErrCtl"; 8156 break; 8157 default: 8158 goto cp0_unimplemented; 8159 } 8160 break; 8161 case CP0_REGISTER_27: 8162 switch (sel) { 8163 case CP0_REG27__CACHERR: 8164 /* ignored */ 8165 register_name = "CacheErr"; 8166 break; 8167 default: 8168 goto cp0_unimplemented; 8169 } 8170 break; 8171 case CP0_REGISTER_28: 8172 switch (sel) { 8173 case CP0_REG28__TAGLO: 8174 case CP0_REG28__TAGLO1: 8175 case CP0_REG28__TAGLO2: 8176 case CP0_REG28__TAGLO3: 8177 gen_helper_mtc0_taglo(tcg_env, arg); 8178 register_name = "TagLo"; 8179 break; 8180 case CP0_REG28__DATALO: 8181 case CP0_REG28__DATALO1: 8182 case CP0_REG28__DATALO2: 8183 case CP0_REG28__DATALO3: 8184 gen_helper_mtc0_datalo(tcg_env, arg); 8185 register_name = "DataLo"; 8186 break; 8187 default: 8188 goto cp0_unimplemented; 8189 } 8190 break; 8191 case CP0_REGISTER_29: 8192 switch (sel) { 8193 case CP0_REG29__TAGHI: 8194 case CP0_REG29__TAGHI1: 8195 case CP0_REG29__TAGHI2: 8196 case CP0_REG29__TAGHI3: 8197 gen_helper_mtc0_taghi(tcg_env, arg); 8198 register_name = "TagHi"; 8199 break; 8200 case CP0_REG29__DATAHI: 8201 case CP0_REG29__DATAHI1: 8202 case CP0_REG29__DATAHI2: 8203 case CP0_REG29__DATAHI3: 8204 gen_helper_mtc0_datahi(tcg_env, arg); 8205 register_name = "DataHi"; 8206 break; 8207 default: 8208 register_name = "invalid sel"; 8209 goto cp0_unimplemented; 8210 } 8211 break; 8212 case CP0_REGISTER_30: 8213 switch (sel) { 8214 case CP0_REG30__ERROREPC: 8215 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); 8216 register_name = "ErrorEPC"; 8217 break; 8218 default: 8219 goto cp0_unimplemented; 8220 } 8221 break; 8222 case CP0_REGISTER_31: 8223 switch (sel) { 8224 case CP0_REG31__DESAVE: 8225 /* EJTAG support */ 8226 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); 8227 register_name = "DESAVE"; 8228 break; 8229 case CP0_REG31__KSCRATCH1: 8230 case CP0_REG31__KSCRATCH2: 8231 case CP0_REG31__KSCRATCH3: 8232 case CP0_REG31__KSCRATCH4: 8233 case CP0_REG31__KSCRATCH5: 8234 case CP0_REG31__KSCRATCH6: 8235 CP0_CHECK(ctx->kscrexist & (1 << sel)); 8236 tcg_gen_st_tl(arg, tcg_env, 8237 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); 8238 register_name = "KScratch"; 8239 break; 8240 default: 8241 goto cp0_unimplemented; 8242 } 8243 break; 8244 default: 8245 goto cp0_unimplemented; 8246 } 8247 trace_mips_translate_c0("dmtc0", register_name, reg, sel); 8248 8249 /* For simplicity assume that all writes can cause interrupts. */ 8250 if (icount) { 8251 /* 8252 * DISAS_STOP isn't sufficient, we need to ensure we break out of 8253 * translated code to check for pending interrupts. 8254 */ 8255 gen_save_pc(ctx->base.pc_next + 4); 8256 ctx->base.is_jmp = DISAS_EXIT; 8257 } 8258 return; 8259 8260 cp0_unimplemented: 8261 qemu_log_mask(LOG_UNIMP, "dmtc0 %s (reg %d sel %d)\n", 8262 register_name, reg, sel); 8263 } 8264 #endif /* TARGET_MIPS64 */ 8265 8266 static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, 8267 int u, int sel, int h) 8268 { 8269 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 8270 TCGv t0 = tcg_temp_new(); 8271 8272 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && 8273 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != 8274 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) { 8275 tcg_gen_movi_tl(t0, -1); 8276 } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > 8277 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) { 8278 tcg_gen_movi_tl(t0, -1); 8279 } else if (u == 0) { 8280 switch (rt) { 8281 case 1: 8282 switch (sel) { 8283 case 1: 8284 gen_helper_mftc0_vpecontrol(t0, tcg_env); 8285 break; 8286 case 2: 8287 gen_helper_mftc0_vpeconf0(t0, tcg_env); 8288 break; 8289 default: 8290 goto die; 8291 break; 8292 } 8293 break; 8294 case 2: 8295 switch (sel) { 8296 case 1: 8297 gen_helper_mftc0_tcstatus(t0, tcg_env); 8298 break; 8299 case 2: 8300 gen_helper_mftc0_tcbind(t0, tcg_env); 8301 break; 8302 case 3: 8303 gen_helper_mftc0_tcrestart(t0, tcg_env); 8304 break; 8305 case 4: 8306 gen_helper_mftc0_tchalt(t0, tcg_env); 8307 break; 8308 case 5: 8309 gen_helper_mftc0_tccontext(t0, tcg_env); 8310 break; 8311 case 6: 8312 gen_helper_mftc0_tcschedule(t0, tcg_env); 8313 break; 8314 case 7: 8315 gen_helper_mftc0_tcschefback(t0, tcg_env); 8316 break; 8317 default: 8318 gen_mfc0(ctx, t0, rt, sel); 8319 break; 8320 } 8321 break; 8322 case 10: 8323 switch (sel) { 8324 case 0: 8325 gen_helper_mftc0_entryhi(t0, tcg_env); 8326 break; 8327 default: 8328 gen_mfc0(ctx, t0, rt, sel); 8329 break; 8330 } 8331 break; 8332 case 12: 8333 switch (sel) { 8334 case 0: 8335 gen_helper_mftc0_status(t0, tcg_env); 8336 break; 8337 default: 8338 gen_mfc0(ctx, t0, rt, sel); 8339 break; 8340 } 8341 break; 8342 case 13: 8343 switch (sel) { 8344 case 0: 8345 gen_helper_mftc0_cause(t0, tcg_env); 8346 break; 8347 default: 8348 goto die; 8349 break; 8350 } 8351 break; 8352 case 14: 8353 switch (sel) { 8354 case 0: 8355 gen_helper_mftc0_epc(t0, tcg_env); 8356 break; 8357 default: 8358 goto die; 8359 break; 8360 } 8361 break; 8362 case 15: 8363 switch (sel) { 8364 case 1: 8365 gen_helper_mftc0_ebase(t0, tcg_env); 8366 break; 8367 default: 8368 goto die; 8369 break; 8370 } 8371 break; 8372 case 16: 8373 switch (sel) { 8374 case 0: 8375 case 1: 8376 case 2: 8377 case 3: 8378 case 4: 8379 case 5: 8380 case 6: 8381 case 7: 8382 gen_helper_mftc0_configx(t0, tcg_env, tcg_constant_tl(sel)); 8383 break; 8384 default: 8385 goto die; 8386 break; 8387 } 8388 break; 8389 case 23: 8390 switch (sel) { 8391 case 0: 8392 gen_helper_mftc0_debug(t0, tcg_env); 8393 break; 8394 default: 8395 gen_mfc0(ctx, t0, rt, sel); 8396 break; 8397 } 8398 break; 8399 default: 8400 gen_mfc0(ctx, t0, rt, sel); 8401 } 8402 } else { 8403 switch (sel) { 8404 /* GPR registers. */ 8405 case 0: 8406 gen_helper_1e0i(mftgpr, t0, rt); 8407 break; 8408 /* Auxiliary CPU registers */ 8409 case 1: 8410 switch (rt) { 8411 case 0: 8412 gen_helper_1e0i(mftlo, t0, 0); 8413 break; 8414 case 1: 8415 gen_helper_1e0i(mfthi, t0, 0); 8416 break; 8417 case 2: 8418 gen_helper_1e0i(mftacx, t0, 0); 8419 break; 8420 case 4: 8421 gen_helper_1e0i(mftlo, t0, 1); 8422 break; 8423 case 5: 8424 gen_helper_1e0i(mfthi, t0, 1); 8425 break; 8426 case 6: 8427 gen_helper_1e0i(mftacx, t0, 1); 8428 break; 8429 case 8: 8430 gen_helper_1e0i(mftlo, t0, 2); 8431 break; 8432 case 9: 8433 gen_helper_1e0i(mfthi, t0, 2); 8434 break; 8435 case 10: 8436 gen_helper_1e0i(mftacx, t0, 2); 8437 break; 8438 case 12: 8439 gen_helper_1e0i(mftlo, t0, 3); 8440 break; 8441 case 13: 8442 gen_helper_1e0i(mfthi, t0, 3); 8443 break; 8444 case 14: 8445 gen_helper_1e0i(mftacx, t0, 3); 8446 break; 8447 case 16: 8448 gen_helper_mftdsp(t0, tcg_env); 8449 break; 8450 default: 8451 goto die; 8452 } 8453 break; 8454 /* Floating point (COP1). */ 8455 case 2: 8456 /* XXX: For now we support only a single FPU context. */ 8457 if (h == 0) { 8458 TCGv_i32 fp0 = tcg_temp_new_i32(); 8459 8460 gen_load_fpr32(ctx, fp0, rt); 8461 tcg_gen_ext_i32_tl(t0, fp0); 8462 } else { 8463 TCGv_i32 fp0 = tcg_temp_new_i32(); 8464 8465 gen_load_fpr32h(ctx, fp0, rt); 8466 tcg_gen_ext_i32_tl(t0, fp0); 8467 } 8468 break; 8469 case 3: 8470 /* XXX: For now we support only a single FPU context. */ 8471 gen_helper_1e0i(cfc1, t0, rt); 8472 break; 8473 /* COP2: Not implemented. */ 8474 case 4: 8475 case 5: 8476 /* fall through */ 8477 default: 8478 goto die; 8479 } 8480 } 8481 trace_mips_translate_tr("mftr", rt, u, sel, h); 8482 gen_store_gpr(t0, rd); 8483 return; 8484 8485 die: 8486 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h); 8487 gen_reserved_instruction(ctx); 8488 } 8489 8490 static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, 8491 int u, int sel, int h) 8492 { 8493 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 8494 TCGv t0 = tcg_temp_new(); 8495 8496 gen_load_gpr(t0, rt); 8497 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && 8498 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != 8499 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) { 8500 /* NOP */ 8501 ; 8502 } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > 8503 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) { 8504 /* NOP */ 8505 ; 8506 } else if (u == 0) { 8507 switch (rd) { 8508 case 1: 8509 switch (sel) { 8510 case 1: 8511 gen_helper_mttc0_vpecontrol(tcg_env, t0); 8512 break; 8513 case 2: 8514 gen_helper_mttc0_vpeconf0(tcg_env, t0); 8515 break; 8516 default: 8517 goto die; 8518 break; 8519 } 8520 break; 8521 case 2: 8522 switch (sel) { 8523 case 1: 8524 gen_helper_mttc0_tcstatus(tcg_env, t0); 8525 break; 8526 case 2: 8527 gen_helper_mttc0_tcbind(tcg_env, t0); 8528 break; 8529 case 3: 8530 gen_helper_mttc0_tcrestart(tcg_env, t0); 8531 break; 8532 case 4: 8533 gen_helper_mttc0_tchalt(tcg_env, t0); 8534 break; 8535 case 5: 8536 gen_helper_mttc0_tccontext(tcg_env, t0); 8537 break; 8538 case 6: 8539 gen_helper_mttc0_tcschedule(tcg_env, t0); 8540 break; 8541 case 7: 8542 gen_helper_mttc0_tcschefback(tcg_env, t0); 8543 break; 8544 default: 8545 gen_mtc0(ctx, t0, rd, sel); 8546 break; 8547 } 8548 break; 8549 case 10: 8550 switch (sel) { 8551 case 0: 8552 gen_helper_mttc0_entryhi(tcg_env, t0); 8553 break; 8554 default: 8555 gen_mtc0(ctx, t0, rd, sel); 8556 break; 8557 } 8558 break; 8559 case 12: 8560 switch (sel) { 8561 case 0: 8562 gen_helper_mttc0_status(tcg_env, t0); 8563 break; 8564 default: 8565 gen_mtc0(ctx, t0, rd, sel); 8566 break; 8567 } 8568 break; 8569 case 13: 8570 switch (sel) { 8571 case 0: 8572 gen_helper_mttc0_cause(tcg_env, t0); 8573 break; 8574 default: 8575 goto die; 8576 break; 8577 } 8578 break; 8579 case 15: 8580 switch (sel) { 8581 case 1: 8582 gen_helper_mttc0_ebase(tcg_env, t0); 8583 break; 8584 default: 8585 goto die; 8586 break; 8587 } 8588 break; 8589 case 23: 8590 switch (sel) { 8591 case 0: 8592 gen_helper_mttc0_debug(tcg_env, t0); 8593 break; 8594 default: 8595 gen_mtc0(ctx, t0, rd, sel); 8596 break; 8597 } 8598 break; 8599 default: 8600 gen_mtc0(ctx, t0, rd, sel); 8601 } 8602 } else { 8603 switch (sel) { 8604 /* GPR registers. */ 8605 case 0: 8606 gen_helper_0e1i(mttgpr, t0, rd); 8607 break; 8608 /* Auxiliary CPU registers */ 8609 case 1: 8610 switch (rd) { 8611 case 0: 8612 gen_helper_0e1i(mttlo, t0, 0); 8613 break; 8614 case 1: 8615 gen_helper_0e1i(mtthi, t0, 0); 8616 break; 8617 case 2: 8618 gen_helper_0e1i(mttacx, t0, 0); 8619 break; 8620 case 4: 8621 gen_helper_0e1i(mttlo, t0, 1); 8622 break; 8623 case 5: 8624 gen_helper_0e1i(mtthi, t0, 1); 8625 break; 8626 case 6: 8627 gen_helper_0e1i(mttacx, t0, 1); 8628 break; 8629 case 8: 8630 gen_helper_0e1i(mttlo, t0, 2); 8631 break; 8632 case 9: 8633 gen_helper_0e1i(mtthi, t0, 2); 8634 break; 8635 case 10: 8636 gen_helper_0e1i(mttacx, t0, 2); 8637 break; 8638 case 12: 8639 gen_helper_0e1i(mttlo, t0, 3); 8640 break; 8641 case 13: 8642 gen_helper_0e1i(mtthi, t0, 3); 8643 break; 8644 case 14: 8645 gen_helper_0e1i(mttacx, t0, 3); 8646 break; 8647 case 16: 8648 gen_helper_mttdsp(tcg_env, t0); 8649 break; 8650 default: 8651 goto die; 8652 } 8653 break; 8654 /* Floating point (COP1). */ 8655 case 2: 8656 /* XXX: For now we support only a single FPU context. */ 8657 if (h == 0) { 8658 TCGv_i32 fp0 = tcg_temp_new_i32(); 8659 8660 tcg_gen_trunc_tl_i32(fp0, t0); 8661 gen_store_fpr32(ctx, fp0, rd); 8662 } else { 8663 TCGv_i32 fp0 = tcg_temp_new_i32(); 8664 8665 tcg_gen_trunc_tl_i32(fp0, t0); 8666 gen_store_fpr32h(ctx, fp0, rd); 8667 } 8668 break; 8669 case 3: 8670 /* XXX: For now we support only a single FPU context. */ 8671 gen_helper_0e2i(ctc1, t0, tcg_constant_i32(rd), rt); 8672 /* Stop translation as we may have changed hflags */ 8673 ctx->base.is_jmp = DISAS_STOP; 8674 break; 8675 /* COP2: Not implemented. */ 8676 case 4: 8677 case 5: 8678 /* fall through */ 8679 default: 8680 goto die; 8681 } 8682 } 8683 trace_mips_translate_tr("mttr", rd, u, sel, h); 8684 return; 8685 8686 die: 8687 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h); 8688 gen_reserved_instruction(ctx); 8689 } 8690 8691 static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, 8692 int rt, int rd) 8693 { 8694 const char *opn = "ldst"; 8695 8696 check_cp0_enabled(ctx); 8697 switch (opc) { 8698 case OPC_MFC0: 8699 if (rt == 0) { 8700 /* Treat as NOP. */ 8701 return; 8702 } 8703 gen_mfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); 8704 opn = "mfc0"; 8705 break; 8706 case OPC_MTC0: 8707 { 8708 TCGv t0 = tcg_temp_new(); 8709 8710 gen_load_gpr(t0, rt); 8711 gen_mtc0(ctx, t0, rd, ctx->opcode & 0x7); 8712 } 8713 opn = "mtc0"; 8714 break; 8715 #if defined(TARGET_MIPS64) 8716 case OPC_DMFC0: 8717 check_insn(ctx, ISA_MIPS3); 8718 if (rt == 0) { 8719 /* Treat as NOP. */ 8720 return; 8721 } 8722 gen_dmfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); 8723 opn = "dmfc0"; 8724 break; 8725 case OPC_DMTC0: 8726 check_insn(ctx, ISA_MIPS3); 8727 { 8728 TCGv t0 = tcg_temp_new(); 8729 8730 gen_load_gpr(t0, rt); 8731 gen_dmtc0(ctx, t0, rd, ctx->opcode & 0x7); 8732 } 8733 opn = "dmtc0"; 8734 break; 8735 #endif 8736 case OPC_MFHC0: 8737 check_mvh(ctx); 8738 if (rt == 0) { 8739 /* Treat as NOP. */ 8740 return; 8741 } 8742 gen_mfhc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); 8743 opn = "mfhc0"; 8744 break; 8745 case OPC_MTHC0: 8746 check_mvh(ctx); 8747 { 8748 TCGv t0 = tcg_temp_new(); 8749 gen_load_gpr(t0, rt); 8750 gen_mthc0(ctx, t0, rd, ctx->opcode & 0x7); 8751 } 8752 opn = "mthc0"; 8753 break; 8754 case OPC_MFTR: 8755 check_cp0_enabled(ctx); 8756 if (rd == 0) { 8757 /* Treat as NOP. */ 8758 return; 8759 } 8760 gen_mftr(env, ctx, rt, rd, (ctx->opcode >> 5) & 1, 8761 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); 8762 opn = "mftr"; 8763 break; 8764 case OPC_MTTR: 8765 check_cp0_enabled(ctx); 8766 gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1, 8767 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); 8768 opn = "mttr"; 8769 break; 8770 case OPC_TLBWI: 8771 opn = "tlbwi"; 8772 if (!env->tlb->helper_tlbwi) { 8773 goto die; 8774 } 8775 gen_helper_tlbwi(tcg_env); 8776 break; 8777 case OPC_TLBINV: 8778 opn = "tlbinv"; 8779 if (ctx->ie >= 2) { 8780 if (!env->tlb->helper_tlbinv) { 8781 goto die; 8782 } 8783 gen_helper_tlbinv(tcg_env); 8784 } /* treat as nop if TLBINV not supported */ 8785 break; 8786 case OPC_TLBINVF: 8787 opn = "tlbinvf"; 8788 if (ctx->ie >= 2) { 8789 if (!env->tlb->helper_tlbinvf) { 8790 goto die; 8791 } 8792 gen_helper_tlbinvf(tcg_env); 8793 } /* treat as nop if TLBINV not supported */ 8794 break; 8795 case OPC_TLBWR: 8796 opn = "tlbwr"; 8797 if (!env->tlb->helper_tlbwr) { 8798 goto die; 8799 } 8800 gen_helper_tlbwr(tcg_env); 8801 break; 8802 case OPC_TLBP: 8803 opn = "tlbp"; 8804 if (!env->tlb->helper_tlbp) { 8805 goto die; 8806 } 8807 gen_helper_tlbp(tcg_env); 8808 break; 8809 case OPC_TLBR: 8810 opn = "tlbr"; 8811 if (!env->tlb->helper_tlbr) { 8812 goto die; 8813 } 8814 gen_helper_tlbr(tcg_env); 8815 break; 8816 case OPC_ERET: /* OPC_ERETNC */ 8817 if ((ctx->insn_flags & ISA_MIPS_R6) && 8818 (ctx->hflags & MIPS_HFLAG_BMASK)) { 8819 goto die; 8820 } else { 8821 int bit_shift = (ctx->hflags & MIPS_HFLAG_M16) ? 16 : 6; 8822 if (ctx->opcode & (1 << bit_shift)) { 8823 /* OPC_ERETNC */ 8824 opn = "eretnc"; 8825 check_insn(ctx, ISA_MIPS_R5); 8826 gen_helper_eretnc(tcg_env); 8827 } else { 8828 /* OPC_ERET */ 8829 opn = "eret"; 8830 check_insn(ctx, ISA_MIPS2); 8831 gen_helper_eret(tcg_env); 8832 } 8833 ctx->base.is_jmp = DISAS_EXIT; 8834 } 8835 break; 8836 case OPC_DERET: 8837 opn = "deret"; 8838 check_insn(ctx, ISA_MIPS_R1); 8839 if ((ctx->insn_flags & ISA_MIPS_R6) && 8840 (ctx->hflags & MIPS_HFLAG_BMASK)) { 8841 goto die; 8842 } 8843 if (!(ctx->hflags & MIPS_HFLAG_DM)) { 8844 MIPS_INVAL(opn); 8845 gen_reserved_instruction(ctx); 8846 } else { 8847 gen_helper_deret(tcg_env); 8848 ctx->base.is_jmp = DISAS_EXIT; 8849 } 8850 break; 8851 case OPC_WAIT: 8852 opn = "wait"; 8853 check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); 8854 if ((ctx->insn_flags & ISA_MIPS_R6) && 8855 (ctx->hflags & MIPS_HFLAG_BMASK)) { 8856 goto die; 8857 } 8858 /* If we get an exception, we want to restart at next instruction */ 8859 ctx->base.pc_next += 4; 8860 save_cpu_state(ctx, 1); 8861 ctx->base.pc_next -= 4; 8862 gen_helper_wait(tcg_env); 8863 ctx->base.is_jmp = DISAS_NORETURN; 8864 break; 8865 default: 8866 die: 8867 MIPS_INVAL(opn); 8868 gen_reserved_instruction(ctx); 8869 return; 8870 } 8871 (void)opn; /* avoid a compiler warning */ 8872 } 8873 #endif /* !CONFIG_USER_ONLY */ 8874 8875 /* CP1 Branches (before delay slot) */ 8876 static void gen_compute_branch1(DisasContext *ctx, uint32_t op, 8877 int32_t cc, int32_t offset) 8878 { 8879 target_ulong btarget; 8880 TCGv_i32 t0 = tcg_temp_new_i32(); 8881 8882 if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { 8883 gen_reserved_instruction(ctx); 8884 return; 8885 } 8886 8887 if (cc != 0) { 8888 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); 8889 } 8890 8891 btarget = ctx->base.pc_next + 4 + offset; 8892 8893 switch (op) { 8894 case OPC_BC1F: 8895 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 8896 tcg_gen_not_i32(t0, t0); 8897 tcg_gen_andi_i32(t0, t0, 1); 8898 tcg_gen_extu_i32_tl(bcond, t0); 8899 goto not_likely; 8900 case OPC_BC1FL: 8901 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 8902 tcg_gen_not_i32(t0, t0); 8903 tcg_gen_andi_i32(t0, t0, 1); 8904 tcg_gen_extu_i32_tl(bcond, t0); 8905 goto likely; 8906 case OPC_BC1T: 8907 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 8908 tcg_gen_andi_i32(t0, t0, 1); 8909 tcg_gen_extu_i32_tl(bcond, t0); 8910 goto not_likely; 8911 case OPC_BC1TL: 8912 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 8913 tcg_gen_andi_i32(t0, t0, 1); 8914 tcg_gen_extu_i32_tl(bcond, t0); 8915 likely: 8916 ctx->hflags |= MIPS_HFLAG_BL; 8917 break; 8918 case OPC_BC1FANY2: 8919 { 8920 TCGv_i32 t1 = tcg_temp_new_i32(); 8921 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 8922 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); 8923 tcg_gen_nand_i32(t0, t0, t1); 8924 tcg_gen_andi_i32(t0, t0, 1); 8925 tcg_gen_extu_i32_tl(bcond, t0); 8926 } 8927 goto not_likely; 8928 case OPC_BC1TANY2: 8929 { 8930 TCGv_i32 t1 = tcg_temp_new_i32(); 8931 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 8932 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); 8933 tcg_gen_or_i32(t0, t0, t1); 8934 tcg_gen_andi_i32(t0, t0, 1); 8935 tcg_gen_extu_i32_tl(bcond, t0); 8936 } 8937 goto not_likely; 8938 case OPC_BC1FANY4: 8939 { 8940 TCGv_i32 t1 = tcg_temp_new_i32(); 8941 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 8942 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); 8943 tcg_gen_and_i32(t0, t0, t1); 8944 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 2)); 8945 tcg_gen_and_i32(t0, t0, t1); 8946 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3)); 8947 tcg_gen_nand_i32(t0, t0, t1); 8948 tcg_gen_andi_i32(t0, t0, 1); 8949 tcg_gen_extu_i32_tl(bcond, t0); 8950 } 8951 goto not_likely; 8952 case OPC_BC1TANY4: 8953 { 8954 TCGv_i32 t1 = tcg_temp_new_i32(); 8955 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 8956 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); 8957 tcg_gen_or_i32(t0, t0, t1); 8958 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 2)); 8959 tcg_gen_or_i32(t0, t0, t1); 8960 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3)); 8961 tcg_gen_or_i32(t0, t0, t1); 8962 tcg_gen_andi_i32(t0, t0, 1); 8963 tcg_gen_extu_i32_tl(bcond, t0); 8964 } 8965 not_likely: 8966 ctx->hflags |= MIPS_HFLAG_BC; 8967 break; 8968 default: 8969 MIPS_INVAL("cp1 cond branch"); 8970 gen_reserved_instruction(ctx); 8971 return; 8972 } 8973 ctx->btarget = btarget; 8974 ctx->hflags |= MIPS_HFLAG_BDS32; 8975 } 8976 8977 /* R6 CP1 Branches */ 8978 static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op, 8979 int32_t ft, int32_t offset, 8980 int delayslot_size) 8981 { 8982 target_ulong btarget; 8983 TCGv_i64 t0 = tcg_temp_new_i64(); 8984 8985 if (ctx->hflags & MIPS_HFLAG_BMASK) { 8986 #ifdef MIPS_DEBUG_DISAS 8987 LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016" 8988 VADDR_PRIx "\n", ctx->base.pc_next); 8989 #endif 8990 gen_reserved_instruction(ctx); 8991 return; 8992 } 8993 8994 gen_load_fpr64(ctx, t0, ft); 8995 tcg_gen_andi_i64(t0, t0, 1); 8996 8997 btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 8998 8999 switch (op) { 9000 case OPC_BC1EQZ: 9001 tcg_gen_xori_i64(t0, t0, 1); 9002 ctx->hflags |= MIPS_HFLAG_BC; 9003 break; 9004 case OPC_BC1NEZ: 9005 /* t0 already set */ 9006 ctx->hflags |= MIPS_HFLAG_BC; 9007 break; 9008 default: 9009 MIPS_INVAL("cp1 cond branch"); 9010 gen_reserved_instruction(ctx); 9011 return; 9012 } 9013 9014 tcg_gen_trunc_i64_tl(bcond, t0); 9015 9016 ctx->btarget = btarget; 9017 9018 switch (delayslot_size) { 9019 case 2: 9020 ctx->hflags |= MIPS_HFLAG_BDS16; 9021 break; 9022 case 4: 9023 ctx->hflags |= MIPS_HFLAG_BDS32; 9024 break; 9025 } 9026 } 9027 9028 /* Coprocessor 1 (FPU) */ 9029 9030 #define FOP(func, fmt) (((fmt) << 21) | (func)) 9031 9032 enum fopcode { 9033 OPC_ADD_S = FOP(0, FMT_S), 9034 OPC_SUB_S = FOP(1, FMT_S), 9035 OPC_MUL_S = FOP(2, FMT_S), 9036 OPC_DIV_S = FOP(3, FMT_S), 9037 OPC_SQRT_S = FOP(4, FMT_S), 9038 OPC_ABS_S = FOP(5, FMT_S), 9039 OPC_MOV_S = FOP(6, FMT_S), 9040 OPC_NEG_S = FOP(7, FMT_S), 9041 OPC_ROUND_L_S = FOP(8, FMT_S), 9042 OPC_TRUNC_L_S = FOP(9, FMT_S), 9043 OPC_CEIL_L_S = FOP(10, FMT_S), 9044 OPC_FLOOR_L_S = FOP(11, FMT_S), 9045 OPC_ROUND_W_S = FOP(12, FMT_S), 9046 OPC_TRUNC_W_S = FOP(13, FMT_S), 9047 OPC_CEIL_W_S = FOP(14, FMT_S), 9048 OPC_FLOOR_W_S = FOP(15, FMT_S), 9049 OPC_SEL_S = FOP(16, FMT_S), 9050 OPC_MOVCF_S = FOP(17, FMT_S), 9051 OPC_MOVZ_S = FOP(18, FMT_S), 9052 OPC_MOVN_S = FOP(19, FMT_S), 9053 OPC_SELEQZ_S = FOP(20, FMT_S), 9054 OPC_RECIP_S = FOP(21, FMT_S), 9055 OPC_RSQRT_S = FOP(22, FMT_S), 9056 OPC_SELNEZ_S = FOP(23, FMT_S), 9057 OPC_MADDF_S = FOP(24, FMT_S), 9058 OPC_MSUBF_S = FOP(25, FMT_S), 9059 OPC_RINT_S = FOP(26, FMT_S), 9060 OPC_CLASS_S = FOP(27, FMT_S), 9061 OPC_MIN_S = FOP(28, FMT_S), 9062 OPC_RECIP2_S = FOP(28, FMT_S), 9063 OPC_MINA_S = FOP(29, FMT_S), 9064 OPC_RECIP1_S = FOP(29, FMT_S), 9065 OPC_MAX_S = FOP(30, FMT_S), 9066 OPC_RSQRT1_S = FOP(30, FMT_S), 9067 OPC_MAXA_S = FOP(31, FMT_S), 9068 OPC_RSQRT2_S = FOP(31, FMT_S), 9069 OPC_CVT_D_S = FOP(33, FMT_S), 9070 OPC_CVT_W_S = FOP(36, FMT_S), 9071 OPC_CVT_L_S = FOP(37, FMT_S), 9072 OPC_CVT_PS_S = FOP(38, FMT_S), 9073 OPC_CMP_F_S = FOP(48, FMT_S), 9074 OPC_CMP_UN_S = FOP(49, FMT_S), 9075 OPC_CMP_EQ_S = FOP(50, FMT_S), 9076 OPC_CMP_UEQ_S = FOP(51, FMT_S), 9077 OPC_CMP_OLT_S = FOP(52, FMT_S), 9078 OPC_CMP_ULT_S = FOP(53, FMT_S), 9079 OPC_CMP_OLE_S = FOP(54, FMT_S), 9080 OPC_CMP_ULE_S = FOP(55, FMT_S), 9081 OPC_CMP_SF_S = FOP(56, FMT_S), 9082 OPC_CMP_NGLE_S = FOP(57, FMT_S), 9083 OPC_CMP_SEQ_S = FOP(58, FMT_S), 9084 OPC_CMP_NGL_S = FOP(59, FMT_S), 9085 OPC_CMP_LT_S = FOP(60, FMT_S), 9086 OPC_CMP_NGE_S = FOP(61, FMT_S), 9087 OPC_CMP_LE_S = FOP(62, FMT_S), 9088 OPC_CMP_NGT_S = FOP(63, FMT_S), 9089 9090 OPC_ADD_D = FOP(0, FMT_D), 9091 OPC_SUB_D = FOP(1, FMT_D), 9092 OPC_MUL_D = FOP(2, FMT_D), 9093 OPC_DIV_D = FOP(3, FMT_D), 9094 OPC_SQRT_D = FOP(4, FMT_D), 9095 OPC_ABS_D = FOP(5, FMT_D), 9096 OPC_MOV_D = FOP(6, FMT_D), 9097 OPC_NEG_D = FOP(7, FMT_D), 9098 OPC_ROUND_L_D = FOP(8, FMT_D), 9099 OPC_TRUNC_L_D = FOP(9, FMT_D), 9100 OPC_CEIL_L_D = FOP(10, FMT_D), 9101 OPC_FLOOR_L_D = FOP(11, FMT_D), 9102 OPC_ROUND_W_D = FOP(12, FMT_D), 9103 OPC_TRUNC_W_D = FOP(13, FMT_D), 9104 OPC_CEIL_W_D = FOP(14, FMT_D), 9105 OPC_FLOOR_W_D = FOP(15, FMT_D), 9106 OPC_SEL_D = FOP(16, FMT_D), 9107 OPC_MOVCF_D = FOP(17, FMT_D), 9108 OPC_MOVZ_D = FOP(18, FMT_D), 9109 OPC_MOVN_D = FOP(19, FMT_D), 9110 OPC_SELEQZ_D = FOP(20, FMT_D), 9111 OPC_RECIP_D = FOP(21, FMT_D), 9112 OPC_RSQRT_D = FOP(22, FMT_D), 9113 OPC_SELNEZ_D = FOP(23, FMT_D), 9114 OPC_MADDF_D = FOP(24, FMT_D), 9115 OPC_MSUBF_D = FOP(25, FMT_D), 9116 OPC_RINT_D = FOP(26, FMT_D), 9117 OPC_CLASS_D = FOP(27, FMT_D), 9118 OPC_MIN_D = FOP(28, FMT_D), 9119 OPC_RECIP2_D = FOP(28, FMT_D), 9120 OPC_MINA_D = FOP(29, FMT_D), 9121 OPC_RECIP1_D = FOP(29, FMT_D), 9122 OPC_MAX_D = FOP(30, FMT_D), 9123 OPC_RSQRT1_D = FOP(30, FMT_D), 9124 OPC_MAXA_D = FOP(31, FMT_D), 9125 OPC_RSQRT2_D = FOP(31, FMT_D), 9126 OPC_CVT_S_D = FOP(32, FMT_D), 9127 OPC_CVT_W_D = FOP(36, FMT_D), 9128 OPC_CVT_L_D = FOP(37, FMT_D), 9129 OPC_CMP_F_D = FOP(48, FMT_D), 9130 OPC_CMP_UN_D = FOP(49, FMT_D), 9131 OPC_CMP_EQ_D = FOP(50, FMT_D), 9132 OPC_CMP_UEQ_D = FOP(51, FMT_D), 9133 OPC_CMP_OLT_D = FOP(52, FMT_D), 9134 OPC_CMP_ULT_D = FOP(53, FMT_D), 9135 OPC_CMP_OLE_D = FOP(54, FMT_D), 9136 OPC_CMP_ULE_D = FOP(55, FMT_D), 9137 OPC_CMP_SF_D = FOP(56, FMT_D), 9138 OPC_CMP_NGLE_D = FOP(57, FMT_D), 9139 OPC_CMP_SEQ_D = FOP(58, FMT_D), 9140 OPC_CMP_NGL_D = FOP(59, FMT_D), 9141 OPC_CMP_LT_D = FOP(60, FMT_D), 9142 OPC_CMP_NGE_D = FOP(61, FMT_D), 9143 OPC_CMP_LE_D = FOP(62, FMT_D), 9144 OPC_CMP_NGT_D = FOP(63, FMT_D), 9145 9146 OPC_CVT_S_W = FOP(32, FMT_W), 9147 OPC_CVT_D_W = FOP(33, FMT_W), 9148 OPC_CVT_S_L = FOP(32, FMT_L), 9149 OPC_CVT_D_L = FOP(33, FMT_L), 9150 OPC_CVT_PS_PW = FOP(38, FMT_W), 9151 9152 OPC_ADD_PS = FOP(0, FMT_PS), 9153 OPC_SUB_PS = FOP(1, FMT_PS), 9154 OPC_MUL_PS = FOP(2, FMT_PS), 9155 OPC_DIV_PS = FOP(3, FMT_PS), 9156 OPC_ABS_PS = FOP(5, FMT_PS), 9157 OPC_MOV_PS = FOP(6, FMT_PS), 9158 OPC_NEG_PS = FOP(7, FMT_PS), 9159 OPC_MOVCF_PS = FOP(17, FMT_PS), 9160 OPC_MOVZ_PS = FOP(18, FMT_PS), 9161 OPC_MOVN_PS = FOP(19, FMT_PS), 9162 OPC_ADDR_PS = FOP(24, FMT_PS), 9163 OPC_MULR_PS = FOP(26, FMT_PS), 9164 OPC_RECIP2_PS = FOP(28, FMT_PS), 9165 OPC_RECIP1_PS = FOP(29, FMT_PS), 9166 OPC_RSQRT1_PS = FOP(30, FMT_PS), 9167 OPC_RSQRT2_PS = FOP(31, FMT_PS), 9168 9169 OPC_CVT_S_PU = FOP(32, FMT_PS), 9170 OPC_CVT_PW_PS = FOP(36, FMT_PS), 9171 OPC_CVT_S_PL = FOP(40, FMT_PS), 9172 OPC_PLL_PS = FOP(44, FMT_PS), 9173 OPC_PLU_PS = FOP(45, FMT_PS), 9174 OPC_PUL_PS = FOP(46, FMT_PS), 9175 OPC_PUU_PS = FOP(47, FMT_PS), 9176 OPC_CMP_F_PS = FOP(48, FMT_PS), 9177 OPC_CMP_UN_PS = FOP(49, FMT_PS), 9178 OPC_CMP_EQ_PS = FOP(50, FMT_PS), 9179 OPC_CMP_UEQ_PS = FOP(51, FMT_PS), 9180 OPC_CMP_OLT_PS = FOP(52, FMT_PS), 9181 OPC_CMP_ULT_PS = FOP(53, FMT_PS), 9182 OPC_CMP_OLE_PS = FOP(54, FMT_PS), 9183 OPC_CMP_ULE_PS = FOP(55, FMT_PS), 9184 OPC_CMP_SF_PS = FOP(56, FMT_PS), 9185 OPC_CMP_NGLE_PS = FOP(57, FMT_PS), 9186 OPC_CMP_SEQ_PS = FOP(58, FMT_PS), 9187 OPC_CMP_NGL_PS = FOP(59, FMT_PS), 9188 OPC_CMP_LT_PS = FOP(60, FMT_PS), 9189 OPC_CMP_NGE_PS = FOP(61, FMT_PS), 9190 OPC_CMP_LE_PS = FOP(62, FMT_PS), 9191 OPC_CMP_NGT_PS = FOP(63, FMT_PS), 9192 }; 9193 9194 enum r6_f_cmp_op { 9195 R6_OPC_CMP_AF_S = FOP(0, FMT_W), 9196 R6_OPC_CMP_UN_S = FOP(1, FMT_W), 9197 R6_OPC_CMP_EQ_S = FOP(2, FMT_W), 9198 R6_OPC_CMP_UEQ_S = FOP(3, FMT_W), 9199 R6_OPC_CMP_LT_S = FOP(4, FMT_W), 9200 R6_OPC_CMP_ULT_S = FOP(5, FMT_W), 9201 R6_OPC_CMP_LE_S = FOP(6, FMT_W), 9202 R6_OPC_CMP_ULE_S = FOP(7, FMT_W), 9203 R6_OPC_CMP_SAF_S = FOP(8, FMT_W), 9204 R6_OPC_CMP_SUN_S = FOP(9, FMT_W), 9205 R6_OPC_CMP_SEQ_S = FOP(10, FMT_W), 9206 R6_OPC_CMP_SEUQ_S = FOP(11, FMT_W), 9207 R6_OPC_CMP_SLT_S = FOP(12, FMT_W), 9208 R6_OPC_CMP_SULT_S = FOP(13, FMT_W), 9209 R6_OPC_CMP_SLE_S = FOP(14, FMT_W), 9210 R6_OPC_CMP_SULE_S = FOP(15, FMT_W), 9211 R6_OPC_CMP_OR_S = FOP(17, FMT_W), 9212 R6_OPC_CMP_UNE_S = FOP(18, FMT_W), 9213 R6_OPC_CMP_NE_S = FOP(19, FMT_W), 9214 R6_OPC_CMP_SOR_S = FOP(25, FMT_W), 9215 R6_OPC_CMP_SUNE_S = FOP(26, FMT_W), 9216 R6_OPC_CMP_SNE_S = FOP(27, FMT_W), 9217 9218 R6_OPC_CMP_AF_D = FOP(0, FMT_L), 9219 R6_OPC_CMP_UN_D = FOP(1, FMT_L), 9220 R6_OPC_CMP_EQ_D = FOP(2, FMT_L), 9221 R6_OPC_CMP_UEQ_D = FOP(3, FMT_L), 9222 R6_OPC_CMP_LT_D = FOP(4, FMT_L), 9223 R6_OPC_CMP_ULT_D = FOP(5, FMT_L), 9224 R6_OPC_CMP_LE_D = FOP(6, FMT_L), 9225 R6_OPC_CMP_ULE_D = FOP(7, FMT_L), 9226 R6_OPC_CMP_SAF_D = FOP(8, FMT_L), 9227 R6_OPC_CMP_SUN_D = FOP(9, FMT_L), 9228 R6_OPC_CMP_SEQ_D = FOP(10, FMT_L), 9229 R6_OPC_CMP_SEUQ_D = FOP(11, FMT_L), 9230 R6_OPC_CMP_SLT_D = FOP(12, FMT_L), 9231 R6_OPC_CMP_SULT_D = FOP(13, FMT_L), 9232 R6_OPC_CMP_SLE_D = FOP(14, FMT_L), 9233 R6_OPC_CMP_SULE_D = FOP(15, FMT_L), 9234 R6_OPC_CMP_OR_D = FOP(17, FMT_L), 9235 R6_OPC_CMP_UNE_D = FOP(18, FMT_L), 9236 R6_OPC_CMP_NE_D = FOP(19, FMT_L), 9237 R6_OPC_CMP_SOR_D = FOP(25, FMT_L), 9238 R6_OPC_CMP_SUNE_D = FOP(26, FMT_L), 9239 R6_OPC_CMP_SNE_D = FOP(27, FMT_L), 9240 }; 9241 9242 static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs) 9243 { 9244 TCGv t0 = tcg_temp_new(); 9245 9246 switch (opc) { 9247 case OPC_MFC1: 9248 { 9249 TCGv_i32 fp0 = tcg_temp_new_i32(); 9250 9251 gen_load_fpr32(ctx, fp0, fs); 9252 tcg_gen_ext_i32_tl(t0, fp0); 9253 } 9254 gen_store_gpr(t0, rt); 9255 break; 9256 case OPC_MTC1: 9257 gen_load_gpr(t0, rt); 9258 { 9259 TCGv_i32 fp0 = tcg_temp_new_i32(); 9260 9261 tcg_gen_trunc_tl_i32(fp0, t0); 9262 gen_store_fpr32(ctx, fp0, fs); 9263 } 9264 break; 9265 case OPC_CFC1: 9266 gen_helper_1e0i(cfc1, t0, fs); 9267 gen_store_gpr(t0, rt); 9268 break; 9269 case OPC_CTC1: 9270 gen_load_gpr(t0, rt); 9271 save_cpu_state(ctx, 0); 9272 gen_helper_0e2i(ctc1, t0, tcg_constant_i32(fs), rt); 9273 /* Stop translation as we may have changed hflags */ 9274 ctx->base.is_jmp = DISAS_STOP; 9275 break; 9276 #if defined(TARGET_MIPS64) 9277 case OPC_DMFC1: 9278 gen_load_fpr64(ctx, t0, fs); 9279 gen_store_gpr(t0, rt); 9280 break; 9281 case OPC_DMTC1: 9282 gen_load_gpr(t0, rt); 9283 gen_store_fpr64(ctx, t0, fs); 9284 break; 9285 #endif 9286 case OPC_MFHC1: 9287 { 9288 TCGv_i32 fp0 = tcg_temp_new_i32(); 9289 9290 gen_load_fpr32h(ctx, fp0, fs); 9291 tcg_gen_ext_i32_tl(t0, fp0); 9292 } 9293 gen_store_gpr(t0, rt); 9294 break; 9295 case OPC_MTHC1: 9296 gen_load_gpr(t0, rt); 9297 { 9298 TCGv_i32 fp0 = tcg_temp_new_i32(); 9299 9300 tcg_gen_trunc_tl_i32(fp0, t0); 9301 gen_store_fpr32h(ctx, fp0, fs); 9302 } 9303 break; 9304 default: 9305 MIPS_INVAL("cp1 move"); 9306 gen_reserved_instruction(ctx); 9307 return; 9308 } 9309 } 9310 9311 static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf) 9312 { 9313 TCGLabel *l1; 9314 TCGCond cond; 9315 TCGv_i32 t0; 9316 9317 if (rd == 0) { 9318 /* Treat as NOP. */ 9319 return; 9320 } 9321 9322 if (tf) { 9323 cond = TCG_COND_EQ; 9324 } else { 9325 cond = TCG_COND_NE; 9326 } 9327 9328 l1 = gen_new_label(); 9329 t0 = tcg_temp_new_i32(); 9330 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); 9331 tcg_gen_brcondi_i32(cond, t0, 0, l1); 9332 gen_load_gpr(cpu_gpr[rd], rs); 9333 gen_set_label(l1); 9334 } 9335 9336 static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc, 9337 int tf) 9338 { 9339 int cond; 9340 TCGv_i32 t0 = tcg_temp_new_i32(); 9341 TCGLabel *l1 = gen_new_label(); 9342 9343 if (tf) { 9344 cond = TCG_COND_EQ; 9345 } else { 9346 cond = TCG_COND_NE; 9347 } 9348 9349 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); 9350 tcg_gen_brcondi_i32(cond, t0, 0, l1); 9351 gen_load_fpr32(ctx, t0, fs); 9352 gen_store_fpr32(ctx, t0, fd); 9353 gen_set_label(l1); 9354 } 9355 9356 static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc, 9357 int tf) 9358 { 9359 int cond; 9360 TCGv_i32 t0 = tcg_temp_new_i32(); 9361 TCGv_i64 fp0; 9362 TCGLabel *l1 = gen_new_label(); 9363 9364 if (tf) { 9365 cond = TCG_COND_EQ; 9366 } else { 9367 cond = TCG_COND_NE; 9368 } 9369 9370 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); 9371 tcg_gen_brcondi_i32(cond, t0, 0, l1); 9372 fp0 = tcg_temp_new_i64(); 9373 gen_load_fpr64(ctx, fp0, fs); 9374 gen_store_fpr64(ctx, fp0, fd); 9375 gen_set_label(l1); 9376 } 9377 9378 static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd, 9379 int cc, int tf) 9380 { 9381 int cond; 9382 TCGv_i32 t0 = tcg_temp_new_i32(); 9383 TCGLabel *l1 = gen_new_label(); 9384 TCGLabel *l2 = gen_new_label(); 9385 9386 if (tf) { 9387 cond = TCG_COND_EQ; 9388 } else { 9389 cond = TCG_COND_NE; 9390 } 9391 9392 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); 9393 tcg_gen_brcondi_i32(cond, t0, 0, l1); 9394 gen_load_fpr32(ctx, t0, fs); 9395 gen_store_fpr32(ctx, t0, fd); 9396 gen_set_label(l1); 9397 9398 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc + 1)); 9399 tcg_gen_brcondi_i32(cond, t0, 0, l2); 9400 gen_load_fpr32h(ctx, t0, fs); 9401 gen_store_fpr32h(ctx, t0, fd); 9402 gen_set_label(l2); 9403 } 9404 9405 static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft, 9406 int fs) 9407 { 9408 TCGv_i32 t1 = tcg_constant_i32(0); 9409 TCGv_i32 fp0 = tcg_temp_new_i32(); 9410 TCGv_i32 fp1 = tcg_temp_new_i32(); 9411 TCGv_i32 fp2 = tcg_temp_new_i32(); 9412 gen_load_fpr32(ctx, fp0, fd); 9413 gen_load_fpr32(ctx, fp1, ft); 9414 gen_load_fpr32(ctx, fp2, fs); 9415 9416 switch (op1) { 9417 case OPC_SEL_S: 9418 tcg_gen_andi_i32(fp0, fp0, 1); 9419 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp0, t1, fp1, fp2); 9420 break; 9421 case OPC_SELEQZ_S: 9422 tcg_gen_andi_i32(fp1, fp1, 1); 9423 tcg_gen_movcond_i32(TCG_COND_EQ, fp0, fp1, t1, fp2, t1); 9424 break; 9425 case OPC_SELNEZ_S: 9426 tcg_gen_andi_i32(fp1, fp1, 1); 9427 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp1, t1, fp2, t1); 9428 break; 9429 default: 9430 MIPS_INVAL("gen_sel_s"); 9431 gen_reserved_instruction(ctx); 9432 break; 9433 } 9434 9435 gen_store_fpr32(ctx, fp0, fd); 9436 } 9437 9438 static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft, 9439 int fs) 9440 { 9441 TCGv_i64 t1 = tcg_constant_i64(0); 9442 TCGv_i64 fp0 = tcg_temp_new_i64(); 9443 TCGv_i64 fp1 = tcg_temp_new_i64(); 9444 TCGv_i64 fp2 = tcg_temp_new_i64(); 9445 gen_load_fpr64(ctx, fp0, fd); 9446 gen_load_fpr64(ctx, fp1, ft); 9447 gen_load_fpr64(ctx, fp2, fs); 9448 9449 switch (op1) { 9450 case OPC_SEL_D: 9451 tcg_gen_andi_i64(fp0, fp0, 1); 9452 tcg_gen_movcond_i64(TCG_COND_NE, fp0, fp0, t1, fp1, fp2); 9453 break; 9454 case OPC_SELEQZ_D: 9455 tcg_gen_andi_i64(fp1, fp1, 1); 9456 tcg_gen_movcond_i64(TCG_COND_EQ, fp0, fp1, t1, fp2, t1); 9457 break; 9458 case OPC_SELNEZ_D: 9459 tcg_gen_andi_i64(fp1, fp1, 1); 9460 tcg_gen_movcond_i64(TCG_COND_NE, fp0, fp1, t1, fp2, t1); 9461 break; 9462 default: 9463 MIPS_INVAL("gen_sel_d"); 9464 gen_reserved_instruction(ctx); 9465 break; 9466 } 9467 9468 gen_store_fpr64(ctx, fp0, fd); 9469 } 9470 9471 static void gen_farith(DisasContext *ctx, enum fopcode op1, 9472 int ft, int fs, int fd, int cc) 9473 { 9474 uint32_t func = ctx->opcode & 0x3f; 9475 switch (op1) { 9476 case OPC_ADD_S: 9477 { 9478 TCGv_i32 fp0 = tcg_temp_new_i32(); 9479 TCGv_i32 fp1 = tcg_temp_new_i32(); 9480 9481 gen_load_fpr32(ctx, fp0, fs); 9482 gen_load_fpr32(ctx, fp1, ft); 9483 gen_helper_float_add_s(fp0, tcg_env, fp0, fp1); 9484 gen_store_fpr32(ctx, fp0, fd); 9485 } 9486 break; 9487 case OPC_SUB_S: 9488 { 9489 TCGv_i32 fp0 = tcg_temp_new_i32(); 9490 TCGv_i32 fp1 = tcg_temp_new_i32(); 9491 9492 gen_load_fpr32(ctx, fp0, fs); 9493 gen_load_fpr32(ctx, fp1, ft); 9494 gen_helper_float_sub_s(fp0, tcg_env, fp0, fp1); 9495 gen_store_fpr32(ctx, fp0, fd); 9496 } 9497 break; 9498 case OPC_MUL_S: 9499 { 9500 TCGv_i32 fp0 = tcg_temp_new_i32(); 9501 TCGv_i32 fp1 = tcg_temp_new_i32(); 9502 9503 gen_load_fpr32(ctx, fp0, fs); 9504 gen_load_fpr32(ctx, fp1, ft); 9505 gen_helper_float_mul_s(fp0, tcg_env, fp0, fp1); 9506 gen_store_fpr32(ctx, fp0, fd); 9507 } 9508 break; 9509 case OPC_DIV_S: 9510 { 9511 TCGv_i32 fp0 = tcg_temp_new_i32(); 9512 TCGv_i32 fp1 = tcg_temp_new_i32(); 9513 9514 gen_load_fpr32(ctx, fp0, fs); 9515 gen_load_fpr32(ctx, fp1, ft); 9516 gen_helper_float_div_s(fp0, tcg_env, fp0, fp1); 9517 gen_store_fpr32(ctx, fp0, fd); 9518 } 9519 break; 9520 case OPC_SQRT_S: 9521 { 9522 TCGv_i32 fp0 = tcg_temp_new_i32(); 9523 9524 gen_load_fpr32(ctx, fp0, fs); 9525 gen_helper_float_sqrt_s(fp0, tcg_env, fp0); 9526 gen_store_fpr32(ctx, fp0, fd); 9527 } 9528 break; 9529 case OPC_ABS_S: 9530 { 9531 TCGv_i32 fp0 = tcg_temp_new_i32(); 9532 9533 gen_load_fpr32(ctx, fp0, fs); 9534 if (ctx->abs2008) { 9535 tcg_gen_andi_i32(fp0, fp0, 0x7fffffffUL); 9536 } else { 9537 gen_helper_float_abs_s(fp0, fp0); 9538 } 9539 gen_store_fpr32(ctx, fp0, fd); 9540 } 9541 break; 9542 case OPC_MOV_S: 9543 { 9544 TCGv_i32 fp0 = tcg_temp_new_i32(); 9545 9546 gen_load_fpr32(ctx, fp0, fs); 9547 gen_store_fpr32(ctx, fp0, fd); 9548 } 9549 break; 9550 case OPC_NEG_S: 9551 { 9552 TCGv_i32 fp0 = tcg_temp_new_i32(); 9553 9554 gen_load_fpr32(ctx, fp0, fs); 9555 if (ctx->abs2008) { 9556 tcg_gen_xori_i32(fp0, fp0, 1UL << 31); 9557 } else { 9558 gen_helper_float_chs_s(fp0, fp0); 9559 } 9560 gen_store_fpr32(ctx, fp0, fd); 9561 } 9562 break; 9563 case OPC_ROUND_L_S: 9564 check_cp1_64bitmode(ctx); 9565 { 9566 TCGv_i32 fp32 = tcg_temp_new_i32(); 9567 TCGv_i64 fp64 = tcg_temp_new_i64(); 9568 9569 gen_load_fpr32(ctx, fp32, fs); 9570 if (ctx->nan2008) { 9571 gen_helper_float_round_2008_l_s(fp64, tcg_env, fp32); 9572 } else { 9573 gen_helper_float_round_l_s(fp64, tcg_env, fp32); 9574 } 9575 gen_store_fpr64(ctx, fp64, fd); 9576 } 9577 break; 9578 case OPC_TRUNC_L_S: 9579 check_cp1_64bitmode(ctx); 9580 { 9581 TCGv_i32 fp32 = tcg_temp_new_i32(); 9582 TCGv_i64 fp64 = tcg_temp_new_i64(); 9583 9584 gen_load_fpr32(ctx, fp32, fs); 9585 if (ctx->nan2008) { 9586 gen_helper_float_trunc_2008_l_s(fp64, tcg_env, fp32); 9587 } else { 9588 gen_helper_float_trunc_l_s(fp64, tcg_env, fp32); 9589 } 9590 gen_store_fpr64(ctx, fp64, fd); 9591 } 9592 break; 9593 case OPC_CEIL_L_S: 9594 check_cp1_64bitmode(ctx); 9595 { 9596 TCGv_i32 fp32 = tcg_temp_new_i32(); 9597 TCGv_i64 fp64 = tcg_temp_new_i64(); 9598 9599 gen_load_fpr32(ctx, fp32, fs); 9600 if (ctx->nan2008) { 9601 gen_helper_float_ceil_2008_l_s(fp64, tcg_env, fp32); 9602 } else { 9603 gen_helper_float_ceil_l_s(fp64, tcg_env, fp32); 9604 } 9605 gen_store_fpr64(ctx, fp64, fd); 9606 } 9607 break; 9608 case OPC_FLOOR_L_S: 9609 check_cp1_64bitmode(ctx); 9610 { 9611 TCGv_i32 fp32 = tcg_temp_new_i32(); 9612 TCGv_i64 fp64 = tcg_temp_new_i64(); 9613 9614 gen_load_fpr32(ctx, fp32, fs); 9615 if (ctx->nan2008) { 9616 gen_helper_float_floor_2008_l_s(fp64, tcg_env, fp32); 9617 } else { 9618 gen_helper_float_floor_l_s(fp64, tcg_env, fp32); 9619 } 9620 gen_store_fpr64(ctx, fp64, fd); 9621 } 9622 break; 9623 case OPC_ROUND_W_S: 9624 { 9625 TCGv_i32 fp0 = tcg_temp_new_i32(); 9626 9627 gen_load_fpr32(ctx, fp0, fs); 9628 if (ctx->nan2008) { 9629 gen_helper_float_round_2008_w_s(fp0, tcg_env, fp0); 9630 } else { 9631 gen_helper_float_round_w_s(fp0, tcg_env, fp0); 9632 } 9633 gen_store_fpr32(ctx, fp0, fd); 9634 } 9635 break; 9636 case OPC_TRUNC_W_S: 9637 { 9638 TCGv_i32 fp0 = tcg_temp_new_i32(); 9639 9640 gen_load_fpr32(ctx, fp0, fs); 9641 if (ctx->nan2008) { 9642 gen_helper_float_trunc_2008_w_s(fp0, tcg_env, fp0); 9643 } else { 9644 gen_helper_float_trunc_w_s(fp0, tcg_env, fp0); 9645 } 9646 gen_store_fpr32(ctx, fp0, fd); 9647 } 9648 break; 9649 case OPC_CEIL_W_S: 9650 { 9651 TCGv_i32 fp0 = tcg_temp_new_i32(); 9652 9653 gen_load_fpr32(ctx, fp0, fs); 9654 if (ctx->nan2008) { 9655 gen_helper_float_ceil_2008_w_s(fp0, tcg_env, fp0); 9656 } else { 9657 gen_helper_float_ceil_w_s(fp0, tcg_env, fp0); 9658 } 9659 gen_store_fpr32(ctx, fp0, fd); 9660 } 9661 break; 9662 case OPC_FLOOR_W_S: 9663 { 9664 TCGv_i32 fp0 = tcg_temp_new_i32(); 9665 9666 gen_load_fpr32(ctx, fp0, fs); 9667 if (ctx->nan2008) { 9668 gen_helper_float_floor_2008_w_s(fp0, tcg_env, fp0); 9669 } else { 9670 gen_helper_float_floor_w_s(fp0, tcg_env, fp0); 9671 } 9672 gen_store_fpr32(ctx, fp0, fd); 9673 } 9674 break; 9675 case OPC_SEL_S: 9676 check_insn(ctx, ISA_MIPS_R6); 9677 gen_sel_s(ctx, op1, fd, ft, fs); 9678 break; 9679 case OPC_SELEQZ_S: 9680 check_insn(ctx, ISA_MIPS_R6); 9681 gen_sel_s(ctx, op1, fd, ft, fs); 9682 break; 9683 case OPC_SELNEZ_S: 9684 check_insn(ctx, ISA_MIPS_R6); 9685 gen_sel_s(ctx, op1, fd, ft, fs); 9686 break; 9687 case OPC_MOVCF_S: 9688 check_insn_opc_removed(ctx, ISA_MIPS_R6); 9689 gen_movcf_s(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); 9690 break; 9691 case OPC_MOVZ_S: 9692 check_insn_opc_removed(ctx, ISA_MIPS_R6); 9693 { 9694 TCGLabel *l1 = gen_new_label(); 9695 TCGv_i32 fp0; 9696 9697 if (ft != 0) { 9698 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); 9699 } 9700 fp0 = tcg_temp_new_i32(); 9701 gen_load_fpr32(ctx, fp0, fs); 9702 gen_store_fpr32(ctx, fp0, fd); 9703 gen_set_label(l1); 9704 } 9705 break; 9706 case OPC_MOVN_S: 9707 check_insn_opc_removed(ctx, ISA_MIPS_R6); 9708 { 9709 TCGLabel *l1 = gen_new_label(); 9710 TCGv_i32 fp0; 9711 9712 if (ft != 0) { 9713 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); 9714 fp0 = tcg_temp_new_i32(); 9715 gen_load_fpr32(ctx, fp0, fs); 9716 gen_store_fpr32(ctx, fp0, fd); 9717 gen_set_label(l1); 9718 } 9719 } 9720 break; 9721 case OPC_RECIP_S: 9722 { 9723 TCGv_i32 fp0 = tcg_temp_new_i32(); 9724 9725 gen_load_fpr32(ctx, fp0, fs); 9726 gen_helper_float_recip_s(fp0, tcg_env, fp0); 9727 gen_store_fpr32(ctx, fp0, fd); 9728 } 9729 break; 9730 case OPC_RSQRT_S: 9731 { 9732 TCGv_i32 fp0 = tcg_temp_new_i32(); 9733 9734 gen_load_fpr32(ctx, fp0, fs); 9735 gen_helper_float_rsqrt_s(fp0, tcg_env, fp0); 9736 gen_store_fpr32(ctx, fp0, fd); 9737 } 9738 break; 9739 case OPC_MADDF_S: 9740 check_insn(ctx, ISA_MIPS_R6); 9741 { 9742 TCGv_i32 fp0 = tcg_temp_new_i32(); 9743 TCGv_i32 fp1 = tcg_temp_new_i32(); 9744 TCGv_i32 fp2 = tcg_temp_new_i32(); 9745 gen_load_fpr32(ctx, fp0, fs); 9746 gen_load_fpr32(ctx, fp1, ft); 9747 gen_load_fpr32(ctx, fp2, fd); 9748 gen_helper_float_maddf_s(fp2, tcg_env, fp0, fp1, fp2); 9749 gen_store_fpr32(ctx, fp2, fd); 9750 } 9751 break; 9752 case OPC_MSUBF_S: 9753 check_insn(ctx, ISA_MIPS_R6); 9754 { 9755 TCGv_i32 fp0 = tcg_temp_new_i32(); 9756 TCGv_i32 fp1 = tcg_temp_new_i32(); 9757 TCGv_i32 fp2 = tcg_temp_new_i32(); 9758 gen_load_fpr32(ctx, fp0, fs); 9759 gen_load_fpr32(ctx, fp1, ft); 9760 gen_load_fpr32(ctx, fp2, fd); 9761 gen_helper_float_msubf_s(fp2, tcg_env, fp0, fp1, fp2); 9762 gen_store_fpr32(ctx, fp2, fd); 9763 } 9764 break; 9765 case OPC_RINT_S: 9766 check_insn(ctx, ISA_MIPS_R6); 9767 { 9768 TCGv_i32 fp0 = tcg_temp_new_i32(); 9769 gen_load_fpr32(ctx, fp0, fs); 9770 gen_helper_float_rint_s(fp0, tcg_env, fp0); 9771 gen_store_fpr32(ctx, fp0, fd); 9772 } 9773 break; 9774 case OPC_CLASS_S: 9775 check_insn(ctx, ISA_MIPS_R6); 9776 { 9777 TCGv_i32 fp0 = tcg_temp_new_i32(); 9778 gen_load_fpr32(ctx, fp0, fs); 9779 gen_helper_float_class_s(fp0, tcg_env, fp0); 9780 gen_store_fpr32(ctx, fp0, fd); 9781 } 9782 break; 9783 case OPC_MIN_S: /* OPC_RECIP2_S */ 9784 if (ctx->insn_flags & ISA_MIPS_R6) { 9785 /* OPC_MIN_S */ 9786 TCGv_i32 fp0 = tcg_temp_new_i32(); 9787 TCGv_i32 fp1 = tcg_temp_new_i32(); 9788 TCGv_i32 fp2 = tcg_temp_new_i32(); 9789 gen_load_fpr32(ctx, fp0, fs); 9790 gen_load_fpr32(ctx, fp1, ft); 9791 gen_helper_float_min_s(fp2, tcg_env, fp0, fp1); 9792 gen_store_fpr32(ctx, fp2, fd); 9793 } else { 9794 /* OPC_RECIP2_S */ 9795 check_cp1_64bitmode(ctx); 9796 { 9797 TCGv_i32 fp0 = tcg_temp_new_i32(); 9798 TCGv_i32 fp1 = tcg_temp_new_i32(); 9799 9800 gen_load_fpr32(ctx, fp0, fs); 9801 gen_load_fpr32(ctx, fp1, ft); 9802 gen_helper_float_recip2_s(fp0, tcg_env, fp0, fp1); 9803 gen_store_fpr32(ctx, fp0, fd); 9804 } 9805 } 9806 break; 9807 case OPC_MINA_S: /* OPC_RECIP1_S */ 9808 if (ctx->insn_flags & ISA_MIPS_R6) { 9809 /* OPC_MINA_S */ 9810 TCGv_i32 fp0 = tcg_temp_new_i32(); 9811 TCGv_i32 fp1 = tcg_temp_new_i32(); 9812 TCGv_i32 fp2 = tcg_temp_new_i32(); 9813 gen_load_fpr32(ctx, fp0, fs); 9814 gen_load_fpr32(ctx, fp1, ft); 9815 gen_helper_float_mina_s(fp2, tcg_env, fp0, fp1); 9816 gen_store_fpr32(ctx, fp2, fd); 9817 } else { 9818 /* OPC_RECIP1_S */ 9819 check_cp1_64bitmode(ctx); 9820 { 9821 TCGv_i32 fp0 = tcg_temp_new_i32(); 9822 9823 gen_load_fpr32(ctx, fp0, fs); 9824 gen_helper_float_recip1_s(fp0, tcg_env, fp0); 9825 gen_store_fpr32(ctx, fp0, fd); 9826 } 9827 } 9828 break; 9829 case OPC_MAX_S: /* OPC_RSQRT1_S */ 9830 if (ctx->insn_flags & ISA_MIPS_R6) { 9831 /* OPC_MAX_S */ 9832 TCGv_i32 fp0 = tcg_temp_new_i32(); 9833 TCGv_i32 fp1 = tcg_temp_new_i32(); 9834 gen_load_fpr32(ctx, fp0, fs); 9835 gen_load_fpr32(ctx, fp1, ft); 9836 gen_helper_float_max_s(fp1, tcg_env, fp0, fp1); 9837 gen_store_fpr32(ctx, fp1, fd); 9838 } else { 9839 /* OPC_RSQRT1_S */ 9840 check_cp1_64bitmode(ctx); 9841 { 9842 TCGv_i32 fp0 = tcg_temp_new_i32(); 9843 9844 gen_load_fpr32(ctx, fp0, fs); 9845 gen_helper_float_rsqrt1_s(fp0, tcg_env, fp0); 9846 gen_store_fpr32(ctx, fp0, fd); 9847 } 9848 } 9849 break; 9850 case OPC_MAXA_S: /* OPC_RSQRT2_S */ 9851 if (ctx->insn_flags & ISA_MIPS_R6) { 9852 /* OPC_MAXA_S */ 9853 TCGv_i32 fp0 = tcg_temp_new_i32(); 9854 TCGv_i32 fp1 = tcg_temp_new_i32(); 9855 gen_load_fpr32(ctx, fp0, fs); 9856 gen_load_fpr32(ctx, fp1, ft); 9857 gen_helper_float_maxa_s(fp1, tcg_env, fp0, fp1); 9858 gen_store_fpr32(ctx, fp1, fd); 9859 } else { 9860 /* OPC_RSQRT2_S */ 9861 check_cp1_64bitmode(ctx); 9862 { 9863 TCGv_i32 fp0 = tcg_temp_new_i32(); 9864 TCGv_i32 fp1 = tcg_temp_new_i32(); 9865 9866 gen_load_fpr32(ctx, fp0, fs); 9867 gen_load_fpr32(ctx, fp1, ft); 9868 gen_helper_float_rsqrt2_s(fp0, tcg_env, fp0, fp1); 9869 gen_store_fpr32(ctx, fp0, fd); 9870 } 9871 } 9872 break; 9873 case OPC_CVT_D_S: 9874 check_cp1_registers(ctx, fd); 9875 { 9876 TCGv_i32 fp32 = tcg_temp_new_i32(); 9877 TCGv_i64 fp64 = tcg_temp_new_i64(); 9878 9879 gen_load_fpr32(ctx, fp32, fs); 9880 gen_helper_float_cvtd_s(fp64, tcg_env, fp32); 9881 gen_store_fpr64(ctx, fp64, fd); 9882 } 9883 break; 9884 case OPC_CVT_W_S: 9885 { 9886 TCGv_i32 fp0 = tcg_temp_new_i32(); 9887 9888 gen_load_fpr32(ctx, fp0, fs); 9889 if (ctx->nan2008) { 9890 gen_helper_float_cvt_2008_w_s(fp0, tcg_env, fp0); 9891 } else { 9892 gen_helper_float_cvt_w_s(fp0, tcg_env, fp0); 9893 } 9894 gen_store_fpr32(ctx, fp0, fd); 9895 } 9896 break; 9897 case OPC_CVT_L_S: 9898 check_cp1_64bitmode(ctx); 9899 { 9900 TCGv_i32 fp32 = tcg_temp_new_i32(); 9901 TCGv_i64 fp64 = tcg_temp_new_i64(); 9902 9903 gen_load_fpr32(ctx, fp32, fs); 9904 if (ctx->nan2008) { 9905 gen_helper_float_cvt_2008_l_s(fp64, tcg_env, fp32); 9906 } else { 9907 gen_helper_float_cvt_l_s(fp64, tcg_env, fp32); 9908 } 9909 gen_store_fpr64(ctx, fp64, fd); 9910 } 9911 break; 9912 case OPC_CVT_PS_S: 9913 check_ps(ctx); 9914 { 9915 TCGv_i64 fp64 = tcg_temp_new_i64(); 9916 TCGv_i32 fp32_0 = tcg_temp_new_i32(); 9917 TCGv_i32 fp32_1 = tcg_temp_new_i32(); 9918 9919 gen_load_fpr32(ctx, fp32_0, fs); 9920 gen_load_fpr32(ctx, fp32_1, ft); 9921 tcg_gen_concat_i32_i64(fp64, fp32_1, fp32_0); 9922 gen_store_fpr64(ctx, fp64, fd); 9923 } 9924 break; 9925 case OPC_CMP_F_S: 9926 case OPC_CMP_UN_S: 9927 case OPC_CMP_EQ_S: 9928 case OPC_CMP_UEQ_S: 9929 case OPC_CMP_OLT_S: 9930 case OPC_CMP_ULT_S: 9931 case OPC_CMP_OLE_S: 9932 case OPC_CMP_ULE_S: 9933 case OPC_CMP_SF_S: 9934 case OPC_CMP_NGLE_S: 9935 case OPC_CMP_SEQ_S: 9936 case OPC_CMP_NGL_S: 9937 case OPC_CMP_LT_S: 9938 case OPC_CMP_NGE_S: 9939 case OPC_CMP_LE_S: 9940 case OPC_CMP_NGT_S: 9941 check_insn_opc_removed(ctx, ISA_MIPS_R6); 9942 if (ctx->opcode & (1 << 6)) { 9943 gen_cmpabs_s(ctx, func - 48, ft, fs, cc); 9944 } else { 9945 gen_cmp_s(ctx, func - 48, ft, fs, cc); 9946 } 9947 break; 9948 case OPC_ADD_D: 9949 check_cp1_registers(ctx, fs | ft | fd); 9950 { 9951 TCGv_i64 fp0 = tcg_temp_new_i64(); 9952 TCGv_i64 fp1 = tcg_temp_new_i64(); 9953 9954 gen_load_fpr64(ctx, fp0, fs); 9955 gen_load_fpr64(ctx, fp1, ft); 9956 gen_helper_float_add_d(fp0, tcg_env, fp0, fp1); 9957 gen_store_fpr64(ctx, fp0, fd); 9958 } 9959 break; 9960 case OPC_SUB_D: 9961 check_cp1_registers(ctx, fs | ft | fd); 9962 { 9963 TCGv_i64 fp0 = tcg_temp_new_i64(); 9964 TCGv_i64 fp1 = tcg_temp_new_i64(); 9965 9966 gen_load_fpr64(ctx, fp0, fs); 9967 gen_load_fpr64(ctx, fp1, ft); 9968 gen_helper_float_sub_d(fp0, tcg_env, fp0, fp1); 9969 gen_store_fpr64(ctx, fp0, fd); 9970 } 9971 break; 9972 case OPC_MUL_D: 9973 check_cp1_registers(ctx, fs | ft | fd); 9974 { 9975 TCGv_i64 fp0 = tcg_temp_new_i64(); 9976 TCGv_i64 fp1 = tcg_temp_new_i64(); 9977 9978 gen_load_fpr64(ctx, fp0, fs); 9979 gen_load_fpr64(ctx, fp1, ft); 9980 gen_helper_float_mul_d(fp0, tcg_env, fp0, fp1); 9981 gen_store_fpr64(ctx, fp0, fd); 9982 } 9983 break; 9984 case OPC_DIV_D: 9985 check_cp1_registers(ctx, fs | ft | fd); 9986 { 9987 TCGv_i64 fp0 = tcg_temp_new_i64(); 9988 TCGv_i64 fp1 = tcg_temp_new_i64(); 9989 9990 gen_load_fpr64(ctx, fp0, fs); 9991 gen_load_fpr64(ctx, fp1, ft); 9992 gen_helper_float_div_d(fp0, tcg_env, fp0, fp1); 9993 gen_store_fpr64(ctx, fp0, fd); 9994 } 9995 break; 9996 case OPC_SQRT_D: 9997 check_cp1_registers(ctx, fs | fd); 9998 { 9999 TCGv_i64 fp0 = tcg_temp_new_i64(); 10000 10001 gen_load_fpr64(ctx, fp0, fs); 10002 gen_helper_float_sqrt_d(fp0, tcg_env, fp0); 10003 gen_store_fpr64(ctx, fp0, fd); 10004 } 10005 break; 10006 case OPC_ABS_D: 10007 check_cp1_registers(ctx, fs | fd); 10008 { 10009 TCGv_i64 fp0 = tcg_temp_new_i64(); 10010 10011 gen_load_fpr64(ctx, fp0, fs); 10012 if (ctx->abs2008) { 10013 tcg_gen_andi_i64(fp0, fp0, 0x7fffffffffffffffULL); 10014 } else { 10015 gen_helper_float_abs_d(fp0, fp0); 10016 } 10017 gen_store_fpr64(ctx, fp0, fd); 10018 } 10019 break; 10020 case OPC_MOV_D: 10021 check_cp1_registers(ctx, fs | fd); 10022 { 10023 TCGv_i64 fp0 = tcg_temp_new_i64(); 10024 10025 gen_load_fpr64(ctx, fp0, fs); 10026 gen_store_fpr64(ctx, fp0, fd); 10027 } 10028 break; 10029 case OPC_NEG_D: 10030 check_cp1_registers(ctx, fs | fd); 10031 { 10032 TCGv_i64 fp0 = tcg_temp_new_i64(); 10033 10034 gen_load_fpr64(ctx, fp0, fs); 10035 if (ctx->abs2008) { 10036 tcg_gen_xori_i64(fp0, fp0, 1ULL << 63); 10037 } else { 10038 gen_helper_float_chs_d(fp0, fp0); 10039 } 10040 gen_store_fpr64(ctx, fp0, fd); 10041 } 10042 break; 10043 case OPC_ROUND_L_D: 10044 check_cp1_64bitmode(ctx); 10045 { 10046 TCGv_i64 fp0 = tcg_temp_new_i64(); 10047 10048 gen_load_fpr64(ctx, fp0, fs); 10049 if (ctx->nan2008) { 10050 gen_helper_float_round_2008_l_d(fp0, tcg_env, fp0); 10051 } else { 10052 gen_helper_float_round_l_d(fp0, tcg_env, fp0); 10053 } 10054 gen_store_fpr64(ctx, fp0, fd); 10055 } 10056 break; 10057 case OPC_TRUNC_L_D: 10058 check_cp1_64bitmode(ctx); 10059 { 10060 TCGv_i64 fp0 = tcg_temp_new_i64(); 10061 10062 gen_load_fpr64(ctx, fp0, fs); 10063 if (ctx->nan2008) { 10064 gen_helper_float_trunc_2008_l_d(fp0, tcg_env, fp0); 10065 } else { 10066 gen_helper_float_trunc_l_d(fp0, tcg_env, fp0); 10067 } 10068 gen_store_fpr64(ctx, fp0, fd); 10069 } 10070 break; 10071 case OPC_CEIL_L_D: 10072 check_cp1_64bitmode(ctx); 10073 { 10074 TCGv_i64 fp0 = tcg_temp_new_i64(); 10075 10076 gen_load_fpr64(ctx, fp0, fs); 10077 if (ctx->nan2008) { 10078 gen_helper_float_ceil_2008_l_d(fp0, tcg_env, fp0); 10079 } else { 10080 gen_helper_float_ceil_l_d(fp0, tcg_env, fp0); 10081 } 10082 gen_store_fpr64(ctx, fp0, fd); 10083 } 10084 break; 10085 case OPC_FLOOR_L_D: 10086 check_cp1_64bitmode(ctx); 10087 { 10088 TCGv_i64 fp0 = tcg_temp_new_i64(); 10089 10090 gen_load_fpr64(ctx, fp0, fs); 10091 if (ctx->nan2008) { 10092 gen_helper_float_floor_2008_l_d(fp0, tcg_env, fp0); 10093 } else { 10094 gen_helper_float_floor_l_d(fp0, tcg_env, fp0); 10095 } 10096 gen_store_fpr64(ctx, fp0, fd); 10097 } 10098 break; 10099 case OPC_ROUND_W_D: 10100 check_cp1_registers(ctx, fs); 10101 { 10102 TCGv_i32 fp32 = tcg_temp_new_i32(); 10103 TCGv_i64 fp64 = tcg_temp_new_i64(); 10104 10105 gen_load_fpr64(ctx, fp64, fs); 10106 if (ctx->nan2008) { 10107 gen_helper_float_round_2008_w_d(fp32, tcg_env, fp64); 10108 } else { 10109 gen_helper_float_round_w_d(fp32, tcg_env, fp64); 10110 } 10111 gen_store_fpr32(ctx, fp32, fd); 10112 } 10113 break; 10114 case OPC_TRUNC_W_D: 10115 check_cp1_registers(ctx, fs); 10116 { 10117 TCGv_i32 fp32 = tcg_temp_new_i32(); 10118 TCGv_i64 fp64 = tcg_temp_new_i64(); 10119 10120 gen_load_fpr64(ctx, fp64, fs); 10121 if (ctx->nan2008) { 10122 gen_helper_float_trunc_2008_w_d(fp32, tcg_env, fp64); 10123 } else { 10124 gen_helper_float_trunc_w_d(fp32, tcg_env, fp64); 10125 } 10126 gen_store_fpr32(ctx, fp32, fd); 10127 } 10128 break; 10129 case OPC_CEIL_W_D: 10130 check_cp1_registers(ctx, fs); 10131 { 10132 TCGv_i32 fp32 = tcg_temp_new_i32(); 10133 TCGv_i64 fp64 = tcg_temp_new_i64(); 10134 10135 gen_load_fpr64(ctx, fp64, fs); 10136 if (ctx->nan2008) { 10137 gen_helper_float_ceil_2008_w_d(fp32, tcg_env, fp64); 10138 } else { 10139 gen_helper_float_ceil_w_d(fp32, tcg_env, fp64); 10140 } 10141 gen_store_fpr32(ctx, fp32, fd); 10142 } 10143 break; 10144 case OPC_FLOOR_W_D: 10145 check_cp1_registers(ctx, fs); 10146 { 10147 TCGv_i32 fp32 = tcg_temp_new_i32(); 10148 TCGv_i64 fp64 = tcg_temp_new_i64(); 10149 10150 gen_load_fpr64(ctx, fp64, fs); 10151 if (ctx->nan2008) { 10152 gen_helper_float_floor_2008_w_d(fp32, tcg_env, fp64); 10153 } else { 10154 gen_helper_float_floor_w_d(fp32, tcg_env, fp64); 10155 } 10156 gen_store_fpr32(ctx, fp32, fd); 10157 } 10158 break; 10159 case OPC_SEL_D: 10160 check_insn(ctx, ISA_MIPS_R6); 10161 gen_sel_d(ctx, op1, fd, ft, fs); 10162 break; 10163 case OPC_SELEQZ_D: 10164 check_insn(ctx, ISA_MIPS_R6); 10165 gen_sel_d(ctx, op1, fd, ft, fs); 10166 break; 10167 case OPC_SELNEZ_D: 10168 check_insn(ctx, ISA_MIPS_R6); 10169 gen_sel_d(ctx, op1, fd, ft, fs); 10170 break; 10171 case OPC_MOVCF_D: 10172 check_insn_opc_removed(ctx, ISA_MIPS_R6); 10173 gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); 10174 break; 10175 case OPC_MOVZ_D: 10176 check_insn_opc_removed(ctx, ISA_MIPS_R6); 10177 { 10178 TCGLabel *l1 = gen_new_label(); 10179 TCGv_i64 fp0; 10180 10181 if (ft != 0) { 10182 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); 10183 } 10184 fp0 = tcg_temp_new_i64(); 10185 gen_load_fpr64(ctx, fp0, fs); 10186 gen_store_fpr64(ctx, fp0, fd); 10187 gen_set_label(l1); 10188 } 10189 break; 10190 case OPC_MOVN_D: 10191 check_insn_opc_removed(ctx, ISA_MIPS_R6); 10192 { 10193 TCGLabel *l1 = gen_new_label(); 10194 TCGv_i64 fp0; 10195 10196 if (ft != 0) { 10197 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); 10198 fp0 = tcg_temp_new_i64(); 10199 gen_load_fpr64(ctx, fp0, fs); 10200 gen_store_fpr64(ctx, fp0, fd); 10201 gen_set_label(l1); 10202 } 10203 } 10204 break; 10205 case OPC_RECIP_D: 10206 check_cp1_registers(ctx, fs | fd); 10207 { 10208 TCGv_i64 fp0 = tcg_temp_new_i64(); 10209 10210 gen_load_fpr64(ctx, fp0, fs); 10211 gen_helper_float_recip_d(fp0, tcg_env, fp0); 10212 gen_store_fpr64(ctx, fp0, fd); 10213 } 10214 break; 10215 case OPC_RSQRT_D: 10216 check_cp1_registers(ctx, fs | fd); 10217 { 10218 TCGv_i64 fp0 = tcg_temp_new_i64(); 10219 10220 gen_load_fpr64(ctx, fp0, fs); 10221 gen_helper_float_rsqrt_d(fp0, tcg_env, fp0); 10222 gen_store_fpr64(ctx, fp0, fd); 10223 } 10224 break; 10225 case OPC_MADDF_D: 10226 check_insn(ctx, ISA_MIPS_R6); 10227 { 10228 TCGv_i64 fp0 = tcg_temp_new_i64(); 10229 TCGv_i64 fp1 = tcg_temp_new_i64(); 10230 TCGv_i64 fp2 = tcg_temp_new_i64(); 10231 gen_load_fpr64(ctx, fp0, fs); 10232 gen_load_fpr64(ctx, fp1, ft); 10233 gen_load_fpr64(ctx, fp2, fd); 10234 gen_helper_float_maddf_d(fp2, tcg_env, fp0, fp1, fp2); 10235 gen_store_fpr64(ctx, fp2, fd); 10236 } 10237 break; 10238 case OPC_MSUBF_D: 10239 check_insn(ctx, ISA_MIPS_R6); 10240 { 10241 TCGv_i64 fp0 = tcg_temp_new_i64(); 10242 TCGv_i64 fp1 = tcg_temp_new_i64(); 10243 TCGv_i64 fp2 = tcg_temp_new_i64(); 10244 gen_load_fpr64(ctx, fp0, fs); 10245 gen_load_fpr64(ctx, fp1, ft); 10246 gen_load_fpr64(ctx, fp2, fd); 10247 gen_helper_float_msubf_d(fp2, tcg_env, fp0, fp1, fp2); 10248 gen_store_fpr64(ctx, fp2, fd); 10249 } 10250 break; 10251 case OPC_RINT_D: 10252 check_insn(ctx, ISA_MIPS_R6); 10253 { 10254 TCGv_i64 fp0 = tcg_temp_new_i64(); 10255 gen_load_fpr64(ctx, fp0, fs); 10256 gen_helper_float_rint_d(fp0, tcg_env, fp0); 10257 gen_store_fpr64(ctx, fp0, fd); 10258 } 10259 break; 10260 case OPC_CLASS_D: 10261 check_insn(ctx, ISA_MIPS_R6); 10262 { 10263 TCGv_i64 fp0 = tcg_temp_new_i64(); 10264 gen_load_fpr64(ctx, fp0, fs); 10265 gen_helper_float_class_d(fp0, tcg_env, fp0); 10266 gen_store_fpr64(ctx, fp0, fd); 10267 } 10268 break; 10269 case OPC_MIN_D: /* OPC_RECIP2_D */ 10270 if (ctx->insn_flags & ISA_MIPS_R6) { 10271 /* OPC_MIN_D */ 10272 TCGv_i64 fp0 = tcg_temp_new_i64(); 10273 TCGv_i64 fp1 = tcg_temp_new_i64(); 10274 gen_load_fpr64(ctx, fp0, fs); 10275 gen_load_fpr64(ctx, fp1, ft); 10276 gen_helper_float_min_d(fp1, tcg_env, fp0, fp1); 10277 gen_store_fpr64(ctx, fp1, fd); 10278 } else { 10279 /* OPC_RECIP2_D */ 10280 check_cp1_64bitmode(ctx); 10281 { 10282 TCGv_i64 fp0 = tcg_temp_new_i64(); 10283 TCGv_i64 fp1 = tcg_temp_new_i64(); 10284 10285 gen_load_fpr64(ctx, fp0, fs); 10286 gen_load_fpr64(ctx, fp1, ft); 10287 gen_helper_float_recip2_d(fp0, tcg_env, fp0, fp1); 10288 gen_store_fpr64(ctx, fp0, fd); 10289 } 10290 } 10291 break; 10292 case OPC_MINA_D: /* OPC_RECIP1_D */ 10293 if (ctx->insn_flags & ISA_MIPS_R6) { 10294 /* OPC_MINA_D */ 10295 TCGv_i64 fp0 = tcg_temp_new_i64(); 10296 TCGv_i64 fp1 = tcg_temp_new_i64(); 10297 gen_load_fpr64(ctx, fp0, fs); 10298 gen_load_fpr64(ctx, fp1, ft); 10299 gen_helper_float_mina_d(fp1, tcg_env, fp0, fp1); 10300 gen_store_fpr64(ctx, fp1, fd); 10301 } else { 10302 /* OPC_RECIP1_D */ 10303 check_cp1_64bitmode(ctx); 10304 { 10305 TCGv_i64 fp0 = tcg_temp_new_i64(); 10306 10307 gen_load_fpr64(ctx, fp0, fs); 10308 gen_helper_float_recip1_d(fp0, tcg_env, fp0); 10309 gen_store_fpr64(ctx, fp0, fd); 10310 } 10311 } 10312 break; 10313 case OPC_MAX_D: /* OPC_RSQRT1_D */ 10314 if (ctx->insn_flags & ISA_MIPS_R6) { 10315 /* OPC_MAX_D */ 10316 TCGv_i64 fp0 = tcg_temp_new_i64(); 10317 TCGv_i64 fp1 = tcg_temp_new_i64(); 10318 gen_load_fpr64(ctx, fp0, fs); 10319 gen_load_fpr64(ctx, fp1, ft); 10320 gen_helper_float_max_d(fp1, tcg_env, fp0, fp1); 10321 gen_store_fpr64(ctx, fp1, fd); 10322 } else { 10323 /* OPC_RSQRT1_D */ 10324 check_cp1_64bitmode(ctx); 10325 { 10326 TCGv_i64 fp0 = tcg_temp_new_i64(); 10327 10328 gen_load_fpr64(ctx, fp0, fs); 10329 gen_helper_float_rsqrt1_d(fp0, tcg_env, fp0); 10330 gen_store_fpr64(ctx, fp0, fd); 10331 } 10332 } 10333 break; 10334 case OPC_MAXA_D: /* OPC_RSQRT2_D */ 10335 if (ctx->insn_flags & ISA_MIPS_R6) { 10336 /* OPC_MAXA_D */ 10337 TCGv_i64 fp0 = tcg_temp_new_i64(); 10338 TCGv_i64 fp1 = tcg_temp_new_i64(); 10339 gen_load_fpr64(ctx, fp0, fs); 10340 gen_load_fpr64(ctx, fp1, ft); 10341 gen_helper_float_maxa_d(fp1, tcg_env, fp0, fp1); 10342 gen_store_fpr64(ctx, fp1, fd); 10343 } else { 10344 /* OPC_RSQRT2_D */ 10345 check_cp1_64bitmode(ctx); 10346 { 10347 TCGv_i64 fp0 = tcg_temp_new_i64(); 10348 TCGv_i64 fp1 = tcg_temp_new_i64(); 10349 10350 gen_load_fpr64(ctx, fp0, fs); 10351 gen_load_fpr64(ctx, fp1, ft); 10352 gen_helper_float_rsqrt2_d(fp0, tcg_env, fp0, fp1); 10353 gen_store_fpr64(ctx, fp0, fd); 10354 } 10355 } 10356 break; 10357 case OPC_CMP_F_D: 10358 case OPC_CMP_UN_D: 10359 case OPC_CMP_EQ_D: 10360 case OPC_CMP_UEQ_D: 10361 case OPC_CMP_OLT_D: 10362 case OPC_CMP_ULT_D: 10363 case OPC_CMP_OLE_D: 10364 case OPC_CMP_ULE_D: 10365 case OPC_CMP_SF_D: 10366 case OPC_CMP_NGLE_D: 10367 case OPC_CMP_SEQ_D: 10368 case OPC_CMP_NGL_D: 10369 case OPC_CMP_LT_D: 10370 case OPC_CMP_NGE_D: 10371 case OPC_CMP_LE_D: 10372 case OPC_CMP_NGT_D: 10373 check_insn_opc_removed(ctx, ISA_MIPS_R6); 10374 if (ctx->opcode & (1 << 6)) { 10375 gen_cmpabs_d(ctx, func - 48, ft, fs, cc); 10376 } else { 10377 gen_cmp_d(ctx, func - 48, ft, fs, cc); 10378 } 10379 break; 10380 case OPC_CVT_S_D: 10381 check_cp1_registers(ctx, fs); 10382 { 10383 TCGv_i32 fp32 = tcg_temp_new_i32(); 10384 TCGv_i64 fp64 = tcg_temp_new_i64(); 10385 10386 gen_load_fpr64(ctx, fp64, fs); 10387 gen_helper_float_cvts_d(fp32, tcg_env, fp64); 10388 gen_store_fpr32(ctx, fp32, fd); 10389 } 10390 break; 10391 case OPC_CVT_W_D: 10392 check_cp1_registers(ctx, fs); 10393 { 10394 TCGv_i32 fp32 = tcg_temp_new_i32(); 10395 TCGv_i64 fp64 = tcg_temp_new_i64(); 10396 10397 gen_load_fpr64(ctx, fp64, fs); 10398 if (ctx->nan2008) { 10399 gen_helper_float_cvt_2008_w_d(fp32, tcg_env, fp64); 10400 } else { 10401 gen_helper_float_cvt_w_d(fp32, tcg_env, fp64); 10402 } 10403 gen_store_fpr32(ctx, fp32, fd); 10404 } 10405 break; 10406 case OPC_CVT_L_D: 10407 check_cp1_64bitmode(ctx); 10408 { 10409 TCGv_i64 fp0 = tcg_temp_new_i64(); 10410 10411 gen_load_fpr64(ctx, fp0, fs); 10412 if (ctx->nan2008) { 10413 gen_helper_float_cvt_2008_l_d(fp0, tcg_env, fp0); 10414 } else { 10415 gen_helper_float_cvt_l_d(fp0, tcg_env, fp0); 10416 } 10417 gen_store_fpr64(ctx, fp0, fd); 10418 } 10419 break; 10420 case OPC_CVT_S_W: 10421 { 10422 TCGv_i32 fp0 = tcg_temp_new_i32(); 10423 10424 gen_load_fpr32(ctx, fp0, fs); 10425 gen_helper_float_cvts_w(fp0, tcg_env, fp0); 10426 gen_store_fpr32(ctx, fp0, fd); 10427 } 10428 break; 10429 case OPC_CVT_D_W: 10430 check_cp1_registers(ctx, fd); 10431 { 10432 TCGv_i32 fp32 = tcg_temp_new_i32(); 10433 TCGv_i64 fp64 = tcg_temp_new_i64(); 10434 10435 gen_load_fpr32(ctx, fp32, fs); 10436 gen_helper_float_cvtd_w(fp64, tcg_env, fp32); 10437 gen_store_fpr64(ctx, fp64, fd); 10438 } 10439 break; 10440 case OPC_CVT_S_L: 10441 check_cp1_64bitmode(ctx); 10442 { 10443 TCGv_i32 fp32 = tcg_temp_new_i32(); 10444 TCGv_i64 fp64 = tcg_temp_new_i64(); 10445 10446 gen_load_fpr64(ctx, fp64, fs); 10447 gen_helper_float_cvts_l(fp32, tcg_env, fp64); 10448 gen_store_fpr32(ctx, fp32, fd); 10449 } 10450 break; 10451 case OPC_CVT_D_L: 10452 check_cp1_64bitmode(ctx); 10453 { 10454 TCGv_i64 fp0 = tcg_temp_new_i64(); 10455 10456 gen_load_fpr64(ctx, fp0, fs); 10457 gen_helper_float_cvtd_l(fp0, tcg_env, fp0); 10458 gen_store_fpr64(ctx, fp0, fd); 10459 } 10460 break; 10461 case OPC_CVT_PS_PW: 10462 check_ps(ctx); 10463 { 10464 TCGv_i64 fp0 = tcg_temp_new_i64(); 10465 10466 gen_load_fpr64(ctx, fp0, fs); 10467 gen_helper_float_cvtps_pw(fp0, tcg_env, fp0); 10468 gen_store_fpr64(ctx, fp0, fd); 10469 } 10470 break; 10471 case OPC_ADD_PS: 10472 check_ps(ctx); 10473 { 10474 TCGv_i64 fp0 = tcg_temp_new_i64(); 10475 TCGv_i64 fp1 = tcg_temp_new_i64(); 10476 10477 gen_load_fpr64(ctx, fp0, fs); 10478 gen_load_fpr64(ctx, fp1, ft); 10479 gen_helper_float_add_ps(fp0, tcg_env, fp0, fp1); 10480 gen_store_fpr64(ctx, fp0, fd); 10481 } 10482 break; 10483 case OPC_SUB_PS: 10484 check_ps(ctx); 10485 { 10486 TCGv_i64 fp0 = tcg_temp_new_i64(); 10487 TCGv_i64 fp1 = tcg_temp_new_i64(); 10488 10489 gen_load_fpr64(ctx, fp0, fs); 10490 gen_load_fpr64(ctx, fp1, ft); 10491 gen_helper_float_sub_ps(fp0, tcg_env, fp0, fp1); 10492 gen_store_fpr64(ctx, fp0, fd); 10493 } 10494 break; 10495 case OPC_MUL_PS: 10496 check_ps(ctx); 10497 { 10498 TCGv_i64 fp0 = tcg_temp_new_i64(); 10499 TCGv_i64 fp1 = tcg_temp_new_i64(); 10500 10501 gen_load_fpr64(ctx, fp0, fs); 10502 gen_load_fpr64(ctx, fp1, ft); 10503 gen_helper_float_mul_ps(fp0, tcg_env, fp0, fp1); 10504 gen_store_fpr64(ctx, fp0, fd); 10505 } 10506 break; 10507 case OPC_ABS_PS: 10508 check_ps(ctx); 10509 { 10510 TCGv_i64 fp0 = tcg_temp_new_i64(); 10511 10512 gen_load_fpr64(ctx, fp0, fs); 10513 gen_helper_float_abs_ps(fp0, fp0); 10514 gen_store_fpr64(ctx, fp0, fd); 10515 } 10516 break; 10517 case OPC_MOV_PS: 10518 check_ps(ctx); 10519 { 10520 TCGv_i64 fp0 = tcg_temp_new_i64(); 10521 10522 gen_load_fpr64(ctx, fp0, fs); 10523 gen_store_fpr64(ctx, fp0, fd); 10524 } 10525 break; 10526 case OPC_NEG_PS: 10527 check_ps(ctx); 10528 { 10529 TCGv_i64 fp0 = tcg_temp_new_i64(); 10530 10531 gen_load_fpr64(ctx, fp0, fs); 10532 gen_helper_float_chs_ps(fp0, fp0); 10533 gen_store_fpr64(ctx, fp0, fd); 10534 } 10535 break; 10536 case OPC_MOVCF_PS: 10537 check_ps(ctx); 10538 gen_movcf_ps(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); 10539 break; 10540 case OPC_MOVZ_PS: 10541 check_ps(ctx); 10542 { 10543 TCGLabel *l1 = gen_new_label(); 10544 TCGv_i64 fp0; 10545 10546 if (ft != 0) { 10547 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); 10548 } 10549 fp0 = tcg_temp_new_i64(); 10550 gen_load_fpr64(ctx, fp0, fs); 10551 gen_store_fpr64(ctx, fp0, fd); 10552 gen_set_label(l1); 10553 } 10554 break; 10555 case OPC_MOVN_PS: 10556 check_ps(ctx); 10557 { 10558 TCGLabel *l1 = gen_new_label(); 10559 TCGv_i64 fp0; 10560 10561 if (ft != 0) { 10562 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); 10563 fp0 = tcg_temp_new_i64(); 10564 gen_load_fpr64(ctx, fp0, fs); 10565 gen_store_fpr64(ctx, fp0, fd); 10566 gen_set_label(l1); 10567 } 10568 } 10569 break; 10570 case OPC_ADDR_PS: 10571 check_ps(ctx); 10572 { 10573 TCGv_i64 fp0 = tcg_temp_new_i64(); 10574 TCGv_i64 fp1 = tcg_temp_new_i64(); 10575 10576 gen_load_fpr64(ctx, fp0, ft); 10577 gen_load_fpr64(ctx, fp1, fs); 10578 gen_helper_float_addr_ps(fp0, tcg_env, fp0, fp1); 10579 gen_store_fpr64(ctx, fp0, fd); 10580 } 10581 break; 10582 case OPC_MULR_PS: 10583 check_ps(ctx); 10584 { 10585 TCGv_i64 fp0 = tcg_temp_new_i64(); 10586 TCGv_i64 fp1 = tcg_temp_new_i64(); 10587 10588 gen_load_fpr64(ctx, fp0, ft); 10589 gen_load_fpr64(ctx, fp1, fs); 10590 gen_helper_float_mulr_ps(fp0, tcg_env, fp0, fp1); 10591 gen_store_fpr64(ctx, fp0, fd); 10592 } 10593 break; 10594 case OPC_RECIP2_PS: 10595 check_ps(ctx); 10596 { 10597 TCGv_i64 fp0 = tcg_temp_new_i64(); 10598 TCGv_i64 fp1 = tcg_temp_new_i64(); 10599 10600 gen_load_fpr64(ctx, fp0, fs); 10601 gen_load_fpr64(ctx, fp1, ft); 10602 gen_helper_float_recip2_ps(fp0, tcg_env, fp0, fp1); 10603 gen_store_fpr64(ctx, fp0, fd); 10604 } 10605 break; 10606 case OPC_RECIP1_PS: 10607 check_ps(ctx); 10608 { 10609 TCGv_i64 fp0 = tcg_temp_new_i64(); 10610 10611 gen_load_fpr64(ctx, fp0, fs); 10612 gen_helper_float_recip1_ps(fp0, tcg_env, fp0); 10613 gen_store_fpr64(ctx, fp0, fd); 10614 } 10615 break; 10616 case OPC_RSQRT1_PS: 10617 check_ps(ctx); 10618 { 10619 TCGv_i64 fp0 = tcg_temp_new_i64(); 10620 10621 gen_load_fpr64(ctx, fp0, fs); 10622 gen_helper_float_rsqrt1_ps(fp0, tcg_env, fp0); 10623 gen_store_fpr64(ctx, fp0, fd); 10624 } 10625 break; 10626 case OPC_RSQRT2_PS: 10627 check_ps(ctx); 10628 { 10629 TCGv_i64 fp0 = tcg_temp_new_i64(); 10630 TCGv_i64 fp1 = tcg_temp_new_i64(); 10631 10632 gen_load_fpr64(ctx, fp0, fs); 10633 gen_load_fpr64(ctx, fp1, ft); 10634 gen_helper_float_rsqrt2_ps(fp0, tcg_env, fp0, fp1); 10635 gen_store_fpr64(ctx, fp0, fd); 10636 } 10637 break; 10638 case OPC_CVT_S_PU: 10639 check_cp1_64bitmode(ctx); 10640 { 10641 TCGv_i32 fp0 = tcg_temp_new_i32(); 10642 10643 gen_load_fpr32h(ctx, fp0, fs); 10644 gen_helper_float_cvts_pu(fp0, tcg_env, fp0); 10645 gen_store_fpr32(ctx, fp0, fd); 10646 } 10647 break; 10648 case OPC_CVT_PW_PS: 10649 check_ps(ctx); 10650 { 10651 TCGv_i64 fp0 = tcg_temp_new_i64(); 10652 10653 gen_load_fpr64(ctx, fp0, fs); 10654 gen_helper_float_cvtpw_ps(fp0, tcg_env, fp0); 10655 gen_store_fpr64(ctx, fp0, fd); 10656 } 10657 break; 10658 case OPC_CVT_S_PL: 10659 check_cp1_64bitmode(ctx); 10660 { 10661 TCGv_i32 fp0 = tcg_temp_new_i32(); 10662 10663 gen_load_fpr32(ctx, fp0, fs); 10664 gen_helper_float_cvts_pl(fp0, tcg_env, fp0); 10665 gen_store_fpr32(ctx, fp0, fd); 10666 } 10667 break; 10668 case OPC_PLL_PS: 10669 check_ps(ctx); 10670 { 10671 TCGv_i32 fp0 = tcg_temp_new_i32(); 10672 TCGv_i32 fp1 = tcg_temp_new_i32(); 10673 10674 gen_load_fpr32(ctx, fp0, fs); 10675 gen_load_fpr32(ctx, fp1, ft); 10676 gen_store_fpr32h(ctx, fp0, fd); 10677 gen_store_fpr32(ctx, fp1, fd); 10678 } 10679 break; 10680 case OPC_PLU_PS: 10681 check_ps(ctx); 10682 { 10683 TCGv_i32 fp0 = tcg_temp_new_i32(); 10684 TCGv_i32 fp1 = tcg_temp_new_i32(); 10685 10686 gen_load_fpr32(ctx, fp0, fs); 10687 gen_load_fpr32h(ctx, fp1, ft); 10688 gen_store_fpr32(ctx, fp1, fd); 10689 gen_store_fpr32h(ctx, fp0, fd); 10690 } 10691 break; 10692 case OPC_PUL_PS: 10693 check_ps(ctx); 10694 { 10695 TCGv_i32 fp0 = tcg_temp_new_i32(); 10696 TCGv_i32 fp1 = tcg_temp_new_i32(); 10697 10698 gen_load_fpr32h(ctx, fp0, fs); 10699 gen_load_fpr32(ctx, fp1, ft); 10700 gen_store_fpr32(ctx, fp1, fd); 10701 gen_store_fpr32h(ctx, fp0, fd); 10702 } 10703 break; 10704 case OPC_PUU_PS: 10705 check_ps(ctx); 10706 { 10707 TCGv_i32 fp0 = tcg_temp_new_i32(); 10708 TCGv_i32 fp1 = tcg_temp_new_i32(); 10709 10710 gen_load_fpr32h(ctx, fp0, fs); 10711 gen_load_fpr32h(ctx, fp1, ft); 10712 gen_store_fpr32(ctx, fp1, fd); 10713 gen_store_fpr32h(ctx, fp0, fd); 10714 } 10715 break; 10716 case OPC_CMP_F_PS: 10717 case OPC_CMP_UN_PS: 10718 case OPC_CMP_EQ_PS: 10719 case OPC_CMP_UEQ_PS: 10720 case OPC_CMP_OLT_PS: 10721 case OPC_CMP_ULT_PS: 10722 case OPC_CMP_OLE_PS: 10723 case OPC_CMP_ULE_PS: 10724 case OPC_CMP_SF_PS: 10725 case OPC_CMP_NGLE_PS: 10726 case OPC_CMP_SEQ_PS: 10727 case OPC_CMP_NGL_PS: 10728 case OPC_CMP_LT_PS: 10729 case OPC_CMP_NGE_PS: 10730 case OPC_CMP_LE_PS: 10731 case OPC_CMP_NGT_PS: 10732 if (ctx->opcode & (1 << 6)) { 10733 gen_cmpabs_ps(ctx, func - 48, ft, fs, cc); 10734 } else { 10735 gen_cmp_ps(ctx, func - 48, ft, fs, cc); 10736 } 10737 break; 10738 default: 10739 MIPS_INVAL("farith"); 10740 gen_reserved_instruction(ctx); 10741 return; 10742 } 10743 } 10744 10745 /* Coprocessor 3 (FPU) */ 10746 static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, 10747 int fd, int fs, int base, int index) 10748 { 10749 TCGv t0 = tcg_temp_new(); 10750 10751 if (base == 0) { 10752 gen_load_gpr(t0, index); 10753 } else if (index == 0) { 10754 gen_load_gpr(t0, base); 10755 } else { 10756 gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]); 10757 } 10758 /* 10759 * Don't do NOP if destination is zero: we must perform the actual 10760 * memory access. 10761 */ 10762 switch (opc) { 10763 case OPC_LWXC1: 10764 check_cop1x(ctx); 10765 { 10766 TCGv_i32 fp0 = tcg_temp_new_i32(); 10767 10768 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL); 10769 tcg_gen_trunc_tl_i32(fp0, t0); 10770 gen_store_fpr32(ctx, fp0, fd); 10771 } 10772 break; 10773 case OPC_LDXC1: 10774 check_cop1x(ctx); 10775 check_cp1_registers(ctx, fd); 10776 { 10777 TCGv_i64 fp0 = tcg_temp_new_i64(); 10778 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); 10779 gen_store_fpr64(ctx, fp0, fd); 10780 } 10781 break; 10782 case OPC_LUXC1: 10783 check_cp1_64bitmode(ctx); 10784 tcg_gen_andi_tl(t0, t0, ~0x7); 10785 { 10786 TCGv_i64 fp0 = tcg_temp_new_i64(); 10787 10788 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); 10789 gen_store_fpr64(ctx, fp0, fd); 10790 } 10791 break; 10792 case OPC_SWXC1: 10793 check_cop1x(ctx); 10794 { 10795 TCGv_i32 fp0 = tcg_temp_new_i32(); 10796 gen_load_fpr32(ctx, fp0, fs); 10797 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL); 10798 } 10799 break; 10800 case OPC_SDXC1: 10801 check_cop1x(ctx); 10802 check_cp1_registers(ctx, fs); 10803 { 10804 TCGv_i64 fp0 = tcg_temp_new_i64(); 10805 gen_load_fpr64(ctx, fp0, fs); 10806 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); 10807 } 10808 break; 10809 case OPC_SUXC1: 10810 check_cp1_64bitmode(ctx); 10811 tcg_gen_andi_tl(t0, t0, ~0x7); 10812 { 10813 TCGv_i64 fp0 = tcg_temp_new_i64(); 10814 gen_load_fpr64(ctx, fp0, fs); 10815 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); 10816 } 10817 break; 10818 } 10819 } 10820 10821 static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, 10822 int fd, int fr, int fs, int ft) 10823 { 10824 switch (opc) { 10825 case OPC_ALNV_PS: 10826 check_ps(ctx); 10827 { 10828 TCGv t0 = tcg_temp_new(); 10829 TCGv_i32 fp = tcg_temp_new_i32(); 10830 TCGv_i32 fph = tcg_temp_new_i32(); 10831 TCGLabel *l1 = gen_new_label(); 10832 TCGLabel *l2 = gen_new_label(); 10833 10834 gen_load_gpr(t0, fr); 10835 tcg_gen_andi_tl(t0, t0, 0x7); 10836 10837 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1); 10838 gen_load_fpr32(ctx, fp, fs); 10839 gen_load_fpr32h(ctx, fph, fs); 10840 gen_store_fpr32(ctx, fp, fd); 10841 gen_store_fpr32h(ctx, fph, fd); 10842 tcg_gen_br(l2); 10843 gen_set_label(l1); 10844 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2); 10845 if (disas_is_bigendian(ctx)) { 10846 gen_load_fpr32(ctx, fp, fs); 10847 gen_load_fpr32h(ctx, fph, ft); 10848 gen_store_fpr32h(ctx, fp, fd); 10849 gen_store_fpr32(ctx, fph, fd); 10850 } else { 10851 gen_load_fpr32h(ctx, fph, fs); 10852 gen_load_fpr32(ctx, fp, ft); 10853 gen_store_fpr32(ctx, fph, fd); 10854 gen_store_fpr32h(ctx, fp, fd); 10855 } 10856 gen_set_label(l2); 10857 } 10858 break; 10859 case OPC_MADD_S: 10860 check_cop1x(ctx); 10861 { 10862 TCGv_i32 fp0 = tcg_temp_new_i32(); 10863 TCGv_i32 fp1 = tcg_temp_new_i32(); 10864 TCGv_i32 fp2 = tcg_temp_new_i32(); 10865 10866 gen_load_fpr32(ctx, fp0, fs); 10867 gen_load_fpr32(ctx, fp1, ft); 10868 gen_load_fpr32(ctx, fp2, fr); 10869 gen_helper_float_madd_s(fp2, tcg_env, fp0, fp1, fp2); 10870 gen_store_fpr32(ctx, fp2, fd); 10871 } 10872 break; 10873 case OPC_MADD_D: 10874 check_cop1x(ctx); 10875 check_cp1_registers(ctx, fd | fs | ft | fr); 10876 { 10877 TCGv_i64 fp0 = tcg_temp_new_i64(); 10878 TCGv_i64 fp1 = tcg_temp_new_i64(); 10879 TCGv_i64 fp2 = tcg_temp_new_i64(); 10880 10881 gen_load_fpr64(ctx, fp0, fs); 10882 gen_load_fpr64(ctx, fp1, ft); 10883 gen_load_fpr64(ctx, fp2, fr); 10884 gen_helper_float_madd_d(fp2, tcg_env, fp0, fp1, fp2); 10885 gen_store_fpr64(ctx, fp2, fd); 10886 } 10887 break; 10888 case OPC_MADD_PS: 10889 check_ps(ctx); 10890 { 10891 TCGv_i64 fp0 = tcg_temp_new_i64(); 10892 TCGv_i64 fp1 = tcg_temp_new_i64(); 10893 TCGv_i64 fp2 = tcg_temp_new_i64(); 10894 10895 gen_load_fpr64(ctx, fp0, fs); 10896 gen_load_fpr64(ctx, fp1, ft); 10897 gen_load_fpr64(ctx, fp2, fr); 10898 gen_helper_float_madd_ps(fp2, tcg_env, fp0, fp1, fp2); 10899 gen_store_fpr64(ctx, fp2, fd); 10900 } 10901 break; 10902 case OPC_MSUB_S: 10903 check_cop1x(ctx); 10904 { 10905 TCGv_i32 fp0 = tcg_temp_new_i32(); 10906 TCGv_i32 fp1 = tcg_temp_new_i32(); 10907 TCGv_i32 fp2 = tcg_temp_new_i32(); 10908 10909 gen_load_fpr32(ctx, fp0, fs); 10910 gen_load_fpr32(ctx, fp1, ft); 10911 gen_load_fpr32(ctx, fp2, fr); 10912 gen_helper_float_msub_s(fp2, tcg_env, fp0, fp1, fp2); 10913 gen_store_fpr32(ctx, fp2, fd); 10914 } 10915 break; 10916 case OPC_MSUB_D: 10917 check_cop1x(ctx); 10918 check_cp1_registers(ctx, fd | fs | ft | fr); 10919 { 10920 TCGv_i64 fp0 = tcg_temp_new_i64(); 10921 TCGv_i64 fp1 = tcg_temp_new_i64(); 10922 TCGv_i64 fp2 = tcg_temp_new_i64(); 10923 10924 gen_load_fpr64(ctx, fp0, fs); 10925 gen_load_fpr64(ctx, fp1, ft); 10926 gen_load_fpr64(ctx, fp2, fr); 10927 gen_helper_float_msub_d(fp2, tcg_env, fp0, fp1, fp2); 10928 gen_store_fpr64(ctx, fp2, fd); 10929 } 10930 break; 10931 case OPC_MSUB_PS: 10932 check_ps(ctx); 10933 { 10934 TCGv_i64 fp0 = tcg_temp_new_i64(); 10935 TCGv_i64 fp1 = tcg_temp_new_i64(); 10936 TCGv_i64 fp2 = tcg_temp_new_i64(); 10937 10938 gen_load_fpr64(ctx, fp0, fs); 10939 gen_load_fpr64(ctx, fp1, ft); 10940 gen_load_fpr64(ctx, fp2, fr); 10941 gen_helper_float_msub_ps(fp2, tcg_env, fp0, fp1, fp2); 10942 gen_store_fpr64(ctx, fp2, fd); 10943 } 10944 break; 10945 case OPC_NMADD_S: 10946 check_cop1x(ctx); 10947 { 10948 TCGv_i32 fp0 = tcg_temp_new_i32(); 10949 TCGv_i32 fp1 = tcg_temp_new_i32(); 10950 TCGv_i32 fp2 = tcg_temp_new_i32(); 10951 10952 gen_load_fpr32(ctx, fp0, fs); 10953 gen_load_fpr32(ctx, fp1, ft); 10954 gen_load_fpr32(ctx, fp2, fr); 10955 gen_helper_float_nmadd_s(fp2, tcg_env, fp0, fp1, fp2); 10956 gen_store_fpr32(ctx, fp2, fd); 10957 } 10958 break; 10959 case OPC_NMADD_D: 10960 check_cop1x(ctx); 10961 check_cp1_registers(ctx, fd | fs | ft | fr); 10962 { 10963 TCGv_i64 fp0 = tcg_temp_new_i64(); 10964 TCGv_i64 fp1 = tcg_temp_new_i64(); 10965 TCGv_i64 fp2 = tcg_temp_new_i64(); 10966 10967 gen_load_fpr64(ctx, fp0, fs); 10968 gen_load_fpr64(ctx, fp1, ft); 10969 gen_load_fpr64(ctx, fp2, fr); 10970 gen_helper_float_nmadd_d(fp2, tcg_env, fp0, fp1, fp2); 10971 gen_store_fpr64(ctx, fp2, fd); 10972 } 10973 break; 10974 case OPC_NMADD_PS: 10975 check_ps(ctx); 10976 { 10977 TCGv_i64 fp0 = tcg_temp_new_i64(); 10978 TCGv_i64 fp1 = tcg_temp_new_i64(); 10979 TCGv_i64 fp2 = tcg_temp_new_i64(); 10980 10981 gen_load_fpr64(ctx, fp0, fs); 10982 gen_load_fpr64(ctx, fp1, ft); 10983 gen_load_fpr64(ctx, fp2, fr); 10984 gen_helper_float_nmadd_ps(fp2, tcg_env, fp0, fp1, fp2); 10985 gen_store_fpr64(ctx, fp2, fd); 10986 } 10987 break; 10988 case OPC_NMSUB_S: 10989 check_cop1x(ctx); 10990 { 10991 TCGv_i32 fp0 = tcg_temp_new_i32(); 10992 TCGv_i32 fp1 = tcg_temp_new_i32(); 10993 TCGv_i32 fp2 = tcg_temp_new_i32(); 10994 10995 gen_load_fpr32(ctx, fp0, fs); 10996 gen_load_fpr32(ctx, fp1, ft); 10997 gen_load_fpr32(ctx, fp2, fr); 10998 gen_helper_float_nmsub_s(fp2, tcg_env, fp0, fp1, fp2); 10999 gen_store_fpr32(ctx, fp2, fd); 11000 } 11001 break; 11002 case OPC_NMSUB_D: 11003 check_cop1x(ctx); 11004 check_cp1_registers(ctx, fd | fs | ft | fr); 11005 { 11006 TCGv_i64 fp0 = tcg_temp_new_i64(); 11007 TCGv_i64 fp1 = tcg_temp_new_i64(); 11008 TCGv_i64 fp2 = tcg_temp_new_i64(); 11009 11010 gen_load_fpr64(ctx, fp0, fs); 11011 gen_load_fpr64(ctx, fp1, ft); 11012 gen_load_fpr64(ctx, fp2, fr); 11013 gen_helper_float_nmsub_d(fp2, tcg_env, fp0, fp1, fp2); 11014 gen_store_fpr64(ctx, fp2, fd); 11015 } 11016 break; 11017 case OPC_NMSUB_PS: 11018 check_ps(ctx); 11019 { 11020 TCGv_i64 fp0 = tcg_temp_new_i64(); 11021 TCGv_i64 fp1 = tcg_temp_new_i64(); 11022 TCGv_i64 fp2 = tcg_temp_new_i64(); 11023 11024 gen_load_fpr64(ctx, fp0, fs); 11025 gen_load_fpr64(ctx, fp1, ft); 11026 gen_load_fpr64(ctx, fp2, fr); 11027 gen_helper_float_nmsub_ps(fp2, tcg_env, fp0, fp1, fp2); 11028 gen_store_fpr64(ctx, fp2, fd); 11029 } 11030 break; 11031 default: 11032 MIPS_INVAL("flt3_arith"); 11033 gen_reserved_instruction(ctx); 11034 return; 11035 } 11036 } 11037 11038 void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel) 11039 { 11040 TCGv t0; 11041 11042 #if !defined(CONFIG_USER_ONLY) 11043 /* 11044 * The Linux kernel will emulate rdhwr if it's not supported natively. 11045 * Therefore only check the ISA in system mode. 11046 */ 11047 check_insn(ctx, ISA_MIPS_R2); 11048 #endif 11049 t0 = tcg_temp_new(); 11050 11051 switch (rd) { 11052 case 0: 11053 gen_helper_rdhwr_cpunum(t0, tcg_env); 11054 gen_store_gpr(t0, rt); 11055 break; 11056 case 1: 11057 gen_helper_rdhwr_synci_step(t0, tcg_env); 11058 gen_store_gpr(t0, rt); 11059 break; 11060 case 2: 11061 translator_io_start(&ctx->base); 11062 gen_helper_rdhwr_cc(t0, tcg_env); 11063 gen_store_gpr(t0, rt); 11064 /* 11065 * Break the TB to be able to take timer interrupts immediately 11066 * after reading count. DISAS_STOP isn't sufficient, we need to ensure 11067 * we break completely out of translated code. 11068 */ 11069 gen_save_pc(ctx->base.pc_next + 4); 11070 ctx->base.is_jmp = DISAS_EXIT; 11071 break; 11072 case 3: 11073 gen_helper_rdhwr_ccres(t0, tcg_env); 11074 gen_store_gpr(t0, rt); 11075 break; 11076 case 4: 11077 check_insn(ctx, ISA_MIPS_R6); 11078 if (sel != 0) { 11079 /* 11080 * Performance counter registers are not implemented other than 11081 * control register 0. 11082 */ 11083 generate_exception(ctx, EXCP_RI); 11084 } 11085 gen_helper_rdhwr_performance(t0, tcg_env); 11086 gen_store_gpr(t0, rt); 11087 break; 11088 case 5: 11089 check_insn(ctx, ISA_MIPS_R6); 11090 gen_helper_rdhwr_xnp(t0, tcg_env); 11091 gen_store_gpr(t0, rt); 11092 break; 11093 case 29: 11094 #if defined(CONFIG_USER_ONLY) 11095 tcg_gen_ld_tl(t0, tcg_env, 11096 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 11097 gen_store_gpr(t0, rt); 11098 break; 11099 #else 11100 if ((ctx->hflags & MIPS_HFLAG_CP0) || 11101 (ctx->hflags & MIPS_HFLAG_HWRENA_ULR)) { 11102 tcg_gen_ld_tl(t0, tcg_env, 11103 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 11104 gen_store_gpr(t0, rt); 11105 } else { 11106 gen_reserved_instruction(ctx); 11107 } 11108 break; 11109 #endif 11110 default: /* Invalid */ 11111 MIPS_INVAL("rdhwr"); 11112 gen_reserved_instruction(ctx); 11113 break; 11114 } 11115 } 11116 11117 static inline void clear_branch_hflags(DisasContext *ctx) 11118 { 11119 ctx->hflags &= ~MIPS_HFLAG_BMASK; 11120 if (ctx->base.is_jmp == DISAS_NEXT) { 11121 save_cpu_state(ctx, 0); 11122 } else { 11123 /* 11124 * It is not safe to save ctx->hflags as hflags may be changed 11125 * in execution time by the instruction in delay / forbidden slot. 11126 */ 11127 tcg_gen_andi_i32(hflags, hflags, ~MIPS_HFLAG_BMASK); 11128 } 11129 } 11130 11131 static void gen_branch(DisasContext *ctx, int insn_bytes) 11132 { 11133 if (ctx->hflags & MIPS_HFLAG_BMASK) { 11134 int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK; 11135 /* Branches completion */ 11136 clear_branch_hflags(ctx); 11137 ctx->base.is_jmp = DISAS_NORETURN; 11138 switch (proc_hflags & MIPS_HFLAG_BMASK_BASE) { 11139 case MIPS_HFLAG_FBNSLOT: 11140 gen_goto_tb(ctx, 0, ctx->base.pc_next + insn_bytes); 11141 break; 11142 case MIPS_HFLAG_B: 11143 /* unconditional branch */ 11144 if (proc_hflags & MIPS_HFLAG_BX) { 11145 tcg_gen_xori_i32(hflags, hflags, MIPS_HFLAG_M16); 11146 } 11147 gen_goto_tb(ctx, 0, ctx->btarget); 11148 break; 11149 case MIPS_HFLAG_BL: 11150 /* blikely taken case */ 11151 gen_goto_tb(ctx, 0, ctx->btarget); 11152 break; 11153 case MIPS_HFLAG_BC: 11154 /* Conditional branch */ 11155 { 11156 TCGLabel *l1 = gen_new_label(); 11157 11158 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); 11159 gen_goto_tb(ctx, 1, ctx->base.pc_next + insn_bytes); 11160 gen_set_label(l1); 11161 gen_goto_tb(ctx, 0, ctx->btarget); 11162 } 11163 break; 11164 case MIPS_HFLAG_BR: 11165 /* unconditional branch to register */ 11166 if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) { 11167 TCGv t0 = tcg_temp_new(); 11168 TCGv_i32 t1 = tcg_temp_new_i32(); 11169 11170 tcg_gen_andi_tl(t0, btarget, 0x1); 11171 tcg_gen_trunc_tl_i32(t1, t0); 11172 tcg_gen_andi_i32(hflags, hflags, ~(uint32_t)MIPS_HFLAG_M16); 11173 tcg_gen_shli_i32(t1, t1, MIPS_HFLAG_M16_SHIFT); 11174 tcg_gen_or_i32(hflags, hflags, t1); 11175 11176 tcg_gen_andi_tl(cpu_PC, btarget, ~(target_ulong)0x1); 11177 } else { 11178 tcg_gen_mov_tl(cpu_PC, btarget); 11179 } 11180 tcg_gen_lookup_and_goto_ptr(); 11181 break; 11182 default: 11183 LOG_DISAS("unknown branch 0x%x\n", proc_hflags); 11184 gen_reserved_instruction(ctx); 11185 } 11186 } 11187 } 11188 11189 /* Compact Branches */ 11190 static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, 11191 int rs, int rt, int32_t offset) 11192 { 11193 int bcond_compute = 0; 11194 TCGv t0 = tcg_temp_new(); 11195 TCGv t1 = tcg_temp_new(); 11196 int m16_lowbit = (ctx->hflags & MIPS_HFLAG_M16) != 0; 11197 11198 if (ctx->hflags & MIPS_HFLAG_BMASK) { 11199 #ifdef MIPS_DEBUG_DISAS 11200 LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016" 11201 VADDR_PRIx "\n", ctx->base.pc_next); 11202 #endif 11203 gen_reserved_instruction(ctx); 11204 return; 11205 } 11206 11207 /* Load needed operands and calculate btarget */ 11208 switch (opc) { 11209 /* compact branch */ 11210 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */ 11211 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */ 11212 gen_load_gpr(t0, rs); 11213 gen_load_gpr(t1, rt); 11214 bcond_compute = 1; 11215 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 11216 if (rs <= rt && rs == 0) { 11217 /* OPC_BEQZALC, OPC_BNEZALC */ 11218 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); 11219 } 11220 break; 11221 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */ 11222 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */ 11223 gen_load_gpr(t0, rs); 11224 gen_load_gpr(t1, rt); 11225 bcond_compute = 1; 11226 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 11227 break; 11228 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */ 11229 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */ 11230 if (rs == 0 || rs == rt) { 11231 /* OPC_BLEZALC, OPC_BGEZALC */ 11232 /* OPC_BGTZALC, OPC_BLTZALC */ 11233 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); 11234 } 11235 gen_load_gpr(t0, rs); 11236 gen_load_gpr(t1, rt); 11237 bcond_compute = 1; 11238 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 11239 break; 11240 case OPC_BC: 11241 case OPC_BALC: 11242 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 11243 break; 11244 case OPC_BEQZC: 11245 case OPC_BNEZC: 11246 if (rs != 0) { 11247 /* OPC_BEQZC, OPC_BNEZC */ 11248 gen_load_gpr(t0, rs); 11249 bcond_compute = 1; 11250 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 11251 } else { 11252 /* OPC_JIC, OPC_JIALC */ 11253 TCGv tbase = tcg_temp_new(); 11254 11255 gen_load_gpr(tbase, rt); 11256 gen_op_addr_addi(ctx, btarget, tbase, offset); 11257 } 11258 break; 11259 default: 11260 MIPS_INVAL("Compact branch/jump"); 11261 gen_reserved_instruction(ctx); 11262 return; 11263 } 11264 11265 if (bcond_compute == 0) { 11266 /* Unconditional compact branch */ 11267 switch (opc) { 11268 case OPC_JIALC: 11269 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); 11270 /* Fallthrough */ 11271 case OPC_JIC: 11272 ctx->hflags |= MIPS_HFLAG_BR; 11273 break; 11274 case OPC_BALC: 11275 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); 11276 /* Fallthrough */ 11277 case OPC_BC: 11278 ctx->hflags |= MIPS_HFLAG_B; 11279 break; 11280 default: 11281 MIPS_INVAL("Compact branch/jump"); 11282 gen_reserved_instruction(ctx); 11283 return; 11284 } 11285 11286 /* Generating branch here as compact branches don't have delay slot */ 11287 gen_branch(ctx, 4); 11288 } else { 11289 /* Conditional compact branch */ 11290 TCGLabel *fs = gen_new_label(); 11291 save_cpu_state(ctx, 0); 11292 11293 switch (opc) { 11294 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */ 11295 if (rs == 0 && rt != 0) { 11296 /* OPC_BLEZALC */ 11297 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs); 11298 } else if (rs != 0 && rt != 0 && rs == rt) { 11299 /* OPC_BGEZALC */ 11300 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs); 11301 } else { 11302 /* OPC_BGEUC */ 11303 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU), t0, t1, fs); 11304 } 11305 break; 11306 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */ 11307 if (rs == 0 && rt != 0) { 11308 /* OPC_BGTZALC */ 11309 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs); 11310 } else if (rs != 0 && rt != 0 && rs == rt) { 11311 /* OPC_BLTZALC */ 11312 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs); 11313 } else { 11314 /* OPC_BLTUC */ 11315 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU), t0, t1, fs); 11316 } 11317 break; 11318 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */ 11319 if (rs == 0 && rt != 0) { 11320 /* OPC_BLEZC */ 11321 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs); 11322 } else if (rs != 0 && rt != 0 && rs == rt) { 11323 /* OPC_BGEZC */ 11324 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs); 11325 } else { 11326 /* OPC_BGEC */ 11327 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE), t0, t1, fs); 11328 } 11329 break; 11330 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */ 11331 if (rs == 0 && rt != 0) { 11332 /* OPC_BGTZC */ 11333 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs); 11334 } else if (rs != 0 && rt != 0 && rs == rt) { 11335 /* OPC_BLTZC */ 11336 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs); 11337 } else { 11338 /* OPC_BLTC */ 11339 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT), t0, t1, fs); 11340 } 11341 break; 11342 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */ 11343 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */ 11344 if (rs >= rt) { 11345 /* OPC_BOVC, OPC_BNVC */ 11346 TCGv t2 = tcg_temp_new(); 11347 TCGv t3 = tcg_temp_new(); 11348 TCGv t4 = tcg_temp_new(); 11349 TCGv input_overflow = tcg_temp_new(); 11350 11351 gen_load_gpr(t0, rs); 11352 gen_load_gpr(t1, rt); 11353 tcg_gen_ext32s_tl(t2, t0); 11354 tcg_gen_setcond_tl(TCG_COND_NE, input_overflow, t2, t0); 11355 tcg_gen_ext32s_tl(t3, t1); 11356 tcg_gen_setcond_tl(TCG_COND_NE, t4, t3, t1); 11357 tcg_gen_or_tl(input_overflow, input_overflow, t4); 11358 11359 tcg_gen_add_tl(t4, t2, t3); 11360 tcg_gen_ext32s_tl(t4, t4); 11361 tcg_gen_xor_tl(t2, t2, t3); 11362 tcg_gen_xor_tl(t3, t4, t3); 11363 tcg_gen_andc_tl(t2, t3, t2); 11364 tcg_gen_setcondi_tl(TCG_COND_LT, t4, t2, 0); 11365 tcg_gen_or_tl(t4, t4, input_overflow); 11366 if (opc == OPC_BOVC) { 11367 /* OPC_BOVC */ 11368 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t4, 0, fs); 11369 } else { 11370 /* OPC_BNVC */ 11371 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t4, 0, fs); 11372 } 11373 } else if (rs < rt && rs == 0) { 11374 /* OPC_BEQZALC, OPC_BNEZALC */ 11375 if (opc == OPC_BEQZALC) { 11376 /* OPC_BEQZALC */ 11377 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t1, 0, fs); 11378 } else { 11379 /* OPC_BNEZALC */ 11380 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t1, 0, fs); 11381 } 11382 } else { 11383 /* OPC_BEQC, OPC_BNEC */ 11384 if (opc == OPC_BEQC) { 11385 /* OPC_BEQC */ 11386 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ), t0, t1, fs); 11387 } else { 11388 /* OPC_BNEC */ 11389 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE), t0, t1, fs); 11390 } 11391 } 11392 break; 11393 case OPC_BEQZC: 11394 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t0, 0, fs); 11395 break; 11396 case OPC_BNEZC: 11397 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t0, 0, fs); 11398 break; 11399 default: 11400 MIPS_INVAL("Compact conditional branch/jump"); 11401 gen_reserved_instruction(ctx); 11402 return; 11403 } 11404 11405 /* Generating branch here as compact branches don't have delay slot */ 11406 gen_goto_tb(ctx, 1, ctx->btarget); 11407 gen_set_label(fs); 11408 11409 ctx->hflags |= MIPS_HFLAG_FBNSLOT; 11410 } 11411 } 11412 11413 void gen_addiupc(DisasContext *ctx, int rx, int imm, 11414 int is_64_bit, int extended) 11415 { 11416 target_ulong npc; 11417 11418 if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) { 11419 gen_reserved_instruction(ctx); 11420 return; 11421 } 11422 11423 npc = pc_relative_pc(ctx) + imm; 11424 if (!is_64_bit) { 11425 npc = (int32_t)npc; 11426 } 11427 tcg_gen_movi_tl(cpu_gpr[rx], npc); 11428 } 11429 11430 static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base, 11431 int16_t offset) 11432 { 11433 TCGv_i32 t0 = tcg_constant_i32(op); 11434 TCGv t1 = tcg_temp_new(); 11435 gen_base_offset_addr(ctx, t1, base, offset); 11436 gen_helper_cache(tcg_env, t1, t0); 11437 } 11438 11439 static inline bool is_uhi(DisasContext *ctx, int sdbbp_code) 11440 { 11441 #ifdef CONFIG_USER_ONLY 11442 return false; 11443 #else 11444 bool is_user = (ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM; 11445 return semihosting_enabled(is_user) && sdbbp_code == 1; 11446 #endif 11447 } 11448 11449 void gen_ldxs(DisasContext *ctx, int base, int index, int rd) 11450 { 11451 TCGv t0 = tcg_temp_new(); 11452 TCGv t1 = tcg_temp_new(); 11453 11454 gen_load_gpr(t0, base); 11455 11456 if (index != 0) { 11457 gen_load_gpr(t1, index); 11458 tcg_gen_shli_tl(t1, t1, 2); 11459 gen_op_addr_add(ctx, t0, t1, t0); 11460 } 11461 11462 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL); 11463 gen_store_gpr(t1, rd); 11464 } 11465 11466 static void gen_sync(int stype) 11467 { 11468 TCGBar tcg_mo = TCG_BAR_SC; 11469 11470 switch (stype) { 11471 case 0x4: /* SYNC_WMB */ 11472 tcg_mo |= TCG_MO_ST_ST; 11473 break; 11474 case 0x10: /* SYNC_MB */ 11475 tcg_mo |= TCG_MO_ALL; 11476 break; 11477 case 0x11: /* SYNC_ACQUIRE */ 11478 tcg_mo |= TCG_MO_LD_LD | TCG_MO_LD_ST; 11479 break; 11480 case 0x12: /* SYNC_RELEASE */ 11481 tcg_mo |= TCG_MO_ST_ST | TCG_MO_LD_ST; 11482 break; 11483 case 0x13: /* SYNC_RMB */ 11484 tcg_mo |= TCG_MO_LD_LD; 11485 break; 11486 default: 11487 tcg_mo |= TCG_MO_ALL; 11488 break; 11489 } 11490 11491 tcg_gen_mb(tcg_mo); 11492 } 11493 11494 /* ISA extensions (ASEs) */ 11495 11496 /* MIPS16 extension to MIPS32 */ 11497 #include "mips16e_translate.c.inc" 11498 11499 /* microMIPS extension to MIPS32/MIPS64 */ 11500 11501 /* 11502 * Values for microMIPS fmt field. Variable-width, depending on which 11503 * formats the instruction supports. 11504 */ 11505 enum { 11506 FMT_SD_S = 0, 11507 FMT_SD_D = 1, 11508 11509 FMT_SDPS_S = 0, 11510 FMT_SDPS_D = 1, 11511 FMT_SDPS_PS = 2, 11512 11513 FMT_SWL_S = 0, 11514 FMT_SWL_W = 1, 11515 FMT_SWL_L = 2, 11516 11517 FMT_DWL_D = 0, 11518 FMT_DWL_W = 1, 11519 FMT_DWL_L = 2 11520 }; 11521 11522 #include "micromips_translate.c.inc" 11523 11524 #include "nanomips_translate.c.inc" 11525 11526 /* MIPSDSP functions. */ 11527 11528 /* Indexed load is not for DSP only */ 11529 static void gen_mips_lx(DisasContext *ctx, uint32_t opc, 11530 int rd, int base, int offset) 11531 { 11532 TCGv t0; 11533 11534 if (!(ctx->insn_flags & INSN_OCTEON)) { 11535 check_dsp(ctx); 11536 } 11537 t0 = tcg_temp_new(); 11538 11539 if (base == 0) { 11540 gen_load_gpr(t0, offset); 11541 } else if (offset == 0) { 11542 gen_load_gpr(t0, base); 11543 } else { 11544 gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]); 11545 } 11546 11547 switch (opc) { 11548 case OPC_LBUX: 11549 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB); 11550 gen_store_gpr(t0, rd); 11551 break; 11552 case OPC_LHX: 11553 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW); 11554 gen_store_gpr(t0, rd); 11555 break; 11556 case OPC_LWX: 11557 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL); 11558 gen_store_gpr(t0, rd); 11559 break; 11560 #if defined(TARGET_MIPS64) 11561 case OPC_LDX: 11562 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); 11563 gen_store_gpr(t0, rd); 11564 break; 11565 #endif 11566 } 11567 } 11568 11569 static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2, 11570 int ret, int v1, int v2) 11571 { 11572 TCGv v1_t; 11573 TCGv v2_t; 11574 11575 if (ret == 0) { 11576 /* Treat as NOP. */ 11577 return; 11578 } 11579 11580 v1_t = tcg_temp_new(); 11581 v2_t = tcg_temp_new(); 11582 11583 gen_load_gpr(v1_t, v1); 11584 gen_load_gpr(v2_t, v2); 11585 11586 switch (op1) { 11587 case OPC_ADDUH_QB_DSP: 11588 check_dsp_r2(ctx); 11589 switch (op2) { 11590 case OPC_ADDUH_QB: 11591 gen_helper_adduh_qb(cpu_gpr[ret], v1_t, v2_t); 11592 break; 11593 case OPC_ADDUH_R_QB: 11594 gen_helper_adduh_r_qb(cpu_gpr[ret], v1_t, v2_t); 11595 break; 11596 case OPC_ADDQH_PH: 11597 gen_helper_addqh_ph(cpu_gpr[ret], v1_t, v2_t); 11598 break; 11599 case OPC_ADDQH_R_PH: 11600 gen_helper_addqh_r_ph(cpu_gpr[ret], v1_t, v2_t); 11601 break; 11602 case OPC_ADDQH_W: 11603 gen_helper_addqh_w(cpu_gpr[ret], v1_t, v2_t); 11604 break; 11605 case OPC_ADDQH_R_W: 11606 gen_helper_addqh_r_w(cpu_gpr[ret], v1_t, v2_t); 11607 break; 11608 case OPC_SUBUH_QB: 11609 gen_helper_subuh_qb(cpu_gpr[ret], v1_t, v2_t); 11610 break; 11611 case OPC_SUBUH_R_QB: 11612 gen_helper_subuh_r_qb(cpu_gpr[ret], v1_t, v2_t); 11613 break; 11614 case OPC_SUBQH_PH: 11615 gen_helper_subqh_ph(cpu_gpr[ret], v1_t, v2_t); 11616 break; 11617 case OPC_SUBQH_R_PH: 11618 gen_helper_subqh_r_ph(cpu_gpr[ret], v1_t, v2_t); 11619 break; 11620 case OPC_SUBQH_W: 11621 gen_helper_subqh_w(cpu_gpr[ret], v1_t, v2_t); 11622 break; 11623 case OPC_SUBQH_R_W: 11624 gen_helper_subqh_r_w(cpu_gpr[ret], v1_t, v2_t); 11625 break; 11626 } 11627 break; 11628 case OPC_ABSQ_S_PH_DSP: 11629 switch (op2) { 11630 case OPC_ABSQ_S_QB: 11631 check_dsp_r2(ctx); 11632 gen_helper_absq_s_qb(cpu_gpr[ret], v2_t, tcg_env); 11633 break; 11634 case OPC_ABSQ_S_PH: 11635 check_dsp(ctx); 11636 gen_helper_absq_s_ph(cpu_gpr[ret], v2_t, tcg_env); 11637 break; 11638 case OPC_ABSQ_S_W: 11639 check_dsp(ctx); 11640 gen_helper_absq_s_w(cpu_gpr[ret], v2_t, tcg_env); 11641 break; 11642 case OPC_PRECEQ_W_PHL: 11643 check_dsp(ctx); 11644 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFF0000); 11645 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); 11646 break; 11647 case OPC_PRECEQ_W_PHR: 11648 check_dsp(ctx); 11649 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0x0000FFFF); 11650 tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 16); 11651 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); 11652 break; 11653 case OPC_PRECEQU_PH_QBL: 11654 check_dsp(ctx); 11655 gen_helper_precequ_ph_qbl(cpu_gpr[ret], v2_t); 11656 break; 11657 case OPC_PRECEQU_PH_QBR: 11658 check_dsp(ctx); 11659 gen_helper_precequ_ph_qbr(cpu_gpr[ret], v2_t); 11660 break; 11661 case OPC_PRECEQU_PH_QBLA: 11662 check_dsp(ctx); 11663 gen_helper_precequ_ph_qbla(cpu_gpr[ret], v2_t); 11664 break; 11665 case OPC_PRECEQU_PH_QBRA: 11666 check_dsp(ctx); 11667 gen_helper_precequ_ph_qbra(cpu_gpr[ret], v2_t); 11668 break; 11669 case OPC_PRECEU_PH_QBL: 11670 check_dsp(ctx); 11671 gen_helper_preceu_ph_qbl(cpu_gpr[ret], v2_t); 11672 break; 11673 case OPC_PRECEU_PH_QBR: 11674 check_dsp(ctx); 11675 gen_helper_preceu_ph_qbr(cpu_gpr[ret], v2_t); 11676 break; 11677 case OPC_PRECEU_PH_QBLA: 11678 check_dsp(ctx); 11679 gen_helper_preceu_ph_qbla(cpu_gpr[ret], v2_t); 11680 break; 11681 case OPC_PRECEU_PH_QBRA: 11682 check_dsp(ctx); 11683 gen_helper_preceu_ph_qbra(cpu_gpr[ret], v2_t); 11684 break; 11685 } 11686 break; 11687 case OPC_ADDU_QB_DSP: 11688 switch (op2) { 11689 case OPC_ADDQ_PH: 11690 check_dsp(ctx); 11691 gen_helper_addq_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11692 break; 11693 case OPC_ADDQ_S_PH: 11694 check_dsp(ctx); 11695 gen_helper_addq_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11696 break; 11697 case OPC_ADDQ_S_W: 11698 check_dsp(ctx); 11699 gen_helper_addq_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11700 break; 11701 case OPC_ADDU_QB: 11702 check_dsp(ctx); 11703 gen_helper_addu_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11704 break; 11705 case OPC_ADDU_S_QB: 11706 check_dsp(ctx); 11707 gen_helper_addu_s_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11708 break; 11709 case OPC_ADDU_PH: 11710 check_dsp_r2(ctx); 11711 gen_helper_addu_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11712 break; 11713 case OPC_ADDU_S_PH: 11714 check_dsp_r2(ctx); 11715 gen_helper_addu_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11716 break; 11717 case OPC_SUBQ_PH: 11718 check_dsp(ctx); 11719 gen_helper_subq_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11720 break; 11721 case OPC_SUBQ_S_PH: 11722 check_dsp(ctx); 11723 gen_helper_subq_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11724 break; 11725 case OPC_SUBQ_S_W: 11726 check_dsp(ctx); 11727 gen_helper_subq_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11728 break; 11729 case OPC_SUBU_QB: 11730 check_dsp(ctx); 11731 gen_helper_subu_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11732 break; 11733 case OPC_SUBU_S_QB: 11734 check_dsp(ctx); 11735 gen_helper_subu_s_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11736 break; 11737 case OPC_SUBU_PH: 11738 check_dsp_r2(ctx); 11739 gen_helper_subu_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11740 break; 11741 case OPC_SUBU_S_PH: 11742 check_dsp_r2(ctx); 11743 gen_helper_subu_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11744 break; 11745 case OPC_ADDSC: 11746 check_dsp(ctx); 11747 gen_helper_addsc(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11748 break; 11749 case OPC_ADDWC: 11750 check_dsp(ctx); 11751 gen_helper_addwc(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11752 break; 11753 case OPC_MODSUB: 11754 check_dsp(ctx); 11755 gen_helper_modsub(cpu_gpr[ret], v1_t, v2_t); 11756 break; 11757 case OPC_RADDU_W_QB: 11758 check_dsp(ctx); 11759 gen_helper_raddu_w_qb(cpu_gpr[ret], v1_t); 11760 break; 11761 } 11762 break; 11763 case OPC_CMPU_EQ_QB_DSP: 11764 switch (op2) { 11765 case OPC_PRECR_QB_PH: 11766 check_dsp_r2(ctx); 11767 gen_helper_precr_qb_ph(cpu_gpr[ret], v1_t, v2_t); 11768 break; 11769 case OPC_PRECRQ_QB_PH: 11770 check_dsp(ctx); 11771 gen_helper_precrq_qb_ph(cpu_gpr[ret], v1_t, v2_t); 11772 break; 11773 case OPC_PRECR_SRA_PH_W: 11774 check_dsp_r2(ctx); 11775 { 11776 TCGv_i32 sa_t = tcg_constant_i32(v2); 11777 gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t, v1_t, 11778 cpu_gpr[ret]); 11779 break; 11780 } 11781 case OPC_PRECR_SRA_R_PH_W: 11782 check_dsp_r2(ctx); 11783 { 11784 TCGv_i32 sa_t = tcg_constant_i32(v2); 11785 gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t, v1_t, 11786 cpu_gpr[ret]); 11787 break; 11788 } 11789 case OPC_PRECRQ_PH_W: 11790 check_dsp(ctx); 11791 gen_helper_precrq_ph_w(cpu_gpr[ret], v1_t, v2_t); 11792 break; 11793 case OPC_PRECRQ_RS_PH_W: 11794 check_dsp(ctx); 11795 gen_helper_precrq_rs_ph_w(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11796 break; 11797 case OPC_PRECRQU_S_QB_PH: 11798 check_dsp(ctx); 11799 gen_helper_precrqu_s_qb_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11800 break; 11801 } 11802 break; 11803 #ifdef TARGET_MIPS64 11804 case OPC_ABSQ_S_QH_DSP: 11805 switch (op2) { 11806 case OPC_PRECEQ_L_PWL: 11807 check_dsp(ctx); 11808 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFFFFFF00000000ull); 11809 break; 11810 case OPC_PRECEQ_L_PWR: 11811 check_dsp(ctx); 11812 tcg_gen_shli_tl(cpu_gpr[ret], v2_t, 32); 11813 break; 11814 case OPC_PRECEQ_PW_QHL: 11815 check_dsp(ctx); 11816 gen_helper_preceq_pw_qhl(cpu_gpr[ret], v2_t); 11817 break; 11818 case OPC_PRECEQ_PW_QHR: 11819 check_dsp(ctx); 11820 gen_helper_preceq_pw_qhr(cpu_gpr[ret], v2_t); 11821 break; 11822 case OPC_PRECEQ_PW_QHLA: 11823 check_dsp(ctx); 11824 gen_helper_preceq_pw_qhla(cpu_gpr[ret], v2_t); 11825 break; 11826 case OPC_PRECEQ_PW_QHRA: 11827 check_dsp(ctx); 11828 gen_helper_preceq_pw_qhra(cpu_gpr[ret], v2_t); 11829 break; 11830 case OPC_PRECEQU_QH_OBL: 11831 check_dsp(ctx); 11832 gen_helper_precequ_qh_obl(cpu_gpr[ret], v2_t); 11833 break; 11834 case OPC_PRECEQU_QH_OBR: 11835 check_dsp(ctx); 11836 gen_helper_precequ_qh_obr(cpu_gpr[ret], v2_t); 11837 break; 11838 case OPC_PRECEQU_QH_OBLA: 11839 check_dsp(ctx); 11840 gen_helper_precequ_qh_obla(cpu_gpr[ret], v2_t); 11841 break; 11842 case OPC_PRECEQU_QH_OBRA: 11843 check_dsp(ctx); 11844 gen_helper_precequ_qh_obra(cpu_gpr[ret], v2_t); 11845 break; 11846 case OPC_PRECEU_QH_OBL: 11847 check_dsp(ctx); 11848 gen_helper_preceu_qh_obl(cpu_gpr[ret], v2_t); 11849 break; 11850 case OPC_PRECEU_QH_OBR: 11851 check_dsp(ctx); 11852 gen_helper_preceu_qh_obr(cpu_gpr[ret], v2_t); 11853 break; 11854 case OPC_PRECEU_QH_OBLA: 11855 check_dsp(ctx); 11856 gen_helper_preceu_qh_obla(cpu_gpr[ret], v2_t); 11857 break; 11858 case OPC_PRECEU_QH_OBRA: 11859 check_dsp(ctx); 11860 gen_helper_preceu_qh_obra(cpu_gpr[ret], v2_t); 11861 break; 11862 case OPC_ABSQ_S_OB: 11863 check_dsp_r2(ctx); 11864 gen_helper_absq_s_ob(cpu_gpr[ret], v2_t, tcg_env); 11865 break; 11866 case OPC_ABSQ_S_PW: 11867 check_dsp(ctx); 11868 gen_helper_absq_s_pw(cpu_gpr[ret], v2_t, tcg_env); 11869 break; 11870 case OPC_ABSQ_S_QH: 11871 check_dsp(ctx); 11872 gen_helper_absq_s_qh(cpu_gpr[ret], v2_t, tcg_env); 11873 break; 11874 } 11875 break; 11876 case OPC_ADDU_OB_DSP: 11877 switch (op2) { 11878 case OPC_RADDU_L_OB: 11879 check_dsp(ctx); 11880 gen_helper_raddu_l_ob(cpu_gpr[ret], v1_t); 11881 break; 11882 case OPC_SUBQ_PW: 11883 check_dsp(ctx); 11884 gen_helper_subq_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11885 break; 11886 case OPC_SUBQ_S_PW: 11887 check_dsp(ctx); 11888 gen_helper_subq_s_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11889 break; 11890 case OPC_SUBQ_QH: 11891 check_dsp(ctx); 11892 gen_helper_subq_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11893 break; 11894 case OPC_SUBQ_S_QH: 11895 check_dsp(ctx); 11896 gen_helper_subq_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11897 break; 11898 case OPC_SUBU_OB: 11899 check_dsp(ctx); 11900 gen_helper_subu_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11901 break; 11902 case OPC_SUBU_S_OB: 11903 check_dsp(ctx); 11904 gen_helper_subu_s_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11905 break; 11906 case OPC_SUBU_QH: 11907 check_dsp_r2(ctx); 11908 gen_helper_subu_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11909 break; 11910 case OPC_SUBU_S_QH: 11911 check_dsp_r2(ctx); 11912 gen_helper_subu_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11913 break; 11914 case OPC_SUBUH_OB: 11915 check_dsp_r2(ctx); 11916 gen_helper_subuh_ob(cpu_gpr[ret], v1_t, v2_t); 11917 break; 11918 case OPC_SUBUH_R_OB: 11919 check_dsp_r2(ctx); 11920 gen_helper_subuh_r_ob(cpu_gpr[ret], v1_t, v2_t); 11921 break; 11922 case OPC_ADDQ_PW: 11923 check_dsp(ctx); 11924 gen_helper_addq_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11925 break; 11926 case OPC_ADDQ_S_PW: 11927 check_dsp(ctx); 11928 gen_helper_addq_s_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11929 break; 11930 case OPC_ADDQ_QH: 11931 check_dsp(ctx); 11932 gen_helper_addq_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11933 break; 11934 case OPC_ADDQ_S_QH: 11935 check_dsp(ctx); 11936 gen_helper_addq_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11937 break; 11938 case OPC_ADDU_OB: 11939 check_dsp(ctx); 11940 gen_helper_addu_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11941 break; 11942 case OPC_ADDU_S_OB: 11943 check_dsp(ctx); 11944 gen_helper_addu_s_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11945 break; 11946 case OPC_ADDU_QH: 11947 check_dsp_r2(ctx); 11948 gen_helper_addu_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11949 break; 11950 case OPC_ADDU_S_QH: 11951 check_dsp_r2(ctx); 11952 gen_helper_addu_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11953 break; 11954 case OPC_ADDUH_OB: 11955 check_dsp_r2(ctx); 11956 gen_helper_adduh_ob(cpu_gpr[ret], v1_t, v2_t); 11957 break; 11958 case OPC_ADDUH_R_OB: 11959 check_dsp_r2(ctx); 11960 gen_helper_adduh_r_ob(cpu_gpr[ret], v1_t, v2_t); 11961 break; 11962 } 11963 break; 11964 case OPC_CMPU_EQ_OB_DSP: 11965 switch (op2) { 11966 case OPC_PRECR_OB_QH: 11967 check_dsp_r2(ctx); 11968 gen_helper_precr_ob_qh(cpu_gpr[ret], v1_t, v2_t); 11969 break; 11970 case OPC_PRECR_SRA_QH_PW: 11971 check_dsp_r2(ctx); 11972 { 11973 TCGv_i32 ret_t = tcg_constant_i32(ret); 11974 gen_helper_precr_sra_qh_pw(v2_t, v1_t, v2_t, ret_t); 11975 break; 11976 } 11977 case OPC_PRECR_SRA_R_QH_PW: 11978 check_dsp_r2(ctx); 11979 { 11980 TCGv_i32 sa_v = tcg_constant_i32(ret); 11981 gen_helper_precr_sra_r_qh_pw(v2_t, v1_t, v2_t, sa_v); 11982 break; 11983 } 11984 case OPC_PRECRQ_OB_QH: 11985 check_dsp(ctx); 11986 gen_helper_precrq_ob_qh(cpu_gpr[ret], v1_t, v2_t); 11987 break; 11988 case OPC_PRECRQ_PW_L: 11989 check_dsp(ctx); 11990 gen_helper_precrq_pw_l(cpu_gpr[ret], v1_t, v2_t); 11991 break; 11992 case OPC_PRECRQ_QH_PW: 11993 check_dsp(ctx); 11994 gen_helper_precrq_qh_pw(cpu_gpr[ret], v1_t, v2_t); 11995 break; 11996 case OPC_PRECRQ_RS_QH_PW: 11997 check_dsp(ctx); 11998 gen_helper_precrq_rs_qh_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11999 break; 12000 case OPC_PRECRQU_S_OB_QH: 12001 check_dsp(ctx); 12002 gen_helper_precrqu_s_ob_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12003 break; 12004 } 12005 break; 12006 #endif 12007 } 12008 } 12009 12010 static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc, 12011 int ret, int v1, int v2) 12012 { 12013 uint32_t op2; 12014 TCGv t0; 12015 TCGv v1_t; 12016 TCGv v2_t; 12017 12018 if (ret == 0) { 12019 /* Treat as NOP. */ 12020 return; 12021 } 12022 12023 t0 = tcg_temp_new(); 12024 v1_t = tcg_temp_new(); 12025 v2_t = tcg_temp_new(); 12026 12027 tcg_gen_movi_tl(t0, v1); 12028 gen_load_gpr(v1_t, v1); 12029 gen_load_gpr(v2_t, v2); 12030 12031 switch (opc) { 12032 case OPC_SHLL_QB_DSP: 12033 { 12034 op2 = MASK_SHLL_QB(ctx->opcode); 12035 switch (op2) { 12036 case OPC_SHLL_QB: 12037 check_dsp(ctx); 12038 gen_helper_shll_qb(cpu_gpr[ret], t0, v2_t, tcg_env); 12039 break; 12040 case OPC_SHLLV_QB: 12041 check_dsp(ctx); 12042 gen_helper_shll_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12043 break; 12044 case OPC_SHLL_PH: 12045 check_dsp(ctx); 12046 gen_helper_shll_ph(cpu_gpr[ret], t0, v2_t, tcg_env); 12047 break; 12048 case OPC_SHLLV_PH: 12049 check_dsp(ctx); 12050 gen_helper_shll_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12051 break; 12052 case OPC_SHLL_S_PH: 12053 check_dsp(ctx); 12054 gen_helper_shll_s_ph(cpu_gpr[ret], t0, v2_t, tcg_env); 12055 break; 12056 case OPC_SHLLV_S_PH: 12057 check_dsp(ctx); 12058 gen_helper_shll_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12059 break; 12060 case OPC_SHLL_S_W: 12061 check_dsp(ctx); 12062 gen_helper_shll_s_w(cpu_gpr[ret], t0, v2_t, tcg_env); 12063 break; 12064 case OPC_SHLLV_S_W: 12065 check_dsp(ctx); 12066 gen_helper_shll_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12067 break; 12068 case OPC_SHRL_QB: 12069 check_dsp(ctx); 12070 gen_helper_shrl_qb(cpu_gpr[ret], t0, v2_t); 12071 break; 12072 case OPC_SHRLV_QB: 12073 check_dsp(ctx); 12074 gen_helper_shrl_qb(cpu_gpr[ret], v1_t, v2_t); 12075 break; 12076 case OPC_SHRL_PH: 12077 check_dsp_r2(ctx); 12078 gen_helper_shrl_ph(cpu_gpr[ret], t0, v2_t); 12079 break; 12080 case OPC_SHRLV_PH: 12081 check_dsp_r2(ctx); 12082 gen_helper_shrl_ph(cpu_gpr[ret], v1_t, v2_t); 12083 break; 12084 case OPC_SHRA_QB: 12085 check_dsp_r2(ctx); 12086 gen_helper_shra_qb(cpu_gpr[ret], t0, v2_t); 12087 break; 12088 case OPC_SHRA_R_QB: 12089 check_dsp_r2(ctx); 12090 gen_helper_shra_r_qb(cpu_gpr[ret], t0, v2_t); 12091 break; 12092 case OPC_SHRAV_QB: 12093 check_dsp_r2(ctx); 12094 gen_helper_shra_qb(cpu_gpr[ret], v1_t, v2_t); 12095 break; 12096 case OPC_SHRAV_R_QB: 12097 check_dsp_r2(ctx); 12098 gen_helper_shra_r_qb(cpu_gpr[ret], v1_t, v2_t); 12099 break; 12100 case OPC_SHRA_PH: 12101 check_dsp(ctx); 12102 gen_helper_shra_ph(cpu_gpr[ret], t0, v2_t); 12103 break; 12104 case OPC_SHRA_R_PH: 12105 check_dsp(ctx); 12106 gen_helper_shra_r_ph(cpu_gpr[ret], t0, v2_t); 12107 break; 12108 case OPC_SHRAV_PH: 12109 check_dsp(ctx); 12110 gen_helper_shra_ph(cpu_gpr[ret], v1_t, v2_t); 12111 break; 12112 case OPC_SHRAV_R_PH: 12113 check_dsp(ctx); 12114 gen_helper_shra_r_ph(cpu_gpr[ret], v1_t, v2_t); 12115 break; 12116 case OPC_SHRA_R_W: 12117 check_dsp(ctx); 12118 gen_helper_shra_r_w(cpu_gpr[ret], t0, v2_t); 12119 break; 12120 case OPC_SHRAV_R_W: 12121 check_dsp(ctx); 12122 gen_helper_shra_r_w(cpu_gpr[ret], v1_t, v2_t); 12123 break; 12124 default: /* Invalid */ 12125 MIPS_INVAL("MASK SHLL.QB"); 12126 gen_reserved_instruction(ctx); 12127 break; 12128 } 12129 break; 12130 } 12131 #ifdef TARGET_MIPS64 12132 case OPC_SHLL_OB_DSP: 12133 op2 = MASK_SHLL_OB(ctx->opcode); 12134 switch (op2) { 12135 case OPC_SHLL_PW: 12136 check_dsp(ctx); 12137 gen_helper_shll_pw(cpu_gpr[ret], v2_t, t0, tcg_env); 12138 break; 12139 case OPC_SHLLV_PW: 12140 check_dsp(ctx); 12141 gen_helper_shll_pw(cpu_gpr[ret], v2_t, v1_t, tcg_env); 12142 break; 12143 case OPC_SHLL_S_PW: 12144 check_dsp(ctx); 12145 gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, t0, tcg_env); 12146 break; 12147 case OPC_SHLLV_S_PW: 12148 check_dsp(ctx); 12149 gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, v1_t, tcg_env); 12150 break; 12151 case OPC_SHLL_OB: 12152 check_dsp(ctx); 12153 gen_helper_shll_ob(cpu_gpr[ret], v2_t, t0, tcg_env); 12154 break; 12155 case OPC_SHLLV_OB: 12156 check_dsp(ctx); 12157 gen_helper_shll_ob(cpu_gpr[ret], v2_t, v1_t, tcg_env); 12158 break; 12159 case OPC_SHLL_QH: 12160 check_dsp(ctx); 12161 gen_helper_shll_qh(cpu_gpr[ret], v2_t, t0, tcg_env); 12162 break; 12163 case OPC_SHLLV_QH: 12164 check_dsp(ctx); 12165 gen_helper_shll_qh(cpu_gpr[ret], v2_t, v1_t, tcg_env); 12166 break; 12167 case OPC_SHLL_S_QH: 12168 check_dsp(ctx); 12169 gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, t0, tcg_env); 12170 break; 12171 case OPC_SHLLV_S_QH: 12172 check_dsp(ctx); 12173 gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, v1_t, tcg_env); 12174 break; 12175 case OPC_SHRA_OB: 12176 check_dsp_r2(ctx); 12177 gen_helper_shra_ob(cpu_gpr[ret], v2_t, t0); 12178 break; 12179 case OPC_SHRAV_OB: 12180 check_dsp_r2(ctx); 12181 gen_helper_shra_ob(cpu_gpr[ret], v2_t, v1_t); 12182 break; 12183 case OPC_SHRA_R_OB: 12184 check_dsp_r2(ctx); 12185 gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, t0); 12186 break; 12187 case OPC_SHRAV_R_OB: 12188 check_dsp_r2(ctx); 12189 gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, v1_t); 12190 break; 12191 case OPC_SHRA_PW: 12192 check_dsp(ctx); 12193 gen_helper_shra_pw(cpu_gpr[ret], v2_t, t0); 12194 break; 12195 case OPC_SHRAV_PW: 12196 check_dsp(ctx); 12197 gen_helper_shra_pw(cpu_gpr[ret], v2_t, v1_t); 12198 break; 12199 case OPC_SHRA_R_PW: 12200 check_dsp(ctx); 12201 gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, t0); 12202 break; 12203 case OPC_SHRAV_R_PW: 12204 check_dsp(ctx); 12205 gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, v1_t); 12206 break; 12207 case OPC_SHRA_QH: 12208 check_dsp(ctx); 12209 gen_helper_shra_qh(cpu_gpr[ret], v2_t, t0); 12210 break; 12211 case OPC_SHRAV_QH: 12212 check_dsp(ctx); 12213 gen_helper_shra_qh(cpu_gpr[ret], v2_t, v1_t); 12214 break; 12215 case OPC_SHRA_R_QH: 12216 check_dsp(ctx); 12217 gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, t0); 12218 break; 12219 case OPC_SHRAV_R_QH: 12220 check_dsp(ctx); 12221 gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, v1_t); 12222 break; 12223 case OPC_SHRL_OB: 12224 check_dsp(ctx); 12225 gen_helper_shrl_ob(cpu_gpr[ret], v2_t, t0); 12226 break; 12227 case OPC_SHRLV_OB: 12228 check_dsp(ctx); 12229 gen_helper_shrl_ob(cpu_gpr[ret], v2_t, v1_t); 12230 break; 12231 case OPC_SHRL_QH: 12232 check_dsp_r2(ctx); 12233 gen_helper_shrl_qh(cpu_gpr[ret], v2_t, t0); 12234 break; 12235 case OPC_SHRLV_QH: 12236 check_dsp_r2(ctx); 12237 gen_helper_shrl_qh(cpu_gpr[ret], v2_t, v1_t); 12238 break; 12239 default: /* Invalid */ 12240 MIPS_INVAL("MASK SHLL.OB"); 12241 gen_reserved_instruction(ctx); 12242 break; 12243 } 12244 break; 12245 #endif 12246 } 12247 } 12248 12249 static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2, 12250 int ret, int v1, int v2, int check_ret) 12251 { 12252 TCGv_i32 t0; 12253 TCGv v1_t; 12254 TCGv v2_t; 12255 12256 if ((ret == 0) && (check_ret == 1)) { 12257 /* Treat as NOP. */ 12258 return; 12259 } 12260 12261 t0 = tcg_temp_new_i32(); 12262 v1_t = tcg_temp_new(); 12263 v2_t = tcg_temp_new(); 12264 12265 tcg_gen_movi_i32(t0, ret); 12266 gen_load_gpr(v1_t, v1); 12267 gen_load_gpr(v2_t, v2); 12268 12269 switch (op1) { 12270 case OPC_MUL_PH_DSP: 12271 check_dsp_r2(ctx); 12272 switch (op2) { 12273 case OPC_MUL_PH: 12274 gen_helper_mul_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12275 break; 12276 case OPC_MUL_S_PH: 12277 gen_helper_mul_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12278 break; 12279 case OPC_MULQ_S_W: 12280 gen_helper_mulq_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12281 break; 12282 case OPC_MULQ_RS_W: 12283 gen_helper_mulq_rs_w(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12284 break; 12285 } 12286 break; 12287 case OPC_DPA_W_PH_DSP: 12288 switch (op2) { 12289 case OPC_DPAU_H_QBL: 12290 check_dsp(ctx); 12291 gen_helper_dpau_h_qbl(t0, v1_t, v2_t, tcg_env); 12292 break; 12293 case OPC_DPAU_H_QBR: 12294 check_dsp(ctx); 12295 gen_helper_dpau_h_qbr(t0, v1_t, v2_t, tcg_env); 12296 break; 12297 case OPC_DPSU_H_QBL: 12298 check_dsp(ctx); 12299 gen_helper_dpsu_h_qbl(t0, v1_t, v2_t, tcg_env); 12300 break; 12301 case OPC_DPSU_H_QBR: 12302 check_dsp(ctx); 12303 gen_helper_dpsu_h_qbr(t0, v1_t, v2_t, tcg_env); 12304 break; 12305 case OPC_DPA_W_PH: 12306 check_dsp_r2(ctx); 12307 gen_helper_dpa_w_ph(t0, v1_t, v2_t, tcg_env); 12308 break; 12309 case OPC_DPAX_W_PH: 12310 check_dsp_r2(ctx); 12311 gen_helper_dpax_w_ph(t0, v1_t, v2_t, tcg_env); 12312 break; 12313 case OPC_DPAQ_S_W_PH: 12314 check_dsp(ctx); 12315 gen_helper_dpaq_s_w_ph(t0, v1_t, v2_t, tcg_env); 12316 break; 12317 case OPC_DPAQX_S_W_PH: 12318 check_dsp_r2(ctx); 12319 gen_helper_dpaqx_s_w_ph(t0, v1_t, v2_t, tcg_env); 12320 break; 12321 case OPC_DPAQX_SA_W_PH: 12322 check_dsp_r2(ctx); 12323 gen_helper_dpaqx_sa_w_ph(t0, v1_t, v2_t, tcg_env); 12324 break; 12325 case OPC_DPS_W_PH: 12326 check_dsp_r2(ctx); 12327 gen_helper_dps_w_ph(t0, v1_t, v2_t, tcg_env); 12328 break; 12329 case OPC_DPSX_W_PH: 12330 check_dsp_r2(ctx); 12331 gen_helper_dpsx_w_ph(t0, v1_t, v2_t, tcg_env); 12332 break; 12333 case OPC_DPSQ_S_W_PH: 12334 check_dsp(ctx); 12335 gen_helper_dpsq_s_w_ph(t0, v1_t, v2_t, tcg_env); 12336 break; 12337 case OPC_DPSQX_S_W_PH: 12338 check_dsp_r2(ctx); 12339 gen_helper_dpsqx_s_w_ph(t0, v1_t, v2_t, tcg_env); 12340 break; 12341 case OPC_DPSQX_SA_W_PH: 12342 check_dsp_r2(ctx); 12343 gen_helper_dpsqx_sa_w_ph(t0, v1_t, v2_t, tcg_env); 12344 break; 12345 case OPC_MULSAQ_S_W_PH: 12346 check_dsp(ctx); 12347 gen_helper_mulsaq_s_w_ph(t0, v1_t, v2_t, tcg_env); 12348 break; 12349 case OPC_DPAQ_SA_L_W: 12350 check_dsp(ctx); 12351 gen_helper_dpaq_sa_l_w(t0, v1_t, v2_t, tcg_env); 12352 break; 12353 case OPC_DPSQ_SA_L_W: 12354 check_dsp(ctx); 12355 gen_helper_dpsq_sa_l_w(t0, v1_t, v2_t, tcg_env); 12356 break; 12357 case OPC_MAQ_S_W_PHL: 12358 check_dsp(ctx); 12359 gen_helper_maq_s_w_phl(t0, v1_t, v2_t, tcg_env); 12360 break; 12361 case OPC_MAQ_S_W_PHR: 12362 check_dsp(ctx); 12363 gen_helper_maq_s_w_phr(t0, v1_t, v2_t, tcg_env); 12364 break; 12365 case OPC_MAQ_SA_W_PHL: 12366 check_dsp(ctx); 12367 gen_helper_maq_sa_w_phl(t0, v1_t, v2_t, tcg_env); 12368 break; 12369 case OPC_MAQ_SA_W_PHR: 12370 check_dsp(ctx); 12371 gen_helper_maq_sa_w_phr(t0, v1_t, v2_t, tcg_env); 12372 break; 12373 case OPC_MULSA_W_PH: 12374 check_dsp_r2(ctx); 12375 gen_helper_mulsa_w_ph(t0, v1_t, v2_t, tcg_env); 12376 break; 12377 } 12378 break; 12379 #ifdef TARGET_MIPS64 12380 case OPC_DPAQ_W_QH_DSP: 12381 { 12382 int ac = ret & 0x03; 12383 tcg_gen_movi_i32(t0, ac); 12384 12385 switch (op2) { 12386 case OPC_DMADD: 12387 check_dsp(ctx); 12388 gen_helper_dmadd(v1_t, v2_t, t0, tcg_env); 12389 break; 12390 case OPC_DMADDU: 12391 check_dsp(ctx); 12392 gen_helper_dmaddu(v1_t, v2_t, t0, tcg_env); 12393 break; 12394 case OPC_DMSUB: 12395 check_dsp(ctx); 12396 gen_helper_dmsub(v1_t, v2_t, t0, tcg_env); 12397 break; 12398 case OPC_DMSUBU: 12399 check_dsp(ctx); 12400 gen_helper_dmsubu(v1_t, v2_t, t0, tcg_env); 12401 break; 12402 case OPC_DPA_W_QH: 12403 check_dsp_r2(ctx); 12404 gen_helper_dpa_w_qh(v1_t, v2_t, t0, tcg_env); 12405 break; 12406 case OPC_DPAQ_S_W_QH: 12407 check_dsp(ctx); 12408 gen_helper_dpaq_s_w_qh(v1_t, v2_t, t0, tcg_env); 12409 break; 12410 case OPC_DPAQ_SA_L_PW: 12411 check_dsp(ctx); 12412 gen_helper_dpaq_sa_l_pw(v1_t, v2_t, t0, tcg_env); 12413 break; 12414 case OPC_DPAU_H_OBL: 12415 check_dsp(ctx); 12416 gen_helper_dpau_h_obl(v1_t, v2_t, t0, tcg_env); 12417 break; 12418 case OPC_DPAU_H_OBR: 12419 check_dsp(ctx); 12420 gen_helper_dpau_h_obr(v1_t, v2_t, t0, tcg_env); 12421 break; 12422 case OPC_DPS_W_QH: 12423 check_dsp_r2(ctx); 12424 gen_helper_dps_w_qh(v1_t, v2_t, t0, tcg_env); 12425 break; 12426 case OPC_DPSQ_S_W_QH: 12427 check_dsp(ctx); 12428 gen_helper_dpsq_s_w_qh(v1_t, v2_t, t0, tcg_env); 12429 break; 12430 case OPC_DPSQ_SA_L_PW: 12431 check_dsp(ctx); 12432 gen_helper_dpsq_sa_l_pw(v1_t, v2_t, t0, tcg_env); 12433 break; 12434 case OPC_DPSU_H_OBL: 12435 check_dsp(ctx); 12436 gen_helper_dpsu_h_obl(v1_t, v2_t, t0, tcg_env); 12437 break; 12438 case OPC_DPSU_H_OBR: 12439 check_dsp(ctx); 12440 gen_helper_dpsu_h_obr(v1_t, v2_t, t0, tcg_env); 12441 break; 12442 case OPC_MAQ_S_L_PWL: 12443 check_dsp(ctx); 12444 gen_helper_maq_s_l_pwl(v1_t, v2_t, t0, tcg_env); 12445 break; 12446 case OPC_MAQ_S_L_PWR: 12447 check_dsp(ctx); 12448 gen_helper_maq_s_l_pwr(v1_t, v2_t, t0, tcg_env); 12449 break; 12450 case OPC_MAQ_S_W_QHLL: 12451 check_dsp(ctx); 12452 gen_helper_maq_s_w_qhll(v1_t, v2_t, t0, tcg_env); 12453 break; 12454 case OPC_MAQ_SA_W_QHLL: 12455 check_dsp(ctx); 12456 gen_helper_maq_sa_w_qhll(v1_t, v2_t, t0, tcg_env); 12457 break; 12458 case OPC_MAQ_S_W_QHLR: 12459 check_dsp(ctx); 12460 gen_helper_maq_s_w_qhlr(v1_t, v2_t, t0, tcg_env); 12461 break; 12462 case OPC_MAQ_SA_W_QHLR: 12463 check_dsp(ctx); 12464 gen_helper_maq_sa_w_qhlr(v1_t, v2_t, t0, tcg_env); 12465 break; 12466 case OPC_MAQ_S_W_QHRL: 12467 check_dsp(ctx); 12468 gen_helper_maq_s_w_qhrl(v1_t, v2_t, t0, tcg_env); 12469 break; 12470 case OPC_MAQ_SA_W_QHRL: 12471 check_dsp(ctx); 12472 gen_helper_maq_sa_w_qhrl(v1_t, v2_t, t0, tcg_env); 12473 break; 12474 case OPC_MAQ_S_W_QHRR: 12475 check_dsp(ctx); 12476 gen_helper_maq_s_w_qhrr(v1_t, v2_t, t0, tcg_env); 12477 break; 12478 case OPC_MAQ_SA_W_QHRR: 12479 check_dsp(ctx); 12480 gen_helper_maq_sa_w_qhrr(v1_t, v2_t, t0, tcg_env); 12481 break; 12482 case OPC_MULSAQ_S_L_PW: 12483 check_dsp(ctx); 12484 gen_helper_mulsaq_s_l_pw(v1_t, v2_t, t0, tcg_env); 12485 break; 12486 case OPC_MULSAQ_S_W_QH: 12487 check_dsp(ctx); 12488 gen_helper_mulsaq_s_w_qh(v1_t, v2_t, t0, tcg_env); 12489 break; 12490 } 12491 } 12492 break; 12493 #endif 12494 case OPC_ADDU_QB_DSP: 12495 switch (op2) { 12496 case OPC_MULEU_S_PH_QBL: 12497 check_dsp(ctx); 12498 gen_helper_muleu_s_ph_qbl(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12499 break; 12500 case OPC_MULEU_S_PH_QBR: 12501 check_dsp(ctx); 12502 gen_helper_muleu_s_ph_qbr(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12503 break; 12504 case OPC_MULQ_RS_PH: 12505 check_dsp(ctx); 12506 gen_helper_mulq_rs_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12507 break; 12508 case OPC_MULEQ_S_W_PHL: 12509 check_dsp(ctx); 12510 gen_helper_muleq_s_w_phl(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12511 break; 12512 case OPC_MULEQ_S_W_PHR: 12513 check_dsp(ctx); 12514 gen_helper_muleq_s_w_phr(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12515 break; 12516 case OPC_MULQ_S_PH: 12517 check_dsp_r2(ctx); 12518 gen_helper_mulq_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12519 break; 12520 } 12521 break; 12522 #ifdef TARGET_MIPS64 12523 case OPC_ADDU_OB_DSP: 12524 switch (op2) { 12525 case OPC_MULEQ_S_PW_QHL: 12526 check_dsp(ctx); 12527 gen_helper_muleq_s_pw_qhl(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12528 break; 12529 case OPC_MULEQ_S_PW_QHR: 12530 check_dsp(ctx); 12531 gen_helper_muleq_s_pw_qhr(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12532 break; 12533 case OPC_MULEU_S_QH_OBL: 12534 check_dsp(ctx); 12535 gen_helper_muleu_s_qh_obl(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12536 break; 12537 case OPC_MULEU_S_QH_OBR: 12538 check_dsp(ctx); 12539 gen_helper_muleu_s_qh_obr(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12540 break; 12541 case OPC_MULQ_RS_QH: 12542 check_dsp(ctx); 12543 gen_helper_mulq_rs_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12544 break; 12545 } 12546 break; 12547 #endif 12548 } 12549 } 12550 12551 static void gen_mipsdsp_bitinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, 12552 int ret, int val) 12553 { 12554 int16_t imm; 12555 TCGv t0; 12556 TCGv val_t; 12557 12558 if (ret == 0) { 12559 /* Treat as NOP. */ 12560 return; 12561 } 12562 12563 t0 = tcg_temp_new(); 12564 val_t = tcg_temp_new(); 12565 gen_load_gpr(val_t, val); 12566 12567 switch (op1) { 12568 case OPC_ABSQ_S_PH_DSP: 12569 switch (op2) { 12570 case OPC_BITREV: 12571 check_dsp(ctx); 12572 gen_helper_bitrev(cpu_gpr[ret], val_t); 12573 break; 12574 case OPC_REPL_QB: 12575 check_dsp(ctx); 12576 { 12577 target_long result; 12578 imm = (ctx->opcode >> 16) & 0xFF; 12579 result = (uint32_t)imm << 24 | 12580 (uint32_t)imm << 16 | 12581 (uint32_t)imm << 8 | 12582 (uint32_t)imm; 12583 result = (int32_t)result; 12584 tcg_gen_movi_tl(cpu_gpr[ret], result); 12585 } 12586 break; 12587 case OPC_REPLV_QB: 12588 check_dsp(ctx); 12589 tcg_gen_ext8u_tl(cpu_gpr[ret], val_t); 12590 tcg_gen_shli_tl(t0, cpu_gpr[ret], 8); 12591 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12592 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); 12593 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12594 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); 12595 break; 12596 case OPC_REPL_PH: 12597 check_dsp(ctx); 12598 { 12599 imm = (ctx->opcode >> 16) & 0x03FF; 12600 imm = (int16_t)(imm << 6) >> 6; 12601 tcg_gen_movi_tl(cpu_gpr[ret], \ 12602 (target_long)((int32_t)imm << 16 | \ 12603 (uint16_t)imm)); 12604 } 12605 break; 12606 case OPC_REPLV_PH: 12607 check_dsp(ctx); 12608 tcg_gen_ext16u_tl(cpu_gpr[ret], val_t); 12609 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); 12610 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12611 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); 12612 break; 12613 } 12614 break; 12615 #ifdef TARGET_MIPS64 12616 case OPC_ABSQ_S_QH_DSP: 12617 switch (op2) { 12618 case OPC_REPL_OB: 12619 check_dsp(ctx); 12620 { 12621 target_long temp; 12622 12623 imm = (ctx->opcode >> 16) & 0xFF; 12624 temp = ((uint64_t)imm << 8) | (uint64_t)imm; 12625 temp = (temp << 16) | temp; 12626 temp = (temp << 32) | temp; 12627 tcg_gen_movi_tl(cpu_gpr[ret], temp); 12628 break; 12629 } 12630 case OPC_REPL_PW: 12631 check_dsp(ctx); 12632 { 12633 target_long temp; 12634 12635 imm = (ctx->opcode >> 16) & 0x03FF; 12636 imm = (int16_t)(imm << 6) >> 6; 12637 temp = ((target_long)imm << 32) \ 12638 | ((target_long)imm & 0xFFFFFFFF); 12639 tcg_gen_movi_tl(cpu_gpr[ret], temp); 12640 break; 12641 } 12642 case OPC_REPL_QH: 12643 check_dsp(ctx); 12644 { 12645 target_long temp; 12646 12647 imm = (ctx->opcode >> 16) & 0x03FF; 12648 imm = (int16_t)(imm << 6) >> 6; 12649 12650 temp = ((uint64_t)(uint16_t)imm << 48) | 12651 ((uint64_t)(uint16_t)imm << 32) | 12652 ((uint64_t)(uint16_t)imm << 16) | 12653 (uint64_t)(uint16_t)imm; 12654 tcg_gen_movi_tl(cpu_gpr[ret], temp); 12655 break; 12656 } 12657 case OPC_REPLV_OB: 12658 check_dsp(ctx); 12659 tcg_gen_ext8u_tl(cpu_gpr[ret], val_t); 12660 tcg_gen_shli_tl(t0, cpu_gpr[ret], 8); 12661 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12662 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); 12663 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12664 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32); 12665 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12666 break; 12667 case OPC_REPLV_PW: 12668 check_dsp(ctx); 12669 tcg_gen_ext32u_i64(cpu_gpr[ret], val_t); 12670 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32); 12671 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12672 break; 12673 case OPC_REPLV_QH: 12674 check_dsp(ctx); 12675 tcg_gen_ext16u_tl(cpu_gpr[ret], val_t); 12676 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); 12677 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12678 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32); 12679 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12680 break; 12681 } 12682 break; 12683 #endif 12684 } 12685 } 12686 12687 static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx, 12688 uint32_t op1, uint32_t op2, 12689 int ret, int v1, int v2, int check_ret) 12690 { 12691 TCGv t1; 12692 TCGv v1_t; 12693 TCGv v2_t; 12694 12695 if ((ret == 0) && (check_ret == 1)) { 12696 /* Treat as NOP. */ 12697 return; 12698 } 12699 12700 t1 = tcg_temp_new(); 12701 v1_t = tcg_temp_new(); 12702 v2_t = tcg_temp_new(); 12703 12704 gen_load_gpr(v1_t, v1); 12705 gen_load_gpr(v2_t, v2); 12706 12707 switch (op1) { 12708 case OPC_CMPU_EQ_QB_DSP: 12709 switch (op2) { 12710 case OPC_CMPU_EQ_QB: 12711 check_dsp(ctx); 12712 gen_helper_cmpu_eq_qb(v1_t, v2_t, tcg_env); 12713 break; 12714 case OPC_CMPU_LT_QB: 12715 check_dsp(ctx); 12716 gen_helper_cmpu_lt_qb(v1_t, v2_t, tcg_env); 12717 break; 12718 case OPC_CMPU_LE_QB: 12719 check_dsp(ctx); 12720 gen_helper_cmpu_le_qb(v1_t, v2_t, tcg_env); 12721 break; 12722 case OPC_CMPGU_EQ_QB: 12723 check_dsp(ctx); 12724 gen_helper_cmpgu_eq_qb(cpu_gpr[ret], v1_t, v2_t); 12725 break; 12726 case OPC_CMPGU_LT_QB: 12727 check_dsp(ctx); 12728 gen_helper_cmpgu_lt_qb(cpu_gpr[ret], v1_t, v2_t); 12729 break; 12730 case OPC_CMPGU_LE_QB: 12731 check_dsp(ctx); 12732 gen_helper_cmpgu_le_qb(cpu_gpr[ret], v1_t, v2_t); 12733 break; 12734 case OPC_CMPGDU_EQ_QB: 12735 check_dsp_r2(ctx); 12736 gen_helper_cmpgu_eq_qb(t1, v1_t, v2_t); 12737 tcg_gen_mov_tl(cpu_gpr[ret], t1); 12738 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); 12739 tcg_gen_shli_tl(t1, t1, 24); 12740 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); 12741 break; 12742 case OPC_CMPGDU_LT_QB: 12743 check_dsp_r2(ctx); 12744 gen_helper_cmpgu_lt_qb(t1, v1_t, v2_t); 12745 tcg_gen_mov_tl(cpu_gpr[ret], t1); 12746 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); 12747 tcg_gen_shli_tl(t1, t1, 24); 12748 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); 12749 break; 12750 case OPC_CMPGDU_LE_QB: 12751 check_dsp_r2(ctx); 12752 gen_helper_cmpgu_le_qb(t1, v1_t, v2_t); 12753 tcg_gen_mov_tl(cpu_gpr[ret], t1); 12754 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); 12755 tcg_gen_shli_tl(t1, t1, 24); 12756 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); 12757 break; 12758 case OPC_CMP_EQ_PH: 12759 check_dsp(ctx); 12760 gen_helper_cmp_eq_ph(v1_t, v2_t, tcg_env); 12761 break; 12762 case OPC_CMP_LT_PH: 12763 check_dsp(ctx); 12764 gen_helper_cmp_lt_ph(v1_t, v2_t, tcg_env); 12765 break; 12766 case OPC_CMP_LE_PH: 12767 check_dsp(ctx); 12768 gen_helper_cmp_le_ph(v1_t, v2_t, tcg_env); 12769 break; 12770 case OPC_PICK_QB: 12771 check_dsp(ctx); 12772 gen_helper_pick_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12773 break; 12774 case OPC_PICK_PH: 12775 check_dsp(ctx); 12776 gen_helper_pick_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12777 break; 12778 case OPC_PACKRL_PH: 12779 check_dsp(ctx); 12780 gen_helper_packrl_ph(cpu_gpr[ret], v1_t, v2_t); 12781 break; 12782 } 12783 break; 12784 #ifdef TARGET_MIPS64 12785 case OPC_CMPU_EQ_OB_DSP: 12786 switch (op2) { 12787 case OPC_CMP_EQ_PW: 12788 check_dsp(ctx); 12789 gen_helper_cmp_eq_pw(v1_t, v2_t, tcg_env); 12790 break; 12791 case OPC_CMP_LT_PW: 12792 check_dsp(ctx); 12793 gen_helper_cmp_lt_pw(v1_t, v2_t, tcg_env); 12794 break; 12795 case OPC_CMP_LE_PW: 12796 check_dsp(ctx); 12797 gen_helper_cmp_le_pw(v1_t, v2_t, tcg_env); 12798 break; 12799 case OPC_CMP_EQ_QH: 12800 check_dsp(ctx); 12801 gen_helper_cmp_eq_qh(v1_t, v2_t, tcg_env); 12802 break; 12803 case OPC_CMP_LT_QH: 12804 check_dsp(ctx); 12805 gen_helper_cmp_lt_qh(v1_t, v2_t, tcg_env); 12806 break; 12807 case OPC_CMP_LE_QH: 12808 check_dsp(ctx); 12809 gen_helper_cmp_le_qh(v1_t, v2_t, tcg_env); 12810 break; 12811 case OPC_CMPGDU_EQ_OB: 12812 check_dsp_r2(ctx); 12813 gen_helper_cmpgdu_eq_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12814 break; 12815 case OPC_CMPGDU_LT_OB: 12816 check_dsp_r2(ctx); 12817 gen_helper_cmpgdu_lt_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12818 break; 12819 case OPC_CMPGDU_LE_OB: 12820 check_dsp_r2(ctx); 12821 gen_helper_cmpgdu_le_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12822 break; 12823 case OPC_CMPGU_EQ_OB: 12824 check_dsp(ctx); 12825 gen_helper_cmpgu_eq_ob(cpu_gpr[ret], v1_t, v2_t); 12826 break; 12827 case OPC_CMPGU_LT_OB: 12828 check_dsp(ctx); 12829 gen_helper_cmpgu_lt_ob(cpu_gpr[ret], v1_t, v2_t); 12830 break; 12831 case OPC_CMPGU_LE_OB: 12832 check_dsp(ctx); 12833 gen_helper_cmpgu_le_ob(cpu_gpr[ret], v1_t, v2_t); 12834 break; 12835 case OPC_CMPU_EQ_OB: 12836 check_dsp(ctx); 12837 gen_helper_cmpu_eq_ob(v1_t, v2_t, tcg_env); 12838 break; 12839 case OPC_CMPU_LT_OB: 12840 check_dsp(ctx); 12841 gen_helper_cmpu_lt_ob(v1_t, v2_t, tcg_env); 12842 break; 12843 case OPC_CMPU_LE_OB: 12844 check_dsp(ctx); 12845 gen_helper_cmpu_le_ob(v1_t, v2_t, tcg_env); 12846 break; 12847 case OPC_PACKRL_PW: 12848 check_dsp(ctx); 12849 gen_helper_packrl_pw(cpu_gpr[ret], v1_t, v2_t); 12850 break; 12851 case OPC_PICK_OB: 12852 check_dsp(ctx); 12853 gen_helper_pick_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12854 break; 12855 case OPC_PICK_PW: 12856 check_dsp(ctx); 12857 gen_helper_pick_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12858 break; 12859 case OPC_PICK_QH: 12860 check_dsp(ctx); 12861 gen_helper_pick_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12862 break; 12863 } 12864 break; 12865 #endif 12866 } 12867 } 12868 12869 static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx, 12870 uint32_t op1, int rt, int rs, int sa) 12871 { 12872 TCGv t0; 12873 12874 check_dsp_r2(ctx); 12875 12876 if (rt == 0) { 12877 /* Treat as NOP. */ 12878 return; 12879 } 12880 12881 t0 = tcg_temp_new(); 12882 gen_load_gpr(t0, rs); 12883 12884 switch (op1) { 12885 case OPC_APPEND_DSP: 12886 switch (MASK_APPEND(ctx->opcode)) { 12887 case OPC_APPEND: 12888 if (sa != 0) { 12889 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 32 - sa); 12890 } 12891 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 12892 break; 12893 case OPC_PREPEND: 12894 if (sa != 0) { 12895 tcg_gen_ext32u_tl(cpu_gpr[rt], cpu_gpr[rt]); 12896 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], sa); 12897 tcg_gen_shli_tl(t0, t0, 32 - sa); 12898 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); 12899 } 12900 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 12901 break; 12902 case OPC_BALIGN: 12903 sa &= 3; 12904 if (sa != 0 && sa != 2) { 12905 tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa); 12906 tcg_gen_ext32u_tl(t0, t0); 12907 tcg_gen_shri_tl(t0, t0, 8 * (4 - sa)); 12908 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); 12909 } 12910 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 12911 break; 12912 default: /* Invalid */ 12913 MIPS_INVAL("MASK APPEND"); 12914 gen_reserved_instruction(ctx); 12915 break; 12916 } 12917 break; 12918 #ifdef TARGET_MIPS64 12919 case OPC_DAPPEND_DSP: 12920 switch (MASK_DAPPEND(ctx->opcode)) { 12921 case OPC_DAPPEND: 12922 if (sa != 0) { 12923 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 64 - sa); 12924 } 12925 break; 12926 case OPC_PREPENDD: 12927 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], 0x20 | sa); 12928 tcg_gen_shli_tl(t0, t0, 64 - (0x20 | sa)); 12929 tcg_gen_or_tl(cpu_gpr[rt], t0, t0); 12930 break; 12931 case OPC_PREPENDW: 12932 if (sa != 0) { 12933 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], sa); 12934 tcg_gen_shli_tl(t0, t0, 64 - sa); 12935 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); 12936 } 12937 break; 12938 case OPC_DBALIGN: 12939 sa &= 7; 12940 if (sa != 0 && sa != 2 && sa != 4) { 12941 tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa); 12942 tcg_gen_shri_tl(t0, t0, 8 * (8 - sa)); 12943 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); 12944 } 12945 break; 12946 default: /* Invalid */ 12947 MIPS_INVAL("MASK DAPPEND"); 12948 gen_reserved_instruction(ctx); 12949 break; 12950 } 12951 break; 12952 #endif 12953 } 12954 } 12955 12956 static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, 12957 int ret, int v1, int v2, int check_ret) 12958 12959 { 12960 TCGv t0; 12961 TCGv t1; 12962 TCGv v1_t; 12963 int16_t imm; 12964 12965 if ((ret == 0) && (check_ret == 1)) { 12966 /* Treat as NOP. */ 12967 return; 12968 } 12969 12970 t0 = tcg_temp_new(); 12971 t1 = tcg_temp_new(); 12972 v1_t = tcg_temp_new(); 12973 12974 gen_load_gpr(v1_t, v1); 12975 12976 switch (op1) { 12977 case OPC_EXTR_W_DSP: 12978 check_dsp(ctx); 12979 switch (op2) { 12980 case OPC_EXTR_W: 12981 tcg_gen_movi_tl(t0, v2); 12982 tcg_gen_movi_tl(t1, v1); 12983 gen_helper_extr_w(cpu_gpr[ret], t0, t1, tcg_env); 12984 break; 12985 case OPC_EXTR_R_W: 12986 tcg_gen_movi_tl(t0, v2); 12987 tcg_gen_movi_tl(t1, v1); 12988 gen_helper_extr_r_w(cpu_gpr[ret], t0, t1, tcg_env); 12989 break; 12990 case OPC_EXTR_RS_W: 12991 tcg_gen_movi_tl(t0, v2); 12992 tcg_gen_movi_tl(t1, v1); 12993 gen_helper_extr_rs_w(cpu_gpr[ret], t0, t1, tcg_env); 12994 break; 12995 case OPC_EXTR_S_H: 12996 tcg_gen_movi_tl(t0, v2); 12997 tcg_gen_movi_tl(t1, v1); 12998 gen_helper_extr_s_h(cpu_gpr[ret], t0, t1, tcg_env); 12999 break; 13000 case OPC_EXTRV_S_H: 13001 tcg_gen_movi_tl(t0, v2); 13002 gen_helper_extr_s_h(cpu_gpr[ret], t0, v1_t, tcg_env); 13003 break; 13004 case OPC_EXTRV_W: 13005 tcg_gen_movi_tl(t0, v2); 13006 gen_helper_extr_w(cpu_gpr[ret], t0, v1_t, tcg_env); 13007 break; 13008 case OPC_EXTRV_R_W: 13009 tcg_gen_movi_tl(t0, v2); 13010 gen_helper_extr_r_w(cpu_gpr[ret], t0, v1_t, tcg_env); 13011 break; 13012 case OPC_EXTRV_RS_W: 13013 tcg_gen_movi_tl(t0, v2); 13014 gen_helper_extr_rs_w(cpu_gpr[ret], t0, v1_t, tcg_env); 13015 break; 13016 case OPC_EXTP: 13017 tcg_gen_movi_tl(t0, v2); 13018 tcg_gen_movi_tl(t1, v1); 13019 gen_helper_extp(cpu_gpr[ret], t0, t1, tcg_env); 13020 break; 13021 case OPC_EXTPV: 13022 tcg_gen_movi_tl(t0, v2); 13023 gen_helper_extp(cpu_gpr[ret], t0, v1_t, tcg_env); 13024 break; 13025 case OPC_EXTPDP: 13026 tcg_gen_movi_tl(t0, v2); 13027 tcg_gen_movi_tl(t1, v1); 13028 gen_helper_extpdp(cpu_gpr[ret], t0, t1, tcg_env); 13029 break; 13030 case OPC_EXTPDPV: 13031 tcg_gen_movi_tl(t0, v2); 13032 gen_helper_extpdp(cpu_gpr[ret], t0, v1_t, tcg_env); 13033 break; 13034 case OPC_SHILO: 13035 imm = (ctx->opcode >> 20) & 0x3F; 13036 tcg_gen_movi_tl(t0, ret); 13037 tcg_gen_movi_tl(t1, imm); 13038 gen_helper_shilo(t0, t1, tcg_env); 13039 break; 13040 case OPC_SHILOV: 13041 tcg_gen_movi_tl(t0, ret); 13042 gen_helper_shilo(t0, v1_t, tcg_env); 13043 break; 13044 case OPC_MTHLIP: 13045 tcg_gen_movi_tl(t0, ret); 13046 gen_helper_mthlip(t0, v1_t, tcg_env); 13047 break; 13048 case OPC_WRDSP: 13049 imm = (ctx->opcode >> 11) & 0x3FF; 13050 tcg_gen_movi_tl(t0, imm); 13051 gen_helper_wrdsp(v1_t, t0, tcg_env); 13052 break; 13053 case OPC_RDDSP: 13054 imm = (ctx->opcode >> 16) & 0x03FF; 13055 tcg_gen_movi_tl(t0, imm); 13056 gen_helper_rddsp(cpu_gpr[ret], t0, tcg_env); 13057 break; 13058 } 13059 break; 13060 #ifdef TARGET_MIPS64 13061 case OPC_DEXTR_W_DSP: 13062 check_dsp(ctx); 13063 switch (op2) { 13064 case OPC_DMTHLIP: 13065 tcg_gen_movi_tl(t0, ret); 13066 gen_helper_dmthlip(v1_t, t0, tcg_env); 13067 break; 13068 case OPC_DSHILO: 13069 { 13070 int shift = (ctx->opcode >> 19) & 0x7F; 13071 int ac = (ctx->opcode >> 11) & 0x03; 13072 tcg_gen_movi_tl(t0, shift); 13073 tcg_gen_movi_tl(t1, ac); 13074 gen_helper_dshilo(t0, t1, tcg_env); 13075 break; 13076 } 13077 case OPC_DSHILOV: 13078 { 13079 int ac = (ctx->opcode >> 11) & 0x03; 13080 tcg_gen_movi_tl(t0, ac); 13081 gen_helper_dshilo(v1_t, t0, tcg_env); 13082 break; 13083 } 13084 case OPC_DEXTP: 13085 tcg_gen_movi_tl(t0, v2); 13086 tcg_gen_movi_tl(t1, v1); 13087 13088 gen_helper_dextp(cpu_gpr[ret], t0, t1, tcg_env); 13089 break; 13090 case OPC_DEXTPV: 13091 tcg_gen_movi_tl(t0, v2); 13092 gen_helper_dextp(cpu_gpr[ret], t0, v1_t, tcg_env); 13093 break; 13094 case OPC_DEXTPDP: 13095 tcg_gen_movi_tl(t0, v2); 13096 tcg_gen_movi_tl(t1, v1); 13097 gen_helper_dextpdp(cpu_gpr[ret], t0, t1, tcg_env); 13098 break; 13099 case OPC_DEXTPDPV: 13100 tcg_gen_movi_tl(t0, v2); 13101 gen_helper_dextpdp(cpu_gpr[ret], t0, v1_t, tcg_env); 13102 break; 13103 case OPC_DEXTR_L: 13104 tcg_gen_movi_tl(t0, v2); 13105 tcg_gen_movi_tl(t1, v1); 13106 gen_helper_dextr_l(cpu_gpr[ret], t0, t1, tcg_env); 13107 break; 13108 case OPC_DEXTR_R_L: 13109 tcg_gen_movi_tl(t0, v2); 13110 tcg_gen_movi_tl(t1, v1); 13111 gen_helper_dextr_r_l(cpu_gpr[ret], t0, t1, tcg_env); 13112 break; 13113 case OPC_DEXTR_RS_L: 13114 tcg_gen_movi_tl(t0, v2); 13115 tcg_gen_movi_tl(t1, v1); 13116 gen_helper_dextr_rs_l(cpu_gpr[ret], t0, t1, tcg_env); 13117 break; 13118 case OPC_DEXTR_W: 13119 tcg_gen_movi_tl(t0, v2); 13120 tcg_gen_movi_tl(t1, v1); 13121 gen_helper_dextr_w(cpu_gpr[ret], t0, t1, tcg_env); 13122 break; 13123 case OPC_DEXTR_R_W: 13124 tcg_gen_movi_tl(t0, v2); 13125 tcg_gen_movi_tl(t1, v1); 13126 gen_helper_dextr_r_w(cpu_gpr[ret], t0, t1, tcg_env); 13127 break; 13128 case OPC_DEXTR_RS_W: 13129 tcg_gen_movi_tl(t0, v2); 13130 tcg_gen_movi_tl(t1, v1); 13131 gen_helper_dextr_rs_w(cpu_gpr[ret], t0, t1, tcg_env); 13132 break; 13133 case OPC_DEXTR_S_H: 13134 tcg_gen_movi_tl(t0, v2); 13135 tcg_gen_movi_tl(t1, v1); 13136 gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, tcg_env); 13137 break; 13138 case OPC_DEXTRV_S_H: 13139 tcg_gen_movi_tl(t0, v2); 13140 gen_helper_dextr_s_h(cpu_gpr[ret], t0, v1_t, tcg_env); 13141 break; 13142 case OPC_DEXTRV_L: 13143 tcg_gen_movi_tl(t0, v2); 13144 gen_helper_dextr_l(cpu_gpr[ret], t0, v1_t, tcg_env); 13145 break; 13146 case OPC_DEXTRV_R_L: 13147 tcg_gen_movi_tl(t0, v2); 13148 gen_helper_dextr_r_l(cpu_gpr[ret], t0, v1_t, tcg_env); 13149 break; 13150 case OPC_DEXTRV_RS_L: 13151 tcg_gen_movi_tl(t0, v2); 13152 gen_helper_dextr_rs_l(cpu_gpr[ret], t0, v1_t, tcg_env); 13153 break; 13154 case OPC_DEXTRV_W: 13155 tcg_gen_movi_tl(t0, v2); 13156 gen_helper_dextr_w(cpu_gpr[ret], t0, v1_t, tcg_env); 13157 break; 13158 case OPC_DEXTRV_R_W: 13159 tcg_gen_movi_tl(t0, v2); 13160 gen_helper_dextr_r_w(cpu_gpr[ret], t0, v1_t, tcg_env); 13161 break; 13162 case OPC_DEXTRV_RS_W: 13163 tcg_gen_movi_tl(t0, v2); 13164 gen_helper_dextr_rs_w(cpu_gpr[ret], t0, v1_t, tcg_env); 13165 break; 13166 } 13167 break; 13168 #endif 13169 } 13170 } 13171 13172 /* End MIPSDSP functions. */ 13173 13174 static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) 13175 { 13176 int rs, rt, rd, sa; 13177 uint32_t op1, op2; 13178 13179 rs = (ctx->opcode >> 21) & 0x1f; 13180 rt = (ctx->opcode >> 16) & 0x1f; 13181 rd = (ctx->opcode >> 11) & 0x1f; 13182 sa = (ctx->opcode >> 6) & 0x1f; 13183 13184 op1 = MASK_SPECIAL(ctx->opcode); 13185 switch (op1) { 13186 case OPC_MULT: 13187 case OPC_MULTU: 13188 case OPC_DIV: 13189 case OPC_DIVU: 13190 op2 = MASK_R6_MULDIV(ctx->opcode); 13191 switch (op2) { 13192 case R6_OPC_MUL: 13193 case R6_OPC_MUH: 13194 case R6_OPC_MULU: 13195 case R6_OPC_MUHU: 13196 case R6_OPC_DIV: 13197 case R6_OPC_MOD: 13198 case R6_OPC_DIVU: 13199 case R6_OPC_MODU: 13200 gen_r6_muldiv(ctx, op2, rd, rs, rt); 13201 break; 13202 default: 13203 MIPS_INVAL("special_r6 muldiv"); 13204 gen_reserved_instruction(ctx); 13205 break; 13206 } 13207 break; 13208 case OPC_SELEQZ: 13209 case OPC_SELNEZ: 13210 gen_cond_move(ctx, op1, rd, rs, rt); 13211 break; 13212 case R6_OPC_CLO: 13213 case R6_OPC_CLZ: 13214 if (rt == 0 && sa == 1) { 13215 /* 13216 * Major opcode and function field is shared with preR6 MFHI/MTHI. 13217 * We need additionally to check other fields. 13218 */ 13219 gen_cl(ctx, op1, rd, rs); 13220 } else { 13221 gen_reserved_instruction(ctx); 13222 } 13223 break; 13224 case R6_OPC_SDBBP: 13225 if (is_uhi(ctx, extract32(ctx->opcode, 6, 20))) { 13226 ctx->base.is_jmp = DISAS_SEMIHOST; 13227 } else { 13228 if (ctx->hflags & MIPS_HFLAG_SBRI) { 13229 gen_reserved_instruction(ctx); 13230 } else { 13231 generate_exception_end(ctx, EXCP_DBp); 13232 } 13233 } 13234 break; 13235 #if defined(TARGET_MIPS64) 13236 case R6_OPC_DCLO: 13237 case R6_OPC_DCLZ: 13238 if (rt == 0 && sa == 1) { 13239 /* 13240 * Major opcode and function field is shared with preR6 MFHI/MTHI. 13241 * We need additionally to check other fields. 13242 */ 13243 check_mips_64(ctx); 13244 gen_cl(ctx, op1, rd, rs); 13245 } else { 13246 gen_reserved_instruction(ctx); 13247 } 13248 break; 13249 case OPC_DMULT: 13250 case OPC_DMULTU: 13251 case OPC_DDIV: 13252 case OPC_DDIVU: 13253 13254 op2 = MASK_R6_MULDIV(ctx->opcode); 13255 switch (op2) { 13256 case R6_OPC_DMUL: 13257 case R6_OPC_DMUH: 13258 case R6_OPC_DMULU: 13259 case R6_OPC_DMUHU: 13260 case R6_OPC_DDIV: 13261 case R6_OPC_DMOD: 13262 case R6_OPC_DDIVU: 13263 case R6_OPC_DMODU: 13264 check_mips_64(ctx); 13265 gen_r6_muldiv(ctx, op2, rd, rs, rt); 13266 break; 13267 default: 13268 MIPS_INVAL("special_r6 muldiv"); 13269 gen_reserved_instruction(ctx); 13270 break; 13271 } 13272 break; 13273 #endif 13274 default: /* Invalid */ 13275 MIPS_INVAL("special_r6"); 13276 gen_reserved_instruction(ctx); 13277 break; 13278 } 13279 } 13280 13281 static void decode_opc_special_tx79(CPUMIPSState *env, DisasContext *ctx) 13282 { 13283 int rs = extract32(ctx->opcode, 21, 5); 13284 int rt = extract32(ctx->opcode, 16, 5); 13285 int rd = extract32(ctx->opcode, 11, 5); 13286 uint32_t op1 = MASK_SPECIAL(ctx->opcode); 13287 13288 switch (op1) { 13289 case OPC_MOVN: /* Conditional move */ 13290 case OPC_MOVZ: 13291 gen_cond_move(ctx, op1, rd, rs, rt); 13292 break; 13293 case OPC_MFHI: /* Move from HI/LO */ 13294 case OPC_MFLO: 13295 gen_HILO(ctx, op1, 0, rd); 13296 break; 13297 case OPC_MTHI: 13298 case OPC_MTLO: /* Move to HI/LO */ 13299 gen_HILO(ctx, op1, 0, rs); 13300 break; 13301 case OPC_MULT: 13302 case OPC_MULTU: 13303 gen_mul_txx9(ctx, op1, rd, rs, rt); 13304 break; 13305 case OPC_DIV: 13306 case OPC_DIVU: 13307 gen_muldiv(ctx, op1, 0, rs, rt); 13308 break; 13309 #if defined(TARGET_MIPS64) 13310 case OPC_DMULT: 13311 case OPC_DMULTU: 13312 case OPC_DDIV: 13313 case OPC_DDIVU: 13314 check_insn_opc_user_only(ctx, INSN_R5900); 13315 gen_muldiv(ctx, op1, 0, rs, rt); 13316 break; 13317 #endif 13318 case OPC_JR: 13319 gen_compute_branch(ctx, op1, 4, rs, 0, 0, 4); 13320 break; 13321 default: /* Invalid */ 13322 MIPS_INVAL("special_tx79"); 13323 gen_reserved_instruction(ctx); 13324 break; 13325 } 13326 } 13327 13328 static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) 13329 { 13330 int rs, rt, rd; 13331 uint32_t op1; 13332 13333 rs = (ctx->opcode >> 21) & 0x1f; 13334 rt = (ctx->opcode >> 16) & 0x1f; 13335 rd = (ctx->opcode >> 11) & 0x1f; 13336 13337 op1 = MASK_SPECIAL(ctx->opcode); 13338 switch (op1) { 13339 case OPC_MOVN: /* Conditional move */ 13340 case OPC_MOVZ: 13341 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | 13342 INSN_LOONGSON2E | INSN_LOONGSON2F); 13343 gen_cond_move(ctx, op1, rd, rs, rt); 13344 break; 13345 case OPC_MFHI: /* Move from HI/LO */ 13346 case OPC_MFLO: 13347 gen_HILO(ctx, op1, rs & 3, rd); 13348 break; 13349 case OPC_MTHI: 13350 case OPC_MTLO: /* Move to HI/LO */ 13351 gen_HILO(ctx, op1, rd & 3, rs); 13352 break; 13353 case OPC_MOVCI: 13354 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); 13355 if (env->CP0_Config1 & (1 << CP0C1_FP)) { 13356 check_cp1_enabled(ctx); 13357 gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7, 13358 (ctx->opcode >> 16) & 1); 13359 } else { 13360 generate_exception_err(ctx, EXCP_CpU, 1); 13361 } 13362 break; 13363 case OPC_MULT: 13364 case OPC_MULTU: 13365 gen_muldiv(ctx, op1, rd & 3, rs, rt); 13366 break; 13367 case OPC_DIV: 13368 case OPC_DIVU: 13369 gen_muldiv(ctx, op1, 0, rs, rt); 13370 break; 13371 #if defined(TARGET_MIPS64) 13372 case OPC_DMULT: 13373 case OPC_DMULTU: 13374 case OPC_DDIV: 13375 case OPC_DDIVU: 13376 check_insn(ctx, ISA_MIPS3); 13377 check_mips_64(ctx); 13378 gen_muldiv(ctx, op1, 0, rs, rt); 13379 break; 13380 #endif 13381 case OPC_JR: 13382 gen_compute_branch(ctx, op1, 4, rs, 0, 0, 4); 13383 break; 13384 case OPC_SPIM: 13385 #ifdef MIPS_STRICT_STANDARD 13386 MIPS_INVAL("SPIM"); 13387 gen_reserved_instruction(ctx); 13388 #else 13389 /* Implemented as RI exception for now. */ 13390 MIPS_INVAL("spim (unofficial)"); 13391 gen_reserved_instruction(ctx); 13392 #endif 13393 break; 13394 default: /* Invalid */ 13395 MIPS_INVAL("special_legacy"); 13396 gen_reserved_instruction(ctx); 13397 break; 13398 } 13399 } 13400 13401 static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) 13402 { 13403 int rs, rt, rd, sa; 13404 uint32_t op1; 13405 13406 rs = (ctx->opcode >> 21) & 0x1f; 13407 rt = (ctx->opcode >> 16) & 0x1f; 13408 rd = (ctx->opcode >> 11) & 0x1f; 13409 sa = (ctx->opcode >> 6) & 0x1f; 13410 13411 op1 = MASK_SPECIAL(ctx->opcode); 13412 switch (op1) { 13413 case OPC_SLL: /* Shift with immediate */ 13414 if (sa == 5 && rd == 0 && 13415 rs == 0 && rt == 0) { /* PAUSE */ 13416 if ((ctx->insn_flags & ISA_MIPS_R6) && 13417 (ctx->hflags & MIPS_HFLAG_BMASK)) { 13418 gen_reserved_instruction(ctx); 13419 break; 13420 } 13421 } 13422 /* Fallthrough */ 13423 case OPC_SRA: 13424 gen_shift_imm(ctx, op1, rd, rt, sa); 13425 break; 13426 case OPC_SRL: 13427 switch ((ctx->opcode >> 21) & 0x1f) { 13428 case 1: 13429 /* rotr is decoded as srl on non-R2 CPUs */ 13430 if (ctx->insn_flags & ISA_MIPS_R2) { 13431 op1 = OPC_ROTR; 13432 } 13433 /* Fallthrough */ 13434 case 0: 13435 gen_shift_imm(ctx, op1, rd, rt, sa); 13436 break; 13437 default: 13438 gen_reserved_instruction(ctx); 13439 break; 13440 } 13441 break; 13442 case OPC_ADD: 13443 case OPC_ADDU: 13444 case OPC_SUB: 13445 case OPC_SUBU: 13446 gen_arith(ctx, op1, rd, rs, rt); 13447 break; 13448 case OPC_SLLV: /* Shifts */ 13449 case OPC_SRAV: 13450 gen_shift(ctx, op1, rd, rs, rt); 13451 break; 13452 case OPC_SRLV: 13453 switch ((ctx->opcode >> 6) & 0x1f) { 13454 case 1: 13455 /* rotrv is decoded as srlv on non-R2 CPUs */ 13456 if (ctx->insn_flags & ISA_MIPS_R2) { 13457 op1 = OPC_ROTRV; 13458 } 13459 /* Fallthrough */ 13460 case 0: 13461 gen_shift(ctx, op1, rd, rs, rt); 13462 break; 13463 default: 13464 gen_reserved_instruction(ctx); 13465 break; 13466 } 13467 break; 13468 case OPC_SLT: /* Set on less than */ 13469 case OPC_SLTU: 13470 gen_slt(ctx, op1, rd, rs, rt); 13471 break; 13472 case OPC_AND: /* Logic*/ 13473 case OPC_OR: 13474 case OPC_NOR: 13475 case OPC_XOR: 13476 gen_logic(ctx, op1, rd, rs, rt); 13477 break; 13478 case OPC_JALR: 13479 gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4); 13480 break; 13481 case OPC_TGE: /* Traps */ 13482 case OPC_TGEU: 13483 case OPC_TLT: 13484 case OPC_TLTU: 13485 case OPC_TEQ: 13486 case OPC_TNE: 13487 check_insn(ctx, ISA_MIPS2); 13488 gen_trap(ctx, op1, rs, rt, -1, extract32(ctx->opcode, 6, 10)); 13489 break; 13490 case OPC_PMON: 13491 /* Pmon entry point, also R4010 selsl */ 13492 #ifdef MIPS_STRICT_STANDARD 13493 MIPS_INVAL("PMON / selsl"); 13494 gen_reserved_instruction(ctx); 13495 #else 13496 gen_helper_pmon(tcg_env, tcg_constant_i32(sa)); 13497 #endif 13498 break; 13499 case OPC_SYSCALL: 13500 generate_exception_end(ctx, EXCP_SYSCALL); 13501 break; 13502 case OPC_BREAK: 13503 generate_exception_break(ctx, extract32(ctx->opcode, 6, 20)); 13504 break; 13505 case OPC_SYNC: 13506 check_insn(ctx, ISA_MIPS2); 13507 gen_sync(extract32(ctx->opcode, 6, 5)); 13508 break; 13509 13510 #if defined(TARGET_MIPS64) 13511 /* MIPS64 specific opcodes */ 13512 case OPC_DSLL: 13513 case OPC_DSRA: 13514 case OPC_DSLL32: 13515 case OPC_DSRA32: 13516 check_insn(ctx, ISA_MIPS3); 13517 check_mips_64(ctx); 13518 gen_shift_imm(ctx, op1, rd, rt, sa); 13519 break; 13520 case OPC_DSRL: 13521 switch ((ctx->opcode >> 21) & 0x1f) { 13522 case 1: 13523 /* drotr is decoded as dsrl on non-R2 CPUs */ 13524 if (ctx->insn_flags & ISA_MIPS_R2) { 13525 op1 = OPC_DROTR; 13526 } 13527 /* Fallthrough */ 13528 case 0: 13529 check_insn(ctx, ISA_MIPS3); 13530 check_mips_64(ctx); 13531 gen_shift_imm(ctx, op1, rd, rt, sa); 13532 break; 13533 default: 13534 gen_reserved_instruction(ctx); 13535 break; 13536 } 13537 break; 13538 case OPC_DSRL32: 13539 switch ((ctx->opcode >> 21) & 0x1f) { 13540 case 1: 13541 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */ 13542 if (ctx->insn_flags & ISA_MIPS_R2) { 13543 op1 = OPC_DROTR32; 13544 } 13545 /* Fallthrough */ 13546 case 0: 13547 check_insn(ctx, ISA_MIPS3); 13548 check_mips_64(ctx); 13549 gen_shift_imm(ctx, op1, rd, rt, sa); 13550 break; 13551 default: 13552 gen_reserved_instruction(ctx); 13553 break; 13554 } 13555 break; 13556 case OPC_DADD: 13557 case OPC_DADDU: 13558 case OPC_DSUB: 13559 case OPC_DSUBU: 13560 check_insn(ctx, ISA_MIPS3); 13561 check_mips_64(ctx); 13562 gen_arith(ctx, op1, rd, rs, rt); 13563 break; 13564 case OPC_DSLLV: 13565 case OPC_DSRAV: 13566 check_insn(ctx, ISA_MIPS3); 13567 check_mips_64(ctx); 13568 gen_shift(ctx, op1, rd, rs, rt); 13569 break; 13570 case OPC_DSRLV: 13571 switch ((ctx->opcode >> 6) & 0x1f) { 13572 case 1: 13573 /* drotrv is decoded as dsrlv on non-R2 CPUs */ 13574 if (ctx->insn_flags & ISA_MIPS_R2) { 13575 op1 = OPC_DROTRV; 13576 } 13577 /* Fallthrough */ 13578 case 0: 13579 check_insn(ctx, ISA_MIPS3); 13580 check_mips_64(ctx); 13581 gen_shift(ctx, op1, rd, rs, rt); 13582 break; 13583 default: 13584 gen_reserved_instruction(ctx); 13585 break; 13586 } 13587 break; 13588 #endif 13589 default: 13590 if (ctx->insn_flags & ISA_MIPS_R6) { 13591 decode_opc_special_r6(env, ctx); 13592 } else if (ctx->insn_flags & INSN_R5900) { 13593 decode_opc_special_tx79(env, ctx); 13594 } else { 13595 decode_opc_special_legacy(env, ctx); 13596 } 13597 } 13598 } 13599 13600 13601 static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) 13602 { 13603 int rs, rt, rd; 13604 uint32_t op1; 13605 13606 rs = (ctx->opcode >> 21) & 0x1f; 13607 rt = (ctx->opcode >> 16) & 0x1f; 13608 rd = (ctx->opcode >> 11) & 0x1f; 13609 13610 op1 = MASK_SPECIAL2(ctx->opcode); 13611 switch (op1) { 13612 case OPC_MADD: /* Multiply and add/sub */ 13613 case OPC_MADDU: 13614 case OPC_MSUB: 13615 case OPC_MSUBU: 13616 check_insn(ctx, ISA_MIPS_R1); 13617 gen_muldiv(ctx, op1, rd & 3, rs, rt); 13618 break; 13619 case OPC_MUL: 13620 gen_arith(ctx, op1, rd, rs, rt); 13621 break; 13622 case OPC_DIV_G_2F: 13623 case OPC_DIVU_G_2F: 13624 case OPC_MULT_G_2F: 13625 case OPC_MULTU_G_2F: 13626 case OPC_MOD_G_2F: 13627 case OPC_MODU_G_2F: 13628 check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); 13629 gen_loongson_integer(ctx, op1, rd, rs, rt); 13630 break; 13631 case OPC_CLO: 13632 case OPC_CLZ: 13633 check_insn(ctx, ISA_MIPS_R1); 13634 gen_cl(ctx, op1, rd, rs); 13635 break; 13636 case OPC_SDBBP: 13637 if (is_uhi(ctx, extract32(ctx->opcode, 6, 20))) { 13638 ctx->base.is_jmp = DISAS_SEMIHOST; 13639 } else { 13640 /* 13641 * XXX: not clear which exception should be raised 13642 * when in debug mode... 13643 */ 13644 check_insn(ctx, ISA_MIPS_R1); 13645 generate_exception_end(ctx, EXCP_DBp); 13646 } 13647 break; 13648 #if defined(TARGET_MIPS64) 13649 case OPC_DCLO: 13650 case OPC_DCLZ: 13651 check_insn(ctx, ISA_MIPS_R1); 13652 check_mips_64(ctx); 13653 gen_cl(ctx, op1, rd, rs); 13654 break; 13655 case OPC_DMULT_G_2F: 13656 case OPC_DMULTU_G_2F: 13657 case OPC_DDIV_G_2F: 13658 case OPC_DDIVU_G_2F: 13659 case OPC_DMOD_G_2F: 13660 case OPC_DMODU_G_2F: 13661 check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); 13662 gen_loongson_integer(ctx, op1, rd, rs, rt); 13663 break; 13664 #endif 13665 default: /* Invalid */ 13666 MIPS_INVAL("special2_legacy"); 13667 gen_reserved_instruction(ctx); 13668 break; 13669 } 13670 } 13671 13672 static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) 13673 { 13674 int rs, rt, rd, sa; 13675 uint32_t op1, op2; 13676 int16_t imm; 13677 13678 rs = (ctx->opcode >> 21) & 0x1f; 13679 rt = (ctx->opcode >> 16) & 0x1f; 13680 rd = (ctx->opcode >> 11) & 0x1f; 13681 sa = (ctx->opcode >> 6) & 0x1f; 13682 imm = (int16_t)ctx->opcode >> 7; 13683 13684 op1 = MASK_SPECIAL3(ctx->opcode); 13685 switch (op1) { 13686 case R6_OPC_PREF: 13687 if (rt >= 24) { 13688 /* hint codes 24-31 are reserved and signal RI */ 13689 gen_reserved_instruction(ctx); 13690 } 13691 /* Treat as NOP. */ 13692 break; 13693 case R6_OPC_CACHE: 13694 check_cp0_enabled(ctx); 13695 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { 13696 gen_cache_operation(ctx, rt, rs, imm); 13697 } 13698 break; 13699 case R6_OPC_SC: 13700 gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, false); 13701 break; 13702 case R6_OPC_LL: 13703 gen_ld(ctx, op1, rt, rs, imm); 13704 break; 13705 case OPC_BSHFL: 13706 { 13707 if (rd == 0) { 13708 /* Treat as NOP. */ 13709 break; 13710 } 13711 op2 = MASK_BSHFL(ctx->opcode); 13712 switch (op2) { 13713 case OPC_ALIGN: 13714 case OPC_ALIGN_1: 13715 case OPC_ALIGN_2: 13716 case OPC_ALIGN_3: 13717 gen_align(ctx, 32, rd, rs, rt, sa & 3); 13718 break; 13719 case OPC_BITSWAP: 13720 gen_bitswap(ctx, op2, rd, rt); 13721 break; 13722 } 13723 } 13724 break; 13725 #ifndef CONFIG_USER_ONLY 13726 case OPC_GINV: 13727 if (unlikely(ctx->gi <= 1)) { 13728 gen_reserved_instruction(ctx); 13729 } 13730 check_cp0_enabled(ctx); 13731 switch ((ctx->opcode >> 6) & 3) { 13732 case 0: /* GINVI */ 13733 /* Treat as NOP. */ 13734 break; 13735 case 2: /* GINVT */ 13736 gen_helper_0e1i(ginvt, cpu_gpr[rs], extract32(ctx->opcode, 8, 2)); 13737 break; 13738 default: 13739 gen_reserved_instruction(ctx); 13740 break; 13741 } 13742 break; 13743 #endif 13744 #if defined(TARGET_MIPS64) 13745 case R6_OPC_SCD: 13746 gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_UQ, false); 13747 break; 13748 case R6_OPC_LLD: 13749 gen_ld(ctx, op1, rt, rs, imm); 13750 break; 13751 case OPC_DBSHFL: 13752 check_mips_64(ctx); 13753 { 13754 if (rd == 0) { 13755 /* Treat as NOP. */ 13756 break; 13757 } 13758 op2 = MASK_DBSHFL(ctx->opcode); 13759 switch (op2) { 13760 case OPC_DALIGN: 13761 case OPC_DALIGN_1: 13762 case OPC_DALIGN_2: 13763 case OPC_DALIGN_3: 13764 case OPC_DALIGN_4: 13765 case OPC_DALIGN_5: 13766 case OPC_DALIGN_6: 13767 case OPC_DALIGN_7: 13768 gen_align(ctx, 64, rd, rs, rt, sa & 7); 13769 break; 13770 case OPC_DBITSWAP: 13771 gen_bitswap(ctx, op2, rd, rt); 13772 break; 13773 } 13774 13775 } 13776 break; 13777 #endif 13778 default: /* Invalid */ 13779 MIPS_INVAL("special3_r6"); 13780 gen_reserved_instruction(ctx); 13781 break; 13782 } 13783 } 13784 13785 static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) 13786 { 13787 int rs, rt, rd; 13788 uint32_t op1, op2; 13789 13790 rs = (ctx->opcode >> 21) & 0x1f; 13791 rt = (ctx->opcode >> 16) & 0x1f; 13792 rd = (ctx->opcode >> 11) & 0x1f; 13793 13794 op1 = MASK_SPECIAL3(ctx->opcode); 13795 switch (op1) { 13796 case OPC_DIV_G_2E: 13797 case OPC_DIVU_G_2E: 13798 case OPC_MOD_G_2E: 13799 case OPC_MODU_G_2E: 13800 case OPC_MULT_G_2E: 13801 case OPC_MULTU_G_2E: 13802 /* 13803 * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have 13804 * the same mask and op1. 13805 */ 13806 if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MUL_PH_DSP)) { 13807 op2 = MASK_ADDUH_QB(ctx->opcode); 13808 switch (op2) { 13809 case OPC_ADDUH_QB: 13810 case OPC_ADDUH_R_QB: 13811 case OPC_ADDQH_PH: 13812 case OPC_ADDQH_R_PH: 13813 case OPC_ADDQH_W: 13814 case OPC_ADDQH_R_W: 13815 case OPC_SUBUH_QB: 13816 case OPC_SUBUH_R_QB: 13817 case OPC_SUBQH_PH: 13818 case OPC_SUBQH_R_PH: 13819 case OPC_SUBQH_W: 13820 case OPC_SUBQH_R_W: 13821 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 13822 break; 13823 case OPC_MUL_PH: 13824 case OPC_MUL_S_PH: 13825 case OPC_MULQ_S_W: 13826 case OPC_MULQ_RS_W: 13827 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1); 13828 break; 13829 default: 13830 MIPS_INVAL("MASK ADDUH.QB"); 13831 gen_reserved_instruction(ctx); 13832 break; 13833 } 13834 } else if (ctx->insn_flags & INSN_LOONGSON2E) { 13835 gen_loongson_integer(ctx, op1, rd, rs, rt); 13836 } else { 13837 gen_reserved_instruction(ctx); 13838 } 13839 break; 13840 case OPC_LX_DSP: 13841 op2 = MASK_LX(ctx->opcode); 13842 switch (op2) { 13843 #if defined(TARGET_MIPS64) 13844 case OPC_LDX: 13845 #endif 13846 case OPC_LBUX: 13847 case OPC_LHX: 13848 case OPC_LWX: 13849 gen_mips_lx(ctx, op2, rd, rs, rt); 13850 break; 13851 default: /* Invalid */ 13852 MIPS_INVAL("MASK LX"); 13853 gen_reserved_instruction(ctx); 13854 break; 13855 } 13856 break; 13857 case OPC_ABSQ_S_PH_DSP: 13858 op2 = MASK_ABSQ_S_PH(ctx->opcode); 13859 switch (op2) { 13860 case OPC_ABSQ_S_QB: 13861 case OPC_ABSQ_S_PH: 13862 case OPC_ABSQ_S_W: 13863 case OPC_PRECEQ_W_PHL: 13864 case OPC_PRECEQ_W_PHR: 13865 case OPC_PRECEQU_PH_QBL: 13866 case OPC_PRECEQU_PH_QBR: 13867 case OPC_PRECEQU_PH_QBLA: 13868 case OPC_PRECEQU_PH_QBRA: 13869 case OPC_PRECEU_PH_QBL: 13870 case OPC_PRECEU_PH_QBR: 13871 case OPC_PRECEU_PH_QBLA: 13872 case OPC_PRECEU_PH_QBRA: 13873 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 13874 break; 13875 case OPC_BITREV: 13876 case OPC_REPL_QB: 13877 case OPC_REPLV_QB: 13878 case OPC_REPL_PH: 13879 case OPC_REPLV_PH: 13880 gen_mipsdsp_bitinsn(ctx, op1, op2, rd, rt); 13881 break; 13882 default: 13883 MIPS_INVAL("MASK ABSQ_S.PH"); 13884 gen_reserved_instruction(ctx); 13885 break; 13886 } 13887 break; 13888 case OPC_ADDU_QB_DSP: 13889 op2 = MASK_ADDU_QB(ctx->opcode); 13890 switch (op2) { 13891 case OPC_ADDQ_PH: 13892 case OPC_ADDQ_S_PH: 13893 case OPC_ADDQ_S_W: 13894 case OPC_ADDU_QB: 13895 case OPC_ADDU_S_QB: 13896 case OPC_ADDU_PH: 13897 case OPC_ADDU_S_PH: 13898 case OPC_SUBQ_PH: 13899 case OPC_SUBQ_S_PH: 13900 case OPC_SUBQ_S_W: 13901 case OPC_SUBU_QB: 13902 case OPC_SUBU_S_QB: 13903 case OPC_SUBU_PH: 13904 case OPC_SUBU_S_PH: 13905 case OPC_ADDSC: 13906 case OPC_ADDWC: 13907 case OPC_MODSUB: 13908 case OPC_RADDU_W_QB: 13909 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 13910 break; 13911 case OPC_MULEU_S_PH_QBL: 13912 case OPC_MULEU_S_PH_QBR: 13913 case OPC_MULQ_RS_PH: 13914 case OPC_MULEQ_S_W_PHL: 13915 case OPC_MULEQ_S_W_PHR: 13916 case OPC_MULQ_S_PH: 13917 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1); 13918 break; 13919 default: /* Invalid */ 13920 MIPS_INVAL("MASK ADDU.QB"); 13921 gen_reserved_instruction(ctx); 13922 break; 13923 13924 } 13925 break; 13926 case OPC_CMPU_EQ_QB_DSP: 13927 op2 = MASK_CMPU_EQ_QB(ctx->opcode); 13928 switch (op2) { 13929 case OPC_PRECR_SRA_PH_W: 13930 case OPC_PRECR_SRA_R_PH_W: 13931 gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd); 13932 break; 13933 case OPC_PRECR_QB_PH: 13934 case OPC_PRECRQ_QB_PH: 13935 case OPC_PRECRQ_PH_W: 13936 case OPC_PRECRQ_RS_PH_W: 13937 case OPC_PRECRQU_S_QB_PH: 13938 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 13939 break; 13940 case OPC_CMPU_EQ_QB: 13941 case OPC_CMPU_LT_QB: 13942 case OPC_CMPU_LE_QB: 13943 case OPC_CMP_EQ_PH: 13944 case OPC_CMP_LT_PH: 13945 case OPC_CMP_LE_PH: 13946 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0); 13947 break; 13948 case OPC_CMPGU_EQ_QB: 13949 case OPC_CMPGU_LT_QB: 13950 case OPC_CMPGU_LE_QB: 13951 case OPC_CMPGDU_EQ_QB: 13952 case OPC_CMPGDU_LT_QB: 13953 case OPC_CMPGDU_LE_QB: 13954 case OPC_PICK_QB: 13955 case OPC_PICK_PH: 13956 case OPC_PACKRL_PH: 13957 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1); 13958 break; 13959 default: /* Invalid */ 13960 MIPS_INVAL("MASK CMPU.EQ.QB"); 13961 gen_reserved_instruction(ctx); 13962 break; 13963 } 13964 break; 13965 case OPC_SHLL_QB_DSP: 13966 gen_mipsdsp_shift(ctx, op1, rd, rs, rt); 13967 break; 13968 case OPC_DPA_W_PH_DSP: 13969 op2 = MASK_DPA_W_PH(ctx->opcode); 13970 switch (op2) { 13971 case OPC_DPAU_H_QBL: 13972 case OPC_DPAU_H_QBR: 13973 case OPC_DPSU_H_QBL: 13974 case OPC_DPSU_H_QBR: 13975 case OPC_DPA_W_PH: 13976 case OPC_DPAX_W_PH: 13977 case OPC_DPAQ_S_W_PH: 13978 case OPC_DPAQX_S_W_PH: 13979 case OPC_DPAQX_SA_W_PH: 13980 case OPC_DPS_W_PH: 13981 case OPC_DPSX_W_PH: 13982 case OPC_DPSQ_S_W_PH: 13983 case OPC_DPSQX_S_W_PH: 13984 case OPC_DPSQX_SA_W_PH: 13985 case OPC_MULSAQ_S_W_PH: 13986 case OPC_DPAQ_SA_L_W: 13987 case OPC_DPSQ_SA_L_W: 13988 case OPC_MAQ_S_W_PHL: 13989 case OPC_MAQ_S_W_PHR: 13990 case OPC_MAQ_SA_W_PHL: 13991 case OPC_MAQ_SA_W_PHR: 13992 case OPC_MULSA_W_PH: 13993 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0); 13994 break; 13995 default: /* Invalid */ 13996 MIPS_INVAL("MASK DPAW.PH"); 13997 gen_reserved_instruction(ctx); 13998 break; 13999 } 14000 break; 14001 case OPC_INSV_DSP: 14002 op2 = MASK_INSV(ctx->opcode); 14003 switch (op2) { 14004 case OPC_INSV: 14005 check_dsp(ctx); 14006 { 14007 TCGv t0, t1; 14008 14009 if (rt == 0) { 14010 break; 14011 } 14012 14013 t0 = tcg_temp_new(); 14014 t1 = tcg_temp_new(); 14015 14016 gen_load_gpr(t0, rt); 14017 gen_load_gpr(t1, rs); 14018 14019 gen_helper_insv(cpu_gpr[rt], tcg_env, t1, t0); 14020 break; 14021 } 14022 default: /* Invalid */ 14023 MIPS_INVAL("MASK INSV"); 14024 gen_reserved_instruction(ctx); 14025 break; 14026 } 14027 break; 14028 case OPC_APPEND_DSP: 14029 gen_mipsdsp_append(env, ctx, op1, rt, rs, rd); 14030 break; 14031 case OPC_EXTR_W_DSP: 14032 op2 = MASK_EXTR_W(ctx->opcode); 14033 switch (op2) { 14034 case OPC_EXTR_W: 14035 case OPC_EXTR_R_W: 14036 case OPC_EXTR_RS_W: 14037 case OPC_EXTR_S_H: 14038 case OPC_EXTRV_S_H: 14039 case OPC_EXTRV_W: 14040 case OPC_EXTRV_R_W: 14041 case OPC_EXTRV_RS_W: 14042 case OPC_EXTP: 14043 case OPC_EXTPV: 14044 case OPC_EXTPDP: 14045 case OPC_EXTPDPV: 14046 gen_mipsdsp_accinsn(ctx, op1, op2, rt, rs, rd, 1); 14047 break; 14048 case OPC_RDDSP: 14049 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 1); 14050 break; 14051 case OPC_SHILO: 14052 case OPC_SHILOV: 14053 case OPC_MTHLIP: 14054 case OPC_WRDSP: 14055 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 0); 14056 break; 14057 default: /* Invalid */ 14058 MIPS_INVAL("MASK EXTR.W"); 14059 gen_reserved_instruction(ctx); 14060 break; 14061 } 14062 break; 14063 #if defined(TARGET_MIPS64) 14064 case OPC_DDIV_G_2E: 14065 case OPC_DDIVU_G_2E: 14066 case OPC_DMULT_G_2E: 14067 case OPC_DMULTU_G_2E: 14068 case OPC_DMOD_G_2E: 14069 case OPC_DMODU_G_2E: 14070 check_insn(ctx, INSN_LOONGSON2E); 14071 gen_loongson_integer(ctx, op1, rd, rs, rt); 14072 break; 14073 case OPC_ABSQ_S_QH_DSP: 14074 op2 = MASK_ABSQ_S_QH(ctx->opcode); 14075 switch (op2) { 14076 case OPC_PRECEQ_L_PWL: 14077 case OPC_PRECEQ_L_PWR: 14078 case OPC_PRECEQ_PW_QHL: 14079 case OPC_PRECEQ_PW_QHR: 14080 case OPC_PRECEQ_PW_QHLA: 14081 case OPC_PRECEQ_PW_QHRA: 14082 case OPC_PRECEQU_QH_OBL: 14083 case OPC_PRECEQU_QH_OBR: 14084 case OPC_PRECEQU_QH_OBLA: 14085 case OPC_PRECEQU_QH_OBRA: 14086 case OPC_PRECEU_QH_OBL: 14087 case OPC_PRECEU_QH_OBR: 14088 case OPC_PRECEU_QH_OBLA: 14089 case OPC_PRECEU_QH_OBRA: 14090 case OPC_ABSQ_S_OB: 14091 case OPC_ABSQ_S_PW: 14092 case OPC_ABSQ_S_QH: 14093 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 14094 break; 14095 case OPC_REPL_OB: 14096 case OPC_REPL_PW: 14097 case OPC_REPL_QH: 14098 case OPC_REPLV_OB: 14099 case OPC_REPLV_PW: 14100 case OPC_REPLV_QH: 14101 gen_mipsdsp_bitinsn(ctx, op1, op2, rd, rt); 14102 break; 14103 default: /* Invalid */ 14104 MIPS_INVAL("MASK ABSQ_S.QH"); 14105 gen_reserved_instruction(ctx); 14106 break; 14107 } 14108 break; 14109 case OPC_ADDU_OB_DSP: 14110 op2 = MASK_ADDU_OB(ctx->opcode); 14111 switch (op2) { 14112 case OPC_RADDU_L_OB: 14113 case OPC_SUBQ_PW: 14114 case OPC_SUBQ_S_PW: 14115 case OPC_SUBQ_QH: 14116 case OPC_SUBQ_S_QH: 14117 case OPC_SUBU_OB: 14118 case OPC_SUBU_S_OB: 14119 case OPC_SUBU_QH: 14120 case OPC_SUBU_S_QH: 14121 case OPC_SUBUH_OB: 14122 case OPC_SUBUH_R_OB: 14123 case OPC_ADDQ_PW: 14124 case OPC_ADDQ_S_PW: 14125 case OPC_ADDQ_QH: 14126 case OPC_ADDQ_S_QH: 14127 case OPC_ADDU_OB: 14128 case OPC_ADDU_S_OB: 14129 case OPC_ADDU_QH: 14130 case OPC_ADDU_S_QH: 14131 case OPC_ADDUH_OB: 14132 case OPC_ADDUH_R_OB: 14133 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 14134 break; 14135 case OPC_MULEQ_S_PW_QHL: 14136 case OPC_MULEQ_S_PW_QHR: 14137 case OPC_MULEU_S_QH_OBL: 14138 case OPC_MULEU_S_QH_OBR: 14139 case OPC_MULQ_RS_QH: 14140 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1); 14141 break; 14142 default: /* Invalid */ 14143 MIPS_INVAL("MASK ADDU.OB"); 14144 gen_reserved_instruction(ctx); 14145 break; 14146 } 14147 break; 14148 case OPC_CMPU_EQ_OB_DSP: 14149 op2 = MASK_CMPU_EQ_OB(ctx->opcode); 14150 switch (op2) { 14151 case OPC_PRECR_SRA_QH_PW: 14152 case OPC_PRECR_SRA_R_QH_PW: 14153 /* Return value is rt. */ 14154 gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd); 14155 break; 14156 case OPC_PRECR_OB_QH: 14157 case OPC_PRECRQ_OB_QH: 14158 case OPC_PRECRQ_PW_L: 14159 case OPC_PRECRQ_QH_PW: 14160 case OPC_PRECRQ_RS_QH_PW: 14161 case OPC_PRECRQU_S_OB_QH: 14162 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 14163 break; 14164 case OPC_CMPU_EQ_OB: 14165 case OPC_CMPU_LT_OB: 14166 case OPC_CMPU_LE_OB: 14167 case OPC_CMP_EQ_QH: 14168 case OPC_CMP_LT_QH: 14169 case OPC_CMP_LE_QH: 14170 case OPC_CMP_EQ_PW: 14171 case OPC_CMP_LT_PW: 14172 case OPC_CMP_LE_PW: 14173 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0); 14174 break; 14175 case OPC_CMPGDU_EQ_OB: 14176 case OPC_CMPGDU_LT_OB: 14177 case OPC_CMPGDU_LE_OB: 14178 case OPC_CMPGU_EQ_OB: 14179 case OPC_CMPGU_LT_OB: 14180 case OPC_CMPGU_LE_OB: 14181 case OPC_PACKRL_PW: 14182 case OPC_PICK_OB: 14183 case OPC_PICK_PW: 14184 case OPC_PICK_QH: 14185 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1); 14186 break; 14187 default: /* Invalid */ 14188 MIPS_INVAL("MASK CMPU_EQ.OB"); 14189 gen_reserved_instruction(ctx); 14190 break; 14191 } 14192 break; 14193 case OPC_DAPPEND_DSP: 14194 gen_mipsdsp_append(env, ctx, op1, rt, rs, rd); 14195 break; 14196 case OPC_DEXTR_W_DSP: 14197 op2 = MASK_DEXTR_W(ctx->opcode); 14198 switch (op2) { 14199 case OPC_DEXTP: 14200 case OPC_DEXTPDP: 14201 case OPC_DEXTPDPV: 14202 case OPC_DEXTPV: 14203 case OPC_DEXTR_L: 14204 case OPC_DEXTR_R_L: 14205 case OPC_DEXTR_RS_L: 14206 case OPC_DEXTR_W: 14207 case OPC_DEXTR_R_W: 14208 case OPC_DEXTR_RS_W: 14209 case OPC_DEXTR_S_H: 14210 case OPC_DEXTRV_L: 14211 case OPC_DEXTRV_R_L: 14212 case OPC_DEXTRV_RS_L: 14213 case OPC_DEXTRV_S_H: 14214 case OPC_DEXTRV_W: 14215 case OPC_DEXTRV_R_W: 14216 case OPC_DEXTRV_RS_W: 14217 gen_mipsdsp_accinsn(ctx, op1, op2, rt, rs, rd, 1); 14218 break; 14219 case OPC_DMTHLIP: 14220 case OPC_DSHILO: 14221 case OPC_DSHILOV: 14222 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 0); 14223 break; 14224 default: /* Invalid */ 14225 MIPS_INVAL("MASK EXTR.W"); 14226 gen_reserved_instruction(ctx); 14227 break; 14228 } 14229 break; 14230 case OPC_DPAQ_W_QH_DSP: 14231 op2 = MASK_DPAQ_W_QH(ctx->opcode); 14232 switch (op2) { 14233 case OPC_DPAU_H_OBL: 14234 case OPC_DPAU_H_OBR: 14235 case OPC_DPSU_H_OBL: 14236 case OPC_DPSU_H_OBR: 14237 case OPC_DPA_W_QH: 14238 case OPC_DPAQ_S_W_QH: 14239 case OPC_DPS_W_QH: 14240 case OPC_DPSQ_S_W_QH: 14241 case OPC_MULSAQ_S_W_QH: 14242 case OPC_DPAQ_SA_L_PW: 14243 case OPC_DPSQ_SA_L_PW: 14244 case OPC_MULSAQ_S_L_PW: 14245 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0); 14246 break; 14247 case OPC_MAQ_S_W_QHLL: 14248 case OPC_MAQ_S_W_QHLR: 14249 case OPC_MAQ_S_W_QHRL: 14250 case OPC_MAQ_S_W_QHRR: 14251 case OPC_MAQ_SA_W_QHLL: 14252 case OPC_MAQ_SA_W_QHLR: 14253 case OPC_MAQ_SA_W_QHRL: 14254 case OPC_MAQ_SA_W_QHRR: 14255 case OPC_MAQ_S_L_PWL: 14256 case OPC_MAQ_S_L_PWR: 14257 case OPC_DMADD: 14258 case OPC_DMADDU: 14259 case OPC_DMSUB: 14260 case OPC_DMSUBU: 14261 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0); 14262 break; 14263 default: /* Invalid */ 14264 MIPS_INVAL("MASK DPAQ.W.QH"); 14265 gen_reserved_instruction(ctx); 14266 break; 14267 } 14268 break; 14269 case OPC_DINSV_DSP: 14270 op2 = MASK_INSV(ctx->opcode); 14271 switch (op2) { 14272 case OPC_DINSV: 14273 { 14274 TCGv t0, t1; 14275 14276 check_dsp(ctx); 14277 14278 if (rt == 0) { 14279 break; 14280 } 14281 14282 t0 = tcg_temp_new(); 14283 t1 = tcg_temp_new(); 14284 14285 gen_load_gpr(t0, rt); 14286 gen_load_gpr(t1, rs); 14287 14288 gen_helper_dinsv(cpu_gpr[rt], tcg_env, t1, t0); 14289 break; 14290 } 14291 default: /* Invalid */ 14292 MIPS_INVAL("MASK DINSV"); 14293 gen_reserved_instruction(ctx); 14294 break; 14295 } 14296 break; 14297 case OPC_SHLL_OB_DSP: 14298 gen_mipsdsp_shift(ctx, op1, rd, rs, rt); 14299 break; 14300 #endif 14301 default: /* Invalid */ 14302 MIPS_INVAL("special3_legacy"); 14303 gen_reserved_instruction(ctx); 14304 break; 14305 } 14306 } 14307 14308 14309 #if defined(TARGET_MIPS64) 14310 14311 static void decode_mmi(CPUMIPSState *env, DisasContext *ctx) 14312 { 14313 uint32_t opc = MASK_MMI(ctx->opcode); 14314 int rs = extract32(ctx->opcode, 21, 5); 14315 int rt = extract32(ctx->opcode, 16, 5); 14316 int rd = extract32(ctx->opcode, 11, 5); 14317 14318 switch (opc) { 14319 case MMI_OPC_MULT1: 14320 case MMI_OPC_MULTU1: 14321 case MMI_OPC_MADD: 14322 case MMI_OPC_MADDU: 14323 case MMI_OPC_MADD1: 14324 case MMI_OPC_MADDU1: 14325 gen_mul_txx9(ctx, opc, rd, rs, rt); 14326 break; 14327 case MMI_OPC_DIV1: 14328 case MMI_OPC_DIVU1: 14329 gen_div1_tx79(ctx, opc, rs, rt); 14330 break; 14331 default: 14332 MIPS_INVAL("TX79 MMI class"); 14333 gen_reserved_instruction(ctx); 14334 break; 14335 } 14336 } 14337 14338 static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset) 14339 { 14340 gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */ 14341 } 14342 14343 /* 14344 * The TX79-specific instruction Store Quadword 14345 * 14346 * +--------+-------+-------+------------------------+ 14347 * | 011111 | base | rt | offset | SQ 14348 * +--------+-------+-------+------------------------+ 14349 * 6 5 5 16 14350 * 14351 * has the same opcode as the Read Hardware Register instruction 14352 * 14353 * +--------+-------+-------+-------+-------+--------+ 14354 * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR 14355 * +--------+-------+-------+-------+-------+--------+ 14356 * 6 5 5 5 5 6 14357 * 14358 * that is required, trapped and emulated by the Linux kernel. However, all 14359 * RDHWR encodings yield address error exceptions on the TX79 since the SQ 14360 * offset is odd. Therefore all valid SQ instructions can execute normally. 14361 * In user mode, QEMU must verify the upper and lower 11 bits to distinguish 14362 * between SQ and RDHWR, as the Linux kernel does. 14363 */ 14364 static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx) 14365 { 14366 int base = extract32(ctx->opcode, 21, 5); 14367 int rt = extract32(ctx->opcode, 16, 5); 14368 int offset = extract32(ctx->opcode, 0, 16); 14369 14370 #ifdef CONFIG_USER_ONLY 14371 uint32_t op1 = MASK_SPECIAL3(ctx->opcode); 14372 uint32_t op2 = extract32(ctx->opcode, 6, 5); 14373 14374 if (base == 0 && op2 == 0 && op1 == OPC_RDHWR) { 14375 int rd = extract32(ctx->opcode, 11, 5); 14376 14377 gen_rdhwr(ctx, rt, rd, 0); 14378 return; 14379 } 14380 #endif 14381 14382 gen_mmi_sq(ctx, base, rt, offset); 14383 } 14384 14385 #endif 14386 14387 static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) 14388 { 14389 int rs, rt, rd, sa; 14390 uint32_t op1, op2; 14391 int16_t imm; 14392 14393 rs = (ctx->opcode >> 21) & 0x1f; 14394 rt = (ctx->opcode >> 16) & 0x1f; 14395 rd = (ctx->opcode >> 11) & 0x1f; 14396 sa = (ctx->opcode >> 6) & 0x1f; 14397 imm = sextract32(ctx->opcode, 7, 9); 14398 14399 op1 = MASK_SPECIAL3(ctx->opcode); 14400 14401 /* 14402 * EVA loads and stores overlap Loongson 2E instructions decoded by 14403 * decode_opc_special3_legacy(), so be careful to allow their decoding when 14404 * EVA is absent. 14405 */ 14406 if (ctx->eva) { 14407 switch (op1) { 14408 case OPC_LWLE: 14409 case OPC_LWRE: 14410 case OPC_LBUE: 14411 case OPC_LHUE: 14412 case OPC_LBE: 14413 case OPC_LHE: 14414 case OPC_LLE: 14415 case OPC_LWE: 14416 check_cp0_enabled(ctx); 14417 gen_ld(ctx, op1, rt, rs, imm); 14418 return; 14419 case OPC_SWLE: 14420 case OPC_SWRE: 14421 case OPC_SBE: 14422 case OPC_SHE: 14423 case OPC_SWE: 14424 check_cp0_enabled(ctx); 14425 gen_st(ctx, op1, rt, rs, imm); 14426 return; 14427 case OPC_SCE: 14428 check_cp0_enabled(ctx); 14429 gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, true); 14430 return; 14431 case OPC_CACHEE: 14432 check_eva(ctx); 14433 check_cp0_enabled(ctx); 14434 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { 14435 gen_cache_operation(ctx, rt, rs, imm); 14436 } 14437 return; 14438 case OPC_PREFE: 14439 check_cp0_enabled(ctx); 14440 /* Treat as NOP. */ 14441 return; 14442 } 14443 } 14444 14445 switch (op1) { 14446 case OPC_EXT: 14447 case OPC_INS: 14448 check_insn(ctx, ISA_MIPS_R2); 14449 gen_bitops(ctx, op1, rt, rs, sa, rd); 14450 break; 14451 case OPC_BSHFL: 14452 op2 = MASK_BSHFL(ctx->opcode); 14453 switch (op2) { 14454 case OPC_ALIGN: 14455 case OPC_ALIGN_1: 14456 case OPC_ALIGN_2: 14457 case OPC_ALIGN_3: 14458 case OPC_BITSWAP: 14459 check_insn(ctx, ISA_MIPS_R6); 14460 decode_opc_special3_r6(env, ctx); 14461 break; 14462 default: 14463 check_insn(ctx, ISA_MIPS_R2); 14464 gen_bshfl(ctx, op2, rt, rd); 14465 break; 14466 } 14467 break; 14468 #if defined(TARGET_MIPS64) 14469 case OPC_DEXTM: 14470 case OPC_DEXTU: 14471 case OPC_DEXT: 14472 case OPC_DINSM: 14473 case OPC_DINSU: 14474 case OPC_DINS: 14475 check_insn(ctx, ISA_MIPS_R2); 14476 check_mips_64(ctx); 14477 gen_bitops(ctx, op1, rt, rs, sa, rd); 14478 break; 14479 case OPC_DBSHFL: 14480 op2 = MASK_DBSHFL(ctx->opcode); 14481 switch (op2) { 14482 case OPC_DALIGN: 14483 case OPC_DALIGN_1: 14484 case OPC_DALIGN_2: 14485 case OPC_DALIGN_3: 14486 case OPC_DALIGN_4: 14487 case OPC_DALIGN_5: 14488 case OPC_DALIGN_6: 14489 case OPC_DALIGN_7: 14490 case OPC_DBITSWAP: 14491 check_insn(ctx, ISA_MIPS_R6); 14492 decode_opc_special3_r6(env, ctx); 14493 break; 14494 default: 14495 check_insn(ctx, ISA_MIPS_R2); 14496 check_mips_64(ctx); 14497 op2 = MASK_DBSHFL(ctx->opcode); 14498 gen_bshfl(ctx, op2, rt, rd); 14499 break; 14500 } 14501 break; 14502 #endif 14503 case OPC_RDHWR: 14504 gen_rdhwr(ctx, rt, rd, extract32(ctx->opcode, 6, 3)); 14505 break; 14506 case OPC_FORK: 14507 check_mt(ctx); 14508 { 14509 TCGv t0 = tcg_temp_new(); 14510 TCGv t1 = tcg_temp_new(); 14511 14512 gen_load_gpr(t0, rt); 14513 gen_load_gpr(t1, rs); 14514 gen_helper_fork(t0, t1); 14515 } 14516 break; 14517 case OPC_YIELD: 14518 check_mt(ctx); 14519 { 14520 TCGv t0 = tcg_temp_new(); 14521 14522 gen_load_gpr(t0, rs); 14523 gen_helper_yield(t0, tcg_env, t0); 14524 gen_store_gpr(t0, rd); 14525 } 14526 break; 14527 default: 14528 if (ctx->insn_flags & ISA_MIPS_R6) { 14529 decode_opc_special3_r6(env, ctx); 14530 } else { 14531 decode_opc_special3_legacy(env, ctx); 14532 } 14533 } 14534 } 14535 14536 static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) 14537 { 14538 int32_t offset; 14539 int rs, rt, rd, sa; 14540 uint32_t op, op1; 14541 int16_t imm; 14542 14543 op = MASK_OP_MAJOR(ctx->opcode); 14544 rs = (ctx->opcode >> 21) & 0x1f; 14545 rt = (ctx->opcode >> 16) & 0x1f; 14546 rd = (ctx->opcode >> 11) & 0x1f; 14547 sa = (ctx->opcode >> 6) & 0x1f; 14548 imm = (int16_t)ctx->opcode; 14549 switch (op) { 14550 case OPC_SPECIAL: 14551 decode_opc_special(env, ctx); 14552 break; 14553 case OPC_SPECIAL2: 14554 #if defined(TARGET_MIPS64) 14555 if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) { 14556 decode_mmi(env, ctx); 14557 break; 14558 } 14559 #endif 14560 if (TARGET_LONG_BITS == 32 && (ctx->insn_flags & ASE_MXU)) { 14561 if (decode_ase_mxu(ctx, ctx->opcode)) { 14562 break; 14563 } 14564 } 14565 decode_opc_special2_legacy(env, ctx); 14566 break; 14567 case OPC_SPECIAL3: 14568 #if defined(TARGET_MIPS64) 14569 if (ctx->insn_flags & INSN_R5900) { 14570 decode_mmi_sq(env, ctx); /* MMI_OPC_SQ */ 14571 } else { 14572 decode_opc_special3(env, ctx); 14573 } 14574 #else 14575 decode_opc_special3(env, ctx); 14576 #endif 14577 break; 14578 case OPC_REGIMM: 14579 op1 = MASK_REGIMM(ctx->opcode); 14580 switch (op1) { 14581 case OPC_BLTZL: /* REGIMM branches */ 14582 case OPC_BGEZL: 14583 case OPC_BLTZALL: 14584 case OPC_BGEZALL: 14585 check_insn(ctx, ISA_MIPS2); 14586 check_insn_opc_removed(ctx, ISA_MIPS_R6); 14587 /* Fallthrough */ 14588 case OPC_BLTZ: 14589 case OPC_BGEZ: 14590 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); 14591 break; 14592 case OPC_BLTZAL: 14593 case OPC_BGEZAL: 14594 if (ctx->insn_flags & ISA_MIPS_R6) { 14595 if (rs == 0) { 14596 /* OPC_NAL, OPC_BAL */ 14597 gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4); 14598 } else { 14599 gen_reserved_instruction(ctx); 14600 } 14601 } else { 14602 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); 14603 } 14604 break; 14605 case OPC_TGEI: /* REGIMM traps */ 14606 case OPC_TGEIU: 14607 case OPC_TLTI: 14608 case OPC_TLTIU: 14609 case OPC_TEQI: 14610 case OPC_TNEI: 14611 check_insn(ctx, ISA_MIPS2); 14612 check_insn_opc_removed(ctx, ISA_MIPS_R6); 14613 gen_trap(ctx, op1, rs, -1, imm, 0); 14614 break; 14615 case OPC_SIGRIE: 14616 check_insn(ctx, ISA_MIPS_R6); 14617 gen_reserved_instruction(ctx); 14618 break; 14619 case OPC_SYNCI: 14620 check_insn(ctx, ISA_MIPS_R2); 14621 /* 14622 * Break the TB to be able to sync copied instructions 14623 * immediately. 14624 */ 14625 ctx->base.is_jmp = DISAS_STOP; 14626 break; 14627 case OPC_BPOSGE32: /* MIPS DSP branch */ 14628 #if defined(TARGET_MIPS64) 14629 case OPC_BPOSGE64: 14630 #endif 14631 check_dsp(ctx); 14632 gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2, 4); 14633 break; 14634 #if defined(TARGET_MIPS64) 14635 case OPC_DAHI: 14636 check_insn(ctx, ISA_MIPS_R6); 14637 check_mips_64(ctx); 14638 if (rs != 0) { 14639 tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 32); 14640 } 14641 break; 14642 case OPC_DATI: 14643 check_insn(ctx, ISA_MIPS_R6); 14644 check_mips_64(ctx); 14645 if (rs != 0) { 14646 tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 48); 14647 } 14648 break; 14649 #endif 14650 default: /* Invalid */ 14651 MIPS_INVAL("regimm"); 14652 gen_reserved_instruction(ctx); 14653 break; 14654 } 14655 break; 14656 case OPC_CP0: 14657 check_cp0_enabled(ctx); 14658 op1 = MASK_CP0(ctx->opcode); 14659 switch (op1) { 14660 case OPC_MFC0: 14661 case OPC_MTC0: 14662 case OPC_MFTR: 14663 case OPC_MTTR: 14664 case OPC_MFHC0: 14665 case OPC_MTHC0: 14666 #if defined(TARGET_MIPS64) 14667 case OPC_DMFC0: 14668 case OPC_DMTC0: 14669 #endif 14670 #ifndef CONFIG_USER_ONLY 14671 gen_cp0(env, ctx, op1, rt, rd); 14672 #endif /* !CONFIG_USER_ONLY */ 14673 break; 14674 case OPC_C0: 14675 case OPC_C0_1: 14676 case OPC_C0_2: 14677 case OPC_C0_3: 14678 case OPC_C0_4: 14679 case OPC_C0_5: 14680 case OPC_C0_6: 14681 case OPC_C0_7: 14682 case OPC_C0_8: 14683 case OPC_C0_9: 14684 case OPC_C0_A: 14685 case OPC_C0_B: 14686 case OPC_C0_C: 14687 case OPC_C0_D: 14688 case OPC_C0_E: 14689 case OPC_C0_F: 14690 #ifndef CONFIG_USER_ONLY 14691 gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd); 14692 #endif /* !CONFIG_USER_ONLY */ 14693 break; 14694 case OPC_MFMC0: 14695 #ifndef CONFIG_USER_ONLY 14696 { 14697 uint32_t op2; 14698 TCGv t0 = tcg_temp_new(); 14699 14700 op2 = MASK_MFMC0(ctx->opcode); 14701 switch (op2) { 14702 case OPC_DMT: 14703 check_cp0_mt(ctx); 14704 gen_helper_dmt(t0); 14705 gen_store_gpr(t0, rt); 14706 break; 14707 case OPC_EMT: 14708 check_cp0_mt(ctx); 14709 gen_helper_emt(t0); 14710 gen_store_gpr(t0, rt); 14711 break; 14712 case OPC_DVPE: 14713 check_cp0_mt(ctx); 14714 gen_helper_dvpe(t0, tcg_env); 14715 gen_store_gpr(t0, rt); 14716 break; 14717 case OPC_EVPE: 14718 check_cp0_mt(ctx); 14719 gen_helper_evpe(t0, tcg_env); 14720 gen_store_gpr(t0, rt); 14721 break; 14722 case OPC_DVP: 14723 check_insn(ctx, ISA_MIPS_R6); 14724 if (ctx->vp) { 14725 gen_helper_dvp(t0, tcg_env); 14726 gen_store_gpr(t0, rt); 14727 } 14728 break; 14729 case OPC_EVP: 14730 check_insn(ctx, ISA_MIPS_R6); 14731 if (ctx->vp) { 14732 gen_helper_evp(t0, tcg_env); 14733 gen_store_gpr(t0, rt); 14734 } 14735 break; 14736 case OPC_DI: 14737 check_insn(ctx, ISA_MIPS_R2); 14738 save_cpu_state(ctx, 1); 14739 gen_helper_di(t0, tcg_env); 14740 gen_store_gpr(t0, rt); 14741 /* 14742 * Stop translation as we may have switched 14743 * the execution mode. 14744 */ 14745 ctx->base.is_jmp = DISAS_STOP; 14746 break; 14747 case OPC_EI: 14748 check_insn(ctx, ISA_MIPS_R2); 14749 save_cpu_state(ctx, 1); 14750 gen_helper_ei(t0, tcg_env); 14751 gen_store_gpr(t0, rt); 14752 /* 14753 * DISAS_STOP isn't sufficient, we need to ensure we break 14754 * out of translated code to check for pending interrupts. 14755 */ 14756 gen_save_pc(ctx->base.pc_next + 4); 14757 ctx->base.is_jmp = DISAS_EXIT; 14758 break; 14759 default: /* Invalid */ 14760 MIPS_INVAL("mfmc0"); 14761 gen_reserved_instruction(ctx); 14762 break; 14763 } 14764 } 14765 #endif /* !CONFIG_USER_ONLY */ 14766 break; 14767 case OPC_RDPGPR: 14768 check_insn(ctx, ISA_MIPS_R2); 14769 gen_load_srsgpr(rt, rd); 14770 break; 14771 case OPC_WRPGPR: 14772 check_insn(ctx, ISA_MIPS_R2); 14773 gen_store_srsgpr(rt, rd); 14774 break; 14775 default: 14776 MIPS_INVAL("cp0"); 14777 gen_reserved_instruction(ctx); 14778 break; 14779 } 14780 break; 14781 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC, OPC_ADDI */ 14782 if (ctx->insn_flags & ISA_MIPS_R6) { 14783 /* OPC_BOVC, OPC_BEQZALC, OPC_BEQC */ 14784 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 14785 } else { 14786 /* OPC_ADDI */ 14787 /* Arithmetic with immediate opcode */ 14788 gen_arith_imm(ctx, op, rt, rs, imm); 14789 } 14790 break; 14791 case OPC_ADDIU: 14792 gen_arith_imm(ctx, op, rt, rs, imm); 14793 break; 14794 case OPC_SLTI: /* Set on less than with immediate opcode */ 14795 case OPC_SLTIU: 14796 gen_slt_imm(ctx, op, rt, rs, imm); 14797 break; 14798 case OPC_ANDI: /* Arithmetic with immediate opcode */ 14799 case OPC_LUI: /* OPC_AUI */ 14800 case OPC_ORI: 14801 case OPC_XORI: 14802 gen_logic_imm(ctx, op, rt, rs, imm); 14803 break; 14804 case OPC_J: /* Jump */ 14805 case OPC_JAL: 14806 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; 14807 gen_compute_branch(ctx, op, 4, rs, rt, offset, 4); 14808 break; 14809 /* Branch */ 14810 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */ 14811 if (ctx->insn_flags & ISA_MIPS_R6) { 14812 if (rt == 0) { 14813 gen_reserved_instruction(ctx); 14814 break; 14815 } 14816 /* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */ 14817 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 14818 } else { 14819 /* OPC_BLEZL */ 14820 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); 14821 } 14822 break; 14823 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */ 14824 if (ctx->insn_flags & ISA_MIPS_R6) { 14825 if (rt == 0) { 14826 gen_reserved_instruction(ctx); 14827 break; 14828 } 14829 /* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */ 14830 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 14831 } else { 14832 /* OPC_BGTZL */ 14833 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); 14834 } 14835 break; 14836 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC, OPC_BLEZ */ 14837 if (rt == 0) { 14838 /* OPC_BLEZ */ 14839 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); 14840 } else { 14841 check_insn(ctx, ISA_MIPS_R6); 14842 /* OPC_BLEZALC, OPC_BGEZALC, OPC_BGEUC */ 14843 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 14844 } 14845 break; 14846 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC, OPC_BGTZ */ 14847 if (rt == 0) { 14848 /* OPC_BGTZ */ 14849 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); 14850 } else { 14851 check_insn(ctx, ISA_MIPS_R6); 14852 /* OPC_BGTZALC, OPC_BLTZALC, OPC_BLTUC */ 14853 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 14854 } 14855 break; 14856 case OPC_BEQL: 14857 case OPC_BNEL: 14858 check_insn(ctx, ISA_MIPS2); 14859 check_insn_opc_removed(ctx, ISA_MIPS_R6); 14860 /* Fallthrough */ 14861 case OPC_BEQ: 14862 case OPC_BNE: 14863 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); 14864 break; 14865 case OPC_LL: /* Load and stores */ 14866 check_insn(ctx, ISA_MIPS2); 14867 if (ctx->insn_flags & INSN_R5900) { 14868 check_insn_opc_user_only(ctx, INSN_R5900); 14869 } 14870 /* Fallthrough */ 14871 case OPC_LWL: 14872 case OPC_LWR: 14873 case OPC_LB: 14874 case OPC_LH: 14875 case OPC_LW: 14876 case OPC_LWPC: 14877 case OPC_LBU: 14878 case OPC_LHU: 14879 gen_ld(ctx, op, rt, rs, imm); 14880 break; 14881 case OPC_SWL: 14882 case OPC_SWR: 14883 case OPC_SB: 14884 case OPC_SH: 14885 case OPC_SW: 14886 gen_st(ctx, op, rt, rs, imm); 14887 break; 14888 case OPC_SC: 14889 check_insn(ctx, ISA_MIPS2); 14890 if (ctx->insn_flags & INSN_R5900) { 14891 check_insn_opc_user_only(ctx, INSN_R5900); 14892 } 14893 gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, false); 14894 break; 14895 case OPC_CACHE: 14896 check_cp0_enabled(ctx); 14897 check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); 14898 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { 14899 gen_cache_operation(ctx, rt, rs, imm); 14900 } 14901 /* Treat as NOP. */ 14902 break; 14903 case OPC_PREF: 14904 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | INSN_R5900); 14905 /* Treat as NOP. */ 14906 break; 14907 14908 /* Floating point (COP1). */ 14909 case OPC_LWC1: 14910 case OPC_LDC1: 14911 case OPC_SWC1: 14912 case OPC_SDC1: 14913 gen_cop1_ldst(ctx, op, rt, rs, imm); 14914 break; 14915 14916 case OPC_CP1: 14917 op1 = MASK_CP1(ctx->opcode); 14918 14919 switch (op1) { 14920 case OPC_MFHC1: 14921 case OPC_MTHC1: 14922 check_cp1_enabled(ctx); 14923 check_insn(ctx, ISA_MIPS_R2); 14924 /* fall through */ 14925 case OPC_MFC1: 14926 case OPC_CFC1: 14927 case OPC_MTC1: 14928 case OPC_CTC1: 14929 check_cp1_enabled(ctx); 14930 gen_cp1(ctx, op1, rt, rd); 14931 break; 14932 #if defined(TARGET_MIPS64) 14933 case OPC_DMFC1: 14934 case OPC_DMTC1: 14935 check_cp1_enabled(ctx); 14936 check_insn(ctx, ISA_MIPS3); 14937 check_mips_64(ctx); 14938 gen_cp1(ctx, op1, rt, rd); 14939 break; 14940 #endif 14941 case OPC_BC1EQZ: /* OPC_BC1ANY2 */ 14942 check_cp1_enabled(ctx); 14943 if (ctx->insn_flags & ISA_MIPS_R6) { 14944 /* OPC_BC1EQZ */ 14945 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), 14946 rt, imm << 2, 4); 14947 } else { 14948 /* OPC_BC1ANY2 */ 14949 check_cop1x(ctx); 14950 check_insn(ctx, ASE_MIPS3D); 14951 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), 14952 (rt >> 2) & 0x7, imm << 2); 14953 } 14954 break; 14955 case OPC_BC1NEZ: 14956 check_cp1_enabled(ctx); 14957 check_insn(ctx, ISA_MIPS_R6); 14958 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), 14959 rt, imm << 2, 4); 14960 break; 14961 case OPC_BC1ANY4: 14962 check_cp1_enabled(ctx); 14963 check_insn_opc_removed(ctx, ISA_MIPS_R6); 14964 check_cop1x(ctx); 14965 check_insn(ctx, ASE_MIPS3D); 14966 /* fall through */ 14967 case OPC_BC1: 14968 check_cp1_enabled(ctx); 14969 check_insn_opc_removed(ctx, ISA_MIPS_R6); 14970 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), 14971 (rt >> 2) & 0x7, imm << 2); 14972 break; 14973 case OPC_PS_FMT: 14974 check_ps(ctx); 14975 /* fall through */ 14976 case OPC_S_FMT: 14977 case OPC_D_FMT: 14978 check_cp1_enabled(ctx); 14979 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa, 14980 (imm >> 8) & 0x7); 14981 break; 14982 case OPC_W_FMT: 14983 case OPC_L_FMT: 14984 { 14985 int r6_op = ctx->opcode & FOP(0x3f, 0x1f); 14986 check_cp1_enabled(ctx); 14987 if (ctx->insn_flags & ISA_MIPS_R6) { 14988 switch (r6_op) { 14989 case R6_OPC_CMP_AF_S: 14990 case R6_OPC_CMP_UN_S: 14991 case R6_OPC_CMP_EQ_S: 14992 case R6_OPC_CMP_UEQ_S: 14993 case R6_OPC_CMP_LT_S: 14994 case R6_OPC_CMP_ULT_S: 14995 case R6_OPC_CMP_LE_S: 14996 case R6_OPC_CMP_ULE_S: 14997 case R6_OPC_CMP_SAF_S: 14998 case R6_OPC_CMP_SUN_S: 14999 case R6_OPC_CMP_SEQ_S: 15000 case R6_OPC_CMP_SEUQ_S: 15001 case R6_OPC_CMP_SLT_S: 15002 case R6_OPC_CMP_SULT_S: 15003 case R6_OPC_CMP_SLE_S: 15004 case R6_OPC_CMP_SULE_S: 15005 case R6_OPC_CMP_OR_S: 15006 case R6_OPC_CMP_UNE_S: 15007 case R6_OPC_CMP_NE_S: 15008 case R6_OPC_CMP_SOR_S: 15009 case R6_OPC_CMP_SUNE_S: 15010 case R6_OPC_CMP_SNE_S: 15011 gen_r6_cmp_s(ctx, ctx->opcode & 0x1f, rt, rd, sa); 15012 break; 15013 case R6_OPC_CMP_AF_D: 15014 case R6_OPC_CMP_UN_D: 15015 case R6_OPC_CMP_EQ_D: 15016 case R6_OPC_CMP_UEQ_D: 15017 case R6_OPC_CMP_LT_D: 15018 case R6_OPC_CMP_ULT_D: 15019 case R6_OPC_CMP_LE_D: 15020 case R6_OPC_CMP_ULE_D: 15021 case R6_OPC_CMP_SAF_D: 15022 case R6_OPC_CMP_SUN_D: 15023 case R6_OPC_CMP_SEQ_D: 15024 case R6_OPC_CMP_SEUQ_D: 15025 case R6_OPC_CMP_SLT_D: 15026 case R6_OPC_CMP_SULT_D: 15027 case R6_OPC_CMP_SLE_D: 15028 case R6_OPC_CMP_SULE_D: 15029 case R6_OPC_CMP_OR_D: 15030 case R6_OPC_CMP_UNE_D: 15031 case R6_OPC_CMP_NE_D: 15032 case R6_OPC_CMP_SOR_D: 15033 case R6_OPC_CMP_SUNE_D: 15034 case R6_OPC_CMP_SNE_D: 15035 gen_r6_cmp_d(ctx, ctx->opcode & 0x1f, rt, rd, sa); 15036 break; 15037 default: 15038 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), 15039 rt, rd, sa, (imm >> 8) & 0x7); 15040 15041 break; 15042 } 15043 } else { 15044 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa, 15045 (imm >> 8) & 0x7); 15046 } 15047 break; 15048 } 15049 default: 15050 MIPS_INVAL("cp1"); 15051 gen_reserved_instruction(ctx); 15052 break; 15053 } 15054 break; 15055 15056 /* Compact branches [R6] and COP2 [non-R6] */ 15057 case OPC_BC: /* OPC_LWC2 */ 15058 case OPC_BALC: /* OPC_SWC2 */ 15059 if (ctx->insn_flags & ISA_MIPS_R6) { 15060 /* OPC_BC, OPC_BALC */ 15061 gen_compute_compact_branch(ctx, op, 0, 0, 15062 sextract32(ctx->opcode << 2, 0, 28)); 15063 } else if (ctx->insn_flags & ASE_LEXT) { 15064 gen_loongson_lswc2(ctx, rt, rs, rd); 15065 } else { 15066 /* OPC_LWC2, OPC_SWC2 */ 15067 /* COP2: Not implemented. */ 15068 generate_exception_err(ctx, EXCP_CpU, 2); 15069 } 15070 break; 15071 case OPC_BEQZC: /* OPC_JIC, OPC_LDC2 */ 15072 case OPC_BNEZC: /* OPC_JIALC, OPC_SDC2 */ 15073 if (ctx->insn_flags & ISA_MIPS_R6) { 15074 if (rs != 0) { 15075 /* OPC_BEQZC, OPC_BNEZC */ 15076 gen_compute_compact_branch(ctx, op, rs, 0, 15077 sextract32(ctx->opcode << 2, 0, 23)); 15078 } else { 15079 /* OPC_JIC, OPC_JIALC */ 15080 gen_compute_compact_branch(ctx, op, 0, rt, imm); 15081 } 15082 } else if (ctx->insn_flags & ASE_LEXT) { 15083 gen_loongson_lsdc2(ctx, rt, rs, rd); 15084 } else { 15085 /* OPC_LWC2, OPC_SWC2 */ 15086 /* COP2: Not implemented. */ 15087 generate_exception_err(ctx, EXCP_CpU, 2); 15088 } 15089 break; 15090 case OPC_CP2: 15091 check_insn(ctx, ASE_LMMI); 15092 /* Note that these instructions use different fields. */ 15093 gen_loongson_multimedia(ctx, sa, rd, rt); 15094 break; 15095 15096 case OPC_CP3: 15097 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { 15098 check_cp1_enabled(ctx); 15099 op1 = MASK_CP3(ctx->opcode); 15100 switch (op1) { 15101 case OPC_LUXC1: 15102 case OPC_SUXC1: 15103 check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2); 15104 /* Fallthrough */ 15105 case OPC_LWXC1: 15106 case OPC_LDXC1: 15107 case OPC_SWXC1: 15108 case OPC_SDXC1: 15109 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); 15110 gen_flt3_ldst(ctx, op1, sa, rd, rs, rt); 15111 break; 15112 case OPC_PREFX: 15113 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); 15114 /* Treat as NOP. */ 15115 break; 15116 case OPC_ALNV_PS: 15117 check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2); 15118 /* Fallthrough */ 15119 case OPC_MADD_S: 15120 case OPC_MADD_D: 15121 case OPC_MADD_PS: 15122 case OPC_MSUB_S: 15123 case OPC_MSUB_D: 15124 case OPC_MSUB_PS: 15125 case OPC_NMADD_S: 15126 case OPC_NMADD_D: 15127 case OPC_NMADD_PS: 15128 case OPC_NMSUB_S: 15129 case OPC_NMSUB_D: 15130 case OPC_NMSUB_PS: 15131 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); 15132 gen_flt3_arith(ctx, op1, sa, rs, rd, rt); 15133 break; 15134 default: 15135 MIPS_INVAL("cp3"); 15136 gen_reserved_instruction(ctx); 15137 break; 15138 } 15139 } else { 15140 generate_exception_err(ctx, EXCP_CpU, 1); 15141 } 15142 break; 15143 15144 #if defined(TARGET_MIPS64) 15145 /* MIPS64 opcodes */ 15146 case OPC_LLD: 15147 if (ctx->insn_flags & INSN_R5900) { 15148 check_insn_opc_user_only(ctx, INSN_R5900); 15149 } 15150 /* fall through */ 15151 case OPC_LDL: 15152 case OPC_LDR: 15153 case OPC_LWU: 15154 case OPC_LD: 15155 check_insn(ctx, ISA_MIPS3); 15156 check_mips_64(ctx); 15157 gen_ld(ctx, op, rt, rs, imm); 15158 break; 15159 case OPC_SDL: 15160 case OPC_SDR: 15161 case OPC_SD: 15162 check_insn(ctx, ISA_MIPS3); 15163 check_mips_64(ctx); 15164 gen_st(ctx, op, rt, rs, imm); 15165 break; 15166 case OPC_SCD: 15167 check_insn(ctx, ISA_MIPS3); 15168 if (ctx->insn_flags & INSN_R5900) { 15169 check_insn_opc_user_only(ctx, INSN_R5900); 15170 } 15171 check_mips_64(ctx); 15172 gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_UQ, false); 15173 break; 15174 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */ 15175 if (ctx->insn_flags & ISA_MIPS_R6) { 15176 /* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */ 15177 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 15178 } else { 15179 /* OPC_DADDI */ 15180 check_insn(ctx, ISA_MIPS3); 15181 check_mips_64(ctx); 15182 gen_arith_imm(ctx, op, rt, rs, imm); 15183 } 15184 break; 15185 case OPC_DADDIU: 15186 check_insn(ctx, ISA_MIPS3); 15187 check_mips_64(ctx); 15188 gen_arith_imm(ctx, op, rt, rs, imm); 15189 break; 15190 #else 15191 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */ 15192 if (ctx->insn_flags & ISA_MIPS_R6) { 15193 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 15194 } else { 15195 MIPS_INVAL("major opcode"); 15196 gen_reserved_instruction(ctx); 15197 } 15198 break; 15199 #endif 15200 case OPC_DAUI: /* OPC_JALX */ 15201 if (ctx->insn_flags & ISA_MIPS_R6) { 15202 #if defined(TARGET_MIPS64) 15203 /* OPC_DAUI */ 15204 check_mips_64(ctx); 15205 if (rs == 0) { 15206 generate_exception(ctx, EXCP_RI); 15207 } else if (rt != 0) { 15208 TCGv t0 = tcg_temp_new(); 15209 gen_load_gpr(t0, rs); 15210 tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16); 15211 } 15212 #else 15213 gen_reserved_instruction(ctx); 15214 MIPS_INVAL("major opcode"); 15215 #endif 15216 } else { 15217 /* OPC_JALX */ 15218 check_insn(ctx, ASE_MIPS16 | ASE_MICROMIPS); 15219 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; 15220 gen_compute_branch(ctx, op, 4, rs, rt, offset, 4); 15221 } 15222 break; 15223 case OPC_MDMX: 15224 /* MDMX: Not implemented. */ 15225 break; 15226 case OPC_PCREL: 15227 check_insn(ctx, ISA_MIPS_R6); 15228 gen_pcrel(ctx, ctx->opcode, ctx->base.pc_next, rs); 15229 break; 15230 default: /* Invalid */ 15231 MIPS_INVAL("major opcode"); 15232 return false; 15233 } 15234 return true; 15235 } 15236 15237 static void decode_opc(CPUMIPSState *env, DisasContext *ctx) 15238 { 15239 /* make sure instructions are on a word boundary */ 15240 if (ctx->base.pc_next & 0x3) { 15241 env->CP0_BadVAddr = ctx->base.pc_next; 15242 generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL); 15243 return; 15244 } 15245 15246 /* Handle blikely not taken case */ 15247 if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) { 15248 TCGLabel *l1 = gen_new_label(); 15249 15250 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); 15251 tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK); 15252 gen_goto_tb(ctx, 1, ctx->base.pc_next + 4); 15253 gen_set_label(l1); 15254 } 15255 15256 /* Transition to the auto-generated decoder. */ 15257 15258 /* Vendor specific extensions */ 15259 if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opcode)) { 15260 return; 15261 } 15262 if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) { 15263 return; 15264 } 15265 #if defined(TARGET_MIPS64) 15266 if (ase_lcsr_available(env) && decode_ase_lcsr(ctx, ctx->opcode)) { 15267 return; 15268 } 15269 if (cpu_supports_isa(env, INSN_OCTEON) && decode_ext_octeon(ctx, ctx->opcode)) { 15270 return; 15271 } 15272 #endif 15273 15274 /* ISA extensions */ 15275 if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) { 15276 return; 15277 } 15278 15279 /* ISA (from latest to oldest) */ 15280 if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->opcode)) { 15281 return; 15282 } 15283 15284 if (decode_opc_legacy(env, ctx)) { 15285 return; 15286 } 15287 15288 gen_reserved_instruction(ctx); 15289 } 15290 15291 static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 15292 { 15293 DisasContext *ctx = container_of(dcbase, DisasContext, base); 15294 CPUMIPSState *env = cpu_env(cs); 15295 15296 ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 15297 ctx->saved_pc = -1; 15298 ctx->insn_flags = env->insn_flags; 15299 ctx->CP0_Config0 = env->CP0_Config0; 15300 ctx->CP0_Config1 = env->CP0_Config1; 15301 ctx->CP0_Config2 = env->CP0_Config2; 15302 ctx->CP0_Config3 = env->CP0_Config3; 15303 ctx->CP0_Config5 = env->CP0_Config5; 15304 ctx->btarget = 0; 15305 ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; 15306 ctx->rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1; 15307 ctx->ie = (env->CP0_Config4 >> CP0C4_IE) & 3; 15308 ctx->bi = (env->CP0_Config3 >> CP0C3_BI) & 1; 15309 ctx->bp = (env->CP0_Config3 >> CP0C3_BP) & 1; 15310 ctx->PAMask = env->PAMask; 15311 ctx->mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1; 15312 ctx->eva = (env->CP0_Config5 >> CP0C5_EVA) & 1; 15313 ctx->sc = (env->CP0_Config3 >> CP0C3_SC) & 1; 15314 ctx->CP0_LLAddr_shift = env->CP0_LLAddr_shift; 15315 ctx->cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1; 15316 /* Restore delay slot state from the tb context. */ 15317 ctx->hflags = (uint32_t)ctx->base.tb->flags; /* FIXME: maybe use 64 bits? */ 15318 ctx->ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1; 15319 ctx->ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) || 15320 (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)); 15321 ctx->vp = (env->CP0_Config5 >> CP0C5_VP) & 1; 15322 ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1; 15323 ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; 15324 ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; 15325 ctx->mi = (env->CP0_Config5 >> CP0C5_MI) & 1; 15326 ctx->gi = (env->CP0_Config5 >> CP0C5_GI) & 3; 15327 restore_cpu_state(env, ctx); 15328 #ifdef CONFIG_USER_ONLY 15329 ctx->mem_idx = MIPS_HFLAG_UM; 15330 #else 15331 ctx->mem_idx = hflags_mmu_index(ctx->hflags); 15332 #endif 15333 ctx->default_tcg_memop_mask = (!(ctx->insn_flags & ISA_NANOMIPS32) && 15334 (ctx->insn_flags & (ISA_MIPS_R6 | 15335 INSN_LOONGSON3A))) ? MO_UNALN : MO_ALIGN; 15336 15337 /* 15338 * Execute a branch and its delay slot as a single instruction. 15339 * This is what GDB expects and is consistent with what the 15340 * hardware does (e.g. if a delay slot instruction faults, the 15341 * reported PC is the PC of the branch). 15342 */ 15343 if ((tb_cflags(ctx->base.tb) & CF_SINGLE_STEP) && 15344 (ctx->hflags & MIPS_HFLAG_BMASK)) { 15345 ctx->base.max_insns = 2; 15346 } 15347 15348 LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, 15349 ctx->hflags); 15350 } 15351 15352 static void mips_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) 15353 { 15354 } 15355 15356 static void mips_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 15357 { 15358 DisasContext *ctx = container_of(dcbase, DisasContext, base); 15359 15360 tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMASK, 15361 ctx->btarget); 15362 } 15363 15364 static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 15365 { 15366 CPUMIPSState *env = cpu_env(cs); 15367 DisasContext *ctx = container_of(dcbase, DisasContext, base); 15368 int insn_bytes; 15369 int is_slot; 15370 15371 is_slot = ctx->hflags & MIPS_HFLAG_BMASK; 15372 if (ctx->insn_flags & ISA_NANOMIPS32) { 15373 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); 15374 insn_bytes = decode_isa_nanomips(env, ctx); 15375 } else if (!(ctx->hflags & MIPS_HFLAG_M16)) { 15376 ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next); 15377 insn_bytes = 4; 15378 decode_opc(env, ctx); 15379 } else if (ctx->insn_flags & ASE_MICROMIPS) { 15380 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); 15381 insn_bytes = decode_isa_micromips(env, ctx); 15382 } else if (ctx->insn_flags & ASE_MIPS16) { 15383 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); 15384 insn_bytes = decode_ase_mips16e(env, ctx); 15385 } else { 15386 gen_reserved_instruction(ctx); 15387 g_assert(ctx->base.is_jmp == DISAS_NORETURN); 15388 return; 15389 } 15390 15391 if (ctx->hflags & MIPS_HFLAG_BMASK) { 15392 if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 | 15393 MIPS_HFLAG_FBNSLOT))) { 15394 /* 15395 * Force to generate branch as there is neither delay nor 15396 * forbidden slot. 15397 */ 15398 is_slot = 1; 15399 } 15400 if ((ctx->hflags & MIPS_HFLAG_M16) && 15401 (ctx->hflags & MIPS_HFLAG_FBNSLOT)) { 15402 /* 15403 * Force to generate branch as microMIPS R6 doesn't restrict 15404 * branches in the forbidden slot. 15405 */ 15406 is_slot = 1; 15407 } 15408 } 15409 if (is_slot) { 15410 gen_branch(ctx, insn_bytes); 15411 } 15412 if (ctx->base.is_jmp == DISAS_SEMIHOST) { 15413 generate_exception_err(ctx, EXCP_SEMIHOST, insn_bytes); 15414 } 15415 ctx->base.pc_next += insn_bytes; 15416 15417 if (ctx->base.is_jmp != DISAS_NEXT) { 15418 return; 15419 } 15420 15421 /* 15422 * End the TB on (most) page crossings. 15423 * See mips_tr_init_disas_context about single-stepping a branch 15424 * together with its delay slot. 15425 */ 15426 if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE 15427 && !(tb_cflags(ctx->base.tb) & CF_SINGLE_STEP)) { 15428 ctx->base.is_jmp = DISAS_TOO_MANY; 15429 } 15430 } 15431 15432 static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 15433 { 15434 DisasContext *ctx = container_of(dcbase, DisasContext, base); 15435 15436 switch (ctx->base.is_jmp) { 15437 case DISAS_STOP: 15438 gen_save_pc(ctx->base.pc_next); 15439 tcg_gen_lookup_and_goto_ptr(); 15440 break; 15441 case DISAS_NEXT: 15442 case DISAS_TOO_MANY: 15443 save_cpu_state(ctx, 0); 15444 gen_goto_tb(ctx, 0, ctx->base.pc_next); 15445 break; 15446 case DISAS_EXIT: 15447 tcg_gen_exit_tb(NULL, 0); 15448 break; 15449 case DISAS_NORETURN: 15450 break; 15451 default: 15452 g_assert_not_reached(); 15453 } 15454 } 15455 15456 static const TranslatorOps mips_tr_ops = { 15457 .init_disas_context = mips_tr_init_disas_context, 15458 .tb_start = mips_tr_tb_start, 15459 .insn_start = mips_tr_insn_start, 15460 .translate_insn = mips_tr_translate_insn, 15461 .tb_stop = mips_tr_tb_stop, 15462 }; 15463 15464 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 15465 vaddr pc, void *host_pc) 15466 { 15467 DisasContext ctx; 15468 15469 translator_loop(cs, tb, max_insns, pc, host_pc, &mips_tr_ops, &ctx.base); 15470 } 15471 15472 void mips_tcg_init(void) 15473 { 15474 cpu_gpr[0] = NULL; 15475 for (unsigned i = 1; i < 32; i++) 15476 cpu_gpr[i] = tcg_global_mem_new(tcg_env, 15477 offsetof(CPUMIPSState, 15478 active_tc.gpr[i]), 15479 regnames[i]); 15480 #if defined(TARGET_MIPS64) 15481 cpu_gpr_hi[0] = NULL; 15482 15483 for (unsigned i = 1; i < 32; i++) { 15484 g_autofree char *rname = g_strdup_printf("%s[hi]", regnames[i]); 15485 15486 cpu_gpr_hi[i] = tcg_global_mem_new_i64(tcg_env, 15487 offsetof(CPUMIPSState, 15488 active_tc.gpr_hi[i]), 15489 rname); 15490 } 15491 #endif /* !TARGET_MIPS64 */ 15492 for (unsigned i = 0; i < 32; i++) { 15493 int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); 15494 15495 fpu_f64[i] = tcg_global_mem_new_i64(tcg_env, off, fregnames[i]); 15496 } 15497 msa_translate_init(); 15498 cpu_PC = tcg_global_mem_new(tcg_env, 15499 offsetof(CPUMIPSState, active_tc.PC), "PC"); 15500 for (unsigned i = 0; i < MIPS_DSP_ACC; i++) { 15501 cpu_HI[i] = tcg_global_mem_new(tcg_env, 15502 offsetof(CPUMIPSState, active_tc.HI[i]), 15503 regnames_HI[i]); 15504 cpu_LO[i] = tcg_global_mem_new(tcg_env, 15505 offsetof(CPUMIPSState, active_tc.LO[i]), 15506 regnames_LO[i]); 15507 } 15508 cpu_dspctrl = tcg_global_mem_new(tcg_env, 15509 offsetof(CPUMIPSState, 15510 active_tc.DSPControl), 15511 "DSPControl"); 15512 bcond = tcg_global_mem_new(tcg_env, 15513 offsetof(CPUMIPSState, bcond), "bcond"); 15514 btarget = tcg_global_mem_new(tcg_env, 15515 offsetof(CPUMIPSState, btarget), "btarget"); 15516 hflags = tcg_global_mem_new_i32(tcg_env, 15517 offsetof(CPUMIPSState, hflags), "hflags"); 15518 15519 fpu_fcr0 = tcg_global_mem_new_i32(tcg_env, 15520 offsetof(CPUMIPSState, active_fpu.fcr0), 15521 "fcr0"); 15522 fpu_fcr31 = tcg_global_mem_new_i32(tcg_env, 15523 offsetof(CPUMIPSState, active_fpu.fcr31), 15524 "fcr31"); 15525 cpu_lladdr = tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, lladdr), 15526 "lladdr"); 15527 cpu_llval = tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, llval), 15528 "llval"); 15529 15530 if (TARGET_LONG_BITS == 32) { 15531 mxu_translate_init(); 15532 } 15533 } 15534 15535 void mips_restore_state_to_opc(CPUState *cs, 15536 const TranslationBlock *tb, 15537 const uint64_t *data) 15538 { 15539 CPUMIPSState *env = cpu_env(cs); 15540 15541 env->active_tc.PC = data[0]; 15542 env->hflags &= ~MIPS_HFLAG_BMASK; 15543 env->hflags |= data[1]; 15544 switch (env->hflags & MIPS_HFLAG_BMASK_BASE) { 15545 case MIPS_HFLAG_BR: 15546 break; 15547 case MIPS_HFLAG_BC: 15548 case MIPS_HFLAG_BL: 15549 case MIPS_HFLAG_B: 15550 env->btarget = data[2]; 15551 break; 15552 } 15553 } 15554