1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * Xilinx MicroBlaze emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2009 Edgar E. Iglesias. 5fcf5ef2aSThomas Huth * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 10fcf5ef2aSThomas Huth * version 2 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "disas/disas.h" 24fcf5ef2aSThomas Huth #include "exec/exec-all.h" 25dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 26fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 27fcf5ef2aSThomas Huth #include "microblaze-decode.h" 28fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 29fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 3077fc6f5eSLluís Vilanova #include "exec/translator.h" 3190c84c56SMarkus Armbruster #include "qemu/qemu-print.h" 32fcf5ef2aSThomas Huth 33fcf5ef2aSThomas Huth #include "trace-tcg.h" 34fcf5ef2aSThomas Huth #include "exec/log.h" 35fcf5ef2aSThomas Huth 36fcf5ef2aSThomas Huth 37fcf5ef2aSThomas Huth #define SIM_COMPAT 0 38fcf5ef2aSThomas Huth #define DISAS_GNU 1 39fcf5ef2aSThomas Huth #define DISAS_MB 1 40fcf5ef2aSThomas Huth #if DISAS_MB && !SIM_COMPAT 41fcf5ef2aSThomas Huth # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 42fcf5ef2aSThomas Huth #else 43fcf5ef2aSThomas Huth # define LOG_DIS(...) do { } while (0) 44fcf5ef2aSThomas Huth #endif 45fcf5ef2aSThomas Huth 46fcf5ef2aSThomas Huth #define D(x) 47fcf5ef2aSThomas Huth 48fcf5ef2aSThomas Huth #define EXTRACT_FIELD(src, start, end) \ 49fcf5ef2aSThomas Huth (((src) >> start) & ((1 << (end - start + 1)) - 1)) 50fcf5ef2aSThomas Huth 5177fc6f5eSLluís Vilanova /* is_jmp field values */ 5277fc6f5eSLluís Vilanova #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ 5377fc6f5eSLluís Vilanova #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ 5477fc6f5eSLluís Vilanova #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ 5577fc6f5eSLluís Vilanova 56cfeea807SEdgar E. Iglesias static TCGv_i32 env_debug; 57cfeea807SEdgar E. Iglesias static TCGv_i32 cpu_R[32]; 580f96e96bSRichard Henderson static TCGv_i32 cpu_pc; 593e0e16aeSRichard Henderson static TCGv_i32 cpu_msr; 60aa28e6d4SRichard Henderson static TCGv_i64 cpu_ear; 616efd5599SRichard Henderson static TCGv_i32 cpu_esr; 62cfeea807SEdgar E. Iglesias static TCGv_i32 env_imm; 63cfeea807SEdgar E. Iglesias static TCGv_i32 env_btaken; 640f96e96bSRichard Henderson static TCGv_i32 cpu_btarget; 65cfeea807SEdgar E. Iglesias static TCGv_i32 env_iflags; 66403322eaSEdgar E. Iglesias static TCGv env_res_addr; 67cfeea807SEdgar E. Iglesias static TCGv_i32 env_res_val; 68fcf5ef2aSThomas Huth 69fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 70fcf5ef2aSThomas Huth 71fcf5ef2aSThomas Huth /* This is the state at translation time. */ 72fcf5ef2aSThomas Huth typedef struct DisasContext { 73fcf5ef2aSThomas Huth MicroBlazeCPU *cpu; 74cfeea807SEdgar E. Iglesias uint32_t pc; 75fcf5ef2aSThomas Huth 76fcf5ef2aSThomas Huth /* Decoder. */ 77fcf5ef2aSThomas Huth int type_b; 78fcf5ef2aSThomas Huth uint32_t ir; 79fcf5ef2aSThomas Huth uint8_t opcode; 80fcf5ef2aSThomas Huth uint8_t rd, ra, rb; 81fcf5ef2aSThomas Huth uint16_t imm; 82fcf5ef2aSThomas Huth 83fcf5ef2aSThomas Huth unsigned int cpustate_changed; 84fcf5ef2aSThomas Huth unsigned int delayed_branch; 85fcf5ef2aSThomas Huth unsigned int tb_flags, synced_flags; /* tb dependent flags. */ 86fcf5ef2aSThomas Huth unsigned int clear_imm; 87fcf5ef2aSThomas Huth int is_jmp; 88fcf5ef2aSThomas Huth 89fcf5ef2aSThomas Huth #define JMP_NOJMP 0 90fcf5ef2aSThomas Huth #define JMP_DIRECT 1 91fcf5ef2aSThomas Huth #define JMP_DIRECT_CC 2 92fcf5ef2aSThomas Huth #define JMP_INDIRECT 3 93fcf5ef2aSThomas Huth unsigned int jmp; 94fcf5ef2aSThomas Huth uint32_t jmp_pc; 95fcf5ef2aSThomas Huth 96fcf5ef2aSThomas Huth int abort_at_next_insn; 97fcf5ef2aSThomas Huth struct TranslationBlock *tb; 98fcf5ef2aSThomas Huth int singlestep_enabled; 99fcf5ef2aSThomas Huth } DisasContext; 100fcf5ef2aSThomas Huth 101fcf5ef2aSThomas Huth static const char *regnames[] = 102fcf5ef2aSThomas Huth { 103fcf5ef2aSThomas Huth "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 104fcf5ef2aSThomas Huth "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 105fcf5ef2aSThomas Huth "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 106fcf5ef2aSThomas Huth "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 107fcf5ef2aSThomas Huth }; 108fcf5ef2aSThomas Huth 109fcf5ef2aSThomas Huth static inline void t_sync_flags(DisasContext *dc) 110fcf5ef2aSThomas Huth { 111fcf5ef2aSThomas Huth /* Synch the tb dependent flags between translator and runtime. */ 112fcf5ef2aSThomas Huth if (dc->tb_flags != dc->synced_flags) { 113cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(env_iflags, dc->tb_flags); 114fcf5ef2aSThomas Huth dc->synced_flags = dc->tb_flags; 115fcf5ef2aSThomas Huth } 116fcf5ef2aSThomas Huth } 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index) 119fcf5ef2aSThomas Huth { 120fcf5ef2aSThomas Huth TCGv_i32 tmp = tcg_const_i32(index); 121fcf5ef2aSThomas Huth 122fcf5ef2aSThomas Huth t_sync_flags(dc); 1230f96e96bSRichard Henderson tcg_gen_movi_i32(cpu_pc, dc->pc); 124fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, tmp); 125fcf5ef2aSThomas Huth tcg_temp_free_i32(tmp); 126fcf5ef2aSThomas Huth dc->is_jmp = DISAS_UPDATE; 127fcf5ef2aSThomas Huth } 128fcf5ef2aSThomas Huth 129fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) 130fcf5ef2aSThomas Huth { 131fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 132fcf5ef2aSThomas Huth return (dc->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 133fcf5ef2aSThomas Huth #else 134fcf5ef2aSThomas Huth return true; 135fcf5ef2aSThomas Huth #endif 136fcf5ef2aSThomas Huth } 137fcf5ef2aSThomas Huth 138fcf5ef2aSThomas Huth static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) 139fcf5ef2aSThomas Huth { 140fcf5ef2aSThomas Huth if (use_goto_tb(dc, dest)) { 141fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 1420f96e96bSRichard Henderson tcg_gen_movi_i32(cpu_pc, dest); 14307ea28b4SRichard Henderson tcg_gen_exit_tb(dc->tb, n); 144fcf5ef2aSThomas Huth } else { 1450f96e96bSRichard Henderson tcg_gen_movi_i32(cpu_pc, dest); 14607ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 147fcf5ef2aSThomas Huth } 148fcf5ef2aSThomas Huth } 149fcf5ef2aSThomas Huth 150cfeea807SEdgar E. Iglesias static void read_carry(DisasContext *dc, TCGv_i32 d) 151fcf5ef2aSThomas Huth { 1523e0e16aeSRichard Henderson tcg_gen_shri_i32(d, cpu_msr, 31); 153fcf5ef2aSThomas Huth } 154fcf5ef2aSThomas Huth 155fcf5ef2aSThomas Huth /* 156fcf5ef2aSThomas Huth * write_carry sets the carry bits in MSR based on bit 0 of v. 157fcf5ef2aSThomas Huth * v[31:1] are ignored. 158fcf5ef2aSThomas Huth */ 159cfeea807SEdgar E. Iglesias static void write_carry(DisasContext *dc, TCGv_i32 v) 160fcf5ef2aSThomas Huth { 1610a22f8cfSEdgar E. Iglesias /* Deposit bit 0 into MSR_C and the alias MSR_CC. */ 1623e0e16aeSRichard Henderson tcg_gen_deposit_i32(cpu_msr, cpu_msr, v, 2, 1); 1633e0e16aeSRichard Henderson tcg_gen_deposit_i32(cpu_msr, cpu_msr, v, 31, 1); 164fcf5ef2aSThomas Huth } 165fcf5ef2aSThomas Huth 166fcf5ef2aSThomas Huth static void write_carryi(DisasContext *dc, bool carry) 167fcf5ef2aSThomas Huth { 168cfeea807SEdgar E. Iglesias TCGv_i32 t0 = tcg_temp_new_i32(); 169cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(t0, carry); 170fcf5ef2aSThomas Huth write_carry(dc, t0); 171cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t0); 172fcf5ef2aSThomas Huth } 173fcf5ef2aSThomas Huth 174bdfc1e88SEdgar E. Iglesias /* 1759ba8cd45SEdgar E. Iglesias * Returns true if the insn an illegal operation. 1769ba8cd45SEdgar E. Iglesias * If exceptions are enabled, an exception is raised. 1779ba8cd45SEdgar E. Iglesias */ 1789ba8cd45SEdgar E. Iglesias static bool trap_illegal(DisasContext *dc, bool cond) 1799ba8cd45SEdgar E. Iglesias { 1809ba8cd45SEdgar E. Iglesias if (cond && (dc->tb_flags & MSR_EE_FLAG) 1815143fdf3SEdgar E. Iglesias && dc->cpu->cfg.illegal_opcode_exception) { 1826efd5599SRichard Henderson tcg_gen_movi_i32(cpu_esr, ESR_EC_ILLEGAL_OP); 1839ba8cd45SEdgar E. Iglesias t_gen_raise_exception(dc, EXCP_HW_EXCP); 1849ba8cd45SEdgar E. Iglesias } 1859ba8cd45SEdgar E. Iglesias return cond; 1869ba8cd45SEdgar E. Iglesias } 1879ba8cd45SEdgar E. Iglesias 1889ba8cd45SEdgar E. Iglesias /* 189bdfc1e88SEdgar E. Iglesias * Returns true if the insn is illegal in userspace. 190bdfc1e88SEdgar E. Iglesias * If exceptions are enabled, an exception is raised. 191bdfc1e88SEdgar E. Iglesias */ 192bdfc1e88SEdgar E. Iglesias static bool trap_userspace(DisasContext *dc, bool cond) 193bdfc1e88SEdgar E. Iglesias { 194bdfc1e88SEdgar E. Iglesias int mem_index = cpu_mmu_index(&dc->cpu->env, false); 195bdfc1e88SEdgar E. Iglesias bool cond_user = cond && mem_index == MMU_USER_IDX; 196bdfc1e88SEdgar E. Iglesias 197bdfc1e88SEdgar E. Iglesias if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { 1986efd5599SRichard Henderson tcg_gen_movi_i32(cpu_esr, ESR_EC_PRIVINSN); 199bdfc1e88SEdgar E. Iglesias t_gen_raise_exception(dc, EXCP_HW_EXCP); 200bdfc1e88SEdgar E. Iglesias } 201bdfc1e88SEdgar E. Iglesias return cond_user; 202bdfc1e88SEdgar E. Iglesias } 203bdfc1e88SEdgar E. Iglesias 204fcf5ef2aSThomas Huth /* True if ALU operand b is a small immediate that may deserve 205fcf5ef2aSThomas Huth faster treatment. */ 206fcf5ef2aSThomas Huth static inline int dec_alu_op_b_is_small_imm(DisasContext *dc) 207fcf5ef2aSThomas Huth { 208fcf5ef2aSThomas Huth /* Immediate insn without the imm prefix ? */ 209fcf5ef2aSThomas Huth return dc->type_b && !(dc->tb_flags & IMM_FLAG); 210fcf5ef2aSThomas Huth } 211fcf5ef2aSThomas Huth 212cfeea807SEdgar E. Iglesias static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) 213fcf5ef2aSThomas Huth { 214fcf5ef2aSThomas Huth if (dc->type_b) { 215fcf5ef2aSThomas Huth if (dc->tb_flags & IMM_FLAG) 216cfeea807SEdgar E. Iglesias tcg_gen_ori_i32(env_imm, env_imm, dc->imm); 217fcf5ef2aSThomas Huth else 218cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(env_imm, (int32_t)((int16_t)dc->imm)); 219fcf5ef2aSThomas Huth return &env_imm; 220fcf5ef2aSThomas Huth } else 221fcf5ef2aSThomas Huth return &cpu_R[dc->rb]; 222fcf5ef2aSThomas Huth } 223fcf5ef2aSThomas Huth 224fcf5ef2aSThomas Huth static void dec_add(DisasContext *dc) 225fcf5ef2aSThomas Huth { 226fcf5ef2aSThomas Huth unsigned int k, c; 227cfeea807SEdgar E. Iglesias TCGv_i32 cf; 228fcf5ef2aSThomas Huth 229fcf5ef2aSThomas Huth k = dc->opcode & 4; 230fcf5ef2aSThomas Huth c = dc->opcode & 2; 231fcf5ef2aSThomas Huth 232fcf5ef2aSThomas Huth LOG_DIS("add%s%s%s r%d r%d r%d\n", 233fcf5ef2aSThomas Huth dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "", 234fcf5ef2aSThomas Huth dc->rd, dc->ra, dc->rb); 235fcf5ef2aSThomas Huth 236fcf5ef2aSThomas Huth /* Take care of the easy cases first. */ 237fcf5ef2aSThomas Huth if (k) { 238fcf5ef2aSThomas Huth /* k - keep carry, no need to update MSR. */ 239fcf5ef2aSThomas Huth /* If rd == r0, it's a nop. */ 240fcf5ef2aSThomas Huth if (dc->rd) { 241cfeea807SEdgar E. Iglesias tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); 242fcf5ef2aSThomas Huth 243fcf5ef2aSThomas Huth if (c) { 244fcf5ef2aSThomas Huth /* c - Add carry into the result. */ 245cfeea807SEdgar E. Iglesias cf = tcg_temp_new_i32(); 246fcf5ef2aSThomas Huth 247fcf5ef2aSThomas Huth read_carry(dc, cf); 248cfeea807SEdgar E. Iglesias tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); 249cfeea807SEdgar E. Iglesias tcg_temp_free_i32(cf); 250fcf5ef2aSThomas Huth } 251fcf5ef2aSThomas Huth } 252fcf5ef2aSThomas Huth return; 253fcf5ef2aSThomas Huth } 254fcf5ef2aSThomas Huth 255fcf5ef2aSThomas Huth /* From now on, we can assume k is zero. So we need to update MSR. */ 256fcf5ef2aSThomas Huth /* Extract carry. */ 257cfeea807SEdgar E. Iglesias cf = tcg_temp_new_i32(); 258fcf5ef2aSThomas Huth if (c) { 259fcf5ef2aSThomas Huth read_carry(dc, cf); 260fcf5ef2aSThomas Huth } else { 261cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(cf, 0); 262fcf5ef2aSThomas Huth } 263fcf5ef2aSThomas Huth 264fcf5ef2aSThomas Huth if (dc->rd) { 265cfeea807SEdgar E. Iglesias TCGv_i32 ncf = tcg_temp_new_i32(); 266fcf5ef2aSThomas Huth gen_helper_carry(ncf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); 267cfeea807SEdgar E. Iglesias tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); 268cfeea807SEdgar E. Iglesias tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); 269fcf5ef2aSThomas Huth write_carry(dc, ncf); 270cfeea807SEdgar E. Iglesias tcg_temp_free_i32(ncf); 271fcf5ef2aSThomas Huth } else { 272fcf5ef2aSThomas Huth gen_helper_carry(cf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); 273fcf5ef2aSThomas Huth write_carry(dc, cf); 274fcf5ef2aSThomas Huth } 275cfeea807SEdgar E. Iglesias tcg_temp_free_i32(cf); 276fcf5ef2aSThomas Huth } 277fcf5ef2aSThomas Huth 278fcf5ef2aSThomas Huth static void dec_sub(DisasContext *dc) 279fcf5ef2aSThomas Huth { 280fcf5ef2aSThomas Huth unsigned int u, cmp, k, c; 281cfeea807SEdgar E. Iglesias TCGv_i32 cf, na; 282fcf5ef2aSThomas Huth 283fcf5ef2aSThomas Huth u = dc->imm & 2; 284fcf5ef2aSThomas Huth k = dc->opcode & 4; 285fcf5ef2aSThomas Huth c = dc->opcode & 2; 286fcf5ef2aSThomas Huth cmp = (dc->imm & 1) && (!dc->type_b) && k; 287fcf5ef2aSThomas Huth 288fcf5ef2aSThomas Huth if (cmp) { 289fcf5ef2aSThomas Huth LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir); 290fcf5ef2aSThomas Huth if (dc->rd) { 291fcf5ef2aSThomas Huth if (u) 292fcf5ef2aSThomas Huth gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); 293fcf5ef2aSThomas Huth else 294fcf5ef2aSThomas Huth gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); 295fcf5ef2aSThomas Huth } 296fcf5ef2aSThomas Huth return; 297fcf5ef2aSThomas Huth } 298fcf5ef2aSThomas Huth 299fcf5ef2aSThomas Huth LOG_DIS("sub%s%s r%d, r%d r%d\n", 300fcf5ef2aSThomas Huth k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb); 301fcf5ef2aSThomas Huth 302fcf5ef2aSThomas Huth /* Take care of the easy cases first. */ 303fcf5ef2aSThomas Huth if (k) { 304fcf5ef2aSThomas Huth /* k - keep carry, no need to update MSR. */ 305fcf5ef2aSThomas Huth /* If rd == r0, it's a nop. */ 306fcf5ef2aSThomas Huth if (dc->rd) { 307cfeea807SEdgar E. Iglesias tcg_gen_sub_i32(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]); 308fcf5ef2aSThomas Huth 309fcf5ef2aSThomas Huth if (c) { 310fcf5ef2aSThomas Huth /* c - Add carry into the result. */ 311cfeea807SEdgar E. Iglesias cf = tcg_temp_new_i32(); 312fcf5ef2aSThomas Huth 313fcf5ef2aSThomas Huth read_carry(dc, cf); 314cfeea807SEdgar E. Iglesias tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); 315cfeea807SEdgar E. Iglesias tcg_temp_free_i32(cf); 316fcf5ef2aSThomas Huth } 317fcf5ef2aSThomas Huth } 318fcf5ef2aSThomas Huth return; 319fcf5ef2aSThomas Huth } 320fcf5ef2aSThomas Huth 321fcf5ef2aSThomas Huth /* From now on, we can assume k is zero. So we need to update MSR. */ 322fcf5ef2aSThomas Huth /* Extract carry. And complement a into na. */ 323cfeea807SEdgar E. Iglesias cf = tcg_temp_new_i32(); 324cfeea807SEdgar E. Iglesias na = tcg_temp_new_i32(); 325fcf5ef2aSThomas Huth if (c) { 326fcf5ef2aSThomas Huth read_carry(dc, cf); 327fcf5ef2aSThomas Huth } else { 328cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(cf, 1); 329fcf5ef2aSThomas Huth } 330fcf5ef2aSThomas Huth 331fcf5ef2aSThomas Huth /* d = b + ~a + c. carry defaults to 1. */ 332cfeea807SEdgar E. Iglesias tcg_gen_not_i32(na, cpu_R[dc->ra]); 333fcf5ef2aSThomas Huth 334fcf5ef2aSThomas Huth if (dc->rd) { 335cfeea807SEdgar E. Iglesias TCGv_i32 ncf = tcg_temp_new_i32(); 336fcf5ef2aSThomas Huth gen_helper_carry(ncf, na, *(dec_alu_op_b(dc)), cf); 337cfeea807SEdgar E. Iglesias tcg_gen_add_i32(cpu_R[dc->rd], na, *(dec_alu_op_b(dc))); 338cfeea807SEdgar E. Iglesias tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); 339fcf5ef2aSThomas Huth write_carry(dc, ncf); 340cfeea807SEdgar E. Iglesias tcg_temp_free_i32(ncf); 341fcf5ef2aSThomas Huth } else { 342fcf5ef2aSThomas Huth gen_helper_carry(cf, na, *(dec_alu_op_b(dc)), cf); 343fcf5ef2aSThomas Huth write_carry(dc, cf); 344fcf5ef2aSThomas Huth } 345cfeea807SEdgar E. Iglesias tcg_temp_free_i32(cf); 346cfeea807SEdgar E. Iglesias tcg_temp_free_i32(na); 347fcf5ef2aSThomas Huth } 348fcf5ef2aSThomas Huth 349fcf5ef2aSThomas Huth static void dec_pattern(DisasContext *dc) 350fcf5ef2aSThomas Huth { 351fcf5ef2aSThomas Huth unsigned int mode; 352fcf5ef2aSThomas Huth 3539ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, !dc->cpu->cfg.use_pcmp_instr)) { 3549ba8cd45SEdgar E. Iglesias return; 355fcf5ef2aSThomas Huth } 356fcf5ef2aSThomas Huth 357fcf5ef2aSThomas Huth mode = dc->opcode & 3; 358fcf5ef2aSThomas Huth switch (mode) { 359fcf5ef2aSThomas Huth case 0: 360fcf5ef2aSThomas Huth /* pcmpbf. */ 361fcf5ef2aSThomas Huth LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); 362fcf5ef2aSThomas Huth if (dc->rd) 363fcf5ef2aSThomas Huth gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); 364fcf5ef2aSThomas Huth break; 365fcf5ef2aSThomas Huth case 2: 366fcf5ef2aSThomas Huth LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); 367fcf5ef2aSThomas Huth if (dc->rd) { 368cfeea807SEdgar E. Iglesias tcg_gen_setcond_i32(TCG_COND_EQ, cpu_R[dc->rd], 369fcf5ef2aSThomas Huth cpu_R[dc->ra], cpu_R[dc->rb]); 370fcf5ef2aSThomas Huth } 371fcf5ef2aSThomas Huth break; 372fcf5ef2aSThomas Huth case 3: 373fcf5ef2aSThomas Huth LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); 374fcf5ef2aSThomas Huth if (dc->rd) { 375cfeea807SEdgar E. Iglesias tcg_gen_setcond_i32(TCG_COND_NE, cpu_R[dc->rd], 376fcf5ef2aSThomas Huth cpu_R[dc->ra], cpu_R[dc->rb]); 377fcf5ef2aSThomas Huth } 378fcf5ef2aSThomas Huth break; 379fcf5ef2aSThomas Huth default: 380fcf5ef2aSThomas Huth cpu_abort(CPU(dc->cpu), 381fcf5ef2aSThomas Huth "unsupported pattern insn opcode=%x\n", dc->opcode); 382fcf5ef2aSThomas Huth break; 383fcf5ef2aSThomas Huth } 384fcf5ef2aSThomas Huth } 385fcf5ef2aSThomas Huth 386fcf5ef2aSThomas Huth static void dec_and(DisasContext *dc) 387fcf5ef2aSThomas Huth { 388fcf5ef2aSThomas Huth unsigned int not; 389fcf5ef2aSThomas Huth 390fcf5ef2aSThomas Huth if (!dc->type_b && (dc->imm & (1 << 10))) { 391fcf5ef2aSThomas Huth dec_pattern(dc); 392fcf5ef2aSThomas Huth return; 393fcf5ef2aSThomas Huth } 394fcf5ef2aSThomas Huth 395fcf5ef2aSThomas Huth not = dc->opcode & (1 << 1); 396fcf5ef2aSThomas Huth LOG_DIS("and%s\n", not ? "n" : ""); 397fcf5ef2aSThomas Huth 398fcf5ef2aSThomas Huth if (!dc->rd) 399fcf5ef2aSThomas Huth return; 400fcf5ef2aSThomas Huth 401fcf5ef2aSThomas Huth if (not) { 402cfeea807SEdgar E. Iglesias tcg_gen_andc_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); 403fcf5ef2aSThomas Huth } else 404cfeea807SEdgar E. Iglesias tcg_gen_and_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); 405fcf5ef2aSThomas Huth } 406fcf5ef2aSThomas Huth 407fcf5ef2aSThomas Huth static void dec_or(DisasContext *dc) 408fcf5ef2aSThomas Huth { 409fcf5ef2aSThomas Huth if (!dc->type_b && (dc->imm & (1 << 10))) { 410fcf5ef2aSThomas Huth dec_pattern(dc); 411fcf5ef2aSThomas Huth return; 412fcf5ef2aSThomas Huth } 413fcf5ef2aSThomas Huth 414fcf5ef2aSThomas Huth LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm); 415fcf5ef2aSThomas Huth if (dc->rd) 416cfeea807SEdgar E. Iglesias tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); 417fcf5ef2aSThomas Huth } 418fcf5ef2aSThomas Huth 419fcf5ef2aSThomas Huth static void dec_xor(DisasContext *dc) 420fcf5ef2aSThomas Huth { 421fcf5ef2aSThomas Huth if (!dc->type_b && (dc->imm & (1 << 10))) { 422fcf5ef2aSThomas Huth dec_pattern(dc); 423fcf5ef2aSThomas Huth return; 424fcf5ef2aSThomas Huth } 425fcf5ef2aSThomas Huth 426fcf5ef2aSThomas Huth LOG_DIS("xor r%d\n", dc->rd); 427fcf5ef2aSThomas Huth if (dc->rd) 428cfeea807SEdgar E. Iglesias tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); 429fcf5ef2aSThomas Huth } 430fcf5ef2aSThomas Huth 431cfeea807SEdgar E. Iglesias static inline void msr_read(DisasContext *dc, TCGv_i32 d) 432fcf5ef2aSThomas Huth { 4333e0e16aeSRichard Henderson tcg_gen_mov_i32(d, cpu_msr); 434fcf5ef2aSThomas Huth } 435fcf5ef2aSThomas Huth 436cfeea807SEdgar E. Iglesias static inline void msr_write(DisasContext *dc, TCGv_i32 v) 437fcf5ef2aSThomas Huth { 438fcf5ef2aSThomas Huth dc->cpustate_changed = 1; 4393e0e16aeSRichard Henderson /* PVR bit is not writable, and is never set. */ 4403e0e16aeSRichard Henderson tcg_gen_andi_i32(cpu_msr, v, ~MSR_PVR); 441fcf5ef2aSThomas Huth } 442fcf5ef2aSThomas Huth 443fcf5ef2aSThomas Huth static void dec_msr(DisasContext *dc) 444fcf5ef2aSThomas Huth { 445fcf5ef2aSThomas Huth CPUState *cs = CPU(dc->cpu); 446cfeea807SEdgar E. Iglesias TCGv_i32 t0, t1; 4472023e9a3SEdgar E. Iglesias unsigned int sr, rn; 448f0f7e7f7SEdgar E. Iglesias bool to, clrset, extended = false; 449fcf5ef2aSThomas Huth 4502023e9a3SEdgar E. Iglesias sr = extract32(dc->imm, 0, 14); 4512023e9a3SEdgar E. Iglesias to = extract32(dc->imm, 14, 1); 4522023e9a3SEdgar E. Iglesias clrset = extract32(dc->imm, 15, 1) == 0; 453fcf5ef2aSThomas Huth dc->type_b = 1; 4542023e9a3SEdgar E. Iglesias if (to) { 455fcf5ef2aSThomas Huth dc->cpustate_changed = 1; 456f0f7e7f7SEdgar E. Iglesias } 457f0f7e7f7SEdgar E. Iglesias 458f0f7e7f7SEdgar E. Iglesias /* Extended MSRs are only available if addr_size > 32. */ 459f0f7e7f7SEdgar E. Iglesias if (dc->cpu->cfg.addr_size > 32) { 460f0f7e7f7SEdgar E. Iglesias /* The E-bit is encoded differently for To/From MSR. */ 461f0f7e7f7SEdgar E. Iglesias static const unsigned int e_bit[] = { 19, 24 }; 462f0f7e7f7SEdgar E. Iglesias 463f0f7e7f7SEdgar E. Iglesias extended = extract32(dc->imm, e_bit[to], 1); 4642023e9a3SEdgar E. Iglesias } 465fcf5ef2aSThomas Huth 466fcf5ef2aSThomas Huth /* msrclr and msrset. */ 4672023e9a3SEdgar E. Iglesias if (clrset) { 4682023e9a3SEdgar E. Iglesias bool clr = extract32(dc->ir, 16, 1); 469fcf5ef2aSThomas Huth 470fcf5ef2aSThomas Huth LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set", 471fcf5ef2aSThomas Huth dc->rd, dc->imm); 472fcf5ef2aSThomas Huth 47356837509SEdgar E. Iglesias if (!dc->cpu->cfg.use_msr_instr) { 474fcf5ef2aSThomas Huth /* nop??? */ 475fcf5ef2aSThomas Huth return; 476fcf5ef2aSThomas Huth } 477fcf5ef2aSThomas Huth 478bdfc1e88SEdgar E. Iglesias if (trap_userspace(dc, dc->imm != 4 && dc->imm != 0)) { 479fcf5ef2aSThomas Huth return; 480fcf5ef2aSThomas Huth } 481fcf5ef2aSThomas Huth 482fcf5ef2aSThomas Huth if (dc->rd) 483fcf5ef2aSThomas Huth msr_read(dc, cpu_R[dc->rd]); 484fcf5ef2aSThomas Huth 485cfeea807SEdgar E. Iglesias t0 = tcg_temp_new_i32(); 486cfeea807SEdgar E. Iglesias t1 = tcg_temp_new_i32(); 487fcf5ef2aSThomas Huth msr_read(dc, t0); 488cfeea807SEdgar E. Iglesias tcg_gen_mov_i32(t1, *(dec_alu_op_b(dc))); 489fcf5ef2aSThomas Huth 490fcf5ef2aSThomas Huth if (clr) { 491cfeea807SEdgar E. Iglesias tcg_gen_not_i32(t1, t1); 492cfeea807SEdgar E. Iglesias tcg_gen_and_i32(t0, t0, t1); 493fcf5ef2aSThomas Huth } else 494cfeea807SEdgar E. Iglesias tcg_gen_or_i32(t0, t0, t1); 495fcf5ef2aSThomas Huth msr_write(dc, t0); 496cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t0); 497cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t1); 4980f96e96bSRichard Henderson tcg_gen_movi_i32(cpu_pc, dc->pc + 4); 499fcf5ef2aSThomas Huth dc->is_jmp = DISAS_UPDATE; 500fcf5ef2aSThomas Huth return; 501fcf5ef2aSThomas Huth } 502fcf5ef2aSThomas Huth 503bdfc1e88SEdgar E. Iglesias if (trap_userspace(dc, to)) { 504fcf5ef2aSThomas Huth return; 505fcf5ef2aSThomas Huth } 506fcf5ef2aSThomas Huth 507fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 508fcf5ef2aSThomas Huth /* Catch read/writes to the mmu block. */ 509fcf5ef2aSThomas Huth if ((sr & ~0xff) == 0x1000) { 510f0f7e7f7SEdgar E. Iglesias TCGv_i32 tmp_ext = tcg_const_i32(extended); 51105a9a651SEdgar E. Iglesias TCGv_i32 tmp_sr; 51205a9a651SEdgar E. Iglesias 513fcf5ef2aSThomas Huth sr &= 7; 51405a9a651SEdgar E. Iglesias tmp_sr = tcg_const_i32(sr); 515fcf5ef2aSThomas Huth LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); 51605a9a651SEdgar E. Iglesias if (to) { 517f0f7e7f7SEdgar E. Iglesias gen_helper_mmu_write(cpu_env, tmp_ext, tmp_sr, cpu_R[dc->ra]); 51805a9a651SEdgar E. Iglesias } else { 519f0f7e7f7SEdgar E. Iglesias gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tmp_ext, tmp_sr); 52005a9a651SEdgar E. Iglesias } 52105a9a651SEdgar E. Iglesias tcg_temp_free_i32(tmp_sr); 522f0f7e7f7SEdgar E. Iglesias tcg_temp_free_i32(tmp_ext); 523fcf5ef2aSThomas Huth return; 524fcf5ef2aSThomas Huth } 525fcf5ef2aSThomas Huth #endif 526fcf5ef2aSThomas Huth 527fcf5ef2aSThomas Huth if (to) { 528fcf5ef2aSThomas Huth LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); 529fcf5ef2aSThomas Huth switch (sr) { 530aa28e6d4SRichard Henderson case SR_PC: 531fcf5ef2aSThomas Huth break; 532aa28e6d4SRichard Henderson case SR_MSR: 533fcf5ef2aSThomas Huth msr_write(dc, cpu_R[dc->ra]); 534fcf5ef2aSThomas Huth break; 535351527b7SEdgar E. Iglesias case SR_EAR: 536aa28e6d4SRichard Henderson tcg_gen_extu_i32_i64(cpu_ear, cpu_R[dc->ra]); 537aa28e6d4SRichard Henderson break; 538351527b7SEdgar E. Iglesias case SR_ESR: 5396efd5599SRichard Henderson tcg_gen_mov_i32(cpu_esr, cpu_R[dc->ra]); 540aa28e6d4SRichard Henderson break; 541ab6dd380SEdgar E. Iglesias case SR_FSR: 54286017ccfSRichard Henderson tcg_gen_st_i32(cpu_R[dc->ra], 54386017ccfSRichard Henderson cpu_env, offsetof(CPUMBState, fsr)); 544aa28e6d4SRichard Henderson break; 545aa28e6d4SRichard Henderson case SR_BTR: 546ccf628b7SRichard Henderson tcg_gen_st_i32(cpu_R[dc->ra], 547ccf628b7SRichard Henderson cpu_env, offsetof(CPUMBState, btr)); 548aa28e6d4SRichard Henderson break; 549aa28e6d4SRichard Henderson case SR_EDR: 550*39db007eSRichard Henderson tcg_gen_st_i32(cpu_R[dc->ra], 551*39db007eSRichard Henderson cpu_env, offsetof(CPUMBState, edr)); 552fcf5ef2aSThomas Huth break; 553fcf5ef2aSThomas Huth case 0x800: 554cfeea807SEdgar E. Iglesias tcg_gen_st_i32(cpu_R[dc->ra], 555cfeea807SEdgar E. Iglesias cpu_env, offsetof(CPUMBState, slr)); 556fcf5ef2aSThomas Huth break; 557fcf5ef2aSThomas Huth case 0x802: 558cfeea807SEdgar E. Iglesias tcg_gen_st_i32(cpu_R[dc->ra], 559cfeea807SEdgar E. Iglesias cpu_env, offsetof(CPUMBState, shr)); 560fcf5ef2aSThomas Huth break; 561fcf5ef2aSThomas Huth default: 562fcf5ef2aSThomas Huth cpu_abort(CPU(dc->cpu), "unknown mts reg %x\n", sr); 563fcf5ef2aSThomas Huth break; 564fcf5ef2aSThomas Huth } 565fcf5ef2aSThomas Huth } else { 566fcf5ef2aSThomas Huth LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm); 567fcf5ef2aSThomas Huth 568fcf5ef2aSThomas Huth switch (sr) { 569aa28e6d4SRichard Henderson case SR_PC: 570cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc); 571fcf5ef2aSThomas Huth break; 572aa28e6d4SRichard Henderson case SR_MSR: 573fcf5ef2aSThomas Huth msr_read(dc, cpu_R[dc->rd]); 574fcf5ef2aSThomas Huth break; 575351527b7SEdgar E. Iglesias case SR_EAR: 576a1b48e3aSEdgar E. Iglesias if (extended) { 577aa28e6d4SRichard Henderson tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_ear); 578aa28e6d4SRichard Henderson } else { 579aa28e6d4SRichard Henderson tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_ear); 580a1b48e3aSEdgar E. Iglesias } 581aa28e6d4SRichard Henderson break; 582351527b7SEdgar E. Iglesias case SR_ESR: 5836efd5599SRichard Henderson tcg_gen_mov_i32(cpu_R[dc->rd], cpu_esr); 584aa28e6d4SRichard Henderson break; 585351527b7SEdgar E. Iglesias case SR_FSR: 58686017ccfSRichard Henderson tcg_gen_ld_i32(cpu_R[dc->rd], 58786017ccfSRichard Henderson cpu_env, offsetof(CPUMBState, fsr)); 588aa28e6d4SRichard Henderson break; 589351527b7SEdgar E. Iglesias case SR_BTR: 590ccf628b7SRichard Henderson tcg_gen_ld_i32(cpu_R[dc->rd], 591ccf628b7SRichard Henderson cpu_env, offsetof(CPUMBState, btr)); 592aa28e6d4SRichard Henderson break; 5937cdae31dSTong Ho case SR_EDR: 594*39db007eSRichard Henderson tcg_gen_ld_i32(cpu_R[dc->rd], 595*39db007eSRichard Henderson cpu_env, offsetof(CPUMBState, edr)); 596fcf5ef2aSThomas Huth break; 597fcf5ef2aSThomas Huth case 0x800: 598cfeea807SEdgar E. Iglesias tcg_gen_ld_i32(cpu_R[dc->rd], 599cfeea807SEdgar E. Iglesias cpu_env, offsetof(CPUMBState, slr)); 600fcf5ef2aSThomas Huth break; 601fcf5ef2aSThomas Huth case 0x802: 602cfeea807SEdgar E. Iglesias tcg_gen_ld_i32(cpu_R[dc->rd], 603cfeea807SEdgar E. Iglesias cpu_env, offsetof(CPUMBState, shr)); 604fcf5ef2aSThomas Huth break; 605351527b7SEdgar E. Iglesias case 0x2000 ... 0x200c: 606fcf5ef2aSThomas Huth rn = sr & 0xf; 607cfeea807SEdgar E. Iglesias tcg_gen_ld_i32(cpu_R[dc->rd], 608fcf5ef2aSThomas Huth cpu_env, offsetof(CPUMBState, pvr.regs[rn])); 609fcf5ef2aSThomas Huth break; 610fcf5ef2aSThomas Huth default: 611fcf5ef2aSThomas Huth cpu_abort(cs, "unknown mfs reg %x\n", sr); 612fcf5ef2aSThomas Huth break; 613fcf5ef2aSThomas Huth } 614fcf5ef2aSThomas Huth } 615fcf5ef2aSThomas Huth 616fcf5ef2aSThomas Huth if (dc->rd == 0) { 617cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(cpu_R[0], 0); 618fcf5ef2aSThomas Huth } 619fcf5ef2aSThomas Huth } 620fcf5ef2aSThomas Huth 621fcf5ef2aSThomas Huth /* Multiplier unit. */ 622fcf5ef2aSThomas Huth static void dec_mul(DisasContext *dc) 623fcf5ef2aSThomas Huth { 624cfeea807SEdgar E. Iglesias TCGv_i32 tmp; 625fcf5ef2aSThomas Huth unsigned int subcode; 626fcf5ef2aSThomas Huth 6279ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, !dc->cpu->cfg.use_hw_mul)) { 628fcf5ef2aSThomas Huth return; 629fcf5ef2aSThomas Huth } 630fcf5ef2aSThomas Huth 631fcf5ef2aSThomas Huth subcode = dc->imm & 3; 632fcf5ef2aSThomas Huth 633fcf5ef2aSThomas Huth if (dc->type_b) { 634fcf5ef2aSThomas Huth LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm); 635cfeea807SEdgar E. Iglesias tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); 636fcf5ef2aSThomas Huth return; 637fcf5ef2aSThomas Huth } 638fcf5ef2aSThomas Huth 639fcf5ef2aSThomas Huth /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */ 6409b964318SEdgar E. Iglesias if (subcode >= 1 && subcode <= 3 && dc->cpu->cfg.use_hw_mul < 2) { 641fcf5ef2aSThomas Huth /* nop??? */ 642fcf5ef2aSThomas Huth } 643fcf5ef2aSThomas Huth 644cfeea807SEdgar E. Iglesias tmp = tcg_temp_new_i32(); 645fcf5ef2aSThomas Huth switch (subcode) { 646fcf5ef2aSThomas Huth case 0: 647fcf5ef2aSThomas Huth LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); 648cfeea807SEdgar E. Iglesias tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); 649fcf5ef2aSThomas Huth break; 650fcf5ef2aSThomas Huth case 1: 651fcf5ef2aSThomas Huth LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); 652cfeea807SEdgar E. Iglesias tcg_gen_muls2_i32(tmp, cpu_R[dc->rd], 653cfeea807SEdgar E. Iglesias cpu_R[dc->ra], cpu_R[dc->rb]); 654fcf5ef2aSThomas Huth break; 655fcf5ef2aSThomas Huth case 2: 656fcf5ef2aSThomas Huth LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); 657cfeea807SEdgar E. Iglesias tcg_gen_mulsu2_i32(tmp, cpu_R[dc->rd], 658cfeea807SEdgar E. Iglesias cpu_R[dc->ra], cpu_R[dc->rb]); 659fcf5ef2aSThomas Huth break; 660fcf5ef2aSThomas Huth case 3: 661fcf5ef2aSThomas Huth LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); 662cfeea807SEdgar E. Iglesias tcg_gen_mulu2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); 663fcf5ef2aSThomas Huth break; 664fcf5ef2aSThomas Huth default: 665fcf5ef2aSThomas Huth cpu_abort(CPU(dc->cpu), "unknown MUL insn %x\n", subcode); 666fcf5ef2aSThomas Huth break; 667fcf5ef2aSThomas Huth } 668cfeea807SEdgar E. Iglesias tcg_temp_free_i32(tmp); 669fcf5ef2aSThomas Huth } 670fcf5ef2aSThomas Huth 671fcf5ef2aSThomas Huth /* Div unit. */ 672fcf5ef2aSThomas Huth static void dec_div(DisasContext *dc) 673fcf5ef2aSThomas Huth { 674fcf5ef2aSThomas Huth unsigned int u; 675fcf5ef2aSThomas Huth 676fcf5ef2aSThomas Huth u = dc->imm & 2; 677fcf5ef2aSThomas Huth LOG_DIS("div\n"); 678fcf5ef2aSThomas Huth 6799ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, !dc->cpu->cfg.use_div)) { 6809ba8cd45SEdgar E. Iglesias return; 681fcf5ef2aSThomas Huth } 682fcf5ef2aSThomas Huth 683fcf5ef2aSThomas Huth if (u) 684fcf5ef2aSThomas Huth gen_helper_divu(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)), 685fcf5ef2aSThomas Huth cpu_R[dc->ra]); 686fcf5ef2aSThomas Huth else 687fcf5ef2aSThomas Huth gen_helper_divs(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)), 688fcf5ef2aSThomas Huth cpu_R[dc->ra]); 689fcf5ef2aSThomas Huth if (!dc->rd) 690cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(cpu_R[dc->rd], 0); 691fcf5ef2aSThomas Huth } 692fcf5ef2aSThomas Huth 693fcf5ef2aSThomas Huth static void dec_barrel(DisasContext *dc) 694fcf5ef2aSThomas Huth { 695cfeea807SEdgar E. Iglesias TCGv_i32 t0; 696faa48d74SEdgar E. Iglesias unsigned int imm_w, imm_s; 697d09b2585SEdgar E. Iglesias bool s, t, e = false, i = false; 698fcf5ef2aSThomas Huth 6999ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, !dc->cpu->cfg.use_barrel)) { 700fcf5ef2aSThomas Huth return; 701fcf5ef2aSThomas Huth } 702fcf5ef2aSThomas Huth 703faa48d74SEdgar E. Iglesias if (dc->type_b) { 704faa48d74SEdgar E. Iglesias /* Insert and extract are only available in immediate mode. */ 705d09b2585SEdgar E. Iglesias i = extract32(dc->imm, 15, 1); 706faa48d74SEdgar E. Iglesias e = extract32(dc->imm, 14, 1); 707faa48d74SEdgar E. Iglesias } 708e3e84983SEdgar E. Iglesias s = extract32(dc->imm, 10, 1); 709e3e84983SEdgar E. Iglesias t = extract32(dc->imm, 9, 1); 710faa48d74SEdgar E. Iglesias imm_w = extract32(dc->imm, 6, 5); 711faa48d74SEdgar E. Iglesias imm_s = extract32(dc->imm, 0, 5); 712fcf5ef2aSThomas Huth 713faa48d74SEdgar E. Iglesias LOG_DIS("bs%s%s%s r%d r%d r%d\n", 714faa48d74SEdgar E. Iglesias e ? "e" : "", 715fcf5ef2aSThomas Huth s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb); 716fcf5ef2aSThomas Huth 717faa48d74SEdgar E. Iglesias if (e) { 718faa48d74SEdgar E. Iglesias if (imm_w + imm_s > 32 || imm_w == 0) { 719faa48d74SEdgar E. Iglesias /* These inputs have an undefined behavior. */ 720faa48d74SEdgar E. Iglesias qemu_log_mask(LOG_GUEST_ERROR, "bsefi: Bad input w=%d s=%d\n", 721faa48d74SEdgar E. Iglesias imm_w, imm_s); 722faa48d74SEdgar E. Iglesias } else { 723faa48d74SEdgar E. Iglesias tcg_gen_extract_i32(cpu_R[dc->rd], cpu_R[dc->ra], imm_s, imm_w); 724faa48d74SEdgar E. Iglesias } 725d09b2585SEdgar E. Iglesias } else if (i) { 726d09b2585SEdgar E. Iglesias int width = imm_w - imm_s + 1; 727d09b2585SEdgar E. Iglesias 728d09b2585SEdgar E. Iglesias if (imm_w < imm_s) { 729d09b2585SEdgar E. Iglesias /* These inputs have an undefined behavior. */ 730d09b2585SEdgar E. Iglesias qemu_log_mask(LOG_GUEST_ERROR, "bsifi: Bad input w=%d s=%d\n", 731d09b2585SEdgar E. Iglesias imm_w, imm_s); 732d09b2585SEdgar E. Iglesias } else { 733d09b2585SEdgar E. Iglesias tcg_gen_deposit_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_R[dc->ra], 734d09b2585SEdgar E. Iglesias imm_s, width); 735d09b2585SEdgar E. Iglesias } 736faa48d74SEdgar E. Iglesias } else { 737cfeea807SEdgar E. Iglesias t0 = tcg_temp_new_i32(); 738fcf5ef2aSThomas Huth 739cfeea807SEdgar E. Iglesias tcg_gen_mov_i32(t0, *(dec_alu_op_b(dc))); 740cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t0, t0, 31); 741fcf5ef2aSThomas Huth 7422acf6d53SEdgar E. Iglesias if (s) { 743cfeea807SEdgar E. Iglesias tcg_gen_shl_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); 7442acf6d53SEdgar E. Iglesias } else { 7452acf6d53SEdgar E. Iglesias if (t) { 746cfeea807SEdgar E. Iglesias tcg_gen_sar_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); 7472acf6d53SEdgar E. Iglesias } else { 748cfeea807SEdgar E. Iglesias tcg_gen_shr_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); 749fcf5ef2aSThomas Huth } 750fcf5ef2aSThomas Huth } 751cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t0); 7522acf6d53SEdgar E. Iglesias } 753faa48d74SEdgar E. Iglesias } 754fcf5ef2aSThomas Huth 755fcf5ef2aSThomas Huth static void dec_bit(DisasContext *dc) 756fcf5ef2aSThomas Huth { 757fcf5ef2aSThomas Huth CPUState *cs = CPU(dc->cpu); 758cfeea807SEdgar E. Iglesias TCGv_i32 t0; 759fcf5ef2aSThomas Huth unsigned int op; 760fcf5ef2aSThomas Huth 761fcf5ef2aSThomas Huth op = dc->ir & ((1 << 9) - 1); 762fcf5ef2aSThomas Huth switch (op) { 763fcf5ef2aSThomas Huth case 0x21: 764fcf5ef2aSThomas Huth /* src. */ 765cfeea807SEdgar E. Iglesias t0 = tcg_temp_new_i32(); 766fcf5ef2aSThomas Huth 767fcf5ef2aSThomas Huth LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); 7683e0e16aeSRichard Henderson tcg_gen_andi_i32(t0, cpu_msr, MSR_CC); 769fcf5ef2aSThomas Huth write_carry(dc, cpu_R[dc->ra]); 770fcf5ef2aSThomas Huth if (dc->rd) { 771cfeea807SEdgar E. Iglesias tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); 772cfeea807SEdgar E. Iglesias tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->rd], t0); 773fcf5ef2aSThomas Huth } 774cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t0); 775fcf5ef2aSThomas Huth break; 776fcf5ef2aSThomas Huth 777fcf5ef2aSThomas Huth case 0x1: 778fcf5ef2aSThomas Huth case 0x41: 779fcf5ef2aSThomas Huth /* srl. */ 780fcf5ef2aSThomas Huth LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra); 781fcf5ef2aSThomas Huth 782fcf5ef2aSThomas Huth /* Update carry. Note that write carry only looks at the LSB. */ 783fcf5ef2aSThomas Huth write_carry(dc, cpu_R[dc->ra]); 784fcf5ef2aSThomas Huth if (dc->rd) { 785fcf5ef2aSThomas Huth if (op == 0x41) 786cfeea807SEdgar E. Iglesias tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); 787fcf5ef2aSThomas Huth else 788cfeea807SEdgar E. Iglesias tcg_gen_sari_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); 789fcf5ef2aSThomas Huth } 790fcf5ef2aSThomas Huth break; 791fcf5ef2aSThomas Huth case 0x60: 792fcf5ef2aSThomas Huth LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra); 793fcf5ef2aSThomas Huth tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); 794fcf5ef2aSThomas Huth break; 795fcf5ef2aSThomas Huth case 0x61: 796fcf5ef2aSThomas Huth LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra); 797fcf5ef2aSThomas Huth tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); 798fcf5ef2aSThomas Huth break; 799fcf5ef2aSThomas Huth case 0x64: 800fcf5ef2aSThomas Huth case 0x66: 801fcf5ef2aSThomas Huth case 0x74: 802fcf5ef2aSThomas Huth case 0x76: 803fcf5ef2aSThomas Huth /* wdc. */ 804fcf5ef2aSThomas Huth LOG_DIS("wdc r%d\n", dc->ra); 805bdfc1e88SEdgar E. Iglesias trap_userspace(dc, true); 806fcf5ef2aSThomas Huth break; 807fcf5ef2aSThomas Huth case 0x68: 808fcf5ef2aSThomas Huth /* wic. */ 809fcf5ef2aSThomas Huth LOG_DIS("wic r%d\n", dc->ra); 810bdfc1e88SEdgar E. Iglesias trap_userspace(dc, true); 811fcf5ef2aSThomas Huth break; 812fcf5ef2aSThomas Huth case 0xe0: 8139ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, !dc->cpu->cfg.use_pcmp_instr)) { 8149ba8cd45SEdgar E. Iglesias return; 815fcf5ef2aSThomas Huth } 8168fc5239eSEdgar E. Iglesias if (dc->cpu->cfg.use_pcmp_instr) { 8175318420cSRichard Henderson tcg_gen_clzi_i32(cpu_R[dc->rd], cpu_R[dc->ra], 32); 818fcf5ef2aSThomas Huth } 819fcf5ef2aSThomas Huth break; 820fcf5ef2aSThomas Huth case 0x1e0: 821fcf5ef2aSThomas Huth /* swapb */ 822fcf5ef2aSThomas Huth LOG_DIS("swapb r%d r%d\n", dc->rd, dc->ra); 823fcf5ef2aSThomas Huth tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]); 824fcf5ef2aSThomas Huth break; 825fcf5ef2aSThomas Huth case 0x1e2: 826fcf5ef2aSThomas Huth /*swaph */ 827fcf5ef2aSThomas Huth LOG_DIS("swaph r%d r%d\n", dc->rd, dc->ra); 828fcf5ef2aSThomas Huth tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16); 829fcf5ef2aSThomas Huth break; 830fcf5ef2aSThomas Huth default: 831fcf5ef2aSThomas Huth cpu_abort(cs, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n", 832fcf5ef2aSThomas Huth dc->pc, op, dc->rd, dc->ra, dc->rb); 833fcf5ef2aSThomas Huth break; 834fcf5ef2aSThomas Huth } 835fcf5ef2aSThomas Huth } 836fcf5ef2aSThomas Huth 837fcf5ef2aSThomas Huth static inline void sync_jmpstate(DisasContext *dc) 838fcf5ef2aSThomas Huth { 839fcf5ef2aSThomas Huth if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { 840fcf5ef2aSThomas Huth if (dc->jmp == JMP_DIRECT) { 841cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(env_btaken, 1); 842fcf5ef2aSThomas Huth } 843fcf5ef2aSThomas Huth dc->jmp = JMP_INDIRECT; 8440f96e96bSRichard Henderson tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); 845fcf5ef2aSThomas Huth } 846fcf5ef2aSThomas Huth } 847fcf5ef2aSThomas Huth 848fcf5ef2aSThomas Huth static void dec_imm(DisasContext *dc) 849fcf5ef2aSThomas Huth { 850fcf5ef2aSThomas Huth LOG_DIS("imm %x\n", dc->imm << 16); 851cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(env_imm, (dc->imm << 16)); 852fcf5ef2aSThomas Huth dc->tb_flags |= IMM_FLAG; 853fcf5ef2aSThomas Huth dc->clear_imm = 0; 854fcf5ef2aSThomas Huth } 855fcf5ef2aSThomas Huth 856d248e1beSEdgar E. Iglesias static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) 857fcf5ef2aSThomas Huth { 8580e9033c8SEdgar E. Iglesias bool extimm = dc->tb_flags & IMM_FLAG; 8590e9033c8SEdgar E. Iglesias /* Should be set to true if r1 is used by loadstores. */ 8600e9033c8SEdgar E. Iglesias bool stackprot = false; 861403322eaSEdgar E. Iglesias TCGv_i32 t32; 862fcf5ef2aSThomas Huth 863fcf5ef2aSThomas Huth /* All load/stores use ra. */ 864fcf5ef2aSThomas Huth if (dc->ra == 1 && dc->cpu->cfg.stackprot) { 8650e9033c8SEdgar E. Iglesias stackprot = true; 866fcf5ef2aSThomas Huth } 867fcf5ef2aSThomas Huth 868fcf5ef2aSThomas Huth /* Treat the common cases first. */ 869fcf5ef2aSThomas Huth if (!dc->type_b) { 870d248e1beSEdgar E. Iglesias if (ea) { 871d248e1beSEdgar E. Iglesias int addr_size = dc->cpu->cfg.addr_size; 872d248e1beSEdgar E. Iglesias 873d248e1beSEdgar E. Iglesias if (addr_size == 32) { 874d248e1beSEdgar E. Iglesias tcg_gen_extu_i32_tl(t, cpu_R[dc->rb]); 875d248e1beSEdgar E. Iglesias return; 876d248e1beSEdgar E. Iglesias } 877d248e1beSEdgar E. Iglesias 878d248e1beSEdgar E. Iglesias tcg_gen_concat_i32_i64(t, cpu_R[dc->rb], cpu_R[dc->ra]); 879d248e1beSEdgar E. Iglesias if (addr_size < 64) { 880d248e1beSEdgar E. Iglesias /* Mask off out of range bits. */ 881d248e1beSEdgar E. Iglesias tcg_gen_andi_i64(t, t, MAKE_64BIT_MASK(0, addr_size)); 882d248e1beSEdgar E. Iglesias } 883d248e1beSEdgar E. Iglesias return; 884d248e1beSEdgar E. Iglesias } 885d248e1beSEdgar E. Iglesias 8860dc4af5cSEdgar E. Iglesias /* If any of the regs is r0, set t to the value of the other reg. */ 887fcf5ef2aSThomas Huth if (dc->ra == 0) { 888403322eaSEdgar E. Iglesias tcg_gen_extu_i32_tl(t, cpu_R[dc->rb]); 8890dc4af5cSEdgar E. Iglesias return; 890fcf5ef2aSThomas Huth } else if (dc->rb == 0) { 891403322eaSEdgar E. Iglesias tcg_gen_extu_i32_tl(t, cpu_R[dc->ra]); 8920dc4af5cSEdgar E. Iglesias return; 893fcf5ef2aSThomas Huth } 894fcf5ef2aSThomas Huth 895fcf5ef2aSThomas Huth if (dc->rb == 1 && dc->cpu->cfg.stackprot) { 8960e9033c8SEdgar E. Iglesias stackprot = true; 897fcf5ef2aSThomas Huth } 898fcf5ef2aSThomas Huth 899403322eaSEdgar E. Iglesias t32 = tcg_temp_new_i32(); 900403322eaSEdgar E. Iglesias tcg_gen_add_i32(t32, cpu_R[dc->ra], cpu_R[dc->rb]); 901403322eaSEdgar E. Iglesias tcg_gen_extu_i32_tl(t, t32); 902403322eaSEdgar E. Iglesias tcg_temp_free_i32(t32); 903fcf5ef2aSThomas Huth 904fcf5ef2aSThomas Huth if (stackprot) { 9050a87e691SEdgar E. Iglesias gen_helper_stackprot(cpu_env, t); 906fcf5ef2aSThomas Huth } 9070dc4af5cSEdgar E. Iglesias return; 908fcf5ef2aSThomas Huth } 909fcf5ef2aSThomas Huth /* Immediate. */ 910403322eaSEdgar E. Iglesias t32 = tcg_temp_new_i32(); 911fcf5ef2aSThomas Huth if (!extimm) { 912f7a66e3aSEdgar E. Iglesias tcg_gen_addi_i32(t32, cpu_R[dc->ra], (int16_t)dc->imm); 913403322eaSEdgar E. Iglesias } else { 914403322eaSEdgar E. Iglesias tcg_gen_add_i32(t32, cpu_R[dc->ra], *(dec_alu_op_b(dc))); 915403322eaSEdgar E. Iglesias } 916403322eaSEdgar E. Iglesias tcg_gen_extu_i32_tl(t, t32); 917403322eaSEdgar E. Iglesias tcg_temp_free_i32(t32); 918fcf5ef2aSThomas Huth 919fcf5ef2aSThomas Huth if (stackprot) { 9200a87e691SEdgar E. Iglesias gen_helper_stackprot(cpu_env, t); 921fcf5ef2aSThomas Huth } 9220dc4af5cSEdgar E. Iglesias return; 923fcf5ef2aSThomas Huth } 924fcf5ef2aSThomas Huth 925fcf5ef2aSThomas Huth static void dec_load(DisasContext *dc) 926fcf5ef2aSThomas Huth { 927403322eaSEdgar E. Iglesias TCGv_i32 v; 928403322eaSEdgar E. Iglesias TCGv addr; 9298534063aSEdgar E. Iglesias unsigned int size; 930d248e1beSEdgar E. Iglesias bool rev = false, ex = false, ea = false; 931d248e1beSEdgar E. Iglesias int mem_index = cpu_mmu_index(&dc->cpu->env, false); 93214776ab5STony Nguyen MemOp mop; 933fcf5ef2aSThomas Huth 934fcf5ef2aSThomas Huth mop = dc->opcode & 3; 935fcf5ef2aSThomas Huth size = 1 << mop; 936fcf5ef2aSThomas Huth if (!dc->type_b) { 937d248e1beSEdgar E. Iglesias ea = extract32(dc->ir, 7, 1); 9388534063aSEdgar E. Iglesias rev = extract32(dc->ir, 9, 1); 9398534063aSEdgar E. Iglesias ex = extract32(dc->ir, 10, 1); 940fcf5ef2aSThomas Huth } 941fcf5ef2aSThomas Huth mop |= MO_TE; 942fcf5ef2aSThomas Huth if (rev) { 943fcf5ef2aSThomas Huth mop ^= MO_BSWAP; 944fcf5ef2aSThomas Huth } 945fcf5ef2aSThomas Huth 9469ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, size > 4)) { 947fcf5ef2aSThomas Huth return; 948fcf5ef2aSThomas Huth } 949fcf5ef2aSThomas Huth 950d248e1beSEdgar E. Iglesias if (trap_userspace(dc, ea)) { 951d248e1beSEdgar E. Iglesias return; 952d248e1beSEdgar E. Iglesias } 953d248e1beSEdgar E. Iglesias 954d248e1beSEdgar E. Iglesias LOG_DIS("l%d%s%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "", 955d248e1beSEdgar E. Iglesias ex ? "x" : "", 956d248e1beSEdgar E. Iglesias ea ? "ea" : ""); 957fcf5ef2aSThomas Huth 958fcf5ef2aSThomas Huth t_sync_flags(dc); 959403322eaSEdgar E. Iglesias addr = tcg_temp_new(); 960d248e1beSEdgar E. Iglesias compute_ldst_addr(dc, ea, addr); 961d248e1beSEdgar E. Iglesias /* Extended addressing bypasses the MMU. */ 962d248e1beSEdgar E. Iglesias mem_index = ea ? MMU_NOMMU_IDX : mem_index; 963fcf5ef2aSThomas Huth 964fcf5ef2aSThomas Huth /* 965fcf5ef2aSThomas Huth * When doing reverse accesses we need to do two things. 966fcf5ef2aSThomas Huth * 967fcf5ef2aSThomas Huth * 1. Reverse the address wrt endianness. 968fcf5ef2aSThomas Huth * 2. Byteswap the data lanes on the way back into the CPU core. 969fcf5ef2aSThomas Huth */ 970fcf5ef2aSThomas Huth if (rev && size != 4) { 971fcf5ef2aSThomas Huth /* Endian reverse the address. t is addr. */ 972fcf5ef2aSThomas Huth switch (size) { 973fcf5ef2aSThomas Huth case 1: 974fcf5ef2aSThomas Huth { 975a6338015SEdgar E. Iglesias tcg_gen_xori_tl(addr, addr, 3); 976fcf5ef2aSThomas Huth break; 977fcf5ef2aSThomas Huth } 978fcf5ef2aSThomas Huth 979fcf5ef2aSThomas Huth case 2: 980fcf5ef2aSThomas Huth /* 00 -> 10 981fcf5ef2aSThomas Huth 10 -> 00. */ 982403322eaSEdgar E. Iglesias tcg_gen_xori_tl(addr, addr, 2); 983fcf5ef2aSThomas Huth break; 984fcf5ef2aSThomas Huth default: 985fcf5ef2aSThomas Huth cpu_abort(CPU(dc->cpu), "Invalid reverse size\n"); 986fcf5ef2aSThomas Huth break; 987fcf5ef2aSThomas Huth } 988fcf5ef2aSThomas Huth } 989fcf5ef2aSThomas Huth 990fcf5ef2aSThomas Huth /* lwx does not throw unaligned access errors, so force alignment */ 991fcf5ef2aSThomas Huth if (ex) { 992403322eaSEdgar E. Iglesias tcg_gen_andi_tl(addr, addr, ~3); 993fcf5ef2aSThomas Huth } 994fcf5ef2aSThomas Huth 995fcf5ef2aSThomas Huth /* If we get a fault on a dslot, the jmpstate better be in sync. */ 996fcf5ef2aSThomas Huth sync_jmpstate(dc); 997fcf5ef2aSThomas Huth 998fcf5ef2aSThomas Huth /* Verify alignment if needed. */ 999fcf5ef2aSThomas Huth /* 1000fcf5ef2aSThomas Huth * Microblaze gives MMU faults priority over faults due to 1001fcf5ef2aSThomas Huth * unaligned addresses. That's why we speculatively do the load 1002fcf5ef2aSThomas Huth * into v. If the load succeeds, we verify alignment of the 1003fcf5ef2aSThomas Huth * address and if that succeeds we write into the destination reg. 1004fcf5ef2aSThomas Huth */ 1005cfeea807SEdgar E. Iglesias v = tcg_temp_new_i32(); 1006d248e1beSEdgar E. Iglesias tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); 1007fcf5ef2aSThomas Huth 10081507e5f6SEdgar E. Iglesias if (dc->cpu->cfg.unaligned_exceptions && size > 1) { 1009a6338015SEdgar E. Iglesias TCGv_i32 t0 = tcg_const_i32(0); 1010a6338015SEdgar E. Iglesias TCGv_i32 treg = tcg_const_i32(dc->rd); 1011a6338015SEdgar E. Iglesias TCGv_i32 tsize = tcg_const_i32(size - 1); 1012a6338015SEdgar E. Iglesias 10130f96e96bSRichard Henderson tcg_gen_movi_i32(cpu_pc, dc->pc); 1014a6338015SEdgar E. Iglesias gen_helper_memalign(cpu_env, addr, treg, t0, tsize); 1015a6338015SEdgar E. Iglesias 1016a6338015SEdgar E. Iglesias tcg_temp_free_i32(t0); 1017a6338015SEdgar E. Iglesias tcg_temp_free_i32(treg); 1018a6338015SEdgar E. Iglesias tcg_temp_free_i32(tsize); 1019fcf5ef2aSThomas Huth } 1020fcf5ef2aSThomas Huth 1021fcf5ef2aSThomas Huth if (ex) { 1022403322eaSEdgar E. Iglesias tcg_gen_mov_tl(env_res_addr, addr); 1023cfeea807SEdgar E. Iglesias tcg_gen_mov_i32(env_res_val, v); 1024fcf5ef2aSThomas Huth } 1025fcf5ef2aSThomas Huth if (dc->rd) { 1026cfeea807SEdgar E. Iglesias tcg_gen_mov_i32(cpu_R[dc->rd], v); 1027fcf5ef2aSThomas Huth } 1028cfeea807SEdgar E. Iglesias tcg_temp_free_i32(v); 1029fcf5ef2aSThomas Huth 1030fcf5ef2aSThomas Huth if (ex) { /* lwx */ 1031fcf5ef2aSThomas Huth /* no support for AXI exclusive so always clear C */ 1032fcf5ef2aSThomas Huth write_carryi(dc, 0); 1033fcf5ef2aSThomas Huth } 1034fcf5ef2aSThomas Huth 1035403322eaSEdgar E. Iglesias tcg_temp_free(addr); 1036fcf5ef2aSThomas Huth } 1037fcf5ef2aSThomas Huth 1038fcf5ef2aSThomas Huth static void dec_store(DisasContext *dc) 1039fcf5ef2aSThomas Huth { 1040403322eaSEdgar E. Iglesias TCGv addr; 1041fcf5ef2aSThomas Huth TCGLabel *swx_skip = NULL; 1042b51b3d43SEdgar E. Iglesias unsigned int size; 1043d248e1beSEdgar E. Iglesias bool rev = false, ex = false, ea = false; 1044d248e1beSEdgar E. Iglesias int mem_index = cpu_mmu_index(&dc->cpu->env, false); 104514776ab5STony Nguyen MemOp mop; 1046fcf5ef2aSThomas Huth 1047fcf5ef2aSThomas Huth mop = dc->opcode & 3; 1048fcf5ef2aSThomas Huth size = 1 << mop; 1049fcf5ef2aSThomas Huth if (!dc->type_b) { 1050d248e1beSEdgar E. Iglesias ea = extract32(dc->ir, 7, 1); 1051b51b3d43SEdgar E. Iglesias rev = extract32(dc->ir, 9, 1); 1052b51b3d43SEdgar E. Iglesias ex = extract32(dc->ir, 10, 1); 1053fcf5ef2aSThomas Huth } 1054fcf5ef2aSThomas Huth mop |= MO_TE; 1055fcf5ef2aSThomas Huth if (rev) { 1056fcf5ef2aSThomas Huth mop ^= MO_BSWAP; 1057fcf5ef2aSThomas Huth } 1058fcf5ef2aSThomas Huth 10599ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, size > 4)) { 1060fcf5ef2aSThomas Huth return; 1061fcf5ef2aSThomas Huth } 1062fcf5ef2aSThomas Huth 1063d248e1beSEdgar E. Iglesias trap_userspace(dc, ea); 1064d248e1beSEdgar E. Iglesias 1065d248e1beSEdgar E. Iglesias LOG_DIS("s%d%s%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "", 1066d248e1beSEdgar E. Iglesias ex ? "x" : "", 1067d248e1beSEdgar E. Iglesias ea ? "ea" : ""); 1068fcf5ef2aSThomas Huth t_sync_flags(dc); 1069fcf5ef2aSThomas Huth /* If we get a fault on a dslot, the jmpstate better be in sync. */ 1070fcf5ef2aSThomas Huth sync_jmpstate(dc); 10710dc4af5cSEdgar E. Iglesias /* SWX needs a temp_local. */ 1072403322eaSEdgar E. Iglesias addr = ex ? tcg_temp_local_new() : tcg_temp_new(); 1073d248e1beSEdgar E. Iglesias compute_ldst_addr(dc, ea, addr); 1074d248e1beSEdgar E. Iglesias /* Extended addressing bypasses the MMU. */ 1075d248e1beSEdgar E. Iglesias mem_index = ea ? MMU_NOMMU_IDX : mem_index; 1076fcf5ef2aSThomas Huth 1077fcf5ef2aSThomas Huth if (ex) { /* swx */ 1078cfeea807SEdgar E. Iglesias TCGv_i32 tval; 1079fcf5ef2aSThomas Huth 1080fcf5ef2aSThomas Huth /* swx does not throw unaligned access errors, so force alignment */ 1081403322eaSEdgar E. Iglesias tcg_gen_andi_tl(addr, addr, ~3); 1082fcf5ef2aSThomas Huth 1083fcf5ef2aSThomas Huth write_carryi(dc, 1); 1084fcf5ef2aSThomas Huth swx_skip = gen_new_label(); 1085403322eaSEdgar E. Iglesias tcg_gen_brcond_tl(TCG_COND_NE, env_res_addr, addr, swx_skip); 1086fcf5ef2aSThomas Huth 1087071cdc67SEdgar E. Iglesias /* 1088071cdc67SEdgar E. Iglesias * Compare the value loaded at lwx with current contents of 1089071cdc67SEdgar E. Iglesias * the reserved location. 1090071cdc67SEdgar E. Iglesias */ 1091cfeea807SEdgar E. Iglesias tval = tcg_temp_new_i32(); 1092071cdc67SEdgar E. Iglesias 1093071cdc67SEdgar E. Iglesias tcg_gen_atomic_cmpxchg_i32(tval, addr, env_res_val, 1094071cdc67SEdgar E. Iglesias cpu_R[dc->rd], mem_index, 1095071cdc67SEdgar E. Iglesias mop); 1096071cdc67SEdgar E. Iglesias 1097cfeea807SEdgar E. Iglesias tcg_gen_brcond_i32(TCG_COND_NE, env_res_val, tval, swx_skip); 1098fcf5ef2aSThomas Huth write_carryi(dc, 0); 1099cfeea807SEdgar E. Iglesias tcg_temp_free_i32(tval); 1100fcf5ef2aSThomas Huth } 1101fcf5ef2aSThomas Huth 1102fcf5ef2aSThomas Huth if (rev && size != 4) { 1103fcf5ef2aSThomas Huth /* Endian reverse the address. t is addr. */ 1104fcf5ef2aSThomas Huth switch (size) { 1105fcf5ef2aSThomas Huth case 1: 1106fcf5ef2aSThomas Huth { 1107a6338015SEdgar E. Iglesias tcg_gen_xori_tl(addr, addr, 3); 1108fcf5ef2aSThomas Huth break; 1109fcf5ef2aSThomas Huth } 1110fcf5ef2aSThomas Huth 1111fcf5ef2aSThomas Huth case 2: 1112fcf5ef2aSThomas Huth /* 00 -> 10 1113fcf5ef2aSThomas Huth 10 -> 00. */ 1114fcf5ef2aSThomas Huth /* Force addr into the temp. */ 1115403322eaSEdgar E. Iglesias tcg_gen_xori_tl(addr, addr, 2); 1116fcf5ef2aSThomas Huth break; 1117fcf5ef2aSThomas Huth default: 1118fcf5ef2aSThomas Huth cpu_abort(CPU(dc->cpu), "Invalid reverse size\n"); 1119fcf5ef2aSThomas Huth break; 1120fcf5ef2aSThomas Huth } 1121fcf5ef2aSThomas Huth } 1122071cdc67SEdgar E. Iglesias 1123071cdc67SEdgar E. Iglesias if (!ex) { 1124d248e1beSEdgar E. Iglesias tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, mem_index, mop); 1125071cdc67SEdgar E. Iglesias } 1126fcf5ef2aSThomas Huth 1127fcf5ef2aSThomas Huth /* Verify alignment if needed. */ 11281507e5f6SEdgar E. Iglesias if (dc->cpu->cfg.unaligned_exceptions && size > 1) { 1129a6338015SEdgar E. Iglesias TCGv_i32 t1 = tcg_const_i32(1); 1130a6338015SEdgar E. Iglesias TCGv_i32 treg = tcg_const_i32(dc->rd); 1131a6338015SEdgar E. Iglesias TCGv_i32 tsize = tcg_const_i32(size - 1); 1132a6338015SEdgar E. Iglesias 11330f96e96bSRichard Henderson tcg_gen_movi_i32(cpu_pc, dc->pc); 1134fcf5ef2aSThomas Huth /* FIXME: if the alignment is wrong, we should restore the value 1135fcf5ef2aSThomas Huth * in memory. One possible way to achieve this is to probe 1136fcf5ef2aSThomas Huth * the MMU prior to the memaccess, thay way we could put 1137fcf5ef2aSThomas Huth * the alignment checks in between the probe and the mem 1138fcf5ef2aSThomas Huth * access. 1139fcf5ef2aSThomas Huth */ 1140a6338015SEdgar E. Iglesias gen_helper_memalign(cpu_env, addr, treg, t1, tsize); 1141a6338015SEdgar E. Iglesias 1142a6338015SEdgar E. Iglesias tcg_temp_free_i32(t1); 1143a6338015SEdgar E. Iglesias tcg_temp_free_i32(treg); 1144a6338015SEdgar E. Iglesias tcg_temp_free_i32(tsize); 1145fcf5ef2aSThomas Huth } 1146fcf5ef2aSThomas Huth 1147fcf5ef2aSThomas Huth if (ex) { 1148fcf5ef2aSThomas Huth gen_set_label(swx_skip); 1149fcf5ef2aSThomas Huth } 1150fcf5ef2aSThomas Huth 1151403322eaSEdgar E. Iglesias tcg_temp_free(addr); 1152fcf5ef2aSThomas Huth } 1153fcf5ef2aSThomas Huth 1154fcf5ef2aSThomas Huth static inline void eval_cc(DisasContext *dc, unsigned int cc, 11559e6e1828SEdgar E. Iglesias TCGv_i32 d, TCGv_i32 a) 1156fcf5ef2aSThomas Huth { 1157d89b86e9SEdgar E. Iglesias static const int mb_to_tcg_cc[] = { 1158d89b86e9SEdgar E. Iglesias [CC_EQ] = TCG_COND_EQ, 1159d89b86e9SEdgar E. Iglesias [CC_NE] = TCG_COND_NE, 1160d89b86e9SEdgar E. Iglesias [CC_LT] = TCG_COND_LT, 1161d89b86e9SEdgar E. Iglesias [CC_LE] = TCG_COND_LE, 1162d89b86e9SEdgar E. Iglesias [CC_GE] = TCG_COND_GE, 1163d89b86e9SEdgar E. Iglesias [CC_GT] = TCG_COND_GT, 1164d89b86e9SEdgar E. Iglesias }; 1165d89b86e9SEdgar E. Iglesias 1166fcf5ef2aSThomas Huth switch (cc) { 1167fcf5ef2aSThomas Huth case CC_EQ: 1168fcf5ef2aSThomas Huth case CC_NE: 1169fcf5ef2aSThomas Huth case CC_LT: 1170fcf5ef2aSThomas Huth case CC_LE: 1171fcf5ef2aSThomas Huth case CC_GE: 1172fcf5ef2aSThomas Huth case CC_GT: 11739e6e1828SEdgar E. Iglesias tcg_gen_setcondi_i32(mb_to_tcg_cc[cc], d, a, 0); 1174fcf5ef2aSThomas Huth break; 1175fcf5ef2aSThomas Huth default: 1176fcf5ef2aSThomas Huth cpu_abort(CPU(dc->cpu), "Unknown condition code %x.\n", cc); 1177fcf5ef2aSThomas Huth break; 1178fcf5ef2aSThomas Huth } 1179fcf5ef2aSThomas Huth } 1180fcf5ef2aSThomas Huth 11810f96e96bSRichard Henderson static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) 1182fcf5ef2aSThomas Huth { 11830f96e96bSRichard Henderson TCGv_i32 zero = tcg_const_i32(0); 1184e956caf2SEdgar E. Iglesias 11850f96e96bSRichard Henderson tcg_gen_movcond_i32(TCG_COND_NE, cpu_pc, 11860f96e96bSRichard Henderson env_btaken, zero, 1187e956caf2SEdgar E. Iglesias pc_true, pc_false); 1188e956caf2SEdgar E. Iglesias 11890f96e96bSRichard Henderson tcg_temp_free_i32(zero); 1190fcf5ef2aSThomas Huth } 1191fcf5ef2aSThomas Huth 1192f91c60f0SEdgar E. Iglesias static void dec_setup_dslot(DisasContext *dc) 1193f91c60f0SEdgar E. Iglesias { 1194f91c60f0SEdgar E. Iglesias TCGv_i32 tmp = tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)); 1195f91c60f0SEdgar E. Iglesias 1196f91c60f0SEdgar E. Iglesias dc->delayed_branch = 2; 1197f91c60f0SEdgar E. Iglesias dc->tb_flags |= D_FLAG; 1198f91c60f0SEdgar E. Iglesias 1199f91c60f0SEdgar E. Iglesias tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, bimm)); 1200f91c60f0SEdgar E. Iglesias tcg_temp_free_i32(tmp); 1201f91c60f0SEdgar E. Iglesias } 1202f91c60f0SEdgar E. Iglesias 1203fcf5ef2aSThomas Huth static void dec_bcc(DisasContext *dc) 1204fcf5ef2aSThomas Huth { 1205fcf5ef2aSThomas Huth unsigned int cc; 1206fcf5ef2aSThomas Huth unsigned int dslot; 1207fcf5ef2aSThomas Huth 1208fcf5ef2aSThomas Huth cc = EXTRACT_FIELD(dc->ir, 21, 23); 1209fcf5ef2aSThomas Huth dslot = dc->ir & (1 << 25); 1210fcf5ef2aSThomas Huth LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm); 1211fcf5ef2aSThomas Huth 1212fcf5ef2aSThomas Huth dc->delayed_branch = 1; 1213fcf5ef2aSThomas Huth if (dslot) { 1214f91c60f0SEdgar E. Iglesias dec_setup_dslot(dc); 1215fcf5ef2aSThomas Huth } 1216fcf5ef2aSThomas Huth 1217fcf5ef2aSThomas Huth if (dec_alu_op_b_is_small_imm(dc)) { 1218fcf5ef2aSThomas Huth int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */ 1219fcf5ef2aSThomas Huth 12200f96e96bSRichard Henderson tcg_gen_movi_i32(cpu_btarget, dc->pc + offset); 1221fcf5ef2aSThomas Huth dc->jmp = JMP_DIRECT_CC; 1222fcf5ef2aSThomas Huth dc->jmp_pc = dc->pc + offset; 1223fcf5ef2aSThomas Huth } else { 1224fcf5ef2aSThomas Huth dc->jmp = JMP_INDIRECT; 12250f96e96bSRichard Henderson tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); 1226fcf5ef2aSThomas Huth } 12279e6e1828SEdgar E. Iglesias eval_cc(dc, cc, env_btaken, cpu_R[dc->ra]); 1228fcf5ef2aSThomas Huth } 1229fcf5ef2aSThomas Huth 1230fcf5ef2aSThomas Huth static void dec_br(DisasContext *dc) 1231fcf5ef2aSThomas Huth { 1232fcf5ef2aSThomas Huth unsigned int dslot, link, abs, mbar; 1233fcf5ef2aSThomas Huth 1234fcf5ef2aSThomas Huth dslot = dc->ir & (1 << 20); 1235fcf5ef2aSThomas Huth abs = dc->ir & (1 << 19); 1236fcf5ef2aSThomas Huth link = dc->ir & (1 << 18); 1237fcf5ef2aSThomas Huth 1238fcf5ef2aSThomas Huth /* Memory barrier. */ 1239fcf5ef2aSThomas Huth mbar = (dc->ir >> 16) & 31; 1240fcf5ef2aSThomas Huth if (mbar == 2 && dc->imm == 4) { 1241badcbf9dSEdgar E. Iglesias uint16_t mbar_imm = dc->rd; 1242badcbf9dSEdgar E. Iglesias 12436f3c458bSEdgar E. Iglesias LOG_DIS("mbar %d\n", mbar_imm); 12446f3c458bSEdgar E. Iglesias 12453f172744SEdgar E. Iglesias /* Data access memory barrier. */ 12463f172744SEdgar E. Iglesias if ((mbar_imm & 2) == 0) { 12473f172744SEdgar E. Iglesias tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); 12483f172744SEdgar E. Iglesias } 12493f172744SEdgar E. Iglesias 1250fcf5ef2aSThomas Huth /* mbar IMM & 16 decodes to sleep. */ 1251badcbf9dSEdgar E. Iglesias if (mbar_imm & 16) { 1252fcf5ef2aSThomas Huth TCGv_i32 tmp_hlt = tcg_const_i32(EXCP_HLT); 1253fcf5ef2aSThomas Huth TCGv_i32 tmp_1 = tcg_const_i32(1); 1254fcf5ef2aSThomas Huth 1255fcf5ef2aSThomas Huth LOG_DIS("sleep\n"); 1256fcf5ef2aSThomas Huth 1257b4919e7dSEdgar E. Iglesias if (trap_userspace(dc, true)) { 1258b4919e7dSEdgar E. Iglesias /* Sleep is a privileged instruction. */ 1259b4919e7dSEdgar E. Iglesias return; 1260b4919e7dSEdgar E. Iglesias } 1261b4919e7dSEdgar E. Iglesias 1262fcf5ef2aSThomas Huth t_sync_flags(dc); 1263fcf5ef2aSThomas Huth tcg_gen_st_i32(tmp_1, cpu_env, 1264fcf5ef2aSThomas Huth -offsetof(MicroBlazeCPU, env) 1265fcf5ef2aSThomas Huth +offsetof(CPUState, halted)); 12660f96e96bSRichard Henderson tcg_gen_movi_i32(cpu_pc, dc->pc + 4); 1267fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, tmp_hlt); 1268fcf5ef2aSThomas Huth tcg_temp_free_i32(tmp_hlt); 1269fcf5ef2aSThomas Huth tcg_temp_free_i32(tmp_1); 1270fcf5ef2aSThomas Huth return; 1271fcf5ef2aSThomas Huth } 1272fcf5ef2aSThomas Huth /* Break the TB. */ 1273fcf5ef2aSThomas Huth dc->cpustate_changed = 1; 1274fcf5ef2aSThomas Huth return; 1275fcf5ef2aSThomas Huth } 1276fcf5ef2aSThomas Huth 1277fcf5ef2aSThomas Huth LOG_DIS("br%s%s%s%s imm=%x\n", 1278fcf5ef2aSThomas Huth abs ? "a" : "", link ? "l" : "", 1279fcf5ef2aSThomas Huth dc->type_b ? "i" : "", dslot ? "d" : "", 1280fcf5ef2aSThomas Huth dc->imm); 1281fcf5ef2aSThomas Huth 1282fcf5ef2aSThomas Huth dc->delayed_branch = 1; 1283fcf5ef2aSThomas Huth if (dslot) { 1284f91c60f0SEdgar E. Iglesias dec_setup_dslot(dc); 1285fcf5ef2aSThomas Huth } 1286fcf5ef2aSThomas Huth if (link && dc->rd) 1287cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc); 1288fcf5ef2aSThomas Huth 1289fcf5ef2aSThomas Huth dc->jmp = JMP_INDIRECT; 1290fcf5ef2aSThomas Huth if (abs) { 1291cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(env_btaken, 1); 12920f96e96bSRichard Henderson tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc))); 1293fcf5ef2aSThomas Huth if (link && !dslot) { 1294fcf5ef2aSThomas Huth if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18)) 1295fcf5ef2aSThomas Huth t_gen_raise_exception(dc, EXCP_BREAK); 1296fcf5ef2aSThomas Huth if (dc->imm == 0) { 1297bdfc1e88SEdgar E. Iglesias if (trap_userspace(dc, true)) { 1298fcf5ef2aSThomas Huth return; 1299fcf5ef2aSThomas Huth } 1300fcf5ef2aSThomas Huth 1301fcf5ef2aSThomas Huth t_gen_raise_exception(dc, EXCP_DEBUG); 1302fcf5ef2aSThomas Huth } 1303fcf5ef2aSThomas Huth } 1304fcf5ef2aSThomas Huth } else { 1305fcf5ef2aSThomas Huth if (dec_alu_op_b_is_small_imm(dc)) { 1306fcf5ef2aSThomas Huth dc->jmp = JMP_DIRECT; 1307fcf5ef2aSThomas Huth dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm); 1308fcf5ef2aSThomas Huth } else { 1309cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(env_btaken, 1); 13100f96e96bSRichard Henderson tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc); 1311fcf5ef2aSThomas Huth } 1312fcf5ef2aSThomas Huth } 1313fcf5ef2aSThomas Huth } 1314fcf5ef2aSThomas Huth 1315fcf5ef2aSThomas Huth static inline void do_rti(DisasContext *dc) 1316fcf5ef2aSThomas Huth { 1317cfeea807SEdgar E. Iglesias TCGv_i32 t0, t1; 1318cfeea807SEdgar E. Iglesias t0 = tcg_temp_new_i32(); 1319cfeea807SEdgar E. Iglesias t1 = tcg_temp_new_i32(); 13203e0e16aeSRichard Henderson tcg_gen_mov_i32(t1, cpu_msr); 13210a22f8cfSEdgar E. Iglesias tcg_gen_shri_i32(t0, t1, 1); 13220a22f8cfSEdgar E. Iglesias tcg_gen_ori_i32(t1, t1, MSR_IE); 1323cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); 1324fcf5ef2aSThomas Huth 1325cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); 1326cfeea807SEdgar E. Iglesias tcg_gen_or_i32(t1, t1, t0); 1327fcf5ef2aSThomas Huth msr_write(dc, t1); 1328cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t1); 1329cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t0); 1330fcf5ef2aSThomas Huth dc->tb_flags &= ~DRTI_FLAG; 1331fcf5ef2aSThomas Huth } 1332fcf5ef2aSThomas Huth 1333fcf5ef2aSThomas Huth static inline void do_rtb(DisasContext *dc) 1334fcf5ef2aSThomas Huth { 1335cfeea807SEdgar E. Iglesias TCGv_i32 t0, t1; 1336cfeea807SEdgar E. Iglesias t0 = tcg_temp_new_i32(); 1337cfeea807SEdgar E. Iglesias t1 = tcg_temp_new_i32(); 13383e0e16aeSRichard Henderson tcg_gen_mov_i32(t1, cpu_msr); 13390a22f8cfSEdgar E. Iglesias tcg_gen_andi_i32(t1, t1, ~MSR_BIP); 1340cfeea807SEdgar E. Iglesias tcg_gen_shri_i32(t0, t1, 1); 1341cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); 1342fcf5ef2aSThomas Huth 1343cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); 1344cfeea807SEdgar E. Iglesias tcg_gen_or_i32(t1, t1, t0); 1345fcf5ef2aSThomas Huth msr_write(dc, t1); 1346cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t1); 1347cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t0); 1348fcf5ef2aSThomas Huth dc->tb_flags &= ~DRTB_FLAG; 1349fcf5ef2aSThomas Huth } 1350fcf5ef2aSThomas Huth 1351fcf5ef2aSThomas Huth static inline void do_rte(DisasContext *dc) 1352fcf5ef2aSThomas Huth { 1353cfeea807SEdgar E. Iglesias TCGv_i32 t0, t1; 1354cfeea807SEdgar E. Iglesias t0 = tcg_temp_new_i32(); 1355cfeea807SEdgar E. Iglesias t1 = tcg_temp_new_i32(); 1356fcf5ef2aSThomas Huth 13573e0e16aeSRichard Henderson tcg_gen_mov_i32(t1, cpu_msr); 13580a22f8cfSEdgar E. Iglesias tcg_gen_ori_i32(t1, t1, MSR_EE); 1359cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t1, t1, ~MSR_EIP); 1360cfeea807SEdgar E. Iglesias tcg_gen_shri_i32(t0, t1, 1); 1361cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); 1362fcf5ef2aSThomas Huth 1363cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); 1364cfeea807SEdgar E. Iglesias tcg_gen_or_i32(t1, t1, t0); 1365fcf5ef2aSThomas Huth msr_write(dc, t1); 1366cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t1); 1367cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t0); 1368fcf5ef2aSThomas Huth dc->tb_flags &= ~DRTE_FLAG; 1369fcf5ef2aSThomas Huth } 1370fcf5ef2aSThomas Huth 1371fcf5ef2aSThomas Huth static void dec_rts(DisasContext *dc) 1372fcf5ef2aSThomas Huth { 1373fcf5ef2aSThomas Huth unsigned int b_bit, i_bit, e_bit; 1374fcf5ef2aSThomas Huth 1375fcf5ef2aSThomas Huth i_bit = dc->ir & (1 << 21); 1376fcf5ef2aSThomas Huth b_bit = dc->ir & (1 << 22); 1377fcf5ef2aSThomas Huth e_bit = dc->ir & (1 << 23); 1378fcf5ef2aSThomas Huth 1379bdfc1e88SEdgar E. Iglesias if (trap_userspace(dc, i_bit || b_bit || e_bit)) { 1380bdfc1e88SEdgar E. Iglesias return; 1381bdfc1e88SEdgar E. Iglesias } 1382bdfc1e88SEdgar E. Iglesias 1383f91c60f0SEdgar E. Iglesias dec_setup_dslot(dc); 1384fcf5ef2aSThomas Huth 1385fcf5ef2aSThomas Huth if (i_bit) { 1386fcf5ef2aSThomas Huth LOG_DIS("rtid ir=%x\n", dc->ir); 1387fcf5ef2aSThomas Huth dc->tb_flags |= DRTI_FLAG; 1388fcf5ef2aSThomas Huth } else if (b_bit) { 1389fcf5ef2aSThomas Huth LOG_DIS("rtbd ir=%x\n", dc->ir); 1390fcf5ef2aSThomas Huth dc->tb_flags |= DRTB_FLAG; 1391fcf5ef2aSThomas Huth } else if (e_bit) { 1392fcf5ef2aSThomas Huth LOG_DIS("rted ir=%x\n", dc->ir); 1393fcf5ef2aSThomas Huth dc->tb_flags |= DRTE_FLAG; 1394fcf5ef2aSThomas Huth } else 1395fcf5ef2aSThomas Huth LOG_DIS("rts ir=%x\n", dc->ir); 1396fcf5ef2aSThomas Huth 1397fcf5ef2aSThomas Huth dc->jmp = JMP_INDIRECT; 1398cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(env_btaken, 1); 13990f96e96bSRichard Henderson tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); 1400fcf5ef2aSThomas Huth } 1401fcf5ef2aSThomas Huth 1402fcf5ef2aSThomas Huth static int dec_check_fpuv2(DisasContext *dc) 1403fcf5ef2aSThomas Huth { 1404fcf5ef2aSThomas Huth if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { 14056efd5599SRichard Henderson tcg_gen_movi_i32(cpu_esr, ESR_EC_FPU); 1406fcf5ef2aSThomas Huth t_gen_raise_exception(dc, EXCP_HW_EXCP); 1407fcf5ef2aSThomas Huth } 14082016a6a7SJoe Komlodi return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0; 1409fcf5ef2aSThomas Huth } 1410fcf5ef2aSThomas Huth 1411fcf5ef2aSThomas Huth static void dec_fpu(DisasContext *dc) 1412fcf5ef2aSThomas Huth { 1413fcf5ef2aSThomas Huth unsigned int fpu_insn; 1414fcf5ef2aSThomas Huth 14159ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, !dc->cpu->cfg.use_fpu)) { 1416fcf5ef2aSThomas Huth return; 1417fcf5ef2aSThomas Huth } 1418fcf5ef2aSThomas Huth 1419fcf5ef2aSThomas Huth fpu_insn = (dc->ir >> 7) & 7; 1420fcf5ef2aSThomas Huth 1421fcf5ef2aSThomas Huth switch (fpu_insn) { 1422fcf5ef2aSThomas Huth case 0: 1423fcf5ef2aSThomas Huth gen_helper_fadd(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], 1424fcf5ef2aSThomas Huth cpu_R[dc->rb]); 1425fcf5ef2aSThomas Huth break; 1426fcf5ef2aSThomas Huth 1427fcf5ef2aSThomas Huth case 1: 1428fcf5ef2aSThomas Huth gen_helper_frsub(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], 1429fcf5ef2aSThomas Huth cpu_R[dc->rb]); 1430fcf5ef2aSThomas Huth break; 1431fcf5ef2aSThomas Huth 1432fcf5ef2aSThomas Huth case 2: 1433fcf5ef2aSThomas Huth gen_helper_fmul(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], 1434fcf5ef2aSThomas Huth cpu_R[dc->rb]); 1435fcf5ef2aSThomas Huth break; 1436fcf5ef2aSThomas Huth 1437fcf5ef2aSThomas Huth case 3: 1438fcf5ef2aSThomas Huth gen_helper_fdiv(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], 1439fcf5ef2aSThomas Huth cpu_R[dc->rb]); 1440fcf5ef2aSThomas Huth break; 1441fcf5ef2aSThomas Huth 1442fcf5ef2aSThomas Huth case 4: 1443fcf5ef2aSThomas Huth switch ((dc->ir >> 4) & 7) { 1444fcf5ef2aSThomas Huth case 0: 1445fcf5ef2aSThomas Huth gen_helper_fcmp_un(cpu_R[dc->rd], cpu_env, 1446fcf5ef2aSThomas Huth cpu_R[dc->ra], cpu_R[dc->rb]); 1447fcf5ef2aSThomas Huth break; 1448fcf5ef2aSThomas Huth case 1: 1449fcf5ef2aSThomas Huth gen_helper_fcmp_lt(cpu_R[dc->rd], cpu_env, 1450fcf5ef2aSThomas Huth cpu_R[dc->ra], cpu_R[dc->rb]); 1451fcf5ef2aSThomas Huth break; 1452fcf5ef2aSThomas Huth case 2: 1453fcf5ef2aSThomas Huth gen_helper_fcmp_eq(cpu_R[dc->rd], cpu_env, 1454fcf5ef2aSThomas Huth cpu_R[dc->ra], cpu_R[dc->rb]); 1455fcf5ef2aSThomas Huth break; 1456fcf5ef2aSThomas Huth case 3: 1457fcf5ef2aSThomas Huth gen_helper_fcmp_le(cpu_R[dc->rd], cpu_env, 1458fcf5ef2aSThomas Huth cpu_R[dc->ra], cpu_R[dc->rb]); 1459fcf5ef2aSThomas Huth break; 1460fcf5ef2aSThomas Huth case 4: 1461fcf5ef2aSThomas Huth gen_helper_fcmp_gt(cpu_R[dc->rd], cpu_env, 1462fcf5ef2aSThomas Huth cpu_R[dc->ra], cpu_R[dc->rb]); 1463fcf5ef2aSThomas Huth break; 1464fcf5ef2aSThomas Huth case 5: 1465fcf5ef2aSThomas Huth gen_helper_fcmp_ne(cpu_R[dc->rd], cpu_env, 1466fcf5ef2aSThomas Huth cpu_R[dc->ra], cpu_R[dc->rb]); 1467fcf5ef2aSThomas Huth break; 1468fcf5ef2aSThomas Huth case 6: 1469fcf5ef2aSThomas Huth gen_helper_fcmp_ge(cpu_R[dc->rd], cpu_env, 1470fcf5ef2aSThomas Huth cpu_R[dc->ra], cpu_R[dc->rb]); 1471fcf5ef2aSThomas Huth break; 1472fcf5ef2aSThomas Huth default: 1473fcf5ef2aSThomas Huth qemu_log_mask(LOG_UNIMP, 1474fcf5ef2aSThomas Huth "unimplemented fcmp fpu_insn=%x pc=%x" 1475fcf5ef2aSThomas Huth " opc=%x\n", 1476fcf5ef2aSThomas Huth fpu_insn, dc->pc, dc->opcode); 1477fcf5ef2aSThomas Huth dc->abort_at_next_insn = 1; 1478fcf5ef2aSThomas Huth break; 1479fcf5ef2aSThomas Huth } 1480fcf5ef2aSThomas Huth break; 1481fcf5ef2aSThomas Huth 1482fcf5ef2aSThomas Huth case 5: 1483fcf5ef2aSThomas Huth if (!dec_check_fpuv2(dc)) { 1484fcf5ef2aSThomas Huth return; 1485fcf5ef2aSThomas Huth } 1486fcf5ef2aSThomas Huth gen_helper_flt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); 1487fcf5ef2aSThomas Huth break; 1488fcf5ef2aSThomas Huth 1489fcf5ef2aSThomas Huth case 6: 1490fcf5ef2aSThomas Huth if (!dec_check_fpuv2(dc)) { 1491fcf5ef2aSThomas Huth return; 1492fcf5ef2aSThomas Huth } 1493fcf5ef2aSThomas Huth gen_helper_fint(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); 1494fcf5ef2aSThomas Huth break; 1495fcf5ef2aSThomas Huth 1496fcf5ef2aSThomas Huth case 7: 1497fcf5ef2aSThomas Huth if (!dec_check_fpuv2(dc)) { 1498fcf5ef2aSThomas Huth return; 1499fcf5ef2aSThomas Huth } 1500fcf5ef2aSThomas Huth gen_helper_fsqrt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); 1501fcf5ef2aSThomas Huth break; 1502fcf5ef2aSThomas Huth 1503fcf5ef2aSThomas Huth default: 1504fcf5ef2aSThomas Huth qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=%x pc=%x" 1505fcf5ef2aSThomas Huth " opc=%x\n", 1506fcf5ef2aSThomas Huth fpu_insn, dc->pc, dc->opcode); 1507fcf5ef2aSThomas Huth dc->abort_at_next_insn = 1; 1508fcf5ef2aSThomas Huth break; 1509fcf5ef2aSThomas Huth } 1510fcf5ef2aSThomas Huth } 1511fcf5ef2aSThomas Huth 1512fcf5ef2aSThomas Huth static void dec_null(DisasContext *dc) 1513fcf5ef2aSThomas Huth { 15149ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, true)) { 1515fcf5ef2aSThomas Huth return; 1516fcf5ef2aSThomas Huth } 1517fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode); 1518fcf5ef2aSThomas Huth dc->abort_at_next_insn = 1; 1519fcf5ef2aSThomas Huth } 1520fcf5ef2aSThomas Huth 1521fcf5ef2aSThomas Huth /* Insns connected to FSL or AXI stream attached devices. */ 1522fcf5ef2aSThomas Huth static void dec_stream(DisasContext *dc) 1523fcf5ef2aSThomas Huth { 1524fcf5ef2aSThomas Huth TCGv_i32 t_id, t_ctrl; 1525fcf5ef2aSThomas Huth int ctrl; 1526fcf5ef2aSThomas Huth 1527fcf5ef2aSThomas Huth LOG_DIS("%s%s imm=%x\n", dc->rd ? "get" : "put", 1528fcf5ef2aSThomas Huth dc->type_b ? "" : "d", dc->imm); 1529fcf5ef2aSThomas Huth 1530bdfc1e88SEdgar E. Iglesias if (trap_userspace(dc, true)) { 1531fcf5ef2aSThomas Huth return; 1532fcf5ef2aSThomas Huth } 1533fcf5ef2aSThomas Huth 1534cfeea807SEdgar E. Iglesias t_id = tcg_temp_new_i32(); 1535fcf5ef2aSThomas Huth if (dc->type_b) { 1536cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(t_id, dc->imm & 0xf); 1537fcf5ef2aSThomas Huth ctrl = dc->imm >> 10; 1538fcf5ef2aSThomas Huth } else { 1539cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t_id, cpu_R[dc->rb], 0xf); 1540fcf5ef2aSThomas Huth ctrl = dc->imm >> 5; 1541fcf5ef2aSThomas Huth } 1542fcf5ef2aSThomas Huth 1543cfeea807SEdgar E. Iglesias t_ctrl = tcg_const_i32(ctrl); 1544fcf5ef2aSThomas Huth 1545fcf5ef2aSThomas Huth if (dc->rd == 0) { 1546fcf5ef2aSThomas Huth gen_helper_put(t_id, t_ctrl, cpu_R[dc->ra]); 1547fcf5ef2aSThomas Huth } else { 1548fcf5ef2aSThomas Huth gen_helper_get(cpu_R[dc->rd], t_id, t_ctrl); 1549fcf5ef2aSThomas Huth } 1550cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t_id); 1551cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t_ctrl); 1552fcf5ef2aSThomas Huth } 1553fcf5ef2aSThomas Huth 1554fcf5ef2aSThomas Huth static struct decoder_info { 1555fcf5ef2aSThomas Huth struct { 1556fcf5ef2aSThomas Huth uint32_t bits; 1557fcf5ef2aSThomas Huth uint32_t mask; 1558fcf5ef2aSThomas Huth }; 1559fcf5ef2aSThomas Huth void (*dec)(DisasContext *dc); 1560fcf5ef2aSThomas Huth } decinfo[] = { 1561fcf5ef2aSThomas Huth {DEC_ADD, dec_add}, 1562fcf5ef2aSThomas Huth {DEC_SUB, dec_sub}, 1563fcf5ef2aSThomas Huth {DEC_AND, dec_and}, 1564fcf5ef2aSThomas Huth {DEC_XOR, dec_xor}, 1565fcf5ef2aSThomas Huth {DEC_OR, dec_or}, 1566fcf5ef2aSThomas Huth {DEC_BIT, dec_bit}, 1567fcf5ef2aSThomas Huth {DEC_BARREL, dec_barrel}, 1568fcf5ef2aSThomas Huth {DEC_LD, dec_load}, 1569fcf5ef2aSThomas Huth {DEC_ST, dec_store}, 1570fcf5ef2aSThomas Huth {DEC_IMM, dec_imm}, 1571fcf5ef2aSThomas Huth {DEC_BR, dec_br}, 1572fcf5ef2aSThomas Huth {DEC_BCC, dec_bcc}, 1573fcf5ef2aSThomas Huth {DEC_RTS, dec_rts}, 1574fcf5ef2aSThomas Huth {DEC_FPU, dec_fpu}, 1575fcf5ef2aSThomas Huth {DEC_MUL, dec_mul}, 1576fcf5ef2aSThomas Huth {DEC_DIV, dec_div}, 1577fcf5ef2aSThomas Huth {DEC_MSR, dec_msr}, 1578fcf5ef2aSThomas Huth {DEC_STREAM, dec_stream}, 1579fcf5ef2aSThomas Huth {{0, 0}, dec_null} 1580fcf5ef2aSThomas Huth }; 1581fcf5ef2aSThomas Huth 1582fcf5ef2aSThomas Huth static inline void decode(DisasContext *dc, uint32_t ir) 1583fcf5ef2aSThomas Huth { 1584fcf5ef2aSThomas Huth int i; 1585fcf5ef2aSThomas Huth 1586fcf5ef2aSThomas Huth dc->ir = ir; 1587fcf5ef2aSThomas Huth LOG_DIS("%8.8x\t", dc->ir); 1588fcf5ef2aSThomas Huth 1589462c2544SEdgar E. Iglesias if (ir == 0) { 15901ee1bd28SEdgar E. Iglesias trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal); 1591462c2544SEdgar E. Iglesias /* Don't decode nop/zero instructions any further. */ 1592462c2544SEdgar E. Iglesias return; 1593462c2544SEdgar E. Iglesias } 1594fcf5ef2aSThomas Huth 1595fcf5ef2aSThomas Huth /* bit 2 seems to indicate insn type. */ 1596fcf5ef2aSThomas Huth dc->type_b = ir & (1 << 29); 1597fcf5ef2aSThomas Huth 1598fcf5ef2aSThomas Huth dc->opcode = EXTRACT_FIELD(ir, 26, 31); 1599fcf5ef2aSThomas Huth dc->rd = EXTRACT_FIELD(ir, 21, 25); 1600fcf5ef2aSThomas Huth dc->ra = EXTRACT_FIELD(ir, 16, 20); 1601fcf5ef2aSThomas Huth dc->rb = EXTRACT_FIELD(ir, 11, 15); 1602fcf5ef2aSThomas Huth dc->imm = EXTRACT_FIELD(ir, 0, 15); 1603fcf5ef2aSThomas Huth 1604fcf5ef2aSThomas Huth /* Large switch for all insns. */ 1605fcf5ef2aSThomas Huth for (i = 0; i < ARRAY_SIZE(decinfo); i++) { 1606fcf5ef2aSThomas Huth if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) { 1607fcf5ef2aSThomas Huth decinfo[i].dec(dc); 1608fcf5ef2aSThomas Huth break; 1609fcf5ef2aSThomas Huth } 1610fcf5ef2aSThomas Huth } 1611fcf5ef2aSThomas Huth } 1612fcf5ef2aSThomas Huth 1613fcf5ef2aSThomas Huth /* generate intermediate code for basic block 'tb'. */ 16148b86d6d2SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 1615fcf5ef2aSThomas Huth { 16169c489ea6SLluís Vilanova CPUMBState *env = cs->env_ptr; 1617f5c7e93aSRichard Henderson MicroBlazeCPU *cpu = env_archcpu(env); 1618fcf5ef2aSThomas Huth uint32_t pc_start; 1619fcf5ef2aSThomas Huth struct DisasContext ctx; 1620fcf5ef2aSThomas Huth struct DisasContext *dc = &ctx; 162156371527SEmilio G. Cota uint32_t page_start, org_flags; 1622cfeea807SEdgar E. Iglesias uint32_t npc; 1623fcf5ef2aSThomas Huth int num_insns; 1624fcf5ef2aSThomas Huth 1625fcf5ef2aSThomas Huth pc_start = tb->pc; 1626fcf5ef2aSThomas Huth dc->cpu = cpu; 1627fcf5ef2aSThomas Huth dc->tb = tb; 1628fcf5ef2aSThomas Huth org_flags = dc->synced_flags = dc->tb_flags = tb->flags; 1629fcf5ef2aSThomas Huth 1630fcf5ef2aSThomas Huth dc->is_jmp = DISAS_NEXT; 1631fcf5ef2aSThomas Huth dc->jmp = 0; 1632fcf5ef2aSThomas Huth dc->delayed_branch = !!(dc->tb_flags & D_FLAG); 1633fcf5ef2aSThomas Huth if (dc->delayed_branch) { 1634fcf5ef2aSThomas Huth dc->jmp = JMP_INDIRECT; 1635fcf5ef2aSThomas Huth } 1636fcf5ef2aSThomas Huth dc->pc = pc_start; 1637fcf5ef2aSThomas Huth dc->singlestep_enabled = cs->singlestep_enabled; 1638fcf5ef2aSThomas Huth dc->cpustate_changed = 0; 1639fcf5ef2aSThomas Huth dc->abort_at_next_insn = 0; 1640fcf5ef2aSThomas Huth 1641fcf5ef2aSThomas Huth if (pc_start & 3) { 1642fcf5ef2aSThomas Huth cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start); 1643fcf5ef2aSThomas Huth } 1644fcf5ef2aSThomas Huth 164556371527SEmilio G. Cota page_start = pc_start & TARGET_PAGE_MASK; 1646fcf5ef2aSThomas Huth num_insns = 0; 1647fcf5ef2aSThomas Huth 1648fcf5ef2aSThomas Huth gen_tb_start(tb); 1649fcf5ef2aSThomas Huth do 1650fcf5ef2aSThomas Huth { 1651fcf5ef2aSThomas Huth tcg_gen_insn_start(dc->pc); 1652fcf5ef2aSThomas Huth num_insns++; 1653fcf5ef2aSThomas Huth 1654fcf5ef2aSThomas Huth #if SIM_COMPAT 1655fcf5ef2aSThomas Huth if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { 16560f96e96bSRichard Henderson tcg_gen_movi_i32(cpu_pc, dc->pc); 1657fcf5ef2aSThomas Huth gen_helper_debug(); 1658fcf5ef2aSThomas Huth } 1659fcf5ef2aSThomas Huth #endif 1660fcf5ef2aSThomas Huth 1661fcf5ef2aSThomas Huth if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { 1662fcf5ef2aSThomas Huth t_gen_raise_exception(dc, EXCP_DEBUG); 1663fcf5ef2aSThomas Huth dc->is_jmp = DISAS_UPDATE; 1664fcf5ef2aSThomas Huth /* The address covered by the breakpoint must be included in 1665fcf5ef2aSThomas Huth [tb->pc, tb->pc + tb->size) in order to for it to be 1666fcf5ef2aSThomas Huth properly cleared -- thus we increment the PC here so that 1667fcf5ef2aSThomas Huth the logic setting tb->size below does the right thing. */ 1668fcf5ef2aSThomas Huth dc->pc += 4; 1669fcf5ef2aSThomas Huth break; 1670fcf5ef2aSThomas Huth } 1671fcf5ef2aSThomas Huth 1672fcf5ef2aSThomas Huth /* Pretty disas. */ 1673fcf5ef2aSThomas Huth LOG_DIS("%8.8x:\t", dc->pc); 1674fcf5ef2aSThomas Huth 1675c5a49c63SEmilio G. Cota if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) { 1676fcf5ef2aSThomas Huth gen_io_start(); 1677fcf5ef2aSThomas Huth } 1678fcf5ef2aSThomas Huth 1679fcf5ef2aSThomas Huth dc->clear_imm = 1; 1680fcf5ef2aSThomas Huth decode(dc, cpu_ldl_code(env, dc->pc)); 1681fcf5ef2aSThomas Huth if (dc->clear_imm) 1682fcf5ef2aSThomas Huth dc->tb_flags &= ~IMM_FLAG; 1683fcf5ef2aSThomas Huth dc->pc += 4; 1684fcf5ef2aSThomas Huth 1685fcf5ef2aSThomas Huth if (dc->delayed_branch) { 1686fcf5ef2aSThomas Huth dc->delayed_branch--; 1687fcf5ef2aSThomas Huth if (!dc->delayed_branch) { 1688fcf5ef2aSThomas Huth if (dc->tb_flags & DRTI_FLAG) 1689fcf5ef2aSThomas Huth do_rti(dc); 1690fcf5ef2aSThomas Huth if (dc->tb_flags & DRTB_FLAG) 1691fcf5ef2aSThomas Huth do_rtb(dc); 1692fcf5ef2aSThomas Huth if (dc->tb_flags & DRTE_FLAG) 1693fcf5ef2aSThomas Huth do_rte(dc); 1694fcf5ef2aSThomas Huth /* Clear the delay slot flag. */ 1695fcf5ef2aSThomas Huth dc->tb_flags &= ~D_FLAG; 1696fcf5ef2aSThomas Huth /* If it is a direct jump, try direct chaining. */ 1697fcf5ef2aSThomas Huth if (dc->jmp == JMP_INDIRECT) { 16980f96e96bSRichard Henderson TCGv_i32 tmp_pc = tcg_const_i32(dc->pc); 16990f96e96bSRichard Henderson eval_cond_jmp(dc, cpu_btarget, tmp_pc); 17000f96e96bSRichard Henderson tcg_temp_free_i32(tmp_pc); 1701fcf5ef2aSThomas Huth dc->is_jmp = DISAS_JUMP; 1702fcf5ef2aSThomas Huth } else if (dc->jmp == JMP_DIRECT) { 1703fcf5ef2aSThomas Huth t_sync_flags(dc); 1704fcf5ef2aSThomas Huth gen_goto_tb(dc, 0, dc->jmp_pc); 1705fcf5ef2aSThomas Huth dc->is_jmp = DISAS_TB_JUMP; 1706fcf5ef2aSThomas Huth } else if (dc->jmp == JMP_DIRECT_CC) { 1707fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 1708fcf5ef2aSThomas Huth t_sync_flags(dc); 1709fcf5ef2aSThomas Huth /* Conditional jmp. */ 1710cfeea807SEdgar E. Iglesias tcg_gen_brcondi_i32(TCG_COND_NE, env_btaken, 0, l1); 1711fcf5ef2aSThomas Huth gen_goto_tb(dc, 1, dc->pc); 1712fcf5ef2aSThomas Huth gen_set_label(l1); 1713fcf5ef2aSThomas Huth gen_goto_tb(dc, 0, dc->jmp_pc); 1714fcf5ef2aSThomas Huth 1715fcf5ef2aSThomas Huth dc->is_jmp = DISAS_TB_JUMP; 1716fcf5ef2aSThomas Huth } 1717fcf5ef2aSThomas Huth break; 1718fcf5ef2aSThomas Huth } 1719fcf5ef2aSThomas Huth } 1720fcf5ef2aSThomas Huth if (cs->singlestep_enabled) { 1721fcf5ef2aSThomas Huth break; 1722fcf5ef2aSThomas Huth } 1723fcf5ef2aSThomas Huth } while (!dc->is_jmp && !dc->cpustate_changed 1724fcf5ef2aSThomas Huth && !tcg_op_buf_full() 1725fcf5ef2aSThomas Huth && !singlestep 172656371527SEmilio G. Cota && (dc->pc - page_start < TARGET_PAGE_SIZE) 1727fcf5ef2aSThomas Huth && num_insns < max_insns); 1728fcf5ef2aSThomas Huth 1729fcf5ef2aSThomas Huth npc = dc->pc; 1730fcf5ef2aSThomas Huth if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { 1731fcf5ef2aSThomas Huth if (dc->tb_flags & D_FLAG) { 1732fcf5ef2aSThomas Huth dc->is_jmp = DISAS_UPDATE; 17330f96e96bSRichard Henderson tcg_gen_movi_i32(cpu_pc, npc); 1734fcf5ef2aSThomas Huth sync_jmpstate(dc); 1735fcf5ef2aSThomas Huth } else 1736fcf5ef2aSThomas Huth npc = dc->jmp_pc; 1737fcf5ef2aSThomas Huth } 1738fcf5ef2aSThomas Huth 1739fcf5ef2aSThomas Huth /* Force an update if the per-tb cpu state has changed. */ 1740fcf5ef2aSThomas Huth if (dc->is_jmp == DISAS_NEXT 1741fcf5ef2aSThomas Huth && (dc->cpustate_changed || org_flags != dc->tb_flags)) { 1742fcf5ef2aSThomas Huth dc->is_jmp = DISAS_UPDATE; 17430f96e96bSRichard Henderson tcg_gen_movi_i32(cpu_pc, npc); 1744fcf5ef2aSThomas Huth } 1745fcf5ef2aSThomas Huth t_sync_flags(dc); 1746fcf5ef2aSThomas Huth 1747fcf5ef2aSThomas Huth if (unlikely(cs->singlestep_enabled)) { 1748fcf5ef2aSThomas Huth TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); 1749fcf5ef2aSThomas Huth 1750fcf5ef2aSThomas Huth if (dc->is_jmp != DISAS_JUMP) { 17510f96e96bSRichard Henderson tcg_gen_movi_i32(cpu_pc, npc); 1752fcf5ef2aSThomas Huth } 1753fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, tmp); 1754fcf5ef2aSThomas Huth tcg_temp_free_i32(tmp); 1755fcf5ef2aSThomas Huth } else { 1756fcf5ef2aSThomas Huth switch(dc->is_jmp) { 1757fcf5ef2aSThomas Huth case DISAS_NEXT: 1758fcf5ef2aSThomas Huth gen_goto_tb(dc, 1, npc); 1759fcf5ef2aSThomas Huth break; 1760fcf5ef2aSThomas Huth default: 1761fcf5ef2aSThomas Huth case DISAS_JUMP: 1762fcf5ef2aSThomas Huth case DISAS_UPDATE: 1763fcf5ef2aSThomas Huth /* indicate that the hash table must be used 1764fcf5ef2aSThomas Huth to find the next TB */ 176507ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 1766fcf5ef2aSThomas Huth break; 1767fcf5ef2aSThomas Huth case DISAS_TB_JUMP: 1768fcf5ef2aSThomas Huth /* nothing more to generate */ 1769fcf5ef2aSThomas Huth break; 1770fcf5ef2aSThomas Huth } 1771fcf5ef2aSThomas Huth } 1772fcf5ef2aSThomas Huth gen_tb_end(tb, num_insns); 1773fcf5ef2aSThomas Huth 1774fcf5ef2aSThomas Huth tb->size = dc->pc - pc_start; 1775fcf5ef2aSThomas Huth tb->icount = num_insns; 1776fcf5ef2aSThomas Huth 1777fcf5ef2aSThomas Huth #ifdef DEBUG_DISAS 1778fcf5ef2aSThomas Huth #if !SIM_COMPAT 1779fcf5ef2aSThomas Huth if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) 1780fcf5ef2aSThomas Huth && qemu_log_in_addr_range(pc_start)) { 1781fc59d2d8SRobert Foley FILE *logfile = qemu_log_lock(); 1782fcf5ef2aSThomas Huth qemu_log("--------------\n"); 17831d48474dSRichard Henderson log_target_disas(cs, pc_start, dc->pc - pc_start); 1784fc59d2d8SRobert Foley qemu_log_unlock(logfile); 1785fcf5ef2aSThomas Huth } 1786fcf5ef2aSThomas Huth #endif 1787fcf5ef2aSThomas Huth #endif 1788fcf5ef2aSThomas Huth assert(!dc->abort_at_next_insn); 1789fcf5ef2aSThomas Huth } 1790fcf5ef2aSThomas Huth 179190c84c56SMarkus Armbruster void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1792fcf5ef2aSThomas Huth { 1793fcf5ef2aSThomas Huth MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 1794fcf5ef2aSThomas Huth CPUMBState *env = &cpu->env; 1795fcf5ef2aSThomas Huth int i; 1796fcf5ef2aSThomas Huth 179790c84c56SMarkus Armbruster if (!env) { 1798fcf5ef2aSThomas Huth return; 179990c84c56SMarkus Armbruster } 1800fcf5ef2aSThomas Huth 18010f96e96bSRichard Henderson qemu_fprintf(f, "IN: PC=%x %s\n", 180276e8187dSRichard Henderson env->pc, lookup_symbol(env->pc)); 18036efd5599SRichard Henderson qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " " 1804ccf628b7SRichard Henderson "debug=%x imm=%x iflags=%x fsr=%x rbtr=%x\n", 180578e9caf2SRichard Henderson env->msr, env->esr, env->ear, 18065a8e0136SRichard Henderson env->debug, env->imm, env->iflags, env->fsr, 18076fbf78f2SRichard Henderson env->btr); 18080f96e96bSRichard Henderson qemu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", 1809fcf5ef2aSThomas Huth env->btaken, env->btarget, 18102e5282caSRichard Henderson (env->msr & MSR_UM) ? "user" : "kernel", 18112e5282caSRichard Henderson (env->msr & MSR_UMS) ? "user" : "kernel", 18122e5282caSRichard Henderson (bool)(env->msr & MSR_EIP), 18132e5282caSRichard Henderson (bool)(env->msr & MSR_IE)); 18142ead1b18SJoe Komlodi for (i = 0; i < 12; i++) { 18152ead1b18SJoe Komlodi qemu_fprintf(f, "rpvr%2.2d=%8.8x ", i, env->pvr.regs[i]); 18162ead1b18SJoe Komlodi if ((i + 1) % 4 == 0) { 18172ead1b18SJoe Komlodi qemu_fprintf(f, "\n"); 18182ead1b18SJoe Komlodi } 18192ead1b18SJoe Komlodi } 1820fcf5ef2aSThomas Huth 18212ead1b18SJoe Komlodi /* Registers that aren't modeled are reported as 0 */ 1822*39db007eSRichard Henderson qemu_fprintf(f, "redr=%x rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 " 1823af20a93aSRichard Henderson "rtlblo=0 rtlbhi=0\n", env->edr); 18242ead1b18SJoe Komlodi qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr); 1825fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 182690c84c56SMarkus Armbruster qemu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]); 1827fcf5ef2aSThomas Huth if ((i + 1) % 4 == 0) 182890c84c56SMarkus Armbruster qemu_fprintf(f, "\n"); 1829fcf5ef2aSThomas Huth } 183090c84c56SMarkus Armbruster qemu_fprintf(f, "\n\n"); 1831fcf5ef2aSThomas Huth } 1832fcf5ef2aSThomas Huth 1833fcf5ef2aSThomas Huth void mb_tcg_init(void) 1834fcf5ef2aSThomas Huth { 1835fcf5ef2aSThomas Huth int i; 1836fcf5ef2aSThomas Huth 1837cfeea807SEdgar E. Iglesias env_debug = tcg_global_mem_new_i32(cpu_env, 1838fcf5ef2aSThomas Huth offsetof(CPUMBState, debug), 1839fcf5ef2aSThomas Huth "debug0"); 1840cfeea807SEdgar E. Iglesias env_iflags = tcg_global_mem_new_i32(cpu_env, 1841fcf5ef2aSThomas Huth offsetof(CPUMBState, iflags), 1842fcf5ef2aSThomas Huth "iflags"); 1843cfeea807SEdgar E. Iglesias env_imm = tcg_global_mem_new_i32(cpu_env, 1844fcf5ef2aSThomas Huth offsetof(CPUMBState, imm), 1845fcf5ef2aSThomas Huth "imm"); 18460f96e96bSRichard Henderson cpu_btarget = tcg_global_mem_new_i32(cpu_env, 1847fcf5ef2aSThomas Huth offsetof(CPUMBState, btarget), 1848fcf5ef2aSThomas Huth "btarget"); 1849cfeea807SEdgar E. Iglesias env_btaken = tcg_global_mem_new_i32(cpu_env, 1850fcf5ef2aSThomas Huth offsetof(CPUMBState, btaken), 1851fcf5ef2aSThomas Huth "btaken"); 1852403322eaSEdgar E. Iglesias env_res_addr = tcg_global_mem_new(cpu_env, 1853fcf5ef2aSThomas Huth offsetof(CPUMBState, res_addr), 1854fcf5ef2aSThomas Huth "res_addr"); 1855cfeea807SEdgar E. Iglesias env_res_val = tcg_global_mem_new_i32(cpu_env, 1856fcf5ef2aSThomas Huth offsetof(CPUMBState, res_val), 1857fcf5ef2aSThomas Huth "res_val"); 1858fcf5ef2aSThomas Huth for (i = 0; i < ARRAY_SIZE(cpu_R); i++) { 1859cfeea807SEdgar E. Iglesias cpu_R[i] = tcg_global_mem_new_i32(cpu_env, 1860fcf5ef2aSThomas Huth offsetof(CPUMBState, regs[i]), 1861fcf5ef2aSThomas Huth regnames[i]); 1862fcf5ef2aSThomas Huth } 186376e8187dSRichard Henderson 1864aa28e6d4SRichard Henderson cpu_pc = 18650f96e96bSRichard Henderson tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, pc), "rpc"); 1866aa28e6d4SRichard Henderson cpu_msr = 18673e0e16aeSRichard Henderson tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, msr), "rmsr"); 1868aa28e6d4SRichard Henderson cpu_ear = 1869b2e80a3cSRichard Henderson tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear"); 1870aa28e6d4SRichard Henderson cpu_esr = 18716efd5599SRichard Henderson tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr"); 1872fcf5ef2aSThomas Huth } 1873fcf5ef2aSThomas Huth 1874fcf5ef2aSThomas Huth void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, 1875fcf5ef2aSThomas Huth target_ulong *data) 1876fcf5ef2aSThomas Huth { 187776e8187dSRichard Henderson env->pc = data[0]; 1878fcf5ef2aSThomas Huth } 1879