1 /* 2 * MicroBlaze virtual CPU header 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef MICROBLAZE_CPU_H 21 #define MICROBLAZE_CPU_H 22 23 #include "cpu-qom.h" 24 #include "exec/cpu-defs.h" 25 #include "fpu/softfloat-types.h" 26 27 typedef struct CPUMBState CPUMBState; 28 #if !defined(CONFIG_USER_ONLY) 29 #include "mmu.h" 30 #endif 31 32 #define EXCP_MMU 1 33 #define EXCP_IRQ 2 34 #define EXCP_BREAK 3 35 #define EXCP_HW_BREAK 4 36 #define EXCP_HW_EXCP 5 37 38 /* MicroBlaze-specific interrupt pending bits. */ 39 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 40 41 /* Meanings of the MBCPU object's two inbound GPIO lines */ 42 #define MB_CPU_IRQ 0 43 #define MB_CPU_FIR 1 44 45 /* Register aliases. R0 - R15 */ 46 #define R_SP 1 47 #define SR_PC 0 48 #define SR_MSR 1 49 #define SR_EAR 3 50 #define SR_ESR 5 51 #define SR_FSR 7 52 #define SR_BTR 0xb 53 #define SR_EDR 0xd 54 55 /* MSR flags. */ 56 #define MSR_BE (1<<0) /* 0x001 */ 57 #define MSR_IE (1<<1) /* 0x002 */ 58 #define MSR_C (1<<2) /* 0x004 */ 59 #define MSR_BIP (1<<3) /* 0x008 */ 60 #define MSR_FSL (1<<4) /* 0x010 */ 61 #define MSR_ICE (1<<5) /* 0x020 */ 62 #define MSR_DZ (1<<6) /* 0x040 */ 63 #define MSR_DCE (1<<7) /* 0x080 */ 64 #define MSR_EE (1<<8) /* 0x100 */ 65 #define MSR_EIP (1<<9) /* 0x200 */ 66 #define MSR_PVR (1<<10) /* 0x400 */ 67 #define MSR_CC (1<<31) 68 69 /* Machine State Register (MSR) Fields */ 70 #define MSR_UM (1<<11) /* User Mode */ 71 #define MSR_UMS (1<<12) /* User Mode Save */ 72 #define MSR_VM (1<<13) /* Virtual Mode */ 73 #define MSR_VMS (1<<14) /* Virtual Mode Save */ 74 75 #define MSR_KERNEL MSR_EE|MSR_VM 76 //#define MSR_USER MSR_KERNEL|MSR_UM|MSR_IE 77 #define MSR_KERNEL_VMS MSR_EE|MSR_VMS 78 //#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE 79 80 /* Exception State Register (ESR) Fields */ 81 #define ESR_DIZ (1<<11) /* Zone Protection */ 82 #define ESR_S (1<<10) /* Store instruction */ 83 84 #define ESR_ESS_FSL_OFFSET 5 85 86 #define ESR_EC_FSL 0 87 #define ESR_EC_UNALIGNED_DATA 1 88 #define ESR_EC_ILLEGAL_OP 2 89 #define ESR_EC_INSN_BUS 3 90 #define ESR_EC_DATA_BUS 4 91 #define ESR_EC_DIVZERO 5 92 #define ESR_EC_FPU 6 93 #define ESR_EC_PRIVINSN 7 94 #define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */ 95 #define ESR_EC_DATA_STORAGE 8 96 #define ESR_EC_INSN_STORAGE 9 97 #define ESR_EC_DATA_TLB 10 98 #define ESR_EC_INSN_TLB 11 99 #define ESR_EC_MASK 31 100 101 /* Floating Point Status Register (FSR) Bits */ 102 #define FSR_IO (1<<4) /* Invalid operation */ 103 #define FSR_DZ (1<<3) /* Divide-by-zero */ 104 #define FSR_OF (1<<2) /* Overflow */ 105 #define FSR_UF (1<<1) /* Underflow */ 106 #define FSR_DO (1<<0) /* Denormalized operand error */ 107 108 /* Version reg. */ 109 /* Basic PVR mask */ 110 #define PVR0_PVR_FULL_MASK 0x80000000 111 #define PVR0_USE_BARREL_MASK 0x40000000 112 #define PVR0_USE_DIV_MASK 0x20000000 113 #define PVR0_USE_HW_MUL_MASK 0x10000000 114 #define PVR0_USE_FPU_MASK 0x08000000 115 #define PVR0_USE_EXC_MASK 0x04000000 116 #define PVR0_USE_ICACHE_MASK 0x02000000 117 #define PVR0_USE_DCACHE_MASK 0x01000000 118 #define PVR0_USE_MMU_MASK 0x00800000 119 #define PVR0_USE_BTC 0x00400000 120 #define PVR0_ENDI_MASK 0x00200000 121 #define PVR0_FAULT 0x00100000 122 #define PVR0_VERSION_MASK 0x0000FF00 123 #define PVR0_USER1_MASK 0x000000FF 124 #define PVR0_SPROT_MASK 0x00000001 125 126 #define PVR0_VERSION_SHIFT 8 127 128 /* User 2 PVR mask */ 129 #define PVR1_USER2_MASK 0xFFFFFFFF 130 131 /* Configuration PVR masks */ 132 #define PVR2_D_OPB_MASK 0x80000000 133 #define PVR2_D_LMB_MASK 0x40000000 134 #define PVR2_I_OPB_MASK 0x20000000 135 #define PVR2_I_LMB_MASK 0x10000000 136 #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000 137 #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000 138 #define PVR2_D_PLB_MASK 0x02000000 /* new */ 139 #define PVR2_I_PLB_MASK 0x01000000 /* new */ 140 #define PVR2_INTERCONNECT 0x00800000 /* new */ 141 #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */ 142 #define PVR2_USE_FSL_EXC 0x00040000 /* new */ 143 #define PVR2_USE_MSR_INSTR 0x00020000 144 #define PVR2_USE_PCMP_INSTR 0x00010000 145 #define PVR2_AREA_OPTIMISED 0x00008000 146 #define PVR2_USE_BARREL_MASK 0x00004000 147 #define PVR2_USE_DIV_MASK 0x00002000 148 #define PVR2_USE_HW_MUL_MASK 0x00001000 149 #define PVR2_USE_FPU_MASK 0x00000800 150 #define PVR2_USE_MUL64_MASK 0x00000400 151 #define PVR2_USE_FPU2_MASK 0x00000200 /* new */ 152 #define PVR2_USE_IPLBEXC 0x00000100 153 #define PVR2_USE_DPLBEXC 0x00000080 154 #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040 155 #define PVR2_UNALIGNED_EXC_MASK 0x00000020 156 #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010 157 #define PVR2_IOPB_BUS_EXC_MASK 0x00000008 158 #define PVR2_DOPB_BUS_EXC_MASK 0x00000004 159 #define PVR2_DIV_ZERO_EXC_MASK 0x00000002 160 #define PVR2_FPU_EXC_MASK 0x00000001 161 162 /* Debug and exception PVR masks */ 163 #define PVR3_DEBUG_ENABLED_MASK 0x80000000 164 #define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000 165 #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000 166 #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000 167 #define PVR3_FSL_LINKS_MASK 0x00000380 168 169 /* ICache config PVR masks */ 170 #define PVR4_USE_ICACHE_MASK 0x80000000 171 #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000 172 #define PVR4_ICACHE_USE_FSL_MASK 0x02000000 173 #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000 174 #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 175 #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 176 177 /* DCache config PVR masks */ 178 #define PVR5_USE_DCACHE_MASK 0x80000000 179 #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000 180 #define PVR5_DCACHE_USE_FSL_MASK 0x02000000 181 #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 182 #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 183 #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 184 #define PVR5_DCACHE_WRITEBACK_MASK 0x00004000 185 186 /* ICache base address PVR mask */ 187 #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF 188 189 /* ICache high address PVR mask */ 190 #define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF 191 192 /* DCache base address PVR mask */ 193 #define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF 194 195 /* DCache high address PVR mask */ 196 #define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF 197 198 /* Target family PVR mask */ 199 #define PVR10_TARGET_FAMILY_MASK 0xFF000000 200 #define PVR10_ASIZE_SHIFT 18 201 202 /* MMU descrtiption */ 203 #define PVR11_USE_MMU 0xC0000000 204 #define PVR11_MMU_ITLB_SIZE 0x38000000 205 #define PVR11_MMU_DTLB_SIZE 0x07000000 206 #define PVR11_MMU_TLB_ACCESS 0x00C00000 207 #define PVR11_MMU_ZONES 0x003E0000 208 /* MSR Reset value PVR mask */ 209 #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF 210 211 #define C_PVR_NONE 0 212 #define C_PVR_BASIC 1 213 #define C_PVR_FULL 2 214 215 /* CPU flags. */ 216 217 /* Condition codes. */ 218 #define CC_GE 5 219 #define CC_GT 4 220 #define CC_LE 3 221 #define CC_LT 2 222 #define CC_NE 1 223 #define CC_EQ 0 224 225 #define STREAM_EXCEPTION (1 << 0) 226 #define STREAM_ATOMIC (1 << 1) 227 #define STREAM_TEST (1 << 2) 228 #define STREAM_CONTROL (1 << 3) 229 #define STREAM_NONBLOCK (1 << 4) 230 231 struct CPUMBState { 232 uint32_t debug; 233 uint32_t btaken; 234 uint64_t btarget; 235 uint32_t bimm; 236 237 uint32_t imm; 238 uint32_t regs[32]; 239 uint64_t pc; 240 uint64_t msr; 241 uint64_t ear; 242 uint64_t esr; 243 uint64_t sregs[14]; 244 float_status fp_status; 245 /* Stack protectors. Yes, it's a hw feature. */ 246 uint32_t slr, shr; 247 248 /* lwx/swx reserved address */ 249 #define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */ 250 target_ulong res_addr; 251 uint32_t res_val; 252 253 /* Internal flags. */ 254 #define IMM_FLAG 4 255 #define MSR_EE_FLAG (1 << 8) 256 #define DRTI_FLAG (1 << 16) 257 #define DRTE_FLAG (1 << 17) 258 #define DRTB_FLAG (1 << 18) 259 #define D_FLAG (1 << 19) /* Bit in ESR. */ 260 /* TB dependent CPUMBState. */ 261 #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG) 262 uint32_t iflags; 263 264 #if !defined(CONFIG_USER_ONLY) 265 /* Unified MMU. */ 266 struct microblaze_mmu mmu; 267 #endif 268 269 /* Fields up to this point are cleared by a CPU reset */ 270 struct {} end_reset_fields; 271 272 /* These fields are preserved on reset. */ 273 274 struct { 275 uint32_t regs[13]; 276 } pvr; 277 }; 278 279 /** 280 * MicroBlazeCPU: 281 * @env: #CPUMBState 282 * 283 * A MicroBlaze CPU. 284 */ 285 struct MicroBlazeCPU { 286 /*< private >*/ 287 CPUState parent_obj; 288 289 /*< public >*/ 290 291 CPUNegativeOffsetState neg; 292 CPUMBState env; 293 294 /* Microblaze Configuration Settings */ 295 struct { 296 bool stackprot; 297 uint32_t base_vectors; 298 uint8_t addr_size; 299 uint8_t use_fpu; 300 uint8_t use_hw_mul; 301 bool use_barrel; 302 bool use_div; 303 bool use_msr_instr; 304 bool use_pcmp_instr; 305 bool use_mmu; 306 bool dcache_writeback; 307 bool endi; 308 bool dopb_bus_exception; 309 bool iopb_bus_exception; 310 bool illegal_opcode_exception; 311 bool opcode_0_illegal; 312 bool div_zero_exception; 313 bool unaligned_exceptions; 314 uint8_t pvr_user1; 315 uint32_t pvr_user2; 316 char *version; 317 uint8_t pvr; 318 } cfg; 319 }; 320 321 322 void mb_cpu_do_interrupt(CPUState *cs); 323 bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); 324 void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 325 hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 326 int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 327 int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 328 329 void mb_tcg_init(void); 330 /* you can call this signal handler from your SIGBUS and SIGSEGV 331 signal handlers to inform the virtual CPU of exceptions. non zero 332 is returned if the signal was handled by the virtual CPU. */ 333 int cpu_mb_signal_handler(int host_signum, void *pinfo, 334 void *puc); 335 336 #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU 337 338 #define cpu_signal_handler cpu_mb_signal_handler 339 340 /* MMU modes definitions */ 341 #define MMU_NOMMU_IDX 0 342 #define MMU_KERNEL_IDX 1 343 #define MMU_USER_IDX 2 344 /* See NB_MMU_MODES further up the file. */ 345 346 bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 347 MMUAccessType access_type, int mmu_idx, 348 bool probe, uintptr_t retaddr); 349 350 typedef CPUMBState CPUArchState; 351 typedef MicroBlazeCPU ArchCPU; 352 353 #include "exec/cpu-all.h" 354 355 static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, 356 target_ulong *cs_base, uint32_t *flags) 357 { 358 *pc = env->pc; 359 *cs_base = 0; 360 *flags = (env->iflags & IFLAGS_TB_MASK) | 361 (env->msr & (MSR_UM | MSR_VM | MSR_EE)); 362 } 363 364 #if !defined(CONFIG_USER_ONLY) 365 void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, 366 unsigned size, MMUAccessType access_type, 367 int mmu_idx, MemTxAttrs attrs, 368 MemTxResult response, uintptr_t retaddr); 369 #endif 370 371 static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) 372 { 373 MicroBlazeCPU *cpu = env_archcpu(env); 374 375 /* Are we in nommu mode?. */ 376 if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { 377 return MMU_NOMMU_IDX; 378 } 379 380 if (env->msr & MSR_UM) { 381 return MMU_USER_IDX; 382 } 383 return MMU_KERNEL_IDX; 384 } 385 386 #endif 387