1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "sysemu/hvf.h" 28 #include "hvf/hvf-i386.h" 29 #include "kvm/kvm_i386.h" 30 #include "sev.h" 31 #include "qapi/error.h" 32 #include "qemu/error-report.h" 33 #include "qapi/qapi-visit-machine.h" 34 #include "standard-headers/asm-x86/kvm_para.h" 35 #include "hw/qdev-properties.h" 36 #include "hw/i386/topology.h" 37 #ifndef CONFIG_USER_ONLY 38 #include "sysemu/reset.h" 39 #include "qapi/qapi-commands-machine-target.h" 40 #include "exec/address-spaces.h" 41 #include "hw/boards.h" 42 #include "hw/i386/sgx-epc.h" 43 #endif 44 45 #include "disas/capstone.h" 46 #include "cpu-internal.h" 47 48 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 49 50 /* Helpers for building CPUID[2] descriptors: */ 51 52 struct CPUID2CacheDescriptorInfo { 53 enum CacheType type; 54 int level; 55 int size; 56 int line_size; 57 int associativity; 58 }; 59 60 /* 61 * Known CPUID 2 cache descriptors. 62 * From Intel SDM Volume 2A, CPUID instruction 63 */ 64 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 65 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 66 .associativity = 4, .line_size = 32, }, 67 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 68 .associativity = 4, .line_size = 32, }, 69 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 70 .associativity = 4, .line_size = 64, }, 71 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 72 .associativity = 2, .line_size = 32, }, 73 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 74 .associativity = 4, .line_size = 32, }, 75 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 76 .associativity = 4, .line_size = 64, }, 77 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 78 .associativity = 6, .line_size = 64, }, 79 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 80 .associativity = 2, .line_size = 64, }, 81 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 82 .associativity = 8, .line_size = 64, }, 83 /* lines per sector is not supported cpuid2_cache_descriptor(), 84 * so descriptors 0x22, 0x23 are not included 85 */ 86 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 87 .associativity = 16, .line_size = 64, }, 88 /* lines per sector is not supported cpuid2_cache_descriptor(), 89 * so descriptors 0x25, 0x20 are not included 90 */ 91 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 92 .associativity = 8, .line_size = 64, }, 93 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 94 .associativity = 8, .line_size = 64, }, 95 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 96 .associativity = 4, .line_size = 32, }, 97 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 98 .associativity = 4, .line_size = 32, }, 99 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 100 .associativity = 4, .line_size = 32, }, 101 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 102 .associativity = 4, .line_size = 32, }, 103 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 104 .associativity = 4, .line_size = 32, }, 105 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 106 .associativity = 4, .line_size = 64, }, 107 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 108 .associativity = 8, .line_size = 64, }, 109 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 110 .associativity = 12, .line_size = 64, }, 111 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 112 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 113 .associativity = 12, .line_size = 64, }, 114 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 115 .associativity = 16, .line_size = 64, }, 116 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 117 .associativity = 12, .line_size = 64, }, 118 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 119 .associativity = 16, .line_size = 64, }, 120 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 121 .associativity = 24, .line_size = 64, }, 122 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 123 .associativity = 8, .line_size = 64, }, 124 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 125 .associativity = 4, .line_size = 64, }, 126 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 127 .associativity = 4, .line_size = 64, }, 128 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 129 .associativity = 4, .line_size = 64, }, 130 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 131 .associativity = 4, .line_size = 64, }, 132 /* lines per sector is not supported cpuid2_cache_descriptor(), 133 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 134 */ 135 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 136 .associativity = 8, .line_size = 64, }, 137 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 138 .associativity = 2, .line_size = 64, }, 139 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 140 .associativity = 8, .line_size = 64, }, 141 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 142 .associativity = 8, .line_size = 32, }, 143 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 144 .associativity = 8, .line_size = 32, }, 145 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 146 .associativity = 8, .line_size = 32, }, 147 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 148 .associativity = 8, .line_size = 32, }, 149 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 150 .associativity = 4, .line_size = 64, }, 151 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 152 .associativity = 8, .line_size = 64, }, 153 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 154 .associativity = 4, .line_size = 64, }, 155 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 156 .associativity = 4, .line_size = 64, }, 157 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 158 .associativity = 4, .line_size = 64, }, 159 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 160 .associativity = 8, .line_size = 64, }, 161 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 162 .associativity = 8, .line_size = 64, }, 163 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 164 .associativity = 8, .line_size = 64, }, 165 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 166 .associativity = 12, .line_size = 64, }, 167 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 168 .associativity = 12, .line_size = 64, }, 169 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 170 .associativity = 12, .line_size = 64, }, 171 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 172 .associativity = 16, .line_size = 64, }, 173 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 174 .associativity = 16, .line_size = 64, }, 175 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 176 .associativity = 16, .line_size = 64, }, 177 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 178 .associativity = 24, .line_size = 64, }, 179 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 180 .associativity = 24, .line_size = 64, }, 181 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 182 .associativity = 24, .line_size = 64, }, 183 }; 184 185 /* 186 * "CPUID leaf 2 does not report cache descriptor information, 187 * use CPUID leaf 4 to query cache parameters" 188 */ 189 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 190 191 /* 192 * Return a CPUID 2 cache descriptor for a given cache. 193 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 194 */ 195 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 196 { 197 int i; 198 199 assert(cache->size > 0); 200 assert(cache->level > 0); 201 assert(cache->line_size > 0); 202 assert(cache->associativity > 0); 203 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 204 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 205 if (d->level == cache->level && d->type == cache->type && 206 d->size == cache->size && d->line_size == cache->line_size && 207 d->associativity == cache->associativity) { 208 return i; 209 } 210 } 211 212 return CACHE_DESCRIPTOR_UNAVAILABLE; 213 } 214 215 /* CPUID Leaf 4 constants: */ 216 217 /* EAX: */ 218 #define CACHE_TYPE_D 1 219 #define CACHE_TYPE_I 2 220 #define CACHE_TYPE_UNIFIED 3 221 222 #define CACHE_LEVEL(l) (l << 5) 223 224 #define CACHE_SELF_INIT_LEVEL (1 << 8) 225 226 /* EDX: */ 227 #define CACHE_NO_INVD_SHARING (1 << 0) 228 #define CACHE_INCLUSIVE (1 << 1) 229 #define CACHE_COMPLEX_IDX (1 << 2) 230 231 /* Encode CacheType for CPUID[4].EAX */ 232 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 233 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 234 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 235 0 /* Invalid value */) 236 237 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 238 enum CPUTopoLevel share_level) 239 { 240 uint32_t num_ids = 0; 241 242 switch (share_level) { 243 case CPU_TOPO_LEVEL_CORE: 244 num_ids = 1 << apicid_core_offset(topo_info); 245 break; 246 case CPU_TOPO_LEVEL_DIE: 247 num_ids = 1 << apicid_die_offset(topo_info); 248 break; 249 case CPU_TOPO_LEVEL_PACKAGE: 250 num_ids = 1 << apicid_pkg_offset(topo_info); 251 break; 252 default: 253 /* 254 * Currently there is no use case for SMT and MODULE, so use 255 * assert directly to facilitate debugging. 256 */ 257 g_assert_not_reached(); 258 } 259 260 return num_ids - 1; 261 } 262 263 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 264 { 265 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 266 apicid_core_offset(topo_info)); 267 return num_cores - 1; 268 } 269 270 /* Encode cache info for CPUID[4] */ 271 static void encode_cache_cpuid4(CPUCacheInfo *cache, 272 X86CPUTopoInfo *topo_info, 273 uint32_t *eax, uint32_t *ebx, 274 uint32_t *ecx, uint32_t *edx) 275 { 276 assert(cache->size == cache->line_size * cache->associativity * 277 cache->partitions * cache->sets); 278 279 *eax = CACHE_TYPE(cache->type) | 280 CACHE_LEVEL(cache->level) | 281 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 282 (max_core_ids_in_package(topo_info) << 26) | 283 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); 284 285 assert(cache->line_size > 0); 286 assert(cache->partitions > 0); 287 assert(cache->associativity > 0); 288 /* We don't implement fully-associative caches */ 289 assert(cache->associativity < cache->sets); 290 *ebx = (cache->line_size - 1) | 291 ((cache->partitions - 1) << 12) | 292 ((cache->associativity - 1) << 22); 293 294 assert(cache->sets > 0); 295 *ecx = cache->sets - 1; 296 297 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 298 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 299 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 300 } 301 302 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 303 enum CPUTopoLevel topo_level) 304 { 305 switch (topo_level) { 306 case CPU_TOPO_LEVEL_SMT: 307 return 1; 308 case CPU_TOPO_LEVEL_CORE: 309 return topo_info->threads_per_core; 310 case CPU_TOPO_LEVEL_MODULE: 311 return topo_info->threads_per_core * topo_info->cores_per_module; 312 case CPU_TOPO_LEVEL_DIE: 313 return topo_info->threads_per_core * topo_info->cores_per_module * 314 topo_info->modules_per_die; 315 case CPU_TOPO_LEVEL_PACKAGE: 316 return topo_info->threads_per_core * topo_info->cores_per_module * 317 topo_info->modules_per_die * topo_info->dies_per_pkg; 318 default: 319 g_assert_not_reached(); 320 } 321 return 0; 322 } 323 324 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 325 enum CPUTopoLevel topo_level) 326 { 327 switch (topo_level) { 328 case CPU_TOPO_LEVEL_SMT: 329 return 0; 330 case CPU_TOPO_LEVEL_CORE: 331 return apicid_core_offset(topo_info); 332 case CPU_TOPO_LEVEL_MODULE: 333 return apicid_module_offset(topo_info); 334 case CPU_TOPO_LEVEL_DIE: 335 return apicid_die_offset(topo_info); 336 case CPU_TOPO_LEVEL_PACKAGE: 337 return apicid_pkg_offset(topo_info); 338 default: 339 g_assert_not_reached(); 340 } 341 return 0; 342 } 343 344 static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level) 345 { 346 switch (topo_level) { 347 case CPU_TOPO_LEVEL_INVALID: 348 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 349 case CPU_TOPO_LEVEL_SMT: 350 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 351 case CPU_TOPO_LEVEL_CORE: 352 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 353 case CPU_TOPO_LEVEL_MODULE: 354 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 355 case CPU_TOPO_LEVEL_DIE: 356 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 357 default: 358 /* Other types are not supported in QEMU. */ 359 g_assert_not_reached(); 360 } 361 return 0; 362 } 363 364 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 365 X86CPUTopoInfo *topo_info, 366 uint32_t *eax, uint32_t *ebx, 367 uint32_t *ecx, uint32_t *edx) 368 { 369 X86CPU *cpu = env_archcpu(env); 370 unsigned long level, next_level; 371 uint32_t num_threads_next_level, offset_next_level; 372 373 assert(count + 1 < CPU_TOPO_LEVEL_MAX); 374 375 /* 376 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 377 * The search starts from bit 1 (CPU_TOPO_LEVEL_INVALID + 1). 378 */ 379 level = CPU_TOPO_LEVEL_INVALID; 380 for (int i = 0; i <= count; i++) { 381 level = find_next_bit(env->avail_cpu_topo, 382 CPU_TOPO_LEVEL_PACKAGE, 383 level + 1); 384 385 /* 386 * CPUID[0x1f] doesn't explicitly encode the package level, 387 * and it just encodes the invalid level (all fields are 0) 388 * into the last subleaf of 0x1f. 389 */ 390 if (level == CPU_TOPO_LEVEL_PACKAGE) { 391 level = CPU_TOPO_LEVEL_INVALID; 392 break; 393 } 394 } 395 396 if (level == CPU_TOPO_LEVEL_INVALID) { 397 num_threads_next_level = 0; 398 offset_next_level = 0; 399 } else { 400 next_level = find_next_bit(env->avail_cpu_topo, 401 CPU_TOPO_LEVEL_PACKAGE, 402 level + 1); 403 num_threads_next_level = num_threads_by_topo_level(topo_info, 404 next_level); 405 offset_next_level = apicid_offset_by_topo_level(topo_info, 406 next_level); 407 } 408 409 *eax = offset_next_level; 410 /* The count (bits 15-00) doesn't need to be reliable. */ 411 *ebx = num_threads_next_level & 0xffff; 412 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 413 *edx = cpu->apic_id; 414 415 assert(!(*eax & ~0x1f)); 416 } 417 418 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 419 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 420 { 421 assert(cache->size % 1024 == 0); 422 assert(cache->lines_per_tag > 0); 423 assert(cache->associativity > 0); 424 assert(cache->line_size > 0); 425 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 426 (cache->lines_per_tag << 8) | (cache->line_size); 427 } 428 429 #define ASSOC_FULL 0xFF 430 431 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 432 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 433 a == 2 ? 0x2 : \ 434 a == 4 ? 0x4 : \ 435 a == 8 ? 0x6 : \ 436 a == 16 ? 0x8 : \ 437 a == 32 ? 0xA : \ 438 a == 48 ? 0xB : \ 439 a == 64 ? 0xC : \ 440 a == 96 ? 0xD : \ 441 a == 128 ? 0xE : \ 442 a == ASSOC_FULL ? 0xF : \ 443 0 /* invalid value */) 444 445 /* 446 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 447 * @l3 can be NULL. 448 */ 449 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 450 CPUCacheInfo *l3, 451 uint32_t *ecx, uint32_t *edx) 452 { 453 assert(l2->size % 1024 == 0); 454 assert(l2->associativity > 0); 455 assert(l2->lines_per_tag > 0); 456 assert(l2->line_size > 0); 457 *ecx = ((l2->size / 1024) << 16) | 458 (AMD_ENC_ASSOC(l2->associativity) << 12) | 459 (l2->lines_per_tag << 8) | (l2->line_size); 460 461 if (l3) { 462 assert(l3->size % (512 * 1024) == 0); 463 assert(l3->associativity > 0); 464 assert(l3->lines_per_tag > 0); 465 assert(l3->line_size > 0); 466 *edx = ((l3->size / (512 * 1024)) << 18) | 467 (AMD_ENC_ASSOC(l3->associativity) << 12) | 468 (l3->lines_per_tag << 8) | (l3->line_size); 469 } else { 470 *edx = 0; 471 } 472 } 473 474 /* Encode cache info for CPUID[8000001D] */ 475 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 476 X86CPUTopoInfo *topo_info, 477 uint32_t *eax, uint32_t *ebx, 478 uint32_t *ecx, uint32_t *edx) 479 { 480 assert(cache->size == cache->line_size * cache->associativity * 481 cache->partitions * cache->sets); 482 483 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 484 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 485 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; 486 487 assert(cache->line_size > 0); 488 assert(cache->partitions > 0); 489 assert(cache->associativity > 0); 490 /* We don't implement fully-associative caches */ 491 assert(cache->associativity < cache->sets); 492 *ebx = (cache->line_size - 1) | 493 ((cache->partitions - 1) << 12) | 494 ((cache->associativity - 1) << 22); 495 496 assert(cache->sets > 0); 497 *ecx = cache->sets - 1; 498 499 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 500 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 501 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 502 } 503 504 /* Encode cache info for CPUID[8000001E] */ 505 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 506 uint32_t *eax, uint32_t *ebx, 507 uint32_t *ecx, uint32_t *edx) 508 { 509 X86CPUTopoIDs topo_ids; 510 511 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 512 513 *eax = cpu->apic_id; 514 515 /* 516 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 517 * Read-only. Reset: 0000_XXXXh. 518 * See Core::X86::Cpuid::ExtApicId. 519 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 520 * Bits Description 521 * 31:16 Reserved. 522 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 523 * The number of threads per core is ThreadsPerCore+1. 524 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 525 * 526 * NOTE: CoreId is already part of apic_id. Just use it. We can 527 * use all the 8 bits to represent the core_id here. 528 */ 529 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 530 531 /* 532 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 533 * Read-only. Reset: 0000_0XXXh. 534 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 535 * Bits Description 536 * 31:11 Reserved. 537 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 538 * ValidValues: 539 * Value Description 540 * 0h 1 node per processor. 541 * 7h-1h Reserved. 542 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 543 * 544 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 545 * But users can create more nodes than the actual hardware can 546 * support. To genaralize we can use all the upper 8 bits for nodes. 547 * NodeId is combination of node and socket_id which is already decoded 548 * in apic_id. Just use it by shifting. 549 */ 550 if (cpu->legacy_multi_node) { 551 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 552 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 553 } else { 554 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 555 } 556 557 *edx = 0; 558 } 559 560 /* 561 * Definitions of the hardcoded cache entries we expose: 562 * These are legacy cache values. If there is a need to change any 563 * of these values please use builtin_x86_defs 564 */ 565 566 /* L1 data cache: */ 567 static CPUCacheInfo legacy_l1d_cache = { 568 .type = DATA_CACHE, 569 .level = 1, 570 .size = 32 * KiB, 571 .self_init = 1, 572 .line_size = 64, 573 .associativity = 8, 574 .sets = 64, 575 .partitions = 1, 576 .no_invd_sharing = true, 577 .share_level = CPU_TOPO_LEVEL_CORE, 578 }; 579 580 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 581 static CPUCacheInfo legacy_l1d_cache_amd = { 582 .type = DATA_CACHE, 583 .level = 1, 584 .size = 64 * KiB, 585 .self_init = 1, 586 .line_size = 64, 587 .associativity = 2, 588 .sets = 512, 589 .partitions = 1, 590 .lines_per_tag = 1, 591 .no_invd_sharing = true, 592 .share_level = CPU_TOPO_LEVEL_CORE, 593 }; 594 595 /* L1 instruction cache: */ 596 static CPUCacheInfo legacy_l1i_cache = { 597 .type = INSTRUCTION_CACHE, 598 .level = 1, 599 .size = 32 * KiB, 600 .self_init = 1, 601 .line_size = 64, 602 .associativity = 8, 603 .sets = 64, 604 .partitions = 1, 605 .no_invd_sharing = true, 606 .share_level = CPU_TOPO_LEVEL_CORE, 607 }; 608 609 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 610 static CPUCacheInfo legacy_l1i_cache_amd = { 611 .type = INSTRUCTION_CACHE, 612 .level = 1, 613 .size = 64 * KiB, 614 .self_init = 1, 615 .line_size = 64, 616 .associativity = 2, 617 .sets = 512, 618 .partitions = 1, 619 .lines_per_tag = 1, 620 .no_invd_sharing = true, 621 .share_level = CPU_TOPO_LEVEL_CORE, 622 }; 623 624 /* Level 2 unified cache: */ 625 static CPUCacheInfo legacy_l2_cache = { 626 .type = UNIFIED_CACHE, 627 .level = 2, 628 .size = 4 * MiB, 629 .self_init = 1, 630 .line_size = 64, 631 .associativity = 16, 632 .sets = 4096, 633 .partitions = 1, 634 .no_invd_sharing = true, 635 .share_level = CPU_TOPO_LEVEL_CORE, 636 }; 637 638 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 639 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 640 .type = UNIFIED_CACHE, 641 .level = 2, 642 .size = 2 * MiB, 643 .line_size = 64, 644 .associativity = 8, 645 .share_level = CPU_TOPO_LEVEL_INVALID, 646 }; 647 648 649 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 650 static CPUCacheInfo legacy_l2_cache_amd = { 651 .type = UNIFIED_CACHE, 652 .level = 2, 653 .size = 512 * KiB, 654 .line_size = 64, 655 .lines_per_tag = 1, 656 .associativity = 16, 657 .sets = 512, 658 .partitions = 1, 659 .share_level = CPU_TOPO_LEVEL_CORE, 660 }; 661 662 /* Level 3 unified cache: */ 663 static CPUCacheInfo legacy_l3_cache = { 664 .type = UNIFIED_CACHE, 665 .level = 3, 666 .size = 16 * MiB, 667 .line_size = 64, 668 .associativity = 16, 669 .sets = 16384, 670 .partitions = 1, 671 .lines_per_tag = 1, 672 .self_init = true, 673 .inclusive = true, 674 .complex_indexing = true, 675 .share_level = CPU_TOPO_LEVEL_DIE, 676 }; 677 678 /* TLB definitions: */ 679 680 #define L1_DTLB_2M_ASSOC 1 681 #define L1_DTLB_2M_ENTRIES 255 682 #define L1_DTLB_4K_ASSOC 1 683 #define L1_DTLB_4K_ENTRIES 255 684 685 #define L1_ITLB_2M_ASSOC 1 686 #define L1_ITLB_2M_ENTRIES 255 687 #define L1_ITLB_4K_ASSOC 1 688 #define L1_ITLB_4K_ENTRIES 255 689 690 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 691 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 692 #define L2_DTLB_4K_ASSOC 4 693 #define L2_DTLB_4K_ENTRIES 512 694 695 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 696 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 697 #define L2_ITLB_4K_ASSOC 4 698 #define L2_ITLB_4K_ENTRIES 512 699 700 /* CPUID Leaf 0x14 constants: */ 701 #define INTEL_PT_MAX_SUBLEAF 0x1 702 /* 703 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 704 * MSR can be accessed; 705 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 706 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 707 * of Intel PT MSRs across warm reset; 708 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 709 */ 710 #define INTEL_PT_MINIMAL_EBX 0xf 711 /* 712 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 713 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 714 * accessed; 715 * bit[01]: ToPA tables can hold any number of output entries, up to the 716 * maximum allowed by the MaskOrTableOffset field of 717 * IA32_RTIT_OUTPUT_MASK_PTRS; 718 * bit[02]: Support Single-Range Output scheme; 719 */ 720 #define INTEL_PT_MINIMAL_ECX 0x7 721 /* generated packets which contain IP payloads have LIP values */ 722 #define INTEL_PT_IP_LIP (1 << 31) 723 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 724 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 725 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 726 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 727 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 728 729 /* CPUID Leaf 0x1D constants: */ 730 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 731 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 732 #define INTEL_AMX_BYTES_PER_TILE 0x400 733 #define INTEL_AMX_BYTES_PER_ROW 0x40 734 #define INTEL_AMX_TILE_MAX_NAMES 0x8 735 #define INTEL_AMX_TILE_MAX_ROWS 0x10 736 737 /* CPUID Leaf 0x1E constants: */ 738 #define INTEL_AMX_TMUL_MAX_K 0x10 739 #define INTEL_AMX_TMUL_MAX_N 0x40 740 741 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 742 uint32_t vendor2, uint32_t vendor3) 743 { 744 int i; 745 for (i = 0; i < 4; i++) { 746 dst[i] = vendor1 >> (8 * i); 747 dst[i + 4] = vendor2 >> (8 * i); 748 dst[i + 8] = vendor3 >> (8 * i); 749 } 750 dst[CPUID_VENDOR_SZ] = '\0'; 751 } 752 753 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 754 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 755 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 756 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 757 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 758 CPUID_PSE36 | CPUID_FXSR) 759 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 760 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 761 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 762 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 763 CPUID_PAE | CPUID_SEP | CPUID_APIC) 764 765 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 766 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 767 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 768 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 769 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 770 /* partly implemented: 771 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 772 /* missing: 773 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 774 775 /* 776 * Kernel-only features that can be shown to usermode programs even if 777 * they aren't actually supported by TCG, because qemu-user only runs 778 * in CPL=3; remove them if they are ever implemented for system emulation. 779 */ 780 #if defined CONFIG_USER_ONLY 781 #define CPUID_EXT_KERNEL_FEATURES \ 782 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 783 #else 784 #define CPUID_EXT_KERNEL_FEATURES 0 785 #endif 786 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 787 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 788 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 789 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 790 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 791 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 792 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 793 /* missing: 794 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 795 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 796 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 797 CPUID_EXT_TSC_DEADLINE_TIMER 798 */ 799 800 #ifdef TARGET_X86_64 801 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 802 #else 803 #define TCG_EXT2_X86_64_FEATURES 0 804 #endif 805 806 /* 807 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 808 * in usermode or by 32-bit programs. Those are added to supported 809 * TCG features unconditionally in user-mode emulation mode. This may 810 * indeed seem strange or incorrect, but it works because code running 811 * under usermode emulation cannot access them. 812 * 813 * Even for long mode, qemu-i386 is not running "a userspace program on a 814 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 815 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 816 * but again the difference is only visible in kernel mode. 817 */ 818 #if defined CONFIG_LINUX_USER 819 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 820 #elif defined CONFIG_USER_ONLY 821 /* FIXME: Long mode not yet supported for i386 bsd-user */ 822 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 823 #else 824 #define CPUID_EXT2_KERNEL_FEATURES 0 825 #endif 826 827 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 828 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 829 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 830 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 831 CPUID_EXT2_KERNEL_FEATURES) 832 833 #if defined CONFIG_USER_ONLY 834 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 835 #else 836 #define CPUID_EXT3_KERNEL_FEATURES 0 837 #endif 838 839 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 840 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 841 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES) 842 843 #define TCG_EXT4_FEATURES 0 844 845 #if defined CONFIG_USER_ONLY 846 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 847 #else 848 #define CPUID_SVM_KERNEL_FEATURES 0 849 #endif 850 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 851 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 852 853 #define TCG_KVM_FEATURES 0 854 855 #if defined CONFIG_USER_ONLY 856 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 857 #else 858 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 859 #endif 860 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 861 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 862 CPUID_7_0_EBX_CLFLUSHOPT | \ 863 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 864 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 865 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 866 /* missing: 867 CPUID_7_0_EBX_HLE 868 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 869 870 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 871 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 872 #else 873 #define TCG_7_0_ECX_RDPID 0 874 #endif 875 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 876 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 877 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 878 TCG_7_0_ECX_RDPID) 879 880 #if defined CONFIG_USER_ONLY 881 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 882 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 883 #else 884 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 885 #endif 886 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 887 888 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 889 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 890 #define TCG_7_1_EDX_FEATURES 0 891 #define TCG_7_2_EDX_FEATURES 0 892 #define TCG_APM_FEATURES 0 893 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 894 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 895 /* missing: 896 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 897 #define TCG_14_0_ECX_FEATURES 0 898 #define TCG_SGX_12_0_EAX_FEATURES 0 899 #define TCG_SGX_12_0_EBX_FEATURES 0 900 #define TCG_SGX_12_1_EAX_FEATURES 0 901 902 #if defined CONFIG_USER_ONLY 903 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 904 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 905 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 906 CPUID_8000_0008_EBX_AMD_PSFD) 907 #else 908 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 909 #endif 910 911 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 912 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 913 914 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 915 [FEAT_1_EDX] = { 916 .type = CPUID_FEATURE_WORD, 917 .feat_names = { 918 "fpu", "vme", "de", "pse", 919 "tsc", "msr", "pae", "mce", 920 "cx8", "apic", NULL, "sep", 921 "mtrr", "pge", "mca", "cmov", 922 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 923 NULL, "ds" /* Intel dts */, "acpi", "mmx", 924 "fxsr", "sse", "sse2", "ss", 925 "ht" /* Intel htt */, "tm", "ia64", "pbe", 926 }, 927 .cpuid = {.eax = 1, .reg = R_EDX, }, 928 .tcg_features = TCG_FEATURES, 929 .no_autoenable_flags = CPUID_HT, 930 }, 931 [FEAT_1_ECX] = { 932 .type = CPUID_FEATURE_WORD, 933 .feat_names = { 934 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 935 "ds-cpl", "vmx", "smx", "est", 936 "tm2", "ssse3", "cid", NULL, 937 "fma", "cx16", "xtpr", "pdcm", 938 NULL, "pcid", "dca", "sse4.1", 939 "sse4.2", "x2apic", "movbe", "popcnt", 940 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 941 "avx", "f16c", "rdrand", "hypervisor", 942 }, 943 .cpuid = { .eax = 1, .reg = R_ECX, }, 944 .tcg_features = TCG_EXT_FEATURES, 945 }, 946 /* Feature names that are already defined on feature_name[] but 947 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 948 * names on feat_names below. They are copied automatically 949 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 950 */ 951 [FEAT_8000_0001_EDX] = { 952 .type = CPUID_FEATURE_WORD, 953 .feat_names = { 954 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 955 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 956 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 957 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 958 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 959 "nx", NULL, "mmxext", NULL /* mmx */, 960 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 961 NULL, "lm", "3dnowext", "3dnow", 962 }, 963 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 964 .tcg_features = TCG_EXT2_FEATURES, 965 }, 966 [FEAT_8000_0001_ECX] = { 967 .type = CPUID_FEATURE_WORD, 968 .feat_names = { 969 "lahf-lm", "cmp-legacy", "svm", "extapic", 970 "cr8legacy", "abm", "sse4a", "misalignsse", 971 "3dnowprefetch", "osvw", "ibs", "xop", 972 "skinit", "wdt", NULL, "lwp", 973 "fma4", "tce", NULL, "nodeid-msr", 974 NULL, "tbm", "topoext", "perfctr-core", 975 "perfctr-nb", NULL, NULL, NULL, 976 NULL, NULL, NULL, NULL, 977 }, 978 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 979 .tcg_features = TCG_EXT3_FEATURES, 980 /* 981 * TOPOEXT is always allowed but can't be enabled blindly by 982 * "-cpu host", as it requires consistent cache topology info 983 * to be provided so it doesn't confuse guests. 984 */ 985 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 986 }, 987 [FEAT_C000_0001_EDX] = { 988 .type = CPUID_FEATURE_WORD, 989 .feat_names = { 990 NULL, NULL, "xstore", "xstore-en", 991 NULL, NULL, "xcrypt", "xcrypt-en", 992 "ace2", "ace2-en", "phe", "phe-en", 993 "pmm", "pmm-en", NULL, NULL, 994 NULL, NULL, NULL, NULL, 995 NULL, NULL, NULL, NULL, 996 NULL, NULL, NULL, NULL, 997 NULL, NULL, NULL, NULL, 998 }, 999 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1000 .tcg_features = TCG_EXT4_FEATURES, 1001 }, 1002 [FEAT_KVM] = { 1003 .type = CPUID_FEATURE_WORD, 1004 .feat_names = { 1005 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1006 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1007 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1008 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1009 NULL, NULL, NULL, NULL, 1010 NULL, NULL, NULL, NULL, 1011 "kvmclock-stable-bit", NULL, NULL, NULL, 1012 NULL, NULL, NULL, NULL, 1013 }, 1014 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1015 .tcg_features = TCG_KVM_FEATURES, 1016 }, 1017 [FEAT_KVM_HINTS] = { 1018 .type = CPUID_FEATURE_WORD, 1019 .feat_names = { 1020 "kvm-hint-dedicated", NULL, NULL, NULL, 1021 NULL, NULL, NULL, NULL, 1022 NULL, NULL, NULL, NULL, 1023 NULL, NULL, NULL, NULL, 1024 NULL, NULL, NULL, NULL, 1025 NULL, NULL, NULL, NULL, 1026 NULL, NULL, NULL, NULL, 1027 NULL, NULL, NULL, NULL, 1028 }, 1029 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1030 .tcg_features = TCG_KVM_FEATURES, 1031 /* 1032 * KVM hints aren't auto-enabled by -cpu host, they need to be 1033 * explicitly enabled in the command-line. 1034 */ 1035 .no_autoenable_flags = ~0U, 1036 }, 1037 [FEAT_SVM] = { 1038 .type = CPUID_FEATURE_WORD, 1039 .feat_names = { 1040 "npt", "lbrv", "svm-lock", "nrip-save", 1041 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1042 NULL, NULL, "pause-filter", NULL, 1043 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1044 "vgif", NULL, NULL, NULL, 1045 NULL, NULL, NULL, NULL, 1046 NULL, "vnmi", NULL, NULL, 1047 "svme-addr-chk", NULL, NULL, NULL, 1048 }, 1049 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1050 .tcg_features = TCG_SVM_FEATURES, 1051 }, 1052 [FEAT_7_0_EBX] = { 1053 .type = CPUID_FEATURE_WORD, 1054 .feat_names = { 1055 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1056 "hle", "avx2", "fdp-excptn-only", "smep", 1057 "bmi2", "erms", "invpcid", "rtm", 1058 NULL, "zero-fcs-fds", "mpx", NULL, 1059 "avx512f", "avx512dq", "rdseed", "adx", 1060 "smap", "avx512ifma", "pcommit", "clflushopt", 1061 "clwb", "intel-pt", "avx512pf", "avx512er", 1062 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1063 }, 1064 .cpuid = { 1065 .eax = 7, 1066 .needs_ecx = true, .ecx = 0, 1067 .reg = R_EBX, 1068 }, 1069 .tcg_features = TCG_7_0_EBX_FEATURES, 1070 }, 1071 [FEAT_7_0_ECX] = { 1072 .type = CPUID_FEATURE_WORD, 1073 .feat_names = { 1074 NULL, "avx512vbmi", "umip", "pku", 1075 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1076 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1077 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1078 "la57", NULL, NULL, NULL, 1079 NULL, NULL, "rdpid", NULL, 1080 "bus-lock-detect", "cldemote", NULL, "movdiri", 1081 "movdir64b", NULL, "sgxlc", "pks", 1082 }, 1083 .cpuid = { 1084 .eax = 7, 1085 .needs_ecx = true, .ecx = 0, 1086 .reg = R_ECX, 1087 }, 1088 .tcg_features = TCG_7_0_ECX_FEATURES, 1089 }, 1090 [FEAT_7_0_EDX] = { 1091 .type = CPUID_FEATURE_WORD, 1092 .feat_names = { 1093 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1094 "fsrm", NULL, NULL, NULL, 1095 "avx512-vp2intersect", NULL, "md-clear", NULL, 1096 NULL, NULL, "serialize", NULL, 1097 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1098 NULL, NULL, "amx-bf16", "avx512-fp16", 1099 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1100 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1101 }, 1102 .cpuid = { 1103 .eax = 7, 1104 .needs_ecx = true, .ecx = 0, 1105 .reg = R_EDX, 1106 }, 1107 .tcg_features = TCG_7_0_EDX_FEATURES, 1108 }, 1109 [FEAT_7_1_EAX] = { 1110 .type = CPUID_FEATURE_WORD, 1111 .feat_names = { 1112 NULL, NULL, NULL, NULL, 1113 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1114 NULL, NULL, "fzrm", "fsrs", 1115 "fsrc", NULL, NULL, NULL, 1116 NULL, "fred", "lkgs", "wrmsrns", 1117 NULL, "amx-fp16", NULL, "avx-ifma", 1118 NULL, NULL, "lam", NULL, 1119 NULL, NULL, NULL, NULL, 1120 }, 1121 .cpuid = { 1122 .eax = 7, 1123 .needs_ecx = true, .ecx = 1, 1124 .reg = R_EAX, 1125 }, 1126 .tcg_features = TCG_7_1_EAX_FEATURES, 1127 }, 1128 [FEAT_7_1_EDX] = { 1129 .type = CPUID_FEATURE_WORD, 1130 .feat_names = { 1131 NULL, NULL, NULL, NULL, 1132 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1133 "amx-complex", NULL, "avx-vnni-int16", NULL, 1134 NULL, NULL, "prefetchiti", NULL, 1135 NULL, NULL, NULL, NULL, 1136 NULL, NULL, NULL, NULL, 1137 NULL, NULL, NULL, NULL, 1138 NULL, NULL, NULL, NULL, 1139 }, 1140 .cpuid = { 1141 .eax = 7, 1142 .needs_ecx = true, .ecx = 1, 1143 .reg = R_EDX, 1144 }, 1145 .tcg_features = TCG_7_1_EDX_FEATURES, 1146 }, 1147 [FEAT_7_2_EDX] = { 1148 .type = CPUID_FEATURE_WORD, 1149 .feat_names = { 1150 "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u", 1151 "bhi-ctrl", "mcdt-no", NULL, NULL, 1152 NULL, NULL, NULL, NULL, 1153 NULL, NULL, NULL, NULL, 1154 NULL, NULL, NULL, NULL, 1155 NULL, NULL, NULL, NULL, 1156 NULL, NULL, NULL, NULL, 1157 NULL, NULL, NULL, NULL, 1158 }, 1159 .cpuid = { 1160 .eax = 7, 1161 .needs_ecx = true, .ecx = 2, 1162 .reg = R_EDX, 1163 }, 1164 .tcg_features = TCG_7_2_EDX_FEATURES, 1165 }, 1166 [FEAT_8000_0007_EDX] = { 1167 .type = CPUID_FEATURE_WORD, 1168 .feat_names = { 1169 NULL, NULL, NULL, NULL, 1170 NULL, NULL, NULL, NULL, 1171 "invtsc", NULL, NULL, NULL, 1172 NULL, NULL, NULL, NULL, 1173 NULL, NULL, NULL, NULL, 1174 NULL, NULL, NULL, NULL, 1175 NULL, NULL, NULL, NULL, 1176 NULL, NULL, NULL, NULL, 1177 }, 1178 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1179 .tcg_features = TCG_APM_FEATURES, 1180 .unmigratable_flags = CPUID_APM_INVTSC, 1181 }, 1182 [FEAT_8000_0007_EBX] = { 1183 .type = CPUID_FEATURE_WORD, 1184 .feat_names = { 1185 "overflow-recov", "succor", NULL, NULL, 1186 NULL, NULL, NULL, NULL, 1187 NULL, NULL, NULL, NULL, 1188 NULL, NULL, NULL, NULL, 1189 NULL, NULL, NULL, NULL, 1190 NULL, NULL, NULL, NULL, 1191 NULL, NULL, NULL, NULL, 1192 NULL, NULL, NULL, NULL, 1193 }, 1194 .cpuid = { .eax = 0x80000007, .reg = R_EBX, }, 1195 .tcg_features = 0, 1196 .unmigratable_flags = 0, 1197 }, 1198 [FEAT_8000_0008_EBX] = { 1199 .type = CPUID_FEATURE_WORD, 1200 .feat_names = { 1201 "clzero", NULL, "xsaveerptr", NULL, 1202 NULL, NULL, NULL, NULL, 1203 NULL, "wbnoinvd", NULL, NULL, 1204 "ibpb", NULL, "ibrs", "amd-stibp", 1205 NULL, "stibp-always-on", NULL, NULL, 1206 NULL, NULL, NULL, NULL, 1207 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1208 "amd-psfd", NULL, NULL, NULL, 1209 }, 1210 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1211 .tcg_features = TCG_8000_0008_EBX, 1212 .unmigratable_flags = 0, 1213 }, 1214 [FEAT_8000_0021_EAX] = { 1215 .type = CPUID_FEATURE_WORD, 1216 .feat_names = { 1217 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1218 NULL, NULL, "null-sel-clr-base", NULL, 1219 "auto-ibrs", NULL, NULL, NULL, 1220 NULL, NULL, NULL, NULL, 1221 NULL, NULL, NULL, NULL, 1222 NULL, NULL, NULL, NULL, 1223 "eraps", NULL, NULL, "sbpb", 1224 "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL, 1225 }, 1226 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1227 .tcg_features = 0, 1228 .unmigratable_flags = 0, 1229 }, 1230 [FEAT_8000_0021_EBX] = { 1231 .type = CPUID_FEATURE_WORD, 1232 .cpuid = { .eax = 0x80000021, .reg = R_EBX, }, 1233 .tcg_features = 0, 1234 .unmigratable_flags = 0, 1235 }, 1236 [FEAT_8000_0022_EAX] = { 1237 .type = CPUID_FEATURE_WORD, 1238 .feat_names = { 1239 "perfmon-v2", NULL, NULL, NULL, 1240 NULL, NULL, NULL, NULL, 1241 NULL, NULL, NULL, NULL, 1242 NULL, NULL, NULL, NULL, 1243 NULL, NULL, NULL, NULL, 1244 NULL, NULL, NULL, NULL, 1245 NULL, NULL, NULL, NULL, 1246 NULL, NULL, NULL, NULL, 1247 }, 1248 .cpuid = { .eax = 0x80000022, .reg = R_EAX, }, 1249 .tcg_features = 0, 1250 .unmigratable_flags = 0, 1251 }, 1252 [FEAT_XSAVE] = { 1253 .type = CPUID_FEATURE_WORD, 1254 .feat_names = { 1255 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1256 "xfd", NULL, NULL, NULL, 1257 NULL, NULL, NULL, NULL, 1258 NULL, NULL, NULL, NULL, 1259 NULL, NULL, NULL, NULL, 1260 NULL, NULL, NULL, NULL, 1261 NULL, NULL, NULL, NULL, 1262 NULL, NULL, NULL, NULL, 1263 }, 1264 .cpuid = { 1265 .eax = 0xd, 1266 .needs_ecx = true, .ecx = 1, 1267 .reg = R_EAX, 1268 }, 1269 .tcg_features = TCG_XSAVE_FEATURES, 1270 }, 1271 [FEAT_XSAVE_XSS_LO] = { 1272 .type = CPUID_FEATURE_WORD, 1273 .feat_names = { 1274 NULL, NULL, NULL, NULL, 1275 NULL, NULL, NULL, NULL, 1276 NULL, NULL, NULL, NULL, 1277 NULL, NULL, NULL, NULL, 1278 NULL, NULL, NULL, NULL, 1279 NULL, NULL, NULL, NULL, 1280 NULL, NULL, NULL, NULL, 1281 NULL, NULL, NULL, NULL, 1282 }, 1283 .cpuid = { 1284 .eax = 0xD, 1285 .needs_ecx = true, 1286 .ecx = 1, 1287 .reg = R_ECX, 1288 }, 1289 }, 1290 [FEAT_XSAVE_XSS_HI] = { 1291 .type = CPUID_FEATURE_WORD, 1292 .cpuid = { 1293 .eax = 0xD, 1294 .needs_ecx = true, 1295 .ecx = 1, 1296 .reg = R_EDX 1297 }, 1298 }, 1299 [FEAT_6_EAX] = { 1300 .type = CPUID_FEATURE_WORD, 1301 .feat_names = { 1302 NULL, NULL, "arat", NULL, 1303 NULL, NULL, NULL, NULL, 1304 NULL, NULL, NULL, NULL, 1305 NULL, NULL, NULL, NULL, 1306 NULL, NULL, NULL, NULL, 1307 NULL, NULL, NULL, NULL, 1308 NULL, NULL, NULL, NULL, 1309 NULL, NULL, NULL, NULL, 1310 }, 1311 .cpuid = { .eax = 6, .reg = R_EAX, }, 1312 .tcg_features = TCG_6_EAX_FEATURES, 1313 }, 1314 [FEAT_XSAVE_XCR0_LO] = { 1315 .type = CPUID_FEATURE_WORD, 1316 .cpuid = { 1317 .eax = 0xD, 1318 .needs_ecx = true, .ecx = 0, 1319 .reg = R_EAX, 1320 }, 1321 .tcg_features = ~0U, 1322 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1323 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1324 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1325 XSTATE_PKRU_MASK, 1326 }, 1327 [FEAT_XSAVE_XCR0_HI] = { 1328 .type = CPUID_FEATURE_WORD, 1329 .cpuid = { 1330 .eax = 0xD, 1331 .needs_ecx = true, .ecx = 0, 1332 .reg = R_EDX, 1333 }, 1334 .tcg_features = ~0U, 1335 }, 1336 /*Below are MSR exposed features*/ 1337 [FEAT_ARCH_CAPABILITIES] = { 1338 .type = MSR_FEATURE_WORD, 1339 .feat_names = { 1340 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1341 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1342 "taa-no", NULL, NULL, NULL, 1343 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1344 NULL, "fb-clear", NULL, NULL, 1345 NULL, NULL, NULL, NULL, 1346 "pbrsb-no", NULL, "gds-no", "rfds-no", 1347 "rfds-clear", NULL, NULL, NULL, 1348 }, 1349 .msr = { 1350 .index = MSR_IA32_ARCH_CAPABILITIES, 1351 }, 1352 /* 1353 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1354 * cannot be read from user mode. Therefore, it has no impact 1355 > on any user-mode operation, and warnings about unsupported 1356 * features do not matter. 1357 */ 1358 .tcg_features = ~0U, 1359 }, 1360 [FEAT_CORE_CAPABILITY] = { 1361 .type = MSR_FEATURE_WORD, 1362 .feat_names = { 1363 NULL, NULL, NULL, NULL, 1364 NULL, "split-lock-detect", NULL, NULL, 1365 NULL, NULL, NULL, NULL, 1366 NULL, NULL, NULL, NULL, 1367 NULL, NULL, NULL, NULL, 1368 NULL, NULL, NULL, NULL, 1369 NULL, NULL, NULL, NULL, 1370 NULL, NULL, NULL, NULL, 1371 }, 1372 .msr = { 1373 .index = MSR_IA32_CORE_CAPABILITY, 1374 }, 1375 }, 1376 [FEAT_PERF_CAPABILITIES] = { 1377 .type = MSR_FEATURE_WORD, 1378 .feat_names = { 1379 NULL, NULL, NULL, NULL, 1380 NULL, NULL, NULL, NULL, 1381 NULL, NULL, NULL, NULL, 1382 NULL, "full-width-write", NULL, NULL, 1383 NULL, NULL, NULL, NULL, 1384 NULL, NULL, NULL, NULL, 1385 NULL, NULL, NULL, NULL, 1386 NULL, NULL, NULL, NULL, 1387 }, 1388 .msr = { 1389 .index = MSR_IA32_PERF_CAPABILITIES, 1390 }, 1391 }, 1392 1393 [FEAT_VMX_PROCBASED_CTLS] = { 1394 .type = MSR_FEATURE_WORD, 1395 .feat_names = { 1396 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1397 NULL, NULL, NULL, "vmx-hlt-exit", 1398 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1399 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1400 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1401 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1402 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1403 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1404 }, 1405 .msr = { 1406 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1407 } 1408 }, 1409 1410 [FEAT_VMX_SECONDARY_CTLS] = { 1411 .type = MSR_FEATURE_WORD, 1412 .feat_names = { 1413 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1414 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1415 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1416 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1417 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1418 "vmx-xsaves", NULL, NULL, NULL, 1419 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1420 NULL, NULL, NULL, NULL, 1421 }, 1422 .msr = { 1423 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1424 } 1425 }, 1426 1427 [FEAT_VMX_PINBASED_CTLS] = { 1428 .type = MSR_FEATURE_WORD, 1429 .feat_names = { 1430 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1431 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1432 NULL, NULL, NULL, NULL, 1433 NULL, NULL, NULL, NULL, 1434 NULL, NULL, NULL, NULL, 1435 NULL, NULL, NULL, NULL, 1436 NULL, NULL, NULL, NULL, 1437 NULL, NULL, NULL, NULL, 1438 }, 1439 .msr = { 1440 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1441 } 1442 }, 1443 1444 [FEAT_VMX_EXIT_CTLS] = { 1445 .type = MSR_FEATURE_WORD, 1446 /* 1447 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1448 * the LM CPUID bit. 1449 */ 1450 .feat_names = { 1451 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1452 NULL, NULL, NULL, NULL, 1453 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1454 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1455 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1456 "vmx-exit-save-efer", "vmx-exit-load-efer", 1457 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1458 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1459 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", 1460 }, 1461 .msr = { 1462 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1463 } 1464 }, 1465 1466 [FEAT_VMX_ENTRY_CTLS] = { 1467 .type = MSR_FEATURE_WORD, 1468 .feat_names = { 1469 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1470 NULL, NULL, NULL, NULL, 1471 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1472 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1473 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1474 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred", 1475 NULL, NULL, NULL, NULL, 1476 NULL, NULL, NULL, NULL, 1477 }, 1478 .msr = { 1479 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1480 } 1481 }, 1482 1483 [FEAT_VMX_MISC] = { 1484 .type = MSR_FEATURE_WORD, 1485 .feat_names = { 1486 NULL, NULL, NULL, NULL, 1487 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1488 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1489 NULL, NULL, NULL, NULL, 1490 NULL, NULL, NULL, NULL, 1491 NULL, NULL, NULL, NULL, 1492 NULL, NULL, NULL, NULL, 1493 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1494 }, 1495 .msr = { 1496 .index = MSR_IA32_VMX_MISC, 1497 } 1498 }, 1499 1500 [FEAT_VMX_EPT_VPID_CAPS] = { 1501 .type = MSR_FEATURE_WORD, 1502 .feat_names = { 1503 "vmx-ept-execonly", NULL, NULL, NULL, 1504 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1505 NULL, NULL, NULL, NULL, 1506 NULL, NULL, NULL, NULL, 1507 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1508 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1509 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1510 NULL, NULL, NULL, NULL, 1511 "vmx-invvpid", NULL, NULL, NULL, 1512 NULL, NULL, NULL, NULL, 1513 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1514 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1515 NULL, NULL, NULL, NULL, 1516 NULL, NULL, NULL, NULL, 1517 NULL, NULL, NULL, NULL, 1518 NULL, NULL, NULL, NULL, 1519 NULL, NULL, NULL, NULL, 1520 }, 1521 .msr = { 1522 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1523 } 1524 }, 1525 1526 [FEAT_VMX_BASIC] = { 1527 .type = MSR_FEATURE_WORD, 1528 .feat_names = { 1529 [54] = "vmx-ins-outs", 1530 [55] = "vmx-true-ctls", 1531 [56] = "vmx-any-errcode", 1532 [58] = "vmx-nested-exception", 1533 }, 1534 .msr = { 1535 .index = MSR_IA32_VMX_BASIC, 1536 }, 1537 /* Just to be safe - we don't support setting the MSEG version field. */ 1538 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1539 }, 1540 1541 [FEAT_VMX_VMFUNC] = { 1542 .type = MSR_FEATURE_WORD, 1543 .feat_names = { 1544 [0] = "vmx-eptp-switching", 1545 }, 1546 .msr = { 1547 .index = MSR_IA32_VMX_VMFUNC, 1548 } 1549 }, 1550 1551 [FEAT_14_0_ECX] = { 1552 .type = CPUID_FEATURE_WORD, 1553 .feat_names = { 1554 NULL, NULL, NULL, NULL, 1555 NULL, NULL, NULL, NULL, 1556 NULL, NULL, NULL, NULL, 1557 NULL, NULL, NULL, NULL, 1558 NULL, NULL, NULL, NULL, 1559 NULL, NULL, NULL, NULL, 1560 NULL, NULL, NULL, NULL, 1561 NULL, NULL, NULL, "intel-pt-lip", 1562 }, 1563 .cpuid = { 1564 .eax = 0x14, 1565 .needs_ecx = true, .ecx = 0, 1566 .reg = R_ECX, 1567 }, 1568 .tcg_features = TCG_14_0_ECX_FEATURES, 1569 }, 1570 1571 [FEAT_SGX_12_0_EAX] = { 1572 .type = CPUID_FEATURE_WORD, 1573 .feat_names = { 1574 "sgx1", "sgx2", NULL, NULL, 1575 NULL, NULL, NULL, NULL, 1576 NULL, NULL, NULL, "sgx-edeccssa", 1577 NULL, NULL, NULL, NULL, 1578 NULL, NULL, NULL, NULL, 1579 NULL, NULL, NULL, NULL, 1580 NULL, NULL, NULL, NULL, 1581 NULL, NULL, NULL, NULL, 1582 }, 1583 .cpuid = { 1584 .eax = 0x12, 1585 .needs_ecx = true, .ecx = 0, 1586 .reg = R_EAX, 1587 }, 1588 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1589 }, 1590 1591 [FEAT_SGX_12_0_EBX] = { 1592 .type = CPUID_FEATURE_WORD, 1593 .feat_names = { 1594 "sgx-exinfo" , NULL, NULL, NULL, 1595 NULL, NULL, NULL, NULL, 1596 NULL, NULL, NULL, NULL, 1597 NULL, NULL, NULL, NULL, 1598 NULL, NULL, NULL, NULL, 1599 NULL, NULL, NULL, NULL, 1600 NULL, NULL, NULL, NULL, 1601 NULL, NULL, NULL, NULL, 1602 }, 1603 .cpuid = { 1604 .eax = 0x12, 1605 .needs_ecx = true, .ecx = 0, 1606 .reg = R_EBX, 1607 }, 1608 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1609 }, 1610 1611 [FEAT_SGX_12_1_EAX] = { 1612 .type = CPUID_FEATURE_WORD, 1613 .feat_names = { 1614 NULL, "sgx-debug", "sgx-mode64", NULL, 1615 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1616 NULL, NULL, "sgx-aex-notify", NULL, 1617 NULL, NULL, NULL, NULL, 1618 NULL, NULL, NULL, NULL, 1619 NULL, NULL, NULL, NULL, 1620 NULL, NULL, NULL, NULL, 1621 NULL, NULL, NULL, NULL, 1622 }, 1623 .cpuid = { 1624 .eax = 0x12, 1625 .needs_ecx = true, .ecx = 1, 1626 .reg = R_EAX, 1627 }, 1628 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1629 }, 1630 }; 1631 1632 typedef struct FeatureMask { 1633 FeatureWord index; 1634 uint64_t mask; 1635 } FeatureMask; 1636 1637 typedef struct FeatureDep { 1638 FeatureMask from, to; 1639 } FeatureDep; 1640 1641 static FeatureDep feature_dependencies[] = { 1642 { 1643 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1644 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1645 }, 1646 { 1647 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1648 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1649 }, 1650 { 1651 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1652 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1653 }, 1654 { 1655 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1656 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1657 }, 1658 { 1659 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1660 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1661 }, 1662 { 1663 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1664 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1665 }, 1666 { 1667 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1668 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1669 }, 1670 { 1671 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1672 .to = { FEAT_VMX_MISC, ~0ull }, 1673 }, 1674 { 1675 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1676 .to = { FEAT_VMX_BASIC, ~0ull }, 1677 }, 1678 { 1679 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1680 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1681 }, 1682 { 1683 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1684 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1685 }, 1686 { 1687 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1688 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1689 }, 1690 { 1691 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1692 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1693 }, 1694 { 1695 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1696 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1697 }, 1698 { 1699 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1700 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1701 }, 1702 { 1703 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1704 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1705 }, 1706 { 1707 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1708 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1709 }, 1710 { 1711 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1712 .to = { FEAT_14_0_ECX, ~0ull }, 1713 }, 1714 { 1715 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1716 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1717 }, 1718 { 1719 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1720 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1721 }, 1722 { 1723 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1724 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1725 }, 1726 { 1727 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1728 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1729 }, 1730 { 1731 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1732 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1733 }, 1734 { 1735 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1736 .to = { FEAT_SVM, ~0ull }, 1737 }, 1738 { 1739 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1740 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1741 }, 1742 { 1743 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1744 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1745 }, 1746 { 1747 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1748 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1749 }, 1750 { 1751 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_WRMSRNS }, 1752 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1753 }, 1754 { 1755 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1756 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_SGX_LC }, 1757 }, 1758 { 1759 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1760 .to = { FEAT_SGX_12_0_EAX, ~0ull }, 1761 }, 1762 { 1763 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1764 .to = { FEAT_SGX_12_0_EBX, ~0ull }, 1765 }, 1766 { 1767 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1768 .to = { FEAT_SGX_12_1_EAX, ~0ull }, 1769 }, 1770 }; 1771 1772 typedef struct X86RegisterInfo32 { 1773 /* Name of register */ 1774 const char *name; 1775 /* QAPI enum value register */ 1776 X86CPURegister32 qapi_enum; 1777 } X86RegisterInfo32; 1778 1779 #define REGISTER(reg) \ 1780 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1781 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1782 REGISTER(EAX), 1783 REGISTER(ECX), 1784 REGISTER(EDX), 1785 REGISTER(EBX), 1786 REGISTER(ESP), 1787 REGISTER(EBP), 1788 REGISTER(ESI), 1789 REGISTER(EDI), 1790 }; 1791 #undef REGISTER 1792 1793 /* CPUID feature bits available in XSS */ 1794 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1795 1796 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1797 [XSTATE_FP_BIT] = { 1798 /* x87 FP state component is always enabled if XSAVE is supported */ 1799 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1800 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1801 }, 1802 [XSTATE_SSE_BIT] = { 1803 /* SSE state component is always enabled if XSAVE is supported */ 1804 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1805 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1806 }, 1807 [XSTATE_YMM_BIT] = 1808 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1809 .size = sizeof(XSaveAVX) }, 1810 [XSTATE_BNDREGS_BIT] = 1811 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1812 .size = sizeof(XSaveBNDREG) }, 1813 [XSTATE_BNDCSR_BIT] = 1814 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1815 .size = sizeof(XSaveBNDCSR) }, 1816 [XSTATE_OPMASK_BIT] = 1817 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1818 .size = sizeof(XSaveOpmask) }, 1819 [XSTATE_ZMM_Hi256_BIT] = 1820 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1821 .size = sizeof(XSaveZMM_Hi256) }, 1822 [XSTATE_Hi16_ZMM_BIT] = 1823 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1824 .size = sizeof(XSaveHi16_ZMM) }, 1825 [XSTATE_PKRU_BIT] = 1826 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1827 .size = sizeof(XSavePKRU) }, 1828 [XSTATE_ARCH_LBR_BIT] = { 1829 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1830 .offset = 0 /*supervisor mode component, offset = 0 */, 1831 .size = sizeof(XSavesArchLBR) }, 1832 [XSTATE_XTILE_CFG_BIT] = { 1833 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1834 .size = sizeof(XSaveXTILECFG), 1835 }, 1836 [XSTATE_XTILE_DATA_BIT] = { 1837 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1838 .size = sizeof(XSaveXTILEDATA) 1839 }, 1840 }; 1841 1842 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1843 { 1844 uint64_t ret = x86_ext_save_areas[0].size; 1845 const ExtSaveArea *esa; 1846 uint32_t offset = 0; 1847 int i; 1848 1849 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1850 esa = &x86_ext_save_areas[i]; 1851 if ((mask >> i) & 1) { 1852 offset = compacted ? ret : esa->offset; 1853 ret = MAX(ret, offset + esa->size); 1854 } 1855 } 1856 return ret; 1857 } 1858 1859 static inline bool accel_uses_host_cpuid(void) 1860 { 1861 return kvm_enabled() || hvf_enabled(); 1862 } 1863 1864 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1865 { 1866 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1867 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1868 } 1869 1870 /* Return name of 32-bit register, from a R_* constant */ 1871 static const char *get_register_name_32(unsigned int reg) 1872 { 1873 if (reg >= CPU_NB_REGS32) { 1874 return NULL; 1875 } 1876 return x86_reg_info_32[reg].name; 1877 } 1878 1879 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1880 { 1881 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1882 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1883 } 1884 1885 /* 1886 * Returns the set of feature flags that are supported and migratable by 1887 * QEMU, for a given FeatureWord. 1888 */ 1889 static uint64_t x86_cpu_get_migratable_flags(X86CPU *cpu, FeatureWord w) 1890 { 1891 FeatureWordInfo *wi = &feature_word_info[w]; 1892 CPUX86State *env = &cpu->env; 1893 uint64_t r = 0; 1894 int i; 1895 1896 for (i = 0; i < 64; i++) { 1897 uint64_t f = 1ULL << i; 1898 1899 /* If the feature name is known, it is implicitly considered migratable, 1900 * unless it is explicitly set in unmigratable_flags */ 1901 if ((wi->migratable_flags & f) || 1902 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1903 r |= f; 1904 } 1905 } 1906 1907 /* when tsc-khz is set explicitly, invtsc is migratable */ 1908 if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) { 1909 r |= CPUID_APM_INVTSC; 1910 } 1911 1912 return r; 1913 } 1914 1915 void host_cpuid(uint32_t function, uint32_t count, 1916 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1917 { 1918 uint32_t vec[4]; 1919 1920 #ifdef __x86_64__ 1921 asm volatile("cpuid" 1922 : "=a"(vec[0]), "=b"(vec[1]), 1923 "=c"(vec[2]), "=d"(vec[3]) 1924 : "0"(function), "c"(count) : "cc"); 1925 #elif defined(__i386__) 1926 asm volatile("pusha \n\t" 1927 "cpuid \n\t" 1928 "mov %%eax, 0(%2) \n\t" 1929 "mov %%ebx, 4(%2) \n\t" 1930 "mov %%ecx, 8(%2) \n\t" 1931 "mov %%edx, 12(%2) \n\t" 1932 "popa" 1933 : : "a"(function), "c"(count), "S"(vec) 1934 : "memory", "cc"); 1935 #else 1936 abort(); 1937 #endif 1938 1939 if (eax) 1940 *eax = vec[0]; 1941 if (ebx) 1942 *ebx = vec[1]; 1943 if (ecx) 1944 *ecx = vec[2]; 1945 if (edx) 1946 *edx = vec[3]; 1947 } 1948 1949 /* CPU class name definitions: */ 1950 1951 /* Return type name for a given CPU model name 1952 * Caller is responsible for freeing the returned string. 1953 */ 1954 static char *x86_cpu_type_name(const char *model_name) 1955 { 1956 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1957 } 1958 1959 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1960 { 1961 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1962 return object_class_by_name(typename); 1963 } 1964 1965 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1966 { 1967 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1968 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1969 return cpu_model_from_type(class_name); 1970 } 1971 1972 typedef struct X86CPUVersionDefinition { 1973 X86CPUVersion version; 1974 const char *alias; 1975 const char *note; 1976 PropValue *props; 1977 const CPUCaches *const cache_info; 1978 } X86CPUVersionDefinition; 1979 1980 /* Base definition for a CPU model */ 1981 typedef struct X86CPUDefinition { 1982 const char *name; 1983 uint32_t level; 1984 uint32_t xlevel; 1985 /* vendor is zero-terminated, 12 character ASCII string */ 1986 char vendor[CPUID_VENDOR_SZ + 1]; 1987 int family; 1988 int model; 1989 int stepping; 1990 FeatureWordArray features; 1991 const char *model_id; 1992 const CPUCaches *const cache_info; 1993 /* 1994 * Definitions for alternative versions of CPU model. 1995 * List is terminated by item with version == 0. 1996 * If NULL, version 1 will be registered automatically. 1997 */ 1998 const X86CPUVersionDefinition *versions; 1999 const char *deprecation_note; 2000 } X86CPUDefinition; 2001 2002 /* Reference to a specific CPU model version */ 2003 struct X86CPUModel { 2004 /* Base CPU definition */ 2005 const X86CPUDefinition *cpudef; 2006 /* CPU model version */ 2007 X86CPUVersion version; 2008 const char *note; 2009 /* 2010 * If true, this is an alias CPU model. 2011 * This matters only for "-cpu help" and query-cpu-definitions 2012 */ 2013 bool is_alias; 2014 }; 2015 2016 /* Get full model name for CPU version */ 2017 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 2018 X86CPUVersion version) 2019 { 2020 assert(version > 0); 2021 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 2022 } 2023 2024 static const X86CPUVersionDefinition * 2025 x86_cpu_def_get_versions(const X86CPUDefinition *def) 2026 { 2027 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 2028 static const X86CPUVersionDefinition default_version_list[] = { 2029 { 1 }, 2030 { /* end of list */ } 2031 }; 2032 2033 return def->versions ?: default_version_list; 2034 } 2035 2036 static const CPUCaches epyc_cache_info = { 2037 .l1d_cache = &(CPUCacheInfo) { 2038 .type = DATA_CACHE, 2039 .level = 1, 2040 .size = 32 * KiB, 2041 .line_size = 64, 2042 .associativity = 8, 2043 .partitions = 1, 2044 .sets = 64, 2045 .lines_per_tag = 1, 2046 .self_init = 1, 2047 .no_invd_sharing = true, 2048 .share_level = CPU_TOPO_LEVEL_CORE, 2049 }, 2050 .l1i_cache = &(CPUCacheInfo) { 2051 .type = INSTRUCTION_CACHE, 2052 .level = 1, 2053 .size = 64 * KiB, 2054 .line_size = 64, 2055 .associativity = 4, 2056 .partitions = 1, 2057 .sets = 256, 2058 .lines_per_tag = 1, 2059 .self_init = 1, 2060 .no_invd_sharing = true, 2061 .share_level = CPU_TOPO_LEVEL_CORE, 2062 }, 2063 .l2_cache = &(CPUCacheInfo) { 2064 .type = UNIFIED_CACHE, 2065 .level = 2, 2066 .size = 512 * KiB, 2067 .line_size = 64, 2068 .associativity = 8, 2069 .partitions = 1, 2070 .sets = 1024, 2071 .lines_per_tag = 1, 2072 .share_level = CPU_TOPO_LEVEL_CORE, 2073 }, 2074 .l3_cache = &(CPUCacheInfo) { 2075 .type = UNIFIED_CACHE, 2076 .level = 3, 2077 .size = 8 * MiB, 2078 .line_size = 64, 2079 .associativity = 16, 2080 .partitions = 1, 2081 .sets = 8192, 2082 .lines_per_tag = 1, 2083 .self_init = true, 2084 .inclusive = true, 2085 .complex_indexing = true, 2086 .share_level = CPU_TOPO_LEVEL_DIE, 2087 }, 2088 }; 2089 2090 static CPUCaches epyc_v4_cache_info = { 2091 .l1d_cache = &(CPUCacheInfo) { 2092 .type = DATA_CACHE, 2093 .level = 1, 2094 .size = 32 * KiB, 2095 .line_size = 64, 2096 .associativity = 8, 2097 .partitions = 1, 2098 .sets = 64, 2099 .lines_per_tag = 1, 2100 .self_init = 1, 2101 .no_invd_sharing = true, 2102 .share_level = CPU_TOPO_LEVEL_CORE, 2103 }, 2104 .l1i_cache = &(CPUCacheInfo) { 2105 .type = INSTRUCTION_CACHE, 2106 .level = 1, 2107 .size = 64 * KiB, 2108 .line_size = 64, 2109 .associativity = 4, 2110 .partitions = 1, 2111 .sets = 256, 2112 .lines_per_tag = 1, 2113 .self_init = 1, 2114 .no_invd_sharing = true, 2115 .share_level = CPU_TOPO_LEVEL_CORE, 2116 }, 2117 .l2_cache = &(CPUCacheInfo) { 2118 .type = UNIFIED_CACHE, 2119 .level = 2, 2120 .size = 512 * KiB, 2121 .line_size = 64, 2122 .associativity = 8, 2123 .partitions = 1, 2124 .sets = 1024, 2125 .lines_per_tag = 1, 2126 .share_level = CPU_TOPO_LEVEL_CORE, 2127 }, 2128 .l3_cache = &(CPUCacheInfo) { 2129 .type = UNIFIED_CACHE, 2130 .level = 3, 2131 .size = 8 * MiB, 2132 .line_size = 64, 2133 .associativity = 16, 2134 .partitions = 1, 2135 .sets = 8192, 2136 .lines_per_tag = 1, 2137 .self_init = true, 2138 .inclusive = true, 2139 .complex_indexing = false, 2140 .share_level = CPU_TOPO_LEVEL_DIE, 2141 }, 2142 }; 2143 2144 static const CPUCaches epyc_rome_cache_info = { 2145 .l1d_cache = &(CPUCacheInfo) { 2146 .type = DATA_CACHE, 2147 .level = 1, 2148 .size = 32 * KiB, 2149 .line_size = 64, 2150 .associativity = 8, 2151 .partitions = 1, 2152 .sets = 64, 2153 .lines_per_tag = 1, 2154 .self_init = 1, 2155 .no_invd_sharing = true, 2156 .share_level = CPU_TOPO_LEVEL_CORE, 2157 }, 2158 .l1i_cache = &(CPUCacheInfo) { 2159 .type = INSTRUCTION_CACHE, 2160 .level = 1, 2161 .size = 32 * KiB, 2162 .line_size = 64, 2163 .associativity = 8, 2164 .partitions = 1, 2165 .sets = 64, 2166 .lines_per_tag = 1, 2167 .self_init = 1, 2168 .no_invd_sharing = true, 2169 .share_level = CPU_TOPO_LEVEL_CORE, 2170 }, 2171 .l2_cache = &(CPUCacheInfo) { 2172 .type = UNIFIED_CACHE, 2173 .level = 2, 2174 .size = 512 * KiB, 2175 .line_size = 64, 2176 .associativity = 8, 2177 .partitions = 1, 2178 .sets = 1024, 2179 .lines_per_tag = 1, 2180 .share_level = CPU_TOPO_LEVEL_CORE, 2181 }, 2182 .l3_cache = &(CPUCacheInfo) { 2183 .type = UNIFIED_CACHE, 2184 .level = 3, 2185 .size = 16 * MiB, 2186 .line_size = 64, 2187 .associativity = 16, 2188 .partitions = 1, 2189 .sets = 16384, 2190 .lines_per_tag = 1, 2191 .self_init = true, 2192 .inclusive = true, 2193 .complex_indexing = true, 2194 .share_level = CPU_TOPO_LEVEL_DIE, 2195 }, 2196 }; 2197 2198 static const CPUCaches epyc_rome_v3_cache_info = { 2199 .l1d_cache = &(CPUCacheInfo) { 2200 .type = DATA_CACHE, 2201 .level = 1, 2202 .size = 32 * KiB, 2203 .line_size = 64, 2204 .associativity = 8, 2205 .partitions = 1, 2206 .sets = 64, 2207 .lines_per_tag = 1, 2208 .self_init = 1, 2209 .no_invd_sharing = true, 2210 .share_level = CPU_TOPO_LEVEL_CORE, 2211 }, 2212 .l1i_cache = &(CPUCacheInfo) { 2213 .type = INSTRUCTION_CACHE, 2214 .level = 1, 2215 .size = 32 * KiB, 2216 .line_size = 64, 2217 .associativity = 8, 2218 .partitions = 1, 2219 .sets = 64, 2220 .lines_per_tag = 1, 2221 .self_init = 1, 2222 .no_invd_sharing = true, 2223 .share_level = CPU_TOPO_LEVEL_CORE, 2224 }, 2225 .l2_cache = &(CPUCacheInfo) { 2226 .type = UNIFIED_CACHE, 2227 .level = 2, 2228 .size = 512 * KiB, 2229 .line_size = 64, 2230 .associativity = 8, 2231 .partitions = 1, 2232 .sets = 1024, 2233 .lines_per_tag = 1, 2234 .share_level = CPU_TOPO_LEVEL_CORE, 2235 }, 2236 .l3_cache = &(CPUCacheInfo) { 2237 .type = UNIFIED_CACHE, 2238 .level = 3, 2239 .size = 16 * MiB, 2240 .line_size = 64, 2241 .associativity = 16, 2242 .partitions = 1, 2243 .sets = 16384, 2244 .lines_per_tag = 1, 2245 .self_init = true, 2246 .inclusive = true, 2247 .complex_indexing = false, 2248 .share_level = CPU_TOPO_LEVEL_DIE, 2249 }, 2250 }; 2251 2252 static const CPUCaches epyc_milan_cache_info = { 2253 .l1d_cache = &(CPUCacheInfo) { 2254 .type = DATA_CACHE, 2255 .level = 1, 2256 .size = 32 * KiB, 2257 .line_size = 64, 2258 .associativity = 8, 2259 .partitions = 1, 2260 .sets = 64, 2261 .lines_per_tag = 1, 2262 .self_init = 1, 2263 .no_invd_sharing = true, 2264 .share_level = CPU_TOPO_LEVEL_CORE, 2265 }, 2266 .l1i_cache = &(CPUCacheInfo) { 2267 .type = INSTRUCTION_CACHE, 2268 .level = 1, 2269 .size = 32 * KiB, 2270 .line_size = 64, 2271 .associativity = 8, 2272 .partitions = 1, 2273 .sets = 64, 2274 .lines_per_tag = 1, 2275 .self_init = 1, 2276 .no_invd_sharing = true, 2277 .share_level = CPU_TOPO_LEVEL_CORE, 2278 }, 2279 .l2_cache = &(CPUCacheInfo) { 2280 .type = UNIFIED_CACHE, 2281 .level = 2, 2282 .size = 512 * KiB, 2283 .line_size = 64, 2284 .associativity = 8, 2285 .partitions = 1, 2286 .sets = 1024, 2287 .lines_per_tag = 1, 2288 .share_level = CPU_TOPO_LEVEL_CORE, 2289 }, 2290 .l3_cache = &(CPUCacheInfo) { 2291 .type = UNIFIED_CACHE, 2292 .level = 3, 2293 .size = 32 * MiB, 2294 .line_size = 64, 2295 .associativity = 16, 2296 .partitions = 1, 2297 .sets = 32768, 2298 .lines_per_tag = 1, 2299 .self_init = true, 2300 .inclusive = true, 2301 .complex_indexing = true, 2302 .share_level = CPU_TOPO_LEVEL_DIE, 2303 }, 2304 }; 2305 2306 static const CPUCaches epyc_milan_v2_cache_info = { 2307 .l1d_cache = &(CPUCacheInfo) { 2308 .type = DATA_CACHE, 2309 .level = 1, 2310 .size = 32 * KiB, 2311 .line_size = 64, 2312 .associativity = 8, 2313 .partitions = 1, 2314 .sets = 64, 2315 .lines_per_tag = 1, 2316 .self_init = 1, 2317 .no_invd_sharing = true, 2318 .share_level = CPU_TOPO_LEVEL_CORE, 2319 }, 2320 .l1i_cache = &(CPUCacheInfo) { 2321 .type = INSTRUCTION_CACHE, 2322 .level = 1, 2323 .size = 32 * KiB, 2324 .line_size = 64, 2325 .associativity = 8, 2326 .partitions = 1, 2327 .sets = 64, 2328 .lines_per_tag = 1, 2329 .self_init = 1, 2330 .no_invd_sharing = true, 2331 .share_level = CPU_TOPO_LEVEL_CORE, 2332 }, 2333 .l2_cache = &(CPUCacheInfo) { 2334 .type = UNIFIED_CACHE, 2335 .level = 2, 2336 .size = 512 * KiB, 2337 .line_size = 64, 2338 .associativity = 8, 2339 .partitions = 1, 2340 .sets = 1024, 2341 .lines_per_tag = 1, 2342 .share_level = CPU_TOPO_LEVEL_CORE, 2343 }, 2344 .l3_cache = &(CPUCacheInfo) { 2345 .type = UNIFIED_CACHE, 2346 .level = 3, 2347 .size = 32 * MiB, 2348 .line_size = 64, 2349 .associativity = 16, 2350 .partitions = 1, 2351 .sets = 32768, 2352 .lines_per_tag = 1, 2353 .self_init = true, 2354 .inclusive = true, 2355 .complex_indexing = false, 2356 .share_level = CPU_TOPO_LEVEL_DIE, 2357 }, 2358 }; 2359 2360 static const CPUCaches epyc_genoa_cache_info = { 2361 .l1d_cache = &(CPUCacheInfo) { 2362 .type = DATA_CACHE, 2363 .level = 1, 2364 .size = 32 * KiB, 2365 .line_size = 64, 2366 .associativity = 8, 2367 .partitions = 1, 2368 .sets = 64, 2369 .lines_per_tag = 1, 2370 .self_init = 1, 2371 .no_invd_sharing = true, 2372 .share_level = CPU_TOPO_LEVEL_CORE, 2373 }, 2374 .l1i_cache = &(CPUCacheInfo) { 2375 .type = INSTRUCTION_CACHE, 2376 .level = 1, 2377 .size = 32 * KiB, 2378 .line_size = 64, 2379 .associativity = 8, 2380 .partitions = 1, 2381 .sets = 64, 2382 .lines_per_tag = 1, 2383 .self_init = 1, 2384 .no_invd_sharing = true, 2385 .share_level = CPU_TOPO_LEVEL_CORE, 2386 }, 2387 .l2_cache = &(CPUCacheInfo) { 2388 .type = UNIFIED_CACHE, 2389 .level = 2, 2390 .size = 1 * MiB, 2391 .line_size = 64, 2392 .associativity = 8, 2393 .partitions = 1, 2394 .sets = 2048, 2395 .lines_per_tag = 1, 2396 .share_level = CPU_TOPO_LEVEL_CORE, 2397 }, 2398 .l3_cache = &(CPUCacheInfo) { 2399 .type = UNIFIED_CACHE, 2400 .level = 3, 2401 .size = 32 * MiB, 2402 .line_size = 64, 2403 .associativity = 16, 2404 .partitions = 1, 2405 .sets = 32768, 2406 .lines_per_tag = 1, 2407 .self_init = true, 2408 .inclusive = true, 2409 .complex_indexing = false, 2410 .share_level = CPU_TOPO_LEVEL_DIE, 2411 }, 2412 }; 2413 2414 /* The following VMX features are not supported by KVM and are left out in the 2415 * CPU definitions: 2416 * 2417 * Dual-monitor support (all processors) 2418 * Entry to SMM 2419 * Deactivate dual-monitor treatment 2420 * Number of CR3-target values 2421 * Shutdown activity state 2422 * Wait-for-SIPI activity state 2423 * PAUSE-loop exiting (Westmere and newer) 2424 * EPT-violation #VE (Broadwell and newer) 2425 * Inject event with insn length=0 (Skylake and newer) 2426 * Conceal non-root operation from PT 2427 * Conceal VM exits from PT 2428 * Conceal VM entries from PT 2429 * Enable ENCLS exiting 2430 * Mode-based execute control (XS/XU) 2431 * TSC scaling (Skylake Server and newer) 2432 * GPA translation for PT (IceLake and newer) 2433 * User wait and pause 2434 * ENCLV exiting 2435 * Load IA32_RTIT_CTL 2436 * Clear IA32_RTIT_CTL 2437 * Advanced VM-exit information for EPT violations 2438 * Sub-page write permissions 2439 * PT in VMX operation 2440 */ 2441 2442 static const X86CPUDefinition builtin_x86_defs[] = { 2443 { 2444 .name = "qemu64", 2445 .level = 0xd, 2446 .vendor = CPUID_VENDOR_AMD, 2447 .family = 15, 2448 .model = 107, 2449 .stepping = 1, 2450 .features[FEAT_1_EDX] = 2451 PPRO_FEATURES | 2452 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2453 CPUID_PSE36, 2454 .features[FEAT_1_ECX] = 2455 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2456 .features[FEAT_8000_0001_EDX] = 2457 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2458 .features[FEAT_8000_0001_ECX] = 2459 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2460 .xlevel = 0x8000000A, 2461 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2462 }, 2463 { 2464 .name = "phenom", 2465 .level = 5, 2466 .vendor = CPUID_VENDOR_AMD, 2467 .family = 16, 2468 .model = 2, 2469 .stepping = 3, 2470 /* Missing: CPUID_HT */ 2471 .features[FEAT_1_EDX] = 2472 PPRO_FEATURES | 2473 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2474 CPUID_PSE36 | CPUID_VME, 2475 .features[FEAT_1_ECX] = 2476 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2477 CPUID_EXT_POPCNT, 2478 .features[FEAT_8000_0001_EDX] = 2479 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2480 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2481 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2482 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2483 CPUID_EXT3_CR8LEG, 2484 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2485 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2486 .features[FEAT_8000_0001_ECX] = 2487 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2488 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2489 /* Missing: CPUID_SVM_LBRV */ 2490 .features[FEAT_SVM] = 2491 CPUID_SVM_NPT, 2492 .xlevel = 0x8000001A, 2493 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2494 }, 2495 { 2496 .name = "core2duo", 2497 .level = 10, 2498 .vendor = CPUID_VENDOR_INTEL, 2499 .family = 6, 2500 .model = 15, 2501 .stepping = 11, 2502 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2503 .features[FEAT_1_EDX] = 2504 PPRO_FEATURES | 2505 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2506 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2507 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2508 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2509 .features[FEAT_1_ECX] = 2510 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2511 CPUID_EXT_CX16, 2512 .features[FEAT_8000_0001_EDX] = 2513 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2514 .features[FEAT_8000_0001_ECX] = 2515 CPUID_EXT3_LAHF_LM, 2516 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2517 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2518 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2519 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2520 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2521 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2522 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2523 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2524 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2525 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2526 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2527 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2528 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2529 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2530 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2531 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2532 .features[FEAT_VMX_SECONDARY_CTLS] = 2533 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2534 .xlevel = 0x80000008, 2535 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2536 }, 2537 { 2538 .name = "kvm64", 2539 .level = 0xd, 2540 .vendor = CPUID_VENDOR_INTEL, 2541 .family = 15, 2542 .model = 6, 2543 .stepping = 1, 2544 /* Missing: CPUID_HT */ 2545 .features[FEAT_1_EDX] = 2546 PPRO_FEATURES | CPUID_VME | 2547 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2548 CPUID_PSE36, 2549 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2550 .features[FEAT_1_ECX] = 2551 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2552 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2553 .features[FEAT_8000_0001_EDX] = 2554 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2555 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2556 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2557 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2558 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2559 .features[FEAT_8000_0001_ECX] = 2560 0, 2561 /* VMX features from Cedar Mill/Prescott */ 2562 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2563 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2564 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2565 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2566 VMX_PIN_BASED_NMI_EXITING, 2567 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2568 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2569 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2570 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2571 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2572 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2573 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2574 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2575 .xlevel = 0x80000008, 2576 .model_id = "Common KVM processor" 2577 }, 2578 { 2579 .name = "qemu32", 2580 .level = 4, 2581 .vendor = CPUID_VENDOR_INTEL, 2582 .family = 6, 2583 .model = 6, 2584 .stepping = 3, 2585 .features[FEAT_1_EDX] = 2586 PPRO_FEATURES, 2587 .features[FEAT_1_ECX] = 2588 CPUID_EXT_SSE3, 2589 .xlevel = 0x80000004, 2590 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2591 }, 2592 { 2593 .name = "kvm32", 2594 .level = 5, 2595 .vendor = CPUID_VENDOR_INTEL, 2596 .family = 15, 2597 .model = 6, 2598 .stepping = 1, 2599 .features[FEAT_1_EDX] = 2600 PPRO_FEATURES | CPUID_VME | 2601 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2602 .features[FEAT_1_ECX] = 2603 CPUID_EXT_SSE3, 2604 .features[FEAT_8000_0001_ECX] = 2605 0, 2606 /* VMX features from Yonah */ 2607 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2608 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2609 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2610 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2611 VMX_PIN_BASED_NMI_EXITING, 2612 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2613 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2614 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2615 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2616 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2617 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2618 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2619 .xlevel = 0x80000008, 2620 .model_id = "Common 32-bit KVM processor" 2621 }, 2622 { 2623 .name = "coreduo", 2624 .level = 10, 2625 .vendor = CPUID_VENDOR_INTEL, 2626 .family = 6, 2627 .model = 14, 2628 .stepping = 8, 2629 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2630 .features[FEAT_1_EDX] = 2631 PPRO_FEATURES | CPUID_VME | 2632 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2633 CPUID_SS, 2634 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2635 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2636 .features[FEAT_1_ECX] = 2637 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2638 .features[FEAT_8000_0001_EDX] = 2639 CPUID_EXT2_NX, 2640 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2641 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2642 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2643 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2644 VMX_PIN_BASED_NMI_EXITING, 2645 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2646 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2647 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2648 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2649 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2650 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2651 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2652 .xlevel = 0x80000008, 2653 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2654 }, 2655 { 2656 .name = "486", 2657 .level = 1, 2658 .vendor = CPUID_VENDOR_INTEL, 2659 .family = 4, 2660 .model = 8, 2661 .stepping = 0, 2662 .features[FEAT_1_EDX] = 2663 I486_FEATURES, 2664 .xlevel = 0, 2665 .model_id = "", 2666 }, 2667 { 2668 .name = "pentium", 2669 .level = 1, 2670 .vendor = CPUID_VENDOR_INTEL, 2671 .family = 5, 2672 .model = 4, 2673 .stepping = 3, 2674 .features[FEAT_1_EDX] = 2675 PENTIUM_FEATURES, 2676 .xlevel = 0, 2677 .model_id = "", 2678 }, 2679 { 2680 .name = "pentium2", 2681 .level = 2, 2682 .vendor = CPUID_VENDOR_INTEL, 2683 .family = 6, 2684 .model = 5, 2685 .stepping = 2, 2686 .features[FEAT_1_EDX] = 2687 PENTIUM2_FEATURES, 2688 .xlevel = 0, 2689 .model_id = "", 2690 }, 2691 { 2692 .name = "pentium3", 2693 .level = 3, 2694 .vendor = CPUID_VENDOR_INTEL, 2695 .family = 6, 2696 .model = 7, 2697 .stepping = 3, 2698 .features[FEAT_1_EDX] = 2699 PENTIUM3_FEATURES, 2700 .xlevel = 0, 2701 .model_id = "", 2702 }, 2703 { 2704 .name = "athlon", 2705 .level = 2, 2706 .vendor = CPUID_VENDOR_AMD, 2707 .family = 6, 2708 .model = 2, 2709 .stepping = 3, 2710 .features[FEAT_1_EDX] = 2711 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2712 CPUID_MCA, 2713 .features[FEAT_8000_0001_EDX] = 2714 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2715 .xlevel = 0x80000008, 2716 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2717 }, 2718 { 2719 .name = "n270", 2720 .level = 10, 2721 .vendor = CPUID_VENDOR_INTEL, 2722 .family = 6, 2723 .model = 28, 2724 .stepping = 2, 2725 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2726 .features[FEAT_1_EDX] = 2727 PPRO_FEATURES | 2728 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2729 CPUID_ACPI | CPUID_SS, 2730 /* Some CPUs got no CPUID_SEP */ 2731 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2732 * CPUID_EXT_XTPR */ 2733 .features[FEAT_1_ECX] = 2734 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2735 CPUID_EXT_MOVBE, 2736 .features[FEAT_8000_0001_EDX] = 2737 CPUID_EXT2_NX, 2738 .features[FEAT_8000_0001_ECX] = 2739 CPUID_EXT3_LAHF_LM, 2740 .xlevel = 0x80000008, 2741 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2742 }, 2743 { 2744 .name = "Conroe", 2745 .level = 10, 2746 .vendor = CPUID_VENDOR_INTEL, 2747 .family = 6, 2748 .model = 15, 2749 .stepping = 3, 2750 .features[FEAT_1_EDX] = 2751 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2752 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2753 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2754 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2755 CPUID_DE | CPUID_FP87, 2756 .features[FEAT_1_ECX] = 2757 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2758 .features[FEAT_8000_0001_EDX] = 2759 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2760 .features[FEAT_8000_0001_ECX] = 2761 CPUID_EXT3_LAHF_LM, 2762 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2763 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2764 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2765 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2766 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2767 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2768 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2769 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2770 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2771 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2772 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2773 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2774 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2775 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2776 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2777 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2778 .features[FEAT_VMX_SECONDARY_CTLS] = 2779 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2780 .xlevel = 0x80000008, 2781 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2782 }, 2783 { 2784 .name = "Penryn", 2785 .level = 10, 2786 .vendor = CPUID_VENDOR_INTEL, 2787 .family = 6, 2788 .model = 23, 2789 .stepping = 3, 2790 .features[FEAT_1_EDX] = 2791 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2792 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2793 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2794 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2795 CPUID_DE | CPUID_FP87, 2796 .features[FEAT_1_ECX] = 2797 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2798 CPUID_EXT_SSE3, 2799 .features[FEAT_8000_0001_EDX] = 2800 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2801 .features[FEAT_8000_0001_ECX] = 2802 CPUID_EXT3_LAHF_LM, 2803 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2804 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2805 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2806 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2807 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2808 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2809 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2810 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2811 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2812 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2813 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2814 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2815 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2816 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2817 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2818 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2819 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2820 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2821 .features[FEAT_VMX_SECONDARY_CTLS] = 2822 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2823 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2824 .xlevel = 0x80000008, 2825 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2826 }, 2827 { 2828 .name = "Nehalem", 2829 .level = 11, 2830 .vendor = CPUID_VENDOR_INTEL, 2831 .family = 6, 2832 .model = 26, 2833 .stepping = 3, 2834 .features[FEAT_1_EDX] = 2835 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2836 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2837 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2838 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2839 CPUID_DE | CPUID_FP87, 2840 .features[FEAT_1_ECX] = 2841 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2842 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2843 .features[FEAT_8000_0001_EDX] = 2844 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2845 .features[FEAT_8000_0001_ECX] = 2846 CPUID_EXT3_LAHF_LM, 2847 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2848 MSR_VMX_BASIC_TRUE_CTLS, 2849 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2850 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2851 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2852 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2853 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2854 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2855 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2856 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2857 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2858 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2859 .features[FEAT_VMX_EXIT_CTLS] = 2860 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2861 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2862 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2863 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2864 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2865 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2866 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2867 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2868 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2869 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2870 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2871 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2872 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2873 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2874 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2875 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2876 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2877 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2878 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2879 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2880 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2881 .features[FEAT_VMX_SECONDARY_CTLS] = 2882 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2883 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2884 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2885 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2886 VMX_SECONDARY_EXEC_ENABLE_VPID, 2887 .xlevel = 0x80000008, 2888 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2889 .versions = (X86CPUVersionDefinition[]) { 2890 { .version = 1 }, 2891 { 2892 .version = 2, 2893 .alias = "Nehalem-IBRS", 2894 .props = (PropValue[]) { 2895 { "spec-ctrl", "on" }, 2896 { "model-id", 2897 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2898 { /* end of list */ } 2899 } 2900 }, 2901 { /* end of list */ } 2902 } 2903 }, 2904 { 2905 .name = "Westmere", 2906 .level = 11, 2907 .vendor = CPUID_VENDOR_INTEL, 2908 .family = 6, 2909 .model = 44, 2910 .stepping = 1, 2911 .features[FEAT_1_EDX] = 2912 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2913 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2914 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2915 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2916 CPUID_DE | CPUID_FP87, 2917 .features[FEAT_1_ECX] = 2918 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2919 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2920 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2921 .features[FEAT_8000_0001_EDX] = 2922 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2923 .features[FEAT_8000_0001_ECX] = 2924 CPUID_EXT3_LAHF_LM, 2925 .features[FEAT_6_EAX] = 2926 CPUID_6_EAX_ARAT, 2927 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2928 MSR_VMX_BASIC_TRUE_CTLS, 2929 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2930 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2931 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2932 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2933 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2934 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2935 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2936 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2937 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2938 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2939 .features[FEAT_VMX_EXIT_CTLS] = 2940 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2941 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2942 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2943 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2944 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2945 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2946 MSR_VMX_MISC_STORE_LMA, 2947 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2948 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2949 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2950 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2951 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2952 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2953 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2954 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2955 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2956 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2957 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2958 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2959 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2960 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2961 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2962 .features[FEAT_VMX_SECONDARY_CTLS] = 2963 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2964 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2965 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2966 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2967 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2968 .xlevel = 0x80000008, 2969 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2970 .versions = (X86CPUVersionDefinition[]) { 2971 { .version = 1 }, 2972 { 2973 .version = 2, 2974 .alias = "Westmere-IBRS", 2975 .props = (PropValue[]) { 2976 { "spec-ctrl", "on" }, 2977 { "model-id", 2978 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2979 { /* end of list */ } 2980 } 2981 }, 2982 { /* end of list */ } 2983 } 2984 }, 2985 { 2986 .name = "SandyBridge", 2987 .level = 0xd, 2988 .vendor = CPUID_VENDOR_INTEL, 2989 .family = 6, 2990 .model = 42, 2991 .stepping = 1, 2992 .features[FEAT_1_EDX] = 2993 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2994 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2995 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2996 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2997 CPUID_DE | CPUID_FP87, 2998 .features[FEAT_1_ECX] = 2999 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3000 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3001 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3002 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3003 CPUID_EXT_SSE3, 3004 .features[FEAT_8000_0001_EDX] = 3005 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3006 CPUID_EXT2_SYSCALL, 3007 .features[FEAT_8000_0001_ECX] = 3008 CPUID_EXT3_LAHF_LM, 3009 .features[FEAT_XSAVE] = 3010 CPUID_XSAVE_XSAVEOPT, 3011 .features[FEAT_6_EAX] = 3012 CPUID_6_EAX_ARAT, 3013 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3014 MSR_VMX_BASIC_TRUE_CTLS, 3015 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3016 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3017 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3018 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3019 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3020 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3021 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3022 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3023 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3024 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3025 .features[FEAT_VMX_EXIT_CTLS] = 3026 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3027 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3028 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3029 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3030 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3031 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3032 MSR_VMX_MISC_STORE_LMA, 3033 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3034 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3035 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3036 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3037 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3038 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3039 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3040 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3041 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3042 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3043 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3044 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3045 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3046 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3047 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3048 .features[FEAT_VMX_SECONDARY_CTLS] = 3049 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3050 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3051 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3052 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3053 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3054 .xlevel = 0x80000008, 3055 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 3056 .versions = (X86CPUVersionDefinition[]) { 3057 { .version = 1 }, 3058 { 3059 .version = 2, 3060 .alias = "SandyBridge-IBRS", 3061 .props = (PropValue[]) { 3062 { "spec-ctrl", "on" }, 3063 { "model-id", 3064 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3065 { /* end of list */ } 3066 } 3067 }, 3068 { /* end of list */ } 3069 } 3070 }, 3071 { 3072 .name = "IvyBridge", 3073 .level = 0xd, 3074 .vendor = CPUID_VENDOR_INTEL, 3075 .family = 6, 3076 .model = 58, 3077 .stepping = 9, 3078 .features[FEAT_1_EDX] = 3079 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3080 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3081 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3082 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3083 CPUID_DE | CPUID_FP87, 3084 .features[FEAT_1_ECX] = 3085 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3086 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3087 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3088 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3089 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3090 .features[FEAT_7_0_EBX] = 3091 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3092 CPUID_7_0_EBX_ERMS, 3093 .features[FEAT_8000_0001_EDX] = 3094 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3095 CPUID_EXT2_SYSCALL, 3096 .features[FEAT_8000_0001_ECX] = 3097 CPUID_EXT3_LAHF_LM, 3098 .features[FEAT_XSAVE] = 3099 CPUID_XSAVE_XSAVEOPT, 3100 .features[FEAT_6_EAX] = 3101 CPUID_6_EAX_ARAT, 3102 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3103 MSR_VMX_BASIC_TRUE_CTLS, 3104 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3105 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3106 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3107 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3108 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3109 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3110 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3111 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3112 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3113 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3114 .features[FEAT_VMX_EXIT_CTLS] = 3115 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3116 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3117 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3118 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3119 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3120 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3121 MSR_VMX_MISC_STORE_LMA, 3122 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3123 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3124 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3125 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3126 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3127 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3128 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3129 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3130 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3131 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3132 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3133 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3134 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3135 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3136 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3137 .features[FEAT_VMX_SECONDARY_CTLS] = 3138 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3139 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3140 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3141 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3142 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3143 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3144 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3145 VMX_SECONDARY_EXEC_RDRAND_EXITING, 3146 .xlevel = 0x80000008, 3147 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 3148 .versions = (X86CPUVersionDefinition[]) { 3149 { .version = 1 }, 3150 { 3151 .version = 2, 3152 .alias = "IvyBridge-IBRS", 3153 .props = (PropValue[]) { 3154 { "spec-ctrl", "on" }, 3155 { "model-id", 3156 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 3157 { /* end of list */ } 3158 } 3159 }, 3160 { /* end of list */ } 3161 } 3162 }, 3163 { 3164 .name = "Haswell", 3165 .level = 0xd, 3166 .vendor = CPUID_VENDOR_INTEL, 3167 .family = 6, 3168 .model = 60, 3169 .stepping = 4, 3170 .features[FEAT_1_EDX] = 3171 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3172 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3173 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3174 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3175 CPUID_DE | CPUID_FP87, 3176 .features[FEAT_1_ECX] = 3177 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3178 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3179 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3180 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3181 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3182 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3183 .features[FEAT_8000_0001_EDX] = 3184 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3185 CPUID_EXT2_SYSCALL, 3186 .features[FEAT_8000_0001_ECX] = 3187 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 3188 .features[FEAT_7_0_EBX] = 3189 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3190 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3191 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3192 CPUID_7_0_EBX_RTM, 3193 .features[FEAT_XSAVE] = 3194 CPUID_XSAVE_XSAVEOPT, 3195 .features[FEAT_6_EAX] = 3196 CPUID_6_EAX_ARAT, 3197 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3198 MSR_VMX_BASIC_TRUE_CTLS, 3199 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3200 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3201 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3202 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3203 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3204 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3205 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3206 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3207 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3208 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3209 .features[FEAT_VMX_EXIT_CTLS] = 3210 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3211 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3212 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3213 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3214 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3215 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3216 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3217 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3218 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3219 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3220 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3221 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3222 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3223 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3224 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3225 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3226 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3227 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3228 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3229 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3230 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3231 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3232 .features[FEAT_VMX_SECONDARY_CTLS] = 3233 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3234 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3235 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3236 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3237 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3238 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3239 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3240 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3241 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3242 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3243 .xlevel = 0x80000008, 3244 .model_id = "Intel Core Processor (Haswell)", 3245 .versions = (X86CPUVersionDefinition[]) { 3246 { .version = 1 }, 3247 { 3248 .version = 2, 3249 .alias = "Haswell-noTSX", 3250 .props = (PropValue[]) { 3251 { "hle", "off" }, 3252 { "rtm", "off" }, 3253 { "stepping", "1" }, 3254 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3255 { /* end of list */ } 3256 }, 3257 }, 3258 { 3259 .version = 3, 3260 .alias = "Haswell-IBRS", 3261 .props = (PropValue[]) { 3262 /* Restore TSX features removed by -v2 above */ 3263 { "hle", "on" }, 3264 { "rtm", "on" }, 3265 /* 3266 * Haswell and Haswell-IBRS had stepping=4 in 3267 * QEMU 4.0 and older 3268 */ 3269 { "stepping", "4" }, 3270 { "spec-ctrl", "on" }, 3271 { "model-id", 3272 "Intel Core Processor (Haswell, IBRS)" }, 3273 { /* end of list */ } 3274 } 3275 }, 3276 { 3277 .version = 4, 3278 .alias = "Haswell-noTSX-IBRS", 3279 .props = (PropValue[]) { 3280 { "hle", "off" }, 3281 { "rtm", "off" }, 3282 /* spec-ctrl was already enabled by -v3 above */ 3283 { "stepping", "1" }, 3284 { "model-id", 3285 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3286 { /* end of list */ } 3287 } 3288 }, 3289 { /* end of list */ } 3290 } 3291 }, 3292 { 3293 .name = "Broadwell", 3294 .level = 0xd, 3295 .vendor = CPUID_VENDOR_INTEL, 3296 .family = 6, 3297 .model = 61, 3298 .stepping = 2, 3299 .features[FEAT_1_EDX] = 3300 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3301 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3302 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3303 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3304 CPUID_DE | CPUID_FP87, 3305 .features[FEAT_1_ECX] = 3306 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3307 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3308 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3309 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3310 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3311 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3312 .features[FEAT_8000_0001_EDX] = 3313 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3314 CPUID_EXT2_SYSCALL, 3315 .features[FEAT_8000_0001_ECX] = 3316 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3317 .features[FEAT_7_0_EBX] = 3318 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3319 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3320 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3321 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3322 CPUID_7_0_EBX_SMAP, 3323 .features[FEAT_XSAVE] = 3324 CPUID_XSAVE_XSAVEOPT, 3325 .features[FEAT_6_EAX] = 3326 CPUID_6_EAX_ARAT, 3327 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3328 MSR_VMX_BASIC_TRUE_CTLS, 3329 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3330 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3331 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3332 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3333 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3334 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3335 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3336 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3337 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3338 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3339 .features[FEAT_VMX_EXIT_CTLS] = 3340 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3341 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3342 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3343 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3344 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3345 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3346 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3347 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3348 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3349 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3350 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3351 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3352 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3353 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3354 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3355 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3356 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3357 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3358 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3359 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3360 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3361 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3362 .features[FEAT_VMX_SECONDARY_CTLS] = 3363 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3364 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3365 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3366 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3367 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3368 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3369 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3370 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3371 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3372 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3373 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3374 .xlevel = 0x80000008, 3375 .model_id = "Intel Core Processor (Broadwell)", 3376 .versions = (X86CPUVersionDefinition[]) { 3377 { .version = 1 }, 3378 { 3379 .version = 2, 3380 .alias = "Broadwell-noTSX", 3381 .props = (PropValue[]) { 3382 { "hle", "off" }, 3383 { "rtm", "off" }, 3384 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3385 { /* end of list */ } 3386 }, 3387 }, 3388 { 3389 .version = 3, 3390 .alias = "Broadwell-IBRS", 3391 .props = (PropValue[]) { 3392 /* Restore TSX features removed by -v2 above */ 3393 { "hle", "on" }, 3394 { "rtm", "on" }, 3395 { "spec-ctrl", "on" }, 3396 { "model-id", 3397 "Intel Core Processor (Broadwell, IBRS)" }, 3398 { /* end of list */ } 3399 } 3400 }, 3401 { 3402 .version = 4, 3403 .alias = "Broadwell-noTSX-IBRS", 3404 .props = (PropValue[]) { 3405 { "hle", "off" }, 3406 { "rtm", "off" }, 3407 /* spec-ctrl was already enabled by -v3 above */ 3408 { "model-id", 3409 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3410 { /* end of list */ } 3411 } 3412 }, 3413 { /* end of list */ } 3414 } 3415 }, 3416 { 3417 .name = "Skylake-Client", 3418 .level = 0xd, 3419 .vendor = CPUID_VENDOR_INTEL, 3420 .family = 6, 3421 .model = 94, 3422 .stepping = 3, 3423 .features[FEAT_1_EDX] = 3424 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3425 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3426 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3427 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3428 CPUID_DE | CPUID_FP87, 3429 .features[FEAT_1_ECX] = 3430 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3431 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3432 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3433 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3434 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3435 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3436 .features[FEAT_8000_0001_EDX] = 3437 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3438 CPUID_EXT2_SYSCALL, 3439 .features[FEAT_8000_0001_ECX] = 3440 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3441 .features[FEAT_7_0_EBX] = 3442 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3443 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3444 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3445 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3446 CPUID_7_0_EBX_SMAP, 3447 /* XSAVES is added in version 4 */ 3448 .features[FEAT_XSAVE] = 3449 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3450 CPUID_XSAVE_XGETBV1, 3451 .features[FEAT_6_EAX] = 3452 CPUID_6_EAX_ARAT, 3453 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3454 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3455 MSR_VMX_BASIC_TRUE_CTLS, 3456 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3457 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3458 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3459 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3460 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3461 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3462 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3463 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3464 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3465 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3466 .features[FEAT_VMX_EXIT_CTLS] = 3467 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3468 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3469 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3470 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3471 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3472 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3473 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3474 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3475 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3476 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3477 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3478 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3479 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3480 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3481 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3482 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3483 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3484 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3485 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3486 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3487 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3488 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3489 .features[FEAT_VMX_SECONDARY_CTLS] = 3490 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3491 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3492 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3493 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3494 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3495 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3496 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3497 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3498 .xlevel = 0x80000008, 3499 .model_id = "Intel Core Processor (Skylake)", 3500 .versions = (X86CPUVersionDefinition[]) { 3501 { .version = 1 }, 3502 { 3503 .version = 2, 3504 .alias = "Skylake-Client-IBRS", 3505 .props = (PropValue[]) { 3506 { "spec-ctrl", "on" }, 3507 { "model-id", 3508 "Intel Core Processor (Skylake, IBRS)" }, 3509 { /* end of list */ } 3510 } 3511 }, 3512 { 3513 .version = 3, 3514 .alias = "Skylake-Client-noTSX-IBRS", 3515 .props = (PropValue[]) { 3516 { "hle", "off" }, 3517 { "rtm", "off" }, 3518 { "model-id", 3519 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3520 { /* end of list */ } 3521 } 3522 }, 3523 { 3524 .version = 4, 3525 .note = "IBRS, XSAVES, no TSX", 3526 .props = (PropValue[]) { 3527 { "xsaves", "on" }, 3528 { "vmx-xsaves", "on" }, 3529 { /* end of list */ } 3530 } 3531 }, 3532 { /* end of list */ } 3533 } 3534 }, 3535 { 3536 .name = "Skylake-Server", 3537 .level = 0xd, 3538 .vendor = CPUID_VENDOR_INTEL, 3539 .family = 6, 3540 .model = 85, 3541 .stepping = 4, 3542 .features[FEAT_1_EDX] = 3543 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3544 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3545 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3546 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3547 CPUID_DE | CPUID_FP87, 3548 .features[FEAT_1_ECX] = 3549 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3550 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3551 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3552 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3553 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3554 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3555 .features[FEAT_8000_0001_EDX] = 3556 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3557 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3558 .features[FEAT_8000_0001_ECX] = 3559 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3560 .features[FEAT_7_0_EBX] = 3561 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3562 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3563 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3564 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3565 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3566 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3567 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3568 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3569 .features[FEAT_7_0_ECX] = 3570 CPUID_7_0_ECX_PKU, 3571 /* XSAVES is added in version 5 */ 3572 .features[FEAT_XSAVE] = 3573 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3574 CPUID_XSAVE_XGETBV1, 3575 .features[FEAT_6_EAX] = 3576 CPUID_6_EAX_ARAT, 3577 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3578 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3579 MSR_VMX_BASIC_TRUE_CTLS, 3580 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3581 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3582 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3583 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3584 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3585 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3586 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3587 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3588 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3589 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3590 .features[FEAT_VMX_EXIT_CTLS] = 3591 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3592 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3593 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3594 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3595 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3596 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3597 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3598 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3599 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3600 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3601 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3602 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3603 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3604 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3605 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3606 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3607 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3608 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3609 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3610 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3611 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3612 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3613 .features[FEAT_VMX_SECONDARY_CTLS] = 3614 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3615 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3616 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3617 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3618 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3619 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3620 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3621 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3622 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3623 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3624 .xlevel = 0x80000008, 3625 .model_id = "Intel Xeon Processor (Skylake)", 3626 .versions = (X86CPUVersionDefinition[]) { 3627 { .version = 1 }, 3628 { 3629 .version = 2, 3630 .alias = "Skylake-Server-IBRS", 3631 .props = (PropValue[]) { 3632 /* clflushopt was not added to Skylake-Server-IBRS */ 3633 /* TODO: add -v3 including clflushopt */ 3634 { "clflushopt", "off" }, 3635 { "spec-ctrl", "on" }, 3636 { "model-id", 3637 "Intel Xeon Processor (Skylake, IBRS)" }, 3638 { /* end of list */ } 3639 } 3640 }, 3641 { 3642 .version = 3, 3643 .alias = "Skylake-Server-noTSX-IBRS", 3644 .props = (PropValue[]) { 3645 { "hle", "off" }, 3646 { "rtm", "off" }, 3647 { "model-id", 3648 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3649 { /* end of list */ } 3650 } 3651 }, 3652 { 3653 .version = 4, 3654 .props = (PropValue[]) { 3655 { "vmx-eptp-switching", "on" }, 3656 { /* end of list */ } 3657 } 3658 }, 3659 { 3660 .version = 5, 3661 .note = "IBRS, XSAVES, EPT switching, no TSX", 3662 .props = (PropValue[]) { 3663 { "xsaves", "on" }, 3664 { "vmx-xsaves", "on" }, 3665 { /* end of list */ } 3666 } 3667 }, 3668 { /* end of list */ } 3669 } 3670 }, 3671 { 3672 .name = "Cascadelake-Server", 3673 .level = 0xd, 3674 .vendor = CPUID_VENDOR_INTEL, 3675 .family = 6, 3676 .model = 85, 3677 .stepping = 6, 3678 .features[FEAT_1_EDX] = 3679 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3680 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3681 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3682 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3683 CPUID_DE | CPUID_FP87, 3684 .features[FEAT_1_ECX] = 3685 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3686 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3687 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3688 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3689 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3690 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3691 .features[FEAT_8000_0001_EDX] = 3692 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3693 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3694 .features[FEAT_8000_0001_ECX] = 3695 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3696 .features[FEAT_7_0_EBX] = 3697 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3698 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3699 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3700 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3701 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3702 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3703 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3704 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3705 .features[FEAT_7_0_ECX] = 3706 CPUID_7_0_ECX_PKU | 3707 CPUID_7_0_ECX_AVX512VNNI, 3708 .features[FEAT_7_0_EDX] = 3709 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3710 /* XSAVES is added in version 5 */ 3711 .features[FEAT_XSAVE] = 3712 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3713 CPUID_XSAVE_XGETBV1, 3714 .features[FEAT_6_EAX] = 3715 CPUID_6_EAX_ARAT, 3716 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3717 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3718 MSR_VMX_BASIC_TRUE_CTLS, 3719 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3720 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3721 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3722 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3723 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3724 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3725 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3726 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3727 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3728 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3729 .features[FEAT_VMX_EXIT_CTLS] = 3730 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3731 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3732 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3733 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3734 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3735 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3736 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3737 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3738 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3739 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3740 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3741 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3742 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3743 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3744 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3745 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3746 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3747 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3748 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3749 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3750 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3751 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3752 .features[FEAT_VMX_SECONDARY_CTLS] = 3753 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3754 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3755 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3756 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3757 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3758 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3759 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3760 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3761 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3762 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3763 .xlevel = 0x80000008, 3764 .model_id = "Intel Xeon Processor (Cascadelake)", 3765 .versions = (X86CPUVersionDefinition[]) { 3766 { .version = 1 }, 3767 { .version = 2, 3768 .note = "ARCH_CAPABILITIES", 3769 .props = (PropValue[]) { 3770 { "arch-capabilities", "on" }, 3771 { "rdctl-no", "on" }, 3772 { "ibrs-all", "on" }, 3773 { "skip-l1dfl-vmentry", "on" }, 3774 { "mds-no", "on" }, 3775 { /* end of list */ } 3776 }, 3777 }, 3778 { .version = 3, 3779 .alias = "Cascadelake-Server-noTSX", 3780 .note = "ARCH_CAPABILITIES, no TSX", 3781 .props = (PropValue[]) { 3782 { "hle", "off" }, 3783 { "rtm", "off" }, 3784 { /* end of list */ } 3785 }, 3786 }, 3787 { .version = 4, 3788 .note = "ARCH_CAPABILITIES, no TSX", 3789 .props = (PropValue[]) { 3790 { "vmx-eptp-switching", "on" }, 3791 { /* end of list */ } 3792 }, 3793 }, 3794 { .version = 5, 3795 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3796 .props = (PropValue[]) { 3797 { "xsaves", "on" }, 3798 { "vmx-xsaves", "on" }, 3799 { /* end of list */ } 3800 }, 3801 }, 3802 { /* end of list */ } 3803 } 3804 }, 3805 { 3806 .name = "Cooperlake", 3807 .level = 0xd, 3808 .vendor = CPUID_VENDOR_INTEL, 3809 .family = 6, 3810 .model = 85, 3811 .stepping = 10, 3812 .features[FEAT_1_EDX] = 3813 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3814 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3815 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3816 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3817 CPUID_DE | CPUID_FP87, 3818 .features[FEAT_1_ECX] = 3819 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3820 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3821 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3822 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3823 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3824 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3825 .features[FEAT_8000_0001_EDX] = 3826 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3827 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3828 .features[FEAT_8000_0001_ECX] = 3829 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3830 .features[FEAT_7_0_EBX] = 3831 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3832 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3833 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3834 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3835 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3836 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3837 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3838 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3839 .features[FEAT_7_0_ECX] = 3840 CPUID_7_0_ECX_PKU | 3841 CPUID_7_0_ECX_AVX512VNNI, 3842 .features[FEAT_7_0_EDX] = 3843 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3844 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3845 .features[FEAT_ARCH_CAPABILITIES] = 3846 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3847 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3848 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3849 .features[FEAT_7_1_EAX] = 3850 CPUID_7_1_EAX_AVX512_BF16, 3851 /* XSAVES is added in version 2 */ 3852 .features[FEAT_XSAVE] = 3853 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3854 CPUID_XSAVE_XGETBV1, 3855 .features[FEAT_6_EAX] = 3856 CPUID_6_EAX_ARAT, 3857 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3858 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3859 MSR_VMX_BASIC_TRUE_CTLS, 3860 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3861 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3862 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3863 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3864 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3865 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3866 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3867 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3868 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3869 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3870 .features[FEAT_VMX_EXIT_CTLS] = 3871 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3872 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3873 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3874 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3875 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3876 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3877 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3878 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3879 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3880 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3881 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3882 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3883 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3884 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3885 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3886 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3887 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3888 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3889 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3890 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3891 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3892 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3893 .features[FEAT_VMX_SECONDARY_CTLS] = 3894 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3895 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3896 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3897 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3898 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3899 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3900 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3901 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3902 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3903 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3904 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3905 .xlevel = 0x80000008, 3906 .model_id = "Intel Xeon Processor (Cooperlake)", 3907 .versions = (X86CPUVersionDefinition[]) { 3908 { .version = 1 }, 3909 { .version = 2, 3910 .note = "XSAVES", 3911 .props = (PropValue[]) { 3912 { "xsaves", "on" }, 3913 { "vmx-xsaves", "on" }, 3914 { /* end of list */ } 3915 }, 3916 }, 3917 { /* end of list */ } 3918 } 3919 }, 3920 { 3921 .name = "Icelake-Server", 3922 .level = 0xd, 3923 .vendor = CPUID_VENDOR_INTEL, 3924 .family = 6, 3925 .model = 134, 3926 .stepping = 0, 3927 .features[FEAT_1_EDX] = 3928 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3929 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3930 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3931 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3932 CPUID_DE | CPUID_FP87, 3933 .features[FEAT_1_ECX] = 3934 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3935 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3936 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3937 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3938 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3939 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3940 .features[FEAT_8000_0001_EDX] = 3941 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3942 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3943 .features[FEAT_8000_0001_ECX] = 3944 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3945 .features[FEAT_8000_0008_EBX] = 3946 CPUID_8000_0008_EBX_WBNOINVD, 3947 .features[FEAT_7_0_EBX] = 3948 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3949 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3950 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3951 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3952 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3953 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3954 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3955 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3956 .features[FEAT_7_0_ECX] = 3957 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3958 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3959 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3960 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3961 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3962 .features[FEAT_7_0_EDX] = 3963 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3964 /* XSAVES is added in version 5 */ 3965 .features[FEAT_XSAVE] = 3966 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3967 CPUID_XSAVE_XGETBV1, 3968 .features[FEAT_6_EAX] = 3969 CPUID_6_EAX_ARAT, 3970 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3971 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3972 MSR_VMX_BASIC_TRUE_CTLS, 3973 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3974 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3975 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3976 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3977 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3978 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3979 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3980 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3981 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3982 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3983 .features[FEAT_VMX_EXIT_CTLS] = 3984 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3985 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3986 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3987 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3988 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3989 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3990 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3991 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3992 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3993 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3994 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3995 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3996 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3997 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3998 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3999 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4000 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4001 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4002 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4003 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4004 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4005 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4006 .features[FEAT_VMX_SECONDARY_CTLS] = 4007 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4008 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4009 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4010 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4011 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4012 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4013 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4014 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4015 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 4016 .xlevel = 0x80000008, 4017 .model_id = "Intel Xeon Processor (Icelake)", 4018 .versions = (X86CPUVersionDefinition[]) { 4019 { .version = 1 }, 4020 { 4021 .version = 2, 4022 .note = "no TSX", 4023 .alias = "Icelake-Server-noTSX", 4024 .props = (PropValue[]) { 4025 { "hle", "off" }, 4026 { "rtm", "off" }, 4027 { /* end of list */ } 4028 }, 4029 }, 4030 { 4031 .version = 3, 4032 .props = (PropValue[]) { 4033 { "arch-capabilities", "on" }, 4034 { "rdctl-no", "on" }, 4035 { "ibrs-all", "on" }, 4036 { "skip-l1dfl-vmentry", "on" }, 4037 { "mds-no", "on" }, 4038 { "pschange-mc-no", "on" }, 4039 { "taa-no", "on" }, 4040 { /* end of list */ } 4041 }, 4042 }, 4043 { 4044 .version = 4, 4045 .props = (PropValue[]) { 4046 { "sha-ni", "on" }, 4047 { "avx512ifma", "on" }, 4048 { "rdpid", "on" }, 4049 { "fsrm", "on" }, 4050 { "vmx-rdseed-exit", "on" }, 4051 { "vmx-pml", "on" }, 4052 { "vmx-eptp-switching", "on" }, 4053 { "model", "106" }, 4054 { /* end of list */ } 4055 }, 4056 }, 4057 { 4058 .version = 5, 4059 .note = "XSAVES", 4060 .props = (PropValue[]) { 4061 { "xsaves", "on" }, 4062 { "vmx-xsaves", "on" }, 4063 { /* end of list */ } 4064 }, 4065 }, 4066 { 4067 .version = 6, 4068 .note = "5-level EPT", 4069 .props = (PropValue[]) { 4070 { "vmx-page-walk-5", "on" }, 4071 { /* end of list */ } 4072 }, 4073 }, 4074 { 4075 .version = 7, 4076 .note = "TSX, taa-no", 4077 .props = (PropValue[]) { 4078 /* Restore TSX features removed by -v2 above */ 4079 { "hle", "on" }, 4080 { "rtm", "on" }, 4081 { /* end of list */ } 4082 }, 4083 }, 4084 { /* end of list */ } 4085 } 4086 }, 4087 { 4088 .name = "SapphireRapids", 4089 .level = 0x20, 4090 .vendor = CPUID_VENDOR_INTEL, 4091 .family = 6, 4092 .model = 143, 4093 .stepping = 4, 4094 /* 4095 * please keep the ascending order so that we can have a clear view of 4096 * bit position of each feature. 4097 */ 4098 .features[FEAT_1_EDX] = 4099 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4100 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4101 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4102 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4103 CPUID_SSE | CPUID_SSE2, 4104 .features[FEAT_1_ECX] = 4105 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4106 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4107 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4108 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4109 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4110 .features[FEAT_8000_0001_EDX] = 4111 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4112 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4113 .features[FEAT_8000_0001_ECX] = 4114 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4115 .features[FEAT_8000_0008_EBX] = 4116 CPUID_8000_0008_EBX_WBNOINVD, 4117 .features[FEAT_7_0_EBX] = 4118 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4119 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4120 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4121 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4122 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4123 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4124 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4125 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4126 .features[FEAT_7_0_ECX] = 4127 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4128 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4129 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4130 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4131 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4132 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4133 .features[FEAT_7_0_EDX] = 4134 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4135 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4136 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4137 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4138 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4139 .features[FEAT_ARCH_CAPABILITIES] = 4140 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4141 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4142 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4143 .features[FEAT_XSAVE] = 4144 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4145 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4146 .features[FEAT_6_EAX] = 4147 CPUID_6_EAX_ARAT, 4148 .features[FEAT_7_1_EAX] = 4149 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4150 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 4151 .features[FEAT_VMX_BASIC] = 4152 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4153 .features[FEAT_VMX_ENTRY_CTLS] = 4154 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4155 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4156 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4157 .features[FEAT_VMX_EPT_VPID_CAPS] = 4158 MSR_VMX_EPT_EXECONLY | 4159 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4160 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4161 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4162 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4163 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4164 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4165 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4166 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4167 .features[FEAT_VMX_EXIT_CTLS] = 4168 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4169 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4170 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4171 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4172 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4173 .features[FEAT_VMX_MISC] = 4174 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4175 MSR_VMX_MISC_VMWRITE_VMEXIT, 4176 .features[FEAT_VMX_PINBASED_CTLS] = 4177 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4178 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4179 VMX_PIN_BASED_POSTED_INTR, 4180 .features[FEAT_VMX_PROCBASED_CTLS] = 4181 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4182 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4183 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4184 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4185 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4186 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4187 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4188 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4189 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4190 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4191 VMX_CPU_BASED_PAUSE_EXITING | 4192 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4193 .features[FEAT_VMX_SECONDARY_CTLS] = 4194 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4195 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4196 VMX_SECONDARY_EXEC_RDTSCP | 4197 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4198 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4199 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4200 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4201 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4202 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4203 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4204 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4205 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4206 VMX_SECONDARY_EXEC_XSAVES, 4207 .features[FEAT_VMX_VMFUNC] = 4208 MSR_VMX_VMFUNC_EPT_SWITCHING, 4209 .xlevel = 0x80000008, 4210 .model_id = "Intel Xeon Processor (SapphireRapids)", 4211 .versions = (X86CPUVersionDefinition[]) { 4212 { .version = 1 }, 4213 { 4214 .version = 2, 4215 .props = (PropValue[]) { 4216 { "sbdr-ssdp-no", "on" }, 4217 { "fbsdp-no", "on" }, 4218 { "psdp-no", "on" }, 4219 { /* end of list */ } 4220 } 4221 }, 4222 { 4223 .version = 3, 4224 .props = (PropValue[]) { 4225 { "ss", "on" }, 4226 { "tsc-adjust", "on" }, 4227 { "cldemote", "on" }, 4228 { "movdiri", "on" }, 4229 { "movdir64b", "on" }, 4230 { /* end of list */ } 4231 } 4232 }, 4233 { /* end of list */ } 4234 } 4235 }, 4236 { 4237 .name = "GraniteRapids", 4238 .level = 0x20, 4239 .vendor = CPUID_VENDOR_INTEL, 4240 .family = 6, 4241 .model = 173, 4242 .stepping = 0, 4243 /* 4244 * please keep the ascending order so that we can have a clear view of 4245 * bit position of each feature. 4246 */ 4247 .features[FEAT_1_EDX] = 4248 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4249 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4250 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4251 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4252 CPUID_SSE | CPUID_SSE2, 4253 .features[FEAT_1_ECX] = 4254 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4255 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4256 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4257 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4258 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4259 .features[FEAT_8000_0001_EDX] = 4260 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4261 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4262 .features[FEAT_8000_0001_ECX] = 4263 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4264 .features[FEAT_8000_0008_EBX] = 4265 CPUID_8000_0008_EBX_WBNOINVD, 4266 .features[FEAT_7_0_EBX] = 4267 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4268 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4269 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4270 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4271 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4272 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4273 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4274 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4275 .features[FEAT_7_0_ECX] = 4276 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4277 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4278 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4279 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4280 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4281 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4282 .features[FEAT_7_0_EDX] = 4283 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4284 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4285 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4286 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4287 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4288 .features[FEAT_ARCH_CAPABILITIES] = 4289 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4290 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4291 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4292 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4293 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4294 .features[FEAT_XSAVE] = 4295 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4296 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4297 .features[FEAT_6_EAX] = 4298 CPUID_6_EAX_ARAT, 4299 .features[FEAT_7_1_EAX] = 4300 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4301 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4302 CPUID_7_1_EAX_AMX_FP16, 4303 .features[FEAT_7_1_EDX] = 4304 CPUID_7_1_EDX_PREFETCHITI, 4305 .features[FEAT_7_2_EDX] = 4306 CPUID_7_2_EDX_MCDT_NO, 4307 .features[FEAT_VMX_BASIC] = 4308 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4309 .features[FEAT_VMX_ENTRY_CTLS] = 4310 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4311 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4312 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4313 .features[FEAT_VMX_EPT_VPID_CAPS] = 4314 MSR_VMX_EPT_EXECONLY | 4315 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4316 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4317 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4318 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4319 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4320 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4321 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4322 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4323 .features[FEAT_VMX_EXIT_CTLS] = 4324 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4325 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4326 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4327 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4328 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4329 .features[FEAT_VMX_MISC] = 4330 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4331 MSR_VMX_MISC_VMWRITE_VMEXIT, 4332 .features[FEAT_VMX_PINBASED_CTLS] = 4333 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4334 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4335 VMX_PIN_BASED_POSTED_INTR, 4336 .features[FEAT_VMX_PROCBASED_CTLS] = 4337 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4338 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4339 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4340 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4341 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4342 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4343 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4344 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4345 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4346 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4347 VMX_CPU_BASED_PAUSE_EXITING | 4348 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4349 .features[FEAT_VMX_SECONDARY_CTLS] = 4350 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4351 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4352 VMX_SECONDARY_EXEC_RDTSCP | 4353 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4354 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4355 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4356 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4357 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4358 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4359 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4360 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4361 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4362 VMX_SECONDARY_EXEC_XSAVES, 4363 .features[FEAT_VMX_VMFUNC] = 4364 MSR_VMX_VMFUNC_EPT_SWITCHING, 4365 .xlevel = 0x80000008, 4366 .model_id = "Intel Xeon Processor (GraniteRapids)", 4367 .versions = (X86CPUVersionDefinition[]) { 4368 { .version = 1 }, 4369 { /* end of list */ }, 4370 }, 4371 }, 4372 { 4373 .name = "SierraForest", 4374 .level = 0x23, 4375 .vendor = CPUID_VENDOR_INTEL, 4376 .family = 6, 4377 .model = 175, 4378 .stepping = 0, 4379 /* 4380 * please keep the ascending order so that we can have a clear view of 4381 * bit position of each feature. 4382 */ 4383 .features[FEAT_1_EDX] = 4384 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4385 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4386 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4387 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4388 CPUID_SSE | CPUID_SSE2, 4389 .features[FEAT_1_ECX] = 4390 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4391 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4392 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4393 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4394 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4395 .features[FEAT_8000_0001_EDX] = 4396 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4397 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4398 .features[FEAT_8000_0001_ECX] = 4399 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4400 .features[FEAT_8000_0008_EBX] = 4401 CPUID_8000_0008_EBX_WBNOINVD, 4402 .features[FEAT_7_0_EBX] = 4403 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4404 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4405 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4406 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4407 CPUID_7_0_EBX_SHA_NI, 4408 .features[FEAT_7_0_ECX] = 4409 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4410 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4411 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4412 .features[FEAT_7_0_EDX] = 4413 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4414 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4415 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4416 .features[FEAT_ARCH_CAPABILITIES] = 4417 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4418 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4419 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4420 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4421 MSR_ARCH_CAP_PBRSB_NO, 4422 .features[FEAT_XSAVE] = 4423 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4424 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4425 .features[FEAT_6_EAX] = 4426 CPUID_6_EAX_ARAT, 4427 .features[FEAT_7_1_EAX] = 4428 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4429 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4430 .features[FEAT_7_1_EDX] = 4431 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4432 .features[FEAT_7_2_EDX] = 4433 CPUID_7_2_EDX_MCDT_NO, 4434 .features[FEAT_VMX_BASIC] = 4435 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4436 .features[FEAT_VMX_ENTRY_CTLS] = 4437 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4438 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4439 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4440 .features[FEAT_VMX_EPT_VPID_CAPS] = 4441 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4442 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4443 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4444 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4445 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4446 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4447 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4448 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4449 .features[FEAT_VMX_EXIT_CTLS] = 4450 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4451 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4452 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4453 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4454 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4455 .features[FEAT_VMX_MISC] = 4456 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4457 MSR_VMX_MISC_VMWRITE_VMEXIT, 4458 .features[FEAT_VMX_PINBASED_CTLS] = 4459 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4460 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4461 VMX_PIN_BASED_POSTED_INTR, 4462 .features[FEAT_VMX_PROCBASED_CTLS] = 4463 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4464 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4465 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4466 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4467 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4468 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4469 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4470 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4471 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4472 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4473 VMX_CPU_BASED_PAUSE_EXITING | 4474 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4475 .features[FEAT_VMX_SECONDARY_CTLS] = 4476 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4477 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4478 VMX_SECONDARY_EXEC_RDTSCP | 4479 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4480 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4481 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4482 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4483 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4484 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4485 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4486 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4487 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4488 VMX_SECONDARY_EXEC_XSAVES, 4489 .features[FEAT_VMX_VMFUNC] = 4490 MSR_VMX_VMFUNC_EPT_SWITCHING, 4491 .xlevel = 0x80000008, 4492 .model_id = "Intel Xeon Processor (SierraForest)", 4493 .versions = (X86CPUVersionDefinition[]) { 4494 { .version = 1 }, 4495 { /* end of list */ }, 4496 }, 4497 }, 4498 { 4499 .name = "Denverton", 4500 .level = 21, 4501 .vendor = CPUID_VENDOR_INTEL, 4502 .family = 6, 4503 .model = 95, 4504 .stepping = 1, 4505 .features[FEAT_1_EDX] = 4506 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4507 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4508 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4509 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4510 CPUID_SSE | CPUID_SSE2, 4511 .features[FEAT_1_ECX] = 4512 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4513 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4514 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4515 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4516 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4517 .features[FEAT_8000_0001_EDX] = 4518 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4519 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4520 .features[FEAT_8000_0001_ECX] = 4521 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4522 .features[FEAT_7_0_EBX] = 4523 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4524 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4525 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4526 .features[FEAT_7_0_EDX] = 4527 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4528 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4529 /* XSAVES is added in version 3 */ 4530 .features[FEAT_XSAVE] = 4531 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4532 .features[FEAT_6_EAX] = 4533 CPUID_6_EAX_ARAT, 4534 .features[FEAT_ARCH_CAPABILITIES] = 4535 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4536 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4537 MSR_VMX_BASIC_TRUE_CTLS, 4538 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4539 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4540 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4541 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4542 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4543 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4544 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4545 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4546 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4547 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4548 .features[FEAT_VMX_EXIT_CTLS] = 4549 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4550 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4551 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4552 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4553 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4554 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4555 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4556 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4557 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4558 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4559 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4560 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4561 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4562 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4563 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4564 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4565 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4566 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4567 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4568 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4569 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4570 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4571 .features[FEAT_VMX_SECONDARY_CTLS] = 4572 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4573 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4574 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4575 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4576 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4577 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4578 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4579 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4580 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4581 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4582 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4583 .xlevel = 0x80000008, 4584 .model_id = "Intel Atom Processor (Denverton)", 4585 .versions = (X86CPUVersionDefinition[]) { 4586 { .version = 1 }, 4587 { 4588 .version = 2, 4589 .note = "no MPX, no MONITOR", 4590 .props = (PropValue[]) { 4591 { "monitor", "off" }, 4592 { "mpx", "off" }, 4593 { /* end of list */ }, 4594 }, 4595 }, 4596 { 4597 .version = 3, 4598 .note = "XSAVES, no MPX, no MONITOR", 4599 .props = (PropValue[]) { 4600 { "xsaves", "on" }, 4601 { "vmx-xsaves", "on" }, 4602 { /* end of list */ }, 4603 }, 4604 }, 4605 { /* end of list */ }, 4606 }, 4607 }, 4608 { 4609 .name = "Snowridge", 4610 .level = 27, 4611 .vendor = CPUID_VENDOR_INTEL, 4612 .family = 6, 4613 .model = 134, 4614 .stepping = 1, 4615 .features[FEAT_1_EDX] = 4616 /* missing: CPUID_PN CPUID_IA64 */ 4617 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4618 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4619 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4620 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4621 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4622 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4623 CPUID_MMX | 4624 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4625 .features[FEAT_1_ECX] = 4626 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4627 CPUID_EXT_SSSE3 | 4628 CPUID_EXT_CX16 | 4629 CPUID_EXT_SSE41 | 4630 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4631 CPUID_EXT_POPCNT | 4632 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4633 CPUID_EXT_RDRAND, 4634 .features[FEAT_8000_0001_EDX] = 4635 CPUID_EXT2_SYSCALL | 4636 CPUID_EXT2_NX | 4637 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4638 CPUID_EXT2_LM, 4639 .features[FEAT_8000_0001_ECX] = 4640 CPUID_EXT3_LAHF_LM | 4641 CPUID_EXT3_3DNOWPREFETCH, 4642 .features[FEAT_7_0_EBX] = 4643 CPUID_7_0_EBX_FSGSBASE | 4644 CPUID_7_0_EBX_SMEP | 4645 CPUID_7_0_EBX_ERMS | 4646 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4647 CPUID_7_0_EBX_RDSEED | 4648 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4649 CPUID_7_0_EBX_CLWB | 4650 CPUID_7_0_EBX_SHA_NI, 4651 .features[FEAT_7_0_ECX] = 4652 CPUID_7_0_ECX_UMIP | 4653 /* missing bit 5 */ 4654 CPUID_7_0_ECX_GFNI | 4655 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4656 CPUID_7_0_ECX_MOVDIR64B, 4657 .features[FEAT_7_0_EDX] = 4658 CPUID_7_0_EDX_SPEC_CTRL | 4659 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4660 CPUID_7_0_EDX_CORE_CAPABILITY, 4661 .features[FEAT_CORE_CAPABILITY] = 4662 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4663 /* XSAVES is added in version 3 */ 4664 .features[FEAT_XSAVE] = 4665 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4666 CPUID_XSAVE_XGETBV1, 4667 .features[FEAT_6_EAX] = 4668 CPUID_6_EAX_ARAT, 4669 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4670 MSR_VMX_BASIC_TRUE_CTLS, 4671 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4672 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4673 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4674 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4675 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4676 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4677 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4678 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4679 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4680 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4681 .features[FEAT_VMX_EXIT_CTLS] = 4682 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4683 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4684 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4685 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4686 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4687 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4688 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4689 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4690 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4691 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4692 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4693 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4694 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4695 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4696 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4697 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4698 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4699 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4700 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4701 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4702 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4703 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4704 .features[FEAT_VMX_SECONDARY_CTLS] = 4705 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4706 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4707 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4708 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4709 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4710 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4711 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4712 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4713 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4714 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4715 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4716 .xlevel = 0x80000008, 4717 .model_id = "Intel Atom Processor (SnowRidge)", 4718 .versions = (X86CPUVersionDefinition[]) { 4719 { .version = 1 }, 4720 { 4721 .version = 2, 4722 .props = (PropValue[]) { 4723 { "mpx", "off" }, 4724 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4725 { /* end of list */ }, 4726 }, 4727 }, 4728 { 4729 .version = 3, 4730 .note = "XSAVES, no MPX", 4731 .props = (PropValue[]) { 4732 { "xsaves", "on" }, 4733 { "vmx-xsaves", "on" }, 4734 { /* end of list */ }, 4735 }, 4736 }, 4737 { 4738 .version = 4, 4739 .note = "no split lock detect, no core-capability", 4740 .props = (PropValue[]) { 4741 { "split-lock-detect", "off" }, 4742 { "core-capability", "off" }, 4743 { /* end of list */ }, 4744 }, 4745 }, 4746 { /* end of list */ }, 4747 }, 4748 }, 4749 { 4750 .name = "KnightsMill", 4751 .level = 0xd, 4752 .vendor = CPUID_VENDOR_INTEL, 4753 .family = 6, 4754 .model = 133, 4755 .stepping = 0, 4756 .features[FEAT_1_EDX] = 4757 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4758 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4759 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4760 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4761 CPUID_PSE | CPUID_DE | CPUID_FP87, 4762 .features[FEAT_1_ECX] = 4763 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4764 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4765 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4766 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4767 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4768 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4769 .features[FEAT_8000_0001_EDX] = 4770 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4771 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4772 .features[FEAT_8000_0001_ECX] = 4773 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4774 .features[FEAT_7_0_EBX] = 4775 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4776 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4777 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 4778 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 4779 CPUID_7_0_EBX_AVX512ER, 4780 .features[FEAT_7_0_ECX] = 4781 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 4782 .features[FEAT_7_0_EDX] = 4783 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 4784 .features[FEAT_XSAVE] = 4785 CPUID_XSAVE_XSAVEOPT, 4786 .features[FEAT_6_EAX] = 4787 CPUID_6_EAX_ARAT, 4788 .xlevel = 0x80000008, 4789 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 4790 }, 4791 { 4792 .name = "Opteron_G1", 4793 .level = 5, 4794 .vendor = CPUID_VENDOR_AMD, 4795 .family = 15, 4796 .model = 6, 4797 .stepping = 1, 4798 .features[FEAT_1_EDX] = 4799 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4800 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4801 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4802 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4803 CPUID_DE | CPUID_FP87, 4804 .features[FEAT_1_ECX] = 4805 CPUID_EXT_SSE3, 4806 .features[FEAT_8000_0001_EDX] = 4807 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4808 .xlevel = 0x80000008, 4809 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 4810 }, 4811 { 4812 .name = "Opteron_G2", 4813 .level = 5, 4814 .vendor = CPUID_VENDOR_AMD, 4815 .family = 15, 4816 .model = 6, 4817 .stepping = 1, 4818 .features[FEAT_1_EDX] = 4819 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4820 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4821 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4822 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4823 CPUID_DE | CPUID_FP87, 4824 .features[FEAT_1_ECX] = 4825 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 4826 .features[FEAT_8000_0001_EDX] = 4827 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4828 .features[FEAT_8000_0001_ECX] = 4829 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4830 .xlevel = 0x80000008, 4831 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 4832 }, 4833 { 4834 .name = "Opteron_G3", 4835 .level = 5, 4836 .vendor = CPUID_VENDOR_AMD, 4837 .family = 16, 4838 .model = 2, 4839 .stepping = 3, 4840 .features[FEAT_1_EDX] = 4841 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4842 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4843 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4844 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4845 CPUID_DE | CPUID_FP87, 4846 .features[FEAT_1_ECX] = 4847 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 4848 CPUID_EXT_SSE3, 4849 .features[FEAT_8000_0001_EDX] = 4850 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 4851 CPUID_EXT2_RDTSCP, 4852 .features[FEAT_8000_0001_ECX] = 4853 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 4854 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4855 .xlevel = 0x80000008, 4856 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 4857 }, 4858 { 4859 .name = "Opteron_G4", 4860 .level = 0xd, 4861 .vendor = CPUID_VENDOR_AMD, 4862 .family = 21, 4863 .model = 1, 4864 .stepping = 2, 4865 .features[FEAT_1_EDX] = 4866 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4867 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4868 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4869 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4870 CPUID_DE | CPUID_FP87, 4871 .features[FEAT_1_ECX] = 4872 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4873 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4874 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 4875 CPUID_EXT_SSE3, 4876 .features[FEAT_8000_0001_EDX] = 4877 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4878 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4879 .features[FEAT_8000_0001_ECX] = 4880 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4881 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4882 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4883 CPUID_EXT3_LAHF_LM, 4884 .features[FEAT_SVM] = 4885 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4886 /* no xsaveopt! */ 4887 .xlevel = 0x8000001A, 4888 .model_id = "AMD Opteron 62xx class CPU", 4889 }, 4890 { 4891 .name = "Opteron_G5", 4892 .level = 0xd, 4893 .vendor = CPUID_VENDOR_AMD, 4894 .family = 21, 4895 .model = 2, 4896 .stepping = 0, 4897 .features[FEAT_1_EDX] = 4898 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4899 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4900 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4901 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4902 CPUID_DE | CPUID_FP87, 4903 .features[FEAT_1_ECX] = 4904 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 4905 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 4906 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4907 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4908 .features[FEAT_8000_0001_EDX] = 4909 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4910 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4911 .features[FEAT_8000_0001_ECX] = 4912 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4913 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4914 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4915 CPUID_EXT3_LAHF_LM, 4916 .features[FEAT_SVM] = 4917 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4918 /* no xsaveopt! */ 4919 .xlevel = 0x8000001A, 4920 .model_id = "AMD Opteron 63xx class CPU", 4921 }, 4922 { 4923 .name = "EPYC", 4924 .level = 0xd, 4925 .vendor = CPUID_VENDOR_AMD, 4926 .family = 23, 4927 .model = 1, 4928 .stepping = 2, 4929 .features[FEAT_1_EDX] = 4930 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4931 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4932 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4933 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4934 CPUID_VME | CPUID_FP87, 4935 .features[FEAT_1_ECX] = 4936 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4937 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4938 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4939 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4940 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4941 .features[FEAT_8000_0001_EDX] = 4942 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4943 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4944 CPUID_EXT2_SYSCALL, 4945 .features[FEAT_8000_0001_ECX] = 4946 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4947 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4948 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4949 CPUID_EXT3_TOPOEXT, 4950 .features[FEAT_7_0_EBX] = 4951 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4952 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4953 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4954 CPUID_7_0_EBX_SHA_NI, 4955 .features[FEAT_XSAVE] = 4956 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4957 CPUID_XSAVE_XGETBV1, 4958 .features[FEAT_6_EAX] = 4959 CPUID_6_EAX_ARAT, 4960 .features[FEAT_SVM] = 4961 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4962 .xlevel = 0x8000001E, 4963 .model_id = "AMD EPYC Processor", 4964 .cache_info = &epyc_cache_info, 4965 .versions = (X86CPUVersionDefinition[]) { 4966 { .version = 1 }, 4967 { 4968 .version = 2, 4969 .alias = "EPYC-IBPB", 4970 .props = (PropValue[]) { 4971 { "ibpb", "on" }, 4972 { "model-id", 4973 "AMD EPYC Processor (with IBPB)" }, 4974 { /* end of list */ } 4975 } 4976 }, 4977 { 4978 .version = 3, 4979 .props = (PropValue[]) { 4980 { "ibpb", "on" }, 4981 { "perfctr-core", "on" }, 4982 { "clzero", "on" }, 4983 { "xsaveerptr", "on" }, 4984 { "xsaves", "on" }, 4985 { "model-id", 4986 "AMD EPYC Processor" }, 4987 { /* end of list */ } 4988 } 4989 }, 4990 { 4991 .version = 4, 4992 .props = (PropValue[]) { 4993 { "model-id", 4994 "AMD EPYC-v4 Processor" }, 4995 { /* end of list */ } 4996 }, 4997 .cache_info = &epyc_v4_cache_info 4998 }, 4999 { /* end of list */ } 5000 } 5001 }, 5002 { 5003 .name = "Dhyana", 5004 .level = 0xd, 5005 .vendor = CPUID_VENDOR_HYGON, 5006 .family = 24, 5007 .model = 0, 5008 .stepping = 1, 5009 .features[FEAT_1_EDX] = 5010 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5011 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5012 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5013 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5014 CPUID_VME | CPUID_FP87, 5015 .features[FEAT_1_ECX] = 5016 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5017 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 5018 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5019 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5020 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 5021 .features[FEAT_8000_0001_EDX] = 5022 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5023 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5024 CPUID_EXT2_SYSCALL, 5025 .features[FEAT_8000_0001_ECX] = 5026 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5027 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5028 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5029 CPUID_EXT3_TOPOEXT, 5030 .features[FEAT_8000_0008_EBX] = 5031 CPUID_8000_0008_EBX_IBPB, 5032 .features[FEAT_7_0_EBX] = 5033 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5034 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5035 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 5036 /* XSAVES is added in version 2 */ 5037 .features[FEAT_XSAVE] = 5038 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5039 CPUID_XSAVE_XGETBV1, 5040 .features[FEAT_6_EAX] = 5041 CPUID_6_EAX_ARAT, 5042 .features[FEAT_SVM] = 5043 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5044 .xlevel = 0x8000001E, 5045 .model_id = "Hygon Dhyana Processor", 5046 .cache_info = &epyc_cache_info, 5047 .versions = (X86CPUVersionDefinition[]) { 5048 { .version = 1 }, 5049 { .version = 2, 5050 .note = "XSAVES", 5051 .props = (PropValue[]) { 5052 { "xsaves", "on" }, 5053 { /* end of list */ } 5054 }, 5055 }, 5056 { /* end of list */ } 5057 } 5058 }, 5059 { 5060 .name = "EPYC-Rome", 5061 .level = 0xd, 5062 .vendor = CPUID_VENDOR_AMD, 5063 .family = 23, 5064 .model = 49, 5065 .stepping = 0, 5066 .features[FEAT_1_EDX] = 5067 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5068 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5069 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5070 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5071 CPUID_VME | CPUID_FP87, 5072 .features[FEAT_1_ECX] = 5073 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5074 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5075 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5076 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5077 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5078 .features[FEAT_8000_0001_EDX] = 5079 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5080 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5081 CPUID_EXT2_SYSCALL, 5082 .features[FEAT_8000_0001_ECX] = 5083 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5084 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5085 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5086 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5087 .features[FEAT_8000_0008_EBX] = 5088 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5089 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5090 CPUID_8000_0008_EBX_STIBP, 5091 .features[FEAT_7_0_EBX] = 5092 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5093 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5094 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5095 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 5096 .features[FEAT_7_0_ECX] = 5097 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 5098 .features[FEAT_XSAVE] = 5099 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5100 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5101 .features[FEAT_6_EAX] = 5102 CPUID_6_EAX_ARAT, 5103 .features[FEAT_SVM] = 5104 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5105 .xlevel = 0x8000001E, 5106 .model_id = "AMD EPYC-Rome Processor", 5107 .cache_info = &epyc_rome_cache_info, 5108 .versions = (X86CPUVersionDefinition[]) { 5109 { .version = 1 }, 5110 { 5111 .version = 2, 5112 .props = (PropValue[]) { 5113 { "ibrs", "on" }, 5114 { "amd-ssbd", "on" }, 5115 { /* end of list */ } 5116 } 5117 }, 5118 { 5119 .version = 3, 5120 .props = (PropValue[]) { 5121 { "model-id", 5122 "AMD EPYC-Rome-v3 Processor" }, 5123 { /* end of list */ } 5124 }, 5125 .cache_info = &epyc_rome_v3_cache_info 5126 }, 5127 { 5128 .version = 4, 5129 .props = (PropValue[]) { 5130 /* Erratum 1386 */ 5131 { "model-id", 5132 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 5133 { "xsaves", "off" }, 5134 { /* end of list */ } 5135 }, 5136 }, 5137 { /* end of list */ } 5138 } 5139 }, 5140 { 5141 .name = "EPYC-Milan", 5142 .level = 0xd, 5143 .vendor = CPUID_VENDOR_AMD, 5144 .family = 25, 5145 .model = 1, 5146 .stepping = 1, 5147 .features[FEAT_1_EDX] = 5148 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5149 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5150 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5151 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5152 CPUID_VME | CPUID_FP87, 5153 .features[FEAT_1_ECX] = 5154 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5155 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5156 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5157 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5158 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5159 CPUID_EXT_PCID, 5160 .features[FEAT_8000_0001_EDX] = 5161 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5162 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5163 CPUID_EXT2_SYSCALL, 5164 .features[FEAT_8000_0001_ECX] = 5165 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5166 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5167 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5168 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5169 .features[FEAT_8000_0008_EBX] = 5170 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5171 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5172 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5173 CPUID_8000_0008_EBX_AMD_SSBD, 5174 .features[FEAT_7_0_EBX] = 5175 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5176 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5177 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5178 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 5179 CPUID_7_0_EBX_INVPCID, 5180 .features[FEAT_7_0_ECX] = 5181 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 5182 .features[FEAT_7_0_EDX] = 5183 CPUID_7_0_EDX_FSRM, 5184 .features[FEAT_XSAVE] = 5185 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5186 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5187 .features[FEAT_6_EAX] = 5188 CPUID_6_EAX_ARAT, 5189 .features[FEAT_SVM] = 5190 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 5191 .xlevel = 0x8000001E, 5192 .model_id = "AMD EPYC-Milan Processor", 5193 .cache_info = &epyc_milan_cache_info, 5194 .versions = (X86CPUVersionDefinition[]) { 5195 { .version = 1 }, 5196 { 5197 .version = 2, 5198 .props = (PropValue[]) { 5199 { "model-id", 5200 "AMD EPYC-Milan-v2 Processor" }, 5201 { "vaes", "on" }, 5202 { "vpclmulqdq", "on" }, 5203 { "stibp-always-on", "on" }, 5204 { "amd-psfd", "on" }, 5205 { "no-nested-data-bp", "on" }, 5206 { "lfence-always-serializing", "on" }, 5207 { "null-sel-clr-base", "on" }, 5208 { /* end of list */ } 5209 }, 5210 .cache_info = &epyc_milan_v2_cache_info 5211 }, 5212 { /* end of list */ } 5213 } 5214 }, 5215 { 5216 .name = "EPYC-Genoa", 5217 .level = 0xd, 5218 .vendor = CPUID_VENDOR_AMD, 5219 .family = 25, 5220 .model = 17, 5221 .stepping = 0, 5222 .features[FEAT_1_EDX] = 5223 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5224 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5225 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5226 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5227 CPUID_VME | CPUID_FP87, 5228 .features[FEAT_1_ECX] = 5229 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5230 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5231 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5232 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5233 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 5234 CPUID_EXT_SSE3, 5235 .features[FEAT_8000_0001_EDX] = 5236 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5237 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5238 CPUID_EXT2_SYSCALL, 5239 .features[FEAT_8000_0001_ECX] = 5240 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5241 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5242 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5243 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5244 .features[FEAT_8000_0008_EBX] = 5245 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5246 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5247 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5248 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5249 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5250 .features[FEAT_8000_0021_EAX] = 5251 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | 5252 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5253 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5254 CPUID_8000_0021_EAX_AUTO_IBRS, 5255 .features[FEAT_7_0_EBX] = 5256 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5257 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5258 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5259 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5260 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5261 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5262 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5263 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5264 .features[FEAT_7_0_ECX] = 5265 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5266 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5267 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5268 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5269 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5270 CPUID_7_0_ECX_RDPID, 5271 .features[FEAT_7_0_EDX] = 5272 CPUID_7_0_EDX_FSRM, 5273 .features[FEAT_7_1_EAX] = 5274 CPUID_7_1_EAX_AVX512_BF16, 5275 .features[FEAT_XSAVE] = 5276 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5277 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5278 .features[FEAT_6_EAX] = 5279 CPUID_6_EAX_ARAT, 5280 .features[FEAT_SVM] = 5281 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5282 CPUID_SVM_SVME_ADDR_CHK, 5283 .xlevel = 0x80000022, 5284 .model_id = "AMD EPYC-Genoa Processor", 5285 .cache_info = &epyc_genoa_cache_info, 5286 }, 5287 }; 5288 5289 /* 5290 * We resolve CPU model aliases using -v1 when using "-machine 5291 * none", but this is just for compatibility while libvirt isn't 5292 * adapted to resolve CPU model versions before creating VMs. 5293 * See "Runnability guarantee of CPU models" at 5294 * docs/about/deprecated.rst. 5295 */ 5296 X86CPUVersion default_cpu_version = 1; 5297 5298 void x86_cpu_set_default_version(X86CPUVersion version) 5299 { 5300 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 5301 assert(version != CPU_VERSION_AUTO); 5302 default_cpu_version = version; 5303 } 5304 5305 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 5306 { 5307 int v = 0; 5308 const X86CPUVersionDefinition *vdef = 5309 x86_cpu_def_get_versions(model->cpudef); 5310 while (vdef->version) { 5311 v = vdef->version; 5312 vdef++; 5313 } 5314 return v; 5315 } 5316 5317 /* Return the actual version being used for a specific CPU model */ 5318 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 5319 { 5320 X86CPUVersion v = model->version; 5321 if (v == CPU_VERSION_AUTO) { 5322 v = default_cpu_version; 5323 } 5324 if (v == CPU_VERSION_LATEST) { 5325 return x86_cpu_model_last_version(model); 5326 } 5327 return v; 5328 } 5329 5330 static Property max_x86_cpu_properties[] = { 5331 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 5332 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 5333 DEFINE_PROP_END_OF_LIST() 5334 }; 5335 5336 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 5337 { 5338 Object *obj = OBJECT(dev); 5339 5340 if (!object_property_get_int(obj, "family", &error_abort)) { 5341 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5342 object_property_set_int(obj, "family", 15, &error_abort); 5343 object_property_set_int(obj, "model", 107, &error_abort); 5344 object_property_set_int(obj, "stepping", 1, &error_abort); 5345 } else { 5346 object_property_set_int(obj, "family", 6, &error_abort); 5347 object_property_set_int(obj, "model", 6, &error_abort); 5348 object_property_set_int(obj, "stepping", 3, &error_abort); 5349 } 5350 } 5351 5352 x86_cpu_realizefn(dev, errp); 5353 } 5354 5355 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 5356 { 5357 DeviceClass *dc = DEVICE_CLASS(oc); 5358 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5359 5360 xcc->ordering = 9; 5361 5362 xcc->model_description = 5363 "Enables all features supported by the accelerator in the current host"; 5364 5365 device_class_set_props(dc, max_x86_cpu_properties); 5366 dc->realize = max_x86_cpu_realize; 5367 } 5368 5369 static void max_x86_cpu_initfn(Object *obj) 5370 { 5371 X86CPU *cpu = X86_CPU(obj); 5372 5373 /* We can't fill the features array here because we don't know yet if 5374 * "migratable" is true or false. 5375 */ 5376 cpu->max_features = true; 5377 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 5378 5379 /* 5380 * these defaults are used for TCG and all other accelerators 5381 * besides KVM and HVF, which overwrite these values 5382 */ 5383 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 5384 &error_abort); 5385 object_property_set_str(OBJECT(cpu), "model-id", 5386 "QEMU TCG CPU version " QEMU_HW_VERSION, 5387 &error_abort); 5388 } 5389 5390 static const TypeInfo max_x86_cpu_type_info = { 5391 .name = X86_CPU_TYPE_NAME("max"), 5392 .parent = TYPE_X86_CPU, 5393 .instance_init = max_x86_cpu_initfn, 5394 .class_init = max_x86_cpu_class_init, 5395 }; 5396 5397 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 5398 { 5399 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5400 5401 switch (f->type) { 5402 case CPUID_FEATURE_WORD: 5403 { 5404 const char *reg = get_register_name_32(f->cpuid.reg); 5405 assert(reg); 5406 return g_strdup_printf("CPUID.%02XH:%s", 5407 f->cpuid.eax, reg); 5408 } 5409 case MSR_FEATURE_WORD: 5410 return g_strdup_printf("MSR(%02XH)", 5411 f->msr.index); 5412 } 5413 5414 return NULL; 5415 } 5416 5417 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5418 { 5419 FeatureWord w; 5420 5421 for (w = 0; w < FEATURE_WORDS; w++) { 5422 if (cpu->filtered_features[w]) { 5423 return true; 5424 } 5425 } 5426 5427 return false; 5428 } 5429 5430 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5431 const char *verbose_prefix) 5432 { 5433 CPUX86State *env = &cpu->env; 5434 FeatureWordInfo *f = &feature_word_info[w]; 5435 int i; 5436 5437 if (!cpu->force_features) { 5438 env->features[w] &= ~mask; 5439 } 5440 cpu->filtered_features[w] |= mask; 5441 5442 if (!verbose_prefix) { 5443 return; 5444 } 5445 5446 for (i = 0; i < 64; ++i) { 5447 if ((1ULL << i) & mask) { 5448 g_autofree char *feat_word_str = feature_word_description(f, i); 5449 warn_report("%s: %s%s%s [bit %d]", 5450 verbose_prefix, 5451 feat_word_str, 5452 f->feat_names[i] ? "." : "", 5453 f->feat_names[i] ? f->feat_names[i] : "", i); 5454 } 5455 } 5456 } 5457 5458 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5459 const char *name, void *opaque, 5460 Error **errp) 5461 { 5462 X86CPU *cpu = X86_CPU(obj); 5463 CPUX86State *env = &cpu->env; 5464 uint64_t value; 5465 5466 value = (env->cpuid_version >> 8) & 0xf; 5467 if (value == 0xf) { 5468 value += (env->cpuid_version >> 20) & 0xff; 5469 } 5470 visit_type_uint64(v, name, &value, errp); 5471 } 5472 5473 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5474 const char *name, void *opaque, 5475 Error **errp) 5476 { 5477 X86CPU *cpu = X86_CPU(obj); 5478 CPUX86State *env = &cpu->env; 5479 const uint64_t max = 0xff + 0xf; 5480 uint64_t value; 5481 5482 if (!visit_type_uint64(v, name, &value, errp)) { 5483 return; 5484 } 5485 if (value > max) { 5486 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5487 name ? name : "null", max); 5488 return; 5489 } 5490 5491 env->cpuid_version &= ~0xff00f00; 5492 if (value > 0x0f) { 5493 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5494 } else { 5495 env->cpuid_version |= value << 8; 5496 } 5497 } 5498 5499 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5500 const char *name, void *opaque, 5501 Error **errp) 5502 { 5503 X86CPU *cpu = X86_CPU(obj); 5504 CPUX86State *env = &cpu->env; 5505 uint64_t value; 5506 5507 value = (env->cpuid_version >> 4) & 0xf; 5508 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5509 visit_type_uint64(v, name, &value, errp); 5510 } 5511 5512 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5513 const char *name, void *opaque, 5514 Error **errp) 5515 { 5516 X86CPU *cpu = X86_CPU(obj); 5517 CPUX86State *env = &cpu->env; 5518 const uint64_t max = 0xff; 5519 uint64_t value; 5520 5521 if (!visit_type_uint64(v, name, &value, errp)) { 5522 return; 5523 } 5524 if (value > max) { 5525 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5526 name ? name : "null", max); 5527 return; 5528 } 5529 5530 env->cpuid_version &= ~0xf00f0; 5531 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5532 } 5533 5534 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5535 const char *name, void *opaque, 5536 Error **errp) 5537 { 5538 X86CPU *cpu = X86_CPU(obj); 5539 CPUX86State *env = &cpu->env; 5540 uint64_t value; 5541 5542 value = env->cpuid_version & 0xf; 5543 visit_type_uint64(v, name, &value, errp); 5544 } 5545 5546 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5547 const char *name, void *opaque, 5548 Error **errp) 5549 { 5550 X86CPU *cpu = X86_CPU(obj); 5551 CPUX86State *env = &cpu->env; 5552 const uint64_t max = 0xf; 5553 uint64_t value; 5554 5555 if (!visit_type_uint64(v, name, &value, errp)) { 5556 return; 5557 } 5558 if (value > max) { 5559 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5560 name ? name : "null", max); 5561 return; 5562 } 5563 5564 env->cpuid_version &= ~0xf; 5565 env->cpuid_version |= value & 0xf; 5566 } 5567 5568 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5569 { 5570 X86CPU *cpu = X86_CPU(obj); 5571 CPUX86State *env = &cpu->env; 5572 char *value; 5573 5574 value = g_malloc(CPUID_VENDOR_SZ + 1); 5575 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5576 env->cpuid_vendor3); 5577 return value; 5578 } 5579 5580 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5581 Error **errp) 5582 { 5583 X86CPU *cpu = X86_CPU(obj); 5584 CPUX86State *env = &cpu->env; 5585 int i; 5586 5587 if (strlen(value) != CPUID_VENDOR_SZ) { 5588 error_setg(errp, "value of property 'vendor' must consist of" 5589 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 5590 return; 5591 } 5592 5593 env->cpuid_vendor1 = 0; 5594 env->cpuid_vendor2 = 0; 5595 env->cpuid_vendor3 = 0; 5596 for (i = 0; i < 4; i++) { 5597 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5598 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5599 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5600 } 5601 } 5602 5603 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5604 { 5605 X86CPU *cpu = X86_CPU(obj); 5606 CPUX86State *env = &cpu->env; 5607 char *value; 5608 int i; 5609 5610 value = g_malloc(48 + 1); 5611 for (i = 0; i < 48; i++) { 5612 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5613 } 5614 value[48] = '\0'; 5615 return value; 5616 } 5617 5618 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5619 Error **errp) 5620 { 5621 X86CPU *cpu = X86_CPU(obj); 5622 CPUX86State *env = &cpu->env; 5623 int c, len, i; 5624 5625 if (model_id == NULL) { 5626 model_id = ""; 5627 } 5628 len = strlen(model_id); 5629 memset(env->cpuid_model, 0, 48); 5630 for (i = 0; i < 48; i++) { 5631 if (i >= len) { 5632 c = '\0'; 5633 } else { 5634 c = (uint8_t)model_id[i]; 5635 } 5636 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 5637 } 5638 } 5639 5640 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 5641 void *opaque, Error **errp) 5642 { 5643 X86CPU *cpu = X86_CPU(obj); 5644 int64_t value; 5645 5646 value = cpu->env.tsc_khz * 1000; 5647 visit_type_int(v, name, &value, errp); 5648 } 5649 5650 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 5651 void *opaque, Error **errp) 5652 { 5653 X86CPU *cpu = X86_CPU(obj); 5654 const int64_t max = INT64_MAX; 5655 int64_t value; 5656 5657 if (!visit_type_int(v, name, &value, errp)) { 5658 return; 5659 } 5660 if (value < 0 || value > max) { 5661 error_setg(errp, "parameter '%s' can be at most %" PRId64, 5662 name ? name : "null", max); 5663 return; 5664 } 5665 5666 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 5667 } 5668 5669 /* Generic getter for "feature-words" and "filtered-features" properties */ 5670 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 5671 const char *name, void *opaque, 5672 Error **errp) 5673 { 5674 uint64_t *array = (uint64_t *)opaque; 5675 FeatureWord w; 5676 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 5677 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 5678 X86CPUFeatureWordInfoList *list = NULL; 5679 5680 for (w = 0; w < FEATURE_WORDS; w++) { 5681 FeatureWordInfo *wi = &feature_word_info[w]; 5682 /* 5683 * We didn't have MSR features when "feature-words" was 5684 * introduced. Therefore skipped other type entries. 5685 */ 5686 if (wi->type != CPUID_FEATURE_WORD) { 5687 continue; 5688 } 5689 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 5690 qwi->cpuid_input_eax = wi->cpuid.eax; 5691 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 5692 qwi->cpuid_input_ecx = wi->cpuid.ecx; 5693 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 5694 qwi->features = array[w]; 5695 5696 /* List will be in reverse order, but order shouldn't matter */ 5697 list_entries[w].next = list; 5698 list_entries[w].value = &word_infos[w]; 5699 list = &list_entries[w]; 5700 } 5701 5702 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 5703 } 5704 5705 /* Convert all '_' in a feature string option name to '-', to make feature 5706 * name conform to QOM property naming rule, which uses '-' instead of '_'. 5707 */ 5708 static inline void feat2prop(char *s) 5709 { 5710 while ((s = strchr(s, '_'))) { 5711 *s = '-'; 5712 } 5713 } 5714 5715 /* Return the feature property name for a feature flag bit */ 5716 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 5717 { 5718 const char *name; 5719 /* XSAVE components are automatically enabled by other features, 5720 * so return the original feature name instead 5721 */ 5722 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 5723 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 5724 5725 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 5726 x86_ext_save_areas[comp].bits) { 5727 w = x86_ext_save_areas[comp].feature; 5728 bitnr = ctz32(x86_ext_save_areas[comp].bits); 5729 } 5730 } 5731 5732 assert(bitnr < 64); 5733 assert(w < FEATURE_WORDS); 5734 name = feature_word_info[w].feat_names[bitnr]; 5735 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 5736 return name; 5737 } 5738 5739 /* Compatibility hack to maintain legacy +-feat semantic, 5740 * where +-feat overwrites any feature set by 5741 * feat=on|feat even if the later is parsed after +-feat 5742 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 5743 */ 5744 static GList *plus_features, *minus_features; 5745 5746 static gint compare_string(gconstpointer a, gconstpointer b) 5747 { 5748 return g_strcmp0(a, b); 5749 } 5750 5751 /* Parse "+feature,-feature,feature=foo" CPU feature string 5752 */ 5753 static void x86_cpu_parse_featurestr(const char *typename, char *features, 5754 Error **errp) 5755 { 5756 char *featurestr; /* Single 'key=value" string being parsed */ 5757 static bool cpu_globals_initialized; 5758 bool ambiguous = false; 5759 5760 if (cpu_globals_initialized) { 5761 return; 5762 } 5763 cpu_globals_initialized = true; 5764 5765 if (!features) { 5766 return; 5767 } 5768 5769 for (featurestr = strtok(features, ","); 5770 featurestr; 5771 featurestr = strtok(NULL, ",")) { 5772 const char *name; 5773 const char *val = NULL; 5774 char *eq = NULL; 5775 char num[32]; 5776 GlobalProperty *prop; 5777 5778 /* Compatibility syntax: */ 5779 if (featurestr[0] == '+') { 5780 plus_features = g_list_append(plus_features, 5781 g_strdup(featurestr + 1)); 5782 continue; 5783 } else if (featurestr[0] == '-') { 5784 minus_features = g_list_append(minus_features, 5785 g_strdup(featurestr + 1)); 5786 continue; 5787 } 5788 5789 eq = strchr(featurestr, '='); 5790 if (eq) { 5791 *eq++ = 0; 5792 val = eq; 5793 } else { 5794 val = "on"; 5795 } 5796 5797 feat2prop(featurestr); 5798 name = featurestr; 5799 5800 if (g_list_find_custom(plus_features, name, compare_string)) { 5801 warn_report("Ambiguous CPU model string. " 5802 "Don't mix both \"+%s\" and \"%s=%s\"", 5803 name, name, val); 5804 ambiguous = true; 5805 } 5806 if (g_list_find_custom(minus_features, name, compare_string)) { 5807 warn_report("Ambiguous CPU model string. " 5808 "Don't mix both \"-%s\" and \"%s=%s\"", 5809 name, name, val); 5810 ambiguous = true; 5811 } 5812 5813 /* Special case: */ 5814 if (!strcmp(name, "tsc-freq")) { 5815 int ret; 5816 uint64_t tsc_freq; 5817 5818 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 5819 if (ret < 0 || tsc_freq > INT64_MAX) { 5820 error_setg(errp, "bad numerical value %s", val); 5821 return; 5822 } 5823 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 5824 val = num; 5825 name = "tsc-frequency"; 5826 } 5827 5828 prop = g_new0(typeof(*prop), 1); 5829 prop->driver = typename; 5830 prop->property = g_strdup(name); 5831 prop->value = g_strdup(val); 5832 qdev_prop_register_global(prop); 5833 } 5834 5835 if (ambiguous) { 5836 warn_report("Compatibility of ambiguous CPU model " 5837 "strings won't be kept on future QEMU versions"); 5838 } 5839 } 5840 5841 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 5842 5843 /* Build a list with the name of all features on a feature word array */ 5844 static void x86_cpu_list_feature_names(FeatureWordArray features, 5845 strList **list) 5846 { 5847 strList **tail = list; 5848 FeatureWord w; 5849 5850 for (w = 0; w < FEATURE_WORDS; w++) { 5851 uint64_t filtered = features[w]; 5852 int i; 5853 for (i = 0; i < 64; i++) { 5854 if (filtered & (1ULL << i)) { 5855 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 5856 } 5857 } 5858 } 5859 } 5860 5861 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 5862 const char *name, void *opaque, 5863 Error **errp) 5864 { 5865 X86CPU *xc = X86_CPU(obj); 5866 strList *result = NULL; 5867 5868 x86_cpu_list_feature_names(xc->filtered_features, &result); 5869 visit_type_strList(v, "unavailable-features", &result, errp); 5870 } 5871 5872 /* Print all cpuid feature names in featureset 5873 */ 5874 static void listflags(GList *features) 5875 { 5876 size_t len = 0; 5877 GList *tmp; 5878 5879 for (tmp = features; tmp; tmp = tmp->next) { 5880 const char *name = tmp->data; 5881 if ((len + strlen(name) + 1) >= 75) { 5882 qemu_printf("\n"); 5883 len = 0; 5884 } 5885 qemu_printf("%s%s", len == 0 ? " " : " ", name); 5886 len += strlen(name) + 1; 5887 } 5888 qemu_printf("\n"); 5889 } 5890 5891 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 5892 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 5893 { 5894 ObjectClass *class_a = (ObjectClass *)a; 5895 ObjectClass *class_b = (ObjectClass *)b; 5896 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 5897 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 5898 int ret; 5899 5900 if (cc_a->ordering != cc_b->ordering) { 5901 ret = cc_a->ordering - cc_b->ordering; 5902 } else { 5903 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 5904 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 5905 ret = strcmp(name_a, name_b); 5906 } 5907 return ret; 5908 } 5909 5910 static GSList *get_sorted_cpu_model_list(void) 5911 { 5912 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 5913 list = g_slist_sort(list, x86_cpu_list_compare); 5914 return list; 5915 } 5916 5917 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 5918 { 5919 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 5920 char *r = object_property_get_str(obj, "model-id", &error_abort); 5921 object_unref(obj); 5922 return r; 5923 } 5924 5925 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 5926 { 5927 X86CPUVersion version; 5928 5929 if (!cc->model || !cc->model->is_alias) { 5930 return NULL; 5931 } 5932 version = x86_cpu_model_resolve_version(cc->model); 5933 if (version <= 0) { 5934 return NULL; 5935 } 5936 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 5937 } 5938 5939 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 5940 { 5941 ObjectClass *oc = data; 5942 X86CPUClass *cc = X86_CPU_CLASS(oc); 5943 g_autofree char *name = x86_cpu_class_get_model_name(cc); 5944 g_autofree char *desc = g_strdup(cc->model_description); 5945 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 5946 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 5947 5948 if (!desc && alias_of) { 5949 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 5950 desc = g_strdup("(alias configured by machine type)"); 5951 } else { 5952 desc = g_strdup_printf("(alias of %s)", alias_of); 5953 } 5954 } 5955 if (!desc && cc->model && cc->model->note) { 5956 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 5957 } 5958 if (!desc) { 5959 desc = g_strdup_printf("%s", model_id); 5960 } 5961 5962 if (cc->model && cc->model->cpudef->deprecation_note) { 5963 g_autofree char *olddesc = desc; 5964 desc = g_strdup_printf("%s (deprecated)", olddesc); 5965 } 5966 5967 qemu_printf(" %-20s %s\n", name, desc); 5968 } 5969 5970 /* list available CPU models and flags */ 5971 void x86_cpu_list(void) 5972 { 5973 int i, j; 5974 GSList *list; 5975 GList *names = NULL; 5976 5977 qemu_printf("Available CPUs:\n"); 5978 list = get_sorted_cpu_model_list(); 5979 g_slist_foreach(list, x86_cpu_list_entry, NULL); 5980 g_slist_free(list); 5981 5982 names = NULL; 5983 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 5984 FeatureWordInfo *fw = &feature_word_info[i]; 5985 for (j = 0; j < 64; j++) { 5986 if (fw->feat_names[j]) { 5987 names = g_list_append(names, (gpointer)fw->feat_names[j]); 5988 } 5989 } 5990 } 5991 5992 names = g_list_sort(names, (GCompareFunc)strcmp); 5993 5994 qemu_printf("\nRecognized CPUID flags:\n"); 5995 listflags(names); 5996 qemu_printf("\n"); 5997 g_list_free(names); 5998 } 5999 6000 #ifndef CONFIG_USER_ONLY 6001 6002 /* Check for missing features that may prevent the CPU class from 6003 * running using the current machine and accelerator. 6004 */ 6005 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 6006 strList **list) 6007 { 6008 strList **tail = list; 6009 X86CPU *xc; 6010 Error *err = NULL; 6011 6012 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 6013 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 6014 return; 6015 } 6016 6017 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 6018 6019 x86_cpu_expand_features(xc, &err); 6020 if (err) { 6021 /* Errors at x86_cpu_expand_features should never happen, 6022 * but in case it does, just report the model as not 6023 * runnable at all using the "type" property. 6024 */ 6025 QAPI_LIST_APPEND(tail, g_strdup("type")); 6026 error_free(err); 6027 } 6028 6029 x86_cpu_filter_features(xc, false); 6030 6031 x86_cpu_list_feature_names(xc->filtered_features, tail); 6032 6033 object_unref(OBJECT(xc)); 6034 } 6035 6036 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 6037 { 6038 ObjectClass *oc = data; 6039 X86CPUClass *cc = X86_CPU_CLASS(oc); 6040 CpuDefinitionInfoList **cpu_list = user_data; 6041 CpuDefinitionInfo *info; 6042 6043 info = g_malloc0(sizeof(*info)); 6044 info->name = x86_cpu_class_get_model_name(cc); 6045 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 6046 info->has_unavailable_features = true; 6047 info->q_typename = g_strdup(object_class_get_name(oc)); 6048 info->migration_safe = cc->migration_safe; 6049 info->has_migration_safe = true; 6050 info->q_static = cc->static_model; 6051 if (cc->model && cc->model->cpudef->deprecation_note) { 6052 info->deprecated = true; 6053 } else { 6054 info->deprecated = false; 6055 } 6056 /* 6057 * Old machine types won't report aliases, so that alias translation 6058 * doesn't break compatibility with previous QEMU versions. 6059 */ 6060 if (default_cpu_version != CPU_VERSION_LEGACY) { 6061 info->alias_of = x86_cpu_class_get_alias_of(cc); 6062 } 6063 6064 QAPI_LIST_PREPEND(*cpu_list, info); 6065 } 6066 6067 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 6068 { 6069 CpuDefinitionInfoList *cpu_list = NULL; 6070 GSList *list = get_sorted_cpu_model_list(); 6071 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 6072 g_slist_free(list); 6073 return cpu_list; 6074 } 6075 6076 #endif /* !CONFIG_USER_ONLY */ 6077 6078 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) 6079 { 6080 FeatureWordInfo *wi = &feature_word_info[w]; 6081 uint64_t r = 0; 6082 uint64_t unavail = 0; 6083 6084 if (kvm_enabled()) { 6085 switch (wi->type) { 6086 case CPUID_FEATURE_WORD: 6087 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 6088 wi->cpuid.ecx, 6089 wi->cpuid.reg); 6090 break; 6091 case MSR_FEATURE_WORD: 6092 r = kvm_arch_get_supported_msr_feature(kvm_state, 6093 wi->msr.index); 6094 break; 6095 } 6096 } else if (hvf_enabled()) { 6097 if (wi->type != CPUID_FEATURE_WORD) { 6098 return 0; 6099 } 6100 r = hvf_get_supported_cpuid(wi->cpuid.eax, 6101 wi->cpuid.ecx, 6102 wi->cpuid.reg); 6103 } else if (tcg_enabled()) { 6104 r = wi->tcg_features; 6105 } else { 6106 return ~0; 6107 } 6108 6109 switch (w) { 6110 #ifndef TARGET_X86_64 6111 case FEAT_8000_0001_EDX: 6112 /* 6113 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 6114 * way for userspace to get out of its 32-bit jail, we can leave 6115 * the LM bit set. 6116 */ 6117 unavail = tcg_enabled() 6118 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 6119 : CPUID_EXT2_LM; 6120 break; 6121 #endif 6122 6123 case FEAT_8000_0007_EBX: 6124 if (cpu && !IS_AMD_CPU(&cpu->env)) { 6125 /* Disable AMD machine check architecture for Intel CPU. */ 6126 unavail = ~0; 6127 } 6128 break; 6129 6130 case FEAT_7_0_EBX: 6131 #ifndef CONFIG_USER_ONLY 6132 if (!check_sgx_support()) { 6133 unavail = CPUID_7_0_EBX_SGX; 6134 } 6135 #endif 6136 break; 6137 case FEAT_7_0_ECX: 6138 #ifndef CONFIG_USER_ONLY 6139 if (!check_sgx_support()) { 6140 unavail = CPUID_7_0_ECX_SGX_LC; 6141 } 6142 #endif 6143 break; 6144 6145 default: 6146 break; 6147 } 6148 6149 r &= ~unavail; 6150 if (cpu && cpu->migratable) { 6151 r &= x86_cpu_get_migratable_flags(cpu, w); 6152 } 6153 return r; 6154 } 6155 6156 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 6157 uint32_t *eax, uint32_t *ebx, 6158 uint32_t *ecx, uint32_t *edx) 6159 { 6160 if (kvm_enabled()) { 6161 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 6162 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 6163 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 6164 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 6165 } else if (hvf_enabled()) { 6166 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 6167 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 6168 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 6169 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 6170 } else { 6171 *eax = 0; 6172 *ebx = 0; 6173 *ecx = 0; 6174 *edx = 0; 6175 } 6176 } 6177 6178 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 6179 uint32_t *eax, uint32_t *ebx, 6180 uint32_t *ecx, uint32_t *edx) 6181 { 6182 uint32_t level, unused; 6183 6184 /* Only return valid host leaves. */ 6185 switch (func) { 6186 case 2: 6187 case 4: 6188 host_cpuid(0, 0, &level, &unused, &unused, &unused); 6189 break; 6190 case 0x80000005: 6191 case 0x80000006: 6192 case 0x8000001d: 6193 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 6194 break; 6195 default: 6196 return; 6197 } 6198 6199 if (func > level) { 6200 *eax = 0; 6201 *ebx = 0; 6202 *ecx = 0; 6203 *edx = 0; 6204 } else { 6205 host_cpuid(func, index, eax, ebx, ecx, edx); 6206 } 6207 } 6208 6209 /* 6210 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6211 */ 6212 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 6213 { 6214 PropValue *pv; 6215 for (pv = props; pv->prop; pv++) { 6216 if (!pv->value) { 6217 continue; 6218 } 6219 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 6220 &error_abort); 6221 } 6222 } 6223 6224 /* 6225 * Apply properties for the CPU model version specified in model. 6226 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6227 */ 6228 6229 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 6230 { 6231 const X86CPUVersionDefinition *vdef; 6232 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6233 6234 if (version == CPU_VERSION_LEGACY) { 6235 return; 6236 } 6237 6238 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6239 PropValue *p; 6240 6241 for (p = vdef->props; p && p->prop; p++) { 6242 object_property_parse(OBJECT(cpu), p->prop, p->value, 6243 &error_abort); 6244 } 6245 6246 if (vdef->version == version) { 6247 break; 6248 } 6249 } 6250 6251 /* 6252 * If we reached the end of the list, version number was invalid 6253 */ 6254 assert(vdef->version == version); 6255 } 6256 6257 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 6258 X86CPUModel *model) 6259 { 6260 const X86CPUVersionDefinition *vdef; 6261 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6262 const CPUCaches *cache_info = model->cpudef->cache_info; 6263 6264 if (version == CPU_VERSION_LEGACY) { 6265 return cache_info; 6266 } 6267 6268 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6269 if (vdef->cache_info) { 6270 cache_info = vdef->cache_info; 6271 } 6272 6273 if (vdef->version == version) { 6274 break; 6275 } 6276 } 6277 6278 assert(vdef->version == version); 6279 return cache_info; 6280 } 6281 6282 /* 6283 * Load data from X86CPUDefinition into a X86CPU object. 6284 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6285 */ 6286 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 6287 { 6288 const X86CPUDefinition *def = model->cpudef; 6289 CPUX86State *env = &cpu->env; 6290 FeatureWord w; 6291 6292 /*NOTE: any property set by this function should be returned by 6293 * x86_cpu_static_props(), so static expansion of 6294 * query-cpu-model-expansion is always complete. 6295 */ 6296 6297 /* CPU models only set _minimum_ values for level/xlevel: */ 6298 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 6299 &error_abort); 6300 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 6301 &error_abort); 6302 6303 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 6304 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 6305 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 6306 &error_abort); 6307 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 6308 &error_abort); 6309 for (w = 0; w < FEATURE_WORDS; w++) { 6310 env->features[w] = def->features[w]; 6311 } 6312 6313 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 6314 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 6315 6316 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 6317 6318 /* sysenter isn't supported in compatibility mode on AMD, 6319 * syscall isn't supported in compatibility mode on Intel. 6320 * Normally we advertise the actual CPU vendor, but you can 6321 * override this using the 'vendor' property if you want to use 6322 * KVM's sysenter/syscall emulation in compatibility mode and 6323 * when doing cross vendor migration 6324 */ 6325 6326 /* 6327 * vendor property is set here but then overloaded with the 6328 * host cpu vendor for KVM and HVF. 6329 */ 6330 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 6331 6332 x86_cpu_apply_version_props(cpu, model); 6333 6334 /* 6335 * Properties in versioned CPU model are not user specified features. 6336 * We can simply clear env->user_features here since it will be filled later 6337 * in x86_cpu_expand_features() based on plus_features and minus_features. 6338 */ 6339 memset(&env->user_features, 0, sizeof(env->user_features)); 6340 } 6341 6342 static const gchar *x86_gdb_arch_name(CPUState *cs) 6343 { 6344 #ifdef TARGET_X86_64 6345 return "i386:x86-64"; 6346 #else 6347 return "i386"; 6348 #endif 6349 } 6350 6351 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 6352 { 6353 X86CPUModel *model = data; 6354 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6355 CPUClass *cc = CPU_CLASS(oc); 6356 6357 xcc->model = model; 6358 xcc->migration_safe = true; 6359 cc->deprecation_note = model->cpudef->deprecation_note; 6360 } 6361 6362 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 6363 { 6364 g_autofree char *typename = x86_cpu_type_name(name); 6365 TypeInfo ti = { 6366 .name = typename, 6367 .parent = TYPE_X86_CPU, 6368 .class_init = x86_cpu_cpudef_class_init, 6369 .class_data = model, 6370 }; 6371 6372 type_register(&ti); 6373 } 6374 6375 6376 /* 6377 * register builtin_x86_defs; 6378 * "max", "base" and subclasses ("host") are not registered here. 6379 * See x86_cpu_register_types for all model registrations. 6380 */ 6381 static void x86_register_cpudef_types(const X86CPUDefinition *def) 6382 { 6383 X86CPUModel *m; 6384 const X86CPUVersionDefinition *vdef; 6385 6386 /* AMD aliases are handled at runtime based on CPUID vendor, so 6387 * they shouldn't be set on the CPU model table. 6388 */ 6389 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 6390 /* catch mistakes instead of silently truncating model_id when too long */ 6391 assert(def->model_id && strlen(def->model_id) <= 48); 6392 6393 /* Unversioned model: */ 6394 m = g_new0(X86CPUModel, 1); 6395 m->cpudef = def; 6396 m->version = CPU_VERSION_AUTO; 6397 m->is_alias = true; 6398 x86_register_cpu_model_type(def->name, m); 6399 6400 /* Versioned models: */ 6401 6402 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 6403 g_autofree char *name = 6404 x86_cpu_versioned_model_name(def, vdef->version); 6405 6406 m = g_new0(X86CPUModel, 1); 6407 m->cpudef = def; 6408 m->version = vdef->version; 6409 m->note = vdef->note; 6410 x86_register_cpu_model_type(name, m); 6411 6412 if (vdef->alias) { 6413 X86CPUModel *am = g_new0(X86CPUModel, 1); 6414 am->cpudef = def; 6415 am->version = vdef->version; 6416 am->is_alias = true; 6417 x86_register_cpu_model_type(vdef->alias, am); 6418 } 6419 } 6420 6421 } 6422 6423 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6424 { 6425 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6426 return 57; /* 57 bits virtual */ 6427 } else { 6428 return 48; /* 48 bits virtual */ 6429 } 6430 } 6431 6432 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6433 uint32_t *eax, uint32_t *ebx, 6434 uint32_t *ecx, uint32_t *edx) 6435 { 6436 X86CPU *cpu = env_archcpu(env); 6437 CPUState *cs = env_cpu(env); 6438 uint32_t limit; 6439 uint32_t signature[3]; 6440 X86CPUTopoInfo topo_info; 6441 uint32_t cores_per_pkg; 6442 uint32_t threads_per_pkg; 6443 6444 topo_info.dies_per_pkg = env->nr_dies; 6445 topo_info.modules_per_die = env->nr_modules; 6446 topo_info.cores_per_module = cs->nr_cores / env->nr_dies / env->nr_modules; 6447 topo_info.threads_per_core = cs->nr_threads; 6448 6449 cores_per_pkg = topo_info.cores_per_module * topo_info.modules_per_die * 6450 topo_info.dies_per_pkg; 6451 threads_per_pkg = cores_per_pkg * topo_info.threads_per_core; 6452 6453 /* Calculate & apply limits for different index ranges */ 6454 if (index >= 0xC0000000) { 6455 limit = env->cpuid_xlevel2; 6456 } else if (index >= 0x80000000) { 6457 limit = env->cpuid_xlevel; 6458 } else if (index >= 0x40000000) { 6459 limit = 0x40000001; 6460 } else { 6461 limit = env->cpuid_level; 6462 } 6463 6464 if (index > limit) { 6465 /* Intel documentation states that invalid EAX input will 6466 * return the same information as EAX=cpuid_level 6467 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6468 */ 6469 index = env->cpuid_level; 6470 } 6471 6472 switch(index) { 6473 case 0: 6474 *eax = env->cpuid_level; 6475 *ebx = env->cpuid_vendor1; 6476 *edx = env->cpuid_vendor2; 6477 *ecx = env->cpuid_vendor3; 6478 break; 6479 case 1: 6480 *eax = env->cpuid_version; 6481 *ebx = (cpu->apic_id << 24) | 6482 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6483 *ecx = env->features[FEAT_1_ECX]; 6484 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6485 *ecx |= CPUID_EXT_OSXSAVE; 6486 } 6487 *edx = env->features[FEAT_1_EDX]; 6488 if (threads_per_pkg > 1) { 6489 *ebx |= threads_per_pkg << 16; 6490 *edx |= CPUID_HT; 6491 } 6492 if (!cpu->enable_pmu) { 6493 *ecx &= ~CPUID_EXT_PDCM; 6494 } 6495 break; 6496 case 2: 6497 /* cache info: needed for Pentium Pro compatibility */ 6498 if (cpu->cache_info_passthrough) { 6499 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6500 break; 6501 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6502 *eax = *ebx = *ecx = *edx = 0; 6503 break; 6504 } 6505 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6506 *ebx = 0; 6507 if (!cpu->enable_l3_cache) { 6508 *ecx = 0; 6509 } else { 6510 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6511 } 6512 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6513 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6514 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6515 break; 6516 case 4: 6517 /* cache info: needed for Core compatibility */ 6518 if (cpu->cache_info_passthrough) { 6519 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6520 /* 6521 * QEMU has its own number of cores/logical cpus, 6522 * set 24..14, 31..26 bit to configured values 6523 */ 6524 if (*eax & 31) { 6525 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6526 6527 *eax &= ~0xFC000000; 6528 *eax |= max_core_ids_in_package(&topo_info) << 26; 6529 if (host_vcpus_per_cache > threads_per_pkg) { 6530 *eax &= ~0x3FFC000; 6531 6532 /* Share the cache at package level. */ 6533 *eax |= max_thread_ids_for_cache(&topo_info, 6534 CPU_TOPO_LEVEL_PACKAGE) << 14; 6535 } 6536 } 6537 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6538 *eax = *ebx = *ecx = *edx = 0; 6539 } else { 6540 *eax = 0; 6541 6542 switch (count) { 6543 case 0: /* L1 dcache info */ 6544 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6545 &topo_info, 6546 eax, ebx, ecx, edx); 6547 if (!cpu->l1_cache_per_core) { 6548 *eax &= ~MAKE_64BIT_MASK(14, 12); 6549 } 6550 break; 6551 case 1: /* L1 icache info */ 6552 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6553 &topo_info, 6554 eax, ebx, ecx, edx); 6555 if (!cpu->l1_cache_per_core) { 6556 *eax &= ~MAKE_64BIT_MASK(14, 12); 6557 } 6558 break; 6559 case 2: /* L2 cache info */ 6560 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6561 &topo_info, 6562 eax, ebx, ecx, edx); 6563 break; 6564 case 3: /* L3 cache info */ 6565 if (cpu->enable_l3_cache) { 6566 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6567 &topo_info, 6568 eax, ebx, ecx, edx); 6569 break; 6570 } 6571 /* fall through */ 6572 default: /* end of info */ 6573 *eax = *ebx = *ecx = *edx = 0; 6574 break; 6575 } 6576 } 6577 break; 6578 case 5: 6579 /* MONITOR/MWAIT Leaf */ 6580 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6581 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6582 *ecx = cpu->mwait.ecx; /* flags */ 6583 *edx = cpu->mwait.edx; /* mwait substates */ 6584 break; 6585 case 6: 6586 /* Thermal and Power Leaf */ 6587 *eax = env->features[FEAT_6_EAX]; 6588 *ebx = 0; 6589 *ecx = 0; 6590 *edx = 0; 6591 break; 6592 case 7: 6593 /* Structured Extended Feature Flags Enumeration Leaf */ 6594 if (count == 0) { 6595 /* Maximum ECX value for sub-leaves */ 6596 *eax = env->cpuid_level_func7; 6597 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 6598 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 6599 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 6600 *ecx |= CPUID_7_0_ECX_OSPKE; 6601 } 6602 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 6603 } else if (count == 1) { 6604 *eax = env->features[FEAT_7_1_EAX]; 6605 *edx = env->features[FEAT_7_1_EDX]; 6606 *ebx = 0; 6607 *ecx = 0; 6608 } else if (count == 2) { 6609 *edx = env->features[FEAT_7_2_EDX]; 6610 *eax = 0; 6611 *ebx = 0; 6612 *ecx = 0; 6613 } else { 6614 *eax = 0; 6615 *ebx = 0; 6616 *ecx = 0; 6617 *edx = 0; 6618 } 6619 break; 6620 case 9: 6621 /* Direct Cache Access Information Leaf */ 6622 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6623 *ebx = 0; 6624 *ecx = 0; 6625 *edx = 0; 6626 break; 6627 case 0xA: 6628 /* Architectural Performance Monitoring Leaf */ 6629 if (cpu->enable_pmu) { 6630 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 6631 } else { 6632 *eax = 0; 6633 *ebx = 0; 6634 *ecx = 0; 6635 *edx = 0; 6636 } 6637 break; 6638 case 0xB: 6639 /* Extended Topology Enumeration Leaf */ 6640 if (!cpu->enable_cpuid_0xb) { 6641 *eax = *ebx = *ecx = *edx = 0; 6642 break; 6643 } 6644 6645 *ecx = count & 0xff; 6646 *edx = cpu->apic_id; 6647 6648 switch (count) { 6649 case 0: 6650 *eax = apicid_core_offset(&topo_info); 6651 *ebx = topo_info.threads_per_core; 6652 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 6653 break; 6654 case 1: 6655 *eax = apicid_pkg_offset(&topo_info); 6656 *ebx = threads_per_pkg; 6657 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 6658 break; 6659 default: 6660 *eax = 0; 6661 *ebx = 0; 6662 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 6663 } 6664 6665 assert(!(*eax & ~0x1f)); 6666 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6667 break; 6668 case 0x1C: 6669 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6670 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 6671 *edx = 0; 6672 } 6673 break; 6674 case 0x1F: 6675 /* V2 Extended Topology Enumeration Leaf */ 6676 if (!x86_has_extended_topo(env->avail_cpu_topo)) { 6677 *eax = *ebx = *ecx = *edx = 0; 6678 break; 6679 } 6680 6681 encode_topo_cpuid1f(env, count, &topo_info, eax, ebx, ecx, edx); 6682 break; 6683 case 0xD: { 6684 /* Processor Extended State */ 6685 *eax = 0; 6686 *ebx = 0; 6687 *ecx = 0; 6688 *edx = 0; 6689 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6690 break; 6691 } 6692 6693 if (count == 0) { 6694 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 6695 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 6696 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 6697 /* 6698 * The initial value of xcr0 and ebx == 0, On host without kvm 6699 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 6700 * even through guest update xcr0, this will crash some legacy guest 6701 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 6702 */ 6703 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 6704 } else if (count == 1) { 6705 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 6706 x86_cpu_xsave_xss_components(cpu); 6707 6708 *eax = env->features[FEAT_XSAVE]; 6709 *ebx = xsave_area_size(xstate, true); 6710 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 6711 *edx = env->features[FEAT_XSAVE_XSS_HI]; 6712 if (kvm_enabled() && cpu->enable_pmu && 6713 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 6714 (*eax & CPUID_XSAVE_XSAVES)) { 6715 *ecx |= XSTATE_ARCH_LBR_MASK; 6716 } else { 6717 *ecx &= ~XSTATE_ARCH_LBR_MASK; 6718 } 6719 } else if (count == 0xf && cpu->enable_pmu 6720 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6721 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 6722 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 6723 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 6724 6725 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 6726 *eax = esa->size; 6727 *ebx = esa->offset; 6728 *ecx = esa->ecx & 6729 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 6730 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 6731 *eax = esa->size; 6732 *ebx = 0; 6733 *ecx = 1; 6734 } 6735 } 6736 break; 6737 } 6738 case 0x12: 6739 #ifndef CONFIG_USER_ONLY 6740 if (!kvm_enabled() || 6741 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 6742 *eax = *ebx = *ecx = *edx = 0; 6743 break; 6744 } 6745 6746 /* 6747 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 6748 * the EPC properties, e.g. confidentiality and integrity, from the 6749 * host's first EPC section, i.e. assume there is one EPC section or 6750 * that all EPC sections have the same security properties. 6751 */ 6752 if (count > 1) { 6753 uint64_t epc_addr, epc_size; 6754 6755 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 6756 *eax = *ebx = *ecx = *edx = 0; 6757 break; 6758 } 6759 host_cpuid(index, 2, eax, ebx, ecx, edx); 6760 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 6761 *ebx = (uint32_t)(epc_addr >> 32); 6762 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 6763 *edx = (uint32_t)(epc_size >> 32); 6764 break; 6765 } 6766 6767 /* 6768 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 6769 * and KVM, i.e. QEMU cannot emulate features to override what KVM 6770 * supports. Features can be further restricted by userspace, but not 6771 * made more permissive. 6772 */ 6773 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 6774 6775 if (count == 0) { 6776 *eax &= env->features[FEAT_SGX_12_0_EAX]; 6777 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 6778 } else { 6779 *eax &= env->features[FEAT_SGX_12_1_EAX]; 6780 *ebx &= 0; /* ebx reserve */ 6781 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 6782 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 6783 6784 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 6785 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 6786 6787 /* Access to PROVISIONKEY requires additional credentials. */ 6788 if ((*eax & (1U << 4)) && 6789 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 6790 *eax &= ~(1U << 4); 6791 } 6792 } 6793 #endif 6794 break; 6795 case 0x14: { 6796 /* Intel Processor Trace Enumeration */ 6797 *eax = 0; 6798 *ebx = 0; 6799 *ecx = 0; 6800 *edx = 0; 6801 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 6802 !kvm_enabled()) { 6803 break; 6804 } 6805 6806 /* 6807 * If these are changed, they should stay in sync with 6808 * x86_cpu_filter_features(). 6809 */ 6810 if (count == 0) { 6811 *eax = INTEL_PT_MAX_SUBLEAF; 6812 *ebx = INTEL_PT_MINIMAL_EBX; 6813 *ecx = INTEL_PT_MINIMAL_ECX; 6814 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 6815 *ecx |= CPUID_14_0_ECX_LIP; 6816 } 6817 } else if (count == 1) { 6818 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 6819 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 6820 } 6821 break; 6822 } 6823 case 0x1D: { 6824 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 6825 *eax = 0; 6826 *ebx = 0; 6827 *ecx = 0; 6828 *edx = 0; 6829 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6830 break; 6831 } 6832 6833 if (count == 0) { 6834 /* Highest numbered palette subleaf */ 6835 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 6836 } else if (count == 1) { 6837 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 6838 (INTEL_AMX_BYTES_PER_TILE << 16); 6839 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 6840 *ecx = INTEL_AMX_TILE_MAX_ROWS; 6841 } 6842 break; 6843 } 6844 case 0x1E: { 6845 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 6846 *eax = 0; 6847 *ebx = 0; 6848 *ecx = 0; 6849 *edx = 0; 6850 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6851 break; 6852 } 6853 6854 if (count == 0) { 6855 /* Highest numbered palette subleaf */ 6856 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 6857 } 6858 break; 6859 } 6860 case 0x40000000: 6861 /* 6862 * CPUID code in kvm_arch_init_vcpu() ignores stuff 6863 * set here, but we restrict to TCG none the less. 6864 */ 6865 if (tcg_enabled() && cpu->expose_tcg) { 6866 memcpy(signature, "TCGTCGTCGTCG", 12); 6867 *eax = 0x40000001; 6868 *ebx = signature[0]; 6869 *ecx = signature[1]; 6870 *edx = signature[2]; 6871 } else { 6872 *eax = 0; 6873 *ebx = 0; 6874 *ecx = 0; 6875 *edx = 0; 6876 } 6877 break; 6878 case 0x40000001: 6879 *eax = 0; 6880 *ebx = 0; 6881 *ecx = 0; 6882 *edx = 0; 6883 break; 6884 case 0x80000000: 6885 *eax = env->cpuid_xlevel; 6886 *ebx = env->cpuid_vendor1; 6887 *edx = env->cpuid_vendor2; 6888 *ecx = env->cpuid_vendor3; 6889 break; 6890 case 0x80000001: 6891 *eax = env->cpuid_version; 6892 *ebx = 0; 6893 *ecx = env->features[FEAT_8000_0001_ECX]; 6894 *edx = env->features[FEAT_8000_0001_EDX]; 6895 6896 /* The Linux kernel checks for the CMPLegacy bit and 6897 * discards multiple thread information if it is set. 6898 * So don't set it here for Intel to make Linux guests happy. 6899 */ 6900 if (threads_per_pkg > 1) { 6901 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 6902 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 6903 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 6904 *ecx |= 1 << 1; /* CmpLegacy bit */ 6905 } 6906 } 6907 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 6908 !(env->hflags & HF_LMA_MASK)) { 6909 *edx &= ~CPUID_EXT2_SYSCALL; 6910 } 6911 break; 6912 case 0x80000002: 6913 case 0x80000003: 6914 case 0x80000004: 6915 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 6916 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 6917 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 6918 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 6919 break; 6920 case 0x80000005: 6921 /* cache info (L1 cache) */ 6922 if (cpu->cache_info_passthrough) { 6923 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6924 break; 6925 } 6926 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 6927 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 6928 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 6929 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 6930 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 6931 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 6932 break; 6933 case 0x80000006: 6934 /* cache info (L2 cache) */ 6935 if (cpu->cache_info_passthrough) { 6936 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6937 break; 6938 } 6939 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 6940 (L2_DTLB_2M_ENTRIES << 16) | 6941 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 6942 (L2_ITLB_2M_ENTRIES); 6943 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 6944 (L2_DTLB_4K_ENTRIES << 16) | 6945 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 6946 (L2_ITLB_4K_ENTRIES); 6947 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 6948 cpu->enable_l3_cache ? 6949 env->cache_info_amd.l3_cache : NULL, 6950 ecx, edx); 6951 break; 6952 case 0x80000007: 6953 *eax = 0; 6954 *ebx = env->features[FEAT_8000_0007_EBX]; 6955 *ecx = 0; 6956 *edx = env->features[FEAT_8000_0007_EDX]; 6957 break; 6958 case 0x80000008: 6959 /* virtual & phys address size in low 2 bytes. */ 6960 *eax = cpu->phys_bits; 6961 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6962 /* 64 bit processor */ 6963 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 6964 *eax |= (cpu->guest_phys_bits << 16); 6965 } 6966 *ebx = env->features[FEAT_8000_0008_EBX]; 6967 if (threads_per_pkg > 1) { 6968 /* 6969 * Bits 15:12 is "The number of bits in the initial 6970 * Core::X86::Apic::ApicId[ApicId] value that indicate 6971 * thread ID within a package". 6972 * Bits 7:0 is "The number of threads in the package is NC+1" 6973 */ 6974 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 6975 (threads_per_pkg - 1); 6976 } else { 6977 *ecx = 0; 6978 } 6979 *edx = 0; 6980 break; 6981 case 0x8000000A: 6982 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6983 *eax = 0x00000001; /* SVM Revision */ 6984 *ebx = 0x00000010; /* nr of ASIDs */ 6985 *ecx = 0; 6986 *edx = env->features[FEAT_SVM]; /* optional features */ 6987 } else { 6988 *eax = 0; 6989 *ebx = 0; 6990 *ecx = 0; 6991 *edx = 0; 6992 } 6993 break; 6994 case 0x8000001D: 6995 *eax = 0; 6996 if (cpu->cache_info_passthrough) { 6997 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6998 break; 6999 } 7000 switch (count) { 7001 case 0: /* L1 dcache info */ 7002 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 7003 &topo_info, eax, ebx, ecx, edx); 7004 break; 7005 case 1: /* L1 icache info */ 7006 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 7007 &topo_info, eax, ebx, ecx, edx); 7008 break; 7009 case 2: /* L2 cache info */ 7010 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 7011 &topo_info, eax, ebx, ecx, edx); 7012 break; 7013 case 3: /* L3 cache info */ 7014 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 7015 &topo_info, eax, ebx, ecx, edx); 7016 break; 7017 default: /* end of info */ 7018 *eax = *ebx = *ecx = *edx = 0; 7019 break; 7020 } 7021 if (cpu->amd_topoext_features_only) { 7022 *edx &= CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; 7023 } 7024 break; 7025 case 0x8000001E: 7026 if (cpu->core_id <= 255) { 7027 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 7028 } else { 7029 *eax = 0; 7030 *ebx = 0; 7031 *ecx = 0; 7032 *edx = 0; 7033 } 7034 break; 7035 case 0x80000022: 7036 *eax = *ebx = *ecx = *edx = 0; 7037 /* AMD Extended Performance Monitoring and Debug */ 7038 if (kvm_enabled() && cpu->enable_pmu && 7039 (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) { 7040 *eax |= CPUID_8000_0022_EAX_PERFMON_V2; 7041 *ebx |= kvm_arch_get_supported_cpuid(cs->kvm_state, index, count, 7042 R_EBX) & 0xf; 7043 } 7044 break; 7045 case 0xC0000000: 7046 *eax = env->cpuid_xlevel2; 7047 *ebx = 0; 7048 *ecx = 0; 7049 *edx = 0; 7050 break; 7051 case 0xC0000001: 7052 /* Support for VIA CPU's CPUID instruction */ 7053 *eax = env->cpuid_version; 7054 *ebx = 0; 7055 *ecx = 0; 7056 *edx = env->features[FEAT_C000_0001_EDX]; 7057 break; 7058 case 0xC0000002: 7059 case 0xC0000003: 7060 case 0xC0000004: 7061 /* Reserved for the future, and now filled with zero */ 7062 *eax = 0; 7063 *ebx = 0; 7064 *ecx = 0; 7065 *edx = 0; 7066 break; 7067 case 0x8000001F: 7068 *eax = *ebx = *ecx = *edx = 0; 7069 if (sev_enabled()) { 7070 *eax = 0x2; 7071 *eax |= sev_es_enabled() ? 0x8 : 0; 7072 *eax |= sev_snp_enabled() ? 0x10 : 0; 7073 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 7074 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 7075 } 7076 break; 7077 case 0x80000021: 7078 *eax = *ebx = *ecx = *edx = 0; 7079 *eax = env->features[FEAT_8000_0021_EAX]; 7080 *ebx = env->features[FEAT_8000_0021_EBX]; 7081 break; 7082 default: 7083 /* reserved values: zero */ 7084 *eax = 0; 7085 *ebx = 0; 7086 *ecx = 0; 7087 *edx = 0; 7088 break; 7089 } 7090 } 7091 7092 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 7093 { 7094 #ifndef CONFIG_USER_ONLY 7095 /* Those default values are defined in Skylake HW */ 7096 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 7097 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 7098 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 7099 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 7100 #endif 7101 } 7102 7103 static void x86_cpu_reset_hold(Object *obj, ResetType type) 7104 { 7105 CPUState *cs = CPU(obj); 7106 X86CPU *cpu = X86_CPU(cs); 7107 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7108 CPUX86State *env = &cpu->env; 7109 target_ulong cr4; 7110 uint64_t xcr0; 7111 int i; 7112 7113 if (xcc->parent_phases.hold) { 7114 xcc->parent_phases.hold(obj, type); 7115 } 7116 7117 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 7118 7119 env->old_exception = -1; 7120 7121 /* init to reset state */ 7122 env->int_ctl = 0; 7123 env->hflags2 |= HF2_GIF_MASK; 7124 env->hflags2 |= HF2_VGIF_MASK; 7125 env->hflags &= ~HF_GUEST_MASK; 7126 7127 cpu_x86_update_cr0(env, 0x60000010); 7128 env->a20_mask = ~0x0; 7129 env->smbase = 0x30000; 7130 env->msr_smi_count = 0; 7131 7132 env->idt.limit = 0xffff; 7133 env->gdt.limit = 0xffff; 7134 env->ldt.limit = 0xffff; 7135 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 7136 env->tr.limit = 0xffff; 7137 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 7138 7139 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 7140 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 7141 DESC_R_MASK | DESC_A_MASK); 7142 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 7143 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7144 DESC_A_MASK); 7145 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 7146 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7147 DESC_A_MASK); 7148 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 7149 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7150 DESC_A_MASK); 7151 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 7152 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7153 DESC_A_MASK); 7154 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 7155 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7156 DESC_A_MASK); 7157 7158 env->eip = 0xfff0; 7159 env->regs[R_EDX] = env->cpuid_version; 7160 7161 env->eflags = 0x2; 7162 7163 /* FPU init */ 7164 for (i = 0; i < 8; i++) { 7165 env->fptags[i] = 1; 7166 } 7167 cpu_set_fpuc(env, 0x37f); 7168 7169 env->mxcsr = 0x1f80; 7170 /* All units are in INIT state. */ 7171 env->xstate_bv = 0; 7172 7173 env->pat = 0x0007040600070406ULL; 7174 7175 if (kvm_enabled()) { 7176 /* 7177 * KVM handles TSC = 0 specially and thinks we are hot-plugging 7178 * a new CPU, use 1 instead to force a reset. 7179 */ 7180 if (env->tsc != 0) { 7181 env->tsc = 1; 7182 } 7183 } else { 7184 env->tsc = 0; 7185 } 7186 7187 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 7188 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 7189 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 7190 } 7191 7192 memset(env->dr, 0, sizeof(env->dr)); 7193 env->dr[6] = DR6_FIXED_1; 7194 env->dr[7] = DR7_FIXED_1; 7195 cpu_breakpoint_remove_all(cs, BP_CPU); 7196 cpu_watchpoint_remove_all(cs, BP_CPU); 7197 7198 cr4 = 0; 7199 xcr0 = XSTATE_FP_MASK; 7200 7201 #ifdef CONFIG_USER_ONLY 7202 /* Enable all the features for user-mode. */ 7203 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 7204 xcr0 |= XSTATE_SSE_MASK; 7205 } 7206 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7207 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7208 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 7209 continue; 7210 } 7211 if (env->features[esa->feature] & esa->bits) { 7212 xcr0 |= 1ull << i; 7213 } 7214 } 7215 7216 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 7217 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 7218 } 7219 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 7220 cr4 |= CR4_FSGSBASE_MASK; 7221 } 7222 #endif 7223 7224 env->xcr0 = xcr0; 7225 cpu_x86_update_cr4(env, cr4); 7226 7227 /* 7228 * SDM 11.11.5 requires: 7229 * - IA32_MTRR_DEF_TYPE MSR.E = 0 7230 * - IA32_MTRR_PHYSMASKn.V = 0 7231 * All other bits are undefined. For simplification, zero it all. 7232 */ 7233 env->mtrr_deftype = 0; 7234 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 7235 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 7236 7237 env->interrupt_injected = -1; 7238 env->exception_nr = -1; 7239 env->exception_pending = 0; 7240 env->exception_injected = 0; 7241 env->exception_has_payload = false; 7242 env->exception_payload = 0; 7243 env->nmi_injected = false; 7244 env->triple_fault_pending = false; 7245 #if !defined(CONFIG_USER_ONLY) 7246 /* We hard-wire the BSP to the first CPU. */ 7247 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 7248 7249 cs->halted = !cpu_is_bsp(cpu); 7250 7251 if (kvm_enabled()) { 7252 kvm_arch_reset_vcpu(cpu); 7253 } 7254 7255 x86_cpu_set_sgxlepubkeyhash(env); 7256 7257 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 7258 7259 #endif 7260 } 7261 7262 void x86_cpu_after_reset(X86CPU *cpu) 7263 { 7264 #ifndef CONFIG_USER_ONLY 7265 if (kvm_enabled()) { 7266 kvm_arch_after_reset_vcpu(cpu); 7267 } 7268 7269 if (cpu->apic_state) { 7270 device_cold_reset(cpu->apic_state); 7271 } 7272 #endif 7273 } 7274 7275 static void mce_init(X86CPU *cpu) 7276 { 7277 CPUX86State *cenv = &cpu->env; 7278 unsigned int bank; 7279 7280 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 7281 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 7282 (CPUID_MCE | CPUID_MCA)) { 7283 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 7284 (cpu->enable_lmce ? MCG_LMCE_P : 0); 7285 cenv->mcg_ctl = ~(uint64_t)0; 7286 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 7287 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 7288 } 7289 } 7290 } 7291 7292 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 7293 { 7294 if (*min < value) { 7295 *min = value; 7296 } 7297 } 7298 7299 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 7300 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 7301 { 7302 CPUX86State *env = &cpu->env; 7303 FeatureWordInfo *fi = &feature_word_info[w]; 7304 uint32_t eax = fi->cpuid.eax; 7305 uint32_t region = eax & 0xF0000000; 7306 7307 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 7308 if (!env->features[w]) { 7309 return; 7310 } 7311 7312 switch (region) { 7313 case 0x00000000: 7314 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 7315 break; 7316 case 0x80000000: 7317 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 7318 break; 7319 case 0xC0000000: 7320 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 7321 break; 7322 } 7323 7324 if (eax == 7) { 7325 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 7326 fi->cpuid.ecx); 7327 } 7328 } 7329 7330 /* Calculate XSAVE components based on the configured CPU feature flags */ 7331 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 7332 { 7333 CPUX86State *env = &cpu->env; 7334 int i; 7335 uint64_t mask; 7336 static bool request_perm; 7337 7338 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7339 env->features[FEAT_XSAVE_XCR0_LO] = 0; 7340 env->features[FEAT_XSAVE_XCR0_HI] = 0; 7341 env->features[FEAT_XSAVE_XSS_LO] = 0; 7342 env->features[FEAT_XSAVE_XSS_HI] = 0; 7343 return; 7344 } 7345 7346 mask = 0; 7347 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7348 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7349 if (env->features[esa->feature] & esa->bits) { 7350 mask |= (1ULL << i); 7351 } 7352 } 7353 7354 /* Only request permission for first vcpu */ 7355 if (kvm_enabled() && !request_perm) { 7356 kvm_request_xsave_components(cpu, mask); 7357 request_perm = true; 7358 } 7359 7360 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 7361 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 7362 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 7363 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 7364 } 7365 7366 /***** Steps involved on loading and filtering CPUID data 7367 * 7368 * When initializing and realizing a CPU object, the steps 7369 * involved in setting up CPUID data are: 7370 * 7371 * 1) Loading CPU model definition (X86CPUDefinition). This is 7372 * implemented by x86_cpu_load_model() and should be completely 7373 * transparent, as it is done automatically by instance_init. 7374 * No code should need to look at X86CPUDefinition structs 7375 * outside instance_init. 7376 * 7377 * 2) CPU expansion. This is done by realize before CPUID 7378 * filtering, and will make sure host/accelerator data is 7379 * loaded for CPU models that depend on host capabilities 7380 * (e.g. "host"). Done by x86_cpu_expand_features(). 7381 * 7382 * 3) CPUID filtering. This initializes extra data related to 7383 * CPUID, and checks if the host supports all capabilities 7384 * required by the CPU. Runnability of a CPU model is 7385 * determined at this step. Done by x86_cpu_filter_features(). 7386 * 7387 * Some operations don't require all steps to be performed. 7388 * More precisely: 7389 * 7390 * - CPU instance creation (instance_init) will run only CPU 7391 * model loading. CPU expansion can't run at instance_init-time 7392 * because host/accelerator data may be not available yet. 7393 * - CPU realization will perform both CPU model expansion and CPUID 7394 * filtering, and return an error in case one of them fails. 7395 * - query-cpu-definitions needs to run all 3 steps. It needs 7396 * to run CPUID filtering, as the 'unavailable-features' 7397 * field is set based on the filtering results. 7398 * - The query-cpu-model-expansion QMP command only needs to run 7399 * CPU model loading and CPU expansion. It should not filter 7400 * any CPUID data based on host capabilities. 7401 */ 7402 7403 /* Expand CPU configuration data, based on configured features 7404 * and host/accelerator capabilities when appropriate. 7405 */ 7406 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 7407 { 7408 CPUX86State *env = &cpu->env; 7409 FeatureWord w; 7410 int i; 7411 GList *l; 7412 7413 for (l = plus_features; l; l = l->next) { 7414 const char *prop = l->data; 7415 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7416 return; 7417 } 7418 } 7419 7420 for (l = minus_features; l; l = l->next) { 7421 const char *prop = l->data; 7422 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7423 return; 7424 } 7425 } 7426 7427 /*TODO: Now cpu->max_features doesn't overwrite features 7428 * set using QOM properties, and we can convert 7429 * plus_features & minus_features to global properties 7430 * inside x86_cpu_parse_featurestr() too. 7431 */ 7432 if (cpu->max_features) { 7433 for (w = 0; w < FEATURE_WORDS; w++) { 7434 /* Override only features that weren't set explicitly 7435 * by the user. 7436 */ 7437 env->features[w] |= 7438 x86_cpu_get_supported_feature_word(cpu, w) & 7439 ~env->user_features[w] & 7440 ~feature_word_info[w].no_autoenable_flags; 7441 } 7442 } 7443 7444 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7445 FeatureDep *d = &feature_dependencies[i]; 7446 if (!(env->features[d->from.index] & d->from.mask)) { 7447 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7448 7449 /* Not an error unless the dependent feature was added explicitly. */ 7450 mark_unavailable_features(cpu, d->to.index, 7451 unavailable_features & env->user_features[d->to.index], 7452 "This feature depends on other features that were not requested"); 7453 7454 env->features[d->to.index] &= ~unavailable_features; 7455 } 7456 } 7457 7458 if (!kvm_enabled() || !cpu->expose_kvm) { 7459 env->features[FEAT_KVM] = 0; 7460 } 7461 7462 x86_cpu_enable_xsave_components(cpu); 7463 7464 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7465 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7466 if (cpu->full_cpuid_auto_level) { 7467 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7468 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7469 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7470 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7471 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7472 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7473 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7474 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7475 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7476 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7477 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7478 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7479 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7480 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7481 7482 /* Intel Processor Trace requires CPUID[0x14] */ 7483 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7484 if (cpu->intel_pt_auto_level) { 7485 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7486 } else if (cpu->env.cpuid_min_level < 0x14) { 7487 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7488 CPUID_7_0_EBX_INTEL_PT, 7489 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7490 } 7491 } 7492 7493 /* 7494 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7495 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7496 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7497 * cpu->vendor_cpuid_only has been unset for compatibility with older 7498 * machine types. 7499 */ 7500 if (x86_has_extended_topo(env->avail_cpu_topo) && 7501 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7502 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7503 } 7504 7505 /* SVM requires CPUID[0x8000000A] */ 7506 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7507 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7508 } 7509 7510 /* SEV requires CPUID[0x8000001F] */ 7511 if (sev_enabled()) { 7512 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7513 } 7514 7515 if (env->features[FEAT_8000_0021_EAX]) { 7516 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7517 } 7518 7519 /* SGX requires CPUID[0x12] for EPC enumeration */ 7520 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7521 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7522 } 7523 } 7524 7525 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7526 if (env->cpuid_level_func7 == UINT32_MAX) { 7527 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7528 } 7529 if (env->cpuid_level == UINT32_MAX) { 7530 env->cpuid_level = env->cpuid_min_level; 7531 } 7532 if (env->cpuid_xlevel == UINT32_MAX) { 7533 env->cpuid_xlevel = env->cpuid_min_xlevel; 7534 } 7535 if (env->cpuid_xlevel2 == UINT32_MAX) { 7536 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7537 } 7538 7539 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7540 return; 7541 } 7542 } 7543 7544 /* 7545 * Finishes initialization of CPUID data, filters CPU feature 7546 * words based on host availability of each feature. 7547 * 7548 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 7549 */ 7550 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 7551 { 7552 CPUX86State *env = &cpu->env; 7553 FeatureWord w; 7554 const char *prefix = NULL; 7555 7556 if (verbose) { 7557 prefix = accel_uses_host_cpuid() 7558 ? "host doesn't support requested feature" 7559 : "TCG doesn't support requested feature"; 7560 } 7561 7562 for (w = 0; w < FEATURE_WORDS; w++) { 7563 uint64_t host_feat = 7564 x86_cpu_get_supported_feature_word(NULL, w); 7565 uint64_t requested_features = env->features[w]; 7566 uint64_t unavailable_features = requested_features & ~host_feat; 7567 mark_unavailable_features(cpu, w, unavailable_features, prefix); 7568 } 7569 7570 /* 7571 * Check that KVM actually allows the processor tracing features that 7572 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 7573 */ 7574 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 7575 kvm_enabled()) { 7576 uint32_t eax_0, ebx_0, ecx_0, edx_0_unused; 7577 uint32_t eax_1, ebx_1, ecx_1_unused, edx_1_unused; 7578 7579 x86_cpu_get_supported_cpuid(0x14, 0, 7580 &eax_0, &ebx_0, &ecx_0, &edx_0_unused); 7581 x86_cpu_get_supported_cpuid(0x14, 1, 7582 &eax_1, &ebx_1, &ecx_1_unused, &edx_1_unused); 7583 7584 if (!eax_0 || 7585 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 7586 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 7587 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 7588 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 7589 INTEL_PT_ADDR_RANGES_NUM) || 7590 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 7591 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 7592 ((ecx_0 & CPUID_14_0_ECX_LIP) != 7593 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 7594 /* 7595 * Processor Trace capabilities aren't configurable, so if the 7596 * host can't emulate the capabilities we report on 7597 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 7598 */ 7599 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 7600 } 7601 } 7602 } 7603 7604 static void x86_cpu_hyperv_realize(X86CPU *cpu) 7605 { 7606 size_t len; 7607 7608 /* Hyper-V vendor id */ 7609 if (!cpu->hyperv_vendor) { 7610 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 7611 &error_abort); 7612 } 7613 len = strlen(cpu->hyperv_vendor); 7614 if (len > 12) { 7615 warn_report("hv-vendor-id truncated to 12 characters"); 7616 len = 12; 7617 } 7618 memset(cpu->hyperv_vendor_id, 0, 12); 7619 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 7620 7621 /* 'Hv#1' interface identification*/ 7622 cpu->hyperv_interface_id[0] = 0x31237648; 7623 cpu->hyperv_interface_id[1] = 0; 7624 cpu->hyperv_interface_id[2] = 0; 7625 cpu->hyperv_interface_id[3] = 0; 7626 7627 /* Hypervisor implementation limits */ 7628 cpu->hyperv_limits[0] = 64; 7629 cpu->hyperv_limits[1] = 0; 7630 cpu->hyperv_limits[2] = 0; 7631 } 7632 7633 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 7634 { 7635 CPUState *cs = CPU(dev); 7636 X86CPU *cpu = X86_CPU(dev); 7637 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7638 CPUX86State *env = &cpu->env; 7639 Error *local_err = NULL; 7640 unsigned requested_lbr_fmt; 7641 7642 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 7643 /* Use pc-relative instructions in system-mode */ 7644 tcg_cflags_set(cs, CF_PCREL); 7645 #endif 7646 7647 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 7648 error_setg(errp, "apic-id property was not initialized properly"); 7649 return; 7650 } 7651 7652 /* 7653 * Process Hyper-V enlightenments. 7654 * Note: this currently has to happen before the expansion of CPU features. 7655 */ 7656 x86_cpu_hyperv_realize(cpu); 7657 7658 x86_cpu_expand_features(cpu, &local_err); 7659 if (local_err) { 7660 goto out; 7661 } 7662 7663 /* 7664 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 7665 * with user-provided setting. 7666 */ 7667 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 7668 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 7669 error_setg(errp, "invalid lbr-fmt"); 7670 return; 7671 } 7672 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 7673 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 7674 } 7675 7676 /* 7677 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 7678 * 3)vPMU LBR format matches that of host setting. 7679 */ 7680 requested_lbr_fmt = 7681 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 7682 if (requested_lbr_fmt && kvm_enabled()) { 7683 uint64_t host_perf_cap = 7684 x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); 7685 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 7686 7687 if (!cpu->enable_pmu) { 7688 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 7689 return; 7690 } 7691 if (requested_lbr_fmt != host_lbr_fmt) { 7692 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 7693 "the host value (0x%x).", 7694 requested_lbr_fmt, host_lbr_fmt); 7695 return; 7696 } 7697 } 7698 7699 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 7700 7701 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 7702 error_setg(&local_err, 7703 accel_uses_host_cpuid() ? 7704 "Host doesn't support requested features" : 7705 "TCG doesn't support requested features"); 7706 goto out; 7707 } 7708 7709 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 7710 * CPUID[1].EDX. 7711 */ 7712 if (IS_AMD_CPU(env)) { 7713 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 7714 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 7715 & CPUID_EXT2_AMD_ALIASES); 7716 } 7717 7718 x86_cpu_set_sgxlepubkeyhash(env); 7719 7720 /* 7721 * note: the call to the framework needs to happen after feature expansion, 7722 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 7723 * These may be set by the accel-specific code, 7724 * and the results are subsequently checked / assumed in this function. 7725 */ 7726 cpu_exec_realizefn(cs, &local_err); 7727 if (local_err != NULL) { 7728 error_propagate(errp, local_err); 7729 return; 7730 } 7731 7732 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 7733 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7734 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 7735 goto out; 7736 } 7737 7738 if (cpu->guest_phys_bits == -1) { 7739 /* 7740 * If it was not set by the user, or by the accelerator via 7741 * cpu_exec_realizefn, clear. 7742 */ 7743 cpu->guest_phys_bits = 0; 7744 } 7745 7746 if (cpu->ucode_rev == 0) { 7747 /* 7748 * The default is the same as KVM's. Note that this check 7749 * needs to happen after the evenual setting of ucode_rev in 7750 * accel-specific code in cpu_exec_realizefn. 7751 */ 7752 if (IS_AMD_CPU(env)) { 7753 cpu->ucode_rev = 0x01000065; 7754 } else { 7755 cpu->ucode_rev = 0x100000000ULL; 7756 } 7757 } 7758 7759 /* 7760 * mwait extended info: needed for Core compatibility 7761 * We always wake on interrupt even if host does not have the capability. 7762 * 7763 * requires the accel-specific code in cpu_exec_realizefn to 7764 * have already acquired the CPUID data into cpu->mwait. 7765 */ 7766 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 7767 7768 /* For 64bit systems think about the number of physical bits to present. 7769 * ideally this should be the same as the host; anything other than matching 7770 * the host can cause incorrect guest behaviour. 7771 * QEMU used to pick the magic value of 40 bits that corresponds to 7772 * consumer AMD devices but nothing else. 7773 * 7774 * Note that this code assumes features expansion has already been done 7775 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 7776 * phys_bits adjustments to match the host have been already done in 7777 * accel-specific code in cpu_exec_realizefn. 7778 */ 7779 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7780 if (cpu->phys_bits && 7781 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 7782 cpu->phys_bits < 32)) { 7783 error_setg(errp, "phys-bits should be between 32 and %u " 7784 " (but is %u)", 7785 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 7786 return; 7787 } 7788 /* 7789 * 0 means it was not explicitly set by the user (or by machine 7790 * compat_props or by the host code in host-cpu.c). 7791 * In this case, the default is the value used by TCG (40). 7792 */ 7793 if (cpu->phys_bits == 0) { 7794 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 7795 } 7796 if (cpu->guest_phys_bits && 7797 (cpu->guest_phys_bits > cpu->phys_bits || 7798 cpu->guest_phys_bits < 32)) { 7799 error_setg(errp, "guest-phys-bits should be between 32 and %u " 7800 " (but is %u)", 7801 cpu->phys_bits, cpu->guest_phys_bits); 7802 return; 7803 } 7804 } else { 7805 /* For 32 bit systems don't use the user set value, but keep 7806 * phys_bits consistent with what we tell the guest. 7807 */ 7808 if (cpu->phys_bits != 0) { 7809 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 7810 return; 7811 } 7812 if (cpu->guest_phys_bits != 0) { 7813 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 7814 return; 7815 } 7816 7817 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 7818 cpu->phys_bits = 36; 7819 } else { 7820 cpu->phys_bits = 32; 7821 } 7822 } 7823 7824 /* Cache information initialization */ 7825 if (!cpu->legacy_cache) { 7826 const CPUCaches *cache_info = 7827 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 7828 7829 if (!xcc->model || !cache_info) { 7830 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7831 error_setg(errp, 7832 "CPU model '%s' doesn't support legacy-cache=off", name); 7833 return; 7834 } 7835 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 7836 *cache_info; 7837 } else { 7838 /* Build legacy cache information */ 7839 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 7840 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 7841 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 7842 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 7843 7844 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 7845 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 7846 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 7847 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 7848 7849 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 7850 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 7851 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 7852 env->cache_info_amd.l3_cache = &legacy_l3_cache; 7853 } 7854 7855 #ifndef CONFIG_USER_ONLY 7856 MachineState *ms = MACHINE(qdev_get_machine()); 7857 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 7858 7859 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 7860 x86_cpu_apic_create(cpu, &local_err); 7861 if (local_err != NULL) { 7862 goto out; 7863 } 7864 } 7865 #endif 7866 7867 mce_init(cpu); 7868 7869 x86_cpu_gdb_init(cs); 7870 qemu_init_vcpu(cs); 7871 7872 /* 7873 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 7874 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 7875 * based on inputs (sockets,cores,threads), it is still better to give 7876 * users a warning. 7877 * 7878 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 7879 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 7880 */ 7881 if (IS_AMD_CPU(env) && 7882 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 7883 cs->nr_threads > 1) { 7884 warn_report_once("This family of AMD CPU doesn't support " 7885 "hyperthreading(%d). Please configure -smp " 7886 "options properly or try enabling topoext " 7887 "feature.", cs->nr_threads); 7888 } 7889 7890 #ifndef CONFIG_USER_ONLY 7891 x86_cpu_apic_realize(cpu, &local_err); 7892 if (local_err != NULL) { 7893 goto out; 7894 } 7895 #endif /* !CONFIG_USER_ONLY */ 7896 cpu_reset(cs); 7897 7898 xcc->parent_realize(dev, &local_err); 7899 7900 out: 7901 if (local_err != NULL) { 7902 error_propagate(errp, local_err); 7903 return; 7904 } 7905 } 7906 7907 static void x86_cpu_unrealizefn(DeviceState *dev) 7908 { 7909 X86CPU *cpu = X86_CPU(dev); 7910 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7911 7912 #ifndef CONFIG_USER_ONLY 7913 cpu_remove_sync(CPU(dev)); 7914 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 7915 #endif 7916 7917 if (cpu->apic_state) { 7918 object_unparent(OBJECT(cpu->apic_state)); 7919 cpu->apic_state = NULL; 7920 } 7921 7922 xcc->parent_unrealize(dev); 7923 } 7924 7925 typedef struct BitProperty { 7926 FeatureWord w; 7927 uint64_t mask; 7928 } BitProperty; 7929 7930 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 7931 void *opaque, Error **errp) 7932 { 7933 X86CPU *cpu = X86_CPU(obj); 7934 BitProperty *fp = opaque; 7935 uint64_t f = cpu->env.features[fp->w]; 7936 bool value = (f & fp->mask) == fp->mask; 7937 visit_type_bool(v, name, &value, errp); 7938 } 7939 7940 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 7941 void *opaque, Error **errp) 7942 { 7943 DeviceState *dev = DEVICE(obj); 7944 X86CPU *cpu = X86_CPU(obj); 7945 BitProperty *fp = opaque; 7946 bool value; 7947 7948 if (dev->realized) { 7949 qdev_prop_set_after_realize(dev, name, errp); 7950 return; 7951 } 7952 7953 if (!visit_type_bool(v, name, &value, errp)) { 7954 return; 7955 } 7956 7957 if (value) { 7958 cpu->env.features[fp->w] |= fp->mask; 7959 } else { 7960 cpu->env.features[fp->w] &= ~fp->mask; 7961 } 7962 cpu->env.user_features[fp->w] |= fp->mask; 7963 } 7964 7965 /* Register a boolean property to get/set a single bit in a uint32_t field. 7966 * 7967 * The same property name can be registered multiple times to make it affect 7968 * multiple bits in the same FeatureWord. In that case, the getter will return 7969 * true only if all bits are set. 7970 */ 7971 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 7972 const char *prop_name, 7973 FeatureWord w, 7974 int bitnr) 7975 { 7976 ObjectClass *oc = OBJECT_CLASS(xcc); 7977 BitProperty *fp; 7978 ObjectProperty *op; 7979 uint64_t mask = (1ULL << bitnr); 7980 7981 op = object_class_property_find(oc, prop_name); 7982 if (op) { 7983 fp = op->opaque; 7984 assert(fp->w == w); 7985 fp->mask |= mask; 7986 } else { 7987 fp = g_new0(BitProperty, 1); 7988 fp->w = w; 7989 fp->mask = mask; 7990 object_class_property_add(oc, prop_name, "bool", 7991 x86_cpu_get_bit_prop, 7992 x86_cpu_set_bit_prop, 7993 NULL, fp); 7994 } 7995 } 7996 7997 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 7998 FeatureWord w, 7999 int bitnr) 8000 { 8001 FeatureWordInfo *fi = &feature_word_info[w]; 8002 const char *name = fi->feat_names[bitnr]; 8003 8004 if (!name) { 8005 return; 8006 } 8007 8008 /* Property names should use "-" instead of "_". 8009 * Old names containing underscores are registered as aliases 8010 * using object_property_add_alias() 8011 */ 8012 assert(!strchr(name, '_')); 8013 /* aliases don't use "|" delimiters anymore, they are registered 8014 * manually using object_property_add_alias() */ 8015 assert(!strchr(name, '|')); 8016 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 8017 } 8018 8019 static void x86_cpu_post_initfn(Object *obj) 8020 { 8021 accel_cpu_instance_init(CPU(obj)); 8022 } 8023 8024 static void x86_cpu_init_default_topo(X86CPU *cpu) 8025 { 8026 CPUX86State *env = &cpu->env; 8027 8028 env->nr_modules = 1; 8029 env->nr_dies = 1; 8030 8031 /* SMT, core and package levels are set by default. */ 8032 set_bit(CPU_TOPO_LEVEL_SMT, env->avail_cpu_topo); 8033 set_bit(CPU_TOPO_LEVEL_CORE, env->avail_cpu_topo); 8034 set_bit(CPU_TOPO_LEVEL_PACKAGE, env->avail_cpu_topo); 8035 } 8036 8037 static void x86_cpu_initfn(Object *obj) 8038 { 8039 X86CPU *cpu = X86_CPU(obj); 8040 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 8041 CPUX86State *env = &cpu->env; 8042 8043 x86_cpu_init_default_topo(cpu); 8044 8045 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 8046 x86_cpu_get_feature_words, 8047 NULL, NULL, (void *)env->features); 8048 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 8049 x86_cpu_get_feature_words, 8050 NULL, NULL, (void *)cpu->filtered_features); 8051 8052 object_property_add_alias(obj, "sse3", obj, "pni"); 8053 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 8054 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 8055 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 8056 object_property_add_alias(obj, "xd", obj, "nx"); 8057 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 8058 object_property_add_alias(obj, "i64", obj, "lm"); 8059 8060 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 8061 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 8062 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 8063 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 8064 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 8065 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 8066 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 8067 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 8068 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 8069 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 8070 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 8071 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 8072 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 8073 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 8074 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 8075 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 8076 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 8077 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 8078 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 8079 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 8080 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 8081 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 8082 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 8083 8084 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 8085 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 8086 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 8087 8088 if (xcc->model) { 8089 x86_cpu_load_model(cpu, xcc->model); 8090 } 8091 } 8092 8093 static int64_t x86_cpu_get_arch_id(CPUState *cs) 8094 { 8095 X86CPU *cpu = X86_CPU(cs); 8096 8097 return cpu->apic_id; 8098 } 8099 8100 #if !defined(CONFIG_USER_ONLY) 8101 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 8102 { 8103 X86CPU *cpu = X86_CPU(cs); 8104 8105 return cpu->env.cr[0] & CR0_PG_MASK; 8106 } 8107 #endif /* !CONFIG_USER_ONLY */ 8108 8109 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 8110 { 8111 X86CPU *cpu = X86_CPU(cs); 8112 8113 cpu->env.eip = value; 8114 } 8115 8116 static vaddr x86_cpu_get_pc(CPUState *cs) 8117 { 8118 X86CPU *cpu = X86_CPU(cs); 8119 8120 /* Match cpu_get_tb_cpu_state. */ 8121 return cpu->env.eip + cpu->env.segs[R_CS].base; 8122 } 8123 8124 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 8125 { 8126 X86CPU *cpu = X86_CPU(cs); 8127 CPUX86State *env = &cpu->env; 8128 8129 #if !defined(CONFIG_USER_ONLY) 8130 if (interrupt_request & CPU_INTERRUPT_POLL) { 8131 return CPU_INTERRUPT_POLL; 8132 } 8133 #endif 8134 if (interrupt_request & CPU_INTERRUPT_SIPI) { 8135 return CPU_INTERRUPT_SIPI; 8136 } 8137 8138 if (env->hflags2 & HF2_GIF_MASK) { 8139 if ((interrupt_request & CPU_INTERRUPT_SMI) && 8140 !(env->hflags & HF_SMM_MASK)) { 8141 return CPU_INTERRUPT_SMI; 8142 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 8143 !(env->hflags2 & HF2_NMI_MASK)) { 8144 return CPU_INTERRUPT_NMI; 8145 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 8146 return CPU_INTERRUPT_MCE; 8147 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 8148 (((env->hflags2 & HF2_VINTR_MASK) && 8149 (env->hflags2 & HF2_HIF_MASK)) || 8150 (!(env->hflags2 & HF2_VINTR_MASK) && 8151 (env->eflags & IF_MASK && 8152 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 8153 return CPU_INTERRUPT_HARD; 8154 #if !defined(CONFIG_USER_ONLY) 8155 } else if (env->hflags2 & HF2_VGIF_MASK) { 8156 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 8157 (env->eflags & IF_MASK) && 8158 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 8159 return CPU_INTERRUPT_VIRQ; 8160 } 8161 #endif 8162 } 8163 } 8164 8165 return 0; 8166 } 8167 8168 static bool x86_cpu_has_work(CPUState *cs) 8169 { 8170 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 8171 } 8172 8173 int x86_mmu_index_pl(CPUX86State *env, unsigned pl) 8174 { 8175 int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1; 8176 int mmu_index_base = 8177 pl == 3 ? MMU_USER64_IDX : 8178 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8179 (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; 8180 8181 return mmu_index_base + mmu_index_32; 8182 } 8183 8184 static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) 8185 { 8186 CPUX86State *env = cpu_env(cs); 8187 return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK); 8188 } 8189 8190 static int x86_mmu_index_kernel_pl(CPUX86State *env, unsigned pl) 8191 { 8192 int mmu_index_32 = (env->hflags & HF_LMA_MASK) ? 0 : 1; 8193 int mmu_index_base = 8194 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8195 (pl < 3 && (env->eflags & AC_MASK) 8196 ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX); 8197 8198 return mmu_index_base + mmu_index_32; 8199 } 8200 8201 int cpu_mmu_index_kernel(CPUX86State *env) 8202 { 8203 return x86_mmu_index_kernel_pl(env, env->hflags & HF_CPL_MASK); 8204 } 8205 8206 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 8207 { 8208 X86CPU *cpu = X86_CPU(cs); 8209 CPUX86State *env = &cpu->env; 8210 8211 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 8212 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 8213 : bfd_mach_i386_i8086); 8214 8215 info->cap_arch = CS_ARCH_X86; 8216 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 8217 : env->hflags & HF_CS32_MASK ? CS_MODE_32 8218 : CS_MODE_16); 8219 info->cap_insn_unit = 1; 8220 info->cap_insn_split = 8; 8221 } 8222 8223 void x86_update_hflags(CPUX86State *env) 8224 { 8225 uint32_t hflags; 8226 #define HFLAG_COPY_MASK \ 8227 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 8228 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 8229 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 8230 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 8231 8232 hflags = env->hflags & HFLAG_COPY_MASK; 8233 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 8234 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 8235 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 8236 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 8237 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 8238 8239 if (env->cr[4] & CR4_OSFXSR_MASK) { 8240 hflags |= HF_OSFXSR_MASK; 8241 } 8242 8243 if (env->efer & MSR_EFER_LMA) { 8244 hflags |= HF_LMA_MASK; 8245 } 8246 8247 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 8248 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 8249 } else { 8250 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 8251 (DESC_B_SHIFT - HF_CS32_SHIFT); 8252 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 8253 (DESC_B_SHIFT - HF_SS32_SHIFT); 8254 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 8255 !(hflags & HF_CS32_MASK)) { 8256 hflags |= HF_ADDSEG_MASK; 8257 } else { 8258 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 8259 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 8260 } 8261 } 8262 env->hflags = hflags; 8263 } 8264 8265 static Property x86_cpu_properties[] = { 8266 #ifdef CONFIG_USER_ONLY 8267 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 8268 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 8269 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 8270 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 8271 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 8272 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 8273 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 8274 #else 8275 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 8276 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 8277 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 8278 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 8279 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 8280 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 8281 #endif 8282 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 8283 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 8284 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 8285 8286 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 8287 HYPERV_SPINLOCK_NEVER_NOTIFY), 8288 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 8289 HYPERV_FEAT_RELAXED, 0), 8290 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 8291 HYPERV_FEAT_VAPIC, 0), 8292 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 8293 HYPERV_FEAT_TIME, 0), 8294 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 8295 HYPERV_FEAT_CRASH, 0), 8296 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 8297 HYPERV_FEAT_RESET, 0), 8298 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 8299 HYPERV_FEAT_VPINDEX, 0), 8300 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 8301 HYPERV_FEAT_RUNTIME, 0), 8302 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 8303 HYPERV_FEAT_SYNIC, 0), 8304 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 8305 HYPERV_FEAT_STIMER, 0), 8306 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 8307 HYPERV_FEAT_FREQUENCIES, 0), 8308 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 8309 HYPERV_FEAT_REENLIGHTENMENT, 0), 8310 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 8311 HYPERV_FEAT_TLBFLUSH, 0), 8312 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 8313 HYPERV_FEAT_EVMCS, 0), 8314 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 8315 HYPERV_FEAT_IPI, 0), 8316 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 8317 HYPERV_FEAT_STIMER_DIRECT, 0), 8318 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 8319 HYPERV_FEAT_AVIC, 0), 8320 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 8321 HYPERV_FEAT_MSR_BITMAP, 0), 8322 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 8323 HYPERV_FEAT_XMM_INPUT, 0), 8324 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 8325 HYPERV_FEAT_TLBFLUSH_EXT, 0), 8326 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 8327 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 8328 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 8329 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 8330 #ifdef CONFIG_SYNDBG 8331 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 8332 HYPERV_FEAT_SYNDBG, 0), 8333 #endif 8334 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 8335 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 8336 8337 /* WS2008R2 identify by default */ 8338 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 8339 0x3839), 8340 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 8341 0x000A), 8342 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 8343 0x0000), 8344 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 8345 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 8346 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 8347 8348 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 8349 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 8350 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 8351 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 8352 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 8353 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 8354 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 8355 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 8356 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 8357 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 8358 UINT32_MAX), 8359 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 8360 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 8361 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 8362 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 8363 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 8364 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 8365 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 8366 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 8367 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 8368 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 8369 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 8370 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), 8371 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 8372 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 8373 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 8374 false), 8375 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 8376 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 8377 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 8378 true), 8379 /* 8380 * lecacy_cache defaults to true unless the CPU model provides its 8381 * own cache information (see x86_cpu_load_def()). 8382 */ 8383 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 8384 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 8385 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 8386 8387 /* 8388 * From "Requirements for Implementing the Microsoft 8389 * Hypervisor Interface": 8390 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 8391 * 8392 * "Starting with Windows Server 2012 and Windows 8, if 8393 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 8394 * the hypervisor imposes no specific limit to the number of VPs. 8395 * In this case, Windows Server 2012 guest VMs may use more than 8396 * 64 VPs, up to the maximum supported number of processors applicable 8397 * to the specific Windows version being used." 8398 */ 8399 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 8400 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 8401 false), 8402 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 8403 true), 8404 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 8405 DEFINE_PROP_END_OF_LIST() 8406 }; 8407 8408 #ifndef CONFIG_USER_ONLY 8409 #include "hw/core/sysemu-cpu-ops.h" 8410 8411 static const struct SysemuCPUOps i386_sysemu_ops = { 8412 .get_memory_mapping = x86_cpu_get_memory_mapping, 8413 .get_paging_enabled = x86_cpu_get_paging_enabled, 8414 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 8415 .asidx_from_attrs = x86_asidx_from_attrs, 8416 .get_crash_info = x86_cpu_get_crash_info, 8417 .write_elf32_note = x86_cpu_write_elf32_note, 8418 .write_elf64_note = x86_cpu_write_elf64_note, 8419 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 8420 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 8421 .legacy_vmsd = &vmstate_x86_cpu, 8422 }; 8423 #endif 8424 8425 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 8426 { 8427 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8428 CPUClass *cc = CPU_CLASS(oc); 8429 DeviceClass *dc = DEVICE_CLASS(oc); 8430 ResettableClass *rc = RESETTABLE_CLASS(oc); 8431 FeatureWord w; 8432 8433 device_class_set_parent_realize(dc, x86_cpu_realizefn, 8434 &xcc->parent_realize); 8435 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 8436 &xcc->parent_unrealize); 8437 device_class_set_props(dc, x86_cpu_properties); 8438 8439 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 8440 &xcc->parent_phases); 8441 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 8442 8443 cc->class_by_name = x86_cpu_class_by_name; 8444 cc->parse_features = x86_cpu_parse_featurestr; 8445 cc->has_work = x86_cpu_has_work; 8446 cc->mmu_index = x86_cpu_mmu_index; 8447 cc->dump_state = x86_cpu_dump_state; 8448 cc->set_pc = x86_cpu_set_pc; 8449 cc->get_pc = x86_cpu_get_pc; 8450 cc->gdb_read_register = x86_cpu_gdb_read_register; 8451 cc->gdb_write_register = x86_cpu_gdb_write_register; 8452 cc->get_arch_id = x86_cpu_get_arch_id; 8453 8454 #ifndef CONFIG_USER_ONLY 8455 cc->sysemu_ops = &i386_sysemu_ops; 8456 #endif /* !CONFIG_USER_ONLY */ 8457 8458 cc->gdb_arch_name = x86_gdb_arch_name; 8459 #ifdef TARGET_X86_64 8460 cc->gdb_core_xml_file = "i386-64bit.xml"; 8461 #else 8462 cc->gdb_core_xml_file = "i386-32bit.xml"; 8463 #endif 8464 cc->disas_set_info = x86_disas_set_info; 8465 8466 dc->user_creatable = true; 8467 8468 object_class_property_add(oc, "family", "int", 8469 x86_cpuid_version_get_family, 8470 x86_cpuid_version_set_family, NULL, NULL); 8471 object_class_property_add(oc, "model", "int", 8472 x86_cpuid_version_get_model, 8473 x86_cpuid_version_set_model, NULL, NULL); 8474 object_class_property_add(oc, "stepping", "int", 8475 x86_cpuid_version_get_stepping, 8476 x86_cpuid_version_set_stepping, NULL, NULL); 8477 object_class_property_add_str(oc, "vendor", 8478 x86_cpuid_get_vendor, 8479 x86_cpuid_set_vendor); 8480 object_class_property_add_str(oc, "model-id", 8481 x86_cpuid_get_model_id, 8482 x86_cpuid_set_model_id); 8483 object_class_property_add(oc, "tsc-frequency", "int", 8484 x86_cpuid_get_tsc_freq, 8485 x86_cpuid_set_tsc_freq, NULL, NULL); 8486 /* 8487 * The "unavailable-features" property has the same semantics as 8488 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 8489 * QMP command: they list the features that would have prevented the 8490 * CPU from running if the "enforce" flag was set. 8491 */ 8492 object_class_property_add(oc, "unavailable-features", "strList", 8493 x86_cpu_get_unavailable_features, 8494 NULL, NULL, NULL); 8495 8496 #if !defined(CONFIG_USER_ONLY) 8497 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 8498 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 8499 #endif 8500 8501 for (w = 0; w < FEATURE_WORDS; w++) { 8502 int bitnr; 8503 for (bitnr = 0; bitnr < 64; bitnr++) { 8504 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 8505 } 8506 } 8507 } 8508 8509 static const TypeInfo x86_cpu_type_info = { 8510 .name = TYPE_X86_CPU, 8511 .parent = TYPE_CPU, 8512 .instance_size = sizeof(X86CPU), 8513 .instance_align = __alignof(X86CPU), 8514 .instance_init = x86_cpu_initfn, 8515 .instance_post_init = x86_cpu_post_initfn, 8516 8517 .abstract = true, 8518 .class_size = sizeof(X86CPUClass), 8519 .class_init = x86_cpu_common_class_init, 8520 }; 8521 8522 /* "base" CPU model, used by query-cpu-model-expansion */ 8523 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 8524 { 8525 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8526 8527 xcc->static_model = true; 8528 xcc->migration_safe = true; 8529 xcc->model_description = "base CPU model type with no features enabled"; 8530 xcc->ordering = 8; 8531 } 8532 8533 static const TypeInfo x86_base_cpu_type_info = { 8534 .name = X86_CPU_TYPE_NAME("base"), 8535 .parent = TYPE_X86_CPU, 8536 .class_init = x86_cpu_base_class_init, 8537 }; 8538 8539 static void x86_cpu_register_types(void) 8540 { 8541 int i; 8542 8543 type_register_static(&x86_cpu_type_info); 8544 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 8545 x86_register_cpudef_types(&builtin_x86_defs[i]); 8546 } 8547 type_register_static(&max_x86_cpu_type_info); 8548 type_register_static(&x86_base_cpu_type_info); 8549 } 8550 8551 type_init(x86_cpu_register_types) 8552