161766fe9SRichard Henderson /* 261766fe9SRichard Henderson * HPPA emulation cpu translation for qemu. 361766fe9SRichard Henderson * 461766fe9SRichard Henderson * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> 561766fe9SRichard Henderson * 661766fe9SRichard Henderson * This library is free software; you can redistribute it and/or 761766fe9SRichard Henderson * modify it under the terms of the GNU Lesser General Public 861766fe9SRichard Henderson * License as published by the Free Software Foundation; either 961766fe9SRichard Henderson * version 2 of the License, or (at your option) any later version. 1061766fe9SRichard Henderson * 1161766fe9SRichard Henderson * This library is distributed in the hope that it will be useful, 1261766fe9SRichard Henderson * but WITHOUT ANY WARRANTY; without even the implied warranty of 1361766fe9SRichard Henderson * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1461766fe9SRichard Henderson * Lesser General Public License for more details. 1561766fe9SRichard Henderson * 1661766fe9SRichard Henderson * You should have received a copy of the GNU Lesser General Public 1761766fe9SRichard Henderson * License along with this library; if not, see <http://www.gnu.org/licenses/>. 1861766fe9SRichard Henderson */ 1961766fe9SRichard Henderson 2061766fe9SRichard Henderson #include "qemu/osdep.h" 2161766fe9SRichard Henderson #include "cpu.h" 2261766fe9SRichard Henderson #include "disas/disas.h" 2361766fe9SRichard Henderson #include "qemu/host-utils.h" 2461766fe9SRichard Henderson #include "exec/exec-all.h" 2561766fe9SRichard Henderson #include "tcg-op.h" 2661766fe9SRichard Henderson #include "exec/cpu_ldst.h" 2761766fe9SRichard Henderson #include "exec/helper-proto.h" 2861766fe9SRichard Henderson #include "exec/helper-gen.h" 29869051eaSRichard Henderson #include "exec/translator.h" 3061766fe9SRichard Henderson #include "trace-tcg.h" 3161766fe9SRichard Henderson #include "exec/log.h" 3261766fe9SRichard Henderson 33eaa3783bSRichard Henderson /* Since we have a distinction between register size and address size, 34eaa3783bSRichard Henderson we need to redefine all of these. */ 35eaa3783bSRichard Henderson 36eaa3783bSRichard Henderson #undef TCGv 37eaa3783bSRichard Henderson #undef tcg_temp_new 38eaa3783bSRichard Henderson #undef tcg_global_reg_new 39eaa3783bSRichard Henderson #undef tcg_global_mem_new 40eaa3783bSRichard Henderson #undef tcg_temp_local_new 41eaa3783bSRichard Henderson #undef tcg_temp_free 42eaa3783bSRichard Henderson 43eaa3783bSRichard Henderson #if TARGET_LONG_BITS == 64 44eaa3783bSRichard Henderson #define TCGv_tl TCGv_i64 45eaa3783bSRichard Henderson #define tcg_temp_new_tl tcg_temp_new_i64 46eaa3783bSRichard Henderson #define tcg_temp_free_tl tcg_temp_free_i64 47eaa3783bSRichard Henderson #if TARGET_REGISTER_BITS == 64 48eaa3783bSRichard Henderson #define tcg_gen_extu_reg_tl tcg_gen_mov_i64 49eaa3783bSRichard Henderson #else 50eaa3783bSRichard Henderson #define tcg_gen_extu_reg_tl tcg_gen_extu_i32_i64 51eaa3783bSRichard Henderson #endif 52eaa3783bSRichard Henderson #else 53eaa3783bSRichard Henderson #define TCGv_tl TCGv_i32 54eaa3783bSRichard Henderson #define tcg_temp_new_tl tcg_temp_new_i32 55eaa3783bSRichard Henderson #define tcg_temp_free_tl tcg_temp_free_i32 56eaa3783bSRichard Henderson #define tcg_gen_extu_reg_tl tcg_gen_mov_i32 57eaa3783bSRichard Henderson #endif 58eaa3783bSRichard Henderson 59eaa3783bSRichard Henderson #if TARGET_REGISTER_BITS == 64 60eaa3783bSRichard Henderson #define TCGv_reg TCGv_i64 61eaa3783bSRichard Henderson 62eaa3783bSRichard Henderson #define tcg_temp_new tcg_temp_new_i64 63eaa3783bSRichard Henderson #define tcg_global_reg_new tcg_global_reg_new_i64 64eaa3783bSRichard Henderson #define tcg_global_mem_new tcg_global_mem_new_i64 65eaa3783bSRichard Henderson #define tcg_temp_local_new tcg_temp_local_new_i64 66eaa3783bSRichard Henderson #define tcg_temp_free tcg_temp_free_i64 67eaa3783bSRichard Henderson 68eaa3783bSRichard Henderson #define tcg_gen_movi_reg tcg_gen_movi_i64 69eaa3783bSRichard Henderson #define tcg_gen_mov_reg tcg_gen_mov_i64 70eaa3783bSRichard Henderson #define tcg_gen_ld8u_reg tcg_gen_ld8u_i64 71eaa3783bSRichard Henderson #define tcg_gen_ld8s_reg tcg_gen_ld8s_i64 72eaa3783bSRichard Henderson #define tcg_gen_ld16u_reg tcg_gen_ld16u_i64 73eaa3783bSRichard Henderson #define tcg_gen_ld16s_reg tcg_gen_ld16s_i64 74eaa3783bSRichard Henderson #define tcg_gen_ld32u_reg tcg_gen_ld32u_i64 75eaa3783bSRichard Henderson #define tcg_gen_ld32s_reg tcg_gen_ld32s_i64 76eaa3783bSRichard Henderson #define tcg_gen_ld_reg tcg_gen_ld_i64 77eaa3783bSRichard Henderson #define tcg_gen_st8_reg tcg_gen_st8_i64 78eaa3783bSRichard Henderson #define tcg_gen_st16_reg tcg_gen_st16_i64 79eaa3783bSRichard Henderson #define tcg_gen_st32_reg tcg_gen_st32_i64 80eaa3783bSRichard Henderson #define tcg_gen_st_reg tcg_gen_st_i64 81eaa3783bSRichard Henderson #define tcg_gen_add_reg tcg_gen_add_i64 82eaa3783bSRichard Henderson #define tcg_gen_addi_reg tcg_gen_addi_i64 83eaa3783bSRichard Henderson #define tcg_gen_sub_reg tcg_gen_sub_i64 84eaa3783bSRichard Henderson #define tcg_gen_neg_reg tcg_gen_neg_i64 85eaa3783bSRichard Henderson #define tcg_gen_subfi_reg tcg_gen_subfi_i64 86eaa3783bSRichard Henderson #define tcg_gen_subi_reg tcg_gen_subi_i64 87eaa3783bSRichard Henderson #define tcg_gen_and_reg tcg_gen_and_i64 88eaa3783bSRichard Henderson #define tcg_gen_andi_reg tcg_gen_andi_i64 89eaa3783bSRichard Henderson #define tcg_gen_or_reg tcg_gen_or_i64 90eaa3783bSRichard Henderson #define tcg_gen_ori_reg tcg_gen_ori_i64 91eaa3783bSRichard Henderson #define tcg_gen_xor_reg tcg_gen_xor_i64 92eaa3783bSRichard Henderson #define tcg_gen_xori_reg tcg_gen_xori_i64 93eaa3783bSRichard Henderson #define tcg_gen_not_reg tcg_gen_not_i64 94eaa3783bSRichard Henderson #define tcg_gen_shl_reg tcg_gen_shl_i64 95eaa3783bSRichard Henderson #define tcg_gen_shli_reg tcg_gen_shli_i64 96eaa3783bSRichard Henderson #define tcg_gen_shr_reg tcg_gen_shr_i64 97eaa3783bSRichard Henderson #define tcg_gen_shri_reg tcg_gen_shri_i64 98eaa3783bSRichard Henderson #define tcg_gen_sar_reg tcg_gen_sar_i64 99eaa3783bSRichard Henderson #define tcg_gen_sari_reg tcg_gen_sari_i64 100eaa3783bSRichard Henderson #define tcg_gen_brcond_reg tcg_gen_brcond_i64 101eaa3783bSRichard Henderson #define tcg_gen_brcondi_reg tcg_gen_brcondi_i64 102eaa3783bSRichard Henderson #define tcg_gen_setcond_reg tcg_gen_setcond_i64 103eaa3783bSRichard Henderson #define tcg_gen_setcondi_reg tcg_gen_setcondi_i64 104eaa3783bSRichard Henderson #define tcg_gen_mul_reg tcg_gen_mul_i64 105eaa3783bSRichard Henderson #define tcg_gen_muli_reg tcg_gen_muli_i64 106eaa3783bSRichard Henderson #define tcg_gen_div_reg tcg_gen_div_i64 107eaa3783bSRichard Henderson #define tcg_gen_rem_reg tcg_gen_rem_i64 108eaa3783bSRichard Henderson #define tcg_gen_divu_reg tcg_gen_divu_i64 109eaa3783bSRichard Henderson #define tcg_gen_remu_reg tcg_gen_remu_i64 110eaa3783bSRichard Henderson #define tcg_gen_discard_reg tcg_gen_discard_i64 111eaa3783bSRichard Henderson #define tcg_gen_trunc_reg_i32 tcg_gen_extrl_i64_i32 112eaa3783bSRichard Henderson #define tcg_gen_trunc_i64_reg tcg_gen_mov_i64 113eaa3783bSRichard Henderson #define tcg_gen_extu_i32_reg tcg_gen_extu_i32_i64 114eaa3783bSRichard Henderson #define tcg_gen_ext_i32_reg tcg_gen_ext_i32_i64 115eaa3783bSRichard Henderson #define tcg_gen_extu_reg_i64 tcg_gen_mov_i64 116eaa3783bSRichard Henderson #define tcg_gen_ext_reg_i64 tcg_gen_mov_i64 117eaa3783bSRichard Henderson #define tcg_gen_ext8u_reg tcg_gen_ext8u_i64 118eaa3783bSRichard Henderson #define tcg_gen_ext8s_reg tcg_gen_ext8s_i64 119eaa3783bSRichard Henderson #define tcg_gen_ext16u_reg tcg_gen_ext16u_i64 120eaa3783bSRichard Henderson #define tcg_gen_ext16s_reg tcg_gen_ext16s_i64 121eaa3783bSRichard Henderson #define tcg_gen_ext32u_reg tcg_gen_ext32u_i64 122eaa3783bSRichard Henderson #define tcg_gen_ext32s_reg tcg_gen_ext32s_i64 123eaa3783bSRichard Henderson #define tcg_gen_bswap16_reg tcg_gen_bswap16_i64 124eaa3783bSRichard Henderson #define tcg_gen_bswap32_reg tcg_gen_bswap32_i64 125eaa3783bSRichard Henderson #define tcg_gen_bswap64_reg tcg_gen_bswap64_i64 126eaa3783bSRichard Henderson #define tcg_gen_concat_reg_i64 tcg_gen_concat32_i64 127eaa3783bSRichard Henderson #define tcg_gen_andc_reg tcg_gen_andc_i64 128eaa3783bSRichard Henderson #define tcg_gen_eqv_reg tcg_gen_eqv_i64 129eaa3783bSRichard Henderson #define tcg_gen_nand_reg tcg_gen_nand_i64 130eaa3783bSRichard Henderson #define tcg_gen_nor_reg tcg_gen_nor_i64 131eaa3783bSRichard Henderson #define tcg_gen_orc_reg tcg_gen_orc_i64 132eaa3783bSRichard Henderson #define tcg_gen_clz_reg tcg_gen_clz_i64 133eaa3783bSRichard Henderson #define tcg_gen_ctz_reg tcg_gen_ctz_i64 134eaa3783bSRichard Henderson #define tcg_gen_clzi_reg tcg_gen_clzi_i64 135eaa3783bSRichard Henderson #define tcg_gen_ctzi_reg tcg_gen_ctzi_i64 136eaa3783bSRichard Henderson #define tcg_gen_clrsb_reg tcg_gen_clrsb_i64 137eaa3783bSRichard Henderson #define tcg_gen_ctpop_reg tcg_gen_ctpop_i64 138eaa3783bSRichard Henderson #define tcg_gen_rotl_reg tcg_gen_rotl_i64 139eaa3783bSRichard Henderson #define tcg_gen_rotli_reg tcg_gen_rotli_i64 140eaa3783bSRichard Henderson #define tcg_gen_rotr_reg tcg_gen_rotr_i64 141eaa3783bSRichard Henderson #define tcg_gen_rotri_reg tcg_gen_rotri_i64 142eaa3783bSRichard Henderson #define tcg_gen_deposit_reg tcg_gen_deposit_i64 143eaa3783bSRichard Henderson #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64 144eaa3783bSRichard Henderson #define tcg_gen_extract_reg tcg_gen_extract_i64 145eaa3783bSRichard Henderson #define tcg_gen_sextract_reg tcg_gen_sextract_i64 146eaa3783bSRichard Henderson #define tcg_const_reg tcg_const_i64 147eaa3783bSRichard Henderson #define tcg_const_local_reg tcg_const_local_i64 148eaa3783bSRichard Henderson #define tcg_gen_movcond_reg tcg_gen_movcond_i64 149eaa3783bSRichard Henderson #define tcg_gen_add2_reg tcg_gen_add2_i64 150eaa3783bSRichard Henderson #define tcg_gen_sub2_reg tcg_gen_sub2_i64 151eaa3783bSRichard Henderson #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i64 152eaa3783bSRichard Henderson #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64 153eaa3783bSRichard Henderson #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64 1545bfa8034SRichard Henderson #define tcg_gen_trunc_reg_ptr tcg_gen_trunc_i64_ptr 155eaa3783bSRichard Henderson #else 156eaa3783bSRichard Henderson #define TCGv_reg TCGv_i32 157eaa3783bSRichard Henderson #define tcg_temp_new tcg_temp_new_i32 158eaa3783bSRichard Henderson #define tcg_global_reg_new tcg_global_reg_new_i32 159eaa3783bSRichard Henderson #define tcg_global_mem_new tcg_global_mem_new_i32 160eaa3783bSRichard Henderson #define tcg_temp_local_new tcg_temp_local_new_i32 161eaa3783bSRichard Henderson #define tcg_temp_free tcg_temp_free_i32 162eaa3783bSRichard Henderson 163eaa3783bSRichard Henderson #define tcg_gen_movi_reg tcg_gen_movi_i32 164eaa3783bSRichard Henderson #define tcg_gen_mov_reg tcg_gen_mov_i32 165eaa3783bSRichard Henderson #define tcg_gen_ld8u_reg tcg_gen_ld8u_i32 166eaa3783bSRichard Henderson #define tcg_gen_ld8s_reg tcg_gen_ld8s_i32 167eaa3783bSRichard Henderson #define tcg_gen_ld16u_reg tcg_gen_ld16u_i32 168eaa3783bSRichard Henderson #define tcg_gen_ld16s_reg tcg_gen_ld16s_i32 169eaa3783bSRichard Henderson #define tcg_gen_ld32u_reg tcg_gen_ld_i32 170eaa3783bSRichard Henderson #define tcg_gen_ld32s_reg tcg_gen_ld_i32 171eaa3783bSRichard Henderson #define tcg_gen_ld_reg tcg_gen_ld_i32 172eaa3783bSRichard Henderson #define tcg_gen_st8_reg tcg_gen_st8_i32 173eaa3783bSRichard Henderson #define tcg_gen_st16_reg tcg_gen_st16_i32 174eaa3783bSRichard Henderson #define tcg_gen_st32_reg tcg_gen_st32_i32 175eaa3783bSRichard Henderson #define tcg_gen_st_reg tcg_gen_st_i32 176eaa3783bSRichard Henderson #define tcg_gen_add_reg tcg_gen_add_i32 177eaa3783bSRichard Henderson #define tcg_gen_addi_reg tcg_gen_addi_i32 178eaa3783bSRichard Henderson #define tcg_gen_sub_reg tcg_gen_sub_i32 179eaa3783bSRichard Henderson #define tcg_gen_neg_reg tcg_gen_neg_i32 180eaa3783bSRichard Henderson #define tcg_gen_subfi_reg tcg_gen_subfi_i32 181eaa3783bSRichard Henderson #define tcg_gen_subi_reg tcg_gen_subi_i32 182eaa3783bSRichard Henderson #define tcg_gen_and_reg tcg_gen_and_i32 183eaa3783bSRichard Henderson #define tcg_gen_andi_reg tcg_gen_andi_i32 184eaa3783bSRichard Henderson #define tcg_gen_or_reg tcg_gen_or_i32 185eaa3783bSRichard Henderson #define tcg_gen_ori_reg tcg_gen_ori_i32 186eaa3783bSRichard Henderson #define tcg_gen_xor_reg tcg_gen_xor_i32 187eaa3783bSRichard Henderson #define tcg_gen_xori_reg tcg_gen_xori_i32 188eaa3783bSRichard Henderson #define tcg_gen_not_reg tcg_gen_not_i32 189eaa3783bSRichard Henderson #define tcg_gen_shl_reg tcg_gen_shl_i32 190eaa3783bSRichard Henderson #define tcg_gen_shli_reg tcg_gen_shli_i32 191eaa3783bSRichard Henderson #define tcg_gen_shr_reg tcg_gen_shr_i32 192eaa3783bSRichard Henderson #define tcg_gen_shri_reg tcg_gen_shri_i32 193eaa3783bSRichard Henderson #define tcg_gen_sar_reg tcg_gen_sar_i32 194eaa3783bSRichard Henderson #define tcg_gen_sari_reg tcg_gen_sari_i32 195eaa3783bSRichard Henderson #define tcg_gen_brcond_reg tcg_gen_brcond_i32 196eaa3783bSRichard Henderson #define tcg_gen_brcondi_reg tcg_gen_brcondi_i32 197eaa3783bSRichard Henderson #define tcg_gen_setcond_reg tcg_gen_setcond_i32 198eaa3783bSRichard Henderson #define tcg_gen_setcondi_reg tcg_gen_setcondi_i32 199eaa3783bSRichard Henderson #define tcg_gen_mul_reg tcg_gen_mul_i32 200eaa3783bSRichard Henderson #define tcg_gen_muli_reg tcg_gen_muli_i32 201eaa3783bSRichard Henderson #define tcg_gen_div_reg tcg_gen_div_i32 202eaa3783bSRichard Henderson #define tcg_gen_rem_reg tcg_gen_rem_i32 203eaa3783bSRichard Henderson #define tcg_gen_divu_reg tcg_gen_divu_i32 204eaa3783bSRichard Henderson #define tcg_gen_remu_reg tcg_gen_remu_i32 205eaa3783bSRichard Henderson #define tcg_gen_discard_reg tcg_gen_discard_i32 206eaa3783bSRichard Henderson #define tcg_gen_trunc_reg_i32 tcg_gen_mov_i32 207eaa3783bSRichard Henderson #define tcg_gen_trunc_i64_reg tcg_gen_extrl_i64_i32 208eaa3783bSRichard Henderson #define tcg_gen_extu_i32_reg tcg_gen_mov_i32 209eaa3783bSRichard Henderson #define tcg_gen_ext_i32_reg tcg_gen_mov_i32 210eaa3783bSRichard Henderson #define tcg_gen_extu_reg_i64 tcg_gen_extu_i32_i64 211eaa3783bSRichard Henderson #define tcg_gen_ext_reg_i64 tcg_gen_ext_i32_i64 212eaa3783bSRichard Henderson #define tcg_gen_ext8u_reg tcg_gen_ext8u_i32 213eaa3783bSRichard Henderson #define tcg_gen_ext8s_reg tcg_gen_ext8s_i32 214eaa3783bSRichard Henderson #define tcg_gen_ext16u_reg tcg_gen_ext16u_i32 215eaa3783bSRichard Henderson #define tcg_gen_ext16s_reg tcg_gen_ext16s_i32 216eaa3783bSRichard Henderson #define tcg_gen_ext32u_reg tcg_gen_mov_i32 217eaa3783bSRichard Henderson #define tcg_gen_ext32s_reg tcg_gen_mov_i32 218eaa3783bSRichard Henderson #define tcg_gen_bswap16_reg tcg_gen_bswap16_i32 219eaa3783bSRichard Henderson #define tcg_gen_bswap32_reg tcg_gen_bswap32_i32 220eaa3783bSRichard Henderson #define tcg_gen_concat_reg_i64 tcg_gen_concat_i32_i64 221eaa3783bSRichard Henderson #define tcg_gen_andc_reg tcg_gen_andc_i32 222eaa3783bSRichard Henderson #define tcg_gen_eqv_reg tcg_gen_eqv_i32 223eaa3783bSRichard Henderson #define tcg_gen_nand_reg tcg_gen_nand_i32 224eaa3783bSRichard Henderson #define tcg_gen_nor_reg tcg_gen_nor_i32 225eaa3783bSRichard Henderson #define tcg_gen_orc_reg tcg_gen_orc_i32 226eaa3783bSRichard Henderson #define tcg_gen_clz_reg tcg_gen_clz_i32 227eaa3783bSRichard Henderson #define tcg_gen_ctz_reg tcg_gen_ctz_i32 228eaa3783bSRichard Henderson #define tcg_gen_clzi_reg tcg_gen_clzi_i32 229eaa3783bSRichard Henderson #define tcg_gen_ctzi_reg tcg_gen_ctzi_i32 230eaa3783bSRichard Henderson #define tcg_gen_clrsb_reg tcg_gen_clrsb_i32 231eaa3783bSRichard Henderson #define tcg_gen_ctpop_reg tcg_gen_ctpop_i32 232eaa3783bSRichard Henderson #define tcg_gen_rotl_reg tcg_gen_rotl_i32 233eaa3783bSRichard Henderson #define tcg_gen_rotli_reg tcg_gen_rotli_i32 234eaa3783bSRichard Henderson #define tcg_gen_rotr_reg tcg_gen_rotr_i32 235eaa3783bSRichard Henderson #define tcg_gen_rotri_reg tcg_gen_rotri_i32 236eaa3783bSRichard Henderson #define tcg_gen_deposit_reg tcg_gen_deposit_i32 237eaa3783bSRichard Henderson #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32 238eaa3783bSRichard Henderson #define tcg_gen_extract_reg tcg_gen_extract_i32 239eaa3783bSRichard Henderson #define tcg_gen_sextract_reg tcg_gen_sextract_i32 240eaa3783bSRichard Henderson #define tcg_const_reg tcg_const_i32 241eaa3783bSRichard Henderson #define tcg_const_local_reg tcg_const_local_i32 242eaa3783bSRichard Henderson #define tcg_gen_movcond_reg tcg_gen_movcond_i32 243eaa3783bSRichard Henderson #define tcg_gen_add2_reg tcg_gen_add2_i32 244eaa3783bSRichard Henderson #define tcg_gen_sub2_reg tcg_gen_sub2_i32 245eaa3783bSRichard Henderson #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i32 246eaa3783bSRichard Henderson #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i32 247eaa3783bSRichard Henderson #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32 2485bfa8034SRichard Henderson #define tcg_gen_trunc_reg_ptr tcg_gen_ext_i32_ptr 249eaa3783bSRichard Henderson #endif /* TARGET_REGISTER_BITS */ 250eaa3783bSRichard Henderson 25161766fe9SRichard Henderson typedef struct DisasCond { 25261766fe9SRichard Henderson TCGCond c; 253eaa3783bSRichard Henderson TCGv_reg a0, a1; 25461766fe9SRichard Henderson bool a0_is_n; 25561766fe9SRichard Henderson bool a1_is_0; 25661766fe9SRichard Henderson } DisasCond; 25761766fe9SRichard Henderson 25861766fe9SRichard Henderson typedef struct DisasContext { 259d01a3625SRichard Henderson DisasContextBase base; 26061766fe9SRichard Henderson CPUState *cs; 26161766fe9SRichard Henderson 262eaa3783bSRichard Henderson target_ureg iaoq_f; 263eaa3783bSRichard Henderson target_ureg iaoq_b; 264eaa3783bSRichard Henderson target_ureg iaoq_n; 265eaa3783bSRichard Henderson TCGv_reg iaoq_n_var; 26661766fe9SRichard Henderson 26786f8d05fSRichard Henderson int ntempr, ntempl; 2685eecd37aSRichard Henderson TCGv_reg tempr[8]; 26986f8d05fSRichard Henderson TCGv_tl templ[4]; 27061766fe9SRichard Henderson 27161766fe9SRichard Henderson DisasCond null_cond; 27261766fe9SRichard Henderson TCGLabel *null_lab; 27361766fe9SRichard Henderson 2741a19da0dSRichard Henderson uint32_t insn; 275494737b7SRichard Henderson uint32_t tb_flags; 2763d68ee7bSRichard Henderson int mmu_idx; 2773d68ee7bSRichard Henderson int privilege; 27861766fe9SRichard Henderson bool psw_n_nonzero; 27961766fe9SRichard Henderson } DisasContext; 28061766fe9SRichard Henderson 281e36f27efSRichard Henderson /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ 282e36f27efSRichard Henderson static int expand_sm_imm(int val) 283e36f27efSRichard Henderson { 284e36f27efSRichard Henderson if (val & PSW_SM_E) { 285e36f27efSRichard Henderson val = (val & ~PSW_SM_E) | PSW_E; 286e36f27efSRichard Henderson } 287e36f27efSRichard Henderson if (val & PSW_SM_W) { 288e36f27efSRichard Henderson val = (val & ~PSW_SM_W) | PSW_W; 289e36f27efSRichard Henderson } 290e36f27efSRichard Henderson return val; 291e36f27efSRichard Henderson } 292e36f27efSRichard Henderson 293deee69a1SRichard Henderson /* Inverted space register indicates 0 means sr0 not inferred from base. */ 294deee69a1SRichard Henderson static int expand_sr3x(int val) 295deee69a1SRichard Henderson { 296deee69a1SRichard Henderson return ~val; 297deee69a1SRichard Henderson } 298deee69a1SRichard Henderson 2991cd012a5SRichard Henderson /* Convert the M:A bits within a memory insn to the tri-state value 3001cd012a5SRichard Henderson we use for the final M. */ 3011cd012a5SRichard Henderson static int ma_to_m(int val) 3021cd012a5SRichard Henderson { 3031cd012a5SRichard Henderson return val & 2 ? (val & 1 ? -1 : 1) : 0; 3041cd012a5SRichard Henderson } 3051cd012a5SRichard Henderson 306740038d7SRichard Henderson /* Convert the sign of the displacement to a pre or post-modify. */ 307740038d7SRichard Henderson static int pos_to_m(int val) 308740038d7SRichard Henderson { 309740038d7SRichard Henderson return val ? 1 : -1; 310740038d7SRichard Henderson } 311740038d7SRichard Henderson 312740038d7SRichard Henderson static int neg_to_m(int val) 313740038d7SRichard Henderson { 314740038d7SRichard Henderson return val ? -1 : 1; 315740038d7SRichard Henderson } 316740038d7SRichard Henderson 317740038d7SRichard Henderson /* Used for branch targets and fp memory ops. */ 31801afb7beSRichard Henderson static int expand_shl2(int val) 31901afb7beSRichard Henderson { 32001afb7beSRichard Henderson return val << 2; 32101afb7beSRichard Henderson } 32201afb7beSRichard Henderson 323740038d7SRichard Henderson /* Used for fp memory ops. */ 324740038d7SRichard Henderson static int expand_shl3(int val) 325740038d7SRichard Henderson { 326740038d7SRichard Henderson return val << 3; 327740038d7SRichard Henderson } 328740038d7SRichard Henderson 3290588e061SRichard Henderson /* Used for assemble_21. */ 3300588e061SRichard Henderson static int expand_shl11(int val) 3310588e061SRichard Henderson { 3320588e061SRichard Henderson return val << 11; 3330588e061SRichard Henderson } 3340588e061SRichard Henderson 33501afb7beSRichard Henderson 33640f9f908SRichard Henderson /* Include the auto-generated decoder. */ 33740f9f908SRichard Henderson #include "decode.inc.c" 33840f9f908SRichard Henderson 33961766fe9SRichard Henderson /* We are not using a goto_tb (for whatever reason), but have updated 34061766fe9SRichard Henderson the iaq (for whatever reason), so don't do it again on exit. */ 341869051eaSRichard Henderson #define DISAS_IAQ_N_UPDATED DISAS_TARGET_0 34261766fe9SRichard Henderson 34361766fe9SRichard Henderson /* We are exiting the TB, but have neither emitted a goto_tb, nor 34461766fe9SRichard Henderson updated the iaq for the next instruction to be executed. */ 345869051eaSRichard Henderson #define DISAS_IAQ_N_STALE DISAS_TARGET_1 34661766fe9SRichard Henderson 347e1b5a5edSRichard Henderson /* Similarly, but we want to return to the main loop immediately 348e1b5a5edSRichard Henderson to recognize unmasked interrupts. */ 349e1b5a5edSRichard Henderson #define DISAS_IAQ_N_STALE_EXIT DISAS_TARGET_2 350e1b5a5edSRichard Henderson 35161766fe9SRichard Henderson /* global register indexes */ 352eaa3783bSRichard Henderson static TCGv_reg cpu_gr[32]; 35333423472SRichard Henderson static TCGv_i64 cpu_sr[4]; 354494737b7SRichard Henderson static TCGv_i64 cpu_srH; 355eaa3783bSRichard Henderson static TCGv_reg cpu_iaoq_f; 356eaa3783bSRichard Henderson static TCGv_reg cpu_iaoq_b; 357c301f34eSRichard Henderson static TCGv_i64 cpu_iasq_f; 358c301f34eSRichard Henderson static TCGv_i64 cpu_iasq_b; 359eaa3783bSRichard Henderson static TCGv_reg cpu_sar; 360eaa3783bSRichard Henderson static TCGv_reg cpu_psw_n; 361eaa3783bSRichard Henderson static TCGv_reg cpu_psw_v; 362eaa3783bSRichard Henderson static TCGv_reg cpu_psw_cb; 363eaa3783bSRichard Henderson static TCGv_reg cpu_psw_cb_msb; 36461766fe9SRichard Henderson 36561766fe9SRichard Henderson #include "exec/gen-icount.h" 36661766fe9SRichard Henderson 36761766fe9SRichard Henderson void hppa_translate_init(void) 36861766fe9SRichard Henderson { 36961766fe9SRichard Henderson #define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUHPPAState, V) } 37061766fe9SRichard Henderson 371eaa3783bSRichard Henderson typedef struct { TCGv_reg *var; const char *name; int ofs; } GlobalVar; 37261766fe9SRichard Henderson static const GlobalVar vars[] = { 37335136a77SRichard Henderson { &cpu_sar, "sar", offsetof(CPUHPPAState, cr[CR_SAR]) }, 37461766fe9SRichard Henderson DEF_VAR(psw_n), 37561766fe9SRichard Henderson DEF_VAR(psw_v), 37661766fe9SRichard Henderson DEF_VAR(psw_cb), 37761766fe9SRichard Henderson DEF_VAR(psw_cb_msb), 37861766fe9SRichard Henderson DEF_VAR(iaoq_f), 37961766fe9SRichard Henderson DEF_VAR(iaoq_b), 38061766fe9SRichard Henderson }; 38161766fe9SRichard Henderson 38261766fe9SRichard Henderson #undef DEF_VAR 38361766fe9SRichard Henderson 38461766fe9SRichard Henderson /* Use the symbolic register names that match the disassembler. */ 38561766fe9SRichard Henderson static const char gr_names[32][4] = { 38661766fe9SRichard Henderson "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 38761766fe9SRichard Henderson "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 38861766fe9SRichard Henderson "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 38961766fe9SRichard Henderson "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 39061766fe9SRichard Henderson }; 39133423472SRichard Henderson /* SR[4-7] are not global registers so that we can index them. */ 392494737b7SRichard Henderson static const char sr_names[5][4] = { 393494737b7SRichard Henderson "sr0", "sr1", "sr2", "sr3", "srH" 39433423472SRichard Henderson }; 39561766fe9SRichard Henderson 39661766fe9SRichard Henderson int i; 39761766fe9SRichard Henderson 398f764718dSRichard Henderson cpu_gr[0] = NULL; 39961766fe9SRichard Henderson for (i = 1; i < 32; i++) { 40061766fe9SRichard Henderson cpu_gr[i] = tcg_global_mem_new(cpu_env, 40161766fe9SRichard Henderson offsetof(CPUHPPAState, gr[i]), 40261766fe9SRichard Henderson gr_names[i]); 40361766fe9SRichard Henderson } 40433423472SRichard Henderson for (i = 0; i < 4; i++) { 40533423472SRichard Henderson cpu_sr[i] = tcg_global_mem_new_i64(cpu_env, 40633423472SRichard Henderson offsetof(CPUHPPAState, sr[i]), 40733423472SRichard Henderson sr_names[i]); 40833423472SRichard Henderson } 409494737b7SRichard Henderson cpu_srH = tcg_global_mem_new_i64(cpu_env, 410494737b7SRichard Henderson offsetof(CPUHPPAState, sr[4]), 411494737b7SRichard Henderson sr_names[4]); 41261766fe9SRichard Henderson 41361766fe9SRichard Henderson for (i = 0; i < ARRAY_SIZE(vars); ++i) { 41461766fe9SRichard Henderson const GlobalVar *v = &vars[i]; 41561766fe9SRichard Henderson *v->var = tcg_global_mem_new(cpu_env, v->ofs, v->name); 41661766fe9SRichard Henderson } 417c301f34eSRichard Henderson 418c301f34eSRichard Henderson cpu_iasq_f = tcg_global_mem_new_i64(cpu_env, 419c301f34eSRichard Henderson offsetof(CPUHPPAState, iasq_f), 420c301f34eSRichard Henderson "iasq_f"); 421c301f34eSRichard Henderson cpu_iasq_b = tcg_global_mem_new_i64(cpu_env, 422c301f34eSRichard Henderson offsetof(CPUHPPAState, iasq_b), 423c301f34eSRichard Henderson "iasq_b"); 42461766fe9SRichard Henderson } 42561766fe9SRichard Henderson 426129e9cc3SRichard Henderson static DisasCond cond_make_f(void) 427129e9cc3SRichard Henderson { 428f764718dSRichard Henderson return (DisasCond){ 429f764718dSRichard Henderson .c = TCG_COND_NEVER, 430f764718dSRichard Henderson .a0 = NULL, 431f764718dSRichard Henderson .a1 = NULL, 432f764718dSRichard Henderson }; 433129e9cc3SRichard Henderson } 434129e9cc3SRichard Henderson 435df0232feSRichard Henderson static DisasCond cond_make_t(void) 436df0232feSRichard Henderson { 437df0232feSRichard Henderson return (DisasCond){ 438df0232feSRichard Henderson .c = TCG_COND_ALWAYS, 439df0232feSRichard Henderson .a0 = NULL, 440df0232feSRichard Henderson .a1 = NULL, 441df0232feSRichard Henderson }; 442df0232feSRichard Henderson } 443df0232feSRichard Henderson 444129e9cc3SRichard Henderson static DisasCond cond_make_n(void) 445129e9cc3SRichard Henderson { 446f764718dSRichard Henderson return (DisasCond){ 447f764718dSRichard Henderson .c = TCG_COND_NE, 448f764718dSRichard Henderson .a0 = cpu_psw_n, 449f764718dSRichard Henderson .a0_is_n = true, 450f764718dSRichard Henderson .a1 = NULL, 451f764718dSRichard Henderson .a1_is_0 = true 452f764718dSRichard Henderson }; 453129e9cc3SRichard Henderson } 454129e9cc3SRichard Henderson 455b47a4a02SSven Schnelle static DisasCond cond_make_0_tmp(TCGCond c, TCGv_reg a0) 456b47a4a02SSven Schnelle { 457b47a4a02SSven Schnelle assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS); 458b47a4a02SSven Schnelle return (DisasCond){ 459b47a4a02SSven Schnelle .c = c, .a0 = a0, .a1_is_0 = true 460b47a4a02SSven Schnelle }; 461b47a4a02SSven Schnelle } 462b47a4a02SSven Schnelle 463eaa3783bSRichard Henderson static DisasCond cond_make_0(TCGCond c, TCGv_reg a0) 464129e9cc3SRichard Henderson { 465b47a4a02SSven Schnelle TCGv_reg tmp = tcg_temp_new(); 466b47a4a02SSven Schnelle tcg_gen_mov_reg(tmp, a0); 467b47a4a02SSven Schnelle return cond_make_0_tmp(c, tmp); 468129e9cc3SRichard Henderson } 469129e9cc3SRichard Henderson 470eaa3783bSRichard Henderson static DisasCond cond_make(TCGCond c, TCGv_reg a0, TCGv_reg a1) 471129e9cc3SRichard Henderson { 472129e9cc3SRichard Henderson DisasCond r = { .c = c }; 473129e9cc3SRichard Henderson 474129e9cc3SRichard Henderson assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS); 475129e9cc3SRichard Henderson r.a0 = tcg_temp_new(); 476eaa3783bSRichard Henderson tcg_gen_mov_reg(r.a0, a0); 477129e9cc3SRichard Henderson r.a1 = tcg_temp_new(); 478eaa3783bSRichard Henderson tcg_gen_mov_reg(r.a1, a1); 479129e9cc3SRichard Henderson 480129e9cc3SRichard Henderson return r; 481129e9cc3SRichard Henderson } 482129e9cc3SRichard Henderson 483129e9cc3SRichard Henderson static void cond_prep(DisasCond *cond) 484129e9cc3SRichard Henderson { 485129e9cc3SRichard Henderson if (cond->a1_is_0) { 486129e9cc3SRichard Henderson cond->a1_is_0 = false; 487eaa3783bSRichard Henderson cond->a1 = tcg_const_reg(0); 488129e9cc3SRichard Henderson } 489129e9cc3SRichard Henderson } 490129e9cc3SRichard Henderson 491129e9cc3SRichard Henderson static void cond_free(DisasCond *cond) 492129e9cc3SRichard Henderson { 493129e9cc3SRichard Henderson switch (cond->c) { 494129e9cc3SRichard Henderson default: 495129e9cc3SRichard Henderson if (!cond->a0_is_n) { 496129e9cc3SRichard Henderson tcg_temp_free(cond->a0); 497129e9cc3SRichard Henderson } 498129e9cc3SRichard Henderson if (!cond->a1_is_0) { 499129e9cc3SRichard Henderson tcg_temp_free(cond->a1); 500129e9cc3SRichard Henderson } 501129e9cc3SRichard Henderson cond->a0_is_n = false; 502129e9cc3SRichard Henderson cond->a1_is_0 = false; 503f764718dSRichard Henderson cond->a0 = NULL; 504f764718dSRichard Henderson cond->a1 = NULL; 505129e9cc3SRichard Henderson /* fallthru */ 506129e9cc3SRichard Henderson case TCG_COND_ALWAYS: 507129e9cc3SRichard Henderson cond->c = TCG_COND_NEVER; 508129e9cc3SRichard Henderson break; 509129e9cc3SRichard Henderson case TCG_COND_NEVER: 510129e9cc3SRichard Henderson break; 511129e9cc3SRichard Henderson } 512129e9cc3SRichard Henderson } 513129e9cc3SRichard Henderson 514eaa3783bSRichard Henderson static TCGv_reg get_temp(DisasContext *ctx) 51561766fe9SRichard Henderson { 51686f8d05fSRichard Henderson unsigned i = ctx->ntempr++; 51786f8d05fSRichard Henderson g_assert(i < ARRAY_SIZE(ctx->tempr)); 51886f8d05fSRichard Henderson return ctx->tempr[i] = tcg_temp_new(); 51961766fe9SRichard Henderson } 52061766fe9SRichard Henderson 52186f8d05fSRichard Henderson #ifndef CONFIG_USER_ONLY 52286f8d05fSRichard Henderson static TCGv_tl get_temp_tl(DisasContext *ctx) 52386f8d05fSRichard Henderson { 52486f8d05fSRichard Henderson unsigned i = ctx->ntempl++; 52586f8d05fSRichard Henderson g_assert(i < ARRAY_SIZE(ctx->templ)); 52686f8d05fSRichard Henderson return ctx->templ[i] = tcg_temp_new_tl(); 52786f8d05fSRichard Henderson } 52886f8d05fSRichard Henderson #endif 52986f8d05fSRichard Henderson 530eaa3783bSRichard Henderson static TCGv_reg load_const(DisasContext *ctx, target_sreg v) 53161766fe9SRichard Henderson { 532eaa3783bSRichard Henderson TCGv_reg t = get_temp(ctx); 533eaa3783bSRichard Henderson tcg_gen_movi_reg(t, v); 53461766fe9SRichard Henderson return t; 53561766fe9SRichard Henderson } 53661766fe9SRichard Henderson 537eaa3783bSRichard Henderson static TCGv_reg load_gpr(DisasContext *ctx, unsigned reg) 53861766fe9SRichard Henderson { 53961766fe9SRichard Henderson if (reg == 0) { 540eaa3783bSRichard Henderson TCGv_reg t = get_temp(ctx); 541eaa3783bSRichard Henderson tcg_gen_movi_reg(t, 0); 54261766fe9SRichard Henderson return t; 54361766fe9SRichard Henderson } else { 54461766fe9SRichard Henderson return cpu_gr[reg]; 54561766fe9SRichard Henderson } 54661766fe9SRichard Henderson } 54761766fe9SRichard Henderson 548eaa3783bSRichard Henderson static TCGv_reg dest_gpr(DisasContext *ctx, unsigned reg) 54961766fe9SRichard Henderson { 550129e9cc3SRichard Henderson if (reg == 0 || ctx->null_cond.c != TCG_COND_NEVER) { 55161766fe9SRichard Henderson return get_temp(ctx); 55261766fe9SRichard Henderson } else { 55361766fe9SRichard Henderson return cpu_gr[reg]; 55461766fe9SRichard Henderson } 55561766fe9SRichard Henderson } 55661766fe9SRichard Henderson 557eaa3783bSRichard Henderson static void save_or_nullify(DisasContext *ctx, TCGv_reg dest, TCGv_reg t) 558129e9cc3SRichard Henderson { 559129e9cc3SRichard Henderson if (ctx->null_cond.c != TCG_COND_NEVER) { 560129e9cc3SRichard Henderson cond_prep(&ctx->null_cond); 561eaa3783bSRichard Henderson tcg_gen_movcond_reg(ctx->null_cond.c, dest, ctx->null_cond.a0, 562129e9cc3SRichard Henderson ctx->null_cond.a1, dest, t); 563129e9cc3SRichard Henderson } else { 564eaa3783bSRichard Henderson tcg_gen_mov_reg(dest, t); 565129e9cc3SRichard Henderson } 566129e9cc3SRichard Henderson } 567129e9cc3SRichard Henderson 568eaa3783bSRichard Henderson static void save_gpr(DisasContext *ctx, unsigned reg, TCGv_reg t) 569129e9cc3SRichard Henderson { 570129e9cc3SRichard Henderson if (reg != 0) { 571129e9cc3SRichard Henderson save_or_nullify(ctx, cpu_gr[reg], t); 572129e9cc3SRichard Henderson } 573129e9cc3SRichard Henderson } 574129e9cc3SRichard Henderson 57596d6407fSRichard Henderson #ifdef HOST_WORDS_BIGENDIAN 57696d6407fSRichard Henderson # define HI_OFS 0 57796d6407fSRichard Henderson # define LO_OFS 4 57896d6407fSRichard Henderson #else 57996d6407fSRichard Henderson # define HI_OFS 4 58096d6407fSRichard Henderson # define LO_OFS 0 58196d6407fSRichard Henderson #endif 58296d6407fSRichard Henderson 58396d6407fSRichard Henderson static TCGv_i32 load_frw_i32(unsigned rt) 58496d6407fSRichard Henderson { 58596d6407fSRichard Henderson TCGv_i32 ret = tcg_temp_new_i32(); 58696d6407fSRichard Henderson tcg_gen_ld_i32(ret, cpu_env, 58796d6407fSRichard Henderson offsetof(CPUHPPAState, fr[rt & 31]) 58896d6407fSRichard Henderson + (rt & 32 ? LO_OFS : HI_OFS)); 58996d6407fSRichard Henderson return ret; 59096d6407fSRichard Henderson } 59196d6407fSRichard Henderson 592ebe9383cSRichard Henderson static TCGv_i32 load_frw0_i32(unsigned rt) 593ebe9383cSRichard Henderson { 594ebe9383cSRichard Henderson if (rt == 0) { 595ebe9383cSRichard Henderson return tcg_const_i32(0); 596ebe9383cSRichard Henderson } else { 597ebe9383cSRichard Henderson return load_frw_i32(rt); 598ebe9383cSRichard Henderson } 599ebe9383cSRichard Henderson } 600ebe9383cSRichard Henderson 601ebe9383cSRichard Henderson static TCGv_i64 load_frw0_i64(unsigned rt) 602ebe9383cSRichard Henderson { 603ebe9383cSRichard Henderson if (rt == 0) { 604ebe9383cSRichard Henderson return tcg_const_i64(0); 605ebe9383cSRichard Henderson } else { 606ebe9383cSRichard Henderson TCGv_i64 ret = tcg_temp_new_i64(); 607ebe9383cSRichard Henderson tcg_gen_ld32u_i64(ret, cpu_env, 608ebe9383cSRichard Henderson offsetof(CPUHPPAState, fr[rt & 31]) 609ebe9383cSRichard Henderson + (rt & 32 ? LO_OFS : HI_OFS)); 610ebe9383cSRichard Henderson return ret; 611ebe9383cSRichard Henderson } 612ebe9383cSRichard Henderson } 613ebe9383cSRichard Henderson 61496d6407fSRichard Henderson static void save_frw_i32(unsigned rt, TCGv_i32 val) 61596d6407fSRichard Henderson { 61696d6407fSRichard Henderson tcg_gen_st_i32(val, cpu_env, 61796d6407fSRichard Henderson offsetof(CPUHPPAState, fr[rt & 31]) 61896d6407fSRichard Henderson + (rt & 32 ? LO_OFS : HI_OFS)); 61996d6407fSRichard Henderson } 62096d6407fSRichard Henderson 62196d6407fSRichard Henderson #undef HI_OFS 62296d6407fSRichard Henderson #undef LO_OFS 62396d6407fSRichard Henderson 62496d6407fSRichard Henderson static TCGv_i64 load_frd(unsigned rt) 62596d6407fSRichard Henderson { 62696d6407fSRichard Henderson TCGv_i64 ret = tcg_temp_new_i64(); 62796d6407fSRichard Henderson tcg_gen_ld_i64(ret, cpu_env, offsetof(CPUHPPAState, fr[rt])); 62896d6407fSRichard Henderson return ret; 62996d6407fSRichard Henderson } 63096d6407fSRichard Henderson 631ebe9383cSRichard Henderson static TCGv_i64 load_frd0(unsigned rt) 632ebe9383cSRichard Henderson { 633ebe9383cSRichard Henderson if (rt == 0) { 634ebe9383cSRichard Henderson return tcg_const_i64(0); 635ebe9383cSRichard Henderson } else { 636ebe9383cSRichard Henderson return load_frd(rt); 637ebe9383cSRichard Henderson } 638ebe9383cSRichard Henderson } 639ebe9383cSRichard Henderson 64096d6407fSRichard Henderson static void save_frd(unsigned rt, TCGv_i64 val) 64196d6407fSRichard Henderson { 64296d6407fSRichard Henderson tcg_gen_st_i64(val, cpu_env, offsetof(CPUHPPAState, fr[rt])); 64396d6407fSRichard Henderson } 64496d6407fSRichard Henderson 64533423472SRichard Henderson static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg) 64633423472SRichard Henderson { 64733423472SRichard Henderson #ifdef CONFIG_USER_ONLY 64833423472SRichard Henderson tcg_gen_movi_i64(dest, 0); 64933423472SRichard Henderson #else 65033423472SRichard Henderson if (reg < 4) { 65133423472SRichard Henderson tcg_gen_mov_i64(dest, cpu_sr[reg]); 652494737b7SRichard Henderson } else if (ctx->tb_flags & TB_FLAG_SR_SAME) { 653494737b7SRichard Henderson tcg_gen_mov_i64(dest, cpu_srH); 65433423472SRichard Henderson } else { 65533423472SRichard Henderson tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUHPPAState, sr[reg])); 65633423472SRichard Henderson } 65733423472SRichard Henderson #endif 65833423472SRichard Henderson } 65933423472SRichard Henderson 660129e9cc3SRichard Henderson /* Skip over the implementation of an insn that has been nullified. 661129e9cc3SRichard Henderson Use this when the insn is too complex for a conditional move. */ 662129e9cc3SRichard Henderson static void nullify_over(DisasContext *ctx) 663129e9cc3SRichard Henderson { 664129e9cc3SRichard Henderson if (ctx->null_cond.c != TCG_COND_NEVER) { 665129e9cc3SRichard Henderson /* The always condition should have been handled in the main loop. */ 666129e9cc3SRichard Henderson assert(ctx->null_cond.c != TCG_COND_ALWAYS); 667129e9cc3SRichard Henderson 668129e9cc3SRichard Henderson ctx->null_lab = gen_new_label(); 669129e9cc3SRichard Henderson cond_prep(&ctx->null_cond); 670129e9cc3SRichard Henderson 671129e9cc3SRichard Henderson /* If we're using PSW[N], copy it to a temp because... */ 672129e9cc3SRichard Henderson if (ctx->null_cond.a0_is_n) { 673129e9cc3SRichard Henderson ctx->null_cond.a0_is_n = false; 674129e9cc3SRichard Henderson ctx->null_cond.a0 = tcg_temp_new(); 675eaa3783bSRichard Henderson tcg_gen_mov_reg(ctx->null_cond.a0, cpu_psw_n); 676129e9cc3SRichard Henderson } 677129e9cc3SRichard Henderson /* ... we clear it before branching over the implementation, 678129e9cc3SRichard Henderson so that (1) it's clear after nullifying this insn and 679129e9cc3SRichard Henderson (2) if this insn nullifies the next, PSW[N] is valid. */ 680129e9cc3SRichard Henderson if (ctx->psw_n_nonzero) { 681129e9cc3SRichard Henderson ctx->psw_n_nonzero = false; 682eaa3783bSRichard Henderson tcg_gen_movi_reg(cpu_psw_n, 0); 683129e9cc3SRichard Henderson } 684129e9cc3SRichard Henderson 685eaa3783bSRichard Henderson tcg_gen_brcond_reg(ctx->null_cond.c, ctx->null_cond.a0, 686129e9cc3SRichard Henderson ctx->null_cond.a1, ctx->null_lab); 687129e9cc3SRichard Henderson cond_free(&ctx->null_cond); 688129e9cc3SRichard Henderson } 689129e9cc3SRichard Henderson } 690129e9cc3SRichard Henderson 691129e9cc3SRichard Henderson /* Save the current nullification state to PSW[N]. */ 692129e9cc3SRichard Henderson static void nullify_save(DisasContext *ctx) 693129e9cc3SRichard Henderson { 694129e9cc3SRichard Henderson if (ctx->null_cond.c == TCG_COND_NEVER) { 695129e9cc3SRichard Henderson if (ctx->psw_n_nonzero) { 696eaa3783bSRichard Henderson tcg_gen_movi_reg(cpu_psw_n, 0); 697129e9cc3SRichard Henderson } 698129e9cc3SRichard Henderson return; 699129e9cc3SRichard Henderson } 700129e9cc3SRichard Henderson if (!ctx->null_cond.a0_is_n) { 701129e9cc3SRichard Henderson cond_prep(&ctx->null_cond); 702eaa3783bSRichard Henderson tcg_gen_setcond_reg(ctx->null_cond.c, cpu_psw_n, 703129e9cc3SRichard Henderson ctx->null_cond.a0, ctx->null_cond.a1); 704129e9cc3SRichard Henderson ctx->psw_n_nonzero = true; 705129e9cc3SRichard Henderson } 706129e9cc3SRichard Henderson cond_free(&ctx->null_cond); 707129e9cc3SRichard Henderson } 708129e9cc3SRichard Henderson 709129e9cc3SRichard Henderson /* Set a PSW[N] to X. The intention is that this is used immediately 710129e9cc3SRichard Henderson before a goto_tb/exit_tb, so that there is no fallthru path to other 711129e9cc3SRichard Henderson code within the TB. Therefore we do not update psw_n_nonzero. */ 712129e9cc3SRichard Henderson static void nullify_set(DisasContext *ctx, bool x) 713129e9cc3SRichard Henderson { 714129e9cc3SRichard Henderson if (ctx->psw_n_nonzero || x) { 715eaa3783bSRichard Henderson tcg_gen_movi_reg(cpu_psw_n, x); 716129e9cc3SRichard Henderson } 717129e9cc3SRichard Henderson } 718129e9cc3SRichard Henderson 719129e9cc3SRichard Henderson /* Mark the end of an instruction that may have been nullified. 72040f9f908SRichard Henderson This is the pair to nullify_over. Always returns true so that 72140f9f908SRichard Henderson it may be tail-called from a translate function. */ 72231234768SRichard Henderson static bool nullify_end(DisasContext *ctx) 723129e9cc3SRichard Henderson { 724129e9cc3SRichard Henderson TCGLabel *null_lab = ctx->null_lab; 72531234768SRichard Henderson DisasJumpType status = ctx->base.is_jmp; 726129e9cc3SRichard Henderson 727f49b3537SRichard Henderson /* For NEXT, NORETURN, STALE, we can easily continue (or exit). 728f49b3537SRichard Henderson For UPDATED, we cannot update on the nullified path. */ 729f49b3537SRichard Henderson assert(status != DISAS_IAQ_N_UPDATED); 730f49b3537SRichard Henderson 731129e9cc3SRichard Henderson if (likely(null_lab == NULL)) { 732129e9cc3SRichard Henderson /* The current insn wasn't conditional or handled the condition 733129e9cc3SRichard Henderson applied to it without a branch, so the (new) setting of 734129e9cc3SRichard Henderson NULL_COND can be applied directly to the next insn. */ 73531234768SRichard Henderson return true; 736129e9cc3SRichard Henderson } 737129e9cc3SRichard Henderson ctx->null_lab = NULL; 738129e9cc3SRichard Henderson 739129e9cc3SRichard Henderson if (likely(ctx->null_cond.c == TCG_COND_NEVER)) { 740129e9cc3SRichard Henderson /* The next instruction will be unconditional, 741129e9cc3SRichard Henderson and NULL_COND already reflects that. */ 742129e9cc3SRichard Henderson gen_set_label(null_lab); 743129e9cc3SRichard Henderson } else { 744129e9cc3SRichard Henderson /* The insn that we just executed is itself nullifying the next 745129e9cc3SRichard Henderson instruction. Store the condition in the PSW[N] global. 746129e9cc3SRichard Henderson We asserted PSW[N] = 0 in nullify_over, so that after the 747129e9cc3SRichard Henderson label we have the proper value in place. */ 748129e9cc3SRichard Henderson nullify_save(ctx); 749129e9cc3SRichard Henderson gen_set_label(null_lab); 750129e9cc3SRichard Henderson ctx->null_cond = cond_make_n(); 751129e9cc3SRichard Henderson } 752869051eaSRichard Henderson if (status == DISAS_NORETURN) { 75331234768SRichard Henderson ctx->base.is_jmp = DISAS_NEXT; 754129e9cc3SRichard Henderson } 75531234768SRichard Henderson return true; 756129e9cc3SRichard Henderson } 757129e9cc3SRichard Henderson 758eaa3783bSRichard Henderson static void copy_iaoq_entry(TCGv_reg dest, target_ureg ival, TCGv_reg vval) 75961766fe9SRichard Henderson { 76061766fe9SRichard Henderson if (unlikely(ival == -1)) { 761eaa3783bSRichard Henderson tcg_gen_mov_reg(dest, vval); 76261766fe9SRichard Henderson } else { 763eaa3783bSRichard Henderson tcg_gen_movi_reg(dest, ival); 76461766fe9SRichard Henderson } 76561766fe9SRichard Henderson } 76661766fe9SRichard Henderson 767eaa3783bSRichard Henderson static inline target_ureg iaoq_dest(DisasContext *ctx, target_sreg disp) 76861766fe9SRichard Henderson { 76961766fe9SRichard Henderson return ctx->iaoq_f + disp + 8; 77061766fe9SRichard Henderson } 77161766fe9SRichard Henderson 77261766fe9SRichard Henderson static void gen_excp_1(int exception) 77361766fe9SRichard Henderson { 77461766fe9SRichard Henderson TCGv_i32 t = tcg_const_i32(exception); 77561766fe9SRichard Henderson gen_helper_excp(cpu_env, t); 77661766fe9SRichard Henderson tcg_temp_free_i32(t); 77761766fe9SRichard Henderson } 77861766fe9SRichard Henderson 77931234768SRichard Henderson static void gen_excp(DisasContext *ctx, int exception) 78061766fe9SRichard Henderson { 78161766fe9SRichard Henderson copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); 78261766fe9SRichard Henderson copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); 783129e9cc3SRichard Henderson nullify_save(ctx); 78461766fe9SRichard Henderson gen_excp_1(exception); 78531234768SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 78661766fe9SRichard Henderson } 78761766fe9SRichard Henderson 78831234768SRichard Henderson static bool gen_excp_iir(DisasContext *ctx, int exc) 7891a19da0dSRichard Henderson { 79031234768SRichard Henderson TCGv_reg tmp; 79131234768SRichard Henderson 79231234768SRichard Henderson nullify_over(ctx); 79331234768SRichard Henderson tmp = tcg_const_reg(ctx->insn); 7941a19da0dSRichard Henderson tcg_gen_st_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[CR_IIR])); 7951a19da0dSRichard Henderson tcg_temp_free(tmp); 79631234768SRichard Henderson gen_excp(ctx, exc); 79731234768SRichard Henderson return nullify_end(ctx); 7981a19da0dSRichard Henderson } 7991a19da0dSRichard Henderson 80031234768SRichard Henderson static bool gen_illegal(DisasContext *ctx) 80161766fe9SRichard Henderson { 80231234768SRichard Henderson return gen_excp_iir(ctx, EXCP_ILL); 80361766fe9SRichard Henderson } 80461766fe9SRichard Henderson 80540f9f908SRichard Henderson #ifdef CONFIG_USER_ONLY 80640f9f908SRichard Henderson #define CHECK_MOST_PRIVILEGED(EXCP) \ 80740f9f908SRichard Henderson return gen_excp_iir(ctx, EXCP) 80840f9f908SRichard Henderson #else 809e1b5a5edSRichard Henderson #define CHECK_MOST_PRIVILEGED(EXCP) \ 810e1b5a5edSRichard Henderson do { \ 811e1b5a5edSRichard Henderson if (ctx->privilege != 0) { \ 81231234768SRichard Henderson return gen_excp_iir(ctx, EXCP); \ 813e1b5a5edSRichard Henderson } \ 814e1b5a5edSRichard Henderson } while (0) 81540f9f908SRichard Henderson #endif 816e1b5a5edSRichard Henderson 817eaa3783bSRichard Henderson static bool use_goto_tb(DisasContext *ctx, target_ureg dest) 81861766fe9SRichard Henderson { 81961766fe9SRichard Henderson /* Suppress goto_tb in the case of single-steping and IO. */ 82031234768SRichard Henderson if ((tb_cflags(ctx->base.tb) & CF_LAST_IO) 82131234768SRichard Henderson || ctx->base.singlestep_enabled) { 82261766fe9SRichard Henderson return false; 82361766fe9SRichard Henderson } 82461766fe9SRichard Henderson return true; 82561766fe9SRichard Henderson } 82661766fe9SRichard Henderson 827129e9cc3SRichard Henderson /* If the next insn is to be nullified, and it's on the same page, 828129e9cc3SRichard Henderson and we're not attempting to set a breakpoint on it, then we can 829129e9cc3SRichard Henderson totally skip the nullified insn. This avoids creating and 830129e9cc3SRichard Henderson executing a TB that merely branches to the next TB. */ 831129e9cc3SRichard Henderson static bool use_nullify_skip(DisasContext *ctx) 832129e9cc3SRichard Henderson { 833129e9cc3SRichard Henderson return (((ctx->iaoq_b ^ ctx->iaoq_f) & TARGET_PAGE_MASK) == 0 834129e9cc3SRichard Henderson && !cpu_breakpoint_test(ctx->cs, ctx->iaoq_b, BP_ANY)); 835129e9cc3SRichard Henderson } 836129e9cc3SRichard Henderson 83761766fe9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int which, 838eaa3783bSRichard Henderson target_ureg f, target_ureg b) 83961766fe9SRichard Henderson { 84061766fe9SRichard Henderson if (f != -1 && b != -1 && use_goto_tb(ctx, f)) { 84161766fe9SRichard Henderson tcg_gen_goto_tb(which); 842eaa3783bSRichard Henderson tcg_gen_movi_reg(cpu_iaoq_f, f); 843eaa3783bSRichard Henderson tcg_gen_movi_reg(cpu_iaoq_b, b); 84407ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, which); 84561766fe9SRichard Henderson } else { 84661766fe9SRichard Henderson copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b); 84761766fe9SRichard Henderson copy_iaoq_entry(cpu_iaoq_b, b, ctx->iaoq_n_var); 848d01a3625SRichard Henderson if (ctx->base.singlestep_enabled) { 84961766fe9SRichard Henderson gen_excp_1(EXCP_DEBUG); 85061766fe9SRichard Henderson } else { 8517f11636dSEmilio G. Cota tcg_gen_lookup_and_goto_ptr(); 85261766fe9SRichard Henderson } 85361766fe9SRichard Henderson } 85461766fe9SRichard Henderson } 85561766fe9SRichard Henderson 856b47a4a02SSven Schnelle static bool cond_need_sv(int c) 857b47a4a02SSven Schnelle { 858b47a4a02SSven Schnelle return c == 2 || c == 3 || c == 6; 859b47a4a02SSven Schnelle } 860b47a4a02SSven Schnelle 861b47a4a02SSven Schnelle static bool cond_need_cb(int c) 862b47a4a02SSven Schnelle { 863b47a4a02SSven Schnelle return c == 4 || c == 5; 864b47a4a02SSven Schnelle } 865b47a4a02SSven Schnelle 866b47a4a02SSven Schnelle /* 867b47a4a02SSven Schnelle * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of 868b47a4a02SSven Schnelle * the Parisc 1.1 Architecture Reference Manual for details. 869b47a4a02SSven Schnelle */ 870b2167459SRichard Henderson 871eaa3783bSRichard Henderson static DisasCond do_cond(unsigned cf, TCGv_reg res, 872eaa3783bSRichard Henderson TCGv_reg cb_msb, TCGv_reg sv) 873b2167459SRichard Henderson { 874b2167459SRichard Henderson DisasCond cond; 875eaa3783bSRichard Henderson TCGv_reg tmp; 876b2167459SRichard Henderson 877b2167459SRichard Henderson switch (cf >> 1) { 878b47a4a02SSven Schnelle case 0: /* Never / TR (0 / 1) */ 879b2167459SRichard Henderson cond = cond_make_f(); 880b2167459SRichard Henderson break; 881b2167459SRichard Henderson case 1: /* = / <> (Z / !Z) */ 882b2167459SRichard Henderson cond = cond_make_0(TCG_COND_EQ, res); 883b2167459SRichard Henderson break; 884b47a4a02SSven Schnelle case 2: /* < / >= (N ^ V / !(N ^ V) */ 885b47a4a02SSven Schnelle tmp = tcg_temp_new(); 886b47a4a02SSven Schnelle tcg_gen_xor_reg(tmp, res, sv); 887b47a4a02SSven Schnelle cond = cond_make_0_tmp(TCG_COND_LT, tmp); 888b2167459SRichard Henderson break; 889b47a4a02SSven Schnelle case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */ 890b47a4a02SSven Schnelle /* 891b47a4a02SSven Schnelle * Simplify: 892b47a4a02SSven Schnelle * (N ^ V) | Z 893b47a4a02SSven Schnelle * ((res < 0) ^ (sv < 0)) | !res 894b47a4a02SSven Schnelle * ((res ^ sv) < 0) | !res 895b47a4a02SSven Schnelle * (~(res ^ sv) >= 0) | !res 896b47a4a02SSven Schnelle * !(~(res ^ sv) >> 31) | !res 897b47a4a02SSven Schnelle * !(~(res ^ sv) >> 31 & res) 898b47a4a02SSven Schnelle */ 899b47a4a02SSven Schnelle tmp = tcg_temp_new(); 900b47a4a02SSven Schnelle tcg_gen_eqv_reg(tmp, res, sv); 901b47a4a02SSven Schnelle tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); 902b47a4a02SSven Schnelle tcg_gen_and_reg(tmp, tmp, res); 903b47a4a02SSven Schnelle cond = cond_make_0_tmp(TCG_COND_EQ, tmp); 904b2167459SRichard Henderson break; 905b2167459SRichard Henderson case 4: /* NUV / UV (!C / C) */ 906b2167459SRichard Henderson cond = cond_make_0(TCG_COND_EQ, cb_msb); 907b2167459SRichard Henderson break; 908b2167459SRichard Henderson case 5: /* ZNV / VNZ (!C | Z / C & !Z) */ 909b2167459SRichard Henderson tmp = tcg_temp_new(); 910eaa3783bSRichard Henderson tcg_gen_neg_reg(tmp, cb_msb); 911eaa3783bSRichard Henderson tcg_gen_and_reg(tmp, tmp, res); 912b47a4a02SSven Schnelle cond = cond_make_0_tmp(TCG_COND_EQ, tmp); 913b2167459SRichard Henderson break; 914b2167459SRichard Henderson case 6: /* SV / NSV (V / !V) */ 915b2167459SRichard Henderson cond = cond_make_0(TCG_COND_LT, sv); 916b2167459SRichard Henderson break; 917b2167459SRichard Henderson case 7: /* OD / EV */ 918b2167459SRichard Henderson tmp = tcg_temp_new(); 919eaa3783bSRichard Henderson tcg_gen_andi_reg(tmp, res, 1); 920b47a4a02SSven Schnelle cond = cond_make_0_tmp(TCG_COND_NE, tmp); 921b2167459SRichard Henderson break; 922b2167459SRichard Henderson default: 923b2167459SRichard Henderson g_assert_not_reached(); 924b2167459SRichard Henderson } 925b2167459SRichard Henderson if (cf & 1) { 926b2167459SRichard Henderson cond.c = tcg_invert_cond(cond.c); 927b2167459SRichard Henderson } 928b2167459SRichard Henderson 929b2167459SRichard Henderson return cond; 930b2167459SRichard Henderson } 931b2167459SRichard Henderson 932b2167459SRichard Henderson /* Similar, but for the special case of subtraction without borrow, we 933b2167459SRichard Henderson can use the inputs directly. This can allow other computation to be 934b2167459SRichard Henderson deleted as unused. */ 935b2167459SRichard Henderson 936eaa3783bSRichard Henderson static DisasCond do_sub_cond(unsigned cf, TCGv_reg res, 937eaa3783bSRichard Henderson TCGv_reg in1, TCGv_reg in2, TCGv_reg sv) 938b2167459SRichard Henderson { 939b2167459SRichard Henderson DisasCond cond; 940b2167459SRichard Henderson 941b2167459SRichard Henderson switch (cf >> 1) { 942b2167459SRichard Henderson case 1: /* = / <> */ 943b2167459SRichard Henderson cond = cond_make(TCG_COND_EQ, in1, in2); 944b2167459SRichard Henderson break; 945b2167459SRichard Henderson case 2: /* < / >= */ 946b2167459SRichard Henderson cond = cond_make(TCG_COND_LT, in1, in2); 947b2167459SRichard Henderson break; 948b2167459SRichard Henderson case 3: /* <= / > */ 949b2167459SRichard Henderson cond = cond_make(TCG_COND_LE, in1, in2); 950b2167459SRichard Henderson break; 951b2167459SRichard Henderson case 4: /* << / >>= */ 952b2167459SRichard Henderson cond = cond_make(TCG_COND_LTU, in1, in2); 953b2167459SRichard Henderson break; 954b2167459SRichard Henderson case 5: /* <<= / >> */ 955b2167459SRichard Henderson cond = cond_make(TCG_COND_LEU, in1, in2); 956b2167459SRichard Henderson break; 957b2167459SRichard Henderson default: 958b47a4a02SSven Schnelle return do_cond(cf, res, NULL, sv); 959b2167459SRichard Henderson } 960b2167459SRichard Henderson if (cf & 1) { 961b2167459SRichard Henderson cond.c = tcg_invert_cond(cond.c); 962b2167459SRichard Henderson } 963b2167459SRichard Henderson 964b2167459SRichard Henderson return cond; 965b2167459SRichard Henderson } 966b2167459SRichard Henderson 967df0232feSRichard Henderson /* 968df0232feSRichard Henderson * Similar, but for logicals, where the carry and overflow bits are not 969df0232feSRichard Henderson * computed, and use of them is undefined. 970df0232feSRichard Henderson * 971df0232feSRichard Henderson * Undefined or not, hardware does not trap. It seems reasonable to 972df0232feSRichard Henderson * assume hardware treats cases c={4,5,6} as if C=0 & V=0, since that's 973df0232feSRichard Henderson * how cases c={2,3} are treated. 974df0232feSRichard Henderson */ 975b2167459SRichard Henderson 976eaa3783bSRichard Henderson static DisasCond do_log_cond(unsigned cf, TCGv_reg res) 977b2167459SRichard Henderson { 978df0232feSRichard Henderson switch (cf) { 979df0232feSRichard Henderson case 0: /* never */ 980df0232feSRichard Henderson case 9: /* undef, C */ 981df0232feSRichard Henderson case 11: /* undef, C & !Z */ 982df0232feSRichard Henderson case 12: /* undef, V */ 983df0232feSRichard Henderson return cond_make_f(); 984df0232feSRichard Henderson 985df0232feSRichard Henderson case 1: /* true */ 986df0232feSRichard Henderson case 8: /* undef, !C */ 987df0232feSRichard Henderson case 10: /* undef, !C | Z */ 988df0232feSRichard Henderson case 13: /* undef, !V */ 989df0232feSRichard Henderson return cond_make_t(); 990df0232feSRichard Henderson 991df0232feSRichard Henderson case 2: /* == */ 992df0232feSRichard Henderson return cond_make_0(TCG_COND_EQ, res); 993df0232feSRichard Henderson case 3: /* <> */ 994df0232feSRichard Henderson return cond_make_0(TCG_COND_NE, res); 995df0232feSRichard Henderson case 4: /* < */ 996df0232feSRichard Henderson return cond_make_0(TCG_COND_LT, res); 997df0232feSRichard Henderson case 5: /* >= */ 998df0232feSRichard Henderson return cond_make_0(TCG_COND_GE, res); 999df0232feSRichard Henderson case 6: /* <= */ 1000df0232feSRichard Henderson return cond_make_0(TCG_COND_LE, res); 1001df0232feSRichard Henderson case 7: /* > */ 1002df0232feSRichard Henderson return cond_make_0(TCG_COND_GT, res); 1003df0232feSRichard Henderson 1004df0232feSRichard Henderson case 14: /* OD */ 1005df0232feSRichard Henderson case 15: /* EV */ 1006df0232feSRichard Henderson return do_cond(cf, res, NULL, NULL); 1007df0232feSRichard Henderson 1008df0232feSRichard Henderson default: 1009df0232feSRichard Henderson g_assert_not_reached(); 1010b2167459SRichard Henderson } 1011b2167459SRichard Henderson } 1012b2167459SRichard Henderson 101398cd9ca7SRichard Henderson /* Similar, but for shift/extract/deposit conditions. */ 101498cd9ca7SRichard Henderson 1015eaa3783bSRichard Henderson static DisasCond do_sed_cond(unsigned orig, TCGv_reg res) 101698cd9ca7SRichard Henderson { 101798cd9ca7SRichard Henderson unsigned c, f; 101898cd9ca7SRichard Henderson 101998cd9ca7SRichard Henderson /* Convert the compressed condition codes to standard. 102098cd9ca7SRichard Henderson 0-2 are the same as logicals (nv,<,<=), while 3 is OD. 102198cd9ca7SRichard Henderson 4-7 are the reverse of 0-3. */ 102298cd9ca7SRichard Henderson c = orig & 3; 102398cd9ca7SRichard Henderson if (c == 3) { 102498cd9ca7SRichard Henderson c = 7; 102598cd9ca7SRichard Henderson } 102698cd9ca7SRichard Henderson f = (orig & 4) / 4; 102798cd9ca7SRichard Henderson 102898cd9ca7SRichard Henderson return do_log_cond(c * 2 + f, res); 102998cd9ca7SRichard Henderson } 103098cd9ca7SRichard Henderson 1031b2167459SRichard Henderson /* Similar, but for unit conditions. */ 1032b2167459SRichard Henderson 1033eaa3783bSRichard Henderson static DisasCond do_unit_cond(unsigned cf, TCGv_reg res, 1034eaa3783bSRichard Henderson TCGv_reg in1, TCGv_reg in2) 1035b2167459SRichard Henderson { 1036b2167459SRichard Henderson DisasCond cond; 1037eaa3783bSRichard Henderson TCGv_reg tmp, cb = NULL; 1038b2167459SRichard Henderson 1039b2167459SRichard Henderson if (cf & 8) { 1040b2167459SRichard Henderson /* Since we want to test lots of carry-out bits all at once, do not 1041b2167459SRichard Henderson * do our normal thing and compute carry-in of bit B+1 since that 1042b2167459SRichard Henderson * leaves us with carry bits spread across two words. 1043b2167459SRichard Henderson */ 1044b2167459SRichard Henderson cb = tcg_temp_new(); 1045b2167459SRichard Henderson tmp = tcg_temp_new(); 1046eaa3783bSRichard Henderson tcg_gen_or_reg(cb, in1, in2); 1047eaa3783bSRichard Henderson tcg_gen_and_reg(tmp, in1, in2); 1048eaa3783bSRichard Henderson tcg_gen_andc_reg(cb, cb, res); 1049eaa3783bSRichard Henderson tcg_gen_or_reg(cb, cb, tmp); 1050b2167459SRichard Henderson tcg_temp_free(tmp); 1051b2167459SRichard Henderson } 1052b2167459SRichard Henderson 1053b2167459SRichard Henderson switch (cf >> 1) { 1054b2167459SRichard Henderson case 0: /* never / TR */ 1055b2167459SRichard Henderson case 1: /* undefined */ 1056b2167459SRichard Henderson case 5: /* undefined */ 1057b2167459SRichard Henderson cond = cond_make_f(); 1058b2167459SRichard Henderson break; 1059b2167459SRichard Henderson 1060b2167459SRichard Henderson case 2: /* SBZ / NBZ */ 1061b2167459SRichard Henderson /* See hasless(v,1) from 1062b2167459SRichard Henderson * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord 1063b2167459SRichard Henderson */ 1064b2167459SRichard Henderson tmp = tcg_temp_new(); 1065eaa3783bSRichard Henderson tcg_gen_subi_reg(tmp, res, 0x01010101u); 1066eaa3783bSRichard Henderson tcg_gen_andc_reg(tmp, tmp, res); 1067eaa3783bSRichard Henderson tcg_gen_andi_reg(tmp, tmp, 0x80808080u); 1068b2167459SRichard Henderson cond = cond_make_0(TCG_COND_NE, tmp); 1069b2167459SRichard Henderson tcg_temp_free(tmp); 1070b2167459SRichard Henderson break; 1071b2167459SRichard Henderson 1072b2167459SRichard Henderson case 3: /* SHZ / NHZ */ 1073b2167459SRichard Henderson tmp = tcg_temp_new(); 1074eaa3783bSRichard Henderson tcg_gen_subi_reg(tmp, res, 0x00010001u); 1075eaa3783bSRichard Henderson tcg_gen_andc_reg(tmp, tmp, res); 1076eaa3783bSRichard Henderson tcg_gen_andi_reg(tmp, tmp, 0x80008000u); 1077b2167459SRichard Henderson cond = cond_make_0(TCG_COND_NE, tmp); 1078b2167459SRichard Henderson tcg_temp_free(tmp); 1079b2167459SRichard Henderson break; 1080b2167459SRichard Henderson 1081b2167459SRichard Henderson case 4: /* SDC / NDC */ 1082eaa3783bSRichard Henderson tcg_gen_andi_reg(cb, cb, 0x88888888u); 1083b2167459SRichard Henderson cond = cond_make_0(TCG_COND_NE, cb); 1084b2167459SRichard Henderson break; 1085b2167459SRichard Henderson 1086b2167459SRichard Henderson case 6: /* SBC / NBC */ 1087eaa3783bSRichard Henderson tcg_gen_andi_reg(cb, cb, 0x80808080u); 1088b2167459SRichard Henderson cond = cond_make_0(TCG_COND_NE, cb); 1089b2167459SRichard Henderson break; 1090b2167459SRichard Henderson 1091b2167459SRichard Henderson case 7: /* SHC / NHC */ 1092eaa3783bSRichard Henderson tcg_gen_andi_reg(cb, cb, 0x80008000u); 1093b2167459SRichard Henderson cond = cond_make_0(TCG_COND_NE, cb); 1094b2167459SRichard Henderson break; 1095b2167459SRichard Henderson 1096b2167459SRichard Henderson default: 1097b2167459SRichard Henderson g_assert_not_reached(); 1098b2167459SRichard Henderson } 1099b2167459SRichard Henderson if (cf & 8) { 1100b2167459SRichard Henderson tcg_temp_free(cb); 1101b2167459SRichard Henderson } 1102b2167459SRichard Henderson if (cf & 1) { 1103b2167459SRichard Henderson cond.c = tcg_invert_cond(cond.c); 1104b2167459SRichard Henderson } 1105b2167459SRichard Henderson 1106b2167459SRichard Henderson return cond; 1107b2167459SRichard Henderson } 1108b2167459SRichard Henderson 1109b2167459SRichard Henderson /* Compute signed overflow for addition. */ 1110eaa3783bSRichard Henderson static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg res, 1111eaa3783bSRichard Henderson TCGv_reg in1, TCGv_reg in2) 1112b2167459SRichard Henderson { 1113eaa3783bSRichard Henderson TCGv_reg sv = get_temp(ctx); 1114eaa3783bSRichard Henderson TCGv_reg tmp = tcg_temp_new(); 1115b2167459SRichard Henderson 1116eaa3783bSRichard Henderson tcg_gen_xor_reg(sv, res, in1); 1117eaa3783bSRichard Henderson tcg_gen_xor_reg(tmp, in1, in2); 1118eaa3783bSRichard Henderson tcg_gen_andc_reg(sv, sv, tmp); 1119b2167459SRichard Henderson tcg_temp_free(tmp); 1120b2167459SRichard Henderson 1121b2167459SRichard Henderson return sv; 1122b2167459SRichard Henderson } 1123b2167459SRichard Henderson 1124b2167459SRichard Henderson /* Compute signed overflow for subtraction. */ 1125eaa3783bSRichard Henderson static TCGv_reg do_sub_sv(DisasContext *ctx, TCGv_reg res, 1126eaa3783bSRichard Henderson TCGv_reg in1, TCGv_reg in2) 1127b2167459SRichard Henderson { 1128eaa3783bSRichard Henderson TCGv_reg sv = get_temp(ctx); 1129eaa3783bSRichard Henderson TCGv_reg tmp = tcg_temp_new(); 1130b2167459SRichard Henderson 1131eaa3783bSRichard Henderson tcg_gen_xor_reg(sv, res, in1); 1132eaa3783bSRichard Henderson tcg_gen_xor_reg(tmp, in1, in2); 1133eaa3783bSRichard Henderson tcg_gen_and_reg(sv, sv, tmp); 1134b2167459SRichard Henderson tcg_temp_free(tmp); 1135b2167459SRichard Henderson 1136b2167459SRichard Henderson return sv; 1137b2167459SRichard Henderson } 1138b2167459SRichard Henderson 113931234768SRichard Henderson static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1, 1140eaa3783bSRichard Henderson TCGv_reg in2, unsigned shift, bool is_l, 1141eaa3783bSRichard Henderson bool is_tsv, bool is_tc, bool is_c, unsigned cf) 1142b2167459SRichard Henderson { 1143eaa3783bSRichard Henderson TCGv_reg dest, cb, cb_msb, sv, tmp; 1144b2167459SRichard Henderson unsigned c = cf >> 1; 1145b2167459SRichard Henderson DisasCond cond; 1146b2167459SRichard Henderson 1147b2167459SRichard Henderson dest = tcg_temp_new(); 1148f764718dSRichard Henderson cb = NULL; 1149f764718dSRichard Henderson cb_msb = NULL; 1150b2167459SRichard Henderson 1151b2167459SRichard Henderson if (shift) { 1152b2167459SRichard Henderson tmp = get_temp(ctx); 1153eaa3783bSRichard Henderson tcg_gen_shli_reg(tmp, in1, shift); 1154b2167459SRichard Henderson in1 = tmp; 1155b2167459SRichard Henderson } 1156b2167459SRichard Henderson 1157b47a4a02SSven Schnelle if (!is_l || cond_need_cb(c)) { 1158eaa3783bSRichard Henderson TCGv_reg zero = tcg_const_reg(0); 1159b2167459SRichard Henderson cb_msb = get_temp(ctx); 1160eaa3783bSRichard Henderson tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero); 1161b2167459SRichard Henderson if (is_c) { 1162eaa3783bSRichard Henderson tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cpu_psw_cb_msb, zero); 1163b2167459SRichard Henderson } 1164b2167459SRichard Henderson tcg_temp_free(zero); 1165b2167459SRichard Henderson if (!is_l) { 1166b2167459SRichard Henderson cb = get_temp(ctx); 1167eaa3783bSRichard Henderson tcg_gen_xor_reg(cb, in1, in2); 1168eaa3783bSRichard Henderson tcg_gen_xor_reg(cb, cb, dest); 1169b2167459SRichard Henderson } 1170b2167459SRichard Henderson } else { 1171eaa3783bSRichard Henderson tcg_gen_add_reg(dest, in1, in2); 1172b2167459SRichard Henderson if (is_c) { 1173eaa3783bSRichard Henderson tcg_gen_add_reg(dest, dest, cpu_psw_cb_msb); 1174b2167459SRichard Henderson } 1175b2167459SRichard Henderson } 1176b2167459SRichard Henderson 1177b2167459SRichard Henderson /* Compute signed overflow if required. */ 1178f764718dSRichard Henderson sv = NULL; 1179b47a4a02SSven Schnelle if (is_tsv || cond_need_sv(c)) { 1180b2167459SRichard Henderson sv = do_add_sv(ctx, dest, in1, in2); 1181b2167459SRichard Henderson if (is_tsv) { 1182b2167459SRichard Henderson /* ??? Need to include overflow from shift. */ 1183b2167459SRichard Henderson gen_helper_tsv(cpu_env, sv); 1184b2167459SRichard Henderson } 1185b2167459SRichard Henderson } 1186b2167459SRichard Henderson 1187b2167459SRichard Henderson /* Emit any conditional trap before any writeback. */ 1188b2167459SRichard Henderson cond = do_cond(cf, dest, cb_msb, sv); 1189b2167459SRichard Henderson if (is_tc) { 1190b2167459SRichard Henderson cond_prep(&cond); 1191b2167459SRichard Henderson tmp = tcg_temp_new(); 1192eaa3783bSRichard Henderson tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); 1193b2167459SRichard Henderson gen_helper_tcond(cpu_env, tmp); 1194b2167459SRichard Henderson tcg_temp_free(tmp); 1195b2167459SRichard Henderson } 1196b2167459SRichard Henderson 1197b2167459SRichard Henderson /* Write back the result. */ 1198b2167459SRichard Henderson if (!is_l) { 1199b2167459SRichard Henderson save_or_nullify(ctx, cpu_psw_cb, cb); 1200b2167459SRichard Henderson save_or_nullify(ctx, cpu_psw_cb_msb, cb_msb); 1201b2167459SRichard Henderson } 1202b2167459SRichard Henderson save_gpr(ctx, rt, dest); 1203b2167459SRichard Henderson tcg_temp_free(dest); 1204b2167459SRichard Henderson 1205b2167459SRichard Henderson /* Install the new nullification. */ 1206b2167459SRichard Henderson cond_free(&ctx->null_cond); 1207b2167459SRichard Henderson ctx->null_cond = cond; 1208b2167459SRichard Henderson } 1209b2167459SRichard Henderson 12100c982a28SRichard Henderson static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_sh *a, 12110c982a28SRichard Henderson bool is_l, bool is_tsv, bool is_tc, bool is_c) 12120c982a28SRichard Henderson { 12130c982a28SRichard Henderson TCGv_reg tcg_r1, tcg_r2; 12140c982a28SRichard Henderson 12150c982a28SRichard Henderson if (a->cf) { 12160c982a28SRichard Henderson nullify_over(ctx); 12170c982a28SRichard Henderson } 12180c982a28SRichard Henderson tcg_r1 = load_gpr(ctx, a->r1); 12190c982a28SRichard Henderson tcg_r2 = load_gpr(ctx, a->r2); 12200c982a28SRichard Henderson do_add(ctx, a->t, tcg_r1, tcg_r2, a->sh, is_l, is_tsv, is_tc, is_c, a->cf); 12210c982a28SRichard Henderson return nullify_end(ctx); 12220c982a28SRichard Henderson } 12230c982a28SRichard Henderson 12240588e061SRichard Henderson static bool do_add_imm(DisasContext *ctx, arg_rri_cf *a, 12250588e061SRichard Henderson bool is_tsv, bool is_tc) 12260588e061SRichard Henderson { 12270588e061SRichard Henderson TCGv_reg tcg_im, tcg_r2; 12280588e061SRichard Henderson 12290588e061SRichard Henderson if (a->cf) { 12300588e061SRichard Henderson nullify_over(ctx); 12310588e061SRichard Henderson } 12320588e061SRichard Henderson tcg_im = load_const(ctx, a->i); 12330588e061SRichard Henderson tcg_r2 = load_gpr(ctx, a->r); 12340588e061SRichard Henderson do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf); 12350588e061SRichard Henderson return nullify_end(ctx); 12360588e061SRichard Henderson } 12370588e061SRichard Henderson 123831234768SRichard Henderson static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1, 1239eaa3783bSRichard Henderson TCGv_reg in2, bool is_tsv, bool is_b, 1240eaa3783bSRichard Henderson bool is_tc, unsigned cf) 1241b2167459SRichard Henderson { 1242eaa3783bSRichard Henderson TCGv_reg dest, sv, cb, cb_msb, zero, tmp; 1243b2167459SRichard Henderson unsigned c = cf >> 1; 1244b2167459SRichard Henderson DisasCond cond; 1245b2167459SRichard Henderson 1246b2167459SRichard Henderson dest = tcg_temp_new(); 1247b2167459SRichard Henderson cb = tcg_temp_new(); 1248b2167459SRichard Henderson cb_msb = tcg_temp_new(); 1249b2167459SRichard Henderson 1250eaa3783bSRichard Henderson zero = tcg_const_reg(0); 1251b2167459SRichard Henderson if (is_b) { 1252b2167459SRichard Henderson /* DEST,C = IN1 + ~IN2 + C. */ 1253eaa3783bSRichard Henderson tcg_gen_not_reg(cb, in2); 1254eaa3783bSRichard Henderson tcg_gen_add2_reg(dest, cb_msb, in1, zero, cpu_psw_cb_msb, zero); 1255eaa3783bSRichard Henderson tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cb, zero); 1256eaa3783bSRichard Henderson tcg_gen_xor_reg(cb, cb, in1); 1257eaa3783bSRichard Henderson tcg_gen_xor_reg(cb, cb, dest); 1258b2167459SRichard Henderson } else { 1259b2167459SRichard Henderson /* DEST,C = IN1 + ~IN2 + 1. We can produce the same result in fewer 1260b2167459SRichard Henderson operations by seeding the high word with 1 and subtracting. */ 1261eaa3783bSRichard Henderson tcg_gen_movi_reg(cb_msb, 1); 1262eaa3783bSRichard Henderson tcg_gen_sub2_reg(dest, cb_msb, in1, cb_msb, in2, zero); 1263eaa3783bSRichard Henderson tcg_gen_eqv_reg(cb, in1, in2); 1264eaa3783bSRichard Henderson tcg_gen_xor_reg(cb, cb, dest); 1265b2167459SRichard Henderson } 1266b2167459SRichard Henderson tcg_temp_free(zero); 1267b2167459SRichard Henderson 1268b2167459SRichard Henderson /* Compute signed overflow if required. */ 1269f764718dSRichard Henderson sv = NULL; 1270b47a4a02SSven Schnelle if (is_tsv || cond_need_sv(c)) { 1271b2167459SRichard Henderson sv = do_sub_sv(ctx, dest, in1, in2); 1272b2167459SRichard Henderson if (is_tsv) { 1273b2167459SRichard Henderson gen_helper_tsv(cpu_env, sv); 1274b2167459SRichard Henderson } 1275b2167459SRichard Henderson } 1276b2167459SRichard Henderson 1277b2167459SRichard Henderson /* Compute the condition. We cannot use the special case for borrow. */ 1278b2167459SRichard Henderson if (!is_b) { 1279b2167459SRichard Henderson cond = do_sub_cond(cf, dest, in1, in2, sv); 1280b2167459SRichard Henderson } else { 1281b2167459SRichard Henderson cond = do_cond(cf, dest, cb_msb, sv); 1282b2167459SRichard Henderson } 1283b2167459SRichard Henderson 1284b2167459SRichard Henderson /* Emit any conditional trap before any writeback. */ 1285b2167459SRichard Henderson if (is_tc) { 1286b2167459SRichard Henderson cond_prep(&cond); 1287b2167459SRichard Henderson tmp = tcg_temp_new(); 1288eaa3783bSRichard Henderson tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); 1289b2167459SRichard Henderson gen_helper_tcond(cpu_env, tmp); 1290b2167459SRichard Henderson tcg_temp_free(tmp); 1291b2167459SRichard Henderson } 1292b2167459SRichard Henderson 1293b2167459SRichard Henderson /* Write back the result. */ 1294b2167459SRichard Henderson save_or_nullify(ctx, cpu_psw_cb, cb); 1295b2167459SRichard Henderson save_or_nullify(ctx, cpu_psw_cb_msb, cb_msb); 1296b2167459SRichard Henderson save_gpr(ctx, rt, dest); 1297b2167459SRichard Henderson tcg_temp_free(dest); 1298b2167459SRichard Henderson 1299b2167459SRichard Henderson /* Install the new nullification. */ 1300b2167459SRichard Henderson cond_free(&ctx->null_cond); 1301b2167459SRichard Henderson ctx->null_cond = cond; 1302b2167459SRichard Henderson } 1303b2167459SRichard Henderson 13040c982a28SRichard Henderson static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf *a, 13050c982a28SRichard Henderson bool is_tsv, bool is_b, bool is_tc) 13060c982a28SRichard Henderson { 13070c982a28SRichard Henderson TCGv_reg tcg_r1, tcg_r2; 13080c982a28SRichard Henderson 13090c982a28SRichard Henderson if (a->cf) { 13100c982a28SRichard Henderson nullify_over(ctx); 13110c982a28SRichard Henderson } 13120c982a28SRichard Henderson tcg_r1 = load_gpr(ctx, a->r1); 13130c982a28SRichard Henderson tcg_r2 = load_gpr(ctx, a->r2); 13140c982a28SRichard Henderson do_sub(ctx, a->t, tcg_r1, tcg_r2, is_tsv, is_b, is_tc, a->cf); 13150c982a28SRichard Henderson return nullify_end(ctx); 13160c982a28SRichard Henderson } 13170c982a28SRichard Henderson 13180588e061SRichard Henderson static bool do_sub_imm(DisasContext *ctx, arg_rri_cf *a, bool is_tsv) 13190588e061SRichard Henderson { 13200588e061SRichard Henderson TCGv_reg tcg_im, tcg_r2; 13210588e061SRichard Henderson 13220588e061SRichard Henderson if (a->cf) { 13230588e061SRichard Henderson nullify_over(ctx); 13240588e061SRichard Henderson } 13250588e061SRichard Henderson tcg_im = load_const(ctx, a->i); 13260588e061SRichard Henderson tcg_r2 = load_gpr(ctx, a->r); 13270588e061SRichard Henderson do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf); 13280588e061SRichard Henderson return nullify_end(ctx); 13290588e061SRichard Henderson } 13300588e061SRichard Henderson 133131234768SRichard Henderson static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1, 1332eaa3783bSRichard Henderson TCGv_reg in2, unsigned cf) 1333b2167459SRichard Henderson { 1334eaa3783bSRichard Henderson TCGv_reg dest, sv; 1335b2167459SRichard Henderson DisasCond cond; 1336b2167459SRichard Henderson 1337b2167459SRichard Henderson dest = tcg_temp_new(); 1338eaa3783bSRichard Henderson tcg_gen_sub_reg(dest, in1, in2); 1339b2167459SRichard Henderson 1340b2167459SRichard Henderson /* Compute signed overflow if required. */ 1341f764718dSRichard Henderson sv = NULL; 1342b47a4a02SSven Schnelle if (cond_need_sv(cf >> 1)) { 1343b2167459SRichard Henderson sv = do_sub_sv(ctx, dest, in1, in2); 1344b2167459SRichard Henderson } 1345b2167459SRichard Henderson 1346b2167459SRichard Henderson /* Form the condition for the compare. */ 1347b2167459SRichard Henderson cond = do_sub_cond(cf, dest, in1, in2, sv); 1348b2167459SRichard Henderson 1349b2167459SRichard Henderson /* Clear. */ 1350eaa3783bSRichard Henderson tcg_gen_movi_reg(dest, 0); 1351b2167459SRichard Henderson save_gpr(ctx, rt, dest); 1352b2167459SRichard Henderson tcg_temp_free(dest); 1353b2167459SRichard Henderson 1354b2167459SRichard Henderson /* Install the new nullification. */ 1355b2167459SRichard Henderson cond_free(&ctx->null_cond); 1356b2167459SRichard Henderson ctx->null_cond = cond; 1357b2167459SRichard Henderson } 1358b2167459SRichard Henderson 135931234768SRichard Henderson static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1, 1360eaa3783bSRichard Henderson TCGv_reg in2, unsigned cf, 1361eaa3783bSRichard Henderson void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) 1362b2167459SRichard Henderson { 1363eaa3783bSRichard Henderson TCGv_reg dest = dest_gpr(ctx, rt); 1364b2167459SRichard Henderson 1365b2167459SRichard Henderson /* Perform the operation, and writeback. */ 1366b2167459SRichard Henderson fn(dest, in1, in2); 1367b2167459SRichard Henderson save_gpr(ctx, rt, dest); 1368b2167459SRichard Henderson 1369b2167459SRichard Henderson /* Install the new nullification. */ 1370b2167459SRichard Henderson cond_free(&ctx->null_cond); 1371b2167459SRichard Henderson if (cf) { 1372b2167459SRichard Henderson ctx->null_cond = do_log_cond(cf, dest); 1373b2167459SRichard Henderson } 1374b2167459SRichard Henderson } 1375b2167459SRichard Henderson 13760c982a28SRichard Henderson static bool do_log_reg(DisasContext *ctx, arg_rrr_cf *a, 13770c982a28SRichard Henderson void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) 13780c982a28SRichard Henderson { 13790c982a28SRichard Henderson TCGv_reg tcg_r1, tcg_r2; 13800c982a28SRichard Henderson 13810c982a28SRichard Henderson if (a->cf) { 13820c982a28SRichard Henderson nullify_over(ctx); 13830c982a28SRichard Henderson } 13840c982a28SRichard Henderson tcg_r1 = load_gpr(ctx, a->r1); 13850c982a28SRichard Henderson tcg_r2 = load_gpr(ctx, a->r2); 13860c982a28SRichard Henderson do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, fn); 13870c982a28SRichard Henderson return nullify_end(ctx); 13880c982a28SRichard Henderson } 13890c982a28SRichard Henderson 139031234768SRichard Henderson static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, 1391eaa3783bSRichard Henderson TCGv_reg in2, unsigned cf, bool is_tc, 1392eaa3783bSRichard Henderson void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) 1393b2167459SRichard Henderson { 1394eaa3783bSRichard Henderson TCGv_reg dest; 1395b2167459SRichard Henderson DisasCond cond; 1396b2167459SRichard Henderson 1397b2167459SRichard Henderson if (cf == 0) { 1398b2167459SRichard Henderson dest = dest_gpr(ctx, rt); 1399b2167459SRichard Henderson fn(dest, in1, in2); 1400b2167459SRichard Henderson save_gpr(ctx, rt, dest); 1401b2167459SRichard Henderson cond_free(&ctx->null_cond); 1402b2167459SRichard Henderson } else { 1403b2167459SRichard Henderson dest = tcg_temp_new(); 1404b2167459SRichard Henderson fn(dest, in1, in2); 1405b2167459SRichard Henderson 1406b2167459SRichard Henderson cond = do_unit_cond(cf, dest, in1, in2); 1407b2167459SRichard Henderson 1408b2167459SRichard Henderson if (is_tc) { 1409eaa3783bSRichard Henderson TCGv_reg tmp = tcg_temp_new(); 1410b2167459SRichard Henderson cond_prep(&cond); 1411eaa3783bSRichard Henderson tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); 1412b2167459SRichard Henderson gen_helper_tcond(cpu_env, tmp); 1413b2167459SRichard Henderson tcg_temp_free(tmp); 1414b2167459SRichard Henderson } 1415b2167459SRichard Henderson save_gpr(ctx, rt, dest); 1416b2167459SRichard Henderson 1417b2167459SRichard Henderson cond_free(&ctx->null_cond); 1418b2167459SRichard Henderson ctx->null_cond = cond; 1419b2167459SRichard Henderson } 1420b2167459SRichard Henderson } 1421b2167459SRichard Henderson 142286f8d05fSRichard Henderson #ifndef CONFIG_USER_ONLY 14238d6ae7fbSRichard Henderson /* The "normal" usage is SP >= 0, wherein SP == 0 selects the space 14248d6ae7fbSRichard Henderson from the top 2 bits of the base register. There are a few system 14258d6ae7fbSRichard Henderson instructions that have a 3-bit space specifier, for which SR0 is 14268d6ae7fbSRichard Henderson not special. To handle this, pass ~SP. */ 142786f8d05fSRichard Henderson static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) 142886f8d05fSRichard Henderson { 142986f8d05fSRichard Henderson TCGv_ptr ptr; 143086f8d05fSRichard Henderson TCGv_reg tmp; 143186f8d05fSRichard Henderson TCGv_i64 spc; 143286f8d05fSRichard Henderson 143386f8d05fSRichard Henderson if (sp != 0) { 14348d6ae7fbSRichard Henderson if (sp < 0) { 14358d6ae7fbSRichard Henderson sp = ~sp; 14368d6ae7fbSRichard Henderson } 14378d6ae7fbSRichard Henderson spc = get_temp_tl(ctx); 14388d6ae7fbSRichard Henderson load_spr(ctx, spc, sp); 14398d6ae7fbSRichard Henderson return spc; 144086f8d05fSRichard Henderson } 1441494737b7SRichard Henderson if (ctx->tb_flags & TB_FLAG_SR_SAME) { 1442494737b7SRichard Henderson return cpu_srH; 1443494737b7SRichard Henderson } 144486f8d05fSRichard Henderson 144586f8d05fSRichard Henderson ptr = tcg_temp_new_ptr(); 144686f8d05fSRichard Henderson tmp = tcg_temp_new(); 144786f8d05fSRichard Henderson spc = get_temp_tl(ctx); 144886f8d05fSRichard Henderson 144986f8d05fSRichard Henderson tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5); 145086f8d05fSRichard Henderson tcg_gen_andi_reg(tmp, tmp, 030); 145186f8d05fSRichard Henderson tcg_gen_trunc_reg_ptr(ptr, tmp); 145286f8d05fSRichard Henderson tcg_temp_free(tmp); 145386f8d05fSRichard Henderson 145486f8d05fSRichard Henderson tcg_gen_add_ptr(ptr, ptr, cpu_env); 145586f8d05fSRichard Henderson tcg_gen_ld_i64(spc, ptr, offsetof(CPUHPPAState, sr[4])); 145686f8d05fSRichard Henderson tcg_temp_free_ptr(ptr); 145786f8d05fSRichard Henderson 145886f8d05fSRichard Henderson return spc; 145986f8d05fSRichard Henderson } 146086f8d05fSRichard Henderson #endif 146186f8d05fSRichard Henderson 146286f8d05fSRichard Henderson static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs, 146386f8d05fSRichard Henderson unsigned rb, unsigned rx, int scale, target_sreg disp, 146486f8d05fSRichard Henderson unsigned sp, int modify, bool is_phys) 146586f8d05fSRichard Henderson { 146686f8d05fSRichard Henderson TCGv_reg base = load_gpr(ctx, rb); 146786f8d05fSRichard Henderson TCGv_reg ofs; 146886f8d05fSRichard Henderson 146986f8d05fSRichard Henderson /* Note that RX is mutually exclusive with DISP. */ 147086f8d05fSRichard Henderson if (rx) { 147186f8d05fSRichard Henderson ofs = get_temp(ctx); 147286f8d05fSRichard Henderson tcg_gen_shli_reg(ofs, cpu_gr[rx], scale); 147386f8d05fSRichard Henderson tcg_gen_add_reg(ofs, ofs, base); 147486f8d05fSRichard Henderson } else if (disp || modify) { 147586f8d05fSRichard Henderson ofs = get_temp(ctx); 147686f8d05fSRichard Henderson tcg_gen_addi_reg(ofs, base, disp); 147786f8d05fSRichard Henderson } else { 147886f8d05fSRichard Henderson ofs = base; 147986f8d05fSRichard Henderson } 148086f8d05fSRichard Henderson 148186f8d05fSRichard Henderson *pofs = ofs; 148286f8d05fSRichard Henderson #ifdef CONFIG_USER_ONLY 148386f8d05fSRichard Henderson *pgva = (modify <= 0 ? ofs : base); 148486f8d05fSRichard Henderson #else 148586f8d05fSRichard Henderson TCGv_tl addr = get_temp_tl(ctx); 148686f8d05fSRichard Henderson tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base); 1487494737b7SRichard Henderson if (ctx->tb_flags & PSW_W) { 148886f8d05fSRichard Henderson tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull); 148986f8d05fSRichard Henderson } 149086f8d05fSRichard Henderson if (!is_phys) { 149186f8d05fSRichard Henderson tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base)); 149286f8d05fSRichard Henderson } 149386f8d05fSRichard Henderson *pgva = addr; 149486f8d05fSRichard Henderson #endif 149586f8d05fSRichard Henderson } 149686f8d05fSRichard Henderson 149796d6407fSRichard Henderson /* Emit a memory load. The modify parameter should be 149896d6407fSRichard Henderson * < 0 for pre-modify, 149996d6407fSRichard Henderson * > 0 for post-modify, 150096d6407fSRichard Henderson * = 0 for no base register update. 150196d6407fSRichard Henderson */ 150296d6407fSRichard Henderson static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, 1503eaa3783bSRichard Henderson unsigned rx, int scale, target_sreg disp, 150486f8d05fSRichard Henderson unsigned sp, int modify, TCGMemOp mop) 150596d6407fSRichard Henderson { 150686f8d05fSRichard Henderson TCGv_reg ofs; 150786f8d05fSRichard Henderson TCGv_tl addr; 150896d6407fSRichard Henderson 150996d6407fSRichard Henderson /* Caller uses nullify_over/nullify_end. */ 151096d6407fSRichard Henderson assert(ctx->null_cond.c == TCG_COND_NEVER); 151196d6407fSRichard Henderson 151286f8d05fSRichard Henderson form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, 151386f8d05fSRichard Henderson ctx->mmu_idx == MMU_PHYS_IDX); 151486f8d05fSRichard Henderson tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop); 151586f8d05fSRichard Henderson if (modify) { 151686f8d05fSRichard Henderson save_gpr(ctx, rb, ofs); 151796d6407fSRichard Henderson } 151896d6407fSRichard Henderson } 151996d6407fSRichard Henderson 152096d6407fSRichard Henderson static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, 1521eaa3783bSRichard Henderson unsigned rx, int scale, target_sreg disp, 152286f8d05fSRichard Henderson unsigned sp, int modify, TCGMemOp mop) 152396d6407fSRichard Henderson { 152486f8d05fSRichard Henderson TCGv_reg ofs; 152586f8d05fSRichard Henderson TCGv_tl addr; 152696d6407fSRichard Henderson 152796d6407fSRichard Henderson /* Caller uses nullify_over/nullify_end. */ 152896d6407fSRichard Henderson assert(ctx->null_cond.c == TCG_COND_NEVER); 152996d6407fSRichard Henderson 153086f8d05fSRichard Henderson form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, 153186f8d05fSRichard Henderson ctx->mmu_idx == MMU_PHYS_IDX); 15323d68ee7bSRichard Henderson tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop); 153386f8d05fSRichard Henderson if (modify) { 153486f8d05fSRichard Henderson save_gpr(ctx, rb, ofs); 153596d6407fSRichard Henderson } 153696d6407fSRichard Henderson } 153796d6407fSRichard Henderson 153896d6407fSRichard Henderson static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, 1539eaa3783bSRichard Henderson unsigned rx, int scale, target_sreg disp, 154086f8d05fSRichard Henderson unsigned sp, int modify, TCGMemOp mop) 154196d6407fSRichard Henderson { 154286f8d05fSRichard Henderson TCGv_reg ofs; 154386f8d05fSRichard Henderson TCGv_tl addr; 154496d6407fSRichard Henderson 154596d6407fSRichard Henderson /* Caller uses nullify_over/nullify_end. */ 154696d6407fSRichard Henderson assert(ctx->null_cond.c == TCG_COND_NEVER); 154796d6407fSRichard Henderson 154886f8d05fSRichard Henderson form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, 154986f8d05fSRichard Henderson ctx->mmu_idx == MMU_PHYS_IDX); 155086f8d05fSRichard Henderson tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop); 155186f8d05fSRichard Henderson if (modify) { 155286f8d05fSRichard Henderson save_gpr(ctx, rb, ofs); 155396d6407fSRichard Henderson } 155496d6407fSRichard Henderson } 155596d6407fSRichard Henderson 155696d6407fSRichard Henderson static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, 1557eaa3783bSRichard Henderson unsigned rx, int scale, target_sreg disp, 155886f8d05fSRichard Henderson unsigned sp, int modify, TCGMemOp mop) 155996d6407fSRichard Henderson { 156086f8d05fSRichard Henderson TCGv_reg ofs; 156186f8d05fSRichard Henderson TCGv_tl addr; 156296d6407fSRichard Henderson 156396d6407fSRichard Henderson /* Caller uses nullify_over/nullify_end. */ 156496d6407fSRichard Henderson assert(ctx->null_cond.c == TCG_COND_NEVER); 156596d6407fSRichard Henderson 156686f8d05fSRichard Henderson form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, 156786f8d05fSRichard Henderson ctx->mmu_idx == MMU_PHYS_IDX); 156886f8d05fSRichard Henderson tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop); 156986f8d05fSRichard Henderson if (modify) { 157086f8d05fSRichard Henderson save_gpr(ctx, rb, ofs); 157196d6407fSRichard Henderson } 157296d6407fSRichard Henderson } 157396d6407fSRichard Henderson 1574eaa3783bSRichard Henderson #if TARGET_REGISTER_BITS == 64 1575eaa3783bSRichard Henderson #define do_load_reg do_load_64 1576eaa3783bSRichard Henderson #define do_store_reg do_store_64 157796d6407fSRichard Henderson #else 1578eaa3783bSRichard Henderson #define do_load_reg do_load_32 1579eaa3783bSRichard Henderson #define do_store_reg do_store_32 158096d6407fSRichard Henderson #endif 158196d6407fSRichard Henderson 15821cd012a5SRichard Henderson static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb, 1583eaa3783bSRichard Henderson unsigned rx, int scale, target_sreg disp, 158486f8d05fSRichard Henderson unsigned sp, int modify, TCGMemOp mop) 158596d6407fSRichard Henderson { 1586eaa3783bSRichard Henderson TCGv_reg dest; 158796d6407fSRichard Henderson 158896d6407fSRichard Henderson nullify_over(ctx); 158996d6407fSRichard Henderson 159096d6407fSRichard Henderson if (modify == 0) { 159196d6407fSRichard Henderson /* No base register update. */ 159296d6407fSRichard Henderson dest = dest_gpr(ctx, rt); 159396d6407fSRichard Henderson } else { 159496d6407fSRichard Henderson /* Make sure if RT == RB, we see the result of the load. */ 159596d6407fSRichard Henderson dest = get_temp(ctx); 159696d6407fSRichard Henderson } 159786f8d05fSRichard Henderson do_load_reg(ctx, dest, rb, rx, scale, disp, sp, modify, mop); 159896d6407fSRichard Henderson save_gpr(ctx, rt, dest); 159996d6407fSRichard Henderson 16001cd012a5SRichard Henderson return nullify_end(ctx); 160196d6407fSRichard Henderson } 160296d6407fSRichard Henderson 1603740038d7SRichard Henderson static bool do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, 1604eaa3783bSRichard Henderson unsigned rx, int scale, target_sreg disp, 160586f8d05fSRichard Henderson unsigned sp, int modify) 160696d6407fSRichard Henderson { 160796d6407fSRichard Henderson TCGv_i32 tmp; 160896d6407fSRichard Henderson 160996d6407fSRichard Henderson nullify_over(ctx); 161096d6407fSRichard Henderson 161196d6407fSRichard Henderson tmp = tcg_temp_new_i32(); 161286f8d05fSRichard Henderson do_load_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL); 161396d6407fSRichard Henderson save_frw_i32(rt, tmp); 161496d6407fSRichard Henderson tcg_temp_free_i32(tmp); 161596d6407fSRichard Henderson 161696d6407fSRichard Henderson if (rt == 0) { 161796d6407fSRichard Henderson gen_helper_loaded_fr0(cpu_env); 161896d6407fSRichard Henderson } 161996d6407fSRichard Henderson 1620740038d7SRichard Henderson return nullify_end(ctx); 162196d6407fSRichard Henderson } 162296d6407fSRichard Henderson 1623740038d7SRichard Henderson static bool trans_fldw(DisasContext *ctx, arg_ldst *a) 1624740038d7SRichard Henderson { 1625740038d7SRichard Henderson return do_floadw(ctx, a->t, a->b, a->x, a->scale ? 2 : 0, 1626740038d7SRichard Henderson a->disp, a->sp, a->m); 1627740038d7SRichard Henderson } 1628740038d7SRichard Henderson 1629740038d7SRichard Henderson static bool do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, 1630eaa3783bSRichard Henderson unsigned rx, int scale, target_sreg disp, 163186f8d05fSRichard Henderson unsigned sp, int modify) 163296d6407fSRichard Henderson { 163396d6407fSRichard Henderson TCGv_i64 tmp; 163496d6407fSRichard Henderson 163596d6407fSRichard Henderson nullify_over(ctx); 163696d6407fSRichard Henderson 163796d6407fSRichard Henderson tmp = tcg_temp_new_i64(); 163886f8d05fSRichard Henderson do_load_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEQ); 163996d6407fSRichard Henderson save_frd(rt, tmp); 164096d6407fSRichard Henderson tcg_temp_free_i64(tmp); 164196d6407fSRichard Henderson 164296d6407fSRichard Henderson if (rt == 0) { 164396d6407fSRichard Henderson gen_helper_loaded_fr0(cpu_env); 164496d6407fSRichard Henderson } 164596d6407fSRichard Henderson 1646740038d7SRichard Henderson return nullify_end(ctx); 1647740038d7SRichard Henderson } 1648740038d7SRichard Henderson 1649740038d7SRichard Henderson static bool trans_fldd(DisasContext *ctx, arg_ldst *a) 1650740038d7SRichard Henderson { 1651740038d7SRichard Henderson return do_floadd(ctx, a->t, a->b, a->x, a->scale ? 3 : 0, 1652740038d7SRichard Henderson a->disp, a->sp, a->m); 165396d6407fSRichard Henderson } 165496d6407fSRichard Henderson 16551cd012a5SRichard Henderson static bool do_store(DisasContext *ctx, unsigned rt, unsigned rb, 165686f8d05fSRichard Henderson target_sreg disp, unsigned sp, 165786f8d05fSRichard Henderson int modify, TCGMemOp mop) 165896d6407fSRichard Henderson { 165996d6407fSRichard Henderson nullify_over(ctx); 166086f8d05fSRichard Henderson do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop); 16611cd012a5SRichard Henderson return nullify_end(ctx); 166296d6407fSRichard Henderson } 166396d6407fSRichard Henderson 1664740038d7SRichard Henderson static bool do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb, 1665eaa3783bSRichard Henderson unsigned rx, int scale, target_sreg disp, 166686f8d05fSRichard Henderson unsigned sp, int modify) 166796d6407fSRichard Henderson { 166896d6407fSRichard Henderson TCGv_i32 tmp; 166996d6407fSRichard Henderson 167096d6407fSRichard Henderson nullify_over(ctx); 167196d6407fSRichard Henderson 167296d6407fSRichard Henderson tmp = load_frw_i32(rt); 167386f8d05fSRichard Henderson do_store_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL); 167496d6407fSRichard Henderson tcg_temp_free_i32(tmp); 167596d6407fSRichard Henderson 1676740038d7SRichard Henderson return nullify_end(ctx); 167796d6407fSRichard Henderson } 167896d6407fSRichard Henderson 1679740038d7SRichard Henderson static bool trans_fstw(DisasContext *ctx, arg_ldst *a) 1680740038d7SRichard Henderson { 1681740038d7SRichard Henderson return do_fstorew(ctx, a->t, a->b, a->x, a->scale ? 2 : 0, 1682740038d7SRichard Henderson a->disp, a->sp, a->m); 1683740038d7SRichard Henderson } 1684740038d7SRichard Henderson 1685740038d7SRichard Henderson static bool do_fstored(DisasContext *ctx, unsigned rt, unsigned rb, 1686eaa3783bSRichard Henderson unsigned rx, int scale, target_sreg disp, 168786f8d05fSRichard Henderson unsigned sp, int modify) 168896d6407fSRichard Henderson { 168996d6407fSRichard Henderson TCGv_i64 tmp; 169096d6407fSRichard Henderson 169196d6407fSRichard Henderson nullify_over(ctx); 169296d6407fSRichard Henderson 169396d6407fSRichard Henderson tmp = load_frd(rt); 169486f8d05fSRichard Henderson do_store_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEQ); 169596d6407fSRichard Henderson tcg_temp_free_i64(tmp); 169696d6407fSRichard Henderson 1697740038d7SRichard Henderson return nullify_end(ctx); 1698740038d7SRichard Henderson } 1699740038d7SRichard Henderson 1700740038d7SRichard Henderson static bool trans_fstd(DisasContext *ctx, arg_ldst *a) 1701740038d7SRichard Henderson { 1702740038d7SRichard Henderson return do_fstored(ctx, a->t, a->b, a->x, a->scale ? 3 : 0, 1703740038d7SRichard Henderson a->disp, a->sp, a->m); 170496d6407fSRichard Henderson } 170596d6407fSRichard Henderson 17061ca74648SRichard Henderson static bool do_fop_wew(DisasContext *ctx, unsigned rt, unsigned ra, 1707ebe9383cSRichard Henderson void (*func)(TCGv_i32, TCGv_env, TCGv_i32)) 1708ebe9383cSRichard Henderson { 1709ebe9383cSRichard Henderson TCGv_i32 tmp; 1710ebe9383cSRichard Henderson 1711ebe9383cSRichard Henderson nullify_over(ctx); 1712ebe9383cSRichard Henderson tmp = load_frw0_i32(ra); 1713ebe9383cSRichard Henderson 1714ebe9383cSRichard Henderson func(tmp, cpu_env, tmp); 1715ebe9383cSRichard Henderson 1716ebe9383cSRichard Henderson save_frw_i32(rt, tmp); 1717ebe9383cSRichard Henderson tcg_temp_free_i32(tmp); 17181ca74648SRichard Henderson return nullify_end(ctx); 1719ebe9383cSRichard Henderson } 1720ebe9383cSRichard Henderson 17211ca74648SRichard Henderson static bool do_fop_wed(DisasContext *ctx, unsigned rt, unsigned ra, 1722ebe9383cSRichard Henderson void (*func)(TCGv_i32, TCGv_env, TCGv_i64)) 1723ebe9383cSRichard Henderson { 1724ebe9383cSRichard Henderson TCGv_i32 dst; 1725ebe9383cSRichard Henderson TCGv_i64 src; 1726ebe9383cSRichard Henderson 1727ebe9383cSRichard Henderson nullify_over(ctx); 1728ebe9383cSRichard Henderson src = load_frd(ra); 1729ebe9383cSRichard Henderson dst = tcg_temp_new_i32(); 1730ebe9383cSRichard Henderson 1731ebe9383cSRichard Henderson func(dst, cpu_env, src); 1732ebe9383cSRichard Henderson 1733ebe9383cSRichard Henderson tcg_temp_free_i64(src); 1734ebe9383cSRichard Henderson save_frw_i32(rt, dst); 1735ebe9383cSRichard Henderson tcg_temp_free_i32(dst); 17361ca74648SRichard Henderson return nullify_end(ctx); 1737ebe9383cSRichard Henderson } 1738ebe9383cSRichard Henderson 17391ca74648SRichard Henderson static bool do_fop_ded(DisasContext *ctx, unsigned rt, unsigned ra, 1740ebe9383cSRichard Henderson void (*func)(TCGv_i64, TCGv_env, TCGv_i64)) 1741ebe9383cSRichard Henderson { 1742ebe9383cSRichard Henderson TCGv_i64 tmp; 1743ebe9383cSRichard Henderson 1744ebe9383cSRichard Henderson nullify_over(ctx); 1745ebe9383cSRichard Henderson tmp = load_frd0(ra); 1746ebe9383cSRichard Henderson 1747ebe9383cSRichard Henderson func(tmp, cpu_env, tmp); 1748ebe9383cSRichard Henderson 1749ebe9383cSRichard Henderson save_frd(rt, tmp); 1750ebe9383cSRichard Henderson tcg_temp_free_i64(tmp); 17511ca74648SRichard Henderson return nullify_end(ctx); 1752ebe9383cSRichard Henderson } 1753ebe9383cSRichard Henderson 17541ca74648SRichard Henderson static bool do_fop_dew(DisasContext *ctx, unsigned rt, unsigned ra, 1755ebe9383cSRichard Henderson void (*func)(TCGv_i64, TCGv_env, TCGv_i32)) 1756ebe9383cSRichard Henderson { 1757ebe9383cSRichard Henderson TCGv_i32 src; 1758ebe9383cSRichard Henderson TCGv_i64 dst; 1759ebe9383cSRichard Henderson 1760ebe9383cSRichard Henderson nullify_over(ctx); 1761ebe9383cSRichard Henderson src = load_frw0_i32(ra); 1762ebe9383cSRichard Henderson dst = tcg_temp_new_i64(); 1763ebe9383cSRichard Henderson 1764ebe9383cSRichard Henderson func(dst, cpu_env, src); 1765ebe9383cSRichard Henderson 1766ebe9383cSRichard Henderson tcg_temp_free_i32(src); 1767ebe9383cSRichard Henderson save_frd(rt, dst); 1768ebe9383cSRichard Henderson tcg_temp_free_i64(dst); 17691ca74648SRichard Henderson return nullify_end(ctx); 1770ebe9383cSRichard Henderson } 1771ebe9383cSRichard Henderson 17721ca74648SRichard Henderson static bool do_fop_weww(DisasContext *ctx, unsigned rt, 1773ebe9383cSRichard Henderson unsigned ra, unsigned rb, 177431234768SRichard Henderson void (*func)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32)) 1775ebe9383cSRichard Henderson { 1776ebe9383cSRichard Henderson TCGv_i32 a, b; 1777ebe9383cSRichard Henderson 1778ebe9383cSRichard Henderson nullify_over(ctx); 1779ebe9383cSRichard Henderson a = load_frw0_i32(ra); 1780ebe9383cSRichard Henderson b = load_frw0_i32(rb); 1781ebe9383cSRichard Henderson 1782ebe9383cSRichard Henderson func(a, cpu_env, a, b); 1783ebe9383cSRichard Henderson 1784ebe9383cSRichard Henderson tcg_temp_free_i32(b); 1785ebe9383cSRichard Henderson save_frw_i32(rt, a); 1786ebe9383cSRichard Henderson tcg_temp_free_i32(a); 17871ca74648SRichard Henderson return nullify_end(ctx); 1788ebe9383cSRichard Henderson } 1789ebe9383cSRichard Henderson 17901ca74648SRichard Henderson static bool do_fop_dedd(DisasContext *ctx, unsigned rt, 1791ebe9383cSRichard Henderson unsigned ra, unsigned rb, 179231234768SRichard Henderson void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64)) 1793ebe9383cSRichard Henderson { 1794ebe9383cSRichard Henderson TCGv_i64 a, b; 1795ebe9383cSRichard Henderson 1796ebe9383cSRichard Henderson nullify_over(ctx); 1797ebe9383cSRichard Henderson a = load_frd0(ra); 1798ebe9383cSRichard Henderson b = load_frd0(rb); 1799ebe9383cSRichard Henderson 1800ebe9383cSRichard Henderson func(a, cpu_env, a, b); 1801ebe9383cSRichard Henderson 1802ebe9383cSRichard Henderson tcg_temp_free_i64(b); 1803ebe9383cSRichard Henderson save_frd(rt, a); 1804ebe9383cSRichard Henderson tcg_temp_free_i64(a); 18051ca74648SRichard Henderson return nullify_end(ctx); 1806ebe9383cSRichard Henderson } 1807ebe9383cSRichard Henderson 180898cd9ca7SRichard Henderson /* Emit an unconditional branch to a direct target, which may or may not 180998cd9ca7SRichard Henderson have already had nullification handled. */ 181001afb7beSRichard Henderson static bool do_dbranch(DisasContext *ctx, target_ureg dest, 181198cd9ca7SRichard Henderson unsigned link, bool is_n) 181298cd9ca7SRichard Henderson { 181398cd9ca7SRichard Henderson if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { 181498cd9ca7SRichard Henderson if (link != 0) { 181598cd9ca7SRichard Henderson copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); 181698cd9ca7SRichard Henderson } 181798cd9ca7SRichard Henderson ctx->iaoq_n = dest; 181898cd9ca7SRichard Henderson if (is_n) { 181998cd9ca7SRichard Henderson ctx->null_cond.c = TCG_COND_ALWAYS; 182098cd9ca7SRichard Henderson } 182198cd9ca7SRichard Henderson } else { 182298cd9ca7SRichard Henderson nullify_over(ctx); 182398cd9ca7SRichard Henderson 182498cd9ca7SRichard Henderson if (link != 0) { 182598cd9ca7SRichard Henderson copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); 182698cd9ca7SRichard Henderson } 182798cd9ca7SRichard Henderson 182898cd9ca7SRichard Henderson if (is_n && use_nullify_skip(ctx)) { 182998cd9ca7SRichard Henderson nullify_set(ctx, 0); 183098cd9ca7SRichard Henderson gen_goto_tb(ctx, 0, dest, dest + 4); 183198cd9ca7SRichard Henderson } else { 183298cd9ca7SRichard Henderson nullify_set(ctx, is_n); 183398cd9ca7SRichard Henderson gen_goto_tb(ctx, 0, ctx->iaoq_b, dest); 183498cd9ca7SRichard Henderson } 183598cd9ca7SRichard Henderson 183631234768SRichard Henderson nullify_end(ctx); 183798cd9ca7SRichard Henderson 183898cd9ca7SRichard Henderson nullify_set(ctx, 0); 183998cd9ca7SRichard Henderson gen_goto_tb(ctx, 1, ctx->iaoq_b, ctx->iaoq_n); 184031234768SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 184198cd9ca7SRichard Henderson } 184201afb7beSRichard Henderson return true; 184398cd9ca7SRichard Henderson } 184498cd9ca7SRichard Henderson 184598cd9ca7SRichard Henderson /* Emit a conditional branch to a direct target. If the branch itself 184698cd9ca7SRichard Henderson is nullified, we should have already used nullify_over. */ 184701afb7beSRichard Henderson static bool do_cbranch(DisasContext *ctx, target_sreg disp, bool is_n, 184898cd9ca7SRichard Henderson DisasCond *cond) 184998cd9ca7SRichard Henderson { 1850eaa3783bSRichard Henderson target_ureg dest = iaoq_dest(ctx, disp); 185198cd9ca7SRichard Henderson TCGLabel *taken = NULL; 185298cd9ca7SRichard Henderson TCGCond c = cond->c; 185398cd9ca7SRichard Henderson bool n; 185498cd9ca7SRichard Henderson 185598cd9ca7SRichard Henderson assert(ctx->null_cond.c == TCG_COND_NEVER); 185698cd9ca7SRichard Henderson 185798cd9ca7SRichard Henderson /* Handle TRUE and NEVER as direct branches. */ 185898cd9ca7SRichard Henderson if (c == TCG_COND_ALWAYS) { 185901afb7beSRichard Henderson return do_dbranch(ctx, dest, 0, is_n && disp >= 0); 186098cd9ca7SRichard Henderson } 186198cd9ca7SRichard Henderson if (c == TCG_COND_NEVER) { 186201afb7beSRichard Henderson return do_dbranch(ctx, ctx->iaoq_n, 0, is_n && disp < 0); 186398cd9ca7SRichard Henderson } 186498cd9ca7SRichard Henderson 186598cd9ca7SRichard Henderson taken = gen_new_label(); 186698cd9ca7SRichard Henderson cond_prep(cond); 1867eaa3783bSRichard Henderson tcg_gen_brcond_reg(c, cond->a0, cond->a1, taken); 186898cd9ca7SRichard Henderson cond_free(cond); 186998cd9ca7SRichard Henderson 187098cd9ca7SRichard Henderson /* Not taken: Condition not satisfied; nullify on backward branches. */ 187198cd9ca7SRichard Henderson n = is_n && disp < 0; 187298cd9ca7SRichard Henderson if (n && use_nullify_skip(ctx)) { 187398cd9ca7SRichard Henderson nullify_set(ctx, 0); 1874a881c8e7SRichard Henderson gen_goto_tb(ctx, 0, ctx->iaoq_n, ctx->iaoq_n + 4); 187598cd9ca7SRichard Henderson } else { 187698cd9ca7SRichard Henderson if (!n && ctx->null_lab) { 187798cd9ca7SRichard Henderson gen_set_label(ctx->null_lab); 187898cd9ca7SRichard Henderson ctx->null_lab = NULL; 187998cd9ca7SRichard Henderson } 188098cd9ca7SRichard Henderson nullify_set(ctx, n); 1881c301f34eSRichard Henderson if (ctx->iaoq_n == -1) { 1882c301f34eSRichard Henderson /* The temporary iaoq_n_var died at the branch above. 1883c301f34eSRichard Henderson Regenerate it here instead of saving it. */ 1884c301f34eSRichard Henderson tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); 1885c301f34eSRichard Henderson } 1886a881c8e7SRichard Henderson gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); 188798cd9ca7SRichard Henderson } 188898cd9ca7SRichard Henderson 188998cd9ca7SRichard Henderson gen_set_label(taken); 189098cd9ca7SRichard Henderson 189198cd9ca7SRichard Henderson /* Taken: Condition satisfied; nullify on forward branches. */ 189298cd9ca7SRichard Henderson n = is_n && disp >= 0; 189398cd9ca7SRichard Henderson if (n && use_nullify_skip(ctx)) { 189498cd9ca7SRichard Henderson nullify_set(ctx, 0); 1895a881c8e7SRichard Henderson gen_goto_tb(ctx, 1, dest, dest + 4); 189698cd9ca7SRichard Henderson } else { 189798cd9ca7SRichard Henderson nullify_set(ctx, n); 1898a881c8e7SRichard Henderson gen_goto_tb(ctx, 1, ctx->iaoq_b, dest); 189998cd9ca7SRichard Henderson } 190098cd9ca7SRichard Henderson 190198cd9ca7SRichard Henderson /* Not taken: the branch itself was nullified. */ 190298cd9ca7SRichard Henderson if (ctx->null_lab) { 190398cd9ca7SRichard Henderson gen_set_label(ctx->null_lab); 190498cd9ca7SRichard Henderson ctx->null_lab = NULL; 190531234768SRichard Henderson ctx->base.is_jmp = DISAS_IAQ_N_STALE; 190698cd9ca7SRichard Henderson } else { 190731234768SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 190898cd9ca7SRichard Henderson } 190901afb7beSRichard Henderson return true; 191098cd9ca7SRichard Henderson } 191198cd9ca7SRichard Henderson 191298cd9ca7SRichard Henderson /* Emit an unconditional branch to an indirect target. This handles 191398cd9ca7SRichard Henderson nullification of the branch itself. */ 191401afb7beSRichard Henderson static bool do_ibranch(DisasContext *ctx, TCGv_reg dest, 191598cd9ca7SRichard Henderson unsigned link, bool is_n) 191698cd9ca7SRichard Henderson { 1917eaa3783bSRichard Henderson TCGv_reg a0, a1, next, tmp; 191898cd9ca7SRichard Henderson TCGCond c; 191998cd9ca7SRichard Henderson 192098cd9ca7SRichard Henderson assert(ctx->null_lab == NULL); 192198cd9ca7SRichard Henderson 192298cd9ca7SRichard Henderson if (ctx->null_cond.c == TCG_COND_NEVER) { 192398cd9ca7SRichard Henderson if (link != 0) { 192498cd9ca7SRichard Henderson copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); 192598cd9ca7SRichard Henderson } 192698cd9ca7SRichard Henderson next = get_temp(ctx); 1927eaa3783bSRichard Henderson tcg_gen_mov_reg(next, dest); 192898cd9ca7SRichard Henderson if (is_n) { 1929c301f34eSRichard Henderson if (use_nullify_skip(ctx)) { 1930c301f34eSRichard Henderson tcg_gen_mov_reg(cpu_iaoq_f, next); 1931c301f34eSRichard Henderson tcg_gen_addi_reg(cpu_iaoq_b, next, 4); 1932c301f34eSRichard Henderson nullify_set(ctx, 0); 193331234768SRichard Henderson ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; 193401afb7beSRichard Henderson return true; 1935c301f34eSRichard Henderson } 193698cd9ca7SRichard Henderson ctx->null_cond.c = TCG_COND_ALWAYS; 193798cd9ca7SRichard Henderson } 1938c301f34eSRichard Henderson ctx->iaoq_n = -1; 1939c301f34eSRichard Henderson ctx->iaoq_n_var = next; 194098cd9ca7SRichard Henderson } else if (is_n && use_nullify_skip(ctx)) { 194198cd9ca7SRichard Henderson /* The (conditional) branch, B, nullifies the next insn, N, 194298cd9ca7SRichard Henderson and we're allowed to skip execution N (no single-step or 19434137cb83SRichard Henderson tracepoint in effect). Since the goto_ptr that we must use 194498cd9ca7SRichard Henderson for the indirect branch consumes no special resources, we 194598cd9ca7SRichard Henderson can (conditionally) skip B and continue execution. */ 194698cd9ca7SRichard Henderson /* The use_nullify_skip test implies we have a known control path. */ 194798cd9ca7SRichard Henderson tcg_debug_assert(ctx->iaoq_b != -1); 194898cd9ca7SRichard Henderson tcg_debug_assert(ctx->iaoq_n != -1); 194998cd9ca7SRichard Henderson 195098cd9ca7SRichard Henderson /* We do have to handle the non-local temporary, DEST, before 195198cd9ca7SRichard Henderson branching. Since IOAQ_F is not really live at this point, we 195298cd9ca7SRichard Henderson can simply store DEST optimistically. Similarly with IAOQ_B. */ 1953eaa3783bSRichard Henderson tcg_gen_mov_reg(cpu_iaoq_f, dest); 1954eaa3783bSRichard Henderson tcg_gen_addi_reg(cpu_iaoq_b, dest, 4); 195598cd9ca7SRichard Henderson 195698cd9ca7SRichard Henderson nullify_over(ctx); 195798cd9ca7SRichard Henderson if (link != 0) { 1958eaa3783bSRichard Henderson tcg_gen_movi_reg(cpu_gr[link], ctx->iaoq_n); 195998cd9ca7SRichard Henderson } 19607f11636dSEmilio G. Cota tcg_gen_lookup_and_goto_ptr(); 196101afb7beSRichard Henderson return nullify_end(ctx); 196298cd9ca7SRichard Henderson } else { 196398cd9ca7SRichard Henderson cond_prep(&ctx->null_cond); 196498cd9ca7SRichard Henderson c = ctx->null_cond.c; 196598cd9ca7SRichard Henderson a0 = ctx->null_cond.a0; 196698cd9ca7SRichard Henderson a1 = ctx->null_cond.a1; 196798cd9ca7SRichard Henderson 196898cd9ca7SRichard Henderson tmp = tcg_temp_new(); 196998cd9ca7SRichard Henderson next = get_temp(ctx); 197098cd9ca7SRichard Henderson 197198cd9ca7SRichard Henderson copy_iaoq_entry(tmp, ctx->iaoq_n, ctx->iaoq_n_var); 1972eaa3783bSRichard Henderson tcg_gen_movcond_reg(c, next, a0, a1, tmp, dest); 197398cd9ca7SRichard Henderson ctx->iaoq_n = -1; 197498cd9ca7SRichard Henderson ctx->iaoq_n_var = next; 197598cd9ca7SRichard Henderson 197698cd9ca7SRichard Henderson if (link != 0) { 1977eaa3783bSRichard Henderson tcg_gen_movcond_reg(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp); 197898cd9ca7SRichard Henderson } 197998cd9ca7SRichard Henderson 198098cd9ca7SRichard Henderson if (is_n) { 198198cd9ca7SRichard Henderson /* The branch nullifies the next insn, which means the state of N 198298cd9ca7SRichard Henderson after the branch is the inverse of the state of N that applied 198398cd9ca7SRichard Henderson to the branch. */ 1984eaa3783bSRichard Henderson tcg_gen_setcond_reg(tcg_invert_cond(c), cpu_psw_n, a0, a1); 198598cd9ca7SRichard Henderson cond_free(&ctx->null_cond); 198698cd9ca7SRichard Henderson ctx->null_cond = cond_make_n(); 198798cd9ca7SRichard Henderson ctx->psw_n_nonzero = true; 198898cd9ca7SRichard Henderson } else { 198998cd9ca7SRichard Henderson cond_free(&ctx->null_cond); 199098cd9ca7SRichard Henderson } 199198cd9ca7SRichard Henderson } 199201afb7beSRichard Henderson return true; 199398cd9ca7SRichard Henderson } 199498cd9ca7SRichard Henderson 1995660eefe1SRichard Henderson /* Implement 1996660eefe1SRichard Henderson * if (IAOQ_Front{30..31} < GR[b]{30..31}) 1997660eefe1SRichard Henderson * IAOQ_Next{30..31} ← GR[b]{30..31}; 1998660eefe1SRichard Henderson * else 1999660eefe1SRichard Henderson * IAOQ_Next{30..31} ← IAOQ_Front{30..31}; 2000660eefe1SRichard Henderson * which keeps the privilege level from being increased. 2001660eefe1SRichard Henderson */ 2002660eefe1SRichard Henderson static TCGv_reg do_ibranch_priv(DisasContext *ctx, TCGv_reg offset) 2003660eefe1SRichard Henderson { 2004660eefe1SRichard Henderson TCGv_reg dest; 2005660eefe1SRichard Henderson switch (ctx->privilege) { 2006660eefe1SRichard Henderson case 0: 2007660eefe1SRichard Henderson /* Privilege 0 is maximum and is allowed to decrease. */ 2008660eefe1SRichard Henderson return offset; 2009660eefe1SRichard Henderson case 3: 2010660eefe1SRichard Henderson /* Privilege 3 is minimum and is never allowed increase. */ 2011660eefe1SRichard Henderson dest = get_temp(ctx); 2012660eefe1SRichard Henderson tcg_gen_ori_reg(dest, offset, 3); 2013660eefe1SRichard Henderson break; 2014660eefe1SRichard Henderson default: 2015660eefe1SRichard Henderson dest = tcg_temp_new(); 2016660eefe1SRichard Henderson tcg_gen_andi_reg(dest, offset, -4); 2017660eefe1SRichard Henderson tcg_gen_ori_reg(dest, dest, ctx->privilege); 2018660eefe1SRichard Henderson tcg_gen_movcond_reg(TCG_COND_GTU, dest, dest, offset, dest, offset); 2019660eefe1SRichard Henderson tcg_temp_free(dest); 2020660eefe1SRichard Henderson break; 2021660eefe1SRichard Henderson } 2022660eefe1SRichard Henderson return dest; 2023660eefe1SRichard Henderson } 2024660eefe1SRichard Henderson 2025ba1d0b44SRichard Henderson #ifdef CONFIG_USER_ONLY 20267ad439dfSRichard Henderson /* On Linux, page zero is normally marked execute only + gateway. 20277ad439dfSRichard Henderson Therefore normal read or write is supposed to fail, but specific 20287ad439dfSRichard Henderson offsets have kernel code mapped to raise permissions to implement 20297ad439dfSRichard Henderson system calls. Handling this via an explicit check here, rather 20307ad439dfSRichard Henderson in than the "be disp(sr2,r0)" instruction that probably sent us 20317ad439dfSRichard Henderson here, is the easiest way to handle the branch delay slot on the 20327ad439dfSRichard Henderson aforementioned BE. */ 203331234768SRichard Henderson static void do_page_zero(DisasContext *ctx) 20347ad439dfSRichard Henderson { 20357ad439dfSRichard Henderson /* If by some means we get here with PSW[N]=1, that implies that 20367ad439dfSRichard Henderson the B,GATE instruction would be skipped, and we'd fault on the 20377ad439dfSRichard Henderson next insn within the privilaged page. */ 20387ad439dfSRichard Henderson switch (ctx->null_cond.c) { 20397ad439dfSRichard Henderson case TCG_COND_NEVER: 20407ad439dfSRichard Henderson break; 20417ad439dfSRichard Henderson case TCG_COND_ALWAYS: 2042eaa3783bSRichard Henderson tcg_gen_movi_reg(cpu_psw_n, 0); 20437ad439dfSRichard Henderson goto do_sigill; 20447ad439dfSRichard Henderson default: 20457ad439dfSRichard Henderson /* Since this is always the first (and only) insn within the 20467ad439dfSRichard Henderson TB, we should know the state of PSW[N] from TB->FLAGS. */ 20477ad439dfSRichard Henderson g_assert_not_reached(); 20487ad439dfSRichard Henderson } 20497ad439dfSRichard Henderson 20507ad439dfSRichard Henderson /* Check that we didn't arrive here via some means that allowed 20517ad439dfSRichard Henderson non-sequential instruction execution. Normally the PSW[B] bit 20527ad439dfSRichard Henderson detects this by disallowing the B,GATE instruction to execute 20537ad439dfSRichard Henderson under such conditions. */ 20547ad439dfSRichard Henderson if (ctx->iaoq_b != ctx->iaoq_f + 4) { 20557ad439dfSRichard Henderson goto do_sigill; 20567ad439dfSRichard Henderson } 20577ad439dfSRichard Henderson 2058ebd0e151SRichard Henderson switch (ctx->iaoq_f & -4) { 20597ad439dfSRichard Henderson case 0x00: /* Null pointer call */ 20602986721dSRichard Henderson gen_excp_1(EXCP_IMP); 206131234768SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 206231234768SRichard Henderson break; 20637ad439dfSRichard Henderson 20647ad439dfSRichard Henderson case 0xb0: /* LWS */ 20657ad439dfSRichard Henderson gen_excp_1(EXCP_SYSCALL_LWS); 206631234768SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 206731234768SRichard Henderson break; 20687ad439dfSRichard Henderson 20697ad439dfSRichard Henderson case 0xe0: /* SET_THREAD_POINTER */ 207035136a77SRichard Henderson tcg_gen_st_reg(cpu_gr[26], cpu_env, offsetof(CPUHPPAState, cr[27])); 2071ebd0e151SRichard Henderson tcg_gen_ori_reg(cpu_iaoq_f, cpu_gr[31], 3); 2072eaa3783bSRichard Henderson tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); 207331234768SRichard Henderson ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; 207431234768SRichard Henderson break; 20757ad439dfSRichard Henderson 20767ad439dfSRichard Henderson case 0x100: /* SYSCALL */ 20777ad439dfSRichard Henderson gen_excp_1(EXCP_SYSCALL); 207831234768SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 207931234768SRichard Henderson break; 20807ad439dfSRichard Henderson 20817ad439dfSRichard Henderson default: 20827ad439dfSRichard Henderson do_sigill: 20832986721dSRichard Henderson gen_excp_1(EXCP_ILL); 208431234768SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 208531234768SRichard Henderson break; 20867ad439dfSRichard Henderson } 20877ad439dfSRichard Henderson } 2088ba1d0b44SRichard Henderson #endif 20897ad439dfSRichard Henderson 2090deee69a1SRichard Henderson static bool trans_nop(DisasContext *ctx, arg_nop *a) 2091b2167459SRichard Henderson { 2092b2167459SRichard Henderson cond_free(&ctx->null_cond); 209331234768SRichard Henderson return true; 2094b2167459SRichard Henderson } 2095b2167459SRichard Henderson 209640f9f908SRichard Henderson static bool trans_break(DisasContext *ctx, arg_break *a) 209798a9cb79SRichard Henderson { 209831234768SRichard Henderson return gen_excp_iir(ctx, EXCP_BREAK); 209998a9cb79SRichard Henderson } 210098a9cb79SRichard Henderson 2101e36f27efSRichard Henderson static bool trans_sync(DisasContext *ctx, arg_sync *a) 210298a9cb79SRichard Henderson { 210398a9cb79SRichard Henderson /* No point in nullifying the memory barrier. */ 210498a9cb79SRichard Henderson tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); 210598a9cb79SRichard Henderson 210698a9cb79SRichard Henderson cond_free(&ctx->null_cond); 210731234768SRichard Henderson return true; 210898a9cb79SRichard Henderson } 210998a9cb79SRichard Henderson 2110c603e14aSRichard Henderson static bool trans_mfia(DisasContext *ctx, arg_mfia *a) 211198a9cb79SRichard Henderson { 2112c603e14aSRichard Henderson unsigned rt = a->t; 2113eaa3783bSRichard Henderson TCGv_reg tmp = dest_gpr(ctx, rt); 2114eaa3783bSRichard Henderson tcg_gen_movi_reg(tmp, ctx->iaoq_f); 211598a9cb79SRichard Henderson save_gpr(ctx, rt, tmp); 211698a9cb79SRichard Henderson 211798a9cb79SRichard Henderson cond_free(&ctx->null_cond); 211831234768SRichard Henderson return true; 211998a9cb79SRichard Henderson } 212098a9cb79SRichard Henderson 2121c603e14aSRichard Henderson static bool trans_mfsp(DisasContext *ctx, arg_mfsp *a) 212298a9cb79SRichard Henderson { 2123c603e14aSRichard Henderson unsigned rt = a->t; 2124c603e14aSRichard Henderson unsigned rs = a->sp; 212533423472SRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 212633423472SRichard Henderson TCGv_reg t1 = tcg_temp_new(); 212798a9cb79SRichard Henderson 212833423472SRichard Henderson load_spr(ctx, t0, rs); 212933423472SRichard Henderson tcg_gen_shri_i64(t0, t0, 32); 213033423472SRichard Henderson tcg_gen_trunc_i64_reg(t1, t0); 213133423472SRichard Henderson 213233423472SRichard Henderson save_gpr(ctx, rt, t1); 213333423472SRichard Henderson tcg_temp_free(t1); 213433423472SRichard Henderson tcg_temp_free_i64(t0); 213598a9cb79SRichard Henderson 213698a9cb79SRichard Henderson cond_free(&ctx->null_cond); 213731234768SRichard Henderson return true; 213898a9cb79SRichard Henderson } 213998a9cb79SRichard Henderson 2140c603e14aSRichard Henderson static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a) 214198a9cb79SRichard Henderson { 2142c603e14aSRichard Henderson unsigned rt = a->t; 2143c603e14aSRichard Henderson unsigned ctl = a->r; 2144eaa3783bSRichard Henderson TCGv_reg tmp; 214598a9cb79SRichard Henderson 214698a9cb79SRichard Henderson switch (ctl) { 214735136a77SRichard Henderson case CR_SAR: 214898a9cb79SRichard Henderson #ifdef TARGET_HPPA64 2149c603e14aSRichard Henderson if (a->e == 0) { 215098a9cb79SRichard Henderson /* MFSAR without ,W masks low 5 bits. */ 215198a9cb79SRichard Henderson tmp = dest_gpr(ctx, rt); 2152eaa3783bSRichard Henderson tcg_gen_andi_reg(tmp, cpu_sar, 31); 215398a9cb79SRichard Henderson save_gpr(ctx, rt, tmp); 215435136a77SRichard Henderson goto done; 215598a9cb79SRichard Henderson } 215698a9cb79SRichard Henderson #endif 215798a9cb79SRichard Henderson save_gpr(ctx, rt, cpu_sar); 215835136a77SRichard Henderson goto done; 215935136a77SRichard Henderson case CR_IT: /* Interval Timer */ 216035136a77SRichard Henderson /* FIXME: Respect PSW_S bit. */ 216135136a77SRichard Henderson nullify_over(ctx); 216298a9cb79SRichard Henderson tmp = dest_gpr(ctx, rt); 216384b41e65SEmilio G. Cota if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 216449c29d6cSRichard Henderson gen_io_start(); 216549c29d6cSRichard Henderson gen_helper_read_interval_timer(tmp); 216649c29d6cSRichard Henderson gen_io_end(); 216731234768SRichard Henderson ctx->base.is_jmp = DISAS_IAQ_N_STALE; 216849c29d6cSRichard Henderson } else { 216949c29d6cSRichard Henderson gen_helper_read_interval_timer(tmp); 217049c29d6cSRichard Henderson } 217198a9cb79SRichard Henderson save_gpr(ctx, rt, tmp); 217231234768SRichard Henderson return nullify_end(ctx); 217398a9cb79SRichard Henderson case 26: 217498a9cb79SRichard Henderson case 27: 217598a9cb79SRichard Henderson break; 217698a9cb79SRichard Henderson default: 217798a9cb79SRichard Henderson /* All other control registers are privileged. */ 217835136a77SRichard Henderson CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); 217935136a77SRichard Henderson break; 218098a9cb79SRichard Henderson } 218198a9cb79SRichard Henderson 218235136a77SRichard Henderson tmp = get_temp(ctx); 218335136a77SRichard Henderson tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[ctl])); 218435136a77SRichard Henderson save_gpr(ctx, rt, tmp); 218535136a77SRichard Henderson 218635136a77SRichard Henderson done: 218798a9cb79SRichard Henderson cond_free(&ctx->null_cond); 218831234768SRichard Henderson return true; 218998a9cb79SRichard Henderson } 219098a9cb79SRichard Henderson 2191c603e14aSRichard Henderson static bool trans_mtsp(DisasContext *ctx, arg_mtsp *a) 219233423472SRichard Henderson { 2193c603e14aSRichard Henderson unsigned rr = a->r; 2194c603e14aSRichard Henderson unsigned rs = a->sp; 219533423472SRichard Henderson TCGv_i64 t64; 219633423472SRichard Henderson 219733423472SRichard Henderson if (rs >= 5) { 219833423472SRichard Henderson CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); 219933423472SRichard Henderson } 220033423472SRichard Henderson nullify_over(ctx); 220133423472SRichard Henderson 220233423472SRichard Henderson t64 = tcg_temp_new_i64(); 220333423472SRichard Henderson tcg_gen_extu_reg_i64(t64, load_gpr(ctx, rr)); 220433423472SRichard Henderson tcg_gen_shli_i64(t64, t64, 32); 220533423472SRichard Henderson 220633423472SRichard Henderson if (rs >= 4) { 220733423472SRichard Henderson tcg_gen_st_i64(t64, cpu_env, offsetof(CPUHPPAState, sr[rs])); 2208494737b7SRichard Henderson ctx->tb_flags &= ~TB_FLAG_SR_SAME; 220933423472SRichard Henderson } else { 221033423472SRichard Henderson tcg_gen_mov_i64(cpu_sr[rs], t64); 221133423472SRichard Henderson } 221233423472SRichard Henderson tcg_temp_free_i64(t64); 221333423472SRichard Henderson 221431234768SRichard Henderson return nullify_end(ctx); 221533423472SRichard Henderson } 221633423472SRichard Henderson 2217c603e14aSRichard Henderson static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a) 221898a9cb79SRichard Henderson { 2219c603e14aSRichard Henderson unsigned ctl = a->t; 2220c603e14aSRichard Henderson TCGv_reg reg = load_gpr(ctx, a->r); 2221eaa3783bSRichard Henderson TCGv_reg tmp; 222298a9cb79SRichard Henderson 222335136a77SRichard Henderson if (ctl == CR_SAR) { 222498a9cb79SRichard Henderson tmp = tcg_temp_new(); 222535136a77SRichard Henderson tcg_gen_andi_reg(tmp, reg, TARGET_REGISTER_BITS - 1); 222698a9cb79SRichard Henderson save_or_nullify(ctx, cpu_sar, tmp); 222798a9cb79SRichard Henderson tcg_temp_free(tmp); 222898a9cb79SRichard Henderson 222998a9cb79SRichard Henderson cond_free(&ctx->null_cond); 223031234768SRichard Henderson return true; 223198a9cb79SRichard Henderson } 223298a9cb79SRichard Henderson 223335136a77SRichard Henderson /* All other control registers are privileged or read-only. */ 223435136a77SRichard Henderson CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); 223535136a77SRichard Henderson 2236c603e14aSRichard Henderson #ifndef CONFIG_USER_ONLY 223735136a77SRichard Henderson nullify_over(ctx); 223835136a77SRichard Henderson switch (ctl) { 223935136a77SRichard Henderson case CR_IT: 224049c29d6cSRichard Henderson gen_helper_write_interval_timer(cpu_env, reg); 224135136a77SRichard Henderson break; 22424f5f2548SRichard Henderson case CR_EIRR: 22434f5f2548SRichard Henderson gen_helper_write_eirr(cpu_env, reg); 22444f5f2548SRichard Henderson break; 22454f5f2548SRichard Henderson case CR_EIEM: 22464f5f2548SRichard Henderson gen_helper_write_eiem(cpu_env, reg); 224731234768SRichard Henderson ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; 22484f5f2548SRichard Henderson break; 22494f5f2548SRichard Henderson 225035136a77SRichard Henderson case CR_IIASQ: 225135136a77SRichard Henderson case CR_IIAOQ: 225235136a77SRichard Henderson /* FIXME: Respect PSW_Q bit */ 225335136a77SRichard Henderson /* The write advances the queue and stores to the back element. */ 225435136a77SRichard Henderson tmp = get_temp(ctx); 225535136a77SRichard Henderson tcg_gen_ld_reg(tmp, cpu_env, 225635136a77SRichard Henderson offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); 225735136a77SRichard Henderson tcg_gen_st_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[ctl])); 225835136a77SRichard Henderson tcg_gen_st_reg(reg, cpu_env, 225935136a77SRichard Henderson offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); 226035136a77SRichard Henderson break; 226135136a77SRichard Henderson 226235136a77SRichard Henderson default: 226335136a77SRichard Henderson tcg_gen_st_reg(reg, cpu_env, offsetof(CPUHPPAState, cr[ctl])); 226435136a77SRichard Henderson break; 226535136a77SRichard Henderson } 226631234768SRichard Henderson return nullify_end(ctx); 22674f5f2548SRichard Henderson #endif 226835136a77SRichard Henderson } 226935136a77SRichard Henderson 2270c603e14aSRichard Henderson static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a) 227198a9cb79SRichard Henderson { 2272eaa3783bSRichard Henderson TCGv_reg tmp = tcg_temp_new(); 227398a9cb79SRichard Henderson 2274c603e14aSRichard Henderson tcg_gen_not_reg(tmp, load_gpr(ctx, a->r)); 2275eaa3783bSRichard Henderson tcg_gen_andi_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); 227698a9cb79SRichard Henderson save_or_nullify(ctx, cpu_sar, tmp); 227798a9cb79SRichard Henderson tcg_temp_free(tmp); 227898a9cb79SRichard Henderson 227998a9cb79SRichard Henderson cond_free(&ctx->null_cond); 228031234768SRichard Henderson return true; 228198a9cb79SRichard Henderson } 228298a9cb79SRichard Henderson 2283e36f27efSRichard Henderson static bool trans_ldsid(DisasContext *ctx, arg_ldsid *a) 228498a9cb79SRichard Henderson { 2285e36f27efSRichard Henderson TCGv_reg dest = dest_gpr(ctx, a->t); 228698a9cb79SRichard Henderson 22872330504cSHelge Deller #ifdef CONFIG_USER_ONLY 22882330504cSHelge Deller /* We don't implement space registers in user mode. */ 2289eaa3783bSRichard Henderson tcg_gen_movi_reg(dest, 0); 22902330504cSHelge Deller #else 22912330504cSHelge Deller TCGv_i64 t0 = tcg_temp_new_i64(); 22922330504cSHelge Deller 2293e36f27efSRichard Henderson tcg_gen_mov_i64(t0, space_select(ctx, a->sp, load_gpr(ctx, a->b))); 22942330504cSHelge Deller tcg_gen_shri_i64(t0, t0, 32); 22952330504cSHelge Deller tcg_gen_trunc_i64_reg(dest, t0); 22962330504cSHelge Deller 22972330504cSHelge Deller tcg_temp_free_i64(t0); 22982330504cSHelge Deller #endif 2299e36f27efSRichard Henderson save_gpr(ctx, a->t, dest); 230098a9cb79SRichard Henderson 230198a9cb79SRichard Henderson cond_free(&ctx->null_cond); 230231234768SRichard Henderson return true; 230398a9cb79SRichard Henderson } 230498a9cb79SRichard Henderson 2305e36f27efSRichard Henderson static bool trans_rsm(DisasContext *ctx, arg_rsm *a) 2306e36f27efSRichard Henderson { 2307e36f27efSRichard Henderson CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); 2308e1b5a5edSRichard Henderson #ifndef CONFIG_USER_ONLY 2309e1b5a5edSRichard Henderson TCGv_reg tmp; 2310e1b5a5edSRichard Henderson 2311e1b5a5edSRichard Henderson nullify_over(ctx); 2312e1b5a5edSRichard Henderson 2313e1b5a5edSRichard Henderson tmp = get_temp(ctx); 2314e1b5a5edSRichard Henderson tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw)); 2315e36f27efSRichard Henderson tcg_gen_andi_reg(tmp, tmp, ~a->i); 2316e1b5a5edSRichard Henderson gen_helper_swap_system_mask(tmp, cpu_env, tmp); 2317e36f27efSRichard Henderson save_gpr(ctx, a->t, tmp); 2318e1b5a5edSRichard Henderson 2319e1b5a5edSRichard Henderson /* Exit the TB to recognize new interrupts, e.g. PSW_M. */ 232031234768SRichard Henderson ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; 232131234768SRichard Henderson return nullify_end(ctx); 2322e36f27efSRichard Henderson #endif 2323e1b5a5edSRichard Henderson } 2324e1b5a5edSRichard Henderson 2325e36f27efSRichard Henderson static bool trans_ssm(DisasContext *ctx, arg_ssm *a) 2326e1b5a5edSRichard Henderson { 2327e36f27efSRichard Henderson CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); 2328e36f27efSRichard Henderson #ifndef CONFIG_USER_ONLY 2329e1b5a5edSRichard Henderson TCGv_reg tmp; 2330e1b5a5edSRichard Henderson 2331e1b5a5edSRichard Henderson nullify_over(ctx); 2332e1b5a5edSRichard Henderson 2333e1b5a5edSRichard Henderson tmp = get_temp(ctx); 2334e1b5a5edSRichard Henderson tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw)); 2335e36f27efSRichard Henderson tcg_gen_ori_reg(tmp, tmp, a->i); 2336e1b5a5edSRichard Henderson gen_helper_swap_system_mask(tmp, cpu_env, tmp); 2337e36f27efSRichard Henderson save_gpr(ctx, a->t, tmp); 2338e1b5a5edSRichard Henderson 2339e1b5a5edSRichard Henderson /* Exit the TB to recognize new interrupts, e.g. PSW_I. */ 234031234768SRichard Henderson ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; 234131234768SRichard Henderson return nullify_end(ctx); 2342e36f27efSRichard Henderson #endif 2343e1b5a5edSRichard Henderson } 2344e1b5a5edSRichard Henderson 2345c603e14aSRichard Henderson static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a) 2346e1b5a5edSRichard Henderson { 2347e1b5a5edSRichard Henderson CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); 2348c603e14aSRichard Henderson #ifndef CONFIG_USER_ONLY 2349c603e14aSRichard Henderson TCGv_reg tmp, reg; 2350e1b5a5edSRichard Henderson nullify_over(ctx); 2351e1b5a5edSRichard Henderson 2352c603e14aSRichard Henderson reg = load_gpr(ctx, a->r); 2353e1b5a5edSRichard Henderson tmp = get_temp(ctx); 2354e1b5a5edSRichard Henderson gen_helper_swap_system_mask(tmp, cpu_env, reg); 2355e1b5a5edSRichard Henderson 2356e1b5a5edSRichard Henderson /* Exit the TB to recognize new interrupts. */ 235731234768SRichard Henderson ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; 235831234768SRichard Henderson return nullify_end(ctx); 2359c603e14aSRichard Henderson #endif 2360e1b5a5edSRichard Henderson } 2361f49b3537SRichard Henderson 2362e36f27efSRichard Henderson static bool do_rfi(DisasContext *ctx, bool rfi_r) 2363f49b3537SRichard Henderson { 2364f49b3537SRichard Henderson CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); 2365e36f27efSRichard Henderson #ifndef CONFIG_USER_ONLY 2366f49b3537SRichard Henderson nullify_over(ctx); 2367f49b3537SRichard Henderson 2368e36f27efSRichard Henderson if (rfi_r) { 2369f49b3537SRichard Henderson gen_helper_rfi_r(cpu_env); 2370f49b3537SRichard Henderson } else { 2371f49b3537SRichard Henderson gen_helper_rfi(cpu_env); 2372f49b3537SRichard Henderson } 237331234768SRichard Henderson /* Exit the TB to recognize new interrupts. */ 2374f49b3537SRichard Henderson if (ctx->base.singlestep_enabled) { 2375f49b3537SRichard Henderson gen_excp_1(EXCP_DEBUG); 2376f49b3537SRichard Henderson } else { 237707ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 2378f49b3537SRichard Henderson } 237931234768SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 2380f49b3537SRichard Henderson 238131234768SRichard Henderson return nullify_end(ctx); 2382e36f27efSRichard Henderson #endif 2383f49b3537SRichard Henderson } 23846210db05SHelge Deller 2385e36f27efSRichard Henderson static bool trans_rfi(DisasContext *ctx, arg_rfi *a) 2386e36f27efSRichard Henderson { 2387e36f27efSRichard Henderson return do_rfi(ctx, false); 2388e36f27efSRichard Henderson } 2389e36f27efSRichard Henderson 2390e36f27efSRichard Henderson static bool trans_rfi_r(DisasContext *ctx, arg_rfi_r *a) 2391e36f27efSRichard Henderson { 2392e36f27efSRichard Henderson return do_rfi(ctx, true); 2393e36f27efSRichard Henderson } 2394e36f27efSRichard Henderson 239596927adbSRichard Henderson static bool trans_halt(DisasContext *ctx, arg_halt *a) 23966210db05SHelge Deller { 23976210db05SHelge Deller CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); 239896927adbSRichard Henderson #ifndef CONFIG_USER_ONLY 23996210db05SHelge Deller nullify_over(ctx); 24006210db05SHelge Deller gen_helper_halt(cpu_env); 240131234768SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 240231234768SRichard Henderson return nullify_end(ctx); 240396927adbSRichard Henderson #endif 24046210db05SHelge Deller } 240596927adbSRichard Henderson 240696927adbSRichard Henderson static bool trans_reset(DisasContext *ctx, arg_reset *a) 240796927adbSRichard Henderson { 240896927adbSRichard Henderson CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); 240996927adbSRichard Henderson #ifndef CONFIG_USER_ONLY 241096927adbSRichard Henderson nullify_over(ctx); 241196927adbSRichard Henderson gen_helper_reset(cpu_env); 241296927adbSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 241396927adbSRichard Henderson return nullify_end(ctx); 241496927adbSRichard Henderson #endif 241596927adbSRichard Henderson } 2416e1b5a5edSRichard Henderson 2417deee69a1SRichard Henderson static bool trans_nop_addrx(DisasContext *ctx, arg_ldst *a) 241898a9cb79SRichard Henderson { 2419deee69a1SRichard Henderson if (a->m) { 2420deee69a1SRichard Henderson TCGv_reg dest = dest_gpr(ctx, a->b); 2421deee69a1SRichard Henderson TCGv_reg src1 = load_gpr(ctx, a->b); 2422deee69a1SRichard Henderson TCGv_reg src2 = load_gpr(ctx, a->x); 242398a9cb79SRichard Henderson 242498a9cb79SRichard Henderson /* The only thing we need to do is the base register modification. */ 2425eaa3783bSRichard Henderson tcg_gen_add_reg(dest, src1, src2); 2426deee69a1SRichard Henderson save_gpr(ctx, a->b, dest); 2427deee69a1SRichard Henderson } 242898a9cb79SRichard Henderson cond_free(&ctx->null_cond); 242931234768SRichard Henderson return true; 243098a9cb79SRichard Henderson } 243198a9cb79SRichard Henderson 2432deee69a1SRichard Henderson static bool trans_probe(DisasContext *ctx, arg_probe *a) 243398a9cb79SRichard Henderson { 243486f8d05fSRichard Henderson TCGv_reg dest, ofs; 2435eed14219SRichard Henderson TCGv_i32 level, want; 243686f8d05fSRichard Henderson TCGv_tl addr; 243798a9cb79SRichard Henderson 243898a9cb79SRichard Henderson nullify_over(ctx); 243998a9cb79SRichard Henderson 2440deee69a1SRichard Henderson dest = dest_gpr(ctx, a->t); 2441deee69a1SRichard Henderson form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false); 2442eed14219SRichard Henderson 2443deee69a1SRichard Henderson if (a->imm) { 2444deee69a1SRichard Henderson level = tcg_const_i32(a->ri); 244598a9cb79SRichard Henderson } else { 2446eed14219SRichard Henderson level = tcg_temp_new_i32(); 2447deee69a1SRichard Henderson tcg_gen_trunc_reg_i32(level, load_gpr(ctx, a->ri)); 2448eed14219SRichard Henderson tcg_gen_andi_i32(level, level, 3); 244998a9cb79SRichard Henderson } 2450deee69a1SRichard Henderson want = tcg_const_i32(a->write ? PAGE_WRITE : PAGE_READ); 2451eed14219SRichard Henderson 2452eed14219SRichard Henderson gen_helper_probe(dest, cpu_env, addr, level, want); 2453eed14219SRichard Henderson 2454eed14219SRichard Henderson tcg_temp_free_i32(want); 2455eed14219SRichard Henderson tcg_temp_free_i32(level); 2456eed14219SRichard Henderson 2457deee69a1SRichard Henderson save_gpr(ctx, a->t, dest); 245831234768SRichard Henderson return nullify_end(ctx); 245998a9cb79SRichard Henderson } 246098a9cb79SRichard Henderson 2461deee69a1SRichard Henderson static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlbx *a) 24628d6ae7fbSRichard Henderson { 2463deee69a1SRichard Henderson CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); 2464deee69a1SRichard Henderson #ifndef CONFIG_USER_ONLY 24658d6ae7fbSRichard Henderson TCGv_tl addr; 24668d6ae7fbSRichard Henderson TCGv_reg ofs, reg; 24678d6ae7fbSRichard Henderson 24688d6ae7fbSRichard Henderson nullify_over(ctx); 24698d6ae7fbSRichard Henderson 2470deee69a1SRichard Henderson form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false); 2471deee69a1SRichard Henderson reg = load_gpr(ctx, a->r); 2472deee69a1SRichard Henderson if (a->addr) { 24738d6ae7fbSRichard Henderson gen_helper_itlba(cpu_env, addr, reg); 24748d6ae7fbSRichard Henderson } else { 24758d6ae7fbSRichard Henderson gen_helper_itlbp(cpu_env, addr, reg); 24768d6ae7fbSRichard Henderson } 24778d6ae7fbSRichard Henderson 24788d6ae7fbSRichard Henderson /* Exit TB for ITLB change if mmu is enabled. This *should* not be 24798d6ae7fbSRichard Henderson the case, since the OS TLB fill handler runs with mmu disabled. */ 2480deee69a1SRichard Henderson if (!a->data && (ctx->tb_flags & PSW_C)) { 248131234768SRichard Henderson ctx->base.is_jmp = DISAS_IAQ_N_STALE; 248231234768SRichard Henderson } 248331234768SRichard Henderson return nullify_end(ctx); 2484deee69a1SRichard Henderson #endif 24858d6ae7fbSRichard Henderson } 248663300a00SRichard Henderson 2487deee69a1SRichard Henderson static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlbx *a) 248863300a00SRichard Henderson { 2489deee69a1SRichard Henderson CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); 2490deee69a1SRichard Henderson #ifndef CONFIG_USER_ONLY 249163300a00SRichard Henderson TCGv_tl addr; 249263300a00SRichard Henderson TCGv_reg ofs; 249363300a00SRichard Henderson 249463300a00SRichard Henderson nullify_over(ctx); 249563300a00SRichard Henderson 2496deee69a1SRichard Henderson form_gva(ctx, &addr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false); 2497deee69a1SRichard Henderson if (a->m) { 2498deee69a1SRichard Henderson save_gpr(ctx, a->b, ofs); 249963300a00SRichard Henderson } 2500deee69a1SRichard Henderson if (a->local) { 250163300a00SRichard Henderson gen_helper_ptlbe(cpu_env); 250263300a00SRichard Henderson } else { 250363300a00SRichard Henderson gen_helper_ptlb(cpu_env, addr); 250463300a00SRichard Henderson } 250563300a00SRichard Henderson 250663300a00SRichard Henderson /* Exit TB for TLB change if mmu is enabled. */ 2507deee69a1SRichard Henderson if (!a->data && (ctx->tb_flags & PSW_C)) { 250831234768SRichard Henderson ctx->base.is_jmp = DISAS_IAQ_N_STALE; 250931234768SRichard Henderson } 251031234768SRichard Henderson return nullify_end(ctx); 2511deee69a1SRichard Henderson #endif 251263300a00SRichard Henderson } 25132dfcca9fSRichard Henderson 2514deee69a1SRichard Henderson static bool trans_lpa(DisasContext *ctx, arg_ldst *a) 25152dfcca9fSRichard Henderson { 2516deee69a1SRichard Henderson CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); 2517deee69a1SRichard Henderson #ifndef CONFIG_USER_ONLY 25182dfcca9fSRichard Henderson TCGv_tl vaddr; 25192dfcca9fSRichard Henderson TCGv_reg ofs, paddr; 25202dfcca9fSRichard Henderson 25212dfcca9fSRichard Henderson nullify_over(ctx); 25222dfcca9fSRichard Henderson 2523deee69a1SRichard Henderson form_gva(ctx, &vaddr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false); 25242dfcca9fSRichard Henderson 25252dfcca9fSRichard Henderson paddr = tcg_temp_new(); 25262dfcca9fSRichard Henderson gen_helper_lpa(paddr, cpu_env, vaddr); 25272dfcca9fSRichard Henderson 25282dfcca9fSRichard Henderson /* Note that physical address result overrides base modification. */ 2529deee69a1SRichard Henderson if (a->m) { 2530deee69a1SRichard Henderson save_gpr(ctx, a->b, ofs); 25312dfcca9fSRichard Henderson } 2532deee69a1SRichard Henderson save_gpr(ctx, a->t, paddr); 25332dfcca9fSRichard Henderson tcg_temp_free(paddr); 25342dfcca9fSRichard Henderson 253531234768SRichard Henderson return nullify_end(ctx); 2536deee69a1SRichard Henderson #endif 25372dfcca9fSRichard Henderson } 253843a97b81SRichard Henderson 2539deee69a1SRichard Henderson static bool trans_lci(DisasContext *ctx, arg_lci *a) 254043a97b81SRichard Henderson { 254143a97b81SRichard Henderson TCGv_reg ci; 254243a97b81SRichard Henderson 254343a97b81SRichard Henderson CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); 254443a97b81SRichard Henderson 254543a97b81SRichard Henderson /* The Coherence Index is an implementation-defined function of the 254643a97b81SRichard Henderson physical address. Two addresses with the same CI have a coherent 254743a97b81SRichard Henderson view of the cache. Our implementation is to return 0 for all, 254843a97b81SRichard Henderson since the entire address space is coherent. */ 254943a97b81SRichard Henderson ci = tcg_const_reg(0); 2550deee69a1SRichard Henderson save_gpr(ctx, a->t, ci); 255143a97b81SRichard Henderson tcg_temp_free(ci); 255243a97b81SRichard Henderson 255331234768SRichard Henderson cond_free(&ctx->null_cond); 255431234768SRichard Henderson return true; 255543a97b81SRichard Henderson } 255698a9cb79SRichard Henderson 25570c982a28SRichard Henderson static bool trans_add(DisasContext *ctx, arg_rrr_cf_sh *a) 2558b2167459SRichard Henderson { 25590c982a28SRichard Henderson return do_add_reg(ctx, a, false, false, false, false); 2560b2167459SRichard Henderson } 2561b2167459SRichard Henderson 25620c982a28SRichard Henderson static bool trans_add_l(DisasContext *ctx, arg_rrr_cf_sh *a) 2563b2167459SRichard Henderson { 25640c982a28SRichard Henderson return do_add_reg(ctx, a, true, false, false, false); 2565b2167459SRichard Henderson } 2566b2167459SRichard Henderson 25670c982a28SRichard Henderson static bool trans_add_tsv(DisasContext *ctx, arg_rrr_cf_sh *a) 2568b2167459SRichard Henderson { 25690c982a28SRichard Henderson return do_add_reg(ctx, a, false, true, false, false); 2570b2167459SRichard Henderson } 2571b2167459SRichard Henderson 25720c982a28SRichard Henderson static bool trans_add_c(DisasContext *ctx, arg_rrr_cf_sh *a) 2573b2167459SRichard Henderson { 25740c982a28SRichard Henderson return do_add_reg(ctx, a, false, false, false, true); 25750c982a28SRichard Henderson } 2576b2167459SRichard Henderson 25770c982a28SRichard Henderson static bool trans_add_c_tsv(DisasContext *ctx, arg_rrr_cf_sh *a) 25780c982a28SRichard Henderson { 25790c982a28SRichard Henderson return do_add_reg(ctx, a, false, true, false, true); 25800c982a28SRichard Henderson } 25810c982a28SRichard Henderson 25820c982a28SRichard Henderson static bool trans_sub(DisasContext *ctx, arg_rrr_cf *a) 25830c982a28SRichard Henderson { 25840c982a28SRichard Henderson return do_sub_reg(ctx, a, false, false, false); 25850c982a28SRichard Henderson } 25860c982a28SRichard Henderson 25870c982a28SRichard Henderson static bool trans_sub_tsv(DisasContext *ctx, arg_rrr_cf *a) 25880c982a28SRichard Henderson { 25890c982a28SRichard Henderson return do_sub_reg(ctx, a, true, false, false); 25900c982a28SRichard Henderson } 25910c982a28SRichard Henderson 25920c982a28SRichard Henderson static bool trans_sub_tc(DisasContext *ctx, arg_rrr_cf *a) 25930c982a28SRichard Henderson { 25940c982a28SRichard Henderson return do_sub_reg(ctx, a, false, false, true); 25950c982a28SRichard Henderson } 25960c982a28SRichard Henderson 25970c982a28SRichard Henderson static bool trans_sub_tsv_tc(DisasContext *ctx, arg_rrr_cf *a) 25980c982a28SRichard Henderson { 25990c982a28SRichard Henderson return do_sub_reg(ctx, a, true, false, true); 26000c982a28SRichard Henderson } 26010c982a28SRichard Henderson 26020c982a28SRichard Henderson static bool trans_sub_b(DisasContext *ctx, arg_rrr_cf *a) 26030c982a28SRichard Henderson { 26040c982a28SRichard Henderson return do_sub_reg(ctx, a, false, true, false); 26050c982a28SRichard Henderson } 26060c982a28SRichard Henderson 26070c982a28SRichard Henderson static bool trans_sub_b_tsv(DisasContext *ctx, arg_rrr_cf *a) 26080c982a28SRichard Henderson { 26090c982a28SRichard Henderson return do_sub_reg(ctx, a, true, true, false); 26100c982a28SRichard Henderson } 26110c982a28SRichard Henderson 26120c982a28SRichard Henderson static bool trans_andcm(DisasContext *ctx, arg_rrr_cf *a) 26130c982a28SRichard Henderson { 26140c982a28SRichard Henderson return do_log_reg(ctx, a, tcg_gen_andc_reg); 26150c982a28SRichard Henderson } 26160c982a28SRichard Henderson 26170c982a28SRichard Henderson static bool trans_and(DisasContext *ctx, arg_rrr_cf *a) 26180c982a28SRichard Henderson { 26190c982a28SRichard Henderson return do_log_reg(ctx, a, tcg_gen_and_reg); 26200c982a28SRichard Henderson } 26210c982a28SRichard Henderson 26220c982a28SRichard Henderson static bool trans_or(DisasContext *ctx, arg_rrr_cf *a) 26230c982a28SRichard Henderson { 26240c982a28SRichard Henderson if (a->cf == 0) { 26250c982a28SRichard Henderson unsigned r2 = a->r2; 26260c982a28SRichard Henderson unsigned r1 = a->r1; 26270c982a28SRichard Henderson unsigned rt = a->t; 26280c982a28SRichard Henderson 26297aee8189SRichard Henderson if (rt == 0) { /* NOP */ 26307aee8189SRichard Henderson cond_free(&ctx->null_cond); 26317aee8189SRichard Henderson return true; 26327aee8189SRichard Henderson } 26337aee8189SRichard Henderson if (r2 == 0) { /* COPY */ 2634b2167459SRichard Henderson if (r1 == 0) { 2635eaa3783bSRichard Henderson TCGv_reg dest = dest_gpr(ctx, rt); 2636eaa3783bSRichard Henderson tcg_gen_movi_reg(dest, 0); 2637b2167459SRichard Henderson save_gpr(ctx, rt, dest); 2638b2167459SRichard Henderson } else { 2639b2167459SRichard Henderson save_gpr(ctx, rt, cpu_gr[r1]); 2640b2167459SRichard Henderson } 2641b2167459SRichard Henderson cond_free(&ctx->null_cond); 264231234768SRichard Henderson return true; 2643b2167459SRichard Henderson } 26447aee8189SRichard Henderson #ifndef CONFIG_USER_ONLY 26457aee8189SRichard Henderson /* These are QEMU extensions and are nops in the real architecture: 26467aee8189SRichard Henderson * 26477aee8189SRichard Henderson * or %r10,%r10,%r10 -- idle loop; wait for interrupt 26487aee8189SRichard Henderson * or %r31,%r31,%r31 -- death loop; offline cpu 26497aee8189SRichard Henderson * currently implemented as idle. 26507aee8189SRichard Henderson */ 26517aee8189SRichard Henderson if ((rt == 10 || rt == 31) && r1 == rt && r2 == rt) { /* PAUSE */ 26527aee8189SRichard Henderson TCGv_i32 tmp; 26537aee8189SRichard Henderson 26547aee8189SRichard Henderson /* No need to check for supervisor, as userland can only pause 26557aee8189SRichard Henderson until the next timer interrupt. */ 26567aee8189SRichard Henderson nullify_over(ctx); 26577aee8189SRichard Henderson 26587aee8189SRichard Henderson /* Advance the instruction queue. */ 26597aee8189SRichard Henderson copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); 26607aee8189SRichard Henderson copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); 26617aee8189SRichard Henderson nullify_set(ctx, 0); 26627aee8189SRichard Henderson 26637aee8189SRichard Henderson /* Tell the qemu main loop to halt until this cpu has work. */ 26647aee8189SRichard Henderson tmp = tcg_const_i32(1); 26657aee8189SRichard Henderson tcg_gen_st_i32(tmp, cpu_env, -offsetof(HPPACPU, env) + 26667aee8189SRichard Henderson offsetof(CPUState, halted)); 26677aee8189SRichard Henderson tcg_temp_free_i32(tmp); 26687aee8189SRichard Henderson gen_excp_1(EXCP_HALTED); 26697aee8189SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 26707aee8189SRichard Henderson 26717aee8189SRichard Henderson return nullify_end(ctx); 26727aee8189SRichard Henderson } 26737aee8189SRichard Henderson #endif 26747aee8189SRichard Henderson } 26750c982a28SRichard Henderson return do_log_reg(ctx, a, tcg_gen_or_reg); 26767aee8189SRichard Henderson } 2677b2167459SRichard Henderson 26780c982a28SRichard Henderson static bool trans_xor(DisasContext *ctx, arg_rrr_cf *a) 2679b2167459SRichard Henderson { 26800c982a28SRichard Henderson return do_log_reg(ctx, a, tcg_gen_xor_reg); 26810c982a28SRichard Henderson } 26820c982a28SRichard Henderson 26830c982a28SRichard Henderson static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf *a) 26840c982a28SRichard Henderson { 2685eaa3783bSRichard Henderson TCGv_reg tcg_r1, tcg_r2; 2686b2167459SRichard Henderson 26870c982a28SRichard Henderson if (a->cf) { 2688b2167459SRichard Henderson nullify_over(ctx); 2689b2167459SRichard Henderson } 26900c982a28SRichard Henderson tcg_r1 = load_gpr(ctx, a->r1); 26910c982a28SRichard Henderson tcg_r2 = load_gpr(ctx, a->r2); 26920c982a28SRichard Henderson do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf); 269331234768SRichard Henderson return nullify_end(ctx); 2694b2167459SRichard Henderson } 2695b2167459SRichard Henderson 26960c982a28SRichard Henderson static bool trans_uxor(DisasContext *ctx, arg_rrr_cf *a) 2697b2167459SRichard Henderson { 2698eaa3783bSRichard Henderson TCGv_reg tcg_r1, tcg_r2; 2699b2167459SRichard Henderson 27000c982a28SRichard Henderson if (a->cf) { 2701b2167459SRichard Henderson nullify_over(ctx); 2702b2167459SRichard Henderson } 27030c982a28SRichard Henderson tcg_r1 = load_gpr(ctx, a->r1); 27040c982a28SRichard Henderson tcg_r2 = load_gpr(ctx, a->r2); 27050c982a28SRichard Henderson do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, false, tcg_gen_xor_reg); 270631234768SRichard Henderson return nullify_end(ctx); 2707b2167459SRichard Henderson } 2708b2167459SRichard Henderson 27090c982a28SRichard Henderson static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf *a, bool is_tc) 2710b2167459SRichard Henderson { 2711eaa3783bSRichard Henderson TCGv_reg tcg_r1, tcg_r2, tmp; 2712b2167459SRichard Henderson 27130c982a28SRichard Henderson if (a->cf) { 2714b2167459SRichard Henderson nullify_over(ctx); 2715b2167459SRichard Henderson } 27160c982a28SRichard Henderson tcg_r1 = load_gpr(ctx, a->r1); 27170c982a28SRichard Henderson tcg_r2 = load_gpr(ctx, a->r2); 2718b2167459SRichard Henderson tmp = get_temp(ctx); 2719eaa3783bSRichard Henderson tcg_gen_not_reg(tmp, tcg_r2); 27200c982a28SRichard Henderson do_unit(ctx, a->t, tcg_r1, tmp, a->cf, is_tc, tcg_gen_add_reg); 272131234768SRichard Henderson return nullify_end(ctx); 2722b2167459SRichard Henderson } 2723b2167459SRichard Henderson 27240c982a28SRichard Henderson static bool trans_uaddcm(DisasContext *ctx, arg_rrr_cf *a) 2725b2167459SRichard Henderson { 27260c982a28SRichard Henderson return do_uaddcm(ctx, a, false); 27270c982a28SRichard Henderson } 27280c982a28SRichard Henderson 27290c982a28SRichard Henderson static bool trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf *a) 27300c982a28SRichard Henderson { 27310c982a28SRichard Henderson return do_uaddcm(ctx, a, true); 27320c982a28SRichard Henderson } 27330c982a28SRichard Henderson 27340c982a28SRichard Henderson static bool do_dcor(DisasContext *ctx, arg_rr_cf *a, bool is_i) 27350c982a28SRichard Henderson { 2736eaa3783bSRichard Henderson TCGv_reg tmp; 2737b2167459SRichard Henderson 2738b2167459SRichard Henderson nullify_over(ctx); 2739b2167459SRichard Henderson 2740b2167459SRichard Henderson tmp = get_temp(ctx); 2741eaa3783bSRichard Henderson tcg_gen_shri_reg(tmp, cpu_psw_cb, 3); 2742b2167459SRichard Henderson if (!is_i) { 2743eaa3783bSRichard Henderson tcg_gen_not_reg(tmp, tmp); 2744b2167459SRichard Henderson } 2745eaa3783bSRichard Henderson tcg_gen_andi_reg(tmp, tmp, 0x11111111); 2746eaa3783bSRichard Henderson tcg_gen_muli_reg(tmp, tmp, 6); 2747*60e29463SSven Schnelle do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, false, 2748eaa3783bSRichard Henderson is_i ? tcg_gen_add_reg : tcg_gen_sub_reg); 274931234768SRichard Henderson return nullify_end(ctx); 2750b2167459SRichard Henderson } 2751b2167459SRichard Henderson 27520c982a28SRichard Henderson static bool trans_dcor(DisasContext *ctx, arg_rr_cf *a) 2753b2167459SRichard Henderson { 27540c982a28SRichard Henderson return do_dcor(ctx, a, false); 27550c982a28SRichard Henderson } 27560c982a28SRichard Henderson 27570c982a28SRichard Henderson static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf *a) 27580c982a28SRichard Henderson { 27590c982a28SRichard Henderson return do_dcor(ctx, a, true); 27600c982a28SRichard Henderson } 27610c982a28SRichard Henderson 27620c982a28SRichard Henderson static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) 27630c982a28SRichard Henderson { 2764eaa3783bSRichard Henderson TCGv_reg dest, add1, add2, addc, zero, in1, in2; 2765b2167459SRichard Henderson 2766b2167459SRichard Henderson nullify_over(ctx); 2767b2167459SRichard Henderson 27680c982a28SRichard Henderson in1 = load_gpr(ctx, a->r1); 27690c982a28SRichard Henderson in2 = load_gpr(ctx, a->r2); 2770b2167459SRichard Henderson 2771b2167459SRichard Henderson add1 = tcg_temp_new(); 2772b2167459SRichard Henderson add2 = tcg_temp_new(); 2773b2167459SRichard Henderson addc = tcg_temp_new(); 2774b2167459SRichard Henderson dest = tcg_temp_new(); 2775eaa3783bSRichard Henderson zero = tcg_const_reg(0); 2776b2167459SRichard Henderson 2777b2167459SRichard Henderson /* Form R1 << 1 | PSW[CB]{8}. */ 2778eaa3783bSRichard Henderson tcg_gen_add_reg(add1, in1, in1); 2779eaa3783bSRichard Henderson tcg_gen_add_reg(add1, add1, cpu_psw_cb_msb); 2780b2167459SRichard Henderson 2781b2167459SRichard Henderson /* Add or subtract R2, depending on PSW[V]. Proper computation of 2782b2167459SRichard Henderson carry{8} requires that we subtract via + ~R2 + 1, as described in 2783b2167459SRichard Henderson the manual. By extracting and masking V, we can produce the 2784b2167459SRichard Henderson proper inputs to the addition without movcond. */ 2785eaa3783bSRichard Henderson tcg_gen_sari_reg(addc, cpu_psw_v, TARGET_REGISTER_BITS - 1); 2786eaa3783bSRichard Henderson tcg_gen_xor_reg(add2, in2, addc); 2787eaa3783bSRichard Henderson tcg_gen_andi_reg(addc, addc, 1); 2788b2167459SRichard Henderson /* ??? This is only correct for 32-bit. */ 2789b2167459SRichard Henderson tcg_gen_add2_i32(dest, cpu_psw_cb_msb, add1, zero, add2, zero); 2790b2167459SRichard Henderson tcg_gen_add2_i32(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zero); 2791b2167459SRichard Henderson 2792b2167459SRichard Henderson tcg_temp_free(addc); 2793b2167459SRichard Henderson tcg_temp_free(zero); 2794b2167459SRichard Henderson 2795b2167459SRichard Henderson /* Write back the result register. */ 27960c982a28SRichard Henderson save_gpr(ctx, a->t, dest); 2797b2167459SRichard Henderson 2798b2167459SRichard Henderson /* Write back PSW[CB]. */ 2799eaa3783bSRichard Henderson tcg_gen_xor_reg(cpu_psw_cb, add1, add2); 2800eaa3783bSRichard Henderson tcg_gen_xor_reg(cpu_psw_cb, cpu_psw_cb, dest); 2801b2167459SRichard Henderson 2802b2167459SRichard Henderson /* Write back PSW[V] for the division step. */ 2803eaa3783bSRichard Henderson tcg_gen_neg_reg(cpu_psw_v, cpu_psw_cb_msb); 2804eaa3783bSRichard Henderson tcg_gen_xor_reg(cpu_psw_v, cpu_psw_v, in2); 2805b2167459SRichard Henderson 2806b2167459SRichard Henderson /* Install the new nullification. */ 28070c982a28SRichard Henderson if (a->cf) { 2808eaa3783bSRichard Henderson TCGv_reg sv = NULL; 2809b47a4a02SSven Schnelle if (cond_need_sv(a->cf >> 1)) { 2810b2167459SRichard Henderson /* ??? The lshift is supposed to contribute to overflow. */ 2811b2167459SRichard Henderson sv = do_add_sv(ctx, dest, add1, add2); 2812b2167459SRichard Henderson } 28130c982a28SRichard Henderson ctx->null_cond = do_cond(a->cf, dest, cpu_psw_cb_msb, sv); 2814b2167459SRichard Henderson } 2815b2167459SRichard Henderson 2816b2167459SRichard Henderson tcg_temp_free(add1); 2817b2167459SRichard Henderson tcg_temp_free(add2); 2818b2167459SRichard Henderson tcg_temp_free(dest); 2819b2167459SRichard Henderson 282031234768SRichard Henderson return nullify_end(ctx); 2821b2167459SRichard Henderson } 2822b2167459SRichard Henderson 28230588e061SRichard Henderson static bool trans_addi(DisasContext *ctx, arg_rri_cf *a) 2824b2167459SRichard Henderson { 28250588e061SRichard Henderson return do_add_imm(ctx, a, false, false); 28260588e061SRichard Henderson } 28270588e061SRichard Henderson 28280588e061SRichard Henderson static bool trans_addi_tsv(DisasContext *ctx, arg_rri_cf *a) 28290588e061SRichard Henderson { 28300588e061SRichard Henderson return do_add_imm(ctx, a, true, false); 28310588e061SRichard Henderson } 28320588e061SRichard Henderson 28330588e061SRichard Henderson static bool trans_addi_tc(DisasContext *ctx, arg_rri_cf *a) 28340588e061SRichard Henderson { 28350588e061SRichard Henderson return do_add_imm(ctx, a, false, true); 28360588e061SRichard Henderson } 28370588e061SRichard Henderson 28380588e061SRichard Henderson static bool trans_addi_tc_tsv(DisasContext *ctx, arg_rri_cf *a) 28390588e061SRichard Henderson { 28400588e061SRichard Henderson return do_add_imm(ctx, a, true, true); 28410588e061SRichard Henderson } 28420588e061SRichard Henderson 28430588e061SRichard Henderson static bool trans_subi(DisasContext *ctx, arg_rri_cf *a) 28440588e061SRichard Henderson { 28450588e061SRichard Henderson return do_sub_imm(ctx, a, false); 28460588e061SRichard Henderson } 28470588e061SRichard Henderson 28480588e061SRichard Henderson static bool trans_subi_tsv(DisasContext *ctx, arg_rri_cf *a) 28490588e061SRichard Henderson { 28500588e061SRichard Henderson return do_sub_imm(ctx, a, true); 28510588e061SRichard Henderson } 28520588e061SRichard Henderson 28530588e061SRichard Henderson static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf *a) 28540588e061SRichard Henderson { 2855eaa3783bSRichard Henderson TCGv_reg tcg_im, tcg_r2; 2856b2167459SRichard Henderson 28570588e061SRichard Henderson if (a->cf) { 2858b2167459SRichard Henderson nullify_over(ctx); 2859b2167459SRichard Henderson } 2860b2167459SRichard Henderson 28610588e061SRichard Henderson tcg_im = load_const(ctx, a->i); 28620588e061SRichard Henderson tcg_r2 = load_gpr(ctx, a->r); 28630588e061SRichard Henderson do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf); 2864b2167459SRichard Henderson 286531234768SRichard Henderson return nullify_end(ctx); 2866b2167459SRichard Henderson } 2867b2167459SRichard Henderson 28681cd012a5SRichard Henderson static bool trans_ld(DisasContext *ctx, arg_ldst *a) 286996d6407fSRichard Henderson { 28701cd012a5SRichard Henderson return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0, 28711cd012a5SRichard Henderson a->disp, a->sp, a->m, a->size | MO_TE); 287296d6407fSRichard Henderson } 287396d6407fSRichard Henderson 28741cd012a5SRichard Henderson static bool trans_st(DisasContext *ctx, arg_ldst *a) 287596d6407fSRichard Henderson { 28761cd012a5SRichard Henderson assert(a->x == 0 && a->scale == 0); 28771cd012a5SRichard Henderson return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE); 287896d6407fSRichard Henderson } 287996d6407fSRichard Henderson 28801cd012a5SRichard Henderson static bool trans_ldc(DisasContext *ctx, arg_ldst *a) 288196d6407fSRichard Henderson { 28821cd012a5SRichard Henderson TCGMemOp mop = MO_TEUL | MO_ALIGN_16 | a->size; 288386f8d05fSRichard Henderson TCGv_reg zero, dest, ofs; 288486f8d05fSRichard Henderson TCGv_tl addr; 288596d6407fSRichard Henderson 288696d6407fSRichard Henderson nullify_over(ctx); 288796d6407fSRichard Henderson 28881cd012a5SRichard Henderson if (a->m) { 288986f8d05fSRichard Henderson /* Base register modification. Make sure if RT == RB, 289086f8d05fSRichard Henderson we see the result of the load. */ 289196d6407fSRichard Henderson dest = get_temp(ctx); 289296d6407fSRichard Henderson } else { 28931cd012a5SRichard Henderson dest = dest_gpr(ctx, a->t); 289496d6407fSRichard Henderson } 289596d6407fSRichard Henderson 28961cd012a5SRichard Henderson form_gva(ctx, &addr, &ofs, a->b, a->x, a->scale ? a->size : 0, 28971cd012a5SRichard Henderson a->disp, a->sp, a->m, ctx->mmu_idx == MMU_PHYS_IDX); 2898eaa3783bSRichard Henderson zero = tcg_const_reg(0); 289986f8d05fSRichard Henderson tcg_gen_atomic_xchg_reg(dest, addr, zero, ctx->mmu_idx, mop); 29001cd012a5SRichard Henderson if (a->m) { 29011cd012a5SRichard Henderson save_gpr(ctx, a->b, ofs); 290296d6407fSRichard Henderson } 29031cd012a5SRichard Henderson save_gpr(ctx, a->t, dest); 290496d6407fSRichard Henderson 290531234768SRichard Henderson return nullify_end(ctx); 290696d6407fSRichard Henderson } 290796d6407fSRichard Henderson 29081cd012a5SRichard Henderson static bool trans_stby(DisasContext *ctx, arg_stby *a) 290996d6407fSRichard Henderson { 291086f8d05fSRichard Henderson TCGv_reg ofs, val; 291186f8d05fSRichard Henderson TCGv_tl addr; 291296d6407fSRichard Henderson 291396d6407fSRichard Henderson nullify_over(ctx); 291496d6407fSRichard Henderson 29151cd012a5SRichard Henderson form_gva(ctx, &addr, &ofs, a->b, 0, 0, a->disp, a->sp, a->m, 291686f8d05fSRichard Henderson ctx->mmu_idx == MMU_PHYS_IDX); 29171cd012a5SRichard Henderson val = load_gpr(ctx, a->r); 29181cd012a5SRichard Henderson if (a->a) { 2919f9f46db4SEmilio G. Cota if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2920f9f46db4SEmilio G. Cota gen_helper_stby_e_parallel(cpu_env, addr, val); 2921f9f46db4SEmilio G. Cota } else { 292296d6407fSRichard Henderson gen_helper_stby_e(cpu_env, addr, val); 2923f9f46db4SEmilio G. Cota } 2924f9f46db4SEmilio G. Cota } else { 2925f9f46db4SEmilio G. Cota if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2926f9f46db4SEmilio G. Cota gen_helper_stby_b_parallel(cpu_env, addr, val); 292796d6407fSRichard Henderson } else { 292896d6407fSRichard Henderson gen_helper_stby_b(cpu_env, addr, val); 292996d6407fSRichard Henderson } 2930f9f46db4SEmilio G. Cota } 29311cd012a5SRichard Henderson if (a->m) { 293286f8d05fSRichard Henderson tcg_gen_andi_reg(ofs, ofs, ~3); 29331cd012a5SRichard Henderson save_gpr(ctx, a->b, ofs); 293496d6407fSRichard Henderson } 293596d6407fSRichard Henderson 293631234768SRichard Henderson return nullify_end(ctx); 293796d6407fSRichard Henderson } 293896d6407fSRichard Henderson 29391cd012a5SRichard Henderson static bool trans_lda(DisasContext *ctx, arg_ldst *a) 2940d0a851ccSRichard Henderson { 2941d0a851ccSRichard Henderson int hold_mmu_idx = ctx->mmu_idx; 2942d0a851ccSRichard Henderson 2943d0a851ccSRichard Henderson CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); 2944d0a851ccSRichard Henderson ctx->mmu_idx = MMU_PHYS_IDX; 29451cd012a5SRichard Henderson trans_ld(ctx, a); 2946d0a851ccSRichard Henderson ctx->mmu_idx = hold_mmu_idx; 294731234768SRichard Henderson return true; 2948d0a851ccSRichard Henderson } 2949d0a851ccSRichard Henderson 29501cd012a5SRichard Henderson static bool trans_sta(DisasContext *ctx, arg_ldst *a) 2951d0a851ccSRichard Henderson { 2952d0a851ccSRichard Henderson int hold_mmu_idx = ctx->mmu_idx; 2953d0a851ccSRichard Henderson 2954d0a851ccSRichard Henderson CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); 2955d0a851ccSRichard Henderson ctx->mmu_idx = MMU_PHYS_IDX; 29561cd012a5SRichard Henderson trans_st(ctx, a); 2957d0a851ccSRichard Henderson ctx->mmu_idx = hold_mmu_idx; 295831234768SRichard Henderson return true; 2959d0a851ccSRichard Henderson } 296095412a61SRichard Henderson 29610588e061SRichard Henderson static bool trans_ldil(DisasContext *ctx, arg_ldil *a) 2962b2167459SRichard Henderson { 29630588e061SRichard Henderson TCGv_reg tcg_rt = dest_gpr(ctx, a->t); 2964b2167459SRichard Henderson 29650588e061SRichard Henderson tcg_gen_movi_reg(tcg_rt, a->i); 29660588e061SRichard Henderson save_gpr(ctx, a->t, tcg_rt); 2967b2167459SRichard Henderson cond_free(&ctx->null_cond); 296831234768SRichard Henderson return true; 2969b2167459SRichard Henderson } 2970b2167459SRichard Henderson 29710588e061SRichard Henderson static bool trans_addil(DisasContext *ctx, arg_addil *a) 2972b2167459SRichard Henderson { 29730588e061SRichard Henderson TCGv_reg tcg_rt = load_gpr(ctx, a->r); 2974eaa3783bSRichard Henderson TCGv_reg tcg_r1 = dest_gpr(ctx, 1); 2975b2167459SRichard Henderson 29760588e061SRichard Henderson tcg_gen_addi_reg(tcg_r1, tcg_rt, a->i); 2977b2167459SRichard Henderson save_gpr(ctx, 1, tcg_r1); 2978b2167459SRichard Henderson cond_free(&ctx->null_cond); 297931234768SRichard Henderson return true; 2980b2167459SRichard Henderson } 2981b2167459SRichard Henderson 29820588e061SRichard Henderson static bool trans_ldo(DisasContext *ctx, arg_ldo *a) 2983b2167459SRichard Henderson { 29840588e061SRichard Henderson TCGv_reg tcg_rt = dest_gpr(ctx, a->t); 2985b2167459SRichard Henderson 2986b2167459SRichard Henderson /* Special case rb == 0, for the LDI pseudo-op. 2987b2167459SRichard Henderson The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */ 29880588e061SRichard Henderson if (a->b == 0) { 29890588e061SRichard Henderson tcg_gen_movi_reg(tcg_rt, a->i); 2990b2167459SRichard Henderson } else { 29910588e061SRichard Henderson tcg_gen_addi_reg(tcg_rt, cpu_gr[a->b], a->i); 2992b2167459SRichard Henderson } 29930588e061SRichard Henderson save_gpr(ctx, a->t, tcg_rt); 2994b2167459SRichard Henderson cond_free(&ctx->null_cond); 299531234768SRichard Henderson return true; 2996b2167459SRichard Henderson } 2997b2167459SRichard Henderson 299801afb7beSRichard Henderson static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1, 299901afb7beSRichard Henderson unsigned c, unsigned f, unsigned n, int disp) 300098cd9ca7SRichard Henderson { 300101afb7beSRichard Henderson TCGv_reg dest, in2, sv; 300298cd9ca7SRichard Henderson DisasCond cond; 300398cd9ca7SRichard Henderson 300498cd9ca7SRichard Henderson in2 = load_gpr(ctx, r); 300598cd9ca7SRichard Henderson dest = get_temp(ctx); 300698cd9ca7SRichard Henderson 3007eaa3783bSRichard Henderson tcg_gen_sub_reg(dest, in1, in2); 300898cd9ca7SRichard Henderson 3009f764718dSRichard Henderson sv = NULL; 3010b47a4a02SSven Schnelle if (cond_need_sv(c)) { 301198cd9ca7SRichard Henderson sv = do_sub_sv(ctx, dest, in1, in2); 301298cd9ca7SRichard Henderson } 301398cd9ca7SRichard Henderson 301401afb7beSRichard Henderson cond = do_sub_cond(c * 2 + f, dest, in1, in2, sv); 301501afb7beSRichard Henderson return do_cbranch(ctx, disp, n, &cond); 301698cd9ca7SRichard Henderson } 301798cd9ca7SRichard Henderson 301801afb7beSRichard Henderson static bool trans_cmpb(DisasContext *ctx, arg_cmpb *a) 301998cd9ca7SRichard Henderson { 302001afb7beSRichard Henderson nullify_over(ctx); 302101afb7beSRichard Henderson return do_cmpb(ctx, a->r2, load_gpr(ctx, a->r1), a->c, a->f, a->n, a->disp); 302201afb7beSRichard Henderson } 302301afb7beSRichard Henderson 302401afb7beSRichard Henderson static bool trans_cmpbi(DisasContext *ctx, arg_cmpbi *a) 302501afb7beSRichard Henderson { 302601afb7beSRichard Henderson nullify_over(ctx); 302701afb7beSRichard Henderson return do_cmpb(ctx, a->r, load_const(ctx, a->i), a->c, a->f, a->n, a->disp); 302801afb7beSRichard Henderson } 302901afb7beSRichard Henderson 303001afb7beSRichard Henderson static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1, 303101afb7beSRichard Henderson unsigned c, unsigned f, unsigned n, int disp) 303201afb7beSRichard Henderson { 303301afb7beSRichard Henderson TCGv_reg dest, in2, sv, cb_msb; 303498cd9ca7SRichard Henderson DisasCond cond; 303598cd9ca7SRichard Henderson 303698cd9ca7SRichard Henderson in2 = load_gpr(ctx, r); 303798cd9ca7SRichard Henderson dest = dest_gpr(ctx, r); 3038f764718dSRichard Henderson sv = NULL; 3039f764718dSRichard Henderson cb_msb = NULL; 304098cd9ca7SRichard Henderson 3041b47a4a02SSven Schnelle if (cond_need_cb(c)) { 304298cd9ca7SRichard Henderson cb_msb = get_temp(ctx); 3043eaa3783bSRichard Henderson tcg_gen_movi_reg(cb_msb, 0); 3044eaa3783bSRichard Henderson tcg_gen_add2_reg(dest, cb_msb, in1, cb_msb, in2, cb_msb); 3045b47a4a02SSven Schnelle } else { 3046eaa3783bSRichard Henderson tcg_gen_add_reg(dest, in1, in2); 3047b47a4a02SSven Schnelle } 3048b47a4a02SSven Schnelle if (cond_need_sv(c)) { 304998cd9ca7SRichard Henderson sv = do_add_sv(ctx, dest, in1, in2); 305098cd9ca7SRichard Henderson } 305198cd9ca7SRichard Henderson 305201afb7beSRichard Henderson cond = do_cond(c * 2 + f, dest, cb_msb, sv); 305301afb7beSRichard Henderson return do_cbranch(ctx, disp, n, &cond); 305498cd9ca7SRichard Henderson } 305598cd9ca7SRichard Henderson 305601afb7beSRichard Henderson static bool trans_addb(DisasContext *ctx, arg_addb *a) 305798cd9ca7SRichard Henderson { 305801afb7beSRichard Henderson nullify_over(ctx); 305901afb7beSRichard Henderson return do_addb(ctx, a->r2, load_gpr(ctx, a->r1), a->c, a->f, a->n, a->disp); 306001afb7beSRichard Henderson } 306101afb7beSRichard Henderson 306201afb7beSRichard Henderson static bool trans_addbi(DisasContext *ctx, arg_addbi *a) 306301afb7beSRichard Henderson { 306401afb7beSRichard Henderson nullify_over(ctx); 306501afb7beSRichard Henderson return do_addb(ctx, a->r, load_const(ctx, a->i), a->c, a->f, a->n, a->disp); 306601afb7beSRichard Henderson } 306701afb7beSRichard Henderson 306801afb7beSRichard Henderson static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) 306901afb7beSRichard Henderson { 3070eaa3783bSRichard Henderson TCGv_reg tmp, tcg_r; 307198cd9ca7SRichard Henderson DisasCond cond; 307298cd9ca7SRichard Henderson 307398cd9ca7SRichard Henderson nullify_over(ctx); 307498cd9ca7SRichard Henderson 307598cd9ca7SRichard Henderson tmp = tcg_temp_new(); 307601afb7beSRichard Henderson tcg_r = load_gpr(ctx, a->r); 3077eaa3783bSRichard Henderson tcg_gen_shl_reg(tmp, tcg_r, cpu_sar); 307898cd9ca7SRichard Henderson 307901afb7beSRichard Henderson cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); 308098cd9ca7SRichard Henderson tcg_temp_free(tmp); 308101afb7beSRichard Henderson return do_cbranch(ctx, a->disp, a->n, &cond); 308298cd9ca7SRichard Henderson } 308398cd9ca7SRichard Henderson 308401afb7beSRichard Henderson static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a) 308598cd9ca7SRichard Henderson { 308601afb7beSRichard Henderson TCGv_reg tmp, tcg_r; 308701afb7beSRichard Henderson DisasCond cond; 308801afb7beSRichard Henderson 308901afb7beSRichard Henderson nullify_over(ctx); 309001afb7beSRichard Henderson 309101afb7beSRichard Henderson tmp = tcg_temp_new(); 309201afb7beSRichard Henderson tcg_r = load_gpr(ctx, a->r); 309301afb7beSRichard Henderson tcg_gen_shli_reg(tmp, tcg_r, a->p); 309401afb7beSRichard Henderson 309501afb7beSRichard Henderson cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); 309601afb7beSRichard Henderson tcg_temp_free(tmp); 309701afb7beSRichard Henderson return do_cbranch(ctx, a->disp, a->n, &cond); 309801afb7beSRichard Henderson } 309901afb7beSRichard Henderson 310001afb7beSRichard Henderson static bool trans_movb(DisasContext *ctx, arg_movb *a) 310101afb7beSRichard Henderson { 3102eaa3783bSRichard Henderson TCGv_reg dest; 310398cd9ca7SRichard Henderson DisasCond cond; 310498cd9ca7SRichard Henderson 310598cd9ca7SRichard Henderson nullify_over(ctx); 310698cd9ca7SRichard Henderson 310701afb7beSRichard Henderson dest = dest_gpr(ctx, a->r2); 310801afb7beSRichard Henderson if (a->r1 == 0) { 3109eaa3783bSRichard Henderson tcg_gen_movi_reg(dest, 0); 311098cd9ca7SRichard Henderson } else { 311101afb7beSRichard Henderson tcg_gen_mov_reg(dest, cpu_gr[a->r1]); 311298cd9ca7SRichard Henderson } 311398cd9ca7SRichard Henderson 311401afb7beSRichard Henderson cond = do_sed_cond(a->c, dest); 311501afb7beSRichard Henderson return do_cbranch(ctx, a->disp, a->n, &cond); 311601afb7beSRichard Henderson } 311701afb7beSRichard Henderson 311801afb7beSRichard Henderson static bool trans_movbi(DisasContext *ctx, arg_movbi *a) 311901afb7beSRichard Henderson { 312001afb7beSRichard Henderson TCGv_reg dest; 312101afb7beSRichard Henderson DisasCond cond; 312201afb7beSRichard Henderson 312301afb7beSRichard Henderson nullify_over(ctx); 312401afb7beSRichard Henderson 312501afb7beSRichard Henderson dest = dest_gpr(ctx, a->r); 312601afb7beSRichard Henderson tcg_gen_movi_reg(dest, a->i); 312701afb7beSRichard Henderson 312801afb7beSRichard Henderson cond = do_sed_cond(a->c, dest); 312901afb7beSRichard Henderson return do_cbranch(ctx, a->disp, a->n, &cond); 313098cd9ca7SRichard Henderson } 313198cd9ca7SRichard Henderson 313230878590SRichard Henderson static bool trans_shrpw_sar(DisasContext *ctx, arg_shrpw_sar *a) 31330b1347d2SRichard Henderson { 3134eaa3783bSRichard Henderson TCGv_reg dest; 31350b1347d2SRichard Henderson 313630878590SRichard Henderson if (a->c) { 31370b1347d2SRichard Henderson nullify_over(ctx); 31380b1347d2SRichard Henderson } 31390b1347d2SRichard Henderson 314030878590SRichard Henderson dest = dest_gpr(ctx, a->t); 314130878590SRichard Henderson if (a->r1 == 0) { 314230878590SRichard Henderson tcg_gen_ext32u_reg(dest, load_gpr(ctx, a->r2)); 3143eaa3783bSRichard Henderson tcg_gen_shr_reg(dest, dest, cpu_sar); 314430878590SRichard Henderson } else if (a->r1 == a->r2) { 31450b1347d2SRichard Henderson TCGv_i32 t32 = tcg_temp_new_i32(); 314630878590SRichard Henderson tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2)); 31470b1347d2SRichard Henderson tcg_gen_rotr_i32(t32, t32, cpu_sar); 3148eaa3783bSRichard Henderson tcg_gen_extu_i32_reg(dest, t32); 31490b1347d2SRichard Henderson tcg_temp_free_i32(t32); 31500b1347d2SRichard Henderson } else { 31510b1347d2SRichard Henderson TCGv_i64 t = tcg_temp_new_i64(); 31520b1347d2SRichard Henderson TCGv_i64 s = tcg_temp_new_i64(); 31530b1347d2SRichard Henderson 315430878590SRichard Henderson tcg_gen_concat_reg_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r1)); 3155eaa3783bSRichard Henderson tcg_gen_extu_reg_i64(s, cpu_sar); 31560b1347d2SRichard Henderson tcg_gen_shr_i64(t, t, s); 3157eaa3783bSRichard Henderson tcg_gen_trunc_i64_reg(dest, t); 31580b1347d2SRichard Henderson 31590b1347d2SRichard Henderson tcg_temp_free_i64(t); 31600b1347d2SRichard Henderson tcg_temp_free_i64(s); 31610b1347d2SRichard Henderson } 316230878590SRichard Henderson save_gpr(ctx, a->t, dest); 31630b1347d2SRichard Henderson 31640b1347d2SRichard Henderson /* Install the new nullification. */ 31650b1347d2SRichard Henderson cond_free(&ctx->null_cond); 316630878590SRichard Henderson if (a->c) { 316730878590SRichard Henderson ctx->null_cond = do_sed_cond(a->c, dest); 31680b1347d2SRichard Henderson } 316931234768SRichard Henderson return nullify_end(ctx); 31700b1347d2SRichard Henderson } 31710b1347d2SRichard Henderson 317230878590SRichard Henderson static bool trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a) 31730b1347d2SRichard Henderson { 317430878590SRichard Henderson unsigned sa = 31 - a->cpos; 3175eaa3783bSRichard Henderson TCGv_reg dest, t2; 31760b1347d2SRichard Henderson 317730878590SRichard Henderson if (a->c) { 31780b1347d2SRichard Henderson nullify_over(ctx); 31790b1347d2SRichard Henderson } 31800b1347d2SRichard Henderson 318130878590SRichard Henderson dest = dest_gpr(ctx, a->t); 318230878590SRichard Henderson t2 = load_gpr(ctx, a->r2); 318330878590SRichard Henderson if (a->r1 == a->r2) { 31840b1347d2SRichard Henderson TCGv_i32 t32 = tcg_temp_new_i32(); 3185eaa3783bSRichard Henderson tcg_gen_trunc_reg_i32(t32, t2); 31860b1347d2SRichard Henderson tcg_gen_rotri_i32(t32, t32, sa); 3187eaa3783bSRichard Henderson tcg_gen_extu_i32_reg(dest, t32); 31880b1347d2SRichard Henderson tcg_temp_free_i32(t32); 318930878590SRichard Henderson } else if (a->r1 == 0) { 3190eaa3783bSRichard Henderson tcg_gen_extract_reg(dest, t2, sa, 32 - sa); 31910b1347d2SRichard Henderson } else { 3192eaa3783bSRichard Henderson TCGv_reg t0 = tcg_temp_new(); 3193eaa3783bSRichard Henderson tcg_gen_extract_reg(t0, t2, sa, 32 - sa); 319430878590SRichard Henderson tcg_gen_deposit_reg(dest, t0, cpu_gr[a->r1], 32 - sa, sa); 31950b1347d2SRichard Henderson tcg_temp_free(t0); 31960b1347d2SRichard Henderson } 319730878590SRichard Henderson save_gpr(ctx, a->t, dest); 31980b1347d2SRichard Henderson 31990b1347d2SRichard Henderson /* Install the new nullification. */ 32000b1347d2SRichard Henderson cond_free(&ctx->null_cond); 320130878590SRichard Henderson if (a->c) { 320230878590SRichard Henderson ctx->null_cond = do_sed_cond(a->c, dest); 32030b1347d2SRichard Henderson } 320431234768SRichard Henderson return nullify_end(ctx); 32050b1347d2SRichard Henderson } 32060b1347d2SRichard Henderson 320730878590SRichard Henderson static bool trans_extrw_sar(DisasContext *ctx, arg_extrw_sar *a) 32080b1347d2SRichard Henderson { 320930878590SRichard Henderson unsigned len = 32 - a->clen; 3210eaa3783bSRichard Henderson TCGv_reg dest, src, tmp; 32110b1347d2SRichard Henderson 321230878590SRichard Henderson if (a->c) { 32130b1347d2SRichard Henderson nullify_over(ctx); 32140b1347d2SRichard Henderson } 32150b1347d2SRichard Henderson 321630878590SRichard Henderson dest = dest_gpr(ctx, a->t); 321730878590SRichard Henderson src = load_gpr(ctx, a->r); 32180b1347d2SRichard Henderson tmp = tcg_temp_new(); 32190b1347d2SRichard Henderson 32200b1347d2SRichard Henderson /* Recall that SAR is using big-endian bit numbering. */ 3221eaa3783bSRichard Henderson tcg_gen_xori_reg(tmp, cpu_sar, TARGET_REGISTER_BITS - 1); 322230878590SRichard Henderson if (a->se) { 3223eaa3783bSRichard Henderson tcg_gen_sar_reg(dest, src, tmp); 3224eaa3783bSRichard Henderson tcg_gen_sextract_reg(dest, dest, 0, len); 32250b1347d2SRichard Henderson } else { 3226eaa3783bSRichard Henderson tcg_gen_shr_reg(dest, src, tmp); 3227eaa3783bSRichard Henderson tcg_gen_extract_reg(dest, dest, 0, len); 32280b1347d2SRichard Henderson } 32290b1347d2SRichard Henderson tcg_temp_free(tmp); 323030878590SRichard Henderson save_gpr(ctx, a->t, dest); 32310b1347d2SRichard Henderson 32320b1347d2SRichard Henderson /* Install the new nullification. */ 32330b1347d2SRichard Henderson cond_free(&ctx->null_cond); 323430878590SRichard Henderson if (a->c) { 323530878590SRichard Henderson ctx->null_cond = do_sed_cond(a->c, dest); 32360b1347d2SRichard Henderson } 323731234768SRichard Henderson return nullify_end(ctx); 32380b1347d2SRichard Henderson } 32390b1347d2SRichard Henderson 324030878590SRichard Henderson static bool trans_extrw_imm(DisasContext *ctx, arg_extrw_imm *a) 32410b1347d2SRichard Henderson { 324230878590SRichard Henderson unsigned len = 32 - a->clen; 324330878590SRichard Henderson unsigned cpos = 31 - a->pos; 3244eaa3783bSRichard Henderson TCGv_reg dest, src; 32450b1347d2SRichard Henderson 324630878590SRichard Henderson if (a->c) { 32470b1347d2SRichard Henderson nullify_over(ctx); 32480b1347d2SRichard Henderson } 32490b1347d2SRichard Henderson 325030878590SRichard Henderson dest = dest_gpr(ctx, a->t); 325130878590SRichard Henderson src = load_gpr(ctx, a->r); 325230878590SRichard Henderson if (a->se) { 3253eaa3783bSRichard Henderson tcg_gen_sextract_reg(dest, src, cpos, len); 32540b1347d2SRichard Henderson } else { 3255eaa3783bSRichard Henderson tcg_gen_extract_reg(dest, src, cpos, len); 32560b1347d2SRichard Henderson } 325730878590SRichard Henderson save_gpr(ctx, a->t, dest); 32580b1347d2SRichard Henderson 32590b1347d2SRichard Henderson /* Install the new nullification. */ 32600b1347d2SRichard Henderson cond_free(&ctx->null_cond); 326130878590SRichard Henderson if (a->c) { 326230878590SRichard Henderson ctx->null_cond = do_sed_cond(a->c, dest); 32630b1347d2SRichard Henderson } 326431234768SRichard Henderson return nullify_end(ctx); 32650b1347d2SRichard Henderson } 32660b1347d2SRichard Henderson 326730878590SRichard Henderson static bool trans_depwi_imm(DisasContext *ctx, arg_depwi_imm *a) 32680b1347d2SRichard Henderson { 326930878590SRichard Henderson unsigned len = 32 - a->clen; 3270eaa3783bSRichard Henderson target_sreg mask0, mask1; 3271eaa3783bSRichard Henderson TCGv_reg dest; 32720b1347d2SRichard Henderson 327330878590SRichard Henderson if (a->c) { 32740b1347d2SRichard Henderson nullify_over(ctx); 32750b1347d2SRichard Henderson } 327630878590SRichard Henderson if (a->cpos + len > 32) { 327730878590SRichard Henderson len = 32 - a->cpos; 32780b1347d2SRichard Henderson } 32790b1347d2SRichard Henderson 328030878590SRichard Henderson dest = dest_gpr(ctx, a->t); 328130878590SRichard Henderson mask0 = deposit64(0, a->cpos, len, a->i); 328230878590SRichard Henderson mask1 = deposit64(-1, a->cpos, len, a->i); 32830b1347d2SRichard Henderson 328430878590SRichard Henderson if (a->nz) { 328530878590SRichard Henderson TCGv_reg src = load_gpr(ctx, a->t); 32860b1347d2SRichard Henderson if (mask1 != -1) { 3287eaa3783bSRichard Henderson tcg_gen_andi_reg(dest, src, mask1); 32880b1347d2SRichard Henderson src = dest; 32890b1347d2SRichard Henderson } 3290eaa3783bSRichard Henderson tcg_gen_ori_reg(dest, src, mask0); 32910b1347d2SRichard Henderson } else { 3292eaa3783bSRichard Henderson tcg_gen_movi_reg(dest, mask0); 32930b1347d2SRichard Henderson } 329430878590SRichard Henderson save_gpr(ctx, a->t, dest); 32950b1347d2SRichard Henderson 32960b1347d2SRichard Henderson /* Install the new nullification. */ 32970b1347d2SRichard Henderson cond_free(&ctx->null_cond); 329830878590SRichard Henderson if (a->c) { 329930878590SRichard Henderson ctx->null_cond = do_sed_cond(a->c, dest); 33000b1347d2SRichard Henderson } 330131234768SRichard Henderson return nullify_end(ctx); 33020b1347d2SRichard Henderson } 33030b1347d2SRichard Henderson 330430878590SRichard Henderson static bool trans_depw_imm(DisasContext *ctx, arg_depw_imm *a) 33050b1347d2SRichard Henderson { 330630878590SRichard Henderson unsigned rs = a->nz ? a->t : 0; 330730878590SRichard Henderson unsigned len = 32 - a->clen; 3308eaa3783bSRichard Henderson TCGv_reg dest, val; 33090b1347d2SRichard Henderson 331030878590SRichard Henderson if (a->c) { 33110b1347d2SRichard Henderson nullify_over(ctx); 33120b1347d2SRichard Henderson } 331330878590SRichard Henderson if (a->cpos + len > 32) { 331430878590SRichard Henderson len = 32 - a->cpos; 33150b1347d2SRichard Henderson } 33160b1347d2SRichard Henderson 331730878590SRichard Henderson dest = dest_gpr(ctx, a->t); 331830878590SRichard Henderson val = load_gpr(ctx, a->r); 33190b1347d2SRichard Henderson if (rs == 0) { 332030878590SRichard Henderson tcg_gen_deposit_z_reg(dest, val, a->cpos, len); 33210b1347d2SRichard Henderson } else { 332230878590SRichard Henderson tcg_gen_deposit_reg(dest, cpu_gr[rs], val, a->cpos, len); 33230b1347d2SRichard Henderson } 332430878590SRichard Henderson save_gpr(ctx, a->t, dest); 33250b1347d2SRichard Henderson 33260b1347d2SRichard Henderson /* Install the new nullification. */ 33270b1347d2SRichard Henderson cond_free(&ctx->null_cond); 332830878590SRichard Henderson if (a->c) { 332930878590SRichard Henderson ctx->null_cond = do_sed_cond(a->c, dest); 33300b1347d2SRichard Henderson } 333131234768SRichard Henderson return nullify_end(ctx); 33320b1347d2SRichard Henderson } 33330b1347d2SRichard Henderson 333430878590SRichard Henderson static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c, 333530878590SRichard Henderson unsigned nz, unsigned clen, TCGv_reg val) 33360b1347d2SRichard Henderson { 33370b1347d2SRichard Henderson unsigned rs = nz ? rt : 0; 33380b1347d2SRichard Henderson unsigned len = 32 - clen; 333930878590SRichard Henderson TCGv_reg mask, tmp, shift, dest; 33400b1347d2SRichard Henderson unsigned msb = 1U << (len - 1); 33410b1347d2SRichard Henderson 33420b1347d2SRichard Henderson if (c) { 33430b1347d2SRichard Henderson nullify_over(ctx); 33440b1347d2SRichard Henderson } 33450b1347d2SRichard Henderson 33460b1347d2SRichard Henderson dest = dest_gpr(ctx, rt); 33470b1347d2SRichard Henderson shift = tcg_temp_new(); 33480b1347d2SRichard Henderson tmp = tcg_temp_new(); 33490b1347d2SRichard Henderson 33500b1347d2SRichard Henderson /* Convert big-endian bit numbering in SAR to left-shift. */ 3351eaa3783bSRichard Henderson tcg_gen_xori_reg(shift, cpu_sar, TARGET_REGISTER_BITS - 1); 33520b1347d2SRichard Henderson 3353eaa3783bSRichard Henderson mask = tcg_const_reg(msb + (msb - 1)); 3354eaa3783bSRichard Henderson tcg_gen_and_reg(tmp, val, mask); 33550b1347d2SRichard Henderson if (rs) { 3356eaa3783bSRichard Henderson tcg_gen_shl_reg(mask, mask, shift); 3357eaa3783bSRichard Henderson tcg_gen_shl_reg(tmp, tmp, shift); 3358eaa3783bSRichard Henderson tcg_gen_andc_reg(dest, cpu_gr[rs], mask); 3359eaa3783bSRichard Henderson tcg_gen_or_reg(dest, dest, tmp); 33600b1347d2SRichard Henderson } else { 3361eaa3783bSRichard Henderson tcg_gen_shl_reg(dest, tmp, shift); 33620b1347d2SRichard Henderson } 33630b1347d2SRichard Henderson tcg_temp_free(shift); 33640b1347d2SRichard Henderson tcg_temp_free(mask); 33650b1347d2SRichard Henderson tcg_temp_free(tmp); 33660b1347d2SRichard Henderson save_gpr(ctx, rt, dest); 33670b1347d2SRichard Henderson 33680b1347d2SRichard Henderson /* Install the new nullification. */ 33690b1347d2SRichard Henderson cond_free(&ctx->null_cond); 33700b1347d2SRichard Henderson if (c) { 33710b1347d2SRichard Henderson ctx->null_cond = do_sed_cond(c, dest); 33720b1347d2SRichard Henderson } 337331234768SRichard Henderson return nullify_end(ctx); 33740b1347d2SRichard Henderson } 33750b1347d2SRichard Henderson 337630878590SRichard Henderson static bool trans_depw_sar(DisasContext *ctx, arg_depw_sar *a) 337730878590SRichard Henderson { 337830878590SRichard Henderson return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, load_gpr(ctx, a->r)); 337930878590SRichard Henderson } 338030878590SRichard Henderson 338130878590SRichard Henderson static bool trans_depwi_sar(DisasContext *ctx, arg_depwi_sar *a) 338230878590SRichard Henderson { 338330878590SRichard Henderson return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, load_const(ctx, a->i)); 338430878590SRichard Henderson } 33850b1347d2SRichard Henderson 33868340f534SRichard Henderson static bool trans_be(DisasContext *ctx, arg_be *a) 338798cd9ca7SRichard Henderson { 3388660eefe1SRichard Henderson TCGv_reg tmp; 338998cd9ca7SRichard Henderson 3390c301f34eSRichard Henderson #ifdef CONFIG_USER_ONLY 339198cd9ca7SRichard Henderson /* ??? It seems like there should be a good way of using 339298cd9ca7SRichard Henderson "be disp(sr2, r0)", the canonical gateway entry mechanism 339398cd9ca7SRichard Henderson to our advantage. But that appears to be inconvenient to 339498cd9ca7SRichard Henderson manage along side branch delay slots. Therefore we handle 339598cd9ca7SRichard Henderson entry into the gateway page via absolute address. */ 339698cd9ca7SRichard Henderson /* Since we don't implement spaces, just branch. Do notice the special 339798cd9ca7SRichard Henderson case of "be disp(*,r0)" using a direct branch to disp, so that we can 339898cd9ca7SRichard Henderson goto_tb to the TB containing the syscall. */ 33998340f534SRichard Henderson if (a->b == 0) { 34008340f534SRichard Henderson return do_dbranch(ctx, a->disp, a->l, a->n); 340198cd9ca7SRichard Henderson } 3402c301f34eSRichard Henderson #else 3403c301f34eSRichard Henderson nullify_over(ctx); 3404660eefe1SRichard Henderson #endif 3405660eefe1SRichard Henderson 3406660eefe1SRichard Henderson tmp = get_temp(ctx); 34078340f534SRichard Henderson tcg_gen_addi_reg(tmp, load_gpr(ctx, a->b), a->disp); 3408660eefe1SRichard Henderson tmp = do_ibranch_priv(ctx, tmp); 3409c301f34eSRichard Henderson 3410c301f34eSRichard Henderson #ifdef CONFIG_USER_ONLY 34118340f534SRichard Henderson return do_ibranch(ctx, tmp, a->l, a->n); 3412c301f34eSRichard Henderson #else 3413c301f34eSRichard Henderson TCGv_i64 new_spc = tcg_temp_new_i64(); 3414c301f34eSRichard Henderson 34158340f534SRichard Henderson load_spr(ctx, new_spc, a->sp); 34168340f534SRichard Henderson if (a->l) { 3417c301f34eSRichard Henderson copy_iaoq_entry(cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var); 3418c301f34eSRichard Henderson tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_f); 3419c301f34eSRichard Henderson } 34208340f534SRichard Henderson if (a->n && use_nullify_skip(ctx)) { 3421c301f34eSRichard Henderson tcg_gen_mov_reg(cpu_iaoq_f, tmp); 3422c301f34eSRichard Henderson tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); 3423c301f34eSRichard Henderson tcg_gen_mov_i64(cpu_iasq_f, new_spc); 3424c301f34eSRichard Henderson tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f); 3425c301f34eSRichard Henderson } else { 3426c301f34eSRichard Henderson copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); 3427c301f34eSRichard Henderson if (ctx->iaoq_b == -1) { 3428c301f34eSRichard Henderson tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); 3429c301f34eSRichard Henderson } 3430c301f34eSRichard Henderson tcg_gen_mov_reg(cpu_iaoq_b, tmp); 3431c301f34eSRichard Henderson tcg_gen_mov_i64(cpu_iasq_b, new_spc); 34328340f534SRichard Henderson nullify_set(ctx, a->n); 3433c301f34eSRichard Henderson } 3434c301f34eSRichard Henderson tcg_temp_free_i64(new_spc); 3435c301f34eSRichard Henderson tcg_gen_lookup_and_goto_ptr(); 343631234768SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 343731234768SRichard Henderson return nullify_end(ctx); 3438c301f34eSRichard Henderson #endif 343998cd9ca7SRichard Henderson } 344098cd9ca7SRichard Henderson 34418340f534SRichard Henderson static bool trans_bl(DisasContext *ctx, arg_bl *a) 344298cd9ca7SRichard Henderson { 34438340f534SRichard Henderson return do_dbranch(ctx, iaoq_dest(ctx, a->disp), a->l, a->n); 344498cd9ca7SRichard Henderson } 344598cd9ca7SRichard Henderson 34468340f534SRichard Henderson static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) 344743e05652SRichard Henderson { 34488340f534SRichard Henderson target_ureg dest = iaoq_dest(ctx, a->disp); 344943e05652SRichard Henderson 345043e05652SRichard Henderson /* Make sure the caller hasn't done something weird with the queue. 345143e05652SRichard Henderson * ??? This is not quite the same as the PSW[B] bit, which would be 345243e05652SRichard Henderson * expensive to track. Real hardware will trap for 345343e05652SRichard Henderson * b gateway 345443e05652SRichard Henderson * b gateway+4 (in delay slot of first branch) 345543e05652SRichard Henderson * However, checking for a non-sequential instruction queue *will* 345643e05652SRichard Henderson * diagnose the security hole 345743e05652SRichard Henderson * b gateway 345843e05652SRichard Henderson * b evil 345943e05652SRichard Henderson * in which instructions at evil would run with increased privs. 346043e05652SRichard Henderson */ 346143e05652SRichard Henderson if (ctx->iaoq_b == -1 || ctx->iaoq_b != ctx->iaoq_f + 4) { 346243e05652SRichard Henderson return gen_illegal(ctx); 346343e05652SRichard Henderson } 346443e05652SRichard Henderson 346543e05652SRichard Henderson #ifndef CONFIG_USER_ONLY 346643e05652SRichard Henderson if (ctx->tb_flags & PSW_C) { 346743e05652SRichard Henderson CPUHPPAState *env = ctx->cs->env_ptr; 346843e05652SRichard Henderson int type = hppa_artype_for_page(env, ctx->base.pc_next); 346943e05652SRichard Henderson /* If we could not find a TLB entry, then we need to generate an 347043e05652SRichard Henderson ITLB miss exception so the kernel will provide it. 347143e05652SRichard Henderson The resulting TLB fill operation will invalidate this TB and 347243e05652SRichard Henderson we will re-translate, at which point we *will* be able to find 347343e05652SRichard Henderson the TLB entry and determine if this is in fact a gateway page. */ 347443e05652SRichard Henderson if (type < 0) { 347531234768SRichard Henderson gen_excp(ctx, EXCP_ITLB_MISS); 347631234768SRichard Henderson return true; 347743e05652SRichard Henderson } 347843e05652SRichard Henderson /* No change for non-gateway pages or for priv decrease. */ 347943e05652SRichard Henderson if (type >= 4 && type - 4 < ctx->privilege) { 348043e05652SRichard Henderson dest = deposit32(dest, 0, 2, type - 4); 348143e05652SRichard Henderson } 348243e05652SRichard Henderson } else { 348343e05652SRichard Henderson dest &= -4; /* priv = 0 */ 348443e05652SRichard Henderson } 348543e05652SRichard Henderson #endif 348643e05652SRichard Henderson 34878340f534SRichard Henderson return do_dbranch(ctx, dest, a->l, a->n); 348843e05652SRichard Henderson } 348943e05652SRichard Henderson 34908340f534SRichard Henderson static bool trans_blr(DisasContext *ctx, arg_blr *a) 349198cd9ca7SRichard Henderson { 3492eaa3783bSRichard Henderson TCGv_reg tmp = get_temp(ctx); 349398cd9ca7SRichard Henderson 34948340f534SRichard Henderson tcg_gen_shli_reg(tmp, load_gpr(ctx, a->x), 3); 3495eaa3783bSRichard Henderson tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8); 3496660eefe1SRichard Henderson /* The computation here never changes privilege level. */ 34978340f534SRichard Henderson return do_ibranch(ctx, tmp, a->l, a->n); 349898cd9ca7SRichard Henderson } 349998cd9ca7SRichard Henderson 35008340f534SRichard Henderson static bool trans_bv(DisasContext *ctx, arg_bv *a) 350198cd9ca7SRichard Henderson { 3502eaa3783bSRichard Henderson TCGv_reg dest; 350398cd9ca7SRichard Henderson 35048340f534SRichard Henderson if (a->x == 0) { 35058340f534SRichard Henderson dest = load_gpr(ctx, a->b); 350698cd9ca7SRichard Henderson } else { 350798cd9ca7SRichard Henderson dest = get_temp(ctx); 35088340f534SRichard Henderson tcg_gen_shli_reg(dest, load_gpr(ctx, a->x), 3); 35098340f534SRichard Henderson tcg_gen_add_reg(dest, dest, load_gpr(ctx, a->b)); 351098cd9ca7SRichard Henderson } 3511660eefe1SRichard Henderson dest = do_ibranch_priv(ctx, dest); 35128340f534SRichard Henderson return do_ibranch(ctx, dest, 0, a->n); 351398cd9ca7SRichard Henderson } 351498cd9ca7SRichard Henderson 35158340f534SRichard Henderson static bool trans_bve(DisasContext *ctx, arg_bve *a) 351698cd9ca7SRichard Henderson { 3517660eefe1SRichard Henderson TCGv_reg dest; 351898cd9ca7SRichard Henderson 3519c301f34eSRichard Henderson #ifdef CONFIG_USER_ONLY 35208340f534SRichard Henderson dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b)); 35218340f534SRichard Henderson return do_ibranch(ctx, dest, a->l, a->n); 3522c301f34eSRichard Henderson #else 3523c301f34eSRichard Henderson nullify_over(ctx); 35248340f534SRichard Henderson dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b)); 3525c301f34eSRichard Henderson 3526c301f34eSRichard Henderson copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); 3527c301f34eSRichard Henderson if (ctx->iaoq_b == -1) { 3528c301f34eSRichard Henderson tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); 3529c301f34eSRichard Henderson } 3530c301f34eSRichard Henderson copy_iaoq_entry(cpu_iaoq_b, -1, dest); 3531c301f34eSRichard Henderson tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest)); 35328340f534SRichard Henderson if (a->l) { 35338340f534SRichard Henderson copy_iaoq_entry(cpu_gr[a->l], ctx->iaoq_n, ctx->iaoq_n_var); 3534c301f34eSRichard Henderson } 35358340f534SRichard Henderson nullify_set(ctx, a->n); 3536c301f34eSRichard Henderson tcg_gen_lookup_and_goto_ptr(); 353731234768SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 353831234768SRichard Henderson return nullify_end(ctx); 3539c301f34eSRichard Henderson #endif 354098cd9ca7SRichard Henderson } 354198cd9ca7SRichard Henderson 35421ca74648SRichard Henderson /* 35431ca74648SRichard Henderson * Float class 0 35441ca74648SRichard Henderson */ 3545ebe9383cSRichard Henderson 35461ca74648SRichard Henderson static void gen_fcpy_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) 3547ebe9383cSRichard Henderson { 3548ebe9383cSRichard Henderson tcg_gen_mov_i32(dst, src); 3549ebe9383cSRichard Henderson } 3550ebe9383cSRichard Henderson 35511ca74648SRichard Henderson static bool trans_fcpy_f(DisasContext *ctx, arg_fclass01 *a) 35521ca74648SRichard Henderson { 35531ca74648SRichard Henderson return do_fop_wew(ctx, a->t, a->r, gen_fcpy_f); 35541ca74648SRichard Henderson } 35551ca74648SRichard Henderson 3556ebe9383cSRichard Henderson static void gen_fcpy_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) 3557ebe9383cSRichard Henderson { 3558ebe9383cSRichard Henderson tcg_gen_mov_i64(dst, src); 3559ebe9383cSRichard Henderson } 3560ebe9383cSRichard Henderson 35611ca74648SRichard Henderson static bool trans_fcpy_d(DisasContext *ctx, arg_fclass01 *a) 35621ca74648SRichard Henderson { 35631ca74648SRichard Henderson return do_fop_ded(ctx, a->t, a->r, gen_fcpy_d); 35641ca74648SRichard Henderson } 35651ca74648SRichard Henderson 35661ca74648SRichard Henderson static void gen_fabs_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) 3567ebe9383cSRichard Henderson { 3568ebe9383cSRichard Henderson tcg_gen_andi_i32(dst, src, INT32_MAX); 3569ebe9383cSRichard Henderson } 3570ebe9383cSRichard Henderson 35711ca74648SRichard Henderson static bool trans_fabs_f(DisasContext *ctx, arg_fclass01 *a) 35721ca74648SRichard Henderson { 35731ca74648SRichard Henderson return do_fop_wew(ctx, a->t, a->r, gen_fabs_f); 35741ca74648SRichard Henderson } 35751ca74648SRichard Henderson 3576ebe9383cSRichard Henderson static void gen_fabs_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) 3577ebe9383cSRichard Henderson { 3578ebe9383cSRichard Henderson tcg_gen_andi_i64(dst, src, INT64_MAX); 3579ebe9383cSRichard Henderson } 3580ebe9383cSRichard Henderson 35811ca74648SRichard Henderson static bool trans_fabs_d(DisasContext *ctx, arg_fclass01 *a) 35821ca74648SRichard Henderson { 35831ca74648SRichard Henderson return do_fop_ded(ctx, a->t, a->r, gen_fabs_d); 35841ca74648SRichard Henderson } 35851ca74648SRichard Henderson 35861ca74648SRichard Henderson static bool trans_fsqrt_f(DisasContext *ctx, arg_fclass01 *a) 35871ca74648SRichard Henderson { 35881ca74648SRichard Henderson return do_fop_wew(ctx, a->t, a->r, gen_helper_fsqrt_s); 35891ca74648SRichard Henderson } 35901ca74648SRichard Henderson 35911ca74648SRichard Henderson static bool trans_fsqrt_d(DisasContext *ctx, arg_fclass01 *a) 35921ca74648SRichard Henderson { 35931ca74648SRichard Henderson return do_fop_ded(ctx, a->t, a->r, gen_helper_fsqrt_d); 35941ca74648SRichard Henderson } 35951ca74648SRichard Henderson 35961ca74648SRichard Henderson static bool trans_frnd_f(DisasContext *ctx, arg_fclass01 *a) 35971ca74648SRichard Henderson { 35981ca74648SRichard Henderson return do_fop_wew(ctx, a->t, a->r, gen_helper_frnd_s); 35991ca74648SRichard Henderson } 36001ca74648SRichard Henderson 36011ca74648SRichard Henderson static bool trans_frnd_d(DisasContext *ctx, arg_fclass01 *a) 36021ca74648SRichard Henderson { 36031ca74648SRichard Henderson return do_fop_ded(ctx, a->t, a->r, gen_helper_frnd_d); 36041ca74648SRichard Henderson } 36051ca74648SRichard Henderson 36061ca74648SRichard Henderson static void gen_fneg_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) 3607ebe9383cSRichard Henderson { 3608ebe9383cSRichard Henderson tcg_gen_xori_i32(dst, src, INT32_MIN); 3609ebe9383cSRichard Henderson } 3610ebe9383cSRichard Henderson 36111ca74648SRichard Henderson static bool trans_fneg_f(DisasContext *ctx, arg_fclass01 *a) 36121ca74648SRichard Henderson { 36131ca74648SRichard Henderson return do_fop_wew(ctx, a->t, a->r, gen_fneg_f); 36141ca74648SRichard Henderson } 36151ca74648SRichard Henderson 3616ebe9383cSRichard Henderson static void gen_fneg_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) 3617ebe9383cSRichard Henderson { 3618ebe9383cSRichard Henderson tcg_gen_xori_i64(dst, src, INT64_MIN); 3619ebe9383cSRichard Henderson } 3620ebe9383cSRichard Henderson 36211ca74648SRichard Henderson static bool trans_fneg_d(DisasContext *ctx, arg_fclass01 *a) 36221ca74648SRichard Henderson { 36231ca74648SRichard Henderson return do_fop_ded(ctx, a->t, a->r, gen_fneg_d); 36241ca74648SRichard Henderson } 36251ca74648SRichard Henderson 36261ca74648SRichard Henderson static void gen_fnegabs_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) 3627ebe9383cSRichard Henderson { 3628ebe9383cSRichard Henderson tcg_gen_ori_i32(dst, src, INT32_MIN); 3629ebe9383cSRichard Henderson } 3630ebe9383cSRichard Henderson 36311ca74648SRichard Henderson static bool trans_fnegabs_f(DisasContext *ctx, arg_fclass01 *a) 36321ca74648SRichard Henderson { 36331ca74648SRichard Henderson return do_fop_wew(ctx, a->t, a->r, gen_fnegabs_f); 36341ca74648SRichard Henderson } 36351ca74648SRichard Henderson 3636ebe9383cSRichard Henderson static void gen_fnegabs_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) 3637ebe9383cSRichard Henderson { 3638ebe9383cSRichard Henderson tcg_gen_ori_i64(dst, src, INT64_MIN); 3639ebe9383cSRichard Henderson } 3640ebe9383cSRichard Henderson 36411ca74648SRichard Henderson static bool trans_fnegabs_d(DisasContext *ctx, arg_fclass01 *a) 36421ca74648SRichard Henderson { 36431ca74648SRichard Henderson return do_fop_ded(ctx, a->t, a->r, gen_fnegabs_d); 36441ca74648SRichard Henderson } 36451ca74648SRichard Henderson 36461ca74648SRichard Henderson /* 36471ca74648SRichard Henderson * Float class 1 36481ca74648SRichard Henderson */ 36491ca74648SRichard Henderson 36501ca74648SRichard Henderson static bool trans_fcnv_d_f(DisasContext *ctx, arg_fclass01 *a) 36511ca74648SRichard Henderson { 36521ca74648SRichard Henderson return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_s); 36531ca74648SRichard Henderson } 36541ca74648SRichard Henderson 36551ca74648SRichard Henderson static bool trans_fcnv_f_d(DisasContext *ctx, arg_fclass01 *a) 36561ca74648SRichard Henderson { 36571ca74648SRichard Henderson return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_d); 36581ca74648SRichard Henderson } 36591ca74648SRichard Henderson 36601ca74648SRichard Henderson static bool trans_fcnv_w_f(DisasContext *ctx, arg_fclass01 *a) 36611ca74648SRichard Henderson { 36621ca74648SRichard Henderson return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_w_s); 36631ca74648SRichard Henderson } 36641ca74648SRichard Henderson 36651ca74648SRichard Henderson static bool trans_fcnv_q_f(DisasContext *ctx, arg_fclass01 *a) 36661ca74648SRichard Henderson { 36671ca74648SRichard Henderson return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_dw_s); 36681ca74648SRichard Henderson } 36691ca74648SRichard Henderson 36701ca74648SRichard Henderson static bool trans_fcnv_w_d(DisasContext *ctx, arg_fclass01 *a) 36711ca74648SRichard Henderson { 36721ca74648SRichard Henderson return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_w_d); 36731ca74648SRichard Henderson } 36741ca74648SRichard Henderson 36751ca74648SRichard Henderson static bool trans_fcnv_q_d(DisasContext *ctx, arg_fclass01 *a) 36761ca74648SRichard Henderson { 36771ca74648SRichard Henderson return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_dw_d); 36781ca74648SRichard Henderson } 36791ca74648SRichard Henderson 36801ca74648SRichard Henderson static bool trans_fcnv_f_w(DisasContext *ctx, arg_fclass01 *a) 36811ca74648SRichard Henderson { 36821ca74648SRichard Henderson return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_s_w); 36831ca74648SRichard Henderson } 36841ca74648SRichard Henderson 36851ca74648SRichard Henderson static bool trans_fcnv_d_w(DisasContext *ctx, arg_fclass01 *a) 36861ca74648SRichard Henderson { 36871ca74648SRichard Henderson return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_w); 36881ca74648SRichard Henderson } 36891ca74648SRichard Henderson 36901ca74648SRichard Henderson static bool trans_fcnv_f_q(DisasContext *ctx, arg_fclass01 *a) 36911ca74648SRichard Henderson { 36921ca74648SRichard Henderson return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_dw); 36931ca74648SRichard Henderson } 36941ca74648SRichard Henderson 36951ca74648SRichard Henderson static bool trans_fcnv_d_q(DisasContext *ctx, arg_fclass01 *a) 36961ca74648SRichard Henderson { 36971ca74648SRichard Henderson return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_d_dw); 36981ca74648SRichard Henderson } 36991ca74648SRichard Henderson 37001ca74648SRichard Henderson static bool trans_fcnv_t_f_w(DisasContext *ctx, arg_fclass01 *a) 37011ca74648SRichard Henderson { 37021ca74648SRichard Henderson return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_t_s_w); 37031ca74648SRichard Henderson } 37041ca74648SRichard Henderson 37051ca74648SRichard Henderson static bool trans_fcnv_t_d_w(DisasContext *ctx, arg_fclass01 *a) 37061ca74648SRichard Henderson { 37071ca74648SRichard Henderson return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_t_d_w); 37081ca74648SRichard Henderson } 37091ca74648SRichard Henderson 37101ca74648SRichard Henderson static bool trans_fcnv_t_f_q(DisasContext *ctx, arg_fclass01 *a) 37111ca74648SRichard Henderson { 37121ca74648SRichard Henderson return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_t_s_dw); 37131ca74648SRichard Henderson } 37141ca74648SRichard Henderson 37151ca74648SRichard Henderson static bool trans_fcnv_t_d_q(DisasContext *ctx, arg_fclass01 *a) 37161ca74648SRichard Henderson { 37171ca74648SRichard Henderson return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_t_d_dw); 37181ca74648SRichard Henderson } 37191ca74648SRichard Henderson 37201ca74648SRichard Henderson static bool trans_fcnv_uw_f(DisasContext *ctx, arg_fclass01 *a) 37211ca74648SRichard Henderson { 37221ca74648SRichard Henderson return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_uw_s); 37231ca74648SRichard Henderson } 37241ca74648SRichard Henderson 37251ca74648SRichard Henderson static bool trans_fcnv_uq_f(DisasContext *ctx, arg_fclass01 *a) 37261ca74648SRichard Henderson { 37271ca74648SRichard Henderson return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_udw_s); 37281ca74648SRichard Henderson } 37291ca74648SRichard Henderson 37301ca74648SRichard Henderson static bool trans_fcnv_uw_d(DisasContext *ctx, arg_fclass01 *a) 37311ca74648SRichard Henderson { 37321ca74648SRichard Henderson return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_uw_d); 37331ca74648SRichard Henderson } 37341ca74648SRichard Henderson 37351ca74648SRichard Henderson static bool trans_fcnv_uq_d(DisasContext *ctx, arg_fclass01 *a) 37361ca74648SRichard Henderson { 37371ca74648SRichard Henderson return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_udw_d); 37381ca74648SRichard Henderson } 37391ca74648SRichard Henderson 37401ca74648SRichard Henderson static bool trans_fcnv_f_uw(DisasContext *ctx, arg_fclass01 *a) 37411ca74648SRichard Henderson { 37421ca74648SRichard Henderson return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_s_uw); 37431ca74648SRichard Henderson } 37441ca74648SRichard Henderson 37451ca74648SRichard Henderson static bool trans_fcnv_d_uw(DisasContext *ctx, arg_fclass01 *a) 37461ca74648SRichard Henderson { 37471ca74648SRichard Henderson return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_uw); 37481ca74648SRichard Henderson } 37491ca74648SRichard Henderson 37501ca74648SRichard Henderson static bool trans_fcnv_f_uq(DisasContext *ctx, arg_fclass01 *a) 37511ca74648SRichard Henderson { 37521ca74648SRichard Henderson return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_udw); 37531ca74648SRichard Henderson } 37541ca74648SRichard Henderson 37551ca74648SRichard Henderson static bool trans_fcnv_d_uq(DisasContext *ctx, arg_fclass01 *a) 37561ca74648SRichard Henderson { 37571ca74648SRichard Henderson return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_d_udw); 37581ca74648SRichard Henderson } 37591ca74648SRichard Henderson 37601ca74648SRichard Henderson static bool trans_fcnv_t_f_uw(DisasContext *ctx, arg_fclass01 *a) 37611ca74648SRichard Henderson { 37621ca74648SRichard Henderson return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_t_s_uw); 37631ca74648SRichard Henderson } 37641ca74648SRichard Henderson 37651ca74648SRichard Henderson static bool trans_fcnv_t_d_uw(DisasContext *ctx, arg_fclass01 *a) 37661ca74648SRichard Henderson { 37671ca74648SRichard Henderson return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_t_d_uw); 37681ca74648SRichard Henderson } 37691ca74648SRichard Henderson 37701ca74648SRichard Henderson static bool trans_fcnv_t_f_uq(DisasContext *ctx, arg_fclass01 *a) 37711ca74648SRichard Henderson { 37721ca74648SRichard Henderson return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_t_s_udw); 37731ca74648SRichard Henderson } 37741ca74648SRichard Henderson 37751ca74648SRichard Henderson static bool trans_fcnv_t_d_uq(DisasContext *ctx, arg_fclass01 *a) 37761ca74648SRichard Henderson { 37771ca74648SRichard Henderson return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_t_d_udw); 37781ca74648SRichard Henderson } 37791ca74648SRichard Henderson 37801ca74648SRichard Henderson /* 37811ca74648SRichard Henderson * Float class 2 37821ca74648SRichard Henderson */ 37831ca74648SRichard Henderson 37841ca74648SRichard Henderson static bool trans_fcmp_f(DisasContext *ctx, arg_fclass2 *a) 3785ebe9383cSRichard Henderson { 3786ebe9383cSRichard Henderson TCGv_i32 ta, tb, tc, ty; 3787ebe9383cSRichard Henderson 3788ebe9383cSRichard Henderson nullify_over(ctx); 3789ebe9383cSRichard Henderson 37901ca74648SRichard Henderson ta = load_frw0_i32(a->r1); 37911ca74648SRichard Henderson tb = load_frw0_i32(a->r2); 37921ca74648SRichard Henderson ty = tcg_const_i32(a->y); 37931ca74648SRichard Henderson tc = tcg_const_i32(a->c); 3794ebe9383cSRichard Henderson 3795ebe9383cSRichard Henderson gen_helper_fcmp_s(cpu_env, ta, tb, ty, tc); 3796ebe9383cSRichard Henderson 3797ebe9383cSRichard Henderson tcg_temp_free_i32(ta); 3798ebe9383cSRichard Henderson tcg_temp_free_i32(tb); 3799ebe9383cSRichard Henderson tcg_temp_free_i32(ty); 3800ebe9383cSRichard Henderson tcg_temp_free_i32(tc); 3801ebe9383cSRichard Henderson 38021ca74648SRichard Henderson return nullify_end(ctx); 3803ebe9383cSRichard Henderson } 3804ebe9383cSRichard Henderson 38051ca74648SRichard Henderson static bool trans_fcmp_d(DisasContext *ctx, arg_fclass2 *a) 3806ebe9383cSRichard Henderson { 3807ebe9383cSRichard Henderson TCGv_i64 ta, tb; 3808ebe9383cSRichard Henderson TCGv_i32 tc, ty; 3809ebe9383cSRichard Henderson 3810ebe9383cSRichard Henderson nullify_over(ctx); 3811ebe9383cSRichard Henderson 38121ca74648SRichard Henderson ta = load_frd0(a->r1); 38131ca74648SRichard Henderson tb = load_frd0(a->r2); 38141ca74648SRichard Henderson ty = tcg_const_i32(a->y); 38151ca74648SRichard Henderson tc = tcg_const_i32(a->c); 3816ebe9383cSRichard Henderson 3817ebe9383cSRichard Henderson gen_helper_fcmp_d(cpu_env, ta, tb, ty, tc); 3818ebe9383cSRichard Henderson 3819ebe9383cSRichard Henderson tcg_temp_free_i64(ta); 3820ebe9383cSRichard Henderson tcg_temp_free_i64(tb); 3821ebe9383cSRichard Henderson tcg_temp_free_i32(ty); 3822ebe9383cSRichard Henderson tcg_temp_free_i32(tc); 3823ebe9383cSRichard Henderson 382431234768SRichard Henderson return nullify_end(ctx); 3825ebe9383cSRichard Henderson } 3826ebe9383cSRichard Henderson 38271ca74648SRichard Henderson static bool trans_ftest(DisasContext *ctx, arg_ftest *a) 3828ebe9383cSRichard Henderson { 3829eaa3783bSRichard Henderson TCGv_reg t; 3830ebe9383cSRichard Henderson 3831ebe9383cSRichard Henderson nullify_over(ctx); 3832ebe9383cSRichard Henderson 38331ca74648SRichard Henderson t = get_temp(ctx); 3834eaa3783bSRichard Henderson tcg_gen_ld32u_reg(t, cpu_env, offsetof(CPUHPPAState, fr0_shadow)); 3835ebe9383cSRichard Henderson 38361ca74648SRichard Henderson if (a->y == 1) { 3837ebe9383cSRichard Henderson int mask; 3838ebe9383cSRichard Henderson bool inv = false; 3839ebe9383cSRichard Henderson 38401ca74648SRichard Henderson switch (a->c) { 3841ebe9383cSRichard Henderson case 0: /* simple */ 3842eaa3783bSRichard Henderson tcg_gen_andi_reg(t, t, 0x4000000); 3843ebe9383cSRichard Henderson ctx->null_cond = cond_make_0(TCG_COND_NE, t); 3844ebe9383cSRichard Henderson goto done; 3845ebe9383cSRichard Henderson case 2: /* rej */ 3846ebe9383cSRichard Henderson inv = true; 3847ebe9383cSRichard Henderson /* fallthru */ 3848ebe9383cSRichard Henderson case 1: /* acc */ 3849ebe9383cSRichard Henderson mask = 0x43ff800; 3850ebe9383cSRichard Henderson break; 3851ebe9383cSRichard Henderson case 6: /* rej8 */ 3852ebe9383cSRichard Henderson inv = true; 3853ebe9383cSRichard Henderson /* fallthru */ 3854ebe9383cSRichard Henderson case 5: /* acc8 */ 3855ebe9383cSRichard Henderson mask = 0x43f8000; 3856ebe9383cSRichard Henderson break; 3857ebe9383cSRichard Henderson case 9: /* acc6 */ 3858ebe9383cSRichard Henderson mask = 0x43e0000; 3859ebe9383cSRichard Henderson break; 3860ebe9383cSRichard Henderson case 13: /* acc4 */ 3861ebe9383cSRichard Henderson mask = 0x4380000; 3862ebe9383cSRichard Henderson break; 3863ebe9383cSRichard Henderson case 17: /* acc2 */ 3864ebe9383cSRichard Henderson mask = 0x4200000; 3865ebe9383cSRichard Henderson break; 3866ebe9383cSRichard Henderson default: 38671ca74648SRichard Henderson gen_illegal(ctx); 38681ca74648SRichard Henderson return true; 3869ebe9383cSRichard Henderson } 3870ebe9383cSRichard Henderson if (inv) { 3871eaa3783bSRichard Henderson TCGv_reg c = load_const(ctx, mask); 3872eaa3783bSRichard Henderson tcg_gen_or_reg(t, t, c); 3873ebe9383cSRichard Henderson ctx->null_cond = cond_make(TCG_COND_EQ, t, c); 3874ebe9383cSRichard Henderson } else { 3875eaa3783bSRichard Henderson tcg_gen_andi_reg(t, t, mask); 3876ebe9383cSRichard Henderson ctx->null_cond = cond_make_0(TCG_COND_EQ, t); 3877ebe9383cSRichard Henderson } 38781ca74648SRichard Henderson } else { 38791ca74648SRichard Henderson unsigned cbit = (a->y ^ 1) - 1; 38801ca74648SRichard Henderson 38811ca74648SRichard Henderson tcg_gen_extract_reg(t, t, 21 - cbit, 1); 38821ca74648SRichard Henderson ctx->null_cond = cond_make_0(TCG_COND_NE, t); 38831ca74648SRichard Henderson tcg_temp_free(t); 38841ca74648SRichard Henderson } 38851ca74648SRichard Henderson 3886ebe9383cSRichard Henderson done: 388731234768SRichard Henderson return nullify_end(ctx); 3888ebe9383cSRichard Henderson } 3889ebe9383cSRichard Henderson 38901ca74648SRichard Henderson /* 38911ca74648SRichard Henderson * Float class 2 38921ca74648SRichard Henderson */ 38931ca74648SRichard Henderson 38941ca74648SRichard Henderson static bool trans_fadd_f(DisasContext *ctx, arg_fclass3 *a) 3895ebe9383cSRichard Henderson { 38961ca74648SRichard Henderson return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fadd_s); 38971ca74648SRichard Henderson } 38981ca74648SRichard Henderson 38991ca74648SRichard Henderson static bool trans_fadd_d(DisasContext *ctx, arg_fclass3 *a) 39001ca74648SRichard Henderson { 39011ca74648SRichard Henderson return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fadd_d); 39021ca74648SRichard Henderson } 39031ca74648SRichard Henderson 39041ca74648SRichard Henderson static bool trans_fsub_f(DisasContext *ctx, arg_fclass3 *a) 39051ca74648SRichard Henderson { 39061ca74648SRichard Henderson return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fsub_s); 39071ca74648SRichard Henderson } 39081ca74648SRichard Henderson 39091ca74648SRichard Henderson static bool trans_fsub_d(DisasContext *ctx, arg_fclass3 *a) 39101ca74648SRichard Henderson { 39111ca74648SRichard Henderson return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fsub_d); 39121ca74648SRichard Henderson } 39131ca74648SRichard Henderson 39141ca74648SRichard Henderson static bool trans_fmpy_f(DisasContext *ctx, arg_fclass3 *a) 39151ca74648SRichard Henderson { 39161ca74648SRichard Henderson return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fmpy_s); 39171ca74648SRichard Henderson } 39181ca74648SRichard Henderson 39191ca74648SRichard Henderson static bool trans_fmpy_d(DisasContext *ctx, arg_fclass3 *a) 39201ca74648SRichard Henderson { 39211ca74648SRichard Henderson return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fmpy_d); 39221ca74648SRichard Henderson } 39231ca74648SRichard Henderson 39241ca74648SRichard Henderson static bool trans_fdiv_f(DisasContext *ctx, arg_fclass3 *a) 39251ca74648SRichard Henderson { 39261ca74648SRichard Henderson return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fdiv_s); 39271ca74648SRichard Henderson } 39281ca74648SRichard Henderson 39291ca74648SRichard Henderson static bool trans_fdiv_d(DisasContext *ctx, arg_fclass3 *a) 39301ca74648SRichard Henderson { 39311ca74648SRichard Henderson return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fdiv_d); 39321ca74648SRichard Henderson } 39331ca74648SRichard Henderson 39341ca74648SRichard Henderson static bool trans_xmpyu(DisasContext *ctx, arg_xmpyu *a) 39351ca74648SRichard Henderson { 39361ca74648SRichard Henderson TCGv_i64 x, y; 3937ebe9383cSRichard Henderson 3938ebe9383cSRichard Henderson nullify_over(ctx); 3939ebe9383cSRichard Henderson 39401ca74648SRichard Henderson x = load_frw0_i64(a->r1); 39411ca74648SRichard Henderson y = load_frw0_i64(a->r2); 39421ca74648SRichard Henderson tcg_gen_mul_i64(x, x, y); 39431ca74648SRichard Henderson save_frd(a->t, x); 39441ca74648SRichard Henderson tcg_temp_free_i64(x); 39451ca74648SRichard Henderson tcg_temp_free_i64(y); 3946ebe9383cSRichard Henderson 394731234768SRichard Henderson return nullify_end(ctx); 3948ebe9383cSRichard Henderson } 3949ebe9383cSRichard Henderson 3950ebe9383cSRichard Henderson /* Convert the fmpyadd single-precision register encodings to standard. */ 3951ebe9383cSRichard Henderson static inline int fmpyadd_s_reg(unsigned r) 3952ebe9383cSRichard Henderson { 3953ebe9383cSRichard Henderson return (r & 16) * 2 + 16 + (r & 15); 3954ebe9383cSRichard Henderson } 3955ebe9383cSRichard Henderson 3956b1e2af57SRichard Henderson static bool do_fmpyadd_s(DisasContext *ctx, arg_mpyadd *a, bool is_sub) 3957ebe9383cSRichard Henderson { 3958b1e2af57SRichard Henderson int tm = fmpyadd_s_reg(a->tm); 3959b1e2af57SRichard Henderson int ra = fmpyadd_s_reg(a->ra); 3960b1e2af57SRichard Henderson int ta = fmpyadd_s_reg(a->ta); 3961b1e2af57SRichard Henderson int rm2 = fmpyadd_s_reg(a->rm2); 3962b1e2af57SRichard Henderson int rm1 = fmpyadd_s_reg(a->rm1); 3963ebe9383cSRichard Henderson 3964ebe9383cSRichard Henderson nullify_over(ctx); 3965ebe9383cSRichard Henderson 3966ebe9383cSRichard Henderson do_fop_weww(ctx, tm, rm1, rm2, gen_helper_fmpy_s); 3967ebe9383cSRichard Henderson do_fop_weww(ctx, ta, ta, ra, 3968ebe9383cSRichard Henderson is_sub ? gen_helper_fsub_s : gen_helper_fadd_s); 3969ebe9383cSRichard Henderson 397031234768SRichard Henderson return nullify_end(ctx); 3971ebe9383cSRichard Henderson } 3972ebe9383cSRichard Henderson 3973b1e2af57SRichard Henderson static bool trans_fmpyadd_f(DisasContext *ctx, arg_mpyadd *a) 3974b1e2af57SRichard Henderson { 3975b1e2af57SRichard Henderson return do_fmpyadd_s(ctx, a, false); 3976b1e2af57SRichard Henderson } 3977b1e2af57SRichard Henderson 3978b1e2af57SRichard Henderson static bool trans_fmpysub_f(DisasContext *ctx, arg_mpyadd *a) 3979b1e2af57SRichard Henderson { 3980b1e2af57SRichard Henderson return do_fmpyadd_s(ctx, a, true); 3981b1e2af57SRichard Henderson } 3982b1e2af57SRichard Henderson 3983b1e2af57SRichard Henderson static bool do_fmpyadd_d(DisasContext *ctx, arg_mpyadd *a, bool is_sub) 3984b1e2af57SRichard Henderson { 3985b1e2af57SRichard Henderson nullify_over(ctx); 3986b1e2af57SRichard Henderson 3987b1e2af57SRichard Henderson do_fop_dedd(ctx, a->tm, a->rm1, a->rm2, gen_helper_fmpy_d); 3988b1e2af57SRichard Henderson do_fop_dedd(ctx, a->ta, a->ta, a->ra, 3989b1e2af57SRichard Henderson is_sub ? gen_helper_fsub_d : gen_helper_fadd_d); 3990b1e2af57SRichard Henderson 3991b1e2af57SRichard Henderson return nullify_end(ctx); 3992b1e2af57SRichard Henderson } 3993b1e2af57SRichard Henderson 3994b1e2af57SRichard Henderson static bool trans_fmpyadd_d(DisasContext *ctx, arg_mpyadd *a) 3995b1e2af57SRichard Henderson { 3996b1e2af57SRichard Henderson return do_fmpyadd_d(ctx, a, false); 3997b1e2af57SRichard Henderson } 3998b1e2af57SRichard Henderson 3999b1e2af57SRichard Henderson static bool trans_fmpysub_d(DisasContext *ctx, arg_mpyadd *a) 4000b1e2af57SRichard Henderson { 4001b1e2af57SRichard Henderson return do_fmpyadd_d(ctx, a, true); 4002b1e2af57SRichard Henderson } 4003b1e2af57SRichard Henderson 4004c3bad4f8SRichard Henderson static bool trans_fmpyfadd_f(DisasContext *ctx, arg_fmpyfadd_f *a) 4005ebe9383cSRichard Henderson { 4006c3bad4f8SRichard Henderson TCGv_i32 x, y, z; 4007ebe9383cSRichard Henderson 4008ebe9383cSRichard Henderson nullify_over(ctx); 4009c3bad4f8SRichard Henderson x = load_frw0_i32(a->rm1); 4010c3bad4f8SRichard Henderson y = load_frw0_i32(a->rm2); 4011c3bad4f8SRichard Henderson z = load_frw0_i32(a->ra3); 4012ebe9383cSRichard Henderson 4013c3bad4f8SRichard Henderson if (a->neg) { 4014c3bad4f8SRichard Henderson gen_helper_fmpynfadd_s(x, cpu_env, x, y, z); 4015ebe9383cSRichard Henderson } else { 4016c3bad4f8SRichard Henderson gen_helper_fmpyfadd_s(x, cpu_env, x, y, z); 4017ebe9383cSRichard Henderson } 4018ebe9383cSRichard Henderson 4019c3bad4f8SRichard Henderson tcg_temp_free_i32(y); 4020c3bad4f8SRichard Henderson tcg_temp_free_i32(z); 4021c3bad4f8SRichard Henderson save_frw_i32(a->t, x); 4022c3bad4f8SRichard Henderson tcg_temp_free_i32(x); 402331234768SRichard Henderson return nullify_end(ctx); 4024ebe9383cSRichard Henderson } 4025ebe9383cSRichard Henderson 4026c3bad4f8SRichard Henderson static bool trans_fmpyfadd_d(DisasContext *ctx, arg_fmpyfadd_d *a) 4027ebe9383cSRichard Henderson { 4028c3bad4f8SRichard Henderson TCGv_i64 x, y, z; 4029ebe9383cSRichard Henderson 4030ebe9383cSRichard Henderson nullify_over(ctx); 4031c3bad4f8SRichard Henderson x = load_frd0(a->rm1); 4032c3bad4f8SRichard Henderson y = load_frd0(a->rm2); 4033c3bad4f8SRichard Henderson z = load_frd0(a->ra3); 4034ebe9383cSRichard Henderson 4035c3bad4f8SRichard Henderson if (a->neg) { 4036c3bad4f8SRichard Henderson gen_helper_fmpynfadd_d(x, cpu_env, x, y, z); 4037ebe9383cSRichard Henderson } else { 4038c3bad4f8SRichard Henderson gen_helper_fmpyfadd_d(x, cpu_env, x, y, z); 4039ebe9383cSRichard Henderson } 4040ebe9383cSRichard Henderson 4041c3bad4f8SRichard Henderson tcg_temp_free_i64(y); 4042c3bad4f8SRichard Henderson tcg_temp_free_i64(z); 4043c3bad4f8SRichard Henderson save_frd(a->t, x); 4044c3bad4f8SRichard Henderson tcg_temp_free_i64(x); 404531234768SRichard Henderson return nullify_end(ctx); 4046ebe9383cSRichard Henderson } 4047ebe9383cSRichard Henderson 4048b542683dSEmilio G. Cota static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 404961766fe9SRichard Henderson { 405051b061fbSRichard Henderson DisasContext *ctx = container_of(dcbase, DisasContext, base); 4051f764718dSRichard Henderson int bound; 405261766fe9SRichard Henderson 405351b061fbSRichard Henderson ctx->cs = cs; 4054494737b7SRichard Henderson ctx->tb_flags = ctx->base.tb->flags; 40553d68ee7bSRichard Henderson 40563d68ee7bSRichard Henderson #ifdef CONFIG_USER_ONLY 40573d68ee7bSRichard Henderson ctx->privilege = MMU_USER_IDX; 40583d68ee7bSRichard Henderson ctx->mmu_idx = MMU_USER_IDX; 4059ebd0e151SRichard Henderson ctx->iaoq_f = ctx->base.pc_first | MMU_USER_IDX; 4060ebd0e151SRichard Henderson ctx->iaoq_b = ctx->base.tb->cs_base | MMU_USER_IDX; 4061c301f34eSRichard Henderson #else 4062494737b7SRichard Henderson ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; 4063494737b7SRichard Henderson ctx->mmu_idx = (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX); 40643d68ee7bSRichard Henderson 4065c301f34eSRichard Henderson /* Recover the IAOQ values from the GVA + PRIV. */ 4066c301f34eSRichard Henderson uint64_t cs_base = ctx->base.tb->cs_base; 4067c301f34eSRichard Henderson uint64_t iasq_f = cs_base & ~0xffffffffull; 4068c301f34eSRichard Henderson int32_t diff = cs_base; 4069c301f34eSRichard Henderson 4070c301f34eSRichard Henderson ctx->iaoq_f = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; 4071c301f34eSRichard Henderson ctx->iaoq_b = (diff ? ctx->iaoq_f + diff : -1); 4072c301f34eSRichard Henderson #endif 407351b061fbSRichard Henderson ctx->iaoq_n = -1; 4074f764718dSRichard Henderson ctx->iaoq_n_var = NULL; 407561766fe9SRichard Henderson 40763d68ee7bSRichard Henderson /* Bound the number of instructions by those left on the page. */ 40773d68ee7bSRichard Henderson bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; 4078b542683dSEmilio G. Cota ctx->base.max_insns = MIN(ctx->base.max_insns, bound); 40793d68ee7bSRichard Henderson 408086f8d05fSRichard Henderson ctx->ntempr = 0; 408186f8d05fSRichard Henderson ctx->ntempl = 0; 408286f8d05fSRichard Henderson memset(ctx->tempr, 0, sizeof(ctx->tempr)); 408386f8d05fSRichard Henderson memset(ctx->templ, 0, sizeof(ctx->templ)); 408461766fe9SRichard Henderson } 408561766fe9SRichard Henderson 408651b061fbSRichard Henderson static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) 408751b061fbSRichard Henderson { 408851b061fbSRichard Henderson DisasContext *ctx = container_of(dcbase, DisasContext, base); 408961766fe9SRichard Henderson 40903d68ee7bSRichard Henderson /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. */ 409151b061fbSRichard Henderson ctx->null_cond = cond_make_f(); 409251b061fbSRichard Henderson ctx->psw_n_nonzero = false; 4093494737b7SRichard Henderson if (ctx->tb_flags & PSW_N) { 409451b061fbSRichard Henderson ctx->null_cond.c = TCG_COND_ALWAYS; 409551b061fbSRichard Henderson ctx->psw_n_nonzero = true; 4096129e9cc3SRichard Henderson } 409751b061fbSRichard Henderson ctx->null_lab = NULL; 409861766fe9SRichard Henderson } 409961766fe9SRichard Henderson 410051b061fbSRichard Henderson static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 410151b061fbSRichard Henderson { 410251b061fbSRichard Henderson DisasContext *ctx = container_of(dcbase, DisasContext, base); 410351b061fbSRichard Henderson 410451b061fbSRichard Henderson tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b); 410551b061fbSRichard Henderson } 410651b061fbSRichard Henderson 410751b061fbSRichard Henderson static bool hppa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 410851b061fbSRichard Henderson const CPUBreakpoint *bp) 410951b061fbSRichard Henderson { 411051b061fbSRichard Henderson DisasContext *ctx = container_of(dcbase, DisasContext, base); 411151b061fbSRichard Henderson 411231234768SRichard Henderson gen_excp(ctx, EXCP_DEBUG); 4113c301f34eSRichard Henderson ctx->base.pc_next += 4; 411451b061fbSRichard Henderson return true; 411551b061fbSRichard Henderson } 411651b061fbSRichard Henderson 411751b061fbSRichard Henderson static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 411851b061fbSRichard Henderson { 411951b061fbSRichard Henderson DisasContext *ctx = container_of(dcbase, DisasContext, base); 412051b061fbSRichard Henderson CPUHPPAState *env = cs->env_ptr; 412151b061fbSRichard Henderson DisasJumpType ret; 412251b061fbSRichard Henderson int i, n; 412351b061fbSRichard Henderson 412451b061fbSRichard Henderson /* Execute one insn. */ 4125ba1d0b44SRichard Henderson #ifdef CONFIG_USER_ONLY 4126c301f34eSRichard Henderson if (ctx->base.pc_next < TARGET_PAGE_SIZE) { 412731234768SRichard Henderson do_page_zero(ctx); 412831234768SRichard Henderson ret = ctx->base.is_jmp; 4129869051eaSRichard Henderson assert(ret != DISAS_NEXT); 4130ba1d0b44SRichard Henderson } else 4131ba1d0b44SRichard Henderson #endif 4132ba1d0b44SRichard Henderson { 413361766fe9SRichard Henderson /* Always fetch the insn, even if nullified, so that we check 413461766fe9SRichard Henderson the page permissions for execute. */ 4135c301f34eSRichard Henderson uint32_t insn = cpu_ldl_code(env, ctx->base.pc_next); 413661766fe9SRichard Henderson 413761766fe9SRichard Henderson /* Set up the IA queue for the next insn. 413861766fe9SRichard Henderson This will be overwritten by a branch. */ 413951b061fbSRichard Henderson if (ctx->iaoq_b == -1) { 414051b061fbSRichard Henderson ctx->iaoq_n = -1; 414151b061fbSRichard Henderson ctx->iaoq_n_var = get_temp(ctx); 4142eaa3783bSRichard Henderson tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); 414361766fe9SRichard Henderson } else { 414451b061fbSRichard Henderson ctx->iaoq_n = ctx->iaoq_b + 4; 4145f764718dSRichard Henderson ctx->iaoq_n_var = NULL; 414661766fe9SRichard Henderson } 414761766fe9SRichard Henderson 414851b061fbSRichard Henderson if (unlikely(ctx->null_cond.c == TCG_COND_ALWAYS)) { 414951b061fbSRichard Henderson ctx->null_cond.c = TCG_COND_NEVER; 4150869051eaSRichard Henderson ret = DISAS_NEXT; 4151129e9cc3SRichard Henderson } else { 41521a19da0dSRichard Henderson ctx->insn = insn; 415331274b46SRichard Henderson if (!decode(ctx, insn)) { 415431274b46SRichard Henderson gen_illegal(ctx); 415531274b46SRichard Henderson } 415631234768SRichard Henderson ret = ctx->base.is_jmp; 415751b061fbSRichard Henderson assert(ctx->null_lab == NULL); 4158129e9cc3SRichard Henderson } 415961766fe9SRichard Henderson } 416061766fe9SRichard Henderson 416151b061fbSRichard Henderson /* Free any temporaries allocated. */ 416286f8d05fSRichard Henderson for (i = 0, n = ctx->ntempr; i < n; ++i) { 416386f8d05fSRichard Henderson tcg_temp_free(ctx->tempr[i]); 416486f8d05fSRichard Henderson ctx->tempr[i] = NULL; 416561766fe9SRichard Henderson } 416686f8d05fSRichard Henderson for (i = 0, n = ctx->ntempl; i < n; ++i) { 416786f8d05fSRichard Henderson tcg_temp_free_tl(ctx->templ[i]); 416886f8d05fSRichard Henderson ctx->templ[i] = NULL; 416986f8d05fSRichard Henderson } 417086f8d05fSRichard Henderson ctx->ntempr = 0; 417186f8d05fSRichard Henderson ctx->ntempl = 0; 417261766fe9SRichard Henderson 41733d68ee7bSRichard Henderson /* Advance the insn queue. Note that this check also detects 41743d68ee7bSRichard Henderson a priority change within the instruction queue. */ 417551b061fbSRichard Henderson if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) { 4176c301f34eSRichard Henderson if (ctx->iaoq_b != -1 && ctx->iaoq_n != -1 4177c301f34eSRichard Henderson && use_goto_tb(ctx, ctx->iaoq_b) 4178c301f34eSRichard Henderson && (ctx->null_cond.c == TCG_COND_NEVER 4179c301f34eSRichard Henderson || ctx->null_cond.c == TCG_COND_ALWAYS)) { 418051b061fbSRichard Henderson nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); 418151b061fbSRichard Henderson gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); 418231234768SRichard Henderson ctx->base.is_jmp = ret = DISAS_NORETURN; 4183129e9cc3SRichard Henderson } else { 418431234768SRichard Henderson ctx->base.is_jmp = ret = DISAS_IAQ_N_STALE; 418561766fe9SRichard Henderson } 4186129e9cc3SRichard Henderson } 418751b061fbSRichard Henderson ctx->iaoq_f = ctx->iaoq_b; 418851b061fbSRichard Henderson ctx->iaoq_b = ctx->iaoq_n; 4189c301f34eSRichard Henderson ctx->base.pc_next += 4; 419061766fe9SRichard Henderson 4191869051eaSRichard Henderson if (ret == DISAS_NORETURN || ret == DISAS_IAQ_N_UPDATED) { 419251b061fbSRichard Henderson return; 419361766fe9SRichard Henderson } 419451b061fbSRichard Henderson if (ctx->iaoq_f == -1) { 4195eaa3783bSRichard Henderson tcg_gen_mov_reg(cpu_iaoq_f, cpu_iaoq_b); 419651b061fbSRichard Henderson copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); 4197c301f34eSRichard Henderson #ifndef CONFIG_USER_ONLY 4198c301f34eSRichard Henderson tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); 4199c301f34eSRichard Henderson #endif 420051b061fbSRichard Henderson nullify_save(ctx); 420151b061fbSRichard Henderson ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; 420251b061fbSRichard Henderson } else if (ctx->iaoq_b == -1) { 4203eaa3783bSRichard Henderson tcg_gen_mov_reg(cpu_iaoq_b, ctx->iaoq_n_var); 420461766fe9SRichard Henderson } 420561766fe9SRichard Henderson } 420661766fe9SRichard Henderson 420751b061fbSRichard Henderson static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 420851b061fbSRichard Henderson { 420951b061fbSRichard Henderson DisasContext *ctx = container_of(dcbase, DisasContext, base); 4210e1b5a5edSRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 421151b061fbSRichard Henderson 4212e1b5a5edSRichard Henderson switch (is_jmp) { 4213869051eaSRichard Henderson case DISAS_NORETURN: 421461766fe9SRichard Henderson break; 421551b061fbSRichard Henderson case DISAS_TOO_MANY: 4216869051eaSRichard Henderson case DISAS_IAQ_N_STALE: 4217e1b5a5edSRichard Henderson case DISAS_IAQ_N_STALE_EXIT: 421851b061fbSRichard Henderson copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); 421951b061fbSRichard Henderson copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); 422051b061fbSRichard Henderson nullify_save(ctx); 422161766fe9SRichard Henderson /* FALLTHRU */ 4222869051eaSRichard Henderson case DISAS_IAQ_N_UPDATED: 422351b061fbSRichard Henderson if (ctx->base.singlestep_enabled) { 422461766fe9SRichard Henderson gen_excp_1(EXCP_DEBUG); 4225e1b5a5edSRichard Henderson } else if (is_jmp == DISAS_IAQ_N_STALE_EXIT) { 422607ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 422761766fe9SRichard Henderson } else { 42287f11636dSEmilio G. Cota tcg_gen_lookup_and_goto_ptr(); 422961766fe9SRichard Henderson } 423061766fe9SRichard Henderson break; 423161766fe9SRichard Henderson default: 423251b061fbSRichard Henderson g_assert_not_reached(); 423361766fe9SRichard Henderson } 423451b061fbSRichard Henderson } 423561766fe9SRichard Henderson 423651b061fbSRichard Henderson static void hppa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 423751b061fbSRichard Henderson { 4238c301f34eSRichard Henderson target_ulong pc = dcbase->pc_first; 423961766fe9SRichard Henderson 4240ba1d0b44SRichard Henderson #ifdef CONFIG_USER_ONLY 4241ba1d0b44SRichard Henderson switch (pc) { 42427ad439dfSRichard Henderson case 0x00: 424351b061fbSRichard Henderson qemu_log("IN:\n0x00000000: (null)\n"); 4244ba1d0b44SRichard Henderson return; 42457ad439dfSRichard Henderson case 0xb0: 424651b061fbSRichard Henderson qemu_log("IN:\n0x000000b0: light-weight-syscall\n"); 4247ba1d0b44SRichard Henderson return; 42487ad439dfSRichard Henderson case 0xe0: 424951b061fbSRichard Henderson qemu_log("IN:\n0x000000e0: set-thread-pointer-syscall\n"); 4250ba1d0b44SRichard Henderson return; 42517ad439dfSRichard Henderson case 0x100: 425251b061fbSRichard Henderson qemu_log("IN:\n0x00000100: syscall\n"); 4253ba1d0b44SRichard Henderson return; 42547ad439dfSRichard Henderson } 4255ba1d0b44SRichard Henderson #endif 4256ba1d0b44SRichard Henderson 4257ba1d0b44SRichard Henderson qemu_log("IN: %s\n", lookup_symbol(pc)); 4258eaa3783bSRichard Henderson log_target_disas(cs, pc, dcbase->tb->size); 425961766fe9SRichard Henderson } 426051b061fbSRichard Henderson 426151b061fbSRichard Henderson static const TranslatorOps hppa_tr_ops = { 426251b061fbSRichard Henderson .init_disas_context = hppa_tr_init_disas_context, 426351b061fbSRichard Henderson .tb_start = hppa_tr_tb_start, 426451b061fbSRichard Henderson .insn_start = hppa_tr_insn_start, 426551b061fbSRichard Henderson .breakpoint_check = hppa_tr_breakpoint_check, 426651b061fbSRichard Henderson .translate_insn = hppa_tr_translate_insn, 426751b061fbSRichard Henderson .tb_stop = hppa_tr_tb_stop, 426851b061fbSRichard Henderson .disas_log = hppa_tr_disas_log, 426951b061fbSRichard Henderson }; 427051b061fbSRichard Henderson 427151b061fbSRichard Henderson void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) 427251b061fbSRichard Henderson 427351b061fbSRichard Henderson { 427451b061fbSRichard Henderson DisasContext ctx; 427551b061fbSRichard Henderson translator_loop(&hppa_tr_ops, &ctx.base, cs, tb); 427661766fe9SRichard Henderson } 427761766fe9SRichard Henderson 427861766fe9SRichard Henderson void restore_state_to_opc(CPUHPPAState *env, TranslationBlock *tb, 427961766fe9SRichard Henderson target_ulong *data) 428061766fe9SRichard Henderson { 428161766fe9SRichard Henderson env->iaoq_f = data[0]; 428286f8d05fSRichard Henderson if (data[1] != (target_ureg)-1) { 428361766fe9SRichard Henderson env->iaoq_b = data[1]; 428461766fe9SRichard Henderson } 428561766fe9SRichard Henderson /* Since we were executing the instruction at IAOQ_F, and took some 428661766fe9SRichard Henderson sort of action that provoked the cpu_restore_state, we can infer 428761766fe9SRichard Henderson that the instruction was not nullified. */ 428861766fe9SRichard Henderson env->psw_n = 0; 428961766fe9SRichard Henderson } 4290