1 /* 2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef HEXAGON_MACROS_H 19 #define HEXAGON_MACROS_H 20 21 #include "cpu.h" 22 #include "hex_regs.h" 23 #include "reg_fields.h" 24 25 #define PCALIGN 4 26 #define PCALIGN_MASK (PCALIGN - 1) 27 28 #define GET_FIELD(FIELD, REGIN) \ 29 fEXTRACTU_BITS(REGIN, reg_field_info[FIELD].width, \ 30 reg_field_info[FIELD].offset) 31 32 #ifdef QEMU_GENERATE 33 #define GET_USR_FIELD(FIELD, DST) \ 34 tcg_gen_extract_tl(DST, hex_gpr[HEX_REG_USR], \ 35 reg_field_info[FIELD].offset, \ 36 reg_field_info[FIELD].width) 37 38 #define TYPE_INT(X) __builtin_types_compatible_p(typeof(X), int) 39 #define TYPE_TCGV(X) __builtin_types_compatible_p(typeof(X), TCGv) 40 #define TYPE_TCGV_I64(X) __builtin_types_compatible_p(typeof(X), TCGv_i64) 41 #else 42 #define GET_USR_FIELD(FIELD) \ 43 fEXTRACTU_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \ 44 reg_field_info[FIELD].offset) 45 46 #define SET_USR_FIELD(FIELD, VAL) \ 47 fINSERT_BITS(env->new_value[HEX_REG_USR], reg_field_info[FIELD].width, \ 48 reg_field_info[FIELD].offset, (VAL)) 49 #endif 50 51 #ifdef QEMU_GENERATE 52 /* 53 * Section 5.5 of the Hexagon V67 Programmer's Reference Manual 54 * 55 * Slot 1 store with slot 0 load 56 * A slot 1 store operation with a slot 0 load operation can appear in a packet. 57 * The packet attribute :mem_noshuf inhibits the instruction reordering that 58 * would otherwise be done by the assembler. For example: 59 * { 60 * memw(R5) = R2 // slot 1 store 61 * R3 = memh(R6) // slot 0 load 62 * }:mem_noshuf 63 * Unlike most packetized operations, these memory operations are not executed 64 * in parallel (Section 3.3.1). Instead, the store instruction in Slot 1 65 * effectively executes first, followed by the load instruction in Slot 0. If 66 * the addresses of the two operations are overlapping, the load will receive 67 * the newly stored data. This feature is supported in processor versions 68 * V65 or greater. 69 * 70 * 71 * For qemu, we look for a load in slot 0 when there is a store in slot 1 72 * in the same packet. When we see this, we call a helper that probes the 73 * load to make sure it doesn't fault. Then, we process the store ahead of 74 * the actual load. 75 76 */ 77 #define CHECK_NOSHUF(VA, SIZE) \ 78 do { \ 79 if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \ 80 probe_noshuf_load(VA, SIZE, ctx->mem_idx); \ 81 process_store(ctx, 1); \ 82 } \ 83 } while (0) 84 85 #define CHECK_NOSHUF_PRED(GET_EA, SIZE, PRED) \ 86 do { \ 87 TCGLabel *label = gen_new_label(); \ 88 tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, label); \ 89 GET_EA; \ 90 if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \ 91 probe_noshuf_load(EA, SIZE, ctx->mem_idx); \ 92 } \ 93 gen_set_label(label); \ 94 if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \ 95 process_store(ctx, 1); \ 96 } \ 97 } while (0) 98 99 #define MEM_LOAD1s(DST, VA) \ 100 do { \ 101 CHECK_NOSHUF(VA, 1); \ 102 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_SB); \ 103 } while (0) 104 #define MEM_LOAD1u(DST, VA) \ 105 do { \ 106 CHECK_NOSHUF(VA, 1); \ 107 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_UB); \ 108 } while (0) 109 #define MEM_LOAD2s(DST, VA) \ 110 do { \ 111 CHECK_NOSHUF(VA, 2); \ 112 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESW); \ 113 } while (0) 114 #define MEM_LOAD2u(DST, VA) \ 115 do { \ 116 CHECK_NOSHUF(VA, 2); \ 117 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUW); \ 118 } while (0) 119 #define MEM_LOAD4s(DST, VA) \ 120 do { \ 121 CHECK_NOSHUF(VA, 4); \ 122 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESL); \ 123 } while (0) 124 #define MEM_LOAD4u(DST, VA) \ 125 do { \ 126 CHECK_NOSHUF(VA, 4); \ 127 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUL); \ 128 } while (0) 129 #define MEM_LOAD8u(DST, VA) \ 130 do { \ 131 CHECK_NOSHUF(VA, 8); \ 132 tcg_gen_qemu_ld_i64(DST, VA, ctx->mem_idx, MO_TEUQ); \ 133 } while (0) 134 135 #define MEM_STORE1_FUNC(X) \ 136 __builtin_choose_expr(TYPE_INT(X), \ 137 gen_store1i, \ 138 __builtin_choose_expr(TYPE_TCGV(X), \ 139 gen_store1, (void)0)) 140 #define MEM_STORE1(VA, DATA, SLOT) \ 141 MEM_STORE1_FUNC(DATA)(cpu_env, VA, DATA, SLOT) 142 143 #define MEM_STORE2_FUNC(X) \ 144 __builtin_choose_expr(TYPE_INT(X), \ 145 gen_store2i, \ 146 __builtin_choose_expr(TYPE_TCGV(X), \ 147 gen_store2, (void)0)) 148 #define MEM_STORE2(VA, DATA, SLOT) \ 149 MEM_STORE2_FUNC(DATA)(cpu_env, VA, DATA, SLOT) 150 151 #define MEM_STORE4_FUNC(X) \ 152 __builtin_choose_expr(TYPE_INT(X), \ 153 gen_store4i, \ 154 __builtin_choose_expr(TYPE_TCGV(X), \ 155 gen_store4, (void)0)) 156 #define MEM_STORE4(VA, DATA, SLOT) \ 157 MEM_STORE4_FUNC(DATA)(cpu_env, VA, DATA, SLOT) 158 159 #define MEM_STORE8_FUNC(X) \ 160 __builtin_choose_expr(TYPE_INT(X), \ 161 gen_store8i, \ 162 __builtin_choose_expr(TYPE_TCGV_I64(X), \ 163 gen_store8, (void)0)) 164 #define MEM_STORE8(VA, DATA, SLOT) \ 165 MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, SLOT) 166 #else 167 #define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, slot, VA)) 168 #define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, slot, VA)) 169 #define MEM_LOAD2s(VA) ((int16_t)mem_load2(env, slot, VA)) 170 #define MEM_LOAD2u(VA) ((uint16_t)mem_load2(env, slot, VA)) 171 #define MEM_LOAD4s(VA) ((int32_t)mem_load4(env, slot, VA)) 172 #define MEM_LOAD4u(VA) ((uint32_t)mem_load4(env, slot, VA)) 173 #define MEM_LOAD8s(VA) ((int64_t)mem_load8(env, slot, VA)) 174 #define MEM_LOAD8u(VA) ((uint64_t)mem_load8(env, slot, VA)) 175 176 #define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT) 177 #define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT) 178 #define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT) 179 #define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8, SLOT) 180 #endif 181 182 #ifdef QEMU_GENERATE 183 static inline void gen_cancel(uint32_t slot) 184 { 185 tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, 1 << slot); 186 } 187 188 #define CANCEL gen_cancel(slot); 189 #else 190 #define CANCEL do { } while (0) 191 #endif 192 193 #define LOAD_CANCEL(EA) do { CANCEL; } while (0) 194 195 #define STORE_CANCEL(EA) { env->slot_cancelled |= (1 << slot); } 196 197 #define fMAX(A, B) (((A) > (B)) ? (A) : (B)) 198 199 #define fMIN(A, B) (((A) < (B)) ? (A) : (B)) 200 201 #define fABS(A) (((A) < 0) ? (-(A)) : (A)) 202 #define fINSERT_BITS(REG, WIDTH, OFFSET, INVAL) \ 203 REG = ((WIDTH) ? deposit64(REG, (OFFSET), (WIDTH), (INVAL)) : REG) 204 #define fEXTRACTU_BITS(INREG, WIDTH, OFFSET) \ 205 ((WIDTH) ? extract64((INREG), (OFFSET), (WIDTH)) : 0LL) 206 #define fEXTRACTU_BIDIR(INREG, WIDTH, OFFSET) \ 207 (fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8))) 208 #define fEXTRACTU_RANGE(INREG, HIBIT, LOWBIT) \ 209 (((HIBIT) - (LOWBIT) + 1) ? \ 210 extract64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1)) : \ 211 0LL) 212 #define fINSERT_RANGE(INREG, HIBIT, LOWBIT, INVAL) \ 213 do { \ 214 int width = ((HIBIT) - (LOWBIT) + 1); \ 215 INREG = (width >= 0 ? \ 216 deposit64((INREG), (LOWBIT), width, (INVAL)) : \ 217 INREG); \ 218 } while (0) 219 220 #define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00) 221 222 #ifdef QEMU_GENERATE 223 #define fLSBOLD(VAL) tcg_gen_andi_tl(LSB, (VAL), 1) 224 #else 225 #define fLSBOLD(VAL) ((VAL) & 1) 226 #endif 227 228 #ifdef QEMU_GENERATE 229 #define fLSBNEW(PVAL) tcg_gen_andi_tl(LSB, (PVAL), 1) 230 #else 231 #define fLSBNEW(PVAL) ((PVAL) & 1) 232 #endif 233 234 #ifdef QEMU_GENERATE 235 #define fLSBOLDNOT(VAL) \ 236 do { \ 237 tcg_gen_andi_tl(LSB, (VAL), 1); \ 238 tcg_gen_xori_tl(LSB, LSB, 1); \ 239 } while (0) 240 #define fLSBNEWNOT(PNUM) \ 241 do { \ 242 tcg_gen_andi_tl(LSB, (PNUM), 1); \ 243 tcg_gen_xori_tl(LSB, LSB, 1); \ 244 } while (0) 245 #else 246 #define fLSBNEWNOT(PNUM) (!fLSBNEW(PNUM)) 247 #define fLSBOLDNOT(VAL) (!fLSBOLD(VAL)) 248 #define fLSBNEW0NOT (!fLSBNEW0) 249 #define fLSBNEW1NOT (!fLSBNEW1) 250 #endif 251 252 #define fNEWREG(VAL) ((int32_t)(VAL)) 253 254 #define fNEWREG_ST(VAL) (VAL) 255 256 #define fVSATUVALN(N, VAL) \ 257 ({ \ 258 (((int64_t)(VAL)) < 0) ? 0 : ((1LL << (N)) - 1); \ 259 }) 260 #define fSATUVALN(N, VAL) \ 261 ({ \ 262 fSET_OVERFLOW(); \ 263 ((VAL) < 0) ? 0 : ((1LL << (N)) - 1); \ 264 }) 265 #define fSATVALN(N, VAL) \ 266 ({ \ 267 fSET_OVERFLOW(); \ 268 ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \ 269 }) 270 #define fVSATVALN(N, VAL) \ 271 ({ \ 272 ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \ 273 }) 274 #define fZXTN(N, M, VAL) (((N) != 0) ? extract64((VAL), 0, (N)) : 0LL) 275 #define fSXTN(N, M, VAL) (((N) != 0) ? sextract64((VAL), 0, (N)) : 0LL) 276 #define fSATN(N, VAL) \ 277 ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATVALN(N, VAL)) 278 #define fVSATN(N, VAL) \ 279 ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATVALN(N, VAL)) 280 #define fADDSAT64(DST, A, B) \ 281 do { \ 282 uint64_t __a = fCAST8u(A); \ 283 uint64_t __b = fCAST8u(B); \ 284 uint64_t __sum = __a + __b; \ 285 uint64_t __xor = __a ^ __b; \ 286 const uint64_t __mask = 0x8000000000000000ULL; \ 287 if (__xor & __mask) { \ 288 DST = __sum; \ 289 } \ 290 else if ((__a ^ __sum) & __mask) { \ 291 if (__sum & __mask) { \ 292 DST = 0x7FFFFFFFFFFFFFFFLL; \ 293 fSET_OVERFLOW(); \ 294 } else { \ 295 DST = 0x8000000000000000LL; \ 296 fSET_OVERFLOW(); \ 297 } \ 298 } else { \ 299 DST = __sum; \ 300 } \ 301 } while (0) 302 #define fVSATUN(N, VAL) \ 303 ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATUVALN(N, VAL)) 304 #define fSATUN(N, VAL) \ 305 ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATUVALN(N, VAL)) 306 #define fSATH(VAL) (fSATN(16, VAL)) 307 #define fSATUH(VAL) (fSATUN(16, VAL)) 308 #define fVSATH(VAL) (fVSATN(16, VAL)) 309 #define fVSATUH(VAL) (fVSATUN(16, VAL)) 310 #define fSATUB(VAL) (fSATUN(8, VAL)) 311 #define fSATB(VAL) (fSATN(8, VAL)) 312 #define fVSATUB(VAL) (fVSATUN(8, VAL)) 313 #define fVSATB(VAL) (fVSATN(8, VAL)) 314 #define fIMMEXT(IMM) (IMM = IMM) 315 #define fMUST_IMMEXT(IMM) fIMMEXT(IMM) 316 317 #define fPCALIGN(IMM) IMM = (IMM & ~PCALIGN_MASK) 318 319 #ifdef QEMU_GENERATE 320 static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift) 321 { 322 /* 323 * Section 2.2.4 of the Hexagon V67 Programmer's Reference Manual 324 * 325 * The "I" value from a modifier register is divided into two pieces 326 * LSB bits 23:17 327 * MSB bits 31:28 328 * The value is signed 329 * 330 * At the end we shift the result according to the shift argument 331 */ 332 TCGv msb = tcg_temp_new(); 333 TCGv lsb = tcg_temp_new(); 334 335 tcg_gen_extract_tl(lsb, val, 17, 7); 336 tcg_gen_sari_tl(msb, val, 21); 337 tcg_gen_deposit_tl(result, msb, lsb, 0, 7); 338 339 tcg_gen_shli_tl(result, result, shift); 340 return result; 341 } 342 #endif 343 344 #define fREAD_LR() (env->gpr[HEX_REG_LR]) 345 346 #define fREAD_SP() (env->gpr[HEX_REG_SP]) 347 #define fREAD_LC0 (env->gpr[HEX_REG_LC0]) 348 #define fREAD_LC1 (env->gpr[HEX_REG_LC1]) 349 #define fREAD_SA0 (env->gpr[HEX_REG_SA0]) 350 #define fREAD_SA1 (env->gpr[HEX_REG_SA1]) 351 #define fREAD_FP() (env->gpr[HEX_REG_FP]) 352 #ifdef FIXME 353 /* Figure out how to get insn->extension_valid to helper */ 354 #define fREAD_GP() \ 355 (insn->extension_valid ? 0 : env->gpr[HEX_REG_GP]) 356 #else 357 #define fREAD_GP() (env->gpr[HEX_REG_GP]) 358 #endif 359 #define fREAD_PC() (PC) 360 361 #define fREAD_P0() (env->pred[0]) 362 363 #define fCHECK_PCALIGN(A) 364 365 #define fWRITE_NPC(A) write_new_pc(env, pkt_has_multi_cof != 0, A) 366 367 #define fBRANCH(LOC, TYPE) fWRITE_NPC(LOC) 368 #define fJUMPR(REGNO, TARGET, TYPE) fBRANCH(TARGET, COF_TYPE_JUMPR) 369 #define fHINTJR(TARGET) { /* Not modelled in qemu */} 370 371 #define fSET_OVERFLOW() SET_USR_FIELD(USR_OVF, 1) 372 #define fSET_LPCFG(VAL) SET_USR_FIELD(USR_LPCFG, (VAL)) 373 #define fGET_LPCFG (GET_USR_FIELD(USR_LPCFG)) 374 #define fPART1(WORK) if (part1) { WORK; return; } 375 #define fCAST4u(A) ((uint32_t)(A)) 376 #define fCAST4s(A) ((int32_t)(A)) 377 #define fCAST8u(A) ((uint64_t)(A)) 378 #define fCAST8s(A) ((int64_t)(A)) 379 #define fCAST2_2s(A) ((int16_t)(A)) 380 #define fCAST2_2u(A) ((uint16_t)(A)) 381 #define fCAST4_4s(A) ((int32_t)(A)) 382 #define fCAST4_4u(A) ((uint32_t)(A)) 383 #define fCAST4_8s(A) ((int64_t)((int32_t)(A))) 384 #define fCAST4_8u(A) ((uint64_t)((uint32_t)(A))) 385 #define fCAST8_8s(A) ((int64_t)(A)) 386 #define fCAST8_8u(A) ((uint64_t)(A)) 387 #define fCAST2_8s(A) ((int64_t)((int16_t)(A))) 388 #define fCAST2_8u(A) ((uint64_t)((uint16_t)(A))) 389 #define fZE8_16(A) ((int16_t)((uint8_t)(A))) 390 #define fSE8_16(A) ((int16_t)((int8_t)(A))) 391 #define fSE16_32(A) ((int32_t)((int16_t)(A))) 392 #define fZE16_32(A) ((uint32_t)((uint16_t)(A))) 393 #define fSE32_64(A) ((int64_t)((int32_t)(A))) 394 #define fZE32_64(A) ((uint64_t)((uint32_t)(A))) 395 #define fSE8_32(A) ((int32_t)((int8_t)(A))) 396 #define fZE8_32(A) ((int32_t)((uint8_t)(A))) 397 #define fMPY8UU(A, B) (int)(fZE8_16(A) * fZE8_16(B)) 398 #define fMPY8US(A, B) (int)(fZE8_16(A) * fSE8_16(B)) 399 #define fMPY8SU(A, B) (int)(fSE8_16(A) * fZE8_16(B)) 400 #define fMPY8SS(A, B) (int)((short)(A) * (short)(B)) 401 #define fMPY16SS(A, B) fSE32_64(fSE16_32(A) * fSE16_32(B)) 402 #define fMPY16UU(A, B) fZE32_64(fZE16_32(A) * fZE16_32(B)) 403 #define fMPY16SU(A, B) fSE32_64(fSE16_32(A) * fZE16_32(B)) 404 #define fMPY16US(A, B) fMPY16SU(B, A) 405 #define fMPY32SS(A, B) (fSE32_64(A) * fSE32_64(B)) 406 #define fMPY32UU(A, B) (fZE32_64(A) * fZE32_64(B)) 407 #define fMPY32SU(A, B) (fSE32_64(A) * fZE32_64(B)) 408 #define fMPY3216SS(A, B) (fSE32_64(A) * fSXTN(16, 64, B)) 409 #define fMPY3216SU(A, B) (fSE32_64(A) * fZXTN(16, 64, B)) 410 #define fROUND(A) (A + 0x8000) 411 #define fCLIP(DST, SRC, U) \ 412 do { \ 413 int32_t maxv = (1 << U) - 1; \ 414 int32_t minv = -(1 << U); \ 415 DST = fMIN(maxv, fMAX(SRC, minv)); \ 416 } while (0) 417 #define fCRND(A) ((((A) & 0x3) == 0x3) ? ((A) + 1) : ((A))) 418 #define fRNDN(A, N) ((((N) == 0) ? (A) : (((fSE32_64(A)) + (1 << ((N) - 1)))))) 419 #define fCRNDN(A, N) (conv_round(A, N)) 420 #define fADD128(A, B) (int128_add(A, B)) 421 #define fSUB128(A, B) (int128_sub(A, B)) 422 #define fSHIFTR128(A, B) (int128_rshift(A, B)) 423 #define fSHIFTL128(A, B) (int128_lshift(A, B)) 424 #define fAND128(A, B) (int128_and(A, B)) 425 #define fCAST8S_16S(A) (int128_exts64(A)) 426 #define fCAST16S_8S(A) (int128_getlo(A)) 427 428 #ifdef QEMU_GENERATE 429 #define fEA_RI(REG, IMM) tcg_gen_addi_tl(EA, REG, IMM) 430 #define fEA_RRs(REG, REG2, SCALE) \ 431 do { \ 432 TCGv tmp = tcg_temp_new(); \ 433 tcg_gen_shli_tl(tmp, REG2, SCALE); \ 434 tcg_gen_add_tl(EA, REG, tmp); \ 435 } while (0) 436 #define fEA_IRs(IMM, REG, SCALE) \ 437 do { \ 438 tcg_gen_shli_tl(EA, REG, SCALE); \ 439 tcg_gen_addi_tl(EA, EA, IMM); \ 440 } while (0) 441 #else 442 #define fEA_RI(REG, IMM) \ 443 do { \ 444 EA = REG + IMM; \ 445 } while (0) 446 #define fEA_RRs(REG, REG2, SCALE) \ 447 do { \ 448 EA = REG + (REG2 << SCALE); \ 449 } while (0) 450 #define fEA_IRs(IMM, REG, SCALE) \ 451 do { \ 452 EA = IMM + (REG << SCALE); \ 453 } while (0) 454 #endif 455 456 #ifdef QEMU_GENERATE 457 #define fEA_IMM(IMM) tcg_gen_movi_tl(EA, IMM) 458 #define fEA_REG(REG) tcg_gen_mov_tl(EA, REG) 459 #define fEA_BREVR(REG) gen_helper_fbrev(EA, REG) 460 #define fPM_I(REG, IMM) tcg_gen_addi_tl(REG, REG, IMM) 461 #define fPM_M(REG, MVAL) tcg_gen_add_tl(REG, REG, MVAL) 462 #define fPM_CIRI(REG, IMM, MVAL) \ 463 do { \ 464 TCGv tcgv_siV = tcg_constant_tl(siV); \ 465 gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, \ 466 hex_gpr[HEX_REG_CS0 + MuN]); \ 467 } while (0) 468 #else 469 #define fEA_IMM(IMM) do { EA = (IMM); } while (0) 470 #define fEA_REG(REG) do { EA = (REG); } while (0) 471 #define fEA_GPI(IMM) do { EA = (fREAD_GP() + (IMM)); } while (0) 472 #define fPM_I(REG, IMM) do { REG = REG + (IMM); } while (0) 473 #define fPM_M(REG, MVAL) do { REG = REG + (MVAL); } while (0) 474 #endif 475 #define fSCALE(N, A) (((int64_t)(A)) << N) 476 #define fVSATW(A) fVSATN(32, ((long long)A)) 477 #define fSATW(A) fSATN(32, ((long long)A)) 478 #define fVSAT(A) fVSATN(32, (A)) 479 #define fSAT(A) fSATN(32, (A)) 480 #define fSAT_ORIG_SHL(A, ORIG_REG) \ 481 ((((int32_t)((fSAT(A)) ^ ((int32_t)(ORIG_REG)))) < 0) \ 482 ? fSATVALN(32, ((int32_t)(ORIG_REG))) \ 483 : ((((ORIG_REG) > 0) && ((A) == 0)) ? fSATVALN(32, (ORIG_REG)) \ 484 : fSAT(A))) 485 #define fPASS(A) A 486 #define fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE) \ 487 (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) >> ((-(SHAMT)) - 1)) >> 1) \ 488 : (fCAST##REGSTYPE(SRC) << (SHAMT))) 489 #define fBIDIR_ASHIFTL(SRC, SHAMT, REGSTYPE) \ 490 fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##s) 491 #define fBIDIR_LSHIFTL(SRC, SHAMT, REGSTYPE) \ 492 fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##u) 493 #define fBIDIR_ASHIFTL_SAT(SRC, SHAMT, REGSTYPE) \ 494 (((SHAMT) < 0) ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT)) - 1)) >> 1) \ 495 : fSAT_ORIG_SHL(fCAST##REGSTYPE##s(SRC) << (SHAMT), (SRC))) 496 #define fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE) \ 497 (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT)) - 1)) << 1) \ 498 : (fCAST##REGSTYPE(SRC) >> (SHAMT))) 499 #define fBIDIR_ASHIFTR(SRC, SHAMT, REGSTYPE) \ 500 fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##s) 501 #define fBIDIR_LSHIFTR(SRC, SHAMT, REGSTYPE) \ 502 fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##u) 503 #define fBIDIR_ASHIFTR_SAT(SRC, SHAMT, REGSTYPE) \ 504 (((SHAMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) \ 505 << ((-(SHAMT)) - 1)) << 1, (SRC)) \ 506 : (fCAST##REGSTYPE##s(SRC) >> (SHAMT))) 507 #define fASHIFTR(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) >> (SHAMT)) 508 #define fLSHIFTR(SRC, SHAMT, REGSTYPE) \ 509 (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##u(SRC) >> (SHAMT))) 510 #define fROTL(SRC, SHAMT, REGSTYPE) \ 511 (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \ 512 ((fCAST##REGSTYPE##u(SRC) >> \ 513 ((sizeof(SRC) * 8) - (SHAMT)))))) 514 #define fROTR(SRC, SHAMT, REGSTYPE) \ 515 (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) >> (SHAMT)) | \ 516 ((fCAST##REGSTYPE##u(SRC) << \ 517 ((sizeof(SRC) * 8) - (SHAMT)))))) 518 #define fASHIFTL(SRC, SHAMT, REGSTYPE) \ 519 (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##s(SRC) << (SHAMT))) 520 521 #ifdef QEMU_GENERATE 522 #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA) 523 #else 524 #define fLOAD(NUM, SIZE, SIGN, EA, DST) \ 525 DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE##SIGN(EA) 526 #endif 527 528 #define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE) 529 530 #define fGET_FRAMEKEY() (env->gpr[HEX_REG_FRAMEKEY]) 531 #define fFRAME_SCRAMBLE(VAL) ((VAL) ^ (fCAST8u(fGET_FRAMEKEY()) << 32)) 532 #define fFRAME_UNSCRAMBLE(VAL) fFRAME_SCRAMBLE(VAL) 533 534 #ifdef CONFIG_USER_ONLY 535 #define fFRAMECHECK(ADDR, EA) do { } while (0) /* Not modelled in linux-user */ 536 #else 537 /* System mode not implemented yet */ 538 #define fFRAMECHECK(ADDR, EA) g_assert_not_reached(); 539 #endif 540 541 #ifdef QEMU_GENERATE 542 #define fLOAD_LOCKED(NUM, SIZE, SIGN, EA, DST) \ 543 gen_load_locked##SIZE##SIGN(DST, EA, ctx->mem_idx); 544 #endif 545 546 #ifdef QEMU_GENERATE 547 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, insn->slot) 548 #else 549 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, slot) 550 #endif 551 552 #ifdef QEMU_GENERATE 553 #define fSTORE_LOCKED(NUM, SIZE, EA, SRC, PRED) \ 554 gen_store_conditional##SIZE(ctx, PRED, EA, SRC); 555 #endif 556 557 #ifdef QEMU_GENERATE 558 #define GETBYTE_FUNC(X) \ 559 __builtin_choose_expr(TYPE_TCGV(X), \ 560 gen_get_byte, \ 561 __builtin_choose_expr(TYPE_TCGV_I64(X), \ 562 gen_get_byte_i64, (void)0)) 563 #define fGETBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, true) 564 #define fGETUBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, false) 565 #else 566 #define fGETBYTE(N, SRC) ((int8_t)((SRC >> ((N) * 8)) & 0xff)) 567 #define fGETUBYTE(N, SRC) ((uint8_t)((SRC >> ((N) * 8)) & 0xff)) 568 #endif 569 570 #define fSETBYTE(N, DST, VAL) \ 571 do { \ 572 DST = (DST & ~(0x0ffLL << ((N) * 8))) | \ 573 (((uint64_t)((VAL) & 0x0ffLL)) << ((N) * 8)); \ 574 } while (0) 575 576 #ifdef QEMU_GENERATE 577 #define fGETHALF(N, SRC) gen_get_half(HALF, N, SRC, true) 578 #define fGETUHALF(N, SRC) gen_get_half(HALF, N, SRC, false) 579 #else 580 #define fGETHALF(N, SRC) ((int16_t)((SRC >> ((N) * 16)) & 0xffff)) 581 #define fGETUHALF(N, SRC) ((uint16_t)((SRC >> ((N) * 16)) & 0xffff)) 582 #endif 583 #define fSETHALF(N, DST, VAL) \ 584 do { \ 585 DST = (DST & ~(0x0ffffLL << ((N) * 16))) | \ 586 (((uint64_t)((VAL) & 0x0ffff)) << ((N) * 16)); \ 587 } while (0) 588 #define fSETHALFw fSETHALF 589 #define fSETHALFd fSETHALF 590 591 #define fGETWORD(N, SRC) \ 592 ((int64_t)((int32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL))) 593 #define fGETUWORD(N, SRC) \ 594 ((uint64_t)((uint32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL))) 595 596 #define fSETWORD(N, DST, VAL) \ 597 do { \ 598 DST = (DST & ~(0x0ffffffffLL << ((N) * 32))) | \ 599 (((VAL) & 0x0ffffffffLL) << ((N) * 32)); \ 600 } while (0) 601 602 #define fSETBIT(N, DST, VAL) \ 603 do { \ 604 DST = (DST & ~(1ULL << (N))) | (((uint64_t)(VAL)) << (N)); \ 605 } while (0) 606 607 #define fGETBIT(N, SRC) (((SRC) >> N) & 1) 608 #define fSETBITS(HI, LO, DST, VAL) \ 609 do { \ 610 int j; \ 611 for (j = LO; j <= HI; j++) { \ 612 fSETBIT(j, DST, VAL); \ 613 } \ 614 } while (0) 615 #define fCOUNTONES_2(VAL) ctpop16(VAL) 616 #define fCOUNTONES_4(VAL) ctpop32(VAL) 617 #define fCOUNTONES_8(VAL) ctpop64(VAL) 618 #define fBREV_8(VAL) revbit64(VAL) 619 #define fBREV_4(VAL) revbit32(VAL) 620 #define fCL1_8(VAL) clo64(VAL) 621 #define fCL1_4(VAL) clo32(VAL) 622 #define fCL1_2(VAL) (clz32(~(uint16_t)(VAL) & 0xffff) - 16) 623 #define fINTERLEAVE(ODD, EVEN) interleave(ODD, EVEN) 624 #define fDEINTERLEAVE(MIXED) deinterleave(MIXED) 625 #define fHIDE(A) A 626 #define fCONSTLL(A) A##LL 627 #define fECHO(A) (A) 628 629 #define fTRAP(TRAPTYPE, IMM) helper_raise_exception(env, HEX_EXCP_TRAP0) 630 #define fPAUSE(IMM) 631 632 #define fALIGN_REG_FIELD_VALUE(FIELD, VAL) \ 633 ((VAL) << reg_field_info[FIELD].offset) 634 #define fGET_REG_FIELD_MASK(FIELD) \ 635 (((1 << reg_field_info[FIELD].width) - 1) << reg_field_info[FIELD].offset) 636 #define fREAD_REG_FIELD(REG, FIELD) \ 637 fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \ 638 reg_field_info[FIELD].width, \ 639 reg_field_info[FIELD].offset) 640 641 #ifdef QEMU_GENERATE 642 #define fDCZEROA(REG) tcg_gen_mov_tl(hex_dczero_addr, (REG)) 643 #endif 644 645 #define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \ 646 STRBITNUM) /* Nothing */ 647 648 649 #endif 650