1 /* 2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef HEXAGON_GEN_TCG_H 19 #define HEXAGON_GEN_TCG_H 20 21 /* 22 * Here is a primer to understand the tag names for load/store instructions 23 * 24 * Data types 25 * b signed byte r0 = memb(r2+#0) 26 * ub unsigned byte r0 = memub(r2+#0) 27 * h signed half word (16 bits) r0 = memh(r2+#0) 28 * uh unsigned half word r0 = memuh(r2+#0) 29 * i integer (32 bits) r0 = memw(r2+#0) 30 * d double word (64 bits) r1:0 = memd(r2+#0) 31 * 32 * Addressing modes 33 * _io indirect with offset r0 = memw(r1+#4) 34 * _ur absolute with register offset r0 = memw(r1<<#4+##variable) 35 * _rr indirect with register offset r0 = memw(r1+r4<<#2) 36 * gp global pointer relative r0 = memw(gp+#200) 37 * _sp stack pointer relative r0 = memw(r29+#12) 38 * _ap absolute set r0 = memw(r1=##variable) 39 * _pr post increment register r0 = memw(r1++m1) 40 * _pbr post increment bit reverse r0 = memw(r1++m1:brev) 41 * _pi post increment immediate r0 = memb(r1++#1) 42 * _pci post increment circular immediate r0 = memw(r1++#4:circ(m0)) 43 * _pcr post increment circular register r0 = memw(r1++I:circ(m0)) 44 */ 45 46 /* Macros for complex addressing modes */ 47 #define GET_EA_ap \ 48 do { \ 49 fEA_IMM(UiV); \ 50 tcg_gen_movi_tl(ReV, UiV); \ 51 } while (0) 52 #define GET_EA_pr \ 53 do { \ 54 fEA_REG(RxV); \ 55 fPM_M(RxV, MuV); \ 56 } while (0) 57 #define GET_EA_pbr \ 58 do { \ 59 gen_helper_fbrev(EA, RxV); \ 60 tcg_gen_add_tl(RxV, RxV, MuV); \ 61 } while (0) 62 #define GET_EA_pi \ 63 do { \ 64 fEA_REG(RxV); \ 65 fPM_I(RxV, siV); \ 66 } while (0) 67 #define GET_EA_pci \ 68 do { \ 69 TCGv tcgv_siV = tcg_constant_tl(siV); \ 70 tcg_gen_mov_tl(EA, RxV); \ 71 gen_helper_fcircadd(RxV, RxV, tcgv_siV, MuV, \ 72 hex_gpr[HEX_REG_CS0 + MuN]); \ 73 } while (0) 74 #define GET_EA_pcr(SHIFT) \ 75 do { \ 76 TCGv ireg = tcg_temp_new(); \ 77 tcg_gen_mov_tl(EA, RxV); \ 78 gen_read_ireg(ireg, MuV, (SHIFT)); \ 79 gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \ 80 } while (0) 81 82 /* Instructions with multiple definitions */ 83 #define fGEN_TCG_LOAD_AP(RES, SIZE, SIGN) \ 84 do { \ 85 fMUST_IMMEXT(UiV); \ 86 fEA_IMM(UiV); \ 87 fLOAD(1, SIZE, SIGN, EA, RES); \ 88 tcg_gen_movi_tl(ReV, UiV); \ 89 } while (0) 90 91 #define fGEN_TCG_L4_loadrub_ap(SHORTCODE) \ 92 fGEN_TCG_LOAD_AP(RdV, 1, u) 93 #define fGEN_TCG_L4_loadrb_ap(SHORTCODE) \ 94 fGEN_TCG_LOAD_AP(RdV, 1, s) 95 #define fGEN_TCG_L4_loadruh_ap(SHORTCODE) \ 96 fGEN_TCG_LOAD_AP(RdV, 2, u) 97 #define fGEN_TCG_L4_loadrh_ap(SHORTCODE) \ 98 fGEN_TCG_LOAD_AP(RdV, 2, s) 99 #define fGEN_TCG_L4_loadri_ap(SHORTCODE) \ 100 fGEN_TCG_LOAD_AP(RdV, 4, u) 101 #define fGEN_TCG_L4_loadrd_ap(SHORTCODE) \ 102 fGEN_TCG_LOAD_AP(RddV, 8, u) 103 104 #define fGEN_TCG_L2_loadrub_pci(SHORTCODE) SHORTCODE 105 #define fGEN_TCG_L2_loadrb_pci(SHORTCODE) SHORTCODE 106 #define fGEN_TCG_L2_loadruh_pci(SHORTCODE) SHORTCODE 107 #define fGEN_TCG_L2_loadrh_pci(SHORTCODE) SHORTCODE 108 #define fGEN_TCG_L2_loadri_pci(SHORTCODE) SHORTCODE 109 #define fGEN_TCG_L2_loadrd_pci(SHORTCODE) SHORTCODE 110 111 #define fGEN_TCG_LOAD_pcr(SHIFT, LOAD) \ 112 do { \ 113 TCGv ireg = tcg_temp_new(); \ 114 tcg_gen_mov_tl(EA, RxV); \ 115 gen_read_ireg(ireg, MuV, SHIFT); \ 116 gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \ 117 LOAD; \ 118 } while (0) 119 120 #define fGEN_TCG_L2_loadrub_pcr(SHORTCODE) \ 121 fGEN_TCG_LOAD_pcr(0, fLOAD(1, 1, u, EA, RdV)) 122 #define fGEN_TCG_L2_loadrb_pcr(SHORTCODE) \ 123 fGEN_TCG_LOAD_pcr(0, fLOAD(1, 1, s, EA, RdV)) 124 #define fGEN_TCG_L2_loadruh_pcr(SHORTCODE) \ 125 fGEN_TCG_LOAD_pcr(1, fLOAD(1, 2, u, EA, RdV)) 126 #define fGEN_TCG_L2_loadrh_pcr(SHORTCODE) \ 127 fGEN_TCG_LOAD_pcr(1, fLOAD(1, 2, s, EA, RdV)) 128 #define fGEN_TCG_L2_loadri_pcr(SHORTCODE) \ 129 fGEN_TCG_LOAD_pcr(2, fLOAD(1, 4, u, EA, RdV)) 130 #define fGEN_TCG_L2_loadrd_pcr(SHORTCODE) \ 131 fGEN_TCG_LOAD_pcr(3, fLOAD(1, 8, u, EA, RddV)) 132 133 #define fGEN_TCG_L2_loadrub_pr(SHORTCODE) SHORTCODE 134 #define fGEN_TCG_L2_loadrub_pbr(SHORTCODE) SHORTCODE 135 #define fGEN_TCG_L2_loadrub_pi(SHORTCODE) SHORTCODE 136 #define fGEN_TCG_L2_loadrb_pr(SHORTCODE) SHORTCODE 137 #define fGEN_TCG_L2_loadrb_pbr(SHORTCODE) SHORTCODE 138 #define fGEN_TCG_L2_loadrb_pi(SHORTCODE) SHORTCODE 139 #define fGEN_TCG_L2_loadruh_pr(SHORTCODE) SHORTCODE 140 #define fGEN_TCG_L2_loadruh_pbr(SHORTCODE) SHORTCODE 141 #define fGEN_TCG_L2_loadruh_pi(SHORTCODE) SHORTCODE 142 #define fGEN_TCG_L2_loadrh_pr(SHORTCODE) SHORTCODE 143 #define fGEN_TCG_L2_loadrh_pbr(SHORTCODE) SHORTCODE 144 #define fGEN_TCG_L2_loadrh_pi(SHORTCODE) SHORTCODE 145 #define fGEN_TCG_L2_loadri_pr(SHORTCODE) SHORTCODE 146 #define fGEN_TCG_L2_loadri_pbr(SHORTCODE) SHORTCODE 147 #define fGEN_TCG_L2_loadri_pi(SHORTCODE) SHORTCODE 148 #define fGEN_TCG_L2_loadrd_pr(SHORTCODE) SHORTCODE 149 #define fGEN_TCG_L2_loadrd_pbr(SHORTCODE) SHORTCODE 150 #define fGEN_TCG_L2_loadrd_pi(SHORTCODE) SHORTCODE 151 152 /* 153 * These instructions load 2 bytes and places them in 154 * two halves of the destination register. 155 * The GET_EA macro determines the addressing mode. 156 * The SIGN argument determines whether to zero-extend or 157 * sign-extend. 158 */ 159 #define fGEN_TCG_loadbXw2(GET_EA, SIGN) \ 160 do { \ 161 TCGv tmp = tcg_temp_new(); \ 162 TCGv byte = tcg_temp_new(); \ 163 GET_EA; \ 164 fLOAD(1, 2, u, EA, tmp); \ 165 tcg_gen_movi_tl(RdV, 0); \ 166 for (int i = 0; i < 2; i++) { \ 167 gen_set_half(i, RdV, gen_get_byte(byte, i, tmp, (SIGN))); \ 168 } \ 169 } while (0) 170 171 #define fGEN_TCG_L2_loadbzw2_io(SHORTCODE) \ 172 fGEN_TCG_loadbXw2(fEA_RI(RsV, siV), false) 173 #define fGEN_TCG_L4_loadbzw2_ur(SHORTCODE) \ 174 fGEN_TCG_loadbXw2(fEA_IRs(UiV, RtV, uiV), false) 175 #define fGEN_TCG_L2_loadbsw2_io(SHORTCODE) \ 176 fGEN_TCG_loadbXw2(fEA_RI(RsV, siV), true) 177 #define fGEN_TCG_L4_loadbsw2_ur(SHORTCODE) \ 178 fGEN_TCG_loadbXw2(fEA_IRs(UiV, RtV, uiV), true) 179 #define fGEN_TCG_L4_loadbzw2_ap(SHORTCODE) \ 180 fGEN_TCG_loadbXw2(GET_EA_ap, false) 181 #define fGEN_TCG_L2_loadbzw2_pr(SHORTCODE) \ 182 fGEN_TCG_loadbXw2(GET_EA_pr, false) 183 #define fGEN_TCG_L2_loadbzw2_pbr(SHORTCODE) \ 184 fGEN_TCG_loadbXw2(GET_EA_pbr, false) 185 #define fGEN_TCG_L2_loadbzw2_pi(SHORTCODE) \ 186 fGEN_TCG_loadbXw2(GET_EA_pi, false) 187 #define fGEN_TCG_L4_loadbsw2_ap(SHORTCODE) \ 188 fGEN_TCG_loadbXw2(GET_EA_ap, true) 189 #define fGEN_TCG_L2_loadbsw2_pr(SHORTCODE) \ 190 fGEN_TCG_loadbXw2(GET_EA_pr, true) 191 #define fGEN_TCG_L2_loadbsw2_pbr(SHORTCODE) \ 192 fGEN_TCG_loadbXw2(GET_EA_pbr, true) 193 #define fGEN_TCG_L2_loadbsw2_pi(SHORTCODE) \ 194 fGEN_TCG_loadbXw2(GET_EA_pi, true) 195 #define fGEN_TCG_L2_loadbzw2_pci(SHORTCODE) \ 196 fGEN_TCG_loadbXw2(GET_EA_pci, false) 197 #define fGEN_TCG_L2_loadbsw2_pci(SHORTCODE) \ 198 fGEN_TCG_loadbXw2(GET_EA_pci, true) 199 #define fGEN_TCG_L2_loadbzw2_pcr(SHORTCODE) \ 200 fGEN_TCG_loadbXw2(GET_EA_pcr(1), false) 201 #define fGEN_TCG_L2_loadbsw2_pcr(SHORTCODE) \ 202 fGEN_TCG_loadbXw2(GET_EA_pcr(1), true) 203 204 /* 205 * These instructions load 4 bytes and places them in 206 * four halves of the destination register pair. 207 * The GET_EA macro determines the addressing mode. 208 * The SIGN argument determines whether to zero-extend or 209 * sign-extend. 210 */ 211 #define fGEN_TCG_loadbXw4(GET_EA, SIGN) \ 212 do { \ 213 TCGv tmp = tcg_temp_new(); \ 214 TCGv byte = tcg_temp_new(); \ 215 GET_EA; \ 216 fLOAD(1, 4, u, EA, tmp); \ 217 tcg_gen_movi_i64(RddV, 0); \ 218 for (int i = 0; i < 4; i++) { \ 219 gen_set_half_i64(i, RddV, gen_get_byte(byte, i, tmp, (SIGN))); \ 220 } \ 221 } while (0) 222 223 #define fGEN_TCG_L2_loadbzw4_io(SHORTCODE) \ 224 fGEN_TCG_loadbXw4(fEA_RI(RsV, siV), false) 225 #define fGEN_TCG_L4_loadbzw4_ur(SHORTCODE) \ 226 fGEN_TCG_loadbXw4(fEA_IRs(UiV, RtV, uiV), false) 227 #define fGEN_TCG_L2_loadbsw4_io(SHORTCODE) \ 228 fGEN_TCG_loadbXw4(fEA_RI(RsV, siV), true) 229 #define fGEN_TCG_L4_loadbsw4_ur(SHORTCODE) \ 230 fGEN_TCG_loadbXw4(fEA_IRs(UiV, RtV, uiV), true) 231 #define fGEN_TCG_L2_loadbzw4_pci(SHORTCODE) \ 232 fGEN_TCG_loadbXw4(GET_EA_pci, false) 233 #define fGEN_TCG_L2_loadbsw4_pci(SHORTCODE) \ 234 fGEN_TCG_loadbXw4(GET_EA_pci, true) 235 #define fGEN_TCG_L2_loadbzw4_pcr(SHORTCODE) \ 236 fGEN_TCG_loadbXw4(GET_EA_pcr(2), false) 237 #define fGEN_TCG_L2_loadbsw4_pcr(SHORTCODE) \ 238 fGEN_TCG_loadbXw4(GET_EA_pcr(2), true) 239 #define fGEN_TCG_L4_loadbzw4_ap(SHORTCODE) \ 240 fGEN_TCG_loadbXw4(GET_EA_ap, false) 241 #define fGEN_TCG_L2_loadbzw4_pr(SHORTCODE) \ 242 fGEN_TCG_loadbXw4(GET_EA_pr, false) 243 #define fGEN_TCG_L2_loadbzw4_pbr(SHORTCODE) \ 244 fGEN_TCG_loadbXw4(GET_EA_pbr, false) 245 #define fGEN_TCG_L2_loadbzw4_pi(SHORTCODE) \ 246 fGEN_TCG_loadbXw4(GET_EA_pi, false) 247 #define fGEN_TCG_L4_loadbsw4_ap(SHORTCODE) \ 248 fGEN_TCG_loadbXw4(GET_EA_ap, true) 249 #define fGEN_TCG_L2_loadbsw4_pr(SHORTCODE) \ 250 fGEN_TCG_loadbXw4(GET_EA_pr, true) 251 #define fGEN_TCG_L2_loadbsw4_pbr(SHORTCODE) \ 252 fGEN_TCG_loadbXw4(GET_EA_pbr, true) 253 #define fGEN_TCG_L2_loadbsw4_pi(SHORTCODE) \ 254 fGEN_TCG_loadbXw4(GET_EA_pi, true) 255 256 /* 257 * These instructions load a half word, shift the destination right by 16 bits 258 * and place the loaded value in the high half word of the destination pair. 259 * The GET_EA macro determines the addressing mode. 260 */ 261 #define fGEN_TCG_loadalignh(GET_EA) \ 262 do { \ 263 TCGv tmp = tcg_temp_new(); \ 264 TCGv_i64 tmp_i64 = tcg_temp_new_i64(); \ 265 GET_EA; \ 266 fLOAD(1, 2, u, EA, tmp); \ 267 tcg_gen_extu_i32_i64(tmp_i64, tmp); \ 268 tcg_gen_shri_i64(RyyV, RyyV, 16); \ 269 tcg_gen_deposit_i64(RyyV, RyyV, tmp_i64, 48, 16); \ 270 } while (0) 271 272 #define fGEN_TCG_L4_loadalignh_ur(SHORTCODE) \ 273 fGEN_TCG_loadalignh(fEA_IRs(UiV, RtV, uiV)) 274 #define fGEN_TCG_L2_loadalignh_io(SHORTCODE) \ 275 fGEN_TCG_loadalignh(fEA_RI(RsV, siV)) 276 #define fGEN_TCG_L2_loadalignh_pci(SHORTCODE) \ 277 fGEN_TCG_loadalignh(GET_EA_pci) 278 #define fGEN_TCG_L2_loadalignh_pcr(SHORTCODE) \ 279 fGEN_TCG_loadalignh(GET_EA_pcr(1)) 280 #define fGEN_TCG_L4_loadalignh_ap(SHORTCODE) \ 281 fGEN_TCG_loadalignh(GET_EA_ap) 282 #define fGEN_TCG_L2_loadalignh_pr(SHORTCODE) \ 283 fGEN_TCG_loadalignh(GET_EA_pr) 284 #define fGEN_TCG_L2_loadalignh_pbr(SHORTCODE) \ 285 fGEN_TCG_loadalignh(GET_EA_pbr) 286 #define fGEN_TCG_L2_loadalignh_pi(SHORTCODE) \ 287 fGEN_TCG_loadalignh(GET_EA_pi) 288 289 /* Same as above, but loads a byte instead of half word */ 290 #define fGEN_TCG_loadalignb(GET_EA) \ 291 do { \ 292 TCGv tmp = tcg_temp_new(); \ 293 TCGv_i64 tmp_i64 = tcg_temp_new_i64(); \ 294 GET_EA; \ 295 fLOAD(1, 1, u, EA, tmp); \ 296 tcg_gen_extu_i32_i64(tmp_i64, tmp); \ 297 tcg_gen_shri_i64(RyyV, RyyV, 8); \ 298 tcg_gen_deposit_i64(RyyV, RyyV, tmp_i64, 56, 8); \ 299 } while (0) 300 301 #define fGEN_TCG_L2_loadalignb_io(SHORTCODE) \ 302 fGEN_TCG_loadalignb(fEA_RI(RsV, siV)) 303 #define fGEN_TCG_L4_loadalignb_ur(SHORTCODE) \ 304 fGEN_TCG_loadalignb(fEA_IRs(UiV, RtV, uiV)) 305 #define fGEN_TCG_L2_loadalignb_pci(SHORTCODE) \ 306 fGEN_TCG_loadalignb(GET_EA_pci) 307 #define fGEN_TCG_L2_loadalignb_pcr(SHORTCODE) \ 308 fGEN_TCG_loadalignb(GET_EA_pcr(0)) 309 #define fGEN_TCG_L4_loadalignb_ap(SHORTCODE) \ 310 fGEN_TCG_loadalignb(GET_EA_ap) 311 #define fGEN_TCG_L2_loadalignb_pr(SHORTCODE) \ 312 fGEN_TCG_loadalignb(GET_EA_pr) 313 #define fGEN_TCG_L2_loadalignb_pbr(SHORTCODE) \ 314 fGEN_TCG_loadalignb(GET_EA_pbr) 315 #define fGEN_TCG_L2_loadalignb_pi(SHORTCODE) \ 316 fGEN_TCG_loadalignb(GET_EA_pi) 317 318 /* 319 * Predicated loads 320 * Here is a primer to understand the tag names 321 * 322 * Predicate used 323 * t true "old" value if (p0) r0 = memb(r2+#0) 324 * f false "old" value if (!p0) r0 = memb(r2+#0) 325 * tnew true "new" value if (p0.new) r0 = memb(r2+#0) 326 * fnew false "new" value if (!p0.new) r0 = memb(r2+#0) 327 */ 328 #define fGEN_TCG_PRED_LOAD(GET_EA, PRED, SIZE, SIGN) \ 329 do { \ 330 TCGv LSB = tcg_temp_new(); \ 331 TCGLabel *label = gen_new_label(); \ 332 tcg_gen_movi_tl(EA, 0); \ 333 PRED; \ 334 CHECK_NOSHUF_PRED(GET_EA, SIZE, LSB); \ 335 PRED_LOAD_CANCEL(LSB, EA); \ 336 tcg_gen_movi_tl(RdV, 0); \ 337 tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \ 338 fLOAD(1, SIZE, SIGN, EA, RdV); \ 339 gen_set_label(label); \ 340 } while (0) 341 342 #define fGEN_TCG_L2_ploadrubt_pi(SHORTCODE) \ 343 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 1, u) 344 #define fGEN_TCG_L2_ploadrubf_pi(SHORTCODE) \ 345 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 1, u) 346 #define fGEN_TCG_L2_ploadrubtnew_pi(SHORTCODE) \ 347 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 1, u) 348 #define fGEN_TCG_L2_ploadrubfnew_pi(SHORTCODE) \ 349 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 1, u) 350 #define fGEN_TCG_L2_ploadrbt_pi(SHORTCODE) \ 351 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 1, s) 352 #define fGEN_TCG_L2_ploadrbf_pi(SHORTCODE) \ 353 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 1, s) 354 #define fGEN_TCG_L2_ploadrbtnew_pi(SHORTCODE) \ 355 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 1, s) 356 #define fGEN_TCG_L2_ploadrbfnew_pi(SHORTCODE) \ 357 fGEN_TCG_PRED_LOAD({ fEA_REG(RxV); fPM_I(RxV, siV); }, \ 358 fLSBNEWNOT(PtN), 1, s) 359 360 #define fGEN_TCG_L2_ploadruht_pi(SHORTCODE) \ 361 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 2, u) 362 #define fGEN_TCG_L2_ploadruhf_pi(SHORTCODE) \ 363 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 2, u) 364 #define fGEN_TCG_L2_ploadruhtnew_pi(SHORTCODE) \ 365 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 2, u) 366 #define fGEN_TCG_L2_ploadruhfnew_pi(SHORTCODE) \ 367 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 2, u) 368 #define fGEN_TCG_L2_ploadrht_pi(SHORTCODE) \ 369 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 2, s) 370 #define fGEN_TCG_L2_ploadrhf_pi(SHORTCODE) \ 371 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 2, s) 372 #define fGEN_TCG_L2_ploadrhtnew_pi(SHORTCODE) \ 373 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 2, s) 374 #define fGEN_TCG_L2_ploadrhfnew_pi(SHORTCODE) \ 375 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 2, s) 376 377 #define fGEN_TCG_L2_ploadrit_pi(SHORTCODE) \ 378 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 4, u) 379 #define fGEN_TCG_L2_ploadrif_pi(SHORTCODE) \ 380 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 4, u) 381 #define fGEN_TCG_L2_ploadritnew_pi(SHORTCODE) \ 382 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 4, u) 383 #define fGEN_TCG_L2_ploadrifnew_pi(SHORTCODE) \ 384 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 4, u) 385 386 /* Predicated loads into a register pair */ 387 #define fGEN_TCG_PRED_LOAD_PAIR(GET_EA, PRED) \ 388 do { \ 389 TCGv LSB = tcg_temp_new(); \ 390 TCGLabel *label = gen_new_label(); \ 391 tcg_gen_movi_tl(EA, 0); \ 392 PRED; \ 393 CHECK_NOSHUF_PRED(GET_EA, 8, LSB); \ 394 PRED_LOAD_CANCEL(LSB, EA); \ 395 tcg_gen_movi_i64(RddV, 0); \ 396 tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \ 397 fLOAD(1, 8, u, EA, RddV); \ 398 gen_set_label(label); \ 399 } while (0) 400 401 #define fGEN_TCG_L2_ploadrdt_pi(SHORTCODE) \ 402 fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBOLD(PtV)) 403 #define fGEN_TCG_L2_ploadrdf_pi(SHORTCODE) \ 404 fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBOLDNOT(PtV)) 405 #define fGEN_TCG_L2_ploadrdtnew_pi(SHORTCODE) \ 406 fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBNEW(PtN)) 407 #define fGEN_TCG_L2_ploadrdfnew_pi(SHORTCODE) \ 408 fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBNEWNOT(PtN)) 409 410 /* load-locked and store-locked */ 411 #define fGEN_TCG_L2_loadw_locked(SHORTCODE) \ 412 SHORTCODE 413 #define fGEN_TCG_L4_loadd_locked(SHORTCODE) \ 414 SHORTCODE 415 #define fGEN_TCG_S2_storew_locked(SHORTCODE) \ 416 SHORTCODE 417 #define fGEN_TCG_S4_stored_locked(SHORTCODE) \ 418 SHORTCODE 419 420 #define fGEN_TCG_STORE(SHORTCODE) \ 421 do { \ 422 TCGv HALF G_GNUC_UNUSED = tcg_temp_new(); \ 423 TCGv BYTE G_GNUC_UNUSED = tcg_temp_new(); \ 424 SHORTCODE; \ 425 } while (0) 426 427 #define fGEN_TCG_STORE_pcr(SHIFT, STORE) \ 428 do { \ 429 TCGv ireg = tcg_temp_new(); \ 430 TCGv HALF G_GNUC_UNUSED = tcg_temp_new(); \ 431 TCGv BYTE G_GNUC_UNUSED = tcg_temp_new(); \ 432 tcg_gen_mov_tl(EA, RxV); \ 433 gen_read_ireg(ireg, MuV, SHIFT); \ 434 gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \ 435 STORE; \ 436 } while (0) 437 438 #define fGEN_TCG_S2_storerb_pbr(SHORTCODE) \ 439 fGEN_TCG_STORE(SHORTCODE) 440 #define fGEN_TCG_S2_storerb_pci(SHORTCODE) \ 441 fGEN_TCG_STORE(SHORTCODE) 442 #define fGEN_TCG_S2_storerb_pcr(SHORTCODE) \ 443 fGEN_TCG_STORE_pcr(0, fSTORE(1, 1, EA, fGETBYTE(0, RtV))) 444 445 #define fGEN_TCG_S2_storerh_pbr(SHORTCODE) \ 446 fGEN_TCG_STORE(SHORTCODE) 447 #define fGEN_TCG_S2_storerh_pci(SHORTCODE) \ 448 fGEN_TCG_STORE(SHORTCODE) 449 #define fGEN_TCG_S2_storerh_pcr(SHORTCODE) \ 450 fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(0, RtV))) 451 452 #define fGEN_TCG_S2_storerf_pbr(SHORTCODE) \ 453 fGEN_TCG_STORE(SHORTCODE) 454 #define fGEN_TCG_S2_storerf_pci(SHORTCODE) \ 455 fGEN_TCG_STORE(SHORTCODE) 456 #define fGEN_TCG_S2_storerf_pcr(SHORTCODE) \ 457 fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(1, RtV))) 458 459 #define fGEN_TCG_S2_storeri_pbr(SHORTCODE) \ 460 fGEN_TCG_STORE(SHORTCODE) 461 #define fGEN_TCG_S2_storeri_pci(SHORTCODE) \ 462 fGEN_TCG_STORE(SHORTCODE) 463 #define fGEN_TCG_S2_storeri_pcr(SHORTCODE) \ 464 fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, RtV)) 465 466 #define fGEN_TCG_S2_storerd_pbr(SHORTCODE) \ 467 fGEN_TCG_STORE(SHORTCODE) 468 #define fGEN_TCG_S2_storerd_pci(SHORTCODE) \ 469 fGEN_TCG_STORE(SHORTCODE) 470 #define fGEN_TCG_S2_storerd_pcr(SHORTCODE) \ 471 fGEN_TCG_STORE_pcr(3, fSTORE(1, 8, EA, RttV)) 472 473 #define fGEN_TCG_S2_storerbnew_pbr(SHORTCODE) \ 474 fGEN_TCG_STORE(SHORTCODE) 475 #define fGEN_TCG_S2_storerbnew_pci(SHORTCODE) \ 476 fGEN_TCG_STORE(SHORTCODE) 477 #define fGEN_TCG_S2_storerbnew_pcr(SHORTCODE) \ 478 fGEN_TCG_STORE_pcr(0, fSTORE(1, 1, EA, fGETBYTE(0, NtN))) 479 480 #define fGEN_TCG_S2_storerhnew_pbr(SHORTCODE) \ 481 fGEN_TCG_STORE(SHORTCODE) 482 #define fGEN_TCG_S2_storerhnew_pci(SHORTCODE) \ 483 fGEN_TCG_STORE(SHORTCODE) 484 #define fGEN_TCG_S2_storerhnew_pcr(SHORTCODE) \ 485 fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(0, NtN))) 486 487 #define fGEN_TCG_S2_storerinew_pbr(SHORTCODE) \ 488 fGEN_TCG_STORE(SHORTCODE) 489 #define fGEN_TCG_S2_storerinew_pci(SHORTCODE) \ 490 fGEN_TCG_STORE(SHORTCODE) 491 #define fGEN_TCG_S2_storerinew_pcr(SHORTCODE) \ 492 fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, NtN)) 493 494 /* 495 * dealloc_return 496 * Assembler mapped to 497 * r31:30 = dealloc_return(r30):raw 498 */ 499 #define fGEN_TCG_L4_return(SHORTCODE) \ 500 gen_return(ctx, RddV, RsV) 501 502 /* 503 * sub-instruction version (no RddV, so handle it manually) 504 */ 505 #define fGEN_TCG_SL2_return(SHORTCODE) \ 506 do { \ 507 TCGv_i64 RddV = tcg_temp_new_i64(); \ 508 gen_return(ctx, RddV, hex_gpr[HEX_REG_FP]); \ 509 gen_log_reg_write_pair(HEX_REG_FP, RddV); \ 510 } while (0) 511 512 /* 513 * Conditional returns follow this naming convention 514 * _t predicate true 515 * _f predicate false 516 * _tnew_pt predicate.new true predict taken 517 * _fnew_pt predicate.new false predict taken 518 * _tnew_pnt predicate.new true predict not taken 519 * _fnew_pnt predicate.new false predict not taken 520 * Predictions are not modelled in QEMU 521 * 522 * Example: 523 * if (p1) r31:30 = dealloc_return(r30):raw 524 */ 525 #define fGEN_TCG_L4_return_t(SHORTCODE) \ 526 gen_cond_return(ctx, RddV, RsV, PvV, TCG_COND_EQ); 527 #define fGEN_TCG_L4_return_f(SHORTCODE) \ 528 gen_cond_return(ctx, RddV, RsV, PvV, TCG_COND_NE) 529 #define fGEN_TCG_L4_return_tnew_pt(SHORTCODE) \ 530 gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_EQ) 531 #define fGEN_TCG_L4_return_fnew_pt(SHORTCODE) \ 532 gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_NE) 533 #define fGEN_TCG_L4_return_tnew_pnt(SHORTCODE) \ 534 gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_EQ) 535 #define fGEN_TCG_L4_return_fnew_pnt(SHORTCODE) \ 536 gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_NE) 537 538 #define fGEN_TCG_SL2_return_t(SHORTCODE) \ 539 gen_cond_return_subinsn(ctx, TCG_COND_EQ, hex_pred[0]) 540 #define fGEN_TCG_SL2_return_f(SHORTCODE) \ 541 gen_cond_return_subinsn(ctx, TCG_COND_NE, hex_pred[0]) 542 #define fGEN_TCG_SL2_return_tnew(SHORTCODE) \ 543 gen_cond_return_subinsn(ctx, TCG_COND_EQ, hex_new_pred_value[0]) 544 #define fGEN_TCG_SL2_return_fnew(SHORTCODE) \ 545 gen_cond_return_subinsn(ctx, TCG_COND_NE, hex_new_pred_value[0]) 546 547 /* 548 * Mathematical operations with more than one definition require 549 * special handling 550 */ 551 #define fGEN_TCG_A5_ACS(SHORTCODE) \ 552 do { \ 553 gen_helper_vacsh_pred(PeV, cpu_env, RxxV, RssV, RttV); \ 554 gen_helper_vacsh_val(RxxV, cpu_env, RxxV, RssV, RttV); \ 555 } while (0) 556 557 /* 558 * Approximate reciprocal 559 * r3,p1 = sfrecipa(r0, r1) 560 * 561 * The helper packs the 2 32-bit results into a 64-bit value, 562 * so unpack them into the proper results. 563 */ 564 #define fGEN_TCG_F2_sfrecipa(SHORTCODE) \ 565 do { \ 566 TCGv_i64 tmp = tcg_temp_new_i64(); \ 567 gen_helper_sfrecipa(tmp, cpu_env, RsV, RtV); \ 568 tcg_gen_extrh_i64_i32(RdV, tmp); \ 569 tcg_gen_extrl_i64_i32(PeV, tmp); \ 570 } while (0) 571 572 /* 573 * Approximation of the reciprocal square root 574 * r1,p0 = sfinvsqrta(r0) 575 * 576 * The helper packs the 2 32-bit results into a 64-bit value, 577 * so unpack them into the proper results. 578 */ 579 #define fGEN_TCG_F2_sfinvsqrta(SHORTCODE) \ 580 do { \ 581 TCGv_i64 tmp = tcg_temp_new_i64(); \ 582 gen_helper_sfinvsqrta(tmp, cpu_env, RsV); \ 583 tcg_gen_extrh_i64_i32(RdV, tmp); \ 584 tcg_gen_extrl_i64_i32(PeV, tmp); \ 585 } while (0) 586 587 /* 588 * Add or subtract with carry. 589 * Predicate register is used as an extra input and output. 590 * r5:4 = add(r1:0, r3:2, p1):carry 591 */ 592 #define fGEN_TCG_A4_addp_c(SHORTCODE) \ 593 do { \ 594 TCGv_i64 carry = tcg_temp_new_i64(); \ 595 TCGv_i64 zero = tcg_constant_i64(0); \ 596 tcg_gen_extu_i32_i64(carry, PxV); \ 597 tcg_gen_andi_i64(carry, carry, 1); \ 598 tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \ 599 tcg_gen_add2_i64(RddV, carry, RddV, carry, RttV, zero); \ 600 tcg_gen_extrl_i64_i32(PxV, carry); \ 601 gen_8bitsof(PxV, PxV); \ 602 } while (0) 603 604 /* r5:4 = sub(r1:0, r3:2, p1):carry */ 605 #define fGEN_TCG_A4_subp_c(SHORTCODE) \ 606 do { \ 607 TCGv_i64 carry = tcg_temp_new_i64(); \ 608 TCGv_i64 zero = tcg_constant_i64(0); \ 609 TCGv_i64 not_RttV = tcg_temp_new_i64(); \ 610 tcg_gen_extu_i32_i64(carry, PxV); \ 611 tcg_gen_andi_i64(carry, carry, 1); \ 612 tcg_gen_not_i64(not_RttV, RttV); \ 613 tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \ 614 tcg_gen_add2_i64(RddV, carry, RddV, carry, not_RttV, zero); \ 615 tcg_gen_extrl_i64_i32(PxV, carry); \ 616 gen_8bitsof(PxV, PxV); \ 617 } while (0) 618 619 /* 620 * Compare each of the 8 unsigned bytes 621 * The minimum is placed in each byte of the destination. 622 * Each bit of the predicate is set true if the bit from the first operand 623 * is greater than the bit from the second operand. 624 * r5:4,p1 = vminub(r1:0, r3:2) 625 */ 626 #define fGEN_TCG_A6_vminub_RdP(SHORTCODE) \ 627 do { \ 628 TCGv left = tcg_temp_new(); \ 629 TCGv right = tcg_temp_new(); \ 630 TCGv tmp = tcg_temp_new(); \ 631 tcg_gen_movi_tl(PeV, 0); \ 632 tcg_gen_movi_i64(RddV, 0); \ 633 for (int i = 0; i < 8; i++) { \ 634 gen_get_byte_i64(left, i, RttV, false); \ 635 gen_get_byte_i64(right, i, RssV, false); \ 636 tcg_gen_setcond_tl(TCG_COND_GT, tmp, left, right); \ 637 tcg_gen_deposit_tl(PeV, PeV, tmp, i, 1); \ 638 tcg_gen_umin_tl(tmp, left, right); \ 639 gen_set_byte_i64(i, RddV, tmp); \ 640 } \ 641 } while (0) 642 643 #define fGEN_TCG_J2_call(SHORTCODE) \ 644 gen_call(ctx, riV) 645 #define fGEN_TCG_J2_callr(SHORTCODE) \ 646 gen_callr(ctx, RsV) 647 648 #define fGEN_TCG_J2_callt(SHORTCODE) \ 649 gen_cond_call(ctx, PuV, TCG_COND_EQ, riV) 650 #define fGEN_TCG_J2_callf(SHORTCODE) \ 651 gen_cond_call(ctx, PuV, TCG_COND_NE, riV) 652 #define fGEN_TCG_J2_callrt(SHORTCODE) \ 653 gen_cond_callr(ctx, TCG_COND_EQ, PuV, RsV) 654 #define fGEN_TCG_J2_callrf(SHORTCODE) \ 655 gen_cond_callr(ctx, TCG_COND_NE, PuV, RsV) 656 657 #define fGEN_TCG_J2_endloop0(SHORTCODE) \ 658 gen_endloop0(ctx) 659 #define fGEN_TCG_J2_endloop1(SHORTCODE) \ 660 gen_endloop1(ctx) 661 #define fGEN_TCG_J2_endloop01(SHORTCODE) \ 662 gen_endloop01(ctx) 663 664 /* 665 * Compound compare and jump instructions 666 * Here is a primer to understand the tag names 667 * 668 * Comparison 669 * cmpeqi compare equal to an immediate 670 * cmpgti compare greater than an immediate 671 * cmpgtiu compare greater than an unsigned immediate 672 * cmpeqn1 compare equal to negative 1 673 * cmpgtn1 compare greater than negative 1 674 * cmpeq compare equal (two registers) 675 * cmpgtu compare greater than unsigned (two registers) 676 * tstbit0 test bit zero 677 * 678 * Condition 679 * tp0 p0 is true p0 = cmp.eq(r0,#5); if (p0.new) jump:nt address 680 * fp0 p0 is false p0 = cmp.eq(r0,#5); if (!p0.new) jump:nt address 681 * tp1 p1 is true p1 = cmp.eq(r0,#5); if (p1.new) jump:nt address 682 * fp1 p1 is false p1 = cmp.eq(r0,#5); if (!p1.new) jump:nt address 683 * 684 * Prediction (not modelled in qemu) 685 * _nt not taken 686 * _t taken 687 */ 688 #define fGEN_TCG_J4_cmpeq_tp0_jump_t(SHORTCODE) \ 689 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_EQ, RsV, RtV, riV) 690 #define fGEN_TCG_J4_cmpeq_tp0_jump_nt(SHORTCODE) \ 691 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_EQ, RsV, RtV, riV) 692 #define fGEN_TCG_J4_cmpeq_fp0_jump_t(SHORTCODE) \ 693 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_EQ, RsV, RtV, riV) 694 #define fGEN_TCG_J4_cmpeq_fp0_jump_nt(SHORTCODE) \ 695 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_EQ, RsV, RtV, riV) 696 #define fGEN_TCG_J4_cmpeq_tp1_jump_t(SHORTCODE) \ 697 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_EQ, RsV, RtV, riV) 698 #define fGEN_TCG_J4_cmpeq_tp1_jump_nt(SHORTCODE) \ 699 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_EQ, RsV, RtV, riV) 700 #define fGEN_TCG_J4_cmpeq_fp1_jump_t(SHORTCODE) \ 701 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_EQ, RsV, RtV, riV) 702 #define fGEN_TCG_J4_cmpeq_fp1_jump_nt(SHORTCODE) \ 703 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_EQ, RsV, RtV, riV) 704 705 #define fGEN_TCG_J4_cmpgt_tp0_jump_t(SHORTCODE) \ 706 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_GT, RsV, RtV, riV) 707 #define fGEN_TCG_J4_cmpgt_tp0_jump_nt(SHORTCODE) \ 708 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_GT, RsV, RtV, riV) 709 #define fGEN_TCG_J4_cmpgt_fp0_jump_t(SHORTCODE) \ 710 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_GT, RsV, RtV, riV) 711 #define fGEN_TCG_J4_cmpgt_fp0_jump_nt(SHORTCODE) \ 712 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_GT, RsV, RtV, riV) 713 #define fGEN_TCG_J4_cmpgt_tp1_jump_t(SHORTCODE) \ 714 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_GT, RsV, RtV, riV) 715 #define fGEN_TCG_J4_cmpgt_tp1_jump_nt(SHORTCODE) \ 716 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_GT, RsV, RtV, riV) 717 #define fGEN_TCG_J4_cmpgt_fp1_jump_t(SHORTCODE) \ 718 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_GT, RsV, RtV, riV) 719 #define fGEN_TCG_J4_cmpgt_fp1_jump_nt(SHORTCODE) \ 720 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_GT, RsV, RtV, riV) 721 722 #define fGEN_TCG_J4_cmpgtu_tp0_jump_t(SHORTCODE) \ 723 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_GTU, RsV, RtV, riV) 724 #define fGEN_TCG_J4_cmpgtu_tp0_jump_nt(SHORTCODE) \ 725 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_GTU, RsV, RtV, riV) 726 #define fGEN_TCG_J4_cmpgtu_fp0_jump_t(SHORTCODE) \ 727 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_GTU, RsV, RtV, riV) 728 #define fGEN_TCG_J4_cmpgtu_fp0_jump_nt(SHORTCODE) \ 729 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_GTU, RsV, RtV, riV) 730 #define fGEN_TCG_J4_cmpgtu_tp1_jump_t(SHORTCODE) \ 731 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_GTU, RsV, RtV, riV) 732 #define fGEN_TCG_J4_cmpgtu_tp1_jump_nt(SHORTCODE) \ 733 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_GTU, RsV, RtV, riV) 734 #define fGEN_TCG_J4_cmpgtu_fp1_jump_t(SHORTCODE) \ 735 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_GTU, RsV, RtV, riV) 736 #define fGEN_TCG_J4_cmpgtu_fp1_jump_nt(SHORTCODE) \ 737 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_GTU, RsV, RtV, riV) 738 739 #define fGEN_TCG_J4_cmpeqi_tp0_jump_t(SHORTCODE) \ 740 gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_EQ, RsV, UiV, riV) 741 #define fGEN_TCG_J4_cmpeqi_tp0_jump_nt(SHORTCODE) \ 742 gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_EQ, RsV, UiV, riV) 743 #define fGEN_TCG_J4_cmpeqi_fp0_jump_t(SHORTCODE) \ 744 gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_EQ, RsV, UiV, riV) 745 #define fGEN_TCG_J4_cmpeqi_fp0_jump_nt(SHORTCODE) \ 746 gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_EQ, RsV, UiV, riV) 747 #define fGEN_TCG_J4_cmpeqi_tp1_jump_t(SHORTCODE) \ 748 gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_EQ, RsV, UiV, riV) 749 #define fGEN_TCG_J4_cmpeqi_tp1_jump_nt(SHORTCODE) \ 750 gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_EQ, RsV, UiV, riV) 751 #define fGEN_TCG_J4_cmpeqi_fp1_jump_t(SHORTCODE) \ 752 gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_EQ, RsV, UiV, riV) 753 #define fGEN_TCG_J4_cmpeqi_fp1_jump_nt(SHORTCODE) \ 754 gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_EQ, RsV, UiV, riV) 755 756 #define fGEN_TCG_J4_cmpgti_tp0_jump_t(SHORTCODE) \ 757 gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_GT, RsV, UiV, riV) 758 #define fGEN_TCG_J4_cmpgti_tp0_jump_nt(SHORTCODE) \ 759 gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_GT, RsV, UiV, riV) 760 #define fGEN_TCG_J4_cmpgti_fp0_jump_t(SHORTCODE) \ 761 gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_GT, RsV, UiV, riV) 762 #define fGEN_TCG_J4_cmpgti_fp0_jump_nt(SHORTCODE) \ 763 gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_GT, RsV, UiV, riV) 764 #define fGEN_TCG_J4_cmpgti_tp1_jump_t(SHORTCODE) \ 765 gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_GT, RsV, UiV, riV) 766 #define fGEN_TCG_J4_cmpgti_tp1_jump_nt(SHORTCODE) \ 767 gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_GT, RsV, UiV, riV) 768 #define fGEN_TCG_J4_cmpgti_fp1_jump_t(SHORTCODE) \ 769 gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_GT, RsV, UiV, riV) 770 #define fGEN_TCG_J4_cmpgti_fp1_jump_nt(SHORTCODE) \ 771 gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_GT, RsV, UiV, riV) 772 773 #define fGEN_TCG_J4_cmpgtui_tp0_jump_t(SHORTCODE) \ 774 gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_GTU, RsV, UiV, riV) 775 #define fGEN_TCG_J4_cmpgtui_tp0_jump_nt(SHORTCODE) \ 776 gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_GTU, RsV, UiV, riV) 777 #define fGEN_TCG_J4_cmpgtui_fp0_jump_t(SHORTCODE) \ 778 gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_GTU, RsV, UiV, riV) 779 #define fGEN_TCG_J4_cmpgtui_fp0_jump_nt(SHORTCODE) \ 780 gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_GTU, RsV, UiV, riV) 781 #define fGEN_TCG_J4_cmpgtui_tp1_jump_t(SHORTCODE) \ 782 gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_GTU, RsV, UiV, riV) 783 #define fGEN_TCG_J4_cmpgtui_tp1_jump_nt(SHORTCODE) \ 784 gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_GTU, RsV, UiV, riV) 785 #define fGEN_TCG_J4_cmpgtui_fp1_jump_t(SHORTCODE) \ 786 gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_GTU, RsV, UiV, riV) 787 #define fGEN_TCG_J4_cmpgtui_fp1_jump_nt(SHORTCODE) \ 788 gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_GTU, RsV, UiV, riV) 789 790 #define fGEN_TCG_J4_cmpeqn1_tp0_jump_t(SHORTCODE) \ 791 gen_cmpnd_cmp_n1_jmp_t(ctx, 0, TCG_COND_EQ, RsV, riV) 792 #define fGEN_TCG_J4_cmpeqn1_tp0_jump_nt(SHORTCODE) \ 793 gen_cmpnd_cmp_n1_jmp_t(ctx, 0, TCG_COND_EQ, RsV, riV) 794 #define fGEN_TCG_J4_cmpeqn1_fp0_jump_t(SHORTCODE) \ 795 gen_cmpnd_cmp_n1_jmp_f(ctx, 0, TCG_COND_EQ, RsV, riV) 796 #define fGEN_TCG_J4_cmpeqn1_fp0_jump_nt(SHORTCODE) \ 797 gen_cmpnd_cmp_n1_jmp_f(ctx, 0, TCG_COND_EQ, RsV, riV) 798 #define fGEN_TCG_J4_cmpeqn1_tp1_jump_t(SHORTCODE) \ 799 gen_cmpnd_cmp_n1_jmp_t(ctx, 1, TCG_COND_EQ, RsV, riV) 800 #define fGEN_TCG_J4_cmpeqn1_tp1_jump_nt(SHORTCODE) \ 801 gen_cmpnd_cmp_n1_jmp_t(ctx, 1, TCG_COND_EQ, RsV, riV) 802 #define fGEN_TCG_J4_cmpeqn1_fp1_jump_t(SHORTCODE) \ 803 gen_cmpnd_cmp_n1_jmp_f(ctx, 1, TCG_COND_EQ, RsV, riV) 804 #define fGEN_TCG_J4_cmpeqn1_fp1_jump_nt(SHORTCODE) \ 805 gen_cmpnd_cmp_n1_jmp_f(ctx, 1, TCG_COND_EQ, RsV, riV) 806 807 #define fGEN_TCG_J4_cmpgtn1_tp0_jump_t(SHORTCODE) \ 808 gen_cmpnd_cmp_n1_jmp_t(ctx, 0, TCG_COND_GT, RsV, riV) 809 #define fGEN_TCG_J4_cmpgtn1_tp0_jump_nt(SHORTCODE) \ 810 gen_cmpnd_cmp_n1_jmp_t(ctx, 0, TCG_COND_GT, RsV, riV) 811 #define fGEN_TCG_J4_cmpgtn1_fp0_jump_t(SHORTCODE) \ 812 gen_cmpnd_cmp_n1_jmp_f(ctx, 0, TCG_COND_GT, RsV, riV) 813 #define fGEN_TCG_J4_cmpgtn1_fp0_jump_nt(SHORTCODE) \ 814 gen_cmpnd_cmp_n1_jmp_f(ctx, 0, TCG_COND_GT, RsV, riV) 815 #define fGEN_TCG_J4_cmpgtn1_tp1_jump_t(SHORTCODE) \ 816 gen_cmpnd_cmp_n1_jmp_t(ctx, 1, TCG_COND_GT, RsV, riV) 817 #define fGEN_TCG_J4_cmpgtn1_tp1_jump_nt(SHORTCODE) \ 818 gen_cmpnd_cmp_n1_jmp_t(ctx, 1, TCG_COND_GT, RsV, riV) 819 #define fGEN_TCG_J4_cmpgtn1_fp1_jump_t(SHORTCODE) \ 820 gen_cmpnd_cmp_n1_jmp_f(ctx, 1, TCG_COND_GT, RsV, riV) 821 #define fGEN_TCG_J4_cmpgtn1_fp1_jump_nt(SHORTCODE) \ 822 gen_cmpnd_cmp_n1_jmp_f(ctx, 1, TCG_COND_GT, RsV, riV) 823 824 #define fGEN_TCG_J4_tstbit0_tp0_jump_nt(SHORTCODE) \ 825 gen_cmpnd_tstbit0_jmp(ctx, 0, RsV, TCG_COND_EQ, riV) 826 #define fGEN_TCG_J4_tstbit0_tp0_jump_t(SHORTCODE) \ 827 gen_cmpnd_tstbit0_jmp(ctx, 0, RsV, TCG_COND_EQ, riV) 828 #define fGEN_TCG_J4_tstbit0_fp0_jump_nt(SHORTCODE) \ 829 gen_cmpnd_tstbit0_jmp(ctx, 0, RsV, TCG_COND_NE, riV) 830 #define fGEN_TCG_J4_tstbit0_fp0_jump_t(SHORTCODE) \ 831 gen_cmpnd_tstbit0_jmp(ctx, 0, RsV, TCG_COND_NE, riV) 832 #define fGEN_TCG_J4_tstbit0_tp1_jump_nt(SHORTCODE) \ 833 gen_cmpnd_tstbit0_jmp(ctx, 1, RsV, TCG_COND_EQ, riV) 834 #define fGEN_TCG_J4_tstbit0_tp1_jump_t(SHORTCODE) \ 835 gen_cmpnd_tstbit0_jmp(ctx, 1, RsV, TCG_COND_EQ, riV) 836 #define fGEN_TCG_J4_tstbit0_fp1_jump_nt(SHORTCODE) \ 837 gen_cmpnd_tstbit0_jmp(ctx, 1, RsV, TCG_COND_NE, riV) 838 #define fGEN_TCG_J4_tstbit0_fp1_jump_t(SHORTCODE) \ 839 gen_cmpnd_tstbit0_jmp(ctx, 1, RsV, TCG_COND_NE, riV) 840 841 #define fGEN_TCG_J2_jump(SHORTCODE) \ 842 gen_jump(ctx, riV) 843 #define fGEN_TCG_J2_jumpr(SHORTCODE) \ 844 gen_jumpr(ctx, RsV) 845 #define fGEN_TCG_J4_jumpseti(SHORTCODE) \ 846 do { \ 847 tcg_gen_movi_tl(RdV, UiV); \ 848 gen_jump(ctx, riV); \ 849 } while (0) 850 851 #define fGEN_TCG_cond_jumpt(COND) \ 852 do { \ 853 TCGv LSB = tcg_temp_new(); \ 854 COND; \ 855 gen_cond_jump(ctx, TCG_COND_EQ, LSB, riV); \ 856 } while (0) 857 #define fGEN_TCG_cond_jumpf(COND) \ 858 do { \ 859 TCGv LSB = tcg_temp_new(); \ 860 COND; \ 861 gen_cond_jump(ctx, TCG_COND_NE, LSB, riV); \ 862 } while (0) 863 864 #define fGEN_TCG_J2_jumpt(SHORTCODE) \ 865 fGEN_TCG_cond_jumpt(fLSBOLD(PuV)) 866 #define fGEN_TCG_J2_jumptpt(SHORTCODE) \ 867 fGEN_TCG_cond_jumpt(fLSBOLD(PuV)) 868 #define fGEN_TCG_J2_jumpf(SHORTCODE) \ 869 fGEN_TCG_cond_jumpf(fLSBOLD(PuV)) 870 #define fGEN_TCG_J2_jumpfpt(SHORTCODE) \ 871 fGEN_TCG_cond_jumpf(fLSBOLD(PuV)) 872 #define fGEN_TCG_J2_jumptnew(SHORTCODE) \ 873 gen_cond_jump(ctx, TCG_COND_EQ, PuN, riV) 874 #define fGEN_TCG_J2_jumptnewpt(SHORTCODE) \ 875 gen_cond_jump(ctx, TCG_COND_EQ, PuN, riV) 876 #define fGEN_TCG_J2_jumpfnewpt(SHORTCODE) \ 877 fGEN_TCG_cond_jumpf(fLSBNEW(PuN)) 878 #define fGEN_TCG_J2_jumpfnew(SHORTCODE) \ 879 fGEN_TCG_cond_jumpf(fLSBNEW(PuN)) 880 #define fGEN_TCG_J2_jumprz(SHORTCODE) \ 881 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_NE, LSB, RsV, 0)) 882 #define fGEN_TCG_J2_jumprzpt(SHORTCODE) \ 883 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_NE, LSB, RsV, 0)) 884 #define fGEN_TCG_J2_jumprnz(SHORTCODE) \ 885 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_EQ, LSB, RsV, 0)) 886 #define fGEN_TCG_J2_jumprnzpt(SHORTCODE) \ 887 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_EQ, LSB, RsV, 0)) 888 #define fGEN_TCG_J2_jumprgtez(SHORTCODE) \ 889 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_GE, LSB, RsV, 0)) 890 #define fGEN_TCG_J2_jumprgtezpt(SHORTCODE) \ 891 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_GE, LSB, RsV, 0)) 892 #define fGEN_TCG_J2_jumprltez(SHORTCODE) \ 893 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_LE, LSB, RsV, 0)) 894 #define fGEN_TCG_J2_jumprltezpt(SHORTCODE) \ 895 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_LE, LSB, RsV, 0)) 896 897 #define fGEN_TCG_cond_jumprt(COND) \ 898 do { \ 899 TCGv LSB = tcg_temp_new(); \ 900 COND; \ 901 gen_cond_jumpr(ctx, RsV, TCG_COND_EQ, LSB); \ 902 } while (0) 903 #define fGEN_TCG_cond_jumprf(COND) \ 904 do { \ 905 TCGv LSB = tcg_temp_new(); \ 906 COND; \ 907 gen_cond_jumpr(ctx, RsV, TCG_COND_NE, LSB); \ 908 } while (0) 909 910 #define fGEN_TCG_J2_jumprt(SHORTCODE) \ 911 fGEN_TCG_cond_jumprt(fLSBOLD(PuV)) 912 #define fGEN_TCG_J2_jumprtpt(SHORTCODE) \ 913 fGEN_TCG_cond_jumprt(fLSBOLD(PuV)) 914 #define fGEN_TCG_J2_jumprf(SHORTCODE) \ 915 fGEN_TCG_cond_jumprf(fLSBOLD(PuV)) 916 #define fGEN_TCG_J2_jumprfpt(SHORTCODE) \ 917 fGEN_TCG_cond_jumprf(fLSBOLD(PuV)) 918 #define fGEN_TCG_J2_jumprtnew(SHORTCODE) \ 919 fGEN_TCG_cond_jumprt(fLSBNEW(PuN)) 920 #define fGEN_TCG_J2_jumprtnewpt(SHORTCODE) \ 921 fGEN_TCG_cond_jumprt(fLSBNEW(PuN)) 922 #define fGEN_TCG_J2_jumprfnew(SHORTCODE) \ 923 fGEN_TCG_cond_jumprf(fLSBNEW(PuN)) 924 #define fGEN_TCG_J2_jumprfnewpt(SHORTCODE) \ 925 fGEN_TCG_cond_jumprf(fLSBNEW(PuN)) 926 927 /* 928 * New value compare & jump instructions 929 * if ([!]COND(r0.new, r1) jump:t address 930 * if ([!]COND(r0.new, #7) jump:t address 931 */ 932 #define fGEN_TCG_J4_cmpgt_t_jumpnv_t(SHORTCODE) \ 933 gen_cmp_jumpnv(ctx, TCG_COND_GT, NsN, RtV, riV) 934 #define fGEN_TCG_J4_cmpgt_t_jumpnv_nt(SHORTCODE) \ 935 gen_cmp_jumpnv(ctx, TCG_COND_GT, NsN, RtV, riV) 936 #define fGEN_TCG_J4_cmpgt_f_jumpnv_t(SHORTCODE) \ 937 gen_cmp_jumpnv(ctx, TCG_COND_LE, NsN, RtV, riV) 938 #define fGEN_TCG_J4_cmpgt_f_jumpnv_nt(SHORTCODE) \ 939 gen_cmp_jumpnv(ctx, TCG_COND_LE, NsN, RtV, riV) 940 941 #define fGEN_TCG_J4_cmpeq_t_jumpnv_t(SHORTCODE) \ 942 gen_cmp_jumpnv(ctx, TCG_COND_EQ, NsN, RtV, riV) 943 #define fGEN_TCG_J4_cmpeq_t_jumpnv_nt(SHORTCODE) \ 944 gen_cmp_jumpnv(ctx, TCG_COND_EQ, NsN, RtV, riV) 945 #define fGEN_TCG_J4_cmpeq_f_jumpnv_t(SHORTCODE) \ 946 gen_cmp_jumpnv(ctx, TCG_COND_NE, NsN, RtV, riV) 947 #define fGEN_TCG_J4_cmpeq_f_jumpnv_nt(SHORTCODE) \ 948 gen_cmp_jumpnv(ctx, TCG_COND_NE, NsN, RtV, riV) 949 950 #define fGEN_TCG_J4_cmplt_t_jumpnv_t(SHORTCODE) \ 951 gen_cmp_jumpnv(ctx, TCG_COND_LT, NsN, RtV, riV) 952 #define fGEN_TCG_J4_cmplt_t_jumpnv_nt(SHORTCODE) \ 953 gen_cmp_jumpnv(ctx, TCG_COND_LT, NsN, RtV, riV) 954 #define fGEN_TCG_J4_cmplt_f_jumpnv_t(SHORTCODE) \ 955 gen_cmp_jumpnv(ctx, TCG_COND_GE, NsN, RtV, riV) 956 #define fGEN_TCG_J4_cmplt_f_jumpnv_nt(SHORTCODE) \ 957 gen_cmp_jumpnv(ctx, TCG_COND_GE, NsN, RtV, riV) 958 959 #define fGEN_TCG_J4_cmpeqi_t_jumpnv_t(SHORTCODE) \ 960 gen_cmpi_jumpnv(ctx, TCG_COND_EQ, NsN, UiV, riV) 961 #define fGEN_TCG_J4_cmpeqi_t_jumpnv_nt(SHORTCODE) \ 962 gen_cmpi_jumpnv(ctx, TCG_COND_EQ, NsN, UiV, riV) 963 #define fGEN_TCG_J4_cmpeqi_f_jumpnv_t(SHORTCODE) \ 964 gen_cmpi_jumpnv(ctx, TCG_COND_NE, NsN, UiV, riV) 965 #define fGEN_TCG_J4_cmpeqi_f_jumpnv_nt(SHORTCODE) \ 966 gen_cmpi_jumpnv(ctx, TCG_COND_NE, NsN, UiV, riV) 967 968 #define fGEN_TCG_J4_cmpgti_t_jumpnv_t(SHORTCODE) \ 969 gen_cmpi_jumpnv(ctx, TCG_COND_GT, NsN, UiV, riV) 970 #define fGEN_TCG_J4_cmpgti_t_jumpnv_nt(SHORTCODE) \ 971 gen_cmpi_jumpnv(ctx, TCG_COND_GT, NsN, UiV, riV) 972 #define fGEN_TCG_J4_cmpgti_f_jumpnv_t(SHORTCODE) \ 973 gen_cmpi_jumpnv(ctx, TCG_COND_LE, NsN, UiV, riV) 974 #define fGEN_TCG_J4_cmpgti_f_jumpnv_nt(SHORTCODE) \ 975 gen_cmpi_jumpnv(ctx, TCG_COND_LE, NsN, UiV, riV) 976 977 #define fGEN_TCG_J4_cmpltu_t_jumpnv_t(SHORTCODE) \ 978 gen_cmp_jumpnv(ctx, TCG_COND_LTU, NsN, RtV, riV) 979 #define fGEN_TCG_J4_cmpltu_t_jumpnv_nt(SHORTCODE) \ 980 gen_cmp_jumpnv(ctx, TCG_COND_LTU, NsN, RtV, riV) 981 #define fGEN_TCG_J4_cmpltu_f_jumpnv_t(SHORTCODE) \ 982 gen_cmp_jumpnv(ctx, TCG_COND_GEU, NsN, RtV, riV) 983 #define fGEN_TCG_J4_cmpltu_f_jumpnv_nt(SHORTCODE) \ 984 gen_cmp_jumpnv(ctx, TCG_COND_GEU, NsN, RtV, riV) 985 986 #define fGEN_TCG_J4_cmpgtui_t_jumpnv_t(SHORTCODE) \ 987 gen_cmpi_jumpnv(ctx, TCG_COND_GTU, NsN, UiV, riV) 988 #define fGEN_TCG_J4_cmpgtui_t_jumpnv_nt(SHORTCODE) \ 989 gen_cmpi_jumpnv(ctx, TCG_COND_GTU, NsN, UiV, riV) 990 #define fGEN_TCG_J4_cmpgtui_f_jumpnv_t(SHORTCODE) \ 991 gen_cmpi_jumpnv(ctx, TCG_COND_LEU, NsN, UiV, riV) 992 #define fGEN_TCG_J4_cmpgtui_f_jumpnv_nt(SHORTCODE) \ 993 gen_cmpi_jumpnv(ctx, TCG_COND_LEU, NsN, UiV, riV) 994 995 #define fGEN_TCG_J4_cmpgtu_t_jumpnv_t(SHORTCODE) \ 996 gen_cmp_jumpnv(ctx, TCG_COND_GTU, NsN, RtV, riV) 997 #define fGEN_TCG_J4_cmpgtu_t_jumpnv_nt(SHORTCODE) \ 998 gen_cmp_jumpnv(ctx, TCG_COND_GTU, NsN, RtV, riV) 999 #define fGEN_TCG_J4_cmpgtu_f_jumpnv_t(SHORTCODE) \ 1000 gen_cmp_jumpnv(ctx, TCG_COND_LEU, NsN, RtV, riV) 1001 #define fGEN_TCG_J4_cmpgtu_f_jumpnv_nt(SHORTCODE) \ 1002 gen_cmp_jumpnv(ctx, TCG_COND_LEU, NsN, RtV, riV) 1003 1004 #define fGEN_TCG_J4_cmpeqn1_t_jumpnv_t(SHORTCODE) \ 1005 gen_cmpi_jumpnv(ctx, TCG_COND_EQ, NsN, -1, riV) 1006 #define fGEN_TCG_J4_cmpeqn1_t_jumpnv_nt(SHORTCODE) \ 1007 gen_cmpi_jumpnv(ctx, TCG_COND_EQ, NsN, -1, riV) 1008 #define fGEN_TCG_J4_cmpeqn1_f_jumpnv_t(SHORTCODE) \ 1009 gen_cmpi_jumpnv(ctx, TCG_COND_NE, NsN, -1, riV) 1010 #define fGEN_TCG_J4_cmpeqn1_f_jumpnv_nt(SHORTCODE) \ 1011 gen_cmpi_jumpnv(ctx, TCG_COND_NE, NsN, -1, riV) 1012 1013 #define fGEN_TCG_J4_cmpgtn1_t_jumpnv_t(SHORTCODE) \ 1014 gen_cmpi_jumpnv(ctx, TCG_COND_GT, NsN, -1, riV) 1015 #define fGEN_TCG_J4_cmpgtn1_t_jumpnv_nt(SHORTCODE) \ 1016 gen_cmpi_jumpnv(ctx, TCG_COND_GT, NsN, -1, riV) 1017 #define fGEN_TCG_J4_cmpgtn1_f_jumpnv_t(SHORTCODE) \ 1018 gen_cmpi_jumpnv(ctx, TCG_COND_LE, NsN, -1, riV) 1019 #define fGEN_TCG_J4_cmpgtn1_f_jumpnv_nt(SHORTCODE) \ 1020 gen_cmpi_jumpnv(ctx, TCG_COND_LE, NsN, -1, riV) 1021 1022 #define fGEN_TCG_J4_tstbit0_t_jumpnv_t(SHORTCODE) \ 1023 gen_testbit0_jumpnv(ctx, NsN, TCG_COND_EQ, riV) 1024 #define fGEN_TCG_J4_tstbit0_t_jumpnv_nt(SHORTCODE) \ 1025 gen_testbit0_jumpnv(ctx, NsN, TCG_COND_EQ, riV) 1026 #define fGEN_TCG_J4_tstbit0_f_jumpnv_t(SHORTCODE) \ 1027 gen_testbit0_jumpnv(ctx, NsN, TCG_COND_NE, riV) 1028 #define fGEN_TCG_J4_tstbit0_f_jumpnv_nt(SHORTCODE) \ 1029 gen_testbit0_jumpnv(ctx, NsN, TCG_COND_NE, riV) 1030 1031 /* r0 = r1 ; jump address */ 1032 #define fGEN_TCG_J4_jumpsetr(SHORTCODE) \ 1033 do { \ 1034 tcg_gen_mov_tl(RdV, RsV); \ 1035 gen_jump(ctx, riV); \ 1036 } while (0) 1037 1038 #define fGEN_TCG_J2_pause(SHORTCODE) \ 1039 do { \ 1040 uiV = uiV; \ 1041 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->next_PC); \ 1042 } while (0) 1043 1044 /* r0 = asr(r1, r2):sat */ 1045 #define fGEN_TCG_S2_asr_r_r_sat(SHORTCODE) \ 1046 gen_asr_r_r_sat(RdV, RsV, RtV) 1047 1048 /* r0 = asl(r1, r2):sat */ 1049 #define fGEN_TCG_S2_asl_r_r_sat(SHORTCODE) \ 1050 gen_asl_r_r_sat(RdV, RsV, RtV) 1051 1052 #define fGEN_TCG_SL2_jumpr31(SHORTCODE) \ 1053 gen_jumpr(ctx, hex_gpr[HEX_REG_LR]) 1054 1055 #define fGEN_TCG_SL2_jumpr31_t(SHORTCODE) \ 1056 gen_cond_jumpr31(ctx, TCG_COND_EQ, hex_pred[0]) 1057 #define fGEN_TCG_SL2_jumpr31_f(SHORTCODE) \ 1058 gen_cond_jumpr31(ctx, TCG_COND_NE, hex_pred[0]) 1059 1060 #define fGEN_TCG_SL2_jumpr31_tnew(SHORTCODE) \ 1061 gen_cond_jumpr31(ctx, TCG_COND_EQ, hex_new_pred_value[0]) 1062 #define fGEN_TCG_SL2_jumpr31_fnew(SHORTCODE) \ 1063 gen_cond_jumpr31(ctx, TCG_COND_NE, hex_new_pred_value[0]) 1064 1065 /* Floating point */ 1066 #define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \ 1067 gen_helper_conv_sf2df(RddV, cpu_env, RsV) 1068 #define fGEN_TCG_F2_conv_df2sf(SHORTCODE) \ 1069 gen_helper_conv_df2sf(RdV, cpu_env, RssV) 1070 #define fGEN_TCG_F2_conv_uw2sf(SHORTCODE) \ 1071 gen_helper_conv_uw2sf(RdV, cpu_env, RsV) 1072 #define fGEN_TCG_F2_conv_uw2df(SHORTCODE) \ 1073 gen_helper_conv_uw2df(RddV, cpu_env, RsV) 1074 #define fGEN_TCG_F2_conv_w2sf(SHORTCODE) \ 1075 gen_helper_conv_w2sf(RdV, cpu_env, RsV) 1076 #define fGEN_TCG_F2_conv_w2df(SHORTCODE) \ 1077 gen_helper_conv_w2df(RddV, cpu_env, RsV) 1078 #define fGEN_TCG_F2_conv_ud2sf(SHORTCODE) \ 1079 gen_helper_conv_ud2sf(RdV, cpu_env, RssV) 1080 #define fGEN_TCG_F2_conv_ud2df(SHORTCODE) \ 1081 gen_helper_conv_ud2df(RddV, cpu_env, RssV) 1082 #define fGEN_TCG_F2_conv_d2sf(SHORTCODE) \ 1083 gen_helper_conv_d2sf(RdV, cpu_env, RssV) 1084 #define fGEN_TCG_F2_conv_d2df(SHORTCODE) \ 1085 gen_helper_conv_d2df(RddV, cpu_env, RssV) 1086 #define fGEN_TCG_F2_conv_sf2uw(SHORTCODE) \ 1087 gen_helper_conv_sf2uw(RdV, cpu_env, RsV) 1088 #define fGEN_TCG_F2_conv_sf2w(SHORTCODE) \ 1089 gen_helper_conv_sf2w(RdV, cpu_env, RsV) 1090 #define fGEN_TCG_F2_conv_sf2ud(SHORTCODE) \ 1091 gen_helper_conv_sf2ud(RddV, cpu_env, RsV) 1092 #define fGEN_TCG_F2_conv_sf2d(SHORTCODE) \ 1093 gen_helper_conv_sf2d(RddV, cpu_env, RsV) 1094 #define fGEN_TCG_F2_conv_df2uw(SHORTCODE) \ 1095 gen_helper_conv_df2uw(RdV, cpu_env, RssV) 1096 #define fGEN_TCG_F2_conv_df2w(SHORTCODE) \ 1097 gen_helper_conv_df2w(RdV, cpu_env, RssV) 1098 #define fGEN_TCG_F2_conv_df2ud(SHORTCODE) \ 1099 gen_helper_conv_df2ud(RddV, cpu_env, RssV) 1100 #define fGEN_TCG_F2_conv_df2d(SHORTCODE) \ 1101 gen_helper_conv_df2d(RddV, cpu_env, RssV) 1102 #define fGEN_TCG_F2_conv_sf2uw_chop(SHORTCODE) \ 1103 gen_helper_conv_sf2uw_chop(RdV, cpu_env, RsV) 1104 #define fGEN_TCG_F2_conv_sf2w_chop(SHORTCODE) \ 1105 gen_helper_conv_sf2w_chop(RdV, cpu_env, RsV) 1106 #define fGEN_TCG_F2_conv_sf2ud_chop(SHORTCODE) \ 1107 gen_helper_conv_sf2ud_chop(RddV, cpu_env, RsV) 1108 #define fGEN_TCG_F2_conv_sf2d_chop(SHORTCODE) \ 1109 gen_helper_conv_sf2d_chop(RddV, cpu_env, RsV) 1110 #define fGEN_TCG_F2_conv_df2uw_chop(SHORTCODE) \ 1111 gen_helper_conv_df2uw_chop(RdV, cpu_env, RssV) 1112 #define fGEN_TCG_F2_conv_df2w_chop(SHORTCODE) \ 1113 gen_helper_conv_df2w_chop(RdV, cpu_env, RssV) 1114 #define fGEN_TCG_F2_conv_df2ud_chop(SHORTCODE) \ 1115 gen_helper_conv_df2ud_chop(RddV, cpu_env, RssV) 1116 #define fGEN_TCG_F2_conv_df2d_chop(SHORTCODE) \ 1117 gen_helper_conv_df2d_chop(RddV, cpu_env, RssV) 1118 #define fGEN_TCG_F2_sfadd(SHORTCODE) \ 1119 gen_helper_sfadd(RdV, cpu_env, RsV, RtV) 1120 #define fGEN_TCG_F2_sfsub(SHORTCODE) \ 1121 gen_helper_sfsub(RdV, cpu_env, RsV, RtV) 1122 #define fGEN_TCG_F2_sfcmpeq(SHORTCODE) \ 1123 gen_helper_sfcmpeq(PdV, cpu_env, RsV, RtV) 1124 #define fGEN_TCG_F2_sfcmpgt(SHORTCODE) \ 1125 gen_helper_sfcmpgt(PdV, cpu_env, RsV, RtV) 1126 #define fGEN_TCG_F2_sfcmpge(SHORTCODE) \ 1127 gen_helper_sfcmpge(PdV, cpu_env, RsV, RtV) 1128 #define fGEN_TCG_F2_sfcmpuo(SHORTCODE) \ 1129 gen_helper_sfcmpuo(PdV, cpu_env, RsV, RtV) 1130 #define fGEN_TCG_F2_sfmax(SHORTCODE) \ 1131 gen_helper_sfmax(RdV, cpu_env, RsV, RtV) 1132 #define fGEN_TCG_F2_sfmin(SHORTCODE) \ 1133 gen_helper_sfmin(RdV, cpu_env, RsV, RtV) 1134 #define fGEN_TCG_F2_sfclass(SHORTCODE) \ 1135 do { \ 1136 TCGv imm = tcg_constant_tl(uiV); \ 1137 gen_helper_sfclass(PdV, cpu_env, RsV, imm); \ 1138 } while (0) 1139 #define fGEN_TCG_F2_sffixupn(SHORTCODE) \ 1140 gen_helper_sffixupn(RdV, cpu_env, RsV, RtV) 1141 #define fGEN_TCG_F2_sffixupd(SHORTCODE) \ 1142 gen_helper_sffixupd(RdV, cpu_env, RsV, RtV) 1143 #define fGEN_TCG_F2_sffixupr(SHORTCODE) \ 1144 gen_helper_sffixupr(RdV, cpu_env, RsV) 1145 #define fGEN_TCG_F2_dfadd(SHORTCODE) \ 1146 gen_helper_dfadd(RddV, cpu_env, RssV, RttV) 1147 #define fGEN_TCG_F2_dfsub(SHORTCODE) \ 1148 gen_helper_dfsub(RddV, cpu_env, RssV, RttV) 1149 #define fGEN_TCG_F2_dfmax(SHORTCODE) \ 1150 gen_helper_dfmax(RddV, cpu_env, RssV, RttV) 1151 #define fGEN_TCG_F2_dfmin(SHORTCODE) \ 1152 gen_helper_dfmin(RddV, cpu_env, RssV, RttV) 1153 #define fGEN_TCG_F2_dfcmpeq(SHORTCODE) \ 1154 gen_helper_dfcmpeq(PdV, cpu_env, RssV, RttV) 1155 #define fGEN_TCG_F2_dfcmpgt(SHORTCODE) \ 1156 gen_helper_dfcmpgt(PdV, cpu_env, RssV, RttV) 1157 #define fGEN_TCG_F2_dfcmpge(SHORTCODE) \ 1158 gen_helper_dfcmpge(PdV, cpu_env, RssV, RttV) 1159 #define fGEN_TCG_F2_dfcmpuo(SHORTCODE) \ 1160 gen_helper_dfcmpuo(PdV, cpu_env, RssV, RttV) 1161 #define fGEN_TCG_F2_dfclass(SHORTCODE) \ 1162 do { \ 1163 TCGv imm = tcg_constant_tl(uiV); \ 1164 gen_helper_dfclass(PdV, cpu_env, RssV, imm); \ 1165 } while (0) 1166 #define fGEN_TCG_F2_sfmpy(SHORTCODE) \ 1167 gen_helper_sfmpy(RdV, cpu_env, RsV, RtV) 1168 #define fGEN_TCG_F2_sffma(SHORTCODE) \ 1169 gen_helper_sffma(RxV, cpu_env, RxV, RsV, RtV) 1170 #define fGEN_TCG_F2_sffma_sc(SHORTCODE) \ 1171 gen_helper_sffma_sc(RxV, cpu_env, RxV, RsV, RtV, PuV) 1172 #define fGEN_TCG_F2_sffms(SHORTCODE) \ 1173 gen_helper_sffms(RxV, cpu_env, RxV, RsV, RtV) 1174 #define fGEN_TCG_F2_sffma_lib(SHORTCODE) \ 1175 gen_helper_sffma_lib(RxV, cpu_env, RxV, RsV, RtV) 1176 #define fGEN_TCG_F2_sffms_lib(SHORTCODE) \ 1177 gen_helper_sffms_lib(RxV, cpu_env, RxV, RsV, RtV) 1178 1179 #define fGEN_TCG_F2_dfmpyfix(SHORTCODE) \ 1180 gen_helper_dfmpyfix(RddV, cpu_env, RssV, RttV) 1181 #define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \ 1182 gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV) 1183 1184 /* Nothing to do for these in qemu, need to suppress compiler warnings */ 1185 #define fGEN_TCG_Y4_l2fetch(SHORTCODE) \ 1186 do { \ 1187 RsV = RsV; \ 1188 RtV = RtV; \ 1189 } while (0) 1190 #define fGEN_TCG_Y5_l2fetch(SHORTCODE) \ 1191 do { \ 1192 RsV = RsV; \ 1193 } while (0) 1194 1195 #define fGEN_TCG_J2_trap0(SHORTCODE) \ 1196 do { \ 1197 uiV = uiV; \ 1198 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->pkt->pc); \ 1199 TCGv excp = tcg_constant_tl(HEX_EXCP_TRAP0); \ 1200 gen_helper_raise_exception(cpu_env, excp); \ 1201 } while (0) 1202 #endif 1203