1f0984d40SFabiano Rosas /* 2f0984d40SFabiano Rosas * ARM translation: AArch32 Neon instructions 3f0984d40SFabiano Rosas * 4f0984d40SFabiano Rosas * Copyright (c) 2003 Fabrice Bellard 5f0984d40SFabiano Rosas * Copyright (c) 2005-2007 CodeSourcery 6f0984d40SFabiano Rosas * Copyright (c) 2007 OpenedHand, Ltd. 7f0984d40SFabiano Rosas * Copyright (c) 2020 Linaro, Ltd. 8f0984d40SFabiano Rosas * 9f0984d40SFabiano Rosas * This library is free software; you can redistribute it and/or 10f0984d40SFabiano Rosas * modify it under the terms of the GNU Lesser General Public 11f0984d40SFabiano Rosas * License as published by the Free Software Foundation; either 12f0984d40SFabiano Rosas * version 2.1 of the License, or (at your option) any later version. 13f0984d40SFabiano Rosas * 14f0984d40SFabiano Rosas * This library is distributed in the hope that it will be useful, 15f0984d40SFabiano Rosas * but WITHOUT ANY WARRANTY; without even the implied warranty of 16f0984d40SFabiano Rosas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17f0984d40SFabiano Rosas * Lesser General Public License for more details. 18f0984d40SFabiano Rosas * 19f0984d40SFabiano Rosas * You should have received a copy of the GNU Lesser General Public 20f0984d40SFabiano Rosas * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21f0984d40SFabiano Rosas */ 22f0984d40SFabiano Rosas 23f0984d40SFabiano Rosas #include "qemu/osdep.h" 24f0984d40SFabiano Rosas #include "translate.h" 25f0984d40SFabiano Rosas #include "translate-a32.h" 26f0984d40SFabiano Rosas 27f0984d40SFabiano Rosas /* Include the generated Neon decoder */ 28f0984d40SFabiano Rosas #include "decode-neon-dp.c.inc" 29f0984d40SFabiano Rosas #include "decode-neon-ls.c.inc" 30f0984d40SFabiano Rosas #include "decode-neon-shared.c.inc" 31f0984d40SFabiano Rosas 32f0984d40SFabiano Rosas static TCGv_ptr vfp_reg_ptr(bool dp, int reg) 33f0984d40SFabiano Rosas { 34f0984d40SFabiano Rosas TCGv_ptr ret = tcg_temp_new_ptr(); 35ad75a51eSRichard Henderson tcg_gen_addi_ptr(ret, tcg_env, vfp_reg_offset(dp, reg)); 36f0984d40SFabiano Rosas return ret; 37f0984d40SFabiano Rosas } 38f0984d40SFabiano Rosas 39f0984d40SFabiano Rosas static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) 40f0984d40SFabiano Rosas { 41f0984d40SFabiano Rosas long offset = neon_element_offset(reg, ele, mop & MO_SIZE); 42f0984d40SFabiano Rosas 43f0984d40SFabiano Rosas switch (mop) { 44f0984d40SFabiano Rosas case MO_UB: 45ad75a51eSRichard Henderson tcg_gen_ld8u_i32(var, tcg_env, offset); 46f0984d40SFabiano Rosas break; 47f0984d40SFabiano Rosas case MO_UW: 48ad75a51eSRichard Henderson tcg_gen_ld16u_i32(var, tcg_env, offset); 49f0984d40SFabiano Rosas break; 50f0984d40SFabiano Rosas case MO_UL: 51ad75a51eSRichard Henderson tcg_gen_ld_i32(var, tcg_env, offset); 52f0984d40SFabiano Rosas break; 53f0984d40SFabiano Rosas default: 54f0984d40SFabiano Rosas g_assert_not_reached(); 55f0984d40SFabiano Rosas } 56f0984d40SFabiano Rosas } 57f0984d40SFabiano Rosas 58f0984d40SFabiano Rosas static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop) 59f0984d40SFabiano Rosas { 60f0984d40SFabiano Rosas long offset = neon_element_offset(reg, ele, mop & MO_SIZE); 61f0984d40SFabiano Rosas 62f0984d40SFabiano Rosas switch (mop) { 63f0984d40SFabiano Rosas case MO_UB: 64ad75a51eSRichard Henderson tcg_gen_ld8u_i64(var, tcg_env, offset); 65f0984d40SFabiano Rosas break; 66f0984d40SFabiano Rosas case MO_UW: 67ad75a51eSRichard Henderson tcg_gen_ld16u_i64(var, tcg_env, offset); 68f0984d40SFabiano Rosas break; 69f0984d40SFabiano Rosas case MO_UL: 70ad75a51eSRichard Henderson tcg_gen_ld32u_i64(var, tcg_env, offset); 71f0984d40SFabiano Rosas break; 72f0984d40SFabiano Rosas case MO_UQ: 73ad75a51eSRichard Henderson tcg_gen_ld_i64(var, tcg_env, offset); 74f0984d40SFabiano Rosas break; 75f0984d40SFabiano Rosas default: 76f0984d40SFabiano Rosas g_assert_not_reached(); 77f0984d40SFabiano Rosas } 78f0984d40SFabiano Rosas } 79f0984d40SFabiano Rosas 80f0984d40SFabiano Rosas static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var) 81f0984d40SFabiano Rosas { 82f0984d40SFabiano Rosas long offset = neon_element_offset(reg, ele, size); 83f0984d40SFabiano Rosas 84f0984d40SFabiano Rosas switch (size) { 85f0984d40SFabiano Rosas case MO_8: 86ad75a51eSRichard Henderson tcg_gen_st8_i32(var, tcg_env, offset); 87f0984d40SFabiano Rosas break; 88f0984d40SFabiano Rosas case MO_16: 89ad75a51eSRichard Henderson tcg_gen_st16_i32(var, tcg_env, offset); 90f0984d40SFabiano Rosas break; 91f0984d40SFabiano Rosas case MO_32: 92ad75a51eSRichard Henderson tcg_gen_st_i32(var, tcg_env, offset); 93f0984d40SFabiano Rosas break; 94f0984d40SFabiano Rosas default: 95f0984d40SFabiano Rosas g_assert_not_reached(); 96f0984d40SFabiano Rosas } 97f0984d40SFabiano Rosas } 98f0984d40SFabiano Rosas 99f0984d40SFabiano Rosas static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 var) 100f0984d40SFabiano Rosas { 101f0984d40SFabiano Rosas long offset = neon_element_offset(reg, ele, size); 102f0984d40SFabiano Rosas 103f0984d40SFabiano Rosas switch (size) { 104f0984d40SFabiano Rosas case MO_8: 105ad75a51eSRichard Henderson tcg_gen_st8_i64(var, tcg_env, offset); 106f0984d40SFabiano Rosas break; 107f0984d40SFabiano Rosas case MO_16: 108ad75a51eSRichard Henderson tcg_gen_st16_i64(var, tcg_env, offset); 109f0984d40SFabiano Rosas break; 110f0984d40SFabiano Rosas case MO_32: 111ad75a51eSRichard Henderson tcg_gen_st32_i64(var, tcg_env, offset); 112f0984d40SFabiano Rosas break; 113f0984d40SFabiano Rosas case MO_64: 114ad75a51eSRichard Henderson tcg_gen_st_i64(var, tcg_env, offset); 115f0984d40SFabiano Rosas break; 116f0984d40SFabiano Rosas default: 117f0984d40SFabiano Rosas g_assert_not_reached(); 118f0984d40SFabiano Rosas } 119f0984d40SFabiano Rosas } 120f0984d40SFabiano Rosas 121f0984d40SFabiano Rosas static bool do_neon_ddda(DisasContext *s, int q, int vd, int vn, int vm, 122f0984d40SFabiano Rosas int data, gen_helper_gvec_4 *fn_gvec) 123f0984d40SFabiano Rosas { 124f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 125f0984d40SFabiano Rosas if (((vd | vn | vm) & 0x10) && !dc_isar_feature(aa32_simd_r32, s)) { 126f0984d40SFabiano Rosas return false; 127f0984d40SFabiano Rosas } 128f0984d40SFabiano Rosas 129f0984d40SFabiano Rosas /* 130f0984d40SFabiano Rosas * UNDEF accesses to odd registers for each bit of Q. 131f0984d40SFabiano Rosas * Q will be 0b111 for all Q-reg instructions, otherwise 132f0984d40SFabiano Rosas * when we have mixed Q- and D-reg inputs. 133f0984d40SFabiano Rosas */ 134f0984d40SFabiano Rosas if (((vd & 1) * 4 | (vn & 1) * 2 | (vm & 1)) & q) { 135f0984d40SFabiano Rosas return false; 136f0984d40SFabiano Rosas } 137f0984d40SFabiano Rosas 138f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 139f0984d40SFabiano Rosas return true; 140f0984d40SFabiano Rosas } 141f0984d40SFabiano Rosas 142f0984d40SFabiano Rosas int opr_sz = q ? 16 : 8; 143f0984d40SFabiano Rosas tcg_gen_gvec_4_ool(vfp_reg_offset(1, vd), 144f0984d40SFabiano Rosas vfp_reg_offset(1, vn), 145f0984d40SFabiano Rosas vfp_reg_offset(1, vm), 146f0984d40SFabiano Rosas vfp_reg_offset(1, vd), 147f0984d40SFabiano Rosas opr_sz, opr_sz, data, fn_gvec); 148f0984d40SFabiano Rosas return true; 149f0984d40SFabiano Rosas } 150f0984d40SFabiano Rosas 151f0984d40SFabiano Rosas static bool do_neon_ddda_fpst(DisasContext *s, int q, int vd, int vn, int vm, 152f0984d40SFabiano Rosas int data, ARMFPStatusFlavour fp_flavour, 153f0984d40SFabiano Rosas gen_helper_gvec_4_ptr *fn_gvec_ptr) 154f0984d40SFabiano Rosas { 155f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 156f0984d40SFabiano Rosas if (((vd | vn | vm) & 0x10) && !dc_isar_feature(aa32_simd_r32, s)) { 157f0984d40SFabiano Rosas return false; 158f0984d40SFabiano Rosas } 159f0984d40SFabiano Rosas 160f0984d40SFabiano Rosas /* 161f0984d40SFabiano Rosas * UNDEF accesses to odd registers for each bit of Q. 162f0984d40SFabiano Rosas * Q will be 0b111 for all Q-reg instructions, otherwise 163f0984d40SFabiano Rosas * when we have mixed Q- and D-reg inputs. 164f0984d40SFabiano Rosas */ 165f0984d40SFabiano Rosas if (((vd & 1) * 4 | (vn & 1) * 2 | (vm & 1)) & q) { 166f0984d40SFabiano Rosas return false; 167f0984d40SFabiano Rosas } 168f0984d40SFabiano Rosas 169f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 170f0984d40SFabiano Rosas return true; 171f0984d40SFabiano Rosas } 172f0984d40SFabiano Rosas 173f0984d40SFabiano Rosas int opr_sz = q ? 16 : 8; 174f0984d40SFabiano Rosas TCGv_ptr fpst = fpstatus_ptr(fp_flavour); 175f0984d40SFabiano Rosas 176f0984d40SFabiano Rosas tcg_gen_gvec_4_ptr(vfp_reg_offset(1, vd), 177f0984d40SFabiano Rosas vfp_reg_offset(1, vn), 178f0984d40SFabiano Rosas vfp_reg_offset(1, vm), 179f0984d40SFabiano Rosas vfp_reg_offset(1, vd), 180f0984d40SFabiano Rosas fpst, opr_sz, opr_sz, data, fn_gvec_ptr); 181f0984d40SFabiano Rosas return true; 182f0984d40SFabiano Rosas } 183f0984d40SFabiano Rosas 184f0984d40SFabiano Rosas static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a) 185f0984d40SFabiano Rosas { 186f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_vcma, s)) { 187f0984d40SFabiano Rosas return false; 188f0984d40SFabiano Rosas } 189f0984d40SFabiano Rosas if (a->size == MO_16) { 190f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_fp16_arith, s)) { 191f0984d40SFabiano Rosas return false; 192f0984d40SFabiano Rosas } 193f0984d40SFabiano Rosas return do_neon_ddda_fpst(s, a->q * 7, a->vd, a->vn, a->vm, a->rot, 194f0984d40SFabiano Rosas FPST_STD_F16, gen_helper_gvec_fcmlah); 195f0984d40SFabiano Rosas } 196f0984d40SFabiano Rosas return do_neon_ddda_fpst(s, a->q * 7, a->vd, a->vn, a->vm, a->rot, 197f0984d40SFabiano Rosas FPST_STD, gen_helper_gvec_fcmlas); 198f0984d40SFabiano Rosas } 199f0984d40SFabiano Rosas 200f0984d40SFabiano Rosas static bool trans_VCADD(DisasContext *s, arg_VCADD *a) 201f0984d40SFabiano Rosas { 202f0984d40SFabiano Rosas int opr_sz; 203f0984d40SFabiano Rosas TCGv_ptr fpst; 204f0984d40SFabiano Rosas gen_helper_gvec_3_ptr *fn_gvec_ptr; 205f0984d40SFabiano Rosas 206f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_vcma, s) 207f0984d40SFabiano Rosas || (a->size == MO_16 && !dc_isar_feature(aa32_fp16_arith, s))) { 208f0984d40SFabiano Rosas return false; 209f0984d40SFabiano Rosas } 210f0984d40SFabiano Rosas 211f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 212f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 213f0984d40SFabiano Rosas ((a->vd | a->vn | a->vm) & 0x10)) { 214f0984d40SFabiano Rosas return false; 215f0984d40SFabiano Rosas } 216f0984d40SFabiano Rosas 217f0984d40SFabiano Rosas if ((a->vn | a->vm | a->vd) & a->q) { 218f0984d40SFabiano Rosas return false; 219f0984d40SFabiano Rosas } 220f0984d40SFabiano Rosas 221f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 222f0984d40SFabiano Rosas return true; 223f0984d40SFabiano Rosas } 224f0984d40SFabiano Rosas 225f0984d40SFabiano Rosas opr_sz = (1 + a->q) * 8; 226f0984d40SFabiano Rosas fpst = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD); 227f0984d40SFabiano Rosas fn_gvec_ptr = (a->size == MO_16) ? 228f0984d40SFabiano Rosas gen_helper_gvec_fcaddh : gen_helper_gvec_fcadds; 229f0984d40SFabiano Rosas tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), 230f0984d40SFabiano Rosas vfp_reg_offset(1, a->vn), 231f0984d40SFabiano Rosas vfp_reg_offset(1, a->vm), 232f0984d40SFabiano Rosas fpst, opr_sz, opr_sz, a->rot, 233f0984d40SFabiano Rosas fn_gvec_ptr); 234f0984d40SFabiano Rosas return true; 235f0984d40SFabiano Rosas } 236f0984d40SFabiano Rosas 237f0984d40SFabiano Rosas static bool trans_VSDOT(DisasContext *s, arg_VSDOT *a) 238f0984d40SFabiano Rosas { 239f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_dp, s)) { 240f0984d40SFabiano Rosas return false; 241f0984d40SFabiano Rosas } 242f0984d40SFabiano Rosas return do_neon_ddda(s, a->q * 7, a->vd, a->vn, a->vm, 0, 243f0984d40SFabiano Rosas gen_helper_gvec_sdot_b); 244f0984d40SFabiano Rosas } 245f0984d40SFabiano Rosas 246f0984d40SFabiano Rosas static bool trans_VUDOT(DisasContext *s, arg_VUDOT *a) 247f0984d40SFabiano Rosas { 248f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_dp, s)) { 249f0984d40SFabiano Rosas return false; 250f0984d40SFabiano Rosas } 251f0984d40SFabiano Rosas return do_neon_ddda(s, a->q * 7, a->vd, a->vn, a->vm, 0, 252f0984d40SFabiano Rosas gen_helper_gvec_udot_b); 253f0984d40SFabiano Rosas } 254f0984d40SFabiano Rosas 255f0984d40SFabiano Rosas static bool trans_VUSDOT(DisasContext *s, arg_VUSDOT *a) 256f0984d40SFabiano Rosas { 257f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_i8mm, s)) { 258f0984d40SFabiano Rosas return false; 259f0984d40SFabiano Rosas } 260f0984d40SFabiano Rosas return do_neon_ddda(s, a->q * 7, a->vd, a->vn, a->vm, 0, 261f0984d40SFabiano Rosas gen_helper_gvec_usdot_b); 262f0984d40SFabiano Rosas } 263f0984d40SFabiano Rosas 264f0984d40SFabiano Rosas static bool trans_VDOT_b16(DisasContext *s, arg_VDOT_b16 *a) 265f0984d40SFabiano Rosas { 266f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_bf16, s)) { 267f0984d40SFabiano Rosas return false; 268f0984d40SFabiano Rosas } 269f0984d40SFabiano Rosas return do_neon_ddda(s, a->q * 7, a->vd, a->vn, a->vm, 0, 270f0984d40SFabiano Rosas gen_helper_gvec_bfdot); 271f0984d40SFabiano Rosas } 272f0984d40SFabiano Rosas 273f0984d40SFabiano Rosas static bool trans_VFML(DisasContext *s, arg_VFML *a) 274f0984d40SFabiano Rosas { 275f0984d40SFabiano Rosas int opr_sz; 276f0984d40SFabiano Rosas 277f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_fhm, s)) { 278f0984d40SFabiano Rosas return false; 279f0984d40SFabiano Rosas } 280f0984d40SFabiano Rosas 281f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 282f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 283f0984d40SFabiano Rosas (a->vd & 0x10)) { 284f0984d40SFabiano Rosas return false; 285f0984d40SFabiano Rosas } 286f0984d40SFabiano Rosas 287f0984d40SFabiano Rosas if (a->vd & a->q) { 288f0984d40SFabiano Rosas return false; 289f0984d40SFabiano Rosas } 290f0984d40SFabiano Rosas 291f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 292f0984d40SFabiano Rosas return true; 293f0984d40SFabiano Rosas } 294f0984d40SFabiano Rosas 295f0984d40SFabiano Rosas opr_sz = (1 + a->q) * 8; 296f0984d40SFabiano Rosas tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), 297f0984d40SFabiano Rosas vfp_reg_offset(a->q, a->vn), 298f0984d40SFabiano Rosas vfp_reg_offset(a->q, a->vm), 299ad75a51eSRichard Henderson tcg_env, opr_sz, opr_sz, a->s, /* is_2 == 0 */ 300f0984d40SFabiano Rosas gen_helper_gvec_fmlal_a32); 301f0984d40SFabiano Rosas return true; 302f0984d40SFabiano Rosas } 303f0984d40SFabiano Rosas 304f0984d40SFabiano Rosas static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a) 305f0984d40SFabiano Rosas { 306f0984d40SFabiano Rosas int data = (a->index << 2) | a->rot; 307f0984d40SFabiano Rosas 308f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_vcma, s)) { 309f0984d40SFabiano Rosas return false; 310f0984d40SFabiano Rosas } 311f0984d40SFabiano Rosas if (a->size == MO_16) { 312f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_fp16_arith, s)) { 313f0984d40SFabiano Rosas return false; 314f0984d40SFabiano Rosas } 315f0984d40SFabiano Rosas return do_neon_ddda_fpst(s, a->q * 6, a->vd, a->vn, a->vm, data, 316f0984d40SFabiano Rosas FPST_STD_F16, gen_helper_gvec_fcmlah_idx); 317f0984d40SFabiano Rosas } 318f0984d40SFabiano Rosas return do_neon_ddda_fpst(s, a->q * 6, a->vd, a->vn, a->vm, data, 319f0984d40SFabiano Rosas FPST_STD, gen_helper_gvec_fcmlas_idx); 320f0984d40SFabiano Rosas } 321f0984d40SFabiano Rosas 322f0984d40SFabiano Rosas static bool trans_VSDOT_scalar(DisasContext *s, arg_VSDOT_scalar *a) 323f0984d40SFabiano Rosas { 324f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_dp, s)) { 325f0984d40SFabiano Rosas return false; 326f0984d40SFabiano Rosas } 327f0984d40SFabiano Rosas return do_neon_ddda(s, a->q * 6, a->vd, a->vn, a->vm, a->index, 328f0984d40SFabiano Rosas gen_helper_gvec_sdot_idx_b); 329f0984d40SFabiano Rosas } 330f0984d40SFabiano Rosas 331f0984d40SFabiano Rosas static bool trans_VUDOT_scalar(DisasContext *s, arg_VUDOT_scalar *a) 332f0984d40SFabiano Rosas { 333f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_dp, s)) { 334f0984d40SFabiano Rosas return false; 335f0984d40SFabiano Rosas } 336f0984d40SFabiano Rosas return do_neon_ddda(s, a->q * 6, a->vd, a->vn, a->vm, a->index, 337f0984d40SFabiano Rosas gen_helper_gvec_udot_idx_b); 338f0984d40SFabiano Rosas } 339f0984d40SFabiano Rosas 340f0984d40SFabiano Rosas static bool trans_VUSDOT_scalar(DisasContext *s, arg_VUSDOT_scalar *a) 341f0984d40SFabiano Rosas { 342f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_i8mm, s)) { 343f0984d40SFabiano Rosas return false; 344f0984d40SFabiano Rosas } 345f0984d40SFabiano Rosas return do_neon_ddda(s, a->q * 6, a->vd, a->vn, a->vm, a->index, 346f0984d40SFabiano Rosas gen_helper_gvec_usdot_idx_b); 347f0984d40SFabiano Rosas } 348f0984d40SFabiano Rosas 349f0984d40SFabiano Rosas static bool trans_VSUDOT_scalar(DisasContext *s, arg_VSUDOT_scalar *a) 350f0984d40SFabiano Rosas { 351f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_i8mm, s)) { 352f0984d40SFabiano Rosas return false; 353f0984d40SFabiano Rosas } 354f0984d40SFabiano Rosas return do_neon_ddda(s, a->q * 6, a->vd, a->vn, a->vm, a->index, 355f0984d40SFabiano Rosas gen_helper_gvec_sudot_idx_b); 356f0984d40SFabiano Rosas } 357f0984d40SFabiano Rosas 358f0984d40SFabiano Rosas static bool trans_VDOT_b16_scal(DisasContext *s, arg_VDOT_b16_scal *a) 359f0984d40SFabiano Rosas { 360f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_bf16, s)) { 361f0984d40SFabiano Rosas return false; 362f0984d40SFabiano Rosas } 363f0984d40SFabiano Rosas return do_neon_ddda(s, a->q * 6, a->vd, a->vn, a->vm, a->index, 364f0984d40SFabiano Rosas gen_helper_gvec_bfdot_idx); 365f0984d40SFabiano Rosas } 366f0984d40SFabiano Rosas 367f0984d40SFabiano Rosas static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a) 368f0984d40SFabiano Rosas { 369f0984d40SFabiano Rosas int opr_sz; 370f0984d40SFabiano Rosas 371f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_fhm, s)) { 372f0984d40SFabiano Rosas return false; 373f0984d40SFabiano Rosas } 374f0984d40SFabiano Rosas 375f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 376f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 377f0984d40SFabiano Rosas ((a->vd & 0x10) || (a->q && (a->vn & 0x10)))) { 378f0984d40SFabiano Rosas return false; 379f0984d40SFabiano Rosas } 380f0984d40SFabiano Rosas 381f0984d40SFabiano Rosas if (a->vd & a->q) { 382f0984d40SFabiano Rosas return false; 383f0984d40SFabiano Rosas } 384f0984d40SFabiano Rosas 385f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 386f0984d40SFabiano Rosas return true; 387f0984d40SFabiano Rosas } 388f0984d40SFabiano Rosas 389f0984d40SFabiano Rosas opr_sz = (1 + a->q) * 8; 390f0984d40SFabiano Rosas tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), 391f0984d40SFabiano Rosas vfp_reg_offset(a->q, a->vn), 392f0984d40SFabiano Rosas vfp_reg_offset(a->q, a->rm), 393ad75a51eSRichard Henderson tcg_env, opr_sz, opr_sz, 394f0984d40SFabiano Rosas (a->index << 2) | a->s, /* is_2 == 0 */ 395f0984d40SFabiano Rosas gen_helper_gvec_fmlal_idx_a32); 396f0984d40SFabiano Rosas return true; 397f0984d40SFabiano Rosas } 398f0984d40SFabiano Rosas 399f0984d40SFabiano Rosas static struct { 400f0984d40SFabiano Rosas int nregs; 401f0984d40SFabiano Rosas int interleave; 402f0984d40SFabiano Rosas int spacing; 403f0984d40SFabiano Rosas } const neon_ls_element_type[11] = { 404f0984d40SFabiano Rosas {1, 4, 1}, 405f0984d40SFabiano Rosas {1, 4, 2}, 406f0984d40SFabiano Rosas {4, 1, 1}, 407f0984d40SFabiano Rosas {2, 2, 2}, 408f0984d40SFabiano Rosas {1, 3, 1}, 409f0984d40SFabiano Rosas {1, 3, 2}, 410f0984d40SFabiano Rosas {3, 1, 1}, 411f0984d40SFabiano Rosas {1, 1, 1}, 412f0984d40SFabiano Rosas {1, 2, 1}, 413f0984d40SFabiano Rosas {1, 2, 2}, 414f0984d40SFabiano Rosas {2, 1, 1} 415f0984d40SFabiano Rosas }; 416f0984d40SFabiano Rosas 417f0984d40SFabiano Rosas static void gen_neon_ldst_base_update(DisasContext *s, int rm, int rn, 418f0984d40SFabiano Rosas int stride) 419f0984d40SFabiano Rosas { 420f0984d40SFabiano Rosas if (rm != 15) { 421f0984d40SFabiano Rosas TCGv_i32 base; 422f0984d40SFabiano Rosas 423f0984d40SFabiano Rosas base = load_reg(s, rn); 424f0984d40SFabiano Rosas if (rm == 13) { 425f0984d40SFabiano Rosas tcg_gen_addi_i32(base, base, stride); 426f0984d40SFabiano Rosas } else { 427f0984d40SFabiano Rosas TCGv_i32 index; 428f0984d40SFabiano Rosas index = load_reg(s, rm); 429f0984d40SFabiano Rosas tcg_gen_add_i32(base, base, index); 430f0984d40SFabiano Rosas } 431f0984d40SFabiano Rosas store_reg(s, rn, base); 432f0984d40SFabiano Rosas } 433f0984d40SFabiano Rosas } 434f0984d40SFabiano Rosas 435f0984d40SFabiano Rosas static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a) 436f0984d40SFabiano Rosas { 437f0984d40SFabiano Rosas /* Neon load/store multiple structures */ 438f0984d40SFabiano Rosas int nregs, interleave, spacing, reg, n; 439f0984d40SFabiano Rosas MemOp mop, align, endian; 440f0984d40SFabiano Rosas int mmu_idx = get_mem_index(s); 441f0984d40SFabiano Rosas int size = a->size; 442f0984d40SFabiano Rosas TCGv_i64 tmp64; 443f0984d40SFabiano Rosas TCGv_i32 addr; 444f0984d40SFabiano Rosas 445f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 446f0984d40SFabiano Rosas return false; 447f0984d40SFabiano Rosas } 448f0984d40SFabiano Rosas 449f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist */ 450f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { 451f0984d40SFabiano Rosas return false; 452f0984d40SFabiano Rosas } 453f0984d40SFabiano Rosas if (a->itype > 10) { 454f0984d40SFabiano Rosas return false; 455f0984d40SFabiano Rosas } 456f0984d40SFabiano Rosas /* Catch UNDEF cases for bad values of align field */ 457f0984d40SFabiano Rosas switch (a->itype & 0xc) { 458f0984d40SFabiano Rosas case 4: 459f0984d40SFabiano Rosas if (a->align >= 2) { 460f0984d40SFabiano Rosas return false; 461f0984d40SFabiano Rosas } 462f0984d40SFabiano Rosas break; 463f0984d40SFabiano Rosas case 8: 464f0984d40SFabiano Rosas if (a->align == 3) { 465f0984d40SFabiano Rosas return false; 466f0984d40SFabiano Rosas } 467f0984d40SFabiano Rosas break; 468f0984d40SFabiano Rosas default: 469f0984d40SFabiano Rosas break; 470f0984d40SFabiano Rosas } 471f0984d40SFabiano Rosas nregs = neon_ls_element_type[a->itype].nregs; 472f0984d40SFabiano Rosas interleave = neon_ls_element_type[a->itype].interleave; 473f0984d40SFabiano Rosas spacing = neon_ls_element_type[a->itype].spacing; 474f0984d40SFabiano Rosas if (size == 3 && (interleave | spacing) != 1) { 475f0984d40SFabiano Rosas return false; 476f0984d40SFabiano Rosas } 477f0984d40SFabiano Rosas 478f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 479f0984d40SFabiano Rosas return true; 480f0984d40SFabiano Rosas } 481f0984d40SFabiano Rosas 482f0984d40SFabiano Rosas /* For our purposes, bytes are always little-endian. */ 483f0984d40SFabiano Rosas endian = s->be_data; 484f0984d40SFabiano Rosas if (size == 0) { 485f0984d40SFabiano Rosas endian = MO_LE; 486f0984d40SFabiano Rosas } 487f0984d40SFabiano Rosas 488f0984d40SFabiano Rosas /* Enforce alignment requested by the instruction */ 489f0984d40SFabiano Rosas if (a->align) { 490f0984d40SFabiano Rosas align = pow2_align(a->align + 2); /* 4 ** a->align */ 491f0984d40SFabiano Rosas } else { 492f0984d40SFabiano Rosas align = s->align_mem ? MO_ALIGN : 0; 493f0984d40SFabiano Rosas } 494f0984d40SFabiano Rosas 495f0984d40SFabiano Rosas /* 496f0984d40SFabiano Rosas * Consecutive little-endian elements from a single register 497f0984d40SFabiano Rosas * can be promoted to a larger little-endian operation. 498f0984d40SFabiano Rosas */ 499f0984d40SFabiano Rosas if (interleave == 1 && endian == MO_LE) { 500f0984d40SFabiano Rosas /* Retain any natural alignment. */ 501f0984d40SFabiano Rosas if (align == MO_ALIGN) { 502f0984d40SFabiano Rosas align = pow2_align(size); 503f0984d40SFabiano Rosas } 504f0984d40SFabiano Rosas size = 3; 505f0984d40SFabiano Rosas } 506f0984d40SFabiano Rosas 507f0984d40SFabiano Rosas tmp64 = tcg_temp_new_i64(); 508f0984d40SFabiano Rosas addr = tcg_temp_new_i32(); 509f0984d40SFabiano Rosas load_reg_var(s, addr, a->rn); 510f0984d40SFabiano Rosas 511f0984d40SFabiano Rosas mop = endian | size | align; 512f0984d40SFabiano Rosas for (reg = 0; reg < nregs; reg++) { 513f0984d40SFabiano Rosas for (n = 0; n < 8 >> size; n++) { 514f0984d40SFabiano Rosas int xs; 515f0984d40SFabiano Rosas for (xs = 0; xs < interleave; xs++) { 516f0984d40SFabiano Rosas int tt = a->vd + reg + spacing * xs; 517f0984d40SFabiano Rosas 518f0984d40SFabiano Rosas if (a->l) { 519f0984d40SFabiano Rosas gen_aa32_ld_internal_i64(s, tmp64, addr, mmu_idx, mop); 520f0984d40SFabiano Rosas neon_store_element64(tt, n, size, tmp64); 521f0984d40SFabiano Rosas } else { 522f0984d40SFabiano Rosas neon_load_element64(tmp64, tt, n, size); 523f0984d40SFabiano Rosas gen_aa32_st_internal_i64(s, tmp64, addr, mmu_idx, mop); 524f0984d40SFabiano Rosas } 525f0984d40SFabiano Rosas tcg_gen_addi_i32(addr, addr, 1 << size); 526f0984d40SFabiano Rosas 527f0984d40SFabiano Rosas /* Subsequent memory operations inherit alignment */ 528f0984d40SFabiano Rosas mop &= ~MO_AMASK; 529f0984d40SFabiano Rosas } 530f0984d40SFabiano Rosas } 531f0984d40SFabiano Rosas } 532f0984d40SFabiano Rosas 533f0984d40SFabiano Rosas gen_neon_ldst_base_update(s, a->rm, a->rn, nregs * interleave * 8); 534f0984d40SFabiano Rosas return true; 535f0984d40SFabiano Rosas } 536f0984d40SFabiano Rosas 537f0984d40SFabiano Rosas static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) 538f0984d40SFabiano Rosas { 539f0984d40SFabiano Rosas /* Neon load single structure to all lanes */ 540f0984d40SFabiano Rosas int reg, stride, vec_size; 541f0984d40SFabiano Rosas int vd = a->vd; 542f0984d40SFabiano Rosas int size = a->size; 543f0984d40SFabiano Rosas int nregs = a->n + 1; 544f0984d40SFabiano Rosas TCGv_i32 addr, tmp; 545f0984d40SFabiano Rosas MemOp mop, align; 546f0984d40SFabiano Rosas 547f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 548f0984d40SFabiano Rosas return false; 549f0984d40SFabiano Rosas } 550f0984d40SFabiano Rosas 551f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist */ 552f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { 553f0984d40SFabiano Rosas return false; 554f0984d40SFabiano Rosas } 555f0984d40SFabiano Rosas 556f0984d40SFabiano Rosas align = 0; 557f0984d40SFabiano Rosas if (size == 3) { 558f0984d40SFabiano Rosas if (nregs != 4 || a->a == 0) { 559f0984d40SFabiano Rosas return false; 560f0984d40SFabiano Rosas } 561f0984d40SFabiano Rosas /* For VLD4 size == 3 a == 1 means 32 bits at 16 byte alignment */ 562f0984d40SFabiano Rosas size = MO_32; 563f0984d40SFabiano Rosas align = MO_ALIGN_16; 564f0984d40SFabiano Rosas } else if (a->a) { 565f0984d40SFabiano Rosas switch (nregs) { 566f0984d40SFabiano Rosas case 1: 567f0984d40SFabiano Rosas if (size == 0) { 568f0984d40SFabiano Rosas return false; 569f0984d40SFabiano Rosas } 570f0984d40SFabiano Rosas align = MO_ALIGN; 571f0984d40SFabiano Rosas break; 572f0984d40SFabiano Rosas case 2: 573f0984d40SFabiano Rosas align = pow2_align(size + 1); 574f0984d40SFabiano Rosas break; 575f0984d40SFabiano Rosas case 3: 576f0984d40SFabiano Rosas return false; 577f0984d40SFabiano Rosas case 4: 578f0984d40SFabiano Rosas if (size == 2) { 579f0984d40SFabiano Rosas align = pow2_align(3); 580f0984d40SFabiano Rosas } else { 581f0984d40SFabiano Rosas align = pow2_align(size + 2); 582f0984d40SFabiano Rosas } 583f0984d40SFabiano Rosas break; 584f0984d40SFabiano Rosas default: 585f0984d40SFabiano Rosas g_assert_not_reached(); 586f0984d40SFabiano Rosas } 587f0984d40SFabiano Rosas } 588f0984d40SFabiano Rosas 589f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 590f0984d40SFabiano Rosas return true; 591f0984d40SFabiano Rosas } 592f0984d40SFabiano Rosas 593f0984d40SFabiano Rosas /* 594f0984d40SFabiano Rosas * VLD1 to all lanes: T bit indicates how many Dregs to write. 595f0984d40SFabiano Rosas * VLD2/3/4 to all lanes: T bit indicates register stride. 596f0984d40SFabiano Rosas */ 597f0984d40SFabiano Rosas stride = a->t ? 2 : 1; 598f0984d40SFabiano Rosas vec_size = nregs == 1 ? stride * 8 : 8; 599f0984d40SFabiano Rosas mop = size | align; 600f0984d40SFabiano Rosas tmp = tcg_temp_new_i32(); 601f0984d40SFabiano Rosas addr = tcg_temp_new_i32(); 602f0984d40SFabiano Rosas load_reg_var(s, addr, a->rn); 603f0984d40SFabiano Rosas for (reg = 0; reg < nregs; reg++) { 604f0984d40SFabiano Rosas gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop); 605f0984d40SFabiano Rosas if ((vd & 1) && vec_size == 16) { 606f0984d40SFabiano Rosas /* 607f0984d40SFabiano Rosas * We cannot write 16 bytes at once because the 608f0984d40SFabiano Rosas * destination is unaligned. 609f0984d40SFabiano Rosas */ 610f0984d40SFabiano Rosas tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd), 611f0984d40SFabiano Rosas 8, 8, tmp); 612f0984d40SFabiano Rosas tcg_gen_gvec_mov(0, neon_full_reg_offset(vd + 1), 613f0984d40SFabiano Rosas neon_full_reg_offset(vd), 8, 8); 614f0984d40SFabiano Rosas } else { 615f0984d40SFabiano Rosas tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd), 616f0984d40SFabiano Rosas vec_size, vec_size, tmp); 617f0984d40SFabiano Rosas } 618f0984d40SFabiano Rosas tcg_gen_addi_i32(addr, addr, 1 << size); 619f0984d40SFabiano Rosas vd += stride; 620f0984d40SFabiano Rosas 621f0984d40SFabiano Rosas /* Subsequent memory operations inherit alignment */ 622f0984d40SFabiano Rosas mop &= ~MO_AMASK; 623f0984d40SFabiano Rosas } 624f0984d40SFabiano Rosas 625f0984d40SFabiano Rosas gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << size) * nregs); 626f0984d40SFabiano Rosas 627f0984d40SFabiano Rosas return true; 628f0984d40SFabiano Rosas } 629f0984d40SFabiano Rosas 630f0984d40SFabiano Rosas static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) 631f0984d40SFabiano Rosas { 632f0984d40SFabiano Rosas /* Neon load/store single structure to one lane */ 633f0984d40SFabiano Rosas int reg; 634f0984d40SFabiano Rosas int nregs = a->n + 1; 635f0984d40SFabiano Rosas int vd = a->vd; 636f0984d40SFabiano Rosas TCGv_i32 addr, tmp; 637f0984d40SFabiano Rosas MemOp mop; 638f0984d40SFabiano Rosas 639f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 640f0984d40SFabiano Rosas return false; 641f0984d40SFabiano Rosas } 642f0984d40SFabiano Rosas 643f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist */ 644f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { 645f0984d40SFabiano Rosas return false; 646f0984d40SFabiano Rosas } 647f0984d40SFabiano Rosas 648f0984d40SFabiano Rosas /* Catch the UNDEF cases. This is unavoidably a bit messy. */ 649f0984d40SFabiano Rosas switch (nregs) { 650f0984d40SFabiano Rosas case 1: 651f0984d40SFabiano Rosas if (a->stride != 1) { 652f0984d40SFabiano Rosas return false; 653f0984d40SFabiano Rosas } 654f0984d40SFabiano Rosas if (((a->align & (1 << a->size)) != 0) || 655f0984d40SFabiano Rosas (a->size == 2 && (a->align == 1 || a->align == 2))) { 656f0984d40SFabiano Rosas return false; 657f0984d40SFabiano Rosas } 658f0984d40SFabiano Rosas break; 659f0984d40SFabiano Rosas case 2: 660f0984d40SFabiano Rosas if (a->size == 2 && (a->align & 2) != 0) { 661f0984d40SFabiano Rosas return false; 662f0984d40SFabiano Rosas } 663f0984d40SFabiano Rosas break; 664f0984d40SFabiano Rosas case 3: 665f0984d40SFabiano Rosas if (a->align != 0) { 666f0984d40SFabiano Rosas return false; 667f0984d40SFabiano Rosas } 668f0984d40SFabiano Rosas break; 669f0984d40SFabiano Rosas case 4: 670f0984d40SFabiano Rosas if (a->size == 2 && a->align == 3) { 671f0984d40SFabiano Rosas return false; 672f0984d40SFabiano Rosas } 673f0984d40SFabiano Rosas break; 674f0984d40SFabiano Rosas default: 675f0984d40SFabiano Rosas g_assert_not_reached(); 676f0984d40SFabiano Rosas } 677f0984d40SFabiano Rosas if ((vd + a->stride * (nregs - 1)) > 31) { 678f0984d40SFabiano Rosas /* 679f0984d40SFabiano Rosas * Attempts to write off the end of the register file are 680f0984d40SFabiano Rosas * UNPREDICTABLE; we choose to UNDEF because otherwise we would 681f0984d40SFabiano Rosas * access off the end of the array that holds the register data. 682f0984d40SFabiano Rosas */ 683f0984d40SFabiano Rosas return false; 684f0984d40SFabiano Rosas } 685f0984d40SFabiano Rosas 686f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 687f0984d40SFabiano Rosas return true; 688f0984d40SFabiano Rosas } 689f0984d40SFabiano Rosas 690f0984d40SFabiano Rosas /* Pick up SCTLR settings */ 691f0984d40SFabiano Rosas mop = finalize_memop(s, a->size); 692f0984d40SFabiano Rosas 693f0984d40SFabiano Rosas if (a->align) { 694f0984d40SFabiano Rosas MemOp align_op; 695f0984d40SFabiano Rosas 696f0984d40SFabiano Rosas switch (nregs) { 697f0984d40SFabiano Rosas case 1: 698f0984d40SFabiano Rosas /* For VLD1, use natural alignment. */ 699f0984d40SFabiano Rosas align_op = MO_ALIGN; 700f0984d40SFabiano Rosas break; 701f0984d40SFabiano Rosas case 2: 702f0984d40SFabiano Rosas /* For VLD2, use double alignment. */ 703f0984d40SFabiano Rosas align_op = pow2_align(a->size + 1); 704f0984d40SFabiano Rosas break; 705f0984d40SFabiano Rosas case 4: 706f0984d40SFabiano Rosas if (a->size == MO_32) { 707f0984d40SFabiano Rosas /* 708f0984d40SFabiano Rosas * For VLD4.32, align = 1 is double alignment, align = 2 is 709f0984d40SFabiano Rosas * quad alignment; align = 3 is rejected above. 710f0984d40SFabiano Rosas */ 711f0984d40SFabiano Rosas align_op = pow2_align(a->size + a->align); 712f0984d40SFabiano Rosas } else { 713f0984d40SFabiano Rosas /* For VLD4.8 and VLD.16, we want quad alignment. */ 714f0984d40SFabiano Rosas align_op = pow2_align(a->size + 2); 715f0984d40SFabiano Rosas } 716f0984d40SFabiano Rosas break; 717f0984d40SFabiano Rosas default: 718f0984d40SFabiano Rosas /* For VLD3, the alignment field is zero and rejected above. */ 719f0984d40SFabiano Rosas g_assert_not_reached(); 720f0984d40SFabiano Rosas } 721f0984d40SFabiano Rosas 722f0984d40SFabiano Rosas mop = (mop & ~MO_AMASK) | align_op; 723f0984d40SFabiano Rosas } 724f0984d40SFabiano Rosas 725f0984d40SFabiano Rosas tmp = tcg_temp_new_i32(); 726f0984d40SFabiano Rosas addr = tcg_temp_new_i32(); 727f0984d40SFabiano Rosas load_reg_var(s, addr, a->rn); 728f0984d40SFabiano Rosas 729f0984d40SFabiano Rosas for (reg = 0; reg < nregs; reg++) { 730f0984d40SFabiano Rosas if (a->l) { 731f0984d40SFabiano Rosas gen_aa32_ld_internal_i32(s, tmp, addr, get_mem_index(s), mop); 732f0984d40SFabiano Rosas neon_store_element(vd, a->reg_idx, a->size, tmp); 733f0984d40SFabiano Rosas } else { /* Store */ 734f0984d40SFabiano Rosas neon_load_element(tmp, vd, a->reg_idx, a->size); 735f0984d40SFabiano Rosas gen_aa32_st_internal_i32(s, tmp, addr, get_mem_index(s), mop); 736f0984d40SFabiano Rosas } 737f0984d40SFabiano Rosas vd += a->stride; 738f0984d40SFabiano Rosas tcg_gen_addi_i32(addr, addr, 1 << a->size); 739f0984d40SFabiano Rosas 740f0984d40SFabiano Rosas /* Subsequent memory operations inherit alignment */ 741f0984d40SFabiano Rosas mop &= ~MO_AMASK; 742f0984d40SFabiano Rosas } 743f0984d40SFabiano Rosas 744f0984d40SFabiano Rosas gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << a->size) * nregs); 745f0984d40SFabiano Rosas 746f0984d40SFabiano Rosas return true; 747f0984d40SFabiano Rosas } 748f0984d40SFabiano Rosas 749f0984d40SFabiano Rosas static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn) 750f0984d40SFabiano Rosas { 751f0984d40SFabiano Rosas int vec_size = a->q ? 16 : 8; 752f0984d40SFabiano Rosas int rd_ofs = neon_full_reg_offset(a->vd); 753f0984d40SFabiano Rosas int rn_ofs = neon_full_reg_offset(a->vn); 754f0984d40SFabiano Rosas int rm_ofs = neon_full_reg_offset(a->vm); 755f0984d40SFabiano Rosas 756f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 757f0984d40SFabiano Rosas return false; 758f0984d40SFabiano Rosas } 759f0984d40SFabiano Rosas 760f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 761f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 762f0984d40SFabiano Rosas ((a->vd | a->vn | a->vm) & 0x10)) { 763f0984d40SFabiano Rosas return false; 764f0984d40SFabiano Rosas } 765f0984d40SFabiano Rosas 766f0984d40SFabiano Rosas if ((a->vn | a->vm | a->vd) & a->q) { 767f0984d40SFabiano Rosas return false; 768f0984d40SFabiano Rosas } 769f0984d40SFabiano Rosas 770f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 771f0984d40SFabiano Rosas return true; 772f0984d40SFabiano Rosas } 773f0984d40SFabiano Rosas 774f0984d40SFabiano Rosas fn(a->size, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size); 775f0984d40SFabiano Rosas return true; 776f0984d40SFabiano Rosas } 777f0984d40SFabiano Rosas 778f0984d40SFabiano Rosas #define DO_3SAME(INSN, FUNC) \ 779f0984d40SFabiano Rosas static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ 780f0984d40SFabiano Rosas { \ 781f0984d40SFabiano Rosas return do_3same(s, a, FUNC); \ 782f0984d40SFabiano Rosas } 783f0984d40SFabiano Rosas 784f0984d40SFabiano Rosas DO_3SAME(VADD, tcg_gen_gvec_add) 785f0984d40SFabiano Rosas DO_3SAME(VSUB, tcg_gen_gvec_sub) 786f0984d40SFabiano Rosas DO_3SAME(VAND, tcg_gen_gvec_and) 787f0984d40SFabiano Rosas DO_3SAME(VBIC, tcg_gen_gvec_andc) 788f0984d40SFabiano Rosas DO_3SAME(VORR, tcg_gen_gvec_or) 789f0984d40SFabiano Rosas DO_3SAME(VORN, tcg_gen_gvec_orc) 790f0984d40SFabiano Rosas DO_3SAME(VEOR, tcg_gen_gvec_xor) 791f0984d40SFabiano Rosas DO_3SAME(VSHL_S, gen_gvec_sshl) 792f0984d40SFabiano Rosas DO_3SAME(VSHL_U, gen_gvec_ushl) 793f0984d40SFabiano Rosas DO_3SAME(VQADD_S, gen_gvec_sqadd_qc) 794f0984d40SFabiano Rosas DO_3SAME(VQADD_U, gen_gvec_uqadd_qc) 795f0984d40SFabiano Rosas DO_3SAME(VQSUB_S, gen_gvec_sqsub_qc) 796f0984d40SFabiano Rosas DO_3SAME(VQSUB_U, gen_gvec_uqsub_qc) 797940392c8SRichard Henderson DO_3SAME(VRSHL_S, gen_gvec_srshl) 798940392c8SRichard Henderson DO_3SAME(VRSHL_U, gen_gvec_urshl) 799e72a6878SRichard Henderson DO_3SAME(VQSHL_S, gen_neon_sqshl) 800e72a6878SRichard Henderson DO_3SAME(VQSHL_U, gen_neon_uqshl) 801cef9d54fSRichard Henderson DO_3SAME(VQRSHL_S, gen_neon_sqrshl) 802cef9d54fSRichard Henderson DO_3SAME(VQRSHL_U, gen_neon_uqrshl) 803f0984d40SFabiano Rosas 804f0984d40SFabiano Rosas /* These insns are all gvec_bitsel but with the inputs in various orders. */ 805f0984d40SFabiano Rosas #define DO_3SAME_BITSEL(INSN, O1, O2, O3) \ 806f0984d40SFabiano Rosas static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ 807f0984d40SFabiano Rosas uint32_t rn_ofs, uint32_t rm_ofs, \ 808f0984d40SFabiano Rosas uint32_t oprsz, uint32_t maxsz) \ 809f0984d40SFabiano Rosas { \ 810f0984d40SFabiano Rosas tcg_gen_gvec_bitsel(vece, rd_ofs, O1, O2, O3, oprsz, maxsz); \ 811f0984d40SFabiano Rosas } \ 812f0984d40SFabiano Rosas DO_3SAME(INSN, gen_##INSN##_3s) 813f0984d40SFabiano Rosas 814f0984d40SFabiano Rosas DO_3SAME_BITSEL(VBSL, rd_ofs, rn_ofs, rm_ofs) 815f0984d40SFabiano Rosas DO_3SAME_BITSEL(VBIT, rm_ofs, rn_ofs, rd_ofs) 816f0984d40SFabiano Rosas DO_3SAME_BITSEL(VBIF, rm_ofs, rd_ofs, rn_ofs) 817f0984d40SFabiano Rosas 818f0984d40SFabiano Rosas #define DO_3SAME_NO_SZ_3(INSN, FUNC) \ 819f0984d40SFabiano Rosas static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ 820f0984d40SFabiano Rosas { \ 821f0984d40SFabiano Rosas if (a->size == 3) { \ 822f0984d40SFabiano Rosas return false; \ 823f0984d40SFabiano Rosas } \ 824f0984d40SFabiano Rosas return do_3same(s, a, FUNC); \ 825f0984d40SFabiano Rosas } 826f0984d40SFabiano Rosas 827f0984d40SFabiano Rosas DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax) 828f0984d40SFabiano Rosas DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax) 829f0984d40SFabiano Rosas DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin) 830f0984d40SFabiano Rosas DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin) 831f0984d40SFabiano Rosas DO_3SAME_NO_SZ_3(VMUL, tcg_gen_gvec_mul) 832f0984d40SFabiano Rosas DO_3SAME_NO_SZ_3(VMLA, gen_gvec_mla) 833f0984d40SFabiano Rosas DO_3SAME_NO_SZ_3(VMLS, gen_gvec_mls) 834f0984d40SFabiano Rosas DO_3SAME_NO_SZ_3(VTST, gen_gvec_cmtst) 835f0984d40SFabiano Rosas DO_3SAME_NO_SZ_3(VABD_S, gen_gvec_sabd) 836f0984d40SFabiano Rosas DO_3SAME_NO_SZ_3(VABA_S, gen_gvec_saba) 837f0984d40SFabiano Rosas DO_3SAME_NO_SZ_3(VABD_U, gen_gvec_uabd) 838f0984d40SFabiano Rosas DO_3SAME_NO_SZ_3(VABA_U, gen_gvec_uaba) 839a11e54edSRichard Henderson DO_3SAME_NO_SZ_3(VPADD, gen_gvec_addp) 840a9240f48SRichard Henderson DO_3SAME_NO_SZ_3(VPMAX_S, gen_gvec_smaxp) 841a9240f48SRichard Henderson DO_3SAME_NO_SZ_3(VPMIN_S, gen_gvec_sminp) 842a9240f48SRichard Henderson DO_3SAME_NO_SZ_3(VPMAX_U, gen_gvec_umaxp) 843a9240f48SRichard Henderson DO_3SAME_NO_SZ_3(VPMIN_U, gen_gvec_uminp) 844203aca91SRichard Henderson DO_3SAME_NO_SZ_3(VHADD_S, gen_gvec_shadd) 845203aca91SRichard Henderson DO_3SAME_NO_SZ_3(VHADD_U, gen_gvec_uhadd) 846*34c0d865SRichard Henderson DO_3SAME_NO_SZ_3(VHSUB_S, gen_gvec_shsub) 847*34c0d865SRichard Henderson DO_3SAME_NO_SZ_3(VHSUB_U, gen_gvec_uhsub) 848f0984d40SFabiano Rosas 849f0984d40SFabiano Rosas #define DO_3SAME_CMP(INSN, COND) \ 850f0984d40SFabiano Rosas static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ 851f0984d40SFabiano Rosas uint32_t rn_ofs, uint32_t rm_ofs, \ 852f0984d40SFabiano Rosas uint32_t oprsz, uint32_t maxsz) \ 853f0984d40SFabiano Rosas { \ 854f0984d40SFabiano Rosas tcg_gen_gvec_cmp(COND, vece, rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz); \ 855f0984d40SFabiano Rosas } \ 856f0984d40SFabiano Rosas DO_3SAME_NO_SZ_3(INSN, gen_##INSN##_3s) 857f0984d40SFabiano Rosas 858f0984d40SFabiano Rosas DO_3SAME_CMP(VCGT_S, TCG_COND_GT) 859f0984d40SFabiano Rosas DO_3SAME_CMP(VCGT_U, TCG_COND_GTU) 860f0984d40SFabiano Rosas DO_3SAME_CMP(VCGE_S, TCG_COND_GE) 861f0984d40SFabiano Rosas DO_3SAME_CMP(VCGE_U, TCG_COND_GEU) 862f0984d40SFabiano Rosas DO_3SAME_CMP(VCEQ, TCG_COND_EQ) 863f0984d40SFabiano Rosas 864f0984d40SFabiano Rosas #define WRAP_OOL_FN(WRAPNAME, FUNC) \ 865f0984d40SFabiano Rosas static void WRAPNAME(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, \ 866f0984d40SFabiano Rosas uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz) \ 867f0984d40SFabiano Rosas { \ 868f0984d40SFabiano Rosas tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, 0, FUNC); \ 869f0984d40SFabiano Rosas } 870f0984d40SFabiano Rosas 871f0984d40SFabiano Rosas WRAP_OOL_FN(gen_VMUL_p_3s, gen_helper_gvec_pmul_b) 872f0984d40SFabiano Rosas 873f0984d40SFabiano Rosas static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a) 874f0984d40SFabiano Rosas { 875f0984d40SFabiano Rosas if (a->size != 0) { 876f0984d40SFabiano Rosas return false; 877f0984d40SFabiano Rosas } 878f0984d40SFabiano Rosas return do_3same(s, a, gen_VMUL_p_3s); 879f0984d40SFabiano Rosas } 880f0984d40SFabiano Rosas 881f0984d40SFabiano Rosas #define DO_VQRDMLAH(INSN, FUNC) \ 882f0984d40SFabiano Rosas static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ 883f0984d40SFabiano Rosas { \ 884f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_rdm, s)) { \ 885f0984d40SFabiano Rosas return false; \ 886f0984d40SFabiano Rosas } \ 887f0984d40SFabiano Rosas if (a->size != 1 && a->size != 2) { \ 888f0984d40SFabiano Rosas return false; \ 889f0984d40SFabiano Rosas } \ 890f0984d40SFabiano Rosas return do_3same(s, a, FUNC); \ 891f0984d40SFabiano Rosas } 892f0984d40SFabiano Rosas 893f0984d40SFabiano Rosas DO_VQRDMLAH(VQRDMLAH, gen_gvec_sqrdmlah_qc) 894f0984d40SFabiano Rosas DO_VQRDMLAH(VQRDMLSH, gen_gvec_sqrdmlsh_qc) 895f0984d40SFabiano Rosas 896f0984d40SFabiano Rosas #define DO_SHA1(NAME, FUNC) \ 897f0984d40SFabiano Rosas WRAP_OOL_FN(gen_##NAME##_3s, FUNC) \ 898f0984d40SFabiano Rosas static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a) \ 899f0984d40SFabiano Rosas { \ 900f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_sha1, s)) { \ 901f0984d40SFabiano Rosas return false; \ 902f0984d40SFabiano Rosas } \ 903f0984d40SFabiano Rosas return do_3same(s, a, gen_##NAME##_3s); \ 904f0984d40SFabiano Rosas } 905f0984d40SFabiano Rosas 906f0984d40SFabiano Rosas DO_SHA1(SHA1C, gen_helper_crypto_sha1c) 907f0984d40SFabiano Rosas DO_SHA1(SHA1P, gen_helper_crypto_sha1p) 908f0984d40SFabiano Rosas DO_SHA1(SHA1M, gen_helper_crypto_sha1m) 909f0984d40SFabiano Rosas DO_SHA1(SHA1SU0, gen_helper_crypto_sha1su0) 910f0984d40SFabiano Rosas 911f0984d40SFabiano Rosas #define DO_SHA2(NAME, FUNC) \ 912f0984d40SFabiano Rosas WRAP_OOL_FN(gen_##NAME##_3s, FUNC) \ 913f0984d40SFabiano Rosas static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a) \ 914f0984d40SFabiano Rosas { \ 915f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_sha2, s)) { \ 916f0984d40SFabiano Rosas return false; \ 917f0984d40SFabiano Rosas } \ 918f0984d40SFabiano Rosas return do_3same(s, a, gen_##NAME##_3s); \ 919f0984d40SFabiano Rosas } 920f0984d40SFabiano Rosas 921f0984d40SFabiano Rosas DO_SHA2(SHA256H, gen_helper_crypto_sha256h) 922f0984d40SFabiano Rosas DO_SHA2(SHA256H2, gen_helper_crypto_sha256h2) 923f0984d40SFabiano Rosas DO_SHA2(SHA256SU1, gen_helper_crypto_sha256su1) 924f0984d40SFabiano Rosas 925f0984d40SFabiano Rosas #define DO_3SAME_32(INSN, FUNC) \ 926f0984d40SFabiano Rosas static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ 927f0984d40SFabiano Rosas uint32_t rn_ofs, uint32_t rm_ofs, \ 928f0984d40SFabiano Rosas uint32_t oprsz, uint32_t maxsz) \ 929f0984d40SFabiano Rosas { \ 930f0984d40SFabiano Rosas static const GVecGen3 ops[4] = { \ 931f0984d40SFabiano Rosas { .fni4 = gen_helper_neon_##FUNC##8 }, \ 932f0984d40SFabiano Rosas { .fni4 = gen_helper_neon_##FUNC##16 }, \ 933f0984d40SFabiano Rosas { .fni4 = gen_helper_neon_##FUNC##32 }, \ 934f0984d40SFabiano Rosas { 0 }, \ 935f0984d40SFabiano Rosas }; \ 936f0984d40SFabiano Rosas tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops[vece]); \ 937f0984d40SFabiano Rosas } \ 938f0984d40SFabiano Rosas static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ 939f0984d40SFabiano Rosas { \ 940f0984d40SFabiano Rosas if (a->size > 2) { \ 941f0984d40SFabiano Rosas return false; \ 942f0984d40SFabiano Rosas } \ 943f0984d40SFabiano Rosas return do_3same(s, a, gen_##INSN##_3s); \ 944f0984d40SFabiano Rosas } 945f0984d40SFabiano Rosas 946f0984d40SFabiano Rosas /* 947ad75a51eSRichard Henderson * Some helper functions need to be passed the tcg_env. In order 948f0984d40SFabiano Rosas * to use those with the gvec APIs like tcg_gen_gvec_3() we need 949f0984d40SFabiano Rosas * to create wrapper functions whose prototype is a NeonGenTwoOpFn() 950f0984d40SFabiano Rosas * and which call a NeonGenTwoOpEnvFn(). 951f0984d40SFabiano Rosas */ 952f0984d40SFabiano Rosas #define WRAP_ENV_FN(WRAPNAME, FUNC) \ 953f0984d40SFabiano Rosas static void WRAPNAME(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m) \ 954f0984d40SFabiano Rosas { \ 955ad75a51eSRichard Henderson FUNC(d, tcg_env, n, m); \ 956f0984d40SFabiano Rosas } 957f0984d40SFabiano Rosas 958f0984d40SFabiano Rosas DO_3SAME_32(VRHADD_S, rhadd_s) 959f0984d40SFabiano Rosas DO_3SAME_32(VRHADD_U, rhadd_u) 960f0984d40SFabiano Rosas 961f0984d40SFabiano Rosas #define DO_3SAME_VQDMULH(INSN, FUNC) \ 962f0984d40SFabiano Rosas WRAP_ENV_FN(gen_##INSN##_tramp16, gen_helper_neon_##FUNC##_s16); \ 963f0984d40SFabiano Rosas WRAP_ENV_FN(gen_##INSN##_tramp32, gen_helper_neon_##FUNC##_s32); \ 964f0984d40SFabiano Rosas static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ 965f0984d40SFabiano Rosas uint32_t rn_ofs, uint32_t rm_ofs, \ 966f0984d40SFabiano Rosas uint32_t oprsz, uint32_t maxsz) \ 967f0984d40SFabiano Rosas { \ 968f0984d40SFabiano Rosas static const GVecGen3 ops[2] = { \ 969f0984d40SFabiano Rosas { .fni4 = gen_##INSN##_tramp16 }, \ 970f0984d40SFabiano Rosas { .fni4 = gen_##INSN##_tramp32 }, \ 971f0984d40SFabiano Rosas }; \ 972f0984d40SFabiano Rosas tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops[vece - 1]); \ 973f0984d40SFabiano Rosas } \ 974f0984d40SFabiano Rosas static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ 975f0984d40SFabiano Rosas { \ 976f0984d40SFabiano Rosas if (a->size != 1 && a->size != 2) { \ 977f0984d40SFabiano Rosas return false; \ 978f0984d40SFabiano Rosas } \ 979f0984d40SFabiano Rosas return do_3same(s, a, gen_##INSN##_3s); \ 980f0984d40SFabiano Rosas } 981f0984d40SFabiano Rosas 982f0984d40SFabiano Rosas DO_3SAME_VQDMULH(VQDMULH, qdmulh) 983f0984d40SFabiano Rosas DO_3SAME_VQDMULH(VQRDMULH, qrdmulh) 984f0984d40SFabiano Rosas 985f0984d40SFabiano Rosas #define WRAP_FP_GVEC(WRAPNAME, FPST, FUNC) \ 986f0984d40SFabiano Rosas static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \ 987f0984d40SFabiano Rosas uint32_t rn_ofs, uint32_t rm_ofs, \ 988f0984d40SFabiano Rosas uint32_t oprsz, uint32_t maxsz) \ 989f0984d40SFabiano Rosas { \ 990f0984d40SFabiano Rosas TCGv_ptr fpst = fpstatus_ptr(FPST); \ 991f0984d40SFabiano Rosas tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpst, \ 992f0984d40SFabiano Rosas oprsz, maxsz, 0, FUNC); \ 993f0984d40SFabiano Rosas } 994f0984d40SFabiano Rosas 995f0984d40SFabiano Rosas #define DO_3S_FP_GVEC(INSN,SFUNC,HFUNC) \ 996f0984d40SFabiano Rosas WRAP_FP_GVEC(gen_##INSN##_fp32_3s, FPST_STD, SFUNC) \ 997f0984d40SFabiano Rosas WRAP_FP_GVEC(gen_##INSN##_fp16_3s, FPST_STD_F16, HFUNC) \ 998f0984d40SFabiano Rosas static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \ 999f0984d40SFabiano Rosas { \ 1000f0984d40SFabiano Rosas if (a->size == MO_16) { \ 1001f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_fp16_arith, s)) { \ 1002f0984d40SFabiano Rosas return false; \ 1003f0984d40SFabiano Rosas } \ 1004f0984d40SFabiano Rosas return do_3same(s, a, gen_##INSN##_fp16_3s); \ 1005f0984d40SFabiano Rosas } \ 1006f0984d40SFabiano Rosas return do_3same(s, a, gen_##INSN##_fp32_3s); \ 1007f0984d40SFabiano Rosas } 1008f0984d40SFabiano Rosas 1009f0984d40SFabiano Rosas 1010f0984d40SFabiano Rosas DO_3S_FP_GVEC(VADD, gen_helper_gvec_fadd_s, gen_helper_gvec_fadd_h) 1011f0984d40SFabiano Rosas DO_3S_FP_GVEC(VSUB, gen_helper_gvec_fsub_s, gen_helper_gvec_fsub_h) 1012f0984d40SFabiano Rosas DO_3S_FP_GVEC(VABD, gen_helper_gvec_fabd_s, gen_helper_gvec_fabd_h) 1013f0984d40SFabiano Rosas DO_3S_FP_GVEC(VMUL, gen_helper_gvec_fmul_s, gen_helper_gvec_fmul_h) 1014f0984d40SFabiano Rosas DO_3S_FP_GVEC(VCEQ, gen_helper_gvec_fceq_s, gen_helper_gvec_fceq_h) 1015f0984d40SFabiano Rosas DO_3S_FP_GVEC(VCGE, gen_helper_gvec_fcge_s, gen_helper_gvec_fcge_h) 1016f0984d40SFabiano Rosas DO_3S_FP_GVEC(VCGT, gen_helper_gvec_fcgt_s, gen_helper_gvec_fcgt_h) 1017f0984d40SFabiano Rosas DO_3S_FP_GVEC(VACGE, gen_helper_gvec_facge_s, gen_helper_gvec_facge_h) 1018f0984d40SFabiano Rosas DO_3S_FP_GVEC(VACGT, gen_helper_gvec_facgt_s, gen_helper_gvec_facgt_h) 1019f0984d40SFabiano Rosas DO_3S_FP_GVEC(VMAX, gen_helper_gvec_fmax_s, gen_helper_gvec_fmax_h) 1020f0984d40SFabiano Rosas DO_3S_FP_GVEC(VMIN, gen_helper_gvec_fmin_s, gen_helper_gvec_fmin_h) 1021f0984d40SFabiano Rosas DO_3S_FP_GVEC(VMLA, gen_helper_gvec_fmla_s, gen_helper_gvec_fmla_h) 1022f0984d40SFabiano Rosas DO_3S_FP_GVEC(VMLS, gen_helper_gvec_fmls_s, gen_helper_gvec_fmls_h) 1023f0984d40SFabiano Rosas DO_3S_FP_GVEC(VFMA, gen_helper_gvec_vfma_s, gen_helper_gvec_vfma_h) 1024f0984d40SFabiano Rosas DO_3S_FP_GVEC(VFMS, gen_helper_gvec_vfms_s, gen_helper_gvec_vfms_h) 1025f0984d40SFabiano Rosas DO_3S_FP_GVEC(VRECPS, gen_helper_gvec_recps_nf_s, gen_helper_gvec_recps_nf_h) 1026f0984d40SFabiano Rosas DO_3S_FP_GVEC(VRSQRTS, gen_helper_gvec_rsqrts_nf_s, gen_helper_gvec_rsqrts_nf_h) 1027c43a23e1SRichard Henderson DO_3S_FP_GVEC(VPADD, gen_helper_gvec_faddp_s, gen_helper_gvec_faddp_h) 1028c43a23e1SRichard Henderson DO_3S_FP_GVEC(VPMAX, gen_helper_gvec_fmaxp_s, gen_helper_gvec_fmaxp_h) 1029c43a23e1SRichard Henderson DO_3S_FP_GVEC(VPMIN, gen_helper_gvec_fminp_s, gen_helper_gvec_fminp_h) 1030f0984d40SFabiano Rosas 1031f0984d40SFabiano Rosas WRAP_FP_GVEC(gen_VMAXNM_fp32_3s, FPST_STD, gen_helper_gvec_fmaxnum_s) 1032f0984d40SFabiano Rosas WRAP_FP_GVEC(gen_VMAXNM_fp16_3s, FPST_STD_F16, gen_helper_gvec_fmaxnum_h) 1033f0984d40SFabiano Rosas WRAP_FP_GVEC(gen_VMINNM_fp32_3s, FPST_STD, gen_helper_gvec_fminnum_s) 1034f0984d40SFabiano Rosas WRAP_FP_GVEC(gen_VMINNM_fp16_3s, FPST_STD_F16, gen_helper_gvec_fminnum_h) 1035f0984d40SFabiano Rosas 1036f0984d40SFabiano Rosas static bool trans_VMAXNM_fp_3s(DisasContext *s, arg_3same *a) 1037f0984d40SFabiano Rosas { 1038f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_V8)) { 1039f0984d40SFabiano Rosas return false; 1040f0984d40SFabiano Rosas } 1041f0984d40SFabiano Rosas 1042f0984d40SFabiano Rosas if (a->size == MO_16) { 1043f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_fp16_arith, s)) { 1044f0984d40SFabiano Rosas return false; 1045f0984d40SFabiano Rosas } 1046f0984d40SFabiano Rosas return do_3same(s, a, gen_VMAXNM_fp16_3s); 1047f0984d40SFabiano Rosas } 1048f0984d40SFabiano Rosas return do_3same(s, a, gen_VMAXNM_fp32_3s); 1049f0984d40SFabiano Rosas } 1050f0984d40SFabiano Rosas 1051f0984d40SFabiano Rosas static bool trans_VMINNM_fp_3s(DisasContext *s, arg_3same *a) 1052f0984d40SFabiano Rosas { 1053f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_V8)) { 1054f0984d40SFabiano Rosas return false; 1055f0984d40SFabiano Rosas } 1056f0984d40SFabiano Rosas 1057f0984d40SFabiano Rosas if (a->size == MO_16) { 1058f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_fp16_arith, s)) { 1059f0984d40SFabiano Rosas return false; 1060f0984d40SFabiano Rosas } 1061f0984d40SFabiano Rosas return do_3same(s, a, gen_VMINNM_fp16_3s); 1062f0984d40SFabiano Rosas } 1063f0984d40SFabiano Rosas return do_3same(s, a, gen_VMINNM_fp32_3s); 1064f0984d40SFabiano Rosas } 1065f0984d40SFabiano Rosas 1066f0984d40SFabiano Rosas static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn) 1067f0984d40SFabiano Rosas { 1068f0984d40SFabiano Rosas /* Handle a 2-reg-shift insn which can be vectorized. */ 1069f0984d40SFabiano Rosas int vec_size = a->q ? 16 : 8; 1070f0984d40SFabiano Rosas int rd_ofs = neon_full_reg_offset(a->vd); 1071f0984d40SFabiano Rosas int rm_ofs = neon_full_reg_offset(a->vm); 1072f0984d40SFabiano Rosas 1073f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 1074f0984d40SFabiano Rosas return false; 1075f0984d40SFabiano Rosas } 1076f0984d40SFabiano Rosas 1077f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 1078f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 1079f0984d40SFabiano Rosas ((a->vd | a->vm) & 0x10)) { 1080f0984d40SFabiano Rosas return false; 1081f0984d40SFabiano Rosas } 1082f0984d40SFabiano Rosas 1083f0984d40SFabiano Rosas if ((a->vm | a->vd) & a->q) { 1084f0984d40SFabiano Rosas return false; 1085f0984d40SFabiano Rosas } 1086f0984d40SFabiano Rosas 1087f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 1088f0984d40SFabiano Rosas return true; 1089f0984d40SFabiano Rosas } 1090f0984d40SFabiano Rosas 1091f0984d40SFabiano Rosas fn(a->size, rd_ofs, rm_ofs, a->shift, vec_size, vec_size); 1092f0984d40SFabiano Rosas return true; 1093f0984d40SFabiano Rosas } 1094f0984d40SFabiano Rosas 1095f0984d40SFabiano Rosas #define DO_2SH(INSN, FUNC) \ 1096f0984d40SFabiano Rosas static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ 1097f0984d40SFabiano Rosas { \ 1098f0984d40SFabiano Rosas return do_vector_2sh(s, a, FUNC); \ 1099f0984d40SFabiano Rosas } \ 1100f0984d40SFabiano Rosas 1101f0984d40SFabiano Rosas DO_2SH(VSHL, tcg_gen_gvec_shli) 1102f0984d40SFabiano Rosas DO_2SH(VSLI, gen_gvec_sli) 1103f0984d40SFabiano Rosas DO_2SH(VSRI, gen_gvec_sri) 1104f0984d40SFabiano Rosas DO_2SH(VSRA_S, gen_gvec_ssra) 1105f0984d40SFabiano Rosas DO_2SH(VSRA_U, gen_gvec_usra) 1106f0984d40SFabiano Rosas DO_2SH(VRSHR_S, gen_gvec_srshr) 1107f0984d40SFabiano Rosas DO_2SH(VRSHR_U, gen_gvec_urshr) 1108f0984d40SFabiano Rosas DO_2SH(VRSRA_S, gen_gvec_srsra) 1109f0984d40SFabiano Rosas DO_2SH(VRSRA_U, gen_gvec_ursra) 1110f0984d40SFabiano Rosas 1111f0984d40SFabiano Rosas static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a) 1112f0984d40SFabiano Rosas { 1113f0984d40SFabiano Rosas /* Signed shift out of range results in all-sign-bits */ 1114f0984d40SFabiano Rosas a->shift = MIN(a->shift, (8 << a->size) - 1); 1115f0984d40SFabiano Rosas return do_vector_2sh(s, a, tcg_gen_gvec_sari); 1116f0984d40SFabiano Rosas } 1117f0984d40SFabiano Rosas 1118f0984d40SFabiano Rosas static void gen_zero_rd_2sh(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 1119f0984d40SFabiano Rosas int64_t shift, uint32_t oprsz, uint32_t maxsz) 1120f0984d40SFabiano Rosas { 1121f0984d40SFabiano Rosas tcg_gen_gvec_dup_imm(vece, rd_ofs, oprsz, maxsz, 0); 1122f0984d40SFabiano Rosas } 1123f0984d40SFabiano Rosas 1124f0984d40SFabiano Rosas static bool trans_VSHR_U_2sh(DisasContext *s, arg_2reg_shift *a) 1125f0984d40SFabiano Rosas { 1126f0984d40SFabiano Rosas /* Shift out of range is architecturally valid and results in zero. */ 1127f0984d40SFabiano Rosas if (a->shift >= (8 << a->size)) { 1128f0984d40SFabiano Rosas return do_vector_2sh(s, a, gen_zero_rd_2sh); 1129f0984d40SFabiano Rosas } else { 1130f0984d40SFabiano Rosas return do_vector_2sh(s, a, tcg_gen_gvec_shri); 1131f0984d40SFabiano Rosas } 1132f0984d40SFabiano Rosas } 1133f0984d40SFabiano Rosas 1134f0984d40SFabiano Rosas static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a, 1135f0984d40SFabiano Rosas NeonGenTwo64OpEnvFn *fn) 1136f0984d40SFabiano Rosas { 1137f0984d40SFabiano Rosas /* 1138f0984d40SFabiano Rosas * 2-reg-and-shift operations, size == 3 case, where the 1139ad75a51eSRichard Henderson * function needs to be passed tcg_env. 1140f0984d40SFabiano Rosas */ 1141f0984d40SFabiano Rosas TCGv_i64 constimm; 1142f0984d40SFabiano Rosas int pass; 1143f0984d40SFabiano Rosas 1144f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 1145f0984d40SFabiano Rosas return false; 1146f0984d40SFabiano Rosas } 1147f0984d40SFabiano Rosas 1148f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 1149f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 1150f0984d40SFabiano Rosas ((a->vd | a->vm) & 0x10)) { 1151f0984d40SFabiano Rosas return false; 1152f0984d40SFabiano Rosas } 1153f0984d40SFabiano Rosas 1154f0984d40SFabiano Rosas if ((a->vm | a->vd) & a->q) { 1155f0984d40SFabiano Rosas return false; 1156f0984d40SFabiano Rosas } 1157f0984d40SFabiano Rosas 1158f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 1159f0984d40SFabiano Rosas return true; 1160f0984d40SFabiano Rosas } 1161f0984d40SFabiano Rosas 1162f0984d40SFabiano Rosas /* 1163f0984d40SFabiano Rosas * To avoid excessive duplication of ops we implement shift 1164f0984d40SFabiano Rosas * by immediate using the variable shift operations. 1165f0984d40SFabiano Rosas */ 1166f0984d40SFabiano Rosas constimm = tcg_constant_i64(dup_const(a->size, a->shift)); 1167f0984d40SFabiano Rosas 1168f0984d40SFabiano Rosas for (pass = 0; pass < a->q + 1; pass++) { 1169f0984d40SFabiano Rosas TCGv_i64 tmp = tcg_temp_new_i64(); 1170f0984d40SFabiano Rosas 1171f0984d40SFabiano Rosas read_neon_element64(tmp, a->vm, pass, MO_64); 1172ad75a51eSRichard Henderson fn(tmp, tcg_env, tmp, constimm); 1173f0984d40SFabiano Rosas write_neon_element64(tmp, a->vd, pass, MO_64); 1174f0984d40SFabiano Rosas } 1175f0984d40SFabiano Rosas return true; 1176f0984d40SFabiano Rosas } 1177f0984d40SFabiano Rosas 1178f0984d40SFabiano Rosas static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a, 1179f0984d40SFabiano Rosas NeonGenTwoOpEnvFn *fn) 1180f0984d40SFabiano Rosas { 1181f0984d40SFabiano Rosas /* 1182f0984d40SFabiano Rosas * 2-reg-and-shift operations, size < 3 case, where the 1183ad75a51eSRichard Henderson * helper needs to be passed tcg_env. 1184f0984d40SFabiano Rosas */ 1185f0984d40SFabiano Rosas TCGv_i32 constimm, tmp; 1186f0984d40SFabiano Rosas int pass; 1187f0984d40SFabiano Rosas 1188f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 1189f0984d40SFabiano Rosas return false; 1190f0984d40SFabiano Rosas } 1191f0984d40SFabiano Rosas 1192f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 1193f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 1194f0984d40SFabiano Rosas ((a->vd | a->vm) & 0x10)) { 1195f0984d40SFabiano Rosas return false; 1196f0984d40SFabiano Rosas } 1197f0984d40SFabiano Rosas 1198f0984d40SFabiano Rosas if ((a->vm | a->vd) & a->q) { 1199f0984d40SFabiano Rosas return false; 1200f0984d40SFabiano Rosas } 1201f0984d40SFabiano Rosas 1202f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 1203f0984d40SFabiano Rosas return true; 1204f0984d40SFabiano Rosas } 1205f0984d40SFabiano Rosas 1206f0984d40SFabiano Rosas /* 1207f0984d40SFabiano Rosas * To avoid excessive duplication of ops we implement shift 1208f0984d40SFabiano Rosas * by immediate using the variable shift operations. 1209f0984d40SFabiano Rosas */ 1210f0984d40SFabiano Rosas constimm = tcg_constant_i32(dup_const(a->size, a->shift)); 1211f0984d40SFabiano Rosas tmp = tcg_temp_new_i32(); 1212f0984d40SFabiano Rosas 1213f0984d40SFabiano Rosas for (pass = 0; pass < (a->q ? 4 : 2); pass++) { 1214f0984d40SFabiano Rosas read_neon_element32(tmp, a->vm, pass, MO_32); 1215ad75a51eSRichard Henderson fn(tmp, tcg_env, tmp, constimm); 1216f0984d40SFabiano Rosas write_neon_element32(tmp, a->vd, pass, MO_32); 1217f0984d40SFabiano Rosas } 1218f0984d40SFabiano Rosas return true; 1219f0984d40SFabiano Rosas } 1220f0984d40SFabiano Rosas 1221f0984d40SFabiano Rosas #define DO_2SHIFT_ENV(INSN, FUNC) \ 1222f0984d40SFabiano Rosas static bool trans_##INSN##_64_2sh(DisasContext *s, arg_2reg_shift *a) \ 1223f0984d40SFabiano Rosas { \ 1224f0984d40SFabiano Rosas return do_2shift_env_64(s, a, gen_helper_neon_##FUNC##64); \ 1225f0984d40SFabiano Rosas } \ 1226f0984d40SFabiano Rosas static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ 1227f0984d40SFabiano Rosas { \ 1228f0984d40SFabiano Rosas static NeonGenTwoOpEnvFn * const fns[] = { \ 1229f0984d40SFabiano Rosas gen_helper_neon_##FUNC##8, \ 1230f0984d40SFabiano Rosas gen_helper_neon_##FUNC##16, \ 1231f0984d40SFabiano Rosas gen_helper_neon_##FUNC##32, \ 1232f0984d40SFabiano Rosas }; \ 1233f0984d40SFabiano Rosas assert(a->size < ARRAY_SIZE(fns)); \ 1234f0984d40SFabiano Rosas return do_2shift_env_32(s, a, fns[a->size]); \ 1235f0984d40SFabiano Rosas } 1236f0984d40SFabiano Rosas 1237f0984d40SFabiano Rosas DO_2SHIFT_ENV(VQSHLU, qshlu_s) 1238f0984d40SFabiano Rosas DO_2SHIFT_ENV(VQSHL_U, qshl_u) 1239f0984d40SFabiano Rosas DO_2SHIFT_ENV(VQSHL_S, qshl_s) 1240f0984d40SFabiano Rosas 1241f0984d40SFabiano Rosas static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a, 1242f0984d40SFabiano Rosas NeonGenTwo64OpFn *shiftfn, 1243f0984d40SFabiano Rosas NeonGenNarrowEnvFn *narrowfn) 1244f0984d40SFabiano Rosas { 1245f0984d40SFabiano Rosas /* 2-reg-and-shift narrowing-shift operations, size == 3 case */ 1246f0984d40SFabiano Rosas TCGv_i64 constimm, rm1, rm2; 1247f0984d40SFabiano Rosas TCGv_i32 rd; 1248f0984d40SFabiano Rosas 1249f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 1250f0984d40SFabiano Rosas return false; 1251f0984d40SFabiano Rosas } 1252f0984d40SFabiano Rosas 1253f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 1254f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 1255f0984d40SFabiano Rosas ((a->vd | a->vm) & 0x10)) { 1256f0984d40SFabiano Rosas return false; 1257f0984d40SFabiano Rosas } 1258f0984d40SFabiano Rosas 1259f0984d40SFabiano Rosas if (a->vm & 1) { 1260f0984d40SFabiano Rosas return false; 1261f0984d40SFabiano Rosas } 1262f0984d40SFabiano Rosas 1263f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 1264f0984d40SFabiano Rosas return true; 1265f0984d40SFabiano Rosas } 1266f0984d40SFabiano Rosas 1267f0984d40SFabiano Rosas /* 1268f0984d40SFabiano Rosas * This is always a right shift, and the shiftfn is always a 1269f0984d40SFabiano Rosas * left-shift helper, which thus needs the negated shift count. 1270f0984d40SFabiano Rosas */ 1271f0984d40SFabiano Rosas constimm = tcg_constant_i64(-a->shift); 1272f0984d40SFabiano Rosas rm1 = tcg_temp_new_i64(); 1273f0984d40SFabiano Rosas rm2 = tcg_temp_new_i64(); 1274f0984d40SFabiano Rosas rd = tcg_temp_new_i32(); 1275f0984d40SFabiano Rosas 1276f0984d40SFabiano Rosas /* Load both inputs first to avoid potential overwrite if rm == rd */ 1277f0984d40SFabiano Rosas read_neon_element64(rm1, a->vm, 0, MO_64); 1278f0984d40SFabiano Rosas read_neon_element64(rm2, a->vm, 1, MO_64); 1279f0984d40SFabiano Rosas 1280f0984d40SFabiano Rosas shiftfn(rm1, rm1, constimm); 1281ad75a51eSRichard Henderson narrowfn(rd, tcg_env, rm1); 1282f0984d40SFabiano Rosas write_neon_element32(rd, a->vd, 0, MO_32); 1283f0984d40SFabiano Rosas 1284f0984d40SFabiano Rosas shiftfn(rm2, rm2, constimm); 1285ad75a51eSRichard Henderson narrowfn(rd, tcg_env, rm2); 1286f0984d40SFabiano Rosas write_neon_element32(rd, a->vd, 1, MO_32); 1287f0984d40SFabiano Rosas 1288f0984d40SFabiano Rosas return true; 1289f0984d40SFabiano Rosas } 1290f0984d40SFabiano Rosas 1291f0984d40SFabiano Rosas static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a, 1292f0984d40SFabiano Rosas NeonGenTwoOpFn *shiftfn, 1293f0984d40SFabiano Rosas NeonGenNarrowEnvFn *narrowfn) 1294f0984d40SFabiano Rosas { 1295f0984d40SFabiano Rosas /* 2-reg-and-shift narrowing-shift operations, size < 3 case */ 1296f0984d40SFabiano Rosas TCGv_i32 constimm, rm1, rm2, rm3, rm4; 1297f0984d40SFabiano Rosas TCGv_i64 rtmp; 1298f0984d40SFabiano Rosas uint32_t imm; 1299f0984d40SFabiano Rosas 1300f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 1301f0984d40SFabiano Rosas return false; 1302f0984d40SFabiano Rosas } 1303f0984d40SFabiano Rosas 1304f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 1305f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 1306f0984d40SFabiano Rosas ((a->vd | a->vm) & 0x10)) { 1307f0984d40SFabiano Rosas return false; 1308f0984d40SFabiano Rosas } 1309f0984d40SFabiano Rosas 1310f0984d40SFabiano Rosas if (a->vm & 1) { 1311f0984d40SFabiano Rosas return false; 1312f0984d40SFabiano Rosas } 1313f0984d40SFabiano Rosas 1314f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 1315f0984d40SFabiano Rosas return true; 1316f0984d40SFabiano Rosas } 1317f0984d40SFabiano Rosas 1318f0984d40SFabiano Rosas /* 1319f0984d40SFabiano Rosas * This is always a right shift, and the shiftfn is always a 1320f0984d40SFabiano Rosas * left-shift helper, which thus needs the negated shift count 1321f0984d40SFabiano Rosas * duplicated into each lane of the immediate value. 1322f0984d40SFabiano Rosas */ 1323f0984d40SFabiano Rosas if (a->size == 1) { 1324f0984d40SFabiano Rosas imm = (uint16_t)(-a->shift); 1325f0984d40SFabiano Rosas imm |= imm << 16; 1326f0984d40SFabiano Rosas } else { 1327f0984d40SFabiano Rosas /* size == 2 */ 1328f0984d40SFabiano Rosas imm = -a->shift; 1329f0984d40SFabiano Rosas } 1330f0984d40SFabiano Rosas constimm = tcg_constant_i32(imm); 1331f0984d40SFabiano Rosas 1332f0984d40SFabiano Rosas /* Load all inputs first to avoid potential overwrite */ 1333f0984d40SFabiano Rosas rm1 = tcg_temp_new_i32(); 1334f0984d40SFabiano Rosas rm2 = tcg_temp_new_i32(); 1335f0984d40SFabiano Rosas rm3 = tcg_temp_new_i32(); 1336f0984d40SFabiano Rosas rm4 = tcg_temp_new_i32(); 1337f0984d40SFabiano Rosas read_neon_element32(rm1, a->vm, 0, MO_32); 1338f0984d40SFabiano Rosas read_neon_element32(rm2, a->vm, 1, MO_32); 1339f0984d40SFabiano Rosas read_neon_element32(rm3, a->vm, 2, MO_32); 1340f0984d40SFabiano Rosas read_neon_element32(rm4, a->vm, 3, MO_32); 1341f0984d40SFabiano Rosas rtmp = tcg_temp_new_i64(); 1342f0984d40SFabiano Rosas 1343f0984d40SFabiano Rosas shiftfn(rm1, rm1, constimm); 1344f0984d40SFabiano Rosas shiftfn(rm2, rm2, constimm); 1345f0984d40SFabiano Rosas 1346f0984d40SFabiano Rosas tcg_gen_concat_i32_i64(rtmp, rm1, rm2); 1347f0984d40SFabiano Rosas 1348ad75a51eSRichard Henderson narrowfn(rm1, tcg_env, rtmp); 1349f0984d40SFabiano Rosas write_neon_element32(rm1, a->vd, 0, MO_32); 1350f0984d40SFabiano Rosas 1351f0984d40SFabiano Rosas shiftfn(rm3, rm3, constimm); 1352f0984d40SFabiano Rosas shiftfn(rm4, rm4, constimm); 1353f0984d40SFabiano Rosas 1354f0984d40SFabiano Rosas tcg_gen_concat_i32_i64(rtmp, rm3, rm4); 1355f0984d40SFabiano Rosas 1356ad75a51eSRichard Henderson narrowfn(rm3, tcg_env, rtmp); 1357f0984d40SFabiano Rosas write_neon_element32(rm3, a->vd, 1, MO_32); 1358f0984d40SFabiano Rosas return true; 1359f0984d40SFabiano Rosas } 1360f0984d40SFabiano Rosas 1361f0984d40SFabiano Rosas #define DO_2SN_64(INSN, FUNC, NARROWFUNC) \ 1362f0984d40SFabiano Rosas static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ 1363f0984d40SFabiano Rosas { \ 1364f0984d40SFabiano Rosas return do_2shift_narrow_64(s, a, FUNC, NARROWFUNC); \ 1365f0984d40SFabiano Rosas } 1366f0984d40SFabiano Rosas #define DO_2SN_32(INSN, FUNC, NARROWFUNC) \ 1367f0984d40SFabiano Rosas static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ 1368f0984d40SFabiano Rosas { \ 1369f0984d40SFabiano Rosas return do_2shift_narrow_32(s, a, FUNC, NARROWFUNC); \ 1370f0984d40SFabiano Rosas } 1371f0984d40SFabiano Rosas 1372f0984d40SFabiano Rosas static void gen_neon_narrow_u32(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) 1373f0984d40SFabiano Rosas { 1374f0984d40SFabiano Rosas tcg_gen_extrl_i64_i32(dest, src); 1375f0984d40SFabiano Rosas } 1376f0984d40SFabiano Rosas 1377f0984d40SFabiano Rosas static void gen_neon_narrow_u16(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) 1378f0984d40SFabiano Rosas { 1379f0984d40SFabiano Rosas gen_helper_neon_narrow_u16(dest, src); 1380f0984d40SFabiano Rosas } 1381f0984d40SFabiano Rosas 1382f0984d40SFabiano Rosas static void gen_neon_narrow_u8(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) 1383f0984d40SFabiano Rosas { 1384f0984d40SFabiano Rosas gen_helper_neon_narrow_u8(dest, src); 1385f0984d40SFabiano Rosas } 1386f0984d40SFabiano Rosas 1387f0984d40SFabiano Rosas DO_2SN_64(VSHRN_64, gen_ushl_i64, gen_neon_narrow_u32) 1388f0984d40SFabiano Rosas DO_2SN_32(VSHRN_32, gen_ushl_i32, gen_neon_narrow_u16) 1389f0984d40SFabiano Rosas DO_2SN_32(VSHRN_16, gen_helper_neon_shl_u16, gen_neon_narrow_u8) 1390f0984d40SFabiano Rosas 1391f0984d40SFabiano Rosas DO_2SN_64(VRSHRN_64, gen_helper_neon_rshl_u64, gen_neon_narrow_u32) 1392f0984d40SFabiano Rosas DO_2SN_32(VRSHRN_32, gen_helper_neon_rshl_u32, gen_neon_narrow_u16) 1393f0984d40SFabiano Rosas DO_2SN_32(VRSHRN_16, gen_helper_neon_rshl_u16, gen_neon_narrow_u8) 1394f0984d40SFabiano Rosas 1395f0984d40SFabiano Rosas DO_2SN_64(VQSHRUN_64, gen_sshl_i64, gen_helper_neon_unarrow_sat32) 1396f0984d40SFabiano Rosas DO_2SN_32(VQSHRUN_32, gen_sshl_i32, gen_helper_neon_unarrow_sat16) 1397f0984d40SFabiano Rosas DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_helper_neon_unarrow_sat8) 1398f0984d40SFabiano Rosas 1399f0984d40SFabiano Rosas DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_sat32) 1400f0984d40SFabiano Rosas DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_sat16) 1401f0984d40SFabiano Rosas DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_sat8) 1402f0984d40SFabiano Rosas DO_2SN_64(VQSHRN_S64, gen_sshl_i64, gen_helper_neon_narrow_sat_s32) 1403f0984d40SFabiano Rosas DO_2SN_32(VQSHRN_S32, gen_sshl_i32, gen_helper_neon_narrow_sat_s16) 1404f0984d40SFabiano Rosas DO_2SN_32(VQSHRN_S16, gen_helper_neon_shl_s16, gen_helper_neon_narrow_sat_s8) 1405f0984d40SFabiano Rosas 1406f0984d40SFabiano Rosas DO_2SN_64(VQRSHRN_S64, gen_helper_neon_rshl_s64, gen_helper_neon_narrow_sat_s32) 1407f0984d40SFabiano Rosas DO_2SN_32(VQRSHRN_S32, gen_helper_neon_rshl_s32, gen_helper_neon_narrow_sat_s16) 1408f0984d40SFabiano Rosas DO_2SN_32(VQRSHRN_S16, gen_helper_neon_rshl_s16, gen_helper_neon_narrow_sat_s8) 1409f0984d40SFabiano Rosas 1410f0984d40SFabiano Rosas DO_2SN_64(VQSHRN_U64, gen_ushl_i64, gen_helper_neon_narrow_sat_u32) 1411f0984d40SFabiano Rosas DO_2SN_32(VQSHRN_U32, gen_ushl_i32, gen_helper_neon_narrow_sat_u16) 1412f0984d40SFabiano Rosas DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_helper_neon_narrow_sat_u8) 1413f0984d40SFabiano Rosas 1414f0984d40SFabiano Rosas DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sat_u32) 1415f0984d40SFabiano Rosas DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sat_u16) 1416f0984d40SFabiano Rosas DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sat_u8) 1417f0984d40SFabiano Rosas 1418f0984d40SFabiano Rosas static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, 1419f0984d40SFabiano Rosas NeonGenWidenFn *widenfn, bool u) 1420f0984d40SFabiano Rosas { 1421f0984d40SFabiano Rosas TCGv_i64 tmp; 1422f0984d40SFabiano Rosas TCGv_i32 rm0, rm1; 1423f0984d40SFabiano Rosas uint64_t widen_mask = 0; 1424f0984d40SFabiano Rosas 1425f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 1426f0984d40SFabiano Rosas return false; 1427f0984d40SFabiano Rosas } 1428f0984d40SFabiano Rosas 1429f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 1430f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 1431f0984d40SFabiano Rosas ((a->vd | a->vm) & 0x10)) { 1432f0984d40SFabiano Rosas return false; 1433f0984d40SFabiano Rosas } 1434f0984d40SFabiano Rosas 1435f0984d40SFabiano Rosas if (a->vd & 1) { 1436f0984d40SFabiano Rosas return false; 1437f0984d40SFabiano Rosas } 1438f0984d40SFabiano Rosas 1439f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 1440f0984d40SFabiano Rosas return true; 1441f0984d40SFabiano Rosas } 1442f0984d40SFabiano Rosas 1443f0984d40SFabiano Rosas /* 1444f0984d40SFabiano Rosas * This is a widen-and-shift operation. The shift is always less 1445f0984d40SFabiano Rosas * than the width of the source type, so after widening the input 1446f0984d40SFabiano Rosas * vector we can simply shift the whole 64-bit widened register, 1447f0984d40SFabiano Rosas * and then clear the potential overflow bits resulting from left 1448f0984d40SFabiano Rosas * bits of the narrow input appearing as right bits of the left 1449f0984d40SFabiano Rosas * neighbour narrow input. Calculate a mask of bits to clear. 1450f0984d40SFabiano Rosas */ 1451f0984d40SFabiano Rosas if ((a->shift != 0) && (a->size < 2 || u)) { 1452f0984d40SFabiano Rosas int esize = 8 << a->size; 1453f0984d40SFabiano Rosas widen_mask = MAKE_64BIT_MASK(0, esize); 1454f0984d40SFabiano Rosas widen_mask >>= esize - a->shift; 1455f0984d40SFabiano Rosas widen_mask = dup_const(a->size + 1, widen_mask); 1456f0984d40SFabiano Rosas } 1457f0984d40SFabiano Rosas 1458f0984d40SFabiano Rosas rm0 = tcg_temp_new_i32(); 1459f0984d40SFabiano Rosas rm1 = tcg_temp_new_i32(); 1460f0984d40SFabiano Rosas read_neon_element32(rm0, a->vm, 0, MO_32); 1461f0984d40SFabiano Rosas read_neon_element32(rm1, a->vm, 1, MO_32); 1462f0984d40SFabiano Rosas tmp = tcg_temp_new_i64(); 1463f0984d40SFabiano Rosas 1464f0984d40SFabiano Rosas widenfn(tmp, rm0); 1465f0984d40SFabiano Rosas if (a->shift != 0) { 1466f0984d40SFabiano Rosas tcg_gen_shli_i64(tmp, tmp, a->shift); 1467f0984d40SFabiano Rosas tcg_gen_andi_i64(tmp, tmp, ~widen_mask); 1468f0984d40SFabiano Rosas } 1469f0984d40SFabiano Rosas write_neon_element64(tmp, a->vd, 0, MO_64); 1470f0984d40SFabiano Rosas 1471f0984d40SFabiano Rosas widenfn(tmp, rm1); 1472f0984d40SFabiano Rosas if (a->shift != 0) { 1473f0984d40SFabiano Rosas tcg_gen_shli_i64(tmp, tmp, a->shift); 1474f0984d40SFabiano Rosas tcg_gen_andi_i64(tmp, tmp, ~widen_mask); 1475f0984d40SFabiano Rosas } 1476f0984d40SFabiano Rosas write_neon_element64(tmp, a->vd, 1, MO_64); 1477f0984d40SFabiano Rosas return true; 1478f0984d40SFabiano Rosas } 1479f0984d40SFabiano Rosas 1480f0984d40SFabiano Rosas static bool trans_VSHLL_S_2sh(DisasContext *s, arg_2reg_shift *a) 1481f0984d40SFabiano Rosas { 1482f0984d40SFabiano Rosas static NeonGenWidenFn * const widenfn[] = { 1483f0984d40SFabiano Rosas gen_helper_neon_widen_s8, 1484f0984d40SFabiano Rosas gen_helper_neon_widen_s16, 1485f0984d40SFabiano Rosas tcg_gen_ext_i32_i64, 1486f0984d40SFabiano Rosas }; 1487f0984d40SFabiano Rosas return do_vshll_2sh(s, a, widenfn[a->size], false); 1488f0984d40SFabiano Rosas } 1489f0984d40SFabiano Rosas 1490f0984d40SFabiano Rosas static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a) 1491f0984d40SFabiano Rosas { 1492f0984d40SFabiano Rosas static NeonGenWidenFn * const widenfn[] = { 1493f0984d40SFabiano Rosas gen_helper_neon_widen_u8, 1494f0984d40SFabiano Rosas gen_helper_neon_widen_u16, 1495f0984d40SFabiano Rosas tcg_gen_extu_i32_i64, 1496f0984d40SFabiano Rosas }; 1497f0984d40SFabiano Rosas return do_vshll_2sh(s, a, widenfn[a->size], true); 1498f0984d40SFabiano Rosas } 1499f0984d40SFabiano Rosas 1500f0984d40SFabiano Rosas static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a, 1501f0984d40SFabiano Rosas gen_helper_gvec_2_ptr *fn) 1502f0984d40SFabiano Rosas { 1503f0984d40SFabiano Rosas /* FP operations in 2-reg-and-shift group */ 1504f0984d40SFabiano Rosas int vec_size = a->q ? 16 : 8; 1505f0984d40SFabiano Rosas int rd_ofs = neon_full_reg_offset(a->vd); 1506f0984d40SFabiano Rosas int rm_ofs = neon_full_reg_offset(a->vm); 1507f0984d40SFabiano Rosas TCGv_ptr fpst; 1508f0984d40SFabiano Rosas 1509f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 1510f0984d40SFabiano Rosas return false; 1511f0984d40SFabiano Rosas } 1512f0984d40SFabiano Rosas 1513f0984d40SFabiano Rosas if (a->size == MO_16) { 1514f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_fp16_arith, s)) { 1515f0984d40SFabiano Rosas return false; 1516f0984d40SFabiano Rosas } 1517f0984d40SFabiano Rosas } 1518f0984d40SFabiano Rosas 1519f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 1520f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 1521f0984d40SFabiano Rosas ((a->vd | a->vm) & 0x10)) { 1522f0984d40SFabiano Rosas return false; 1523f0984d40SFabiano Rosas } 1524f0984d40SFabiano Rosas 1525f0984d40SFabiano Rosas if ((a->vm | a->vd) & a->q) { 1526f0984d40SFabiano Rosas return false; 1527f0984d40SFabiano Rosas } 1528f0984d40SFabiano Rosas 1529f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 1530f0984d40SFabiano Rosas return true; 1531f0984d40SFabiano Rosas } 1532f0984d40SFabiano Rosas 1533f0984d40SFabiano Rosas fpst = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD); 1534f0984d40SFabiano Rosas tcg_gen_gvec_2_ptr(rd_ofs, rm_ofs, fpst, vec_size, vec_size, a->shift, fn); 1535f0984d40SFabiano Rosas return true; 1536f0984d40SFabiano Rosas } 1537f0984d40SFabiano Rosas 1538f0984d40SFabiano Rosas #define DO_FP_2SH(INSN, FUNC) \ 1539f0984d40SFabiano Rosas static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ 1540f0984d40SFabiano Rosas { \ 1541f0984d40SFabiano Rosas return do_fp_2sh(s, a, FUNC); \ 1542f0984d40SFabiano Rosas } 1543f0984d40SFabiano Rosas 1544f0984d40SFabiano Rosas DO_FP_2SH(VCVT_SF, gen_helper_gvec_vcvt_sf) 1545f0984d40SFabiano Rosas DO_FP_2SH(VCVT_UF, gen_helper_gvec_vcvt_uf) 1546f0984d40SFabiano Rosas DO_FP_2SH(VCVT_FS, gen_helper_gvec_vcvt_fs) 1547f0984d40SFabiano Rosas DO_FP_2SH(VCVT_FU, gen_helper_gvec_vcvt_fu) 1548f0984d40SFabiano Rosas 1549f0984d40SFabiano Rosas DO_FP_2SH(VCVT_SH, gen_helper_gvec_vcvt_sh) 1550f0984d40SFabiano Rosas DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh) 1551f0984d40SFabiano Rosas DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs) 1552f0984d40SFabiano Rosas DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu) 1553f0984d40SFabiano Rosas 1554f0984d40SFabiano Rosas static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a, 1555f0984d40SFabiano Rosas GVecGen2iFn *fn) 1556f0984d40SFabiano Rosas { 1557f0984d40SFabiano Rosas uint64_t imm; 1558f0984d40SFabiano Rosas int reg_ofs, vec_size; 1559f0984d40SFabiano Rosas 1560f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 1561f0984d40SFabiano Rosas return false; 1562f0984d40SFabiano Rosas } 1563f0984d40SFabiano Rosas 1564f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 1565f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { 1566f0984d40SFabiano Rosas return false; 1567f0984d40SFabiano Rosas } 1568f0984d40SFabiano Rosas 1569f0984d40SFabiano Rosas if (a->vd & a->q) { 1570f0984d40SFabiano Rosas return false; 1571f0984d40SFabiano Rosas } 1572f0984d40SFabiano Rosas 1573f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 1574f0984d40SFabiano Rosas return true; 1575f0984d40SFabiano Rosas } 1576f0984d40SFabiano Rosas 1577f0984d40SFabiano Rosas reg_ofs = neon_full_reg_offset(a->vd); 1578f0984d40SFabiano Rosas vec_size = a->q ? 16 : 8; 1579f0984d40SFabiano Rosas imm = asimd_imm_const(a->imm, a->cmode, a->op); 1580f0984d40SFabiano Rosas 1581f0984d40SFabiano Rosas fn(MO_64, reg_ofs, reg_ofs, imm, vec_size, vec_size); 1582f0984d40SFabiano Rosas return true; 1583f0984d40SFabiano Rosas } 1584f0984d40SFabiano Rosas 1585f0984d40SFabiano Rosas static void gen_VMOV_1r(unsigned vece, uint32_t dofs, uint32_t aofs, 1586f0984d40SFabiano Rosas int64_t c, uint32_t oprsz, uint32_t maxsz) 1587f0984d40SFabiano Rosas { 1588f0984d40SFabiano Rosas tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, c); 1589f0984d40SFabiano Rosas } 1590f0984d40SFabiano Rosas 1591f0984d40SFabiano Rosas static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a) 1592f0984d40SFabiano Rosas { 1593f0984d40SFabiano Rosas /* Handle decode of cmode/op here between VORR/VBIC/VMOV */ 1594f0984d40SFabiano Rosas GVecGen2iFn *fn; 1595f0984d40SFabiano Rosas 1596f0984d40SFabiano Rosas if ((a->cmode & 1) && a->cmode < 12) { 1597f0984d40SFabiano Rosas /* for op=1, the imm will be inverted, so BIC becomes AND. */ 1598f0984d40SFabiano Rosas fn = a->op ? tcg_gen_gvec_andi : tcg_gen_gvec_ori; 1599f0984d40SFabiano Rosas } else { 1600f0984d40SFabiano Rosas /* There is one unallocated cmode/op combination in this space */ 1601f0984d40SFabiano Rosas if (a->cmode == 15 && a->op == 1) { 1602f0984d40SFabiano Rosas return false; 1603f0984d40SFabiano Rosas } 1604f0984d40SFabiano Rosas fn = gen_VMOV_1r; 1605f0984d40SFabiano Rosas } 1606f0984d40SFabiano Rosas return do_1reg_imm(s, a, fn); 1607f0984d40SFabiano Rosas } 1608f0984d40SFabiano Rosas 1609f0984d40SFabiano Rosas static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, 1610f0984d40SFabiano Rosas NeonGenWidenFn *widenfn, 1611f0984d40SFabiano Rosas NeonGenTwo64OpFn *opfn, 1612f0984d40SFabiano Rosas int src1_mop, int src2_mop) 1613f0984d40SFabiano Rosas { 1614f0984d40SFabiano Rosas /* 3-regs different lengths, prewidening case (VADDL/VSUBL/VAADW/VSUBW) */ 1615f0984d40SFabiano Rosas TCGv_i64 rn0_64, rn1_64, rm_64; 1616f0984d40SFabiano Rosas 1617f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 1618f0984d40SFabiano Rosas return false; 1619f0984d40SFabiano Rosas } 1620f0984d40SFabiano Rosas 1621f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 1622f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 1623f0984d40SFabiano Rosas ((a->vd | a->vn | a->vm) & 0x10)) { 1624f0984d40SFabiano Rosas return false; 1625f0984d40SFabiano Rosas } 1626f0984d40SFabiano Rosas 1627f0984d40SFabiano Rosas if (!opfn) { 1628f0984d40SFabiano Rosas /* size == 3 case, which is an entirely different insn group */ 1629f0984d40SFabiano Rosas return false; 1630f0984d40SFabiano Rosas } 1631f0984d40SFabiano Rosas 1632f0984d40SFabiano Rosas if ((a->vd & 1) || (src1_mop == MO_UQ && (a->vn & 1))) { 1633f0984d40SFabiano Rosas return false; 1634f0984d40SFabiano Rosas } 1635f0984d40SFabiano Rosas 1636f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 1637f0984d40SFabiano Rosas return true; 1638f0984d40SFabiano Rosas } 1639f0984d40SFabiano Rosas 1640f0984d40SFabiano Rosas rn0_64 = tcg_temp_new_i64(); 1641f0984d40SFabiano Rosas rn1_64 = tcg_temp_new_i64(); 1642f0984d40SFabiano Rosas rm_64 = tcg_temp_new_i64(); 1643f0984d40SFabiano Rosas 1644f0984d40SFabiano Rosas if (src1_mop >= 0) { 1645f0984d40SFabiano Rosas read_neon_element64(rn0_64, a->vn, 0, src1_mop); 1646f0984d40SFabiano Rosas } else { 1647f0984d40SFabiano Rosas TCGv_i32 tmp = tcg_temp_new_i32(); 1648f0984d40SFabiano Rosas read_neon_element32(tmp, a->vn, 0, MO_32); 1649f0984d40SFabiano Rosas widenfn(rn0_64, tmp); 1650f0984d40SFabiano Rosas } 1651f0984d40SFabiano Rosas if (src2_mop >= 0) { 1652f0984d40SFabiano Rosas read_neon_element64(rm_64, a->vm, 0, src2_mop); 1653f0984d40SFabiano Rosas } else { 1654f0984d40SFabiano Rosas TCGv_i32 tmp = tcg_temp_new_i32(); 1655f0984d40SFabiano Rosas read_neon_element32(tmp, a->vm, 0, MO_32); 1656f0984d40SFabiano Rosas widenfn(rm_64, tmp); 1657f0984d40SFabiano Rosas } 1658f0984d40SFabiano Rosas 1659f0984d40SFabiano Rosas opfn(rn0_64, rn0_64, rm_64); 1660f0984d40SFabiano Rosas 1661f0984d40SFabiano Rosas /* 1662f0984d40SFabiano Rosas * Load second pass inputs before storing the first pass result, to 1663f0984d40SFabiano Rosas * avoid incorrect results if a narrow input overlaps with the result. 1664f0984d40SFabiano Rosas */ 1665f0984d40SFabiano Rosas if (src1_mop >= 0) { 1666f0984d40SFabiano Rosas read_neon_element64(rn1_64, a->vn, 1, src1_mop); 1667f0984d40SFabiano Rosas } else { 1668f0984d40SFabiano Rosas TCGv_i32 tmp = tcg_temp_new_i32(); 1669f0984d40SFabiano Rosas read_neon_element32(tmp, a->vn, 1, MO_32); 1670f0984d40SFabiano Rosas widenfn(rn1_64, tmp); 1671f0984d40SFabiano Rosas } 1672f0984d40SFabiano Rosas if (src2_mop >= 0) { 1673f0984d40SFabiano Rosas read_neon_element64(rm_64, a->vm, 1, src2_mop); 1674f0984d40SFabiano Rosas } else { 1675f0984d40SFabiano Rosas TCGv_i32 tmp = tcg_temp_new_i32(); 1676f0984d40SFabiano Rosas read_neon_element32(tmp, a->vm, 1, MO_32); 1677f0984d40SFabiano Rosas widenfn(rm_64, tmp); 1678f0984d40SFabiano Rosas } 1679f0984d40SFabiano Rosas 1680f0984d40SFabiano Rosas write_neon_element64(rn0_64, a->vd, 0, MO_64); 1681f0984d40SFabiano Rosas 1682f0984d40SFabiano Rosas opfn(rn1_64, rn1_64, rm_64); 1683f0984d40SFabiano Rosas write_neon_element64(rn1_64, a->vd, 1, MO_64); 1684f0984d40SFabiano Rosas 1685f0984d40SFabiano Rosas return true; 1686f0984d40SFabiano Rosas } 1687f0984d40SFabiano Rosas 1688f0984d40SFabiano Rosas #define DO_PREWIDEN(INSN, S, OP, SRC1WIDE, SIGN) \ 1689f0984d40SFabiano Rosas static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \ 1690f0984d40SFabiano Rosas { \ 1691f0984d40SFabiano Rosas static NeonGenWidenFn * const widenfn[] = { \ 1692f0984d40SFabiano Rosas gen_helper_neon_widen_##S##8, \ 1693f0984d40SFabiano Rosas gen_helper_neon_widen_##S##16, \ 1694f0984d40SFabiano Rosas NULL, NULL, \ 1695f0984d40SFabiano Rosas }; \ 1696f0984d40SFabiano Rosas static NeonGenTwo64OpFn * const addfn[] = { \ 1697f0984d40SFabiano Rosas gen_helper_neon_##OP##l_u16, \ 1698f0984d40SFabiano Rosas gen_helper_neon_##OP##l_u32, \ 1699f0984d40SFabiano Rosas tcg_gen_##OP##_i64, \ 1700f0984d40SFabiano Rosas NULL, \ 1701f0984d40SFabiano Rosas }; \ 1702f0984d40SFabiano Rosas int narrow_mop = a->size == MO_32 ? MO_32 | SIGN : -1; \ 1703f0984d40SFabiano Rosas return do_prewiden_3d(s, a, widenfn[a->size], addfn[a->size], \ 1704f0984d40SFabiano Rosas SRC1WIDE ? MO_UQ : narrow_mop, \ 1705f0984d40SFabiano Rosas narrow_mop); \ 1706f0984d40SFabiano Rosas } 1707f0984d40SFabiano Rosas 1708f0984d40SFabiano Rosas DO_PREWIDEN(VADDL_S, s, add, false, MO_SIGN) 1709f0984d40SFabiano Rosas DO_PREWIDEN(VADDL_U, u, add, false, 0) 1710f0984d40SFabiano Rosas DO_PREWIDEN(VSUBL_S, s, sub, false, MO_SIGN) 1711f0984d40SFabiano Rosas DO_PREWIDEN(VSUBL_U, u, sub, false, 0) 1712f0984d40SFabiano Rosas DO_PREWIDEN(VADDW_S, s, add, true, MO_SIGN) 1713f0984d40SFabiano Rosas DO_PREWIDEN(VADDW_U, u, add, true, 0) 1714f0984d40SFabiano Rosas DO_PREWIDEN(VSUBW_S, s, sub, true, MO_SIGN) 1715f0984d40SFabiano Rosas DO_PREWIDEN(VSUBW_U, u, sub, true, 0) 1716f0984d40SFabiano Rosas 1717f0984d40SFabiano Rosas static bool do_narrow_3d(DisasContext *s, arg_3diff *a, 1718f0984d40SFabiano Rosas NeonGenTwo64OpFn *opfn, NeonGenNarrowFn *narrowfn) 1719f0984d40SFabiano Rosas { 1720f0984d40SFabiano Rosas /* 3-regs different lengths, narrowing (VADDHN/VSUBHN/VRADDHN/VRSUBHN) */ 1721f0984d40SFabiano Rosas TCGv_i64 rn_64, rm_64; 1722f0984d40SFabiano Rosas TCGv_i32 rd0, rd1; 1723f0984d40SFabiano Rosas 1724f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 1725f0984d40SFabiano Rosas return false; 1726f0984d40SFabiano Rosas } 1727f0984d40SFabiano Rosas 1728f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 1729f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 1730f0984d40SFabiano Rosas ((a->vd | a->vn | a->vm) & 0x10)) { 1731f0984d40SFabiano Rosas return false; 1732f0984d40SFabiano Rosas } 1733f0984d40SFabiano Rosas 1734f0984d40SFabiano Rosas if (!opfn || !narrowfn) { 1735f0984d40SFabiano Rosas /* size == 3 case, which is an entirely different insn group */ 1736f0984d40SFabiano Rosas return false; 1737f0984d40SFabiano Rosas } 1738f0984d40SFabiano Rosas 1739f0984d40SFabiano Rosas if ((a->vn | a->vm) & 1) { 1740f0984d40SFabiano Rosas return false; 1741f0984d40SFabiano Rosas } 1742f0984d40SFabiano Rosas 1743f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 1744f0984d40SFabiano Rosas return true; 1745f0984d40SFabiano Rosas } 1746f0984d40SFabiano Rosas 1747f0984d40SFabiano Rosas rn_64 = tcg_temp_new_i64(); 1748f0984d40SFabiano Rosas rm_64 = tcg_temp_new_i64(); 1749f0984d40SFabiano Rosas rd0 = tcg_temp_new_i32(); 1750f0984d40SFabiano Rosas rd1 = tcg_temp_new_i32(); 1751f0984d40SFabiano Rosas 1752f0984d40SFabiano Rosas read_neon_element64(rn_64, a->vn, 0, MO_64); 1753f0984d40SFabiano Rosas read_neon_element64(rm_64, a->vm, 0, MO_64); 1754f0984d40SFabiano Rosas 1755f0984d40SFabiano Rosas opfn(rn_64, rn_64, rm_64); 1756f0984d40SFabiano Rosas 1757f0984d40SFabiano Rosas narrowfn(rd0, rn_64); 1758f0984d40SFabiano Rosas 1759f0984d40SFabiano Rosas read_neon_element64(rn_64, a->vn, 1, MO_64); 1760f0984d40SFabiano Rosas read_neon_element64(rm_64, a->vm, 1, MO_64); 1761f0984d40SFabiano Rosas 1762f0984d40SFabiano Rosas opfn(rn_64, rn_64, rm_64); 1763f0984d40SFabiano Rosas 1764f0984d40SFabiano Rosas narrowfn(rd1, rn_64); 1765f0984d40SFabiano Rosas 1766f0984d40SFabiano Rosas write_neon_element32(rd0, a->vd, 0, MO_32); 1767f0984d40SFabiano Rosas write_neon_element32(rd1, a->vd, 1, MO_32); 1768f0984d40SFabiano Rosas 1769f0984d40SFabiano Rosas return true; 1770f0984d40SFabiano Rosas } 1771f0984d40SFabiano Rosas 1772f0984d40SFabiano Rosas #define DO_NARROW_3D(INSN, OP, NARROWTYPE, EXTOP) \ 1773f0984d40SFabiano Rosas static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \ 1774f0984d40SFabiano Rosas { \ 1775f0984d40SFabiano Rosas static NeonGenTwo64OpFn * const addfn[] = { \ 1776f0984d40SFabiano Rosas gen_helper_neon_##OP##l_u16, \ 1777f0984d40SFabiano Rosas gen_helper_neon_##OP##l_u32, \ 1778f0984d40SFabiano Rosas tcg_gen_##OP##_i64, \ 1779f0984d40SFabiano Rosas NULL, \ 1780f0984d40SFabiano Rosas }; \ 1781f0984d40SFabiano Rosas static NeonGenNarrowFn * const narrowfn[] = { \ 1782f0984d40SFabiano Rosas gen_helper_neon_##NARROWTYPE##_high_u8, \ 1783f0984d40SFabiano Rosas gen_helper_neon_##NARROWTYPE##_high_u16, \ 1784f0984d40SFabiano Rosas EXTOP, \ 1785f0984d40SFabiano Rosas NULL, \ 1786f0984d40SFabiano Rosas }; \ 1787f0984d40SFabiano Rosas return do_narrow_3d(s, a, addfn[a->size], narrowfn[a->size]); \ 1788f0984d40SFabiano Rosas } 1789f0984d40SFabiano Rosas 1790f0984d40SFabiano Rosas static void gen_narrow_round_high_u32(TCGv_i32 rd, TCGv_i64 rn) 1791f0984d40SFabiano Rosas { 1792f0984d40SFabiano Rosas tcg_gen_addi_i64(rn, rn, 1u << 31); 1793f0984d40SFabiano Rosas tcg_gen_extrh_i64_i32(rd, rn); 1794f0984d40SFabiano Rosas } 1795f0984d40SFabiano Rosas 1796f0984d40SFabiano Rosas DO_NARROW_3D(VADDHN, add, narrow, tcg_gen_extrh_i64_i32) 1797f0984d40SFabiano Rosas DO_NARROW_3D(VSUBHN, sub, narrow, tcg_gen_extrh_i64_i32) 1798f0984d40SFabiano Rosas DO_NARROW_3D(VRADDHN, add, narrow_round, gen_narrow_round_high_u32) 1799f0984d40SFabiano Rosas DO_NARROW_3D(VRSUBHN, sub, narrow_round, gen_narrow_round_high_u32) 1800f0984d40SFabiano Rosas 1801f0984d40SFabiano Rosas static bool do_long_3d(DisasContext *s, arg_3diff *a, 1802f0984d40SFabiano Rosas NeonGenTwoOpWidenFn *opfn, 1803f0984d40SFabiano Rosas NeonGenTwo64OpFn *accfn) 1804f0984d40SFabiano Rosas { 1805f0984d40SFabiano Rosas /* 1806f0984d40SFabiano Rosas * 3-regs different lengths, long operations. 1807f0984d40SFabiano Rosas * These perform an operation on two inputs that returns a double-width 1808f0984d40SFabiano Rosas * result, and then possibly perform an accumulation operation of 1809f0984d40SFabiano Rosas * that result into the double-width destination. 1810f0984d40SFabiano Rosas */ 1811f0984d40SFabiano Rosas TCGv_i64 rd0, rd1, tmp; 1812f0984d40SFabiano Rosas TCGv_i32 rn, rm; 1813f0984d40SFabiano Rosas 1814f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 1815f0984d40SFabiano Rosas return false; 1816f0984d40SFabiano Rosas } 1817f0984d40SFabiano Rosas 1818f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 1819f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 1820f0984d40SFabiano Rosas ((a->vd | a->vn | a->vm) & 0x10)) { 1821f0984d40SFabiano Rosas return false; 1822f0984d40SFabiano Rosas } 1823f0984d40SFabiano Rosas 1824f0984d40SFabiano Rosas if (!opfn) { 1825f0984d40SFabiano Rosas /* size == 3 case, which is an entirely different insn group */ 1826f0984d40SFabiano Rosas return false; 1827f0984d40SFabiano Rosas } 1828f0984d40SFabiano Rosas 1829f0984d40SFabiano Rosas if (a->vd & 1) { 1830f0984d40SFabiano Rosas return false; 1831f0984d40SFabiano Rosas } 1832f0984d40SFabiano Rosas 1833f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 1834f0984d40SFabiano Rosas return true; 1835f0984d40SFabiano Rosas } 1836f0984d40SFabiano Rosas 1837f0984d40SFabiano Rosas rd0 = tcg_temp_new_i64(); 1838f0984d40SFabiano Rosas rd1 = tcg_temp_new_i64(); 1839f0984d40SFabiano Rosas 1840f0984d40SFabiano Rosas rn = tcg_temp_new_i32(); 1841f0984d40SFabiano Rosas rm = tcg_temp_new_i32(); 1842f0984d40SFabiano Rosas read_neon_element32(rn, a->vn, 0, MO_32); 1843f0984d40SFabiano Rosas read_neon_element32(rm, a->vm, 0, MO_32); 1844f0984d40SFabiano Rosas opfn(rd0, rn, rm); 1845f0984d40SFabiano Rosas 1846f0984d40SFabiano Rosas read_neon_element32(rn, a->vn, 1, MO_32); 1847f0984d40SFabiano Rosas read_neon_element32(rm, a->vm, 1, MO_32); 1848f0984d40SFabiano Rosas opfn(rd1, rn, rm); 1849f0984d40SFabiano Rosas 1850f0984d40SFabiano Rosas /* Don't store results until after all loads: they might overlap */ 1851f0984d40SFabiano Rosas if (accfn) { 1852f0984d40SFabiano Rosas tmp = tcg_temp_new_i64(); 1853f0984d40SFabiano Rosas read_neon_element64(tmp, a->vd, 0, MO_64); 1854f0984d40SFabiano Rosas accfn(rd0, tmp, rd0); 1855f0984d40SFabiano Rosas read_neon_element64(tmp, a->vd, 1, MO_64); 1856f0984d40SFabiano Rosas accfn(rd1, tmp, rd1); 1857f0984d40SFabiano Rosas } 1858f0984d40SFabiano Rosas 1859f0984d40SFabiano Rosas write_neon_element64(rd0, a->vd, 0, MO_64); 1860f0984d40SFabiano Rosas write_neon_element64(rd1, a->vd, 1, MO_64); 1861f0984d40SFabiano Rosas 1862f0984d40SFabiano Rosas return true; 1863f0984d40SFabiano Rosas } 1864f0984d40SFabiano Rosas 1865f0984d40SFabiano Rosas static bool trans_VABDL_S_3d(DisasContext *s, arg_3diff *a) 1866f0984d40SFabiano Rosas { 1867f0984d40SFabiano Rosas static NeonGenTwoOpWidenFn * const opfn[] = { 1868f0984d40SFabiano Rosas gen_helper_neon_abdl_s16, 1869f0984d40SFabiano Rosas gen_helper_neon_abdl_s32, 1870f0984d40SFabiano Rosas gen_helper_neon_abdl_s64, 1871f0984d40SFabiano Rosas NULL, 1872f0984d40SFabiano Rosas }; 1873f0984d40SFabiano Rosas 1874f0984d40SFabiano Rosas return do_long_3d(s, a, opfn[a->size], NULL); 1875f0984d40SFabiano Rosas } 1876f0984d40SFabiano Rosas 1877f0984d40SFabiano Rosas static bool trans_VABDL_U_3d(DisasContext *s, arg_3diff *a) 1878f0984d40SFabiano Rosas { 1879f0984d40SFabiano Rosas static NeonGenTwoOpWidenFn * const opfn[] = { 1880f0984d40SFabiano Rosas gen_helper_neon_abdl_u16, 1881f0984d40SFabiano Rosas gen_helper_neon_abdl_u32, 1882f0984d40SFabiano Rosas gen_helper_neon_abdl_u64, 1883f0984d40SFabiano Rosas NULL, 1884f0984d40SFabiano Rosas }; 1885f0984d40SFabiano Rosas 1886f0984d40SFabiano Rosas return do_long_3d(s, a, opfn[a->size], NULL); 1887f0984d40SFabiano Rosas } 1888f0984d40SFabiano Rosas 1889f0984d40SFabiano Rosas static bool trans_VABAL_S_3d(DisasContext *s, arg_3diff *a) 1890f0984d40SFabiano Rosas { 1891f0984d40SFabiano Rosas static NeonGenTwoOpWidenFn * const opfn[] = { 1892f0984d40SFabiano Rosas gen_helper_neon_abdl_s16, 1893f0984d40SFabiano Rosas gen_helper_neon_abdl_s32, 1894f0984d40SFabiano Rosas gen_helper_neon_abdl_s64, 1895f0984d40SFabiano Rosas NULL, 1896f0984d40SFabiano Rosas }; 1897f0984d40SFabiano Rosas static NeonGenTwo64OpFn * const addfn[] = { 1898f0984d40SFabiano Rosas gen_helper_neon_addl_u16, 1899f0984d40SFabiano Rosas gen_helper_neon_addl_u32, 1900f0984d40SFabiano Rosas tcg_gen_add_i64, 1901f0984d40SFabiano Rosas NULL, 1902f0984d40SFabiano Rosas }; 1903f0984d40SFabiano Rosas 1904f0984d40SFabiano Rosas return do_long_3d(s, a, opfn[a->size], addfn[a->size]); 1905f0984d40SFabiano Rosas } 1906f0984d40SFabiano Rosas 1907f0984d40SFabiano Rosas static bool trans_VABAL_U_3d(DisasContext *s, arg_3diff *a) 1908f0984d40SFabiano Rosas { 1909f0984d40SFabiano Rosas static NeonGenTwoOpWidenFn * const opfn[] = { 1910f0984d40SFabiano Rosas gen_helper_neon_abdl_u16, 1911f0984d40SFabiano Rosas gen_helper_neon_abdl_u32, 1912f0984d40SFabiano Rosas gen_helper_neon_abdl_u64, 1913f0984d40SFabiano Rosas NULL, 1914f0984d40SFabiano Rosas }; 1915f0984d40SFabiano Rosas static NeonGenTwo64OpFn * const addfn[] = { 1916f0984d40SFabiano Rosas gen_helper_neon_addl_u16, 1917f0984d40SFabiano Rosas gen_helper_neon_addl_u32, 1918f0984d40SFabiano Rosas tcg_gen_add_i64, 1919f0984d40SFabiano Rosas NULL, 1920f0984d40SFabiano Rosas }; 1921f0984d40SFabiano Rosas 1922f0984d40SFabiano Rosas return do_long_3d(s, a, opfn[a->size], addfn[a->size]); 1923f0984d40SFabiano Rosas } 1924f0984d40SFabiano Rosas 1925f0984d40SFabiano Rosas static void gen_mull_s32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) 1926f0984d40SFabiano Rosas { 1927f0984d40SFabiano Rosas TCGv_i32 lo = tcg_temp_new_i32(); 1928f0984d40SFabiano Rosas TCGv_i32 hi = tcg_temp_new_i32(); 1929f0984d40SFabiano Rosas 1930f0984d40SFabiano Rosas tcg_gen_muls2_i32(lo, hi, rn, rm); 1931f0984d40SFabiano Rosas tcg_gen_concat_i32_i64(rd, lo, hi); 1932f0984d40SFabiano Rosas } 1933f0984d40SFabiano Rosas 1934f0984d40SFabiano Rosas static void gen_mull_u32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) 1935f0984d40SFabiano Rosas { 1936f0984d40SFabiano Rosas TCGv_i32 lo = tcg_temp_new_i32(); 1937f0984d40SFabiano Rosas TCGv_i32 hi = tcg_temp_new_i32(); 1938f0984d40SFabiano Rosas 1939f0984d40SFabiano Rosas tcg_gen_mulu2_i32(lo, hi, rn, rm); 1940f0984d40SFabiano Rosas tcg_gen_concat_i32_i64(rd, lo, hi); 1941f0984d40SFabiano Rosas } 1942f0984d40SFabiano Rosas 1943f0984d40SFabiano Rosas static bool trans_VMULL_S_3d(DisasContext *s, arg_3diff *a) 1944f0984d40SFabiano Rosas { 1945f0984d40SFabiano Rosas static NeonGenTwoOpWidenFn * const opfn[] = { 1946f0984d40SFabiano Rosas gen_helper_neon_mull_s8, 1947f0984d40SFabiano Rosas gen_helper_neon_mull_s16, 1948f0984d40SFabiano Rosas gen_mull_s32, 1949f0984d40SFabiano Rosas NULL, 1950f0984d40SFabiano Rosas }; 1951f0984d40SFabiano Rosas 1952f0984d40SFabiano Rosas return do_long_3d(s, a, opfn[a->size], NULL); 1953f0984d40SFabiano Rosas } 1954f0984d40SFabiano Rosas 1955f0984d40SFabiano Rosas static bool trans_VMULL_U_3d(DisasContext *s, arg_3diff *a) 1956f0984d40SFabiano Rosas { 1957f0984d40SFabiano Rosas static NeonGenTwoOpWidenFn * const opfn[] = { 1958f0984d40SFabiano Rosas gen_helper_neon_mull_u8, 1959f0984d40SFabiano Rosas gen_helper_neon_mull_u16, 1960f0984d40SFabiano Rosas gen_mull_u32, 1961f0984d40SFabiano Rosas NULL, 1962f0984d40SFabiano Rosas }; 1963f0984d40SFabiano Rosas 1964f0984d40SFabiano Rosas return do_long_3d(s, a, opfn[a->size], NULL); 1965f0984d40SFabiano Rosas } 1966f0984d40SFabiano Rosas 1967f0984d40SFabiano Rosas #define DO_VMLAL(INSN,MULL,ACC) \ 1968f0984d40SFabiano Rosas static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \ 1969f0984d40SFabiano Rosas { \ 1970f0984d40SFabiano Rosas static NeonGenTwoOpWidenFn * const opfn[] = { \ 1971f0984d40SFabiano Rosas gen_helper_neon_##MULL##8, \ 1972f0984d40SFabiano Rosas gen_helper_neon_##MULL##16, \ 1973f0984d40SFabiano Rosas gen_##MULL##32, \ 1974f0984d40SFabiano Rosas NULL, \ 1975f0984d40SFabiano Rosas }; \ 1976f0984d40SFabiano Rosas static NeonGenTwo64OpFn * const accfn[] = { \ 1977f0984d40SFabiano Rosas gen_helper_neon_##ACC##l_u16, \ 1978f0984d40SFabiano Rosas gen_helper_neon_##ACC##l_u32, \ 1979f0984d40SFabiano Rosas tcg_gen_##ACC##_i64, \ 1980f0984d40SFabiano Rosas NULL, \ 1981f0984d40SFabiano Rosas }; \ 1982f0984d40SFabiano Rosas return do_long_3d(s, a, opfn[a->size], accfn[a->size]); \ 1983f0984d40SFabiano Rosas } 1984f0984d40SFabiano Rosas 1985f0984d40SFabiano Rosas DO_VMLAL(VMLAL_S,mull_s,add) 1986f0984d40SFabiano Rosas DO_VMLAL(VMLAL_U,mull_u,add) 1987f0984d40SFabiano Rosas DO_VMLAL(VMLSL_S,mull_s,sub) 1988f0984d40SFabiano Rosas DO_VMLAL(VMLSL_U,mull_u,sub) 1989f0984d40SFabiano Rosas 1990f0984d40SFabiano Rosas static void gen_VQDMULL_16(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) 1991f0984d40SFabiano Rosas { 1992f0984d40SFabiano Rosas gen_helper_neon_mull_s16(rd, rn, rm); 1993ad75a51eSRichard Henderson gen_helper_neon_addl_saturate_s32(rd, tcg_env, rd, rd); 1994f0984d40SFabiano Rosas } 1995f0984d40SFabiano Rosas 1996f0984d40SFabiano Rosas static void gen_VQDMULL_32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) 1997f0984d40SFabiano Rosas { 1998f0984d40SFabiano Rosas gen_mull_s32(rd, rn, rm); 1999ad75a51eSRichard Henderson gen_helper_neon_addl_saturate_s64(rd, tcg_env, rd, rd); 2000f0984d40SFabiano Rosas } 2001f0984d40SFabiano Rosas 2002f0984d40SFabiano Rosas static bool trans_VQDMULL_3d(DisasContext *s, arg_3diff *a) 2003f0984d40SFabiano Rosas { 2004f0984d40SFabiano Rosas static NeonGenTwoOpWidenFn * const opfn[] = { 2005f0984d40SFabiano Rosas NULL, 2006f0984d40SFabiano Rosas gen_VQDMULL_16, 2007f0984d40SFabiano Rosas gen_VQDMULL_32, 2008f0984d40SFabiano Rosas NULL, 2009f0984d40SFabiano Rosas }; 2010f0984d40SFabiano Rosas 2011f0984d40SFabiano Rosas return do_long_3d(s, a, opfn[a->size], NULL); 2012f0984d40SFabiano Rosas } 2013f0984d40SFabiano Rosas 2014f0984d40SFabiano Rosas static void gen_VQDMLAL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) 2015f0984d40SFabiano Rosas { 2016ad75a51eSRichard Henderson gen_helper_neon_addl_saturate_s32(rd, tcg_env, rn, rm); 2017f0984d40SFabiano Rosas } 2018f0984d40SFabiano Rosas 2019f0984d40SFabiano Rosas static void gen_VQDMLAL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) 2020f0984d40SFabiano Rosas { 2021ad75a51eSRichard Henderson gen_helper_neon_addl_saturate_s64(rd, tcg_env, rn, rm); 2022f0984d40SFabiano Rosas } 2023f0984d40SFabiano Rosas 2024f0984d40SFabiano Rosas static bool trans_VQDMLAL_3d(DisasContext *s, arg_3diff *a) 2025f0984d40SFabiano Rosas { 2026f0984d40SFabiano Rosas static NeonGenTwoOpWidenFn * const opfn[] = { 2027f0984d40SFabiano Rosas NULL, 2028f0984d40SFabiano Rosas gen_VQDMULL_16, 2029f0984d40SFabiano Rosas gen_VQDMULL_32, 2030f0984d40SFabiano Rosas NULL, 2031f0984d40SFabiano Rosas }; 2032f0984d40SFabiano Rosas static NeonGenTwo64OpFn * const accfn[] = { 2033f0984d40SFabiano Rosas NULL, 2034f0984d40SFabiano Rosas gen_VQDMLAL_acc_16, 2035f0984d40SFabiano Rosas gen_VQDMLAL_acc_32, 2036f0984d40SFabiano Rosas NULL, 2037f0984d40SFabiano Rosas }; 2038f0984d40SFabiano Rosas 2039f0984d40SFabiano Rosas return do_long_3d(s, a, opfn[a->size], accfn[a->size]); 2040f0984d40SFabiano Rosas } 2041f0984d40SFabiano Rosas 2042f0984d40SFabiano Rosas static void gen_VQDMLSL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) 2043f0984d40SFabiano Rosas { 2044f0984d40SFabiano Rosas gen_helper_neon_negl_u32(rm, rm); 2045ad75a51eSRichard Henderson gen_helper_neon_addl_saturate_s32(rd, tcg_env, rn, rm); 2046f0984d40SFabiano Rosas } 2047f0984d40SFabiano Rosas 2048f0984d40SFabiano Rosas static void gen_VQDMLSL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) 2049f0984d40SFabiano Rosas { 2050f0984d40SFabiano Rosas tcg_gen_neg_i64(rm, rm); 2051ad75a51eSRichard Henderson gen_helper_neon_addl_saturate_s64(rd, tcg_env, rn, rm); 2052f0984d40SFabiano Rosas } 2053f0984d40SFabiano Rosas 2054f0984d40SFabiano Rosas static bool trans_VQDMLSL_3d(DisasContext *s, arg_3diff *a) 2055f0984d40SFabiano Rosas { 2056f0984d40SFabiano Rosas static NeonGenTwoOpWidenFn * const opfn[] = { 2057f0984d40SFabiano Rosas NULL, 2058f0984d40SFabiano Rosas gen_VQDMULL_16, 2059f0984d40SFabiano Rosas gen_VQDMULL_32, 2060f0984d40SFabiano Rosas NULL, 2061f0984d40SFabiano Rosas }; 2062f0984d40SFabiano Rosas static NeonGenTwo64OpFn * const accfn[] = { 2063f0984d40SFabiano Rosas NULL, 2064f0984d40SFabiano Rosas gen_VQDMLSL_acc_16, 2065f0984d40SFabiano Rosas gen_VQDMLSL_acc_32, 2066f0984d40SFabiano Rosas NULL, 2067f0984d40SFabiano Rosas }; 2068f0984d40SFabiano Rosas 2069f0984d40SFabiano Rosas return do_long_3d(s, a, opfn[a->size], accfn[a->size]); 2070f0984d40SFabiano Rosas } 2071f0984d40SFabiano Rosas 2072f0984d40SFabiano Rosas static bool trans_VMULL_P_3d(DisasContext *s, arg_3diff *a) 2073f0984d40SFabiano Rosas { 2074f0984d40SFabiano Rosas gen_helper_gvec_3 *fn_gvec; 2075f0984d40SFabiano Rosas 2076f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 2077f0984d40SFabiano Rosas return false; 2078f0984d40SFabiano Rosas } 2079f0984d40SFabiano Rosas 2080f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 2081f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 2082f0984d40SFabiano Rosas ((a->vd | a->vn | a->vm) & 0x10)) { 2083f0984d40SFabiano Rosas return false; 2084f0984d40SFabiano Rosas } 2085f0984d40SFabiano Rosas 2086f0984d40SFabiano Rosas if (a->vd & 1) { 2087f0984d40SFabiano Rosas return false; 2088f0984d40SFabiano Rosas } 2089f0984d40SFabiano Rosas 2090f0984d40SFabiano Rosas switch (a->size) { 2091f0984d40SFabiano Rosas case 0: 2092f0984d40SFabiano Rosas fn_gvec = gen_helper_neon_pmull_h; 2093f0984d40SFabiano Rosas break; 2094f0984d40SFabiano Rosas case 2: 2095f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_pmull, s)) { 2096f0984d40SFabiano Rosas return false; 2097f0984d40SFabiano Rosas } 2098f0984d40SFabiano Rosas fn_gvec = gen_helper_gvec_pmull_q; 2099f0984d40SFabiano Rosas break; 2100f0984d40SFabiano Rosas default: 2101f0984d40SFabiano Rosas return false; 2102f0984d40SFabiano Rosas } 2103f0984d40SFabiano Rosas 2104f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 2105f0984d40SFabiano Rosas return true; 2106f0984d40SFabiano Rosas } 2107f0984d40SFabiano Rosas 2108f0984d40SFabiano Rosas tcg_gen_gvec_3_ool(neon_full_reg_offset(a->vd), 2109f0984d40SFabiano Rosas neon_full_reg_offset(a->vn), 2110f0984d40SFabiano Rosas neon_full_reg_offset(a->vm), 2111f0984d40SFabiano Rosas 16, 16, 0, fn_gvec); 2112f0984d40SFabiano Rosas return true; 2113f0984d40SFabiano Rosas } 2114f0984d40SFabiano Rosas 2115f0984d40SFabiano Rosas static void gen_neon_dup_low16(TCGv_i32 var) 2116f0984d40SFabiano Rosas { 2117f0984d40SFabiano Rosas TCGv_i32 tmp = tcg_temp_new_i32(); 2118f0984d40SFabiano Rosas tcg_gen_ext16u_i32(var, var); 2119f0984d40SFabiano Rosas tcg_gen_shli_i32(tmp, var, 16); 2120f0984d40SFabiano Rosas tcg_gen_or_i32(var, var, tmp); 2121f0984d40SFabiano Rosas } 2122f0984d40SFabiano Rosas 2123f0984d40SFabiano Rosas static void gen_neon_dup_high16(TCGv_i32 var) 2124f0984d40SFabiano Rosas { 2125f0984d40SFabiano Rosas TCGv_i32 tmp = tcg_temp_new_i32(); 2126f0984d40SFabiano Rosas tcg_gen_andi_i32(var, var, 0xffff0000); 2127f0984d40SFabiano Rosas tcg_gen_shri_i32(tmp, var, 16); 2128f0984d40SFabiano Rosas tcg_gen_or_i32(var, var, tmp); 2129f0984d40SFabiano Rosas } 2130f0984d40SFabiano Rosas 2131f0984d40SFabiano Rosas static inline TCGv_i32 neon_get_scalar(int size, int reg) 2132f0984d40SFabiano Rosas { 2133f0984d40SFabiano Rosas TCGv_i32 tmp = tcg_temp_new_i32(); 2134f0984d40SFabiano Rosas if (size == MO_16) { 2135f0984d40SFabiano Rosas read_neon_element32(tmp, reg & 7, reg >> 4, MO_32); 2136f0984d40SFabiano Rosas if (reg & 8) { 2137f0984d40SFabiano Rosas gen_neon_dup_high16(tmp); 2138f0984d40SFabiano Rosas } else { 2139f0984d40SFabiano Rosas gen_neon_dup_low16(tmp); 2140f0984d40SFabiano Rosas } 2141f0984d40SFabiano Rosas } else { 2142f0984d40SFabiano Rosas read_neon_element32(tmp, reg & 15, reg >> 4, MO_32); 2143f0984d40SFabiano Rosas } 2144f0984d40SFabiano Rosas return tmp; 2145f0984d40SFabiano Rosas } 2146f0984d40SFabiano Rosas 2147f0984d40SFabiano Rosas static bool do_2scalar(DisasContext *s, arg_2scalar *a, 2148f0984d40SFabiano Rosas NeonGenTwoOpFn *opfn, NeonGenTwoOpFn *accfn) 2149f0984d40SFabiano Rosas { 2150f0984d40SFabiano Rosas /* 2151f0984d40SFabiano Rosas * Two registers and a scalar: perform an operation between 2152f0984d40SFabiano Rosas * the input elements and the scalar, and then possibly 2153f0984d40SFabiano Rosas * perform an accumulation operation of that result into the 2154f0984d40SFabiano Rosas * destination. 2155f0984d40SFabiano Rosas */ 2156f0984d40SFabiano Rosas TCGv_i32 scalar, tmp; 2157f0984d40SFabiano Rosas int pass; 2158f0984d40SFabiano Rosas 2159f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 2160f0984d40SFabiano Rosas return false; 2161f0984d40SFabiano Rosas } 2162f0984d40SFabiano Rosas 2163f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 2164f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 2165f0984d40SFabiano Rosas ((a->vd | a->vn | a->vm) & 0x10)) { 2166f0984d40SFabiano Rosas return false; 2167f0984d40SFabiano Rosas } 2168f0984d40SFabiano Rosas 2169f0984d40SFabiano Rosas if (!opfn) { 2170f0984d40SFabiano Rosas /* Bad size (including size == 3, which is a different insn group) */ 2171f0984d40SFabiano Rosas return false; 2172f0984d40SFabiano Rosas } 2173f0984d40SFabiano Rosas 2174f0984d40SFabiano Rosas if (a->q && ((a->vd | a->vn) & 1)) { 2175f0984d40SFabiano Rosas return false; 2176f0984d40SFabiano Rosas } 2177f0984d40SFabiano Rosas 2178f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 2179f0984d40SFabiano Rosas return true; 2180f0984d40SFabiano Rosas } 2181f0984d40SFabiano Rosas 2182f0984d40SFabiano Rosas scalar = neon_get_scalar(a->size, a->vm); 2183f0984d40SFabiano Rosas tmp = tcg_temp_new_i32(); 2184f0984d40SFabiano Rosas 2185f0984d40SFabiano Rosas for (pass = 0; pass < (a->q ? 4 : 2); pass++) { 2186f0984d40SFabiano Rosas read_neon_element32(tmp, a->vn, pass, MO_32); 2187f0984d40SFabiano Rosas opfn(tmp, tmp, scalar); 2188f0984d40SFabiano Rosas if (accfn) { 2189f0984d40SFabiano Rosas TCGv_i32 rd = tcg_temp_new_i32(); 2190f0984d40SFabiano Rosas read_neon_element32(rd, a->vd, pass, MO_32); 2191f0984d40SFabiano Rosas accfn(tmp, rd, tmp); 2192f0984d40SFabiano Rosas } 2193f0984d40SFabiano Rosas write_neon_element32(tmp, a->vd, pass, MO_32); 2194f0984d40SFabiano Rosas } 2195f0984d40SFabiano Rosas return true; 2196f0984d40SFabiano Rosas } 2197f0984d40SFabiano Rosas 2198f0984d40SFabiano Rosas static bool trans_VMUL_2sc(DisasContext *s, arg_2scalar *a) 2199f0984d40SFabiano Rosas { 2200f0984d40SFabiano Rosas static NeonGenTwoOpFn * const opfn[] = { 2201f0984d40SFabiano Rosas NULL, 2202f0984d40SFabiano Rosas gen_helper_neon_mul_u16, 2203f0984d40SFabiano Rosas tcg_gen_mul_i32, 2204f0984d40SFabiano Rosas NULL, 2205f0984d40SFabiano Rosas }; 2206f0984d40SFabiano Rosas 2207f0984d40SFabiano Rosas return do_2scalar(s, a, opfn[a->size], NULL); 2208f0984d40SFabiano Rosas } 2209f0984d40SFabiano Rosas 2210f0984d40SFabiano Rosas static bool trans_VMLA_2sc(DisasContext *s, arg_2scalar *a) 2211f0984d40SFabiano Rosas { 2212f0984d40SFabiano Rosas static NeonGenTwoOpFn * const opfn[] = { 2213f0984d40SFabiano Rosas NULL, 2214f0984d40SFabiano Rosas gen_helper_neon_mul_u16, 2215f0984d40SFabiano Rosas tcg_gen_mul_i32, 2216f0984d40SFabiano Rosas NULL, 2217f0984d40SFabiano Rosas }; 2218f0984d40SFabiano Rosas static NeonGenTwoOpFn * const accfn[] = { 2219f0984d40SFabiano Rosas NULL, 2220f0984d40SFabiano Rosas gen_helper_neon_add_u16, 2221f0984d40SFabiano Rosas tcg_gen_add_i32, 2222f0984d40SFabiano Rosas NULL, 2223f0984d40SFabiano Rosas }; 2224f0984d40SFabiano Rosas 2225f0984d40SFabiano Rosas return do_2scalar(s, a, opfn[a->size], accfn[a->size]); 2226f0984d40SFabiano Rosas } 2227f0984d40SFabiano Rosas 2228f0984d40SFabiano Rosas static bool trans_VMLS_2sc(DisasContext *s, arg_2scalar *a) 2229f0984d40SFabiano Rosas { 2230f0984d40SFabiano Rosas static NeonGenTwoOpFn * const opfn[] = { 2231f0984d40SFabiano Rosas NULL, 2232f0984d40SFabiano Rosas gen_helper_neon_mul_u16, 2233f0984d40SFabiano Rosas tcg_gen_mul_i32, 2234f0984d40SFabiano Rosas NULL, 2235f0984d40SFabiano Rosas }; 2236f0984d40SFabiano Rosas static NeonGenTwoOpFn * const accfn[] = { 2237f0984d40SFabiano Rosas NULL, 2238f0984d40SFabiano Rosas gen_helper_neon_sub_u16, 2239f0984d40SFabiano Rosas tcg_gen_sub_i32, 2240f0984d40SFabiano Rosas NULL, 2241f0984d40SFabiano Rosas }; 2242f0984d40SFabiano Rosas 2243f0984d40SFabiano Rosas return do_2scalar(s, a, opfn[a->size], accfn[a->size]); 2244f0984d40SFabiano Rosas } 2245f0984d40SFabiano Rosas 2246f0984d40SFabiano Rosas static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a, 2247f0984d40SFabiano Rosas gen_helper_gvec_3_ptr *fn) 2248f0984d40SFabiano Rosas { 2249f0984d40SFabiano Rosas /* Two registers and a scalar, using gvec */ 2250f0984d40SFabiano Rosas int vec_size = a->q ? 16 : 8; 2251f0984d40SFabiano Rosas int rd_ofs = neon_full_reg_offset(a->vd); 2252f0984d40SFabiano Rosas int rn_ofs = neon_full_reg_offset(a->vn); 2253f0984d40SFabiano Rosas int rm_ofs; 2254f0984d40SFabiano Rosas int idx; 2255f0984d40SFabiano Rosas TCGv_ptr fpstatus; 2256f0984d40SFabiano Rosas 2257f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 2258f0984d40SFabiano Rosas return false; 2259f0984d40SFabiano Rosas } 2260f0984d40SFabiano Rosas 2261f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 2262f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 2263f0984d40SFabiano Rosas ((a->vd | a->vn | a->vm) & 0x10)) { 2264f0984d40SFabiano Rosas return false; 2265f0984d40SFabiano Rosas } 2266f0984d40SFabiano Rosas 2267f0984d40SFabiano Rosas if (!fn) { 2268f0984d40SFabiano Rosas /* Bad size (including size == 3, which is a different insn group) */ 2269f0984d40SFabiano Rosas return false; 2270f0984d40SFabiano Rosas } 2271f0984d40SFabiano Rosas 2272f0984d40SFabiano Rosas if (a->q && ((a->vd | a->vn) & 1)) { 2273f0984d40SFabiano Rosas return false; 2274f0984d40SFabiano Rosas } 2275f0984d40SFabiano Rosas 2276f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 2277f0984d40SFabiano Rosas return true; 2278f0984d40SFabiano Rosas } 2279f0984d40SFabiano Rosas 2280f0984d40SFabiano Rosas /* a->vm is M:Vm, which encodes both register and index */ 2281f0984d40SFabiano Rosas idx = extract32(a->vm, a->size + 2, 2); 2282f0984d40SFabiano Rosas a->vm = extract32(a->vm, 0, a->size + 2); 2283f0984d40SFabiano Rosas rm_ofs = neon_full_reg_offset(a->vm); 2284f0984d40SFabiano Rosas 2285f0984d40SFabiano Rosas fpstatus = fpstatus_ptr(a->size == 1 ? FPST_STD_F16 : FPST_STD); 2286f0984d40SFabiano Rosas tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpstatus, 2287f0984d40SFabiano Rosas vec_size, vec_size, idx, fn); 2288f0984d40SFabiano Rosas return true; 2289f0984d40SFabiano Rosas } 2290f0984d40SFabiano Rosas 2291f0984d40SFabiano Rosas #define DO_VMUL_F_2sc(NAME, FUNC) \ 2292f0984d40SFabiano Rosas static bool trans_##NAME##_F_2sc(DisasContext *s, arg_2scalar *a) \ 2293f0984d40SFabiano Rosas { \ 2294f0984d40SFabiano Rosas static gen_helper_gvec_3_ptr * const opfn[] = { \ 2295f0984d40SFabiano Rosas NULL, \ 2296f0984d40SFabiano Rosas gen_helper_##FUNC##_h, \ 2297f0984d40SFabiano Rosas gen_helper_##FUNC##_s, \ 2298f0984d40SFabiano Rosas NULL, \ 2299f0984d40SFabiano Rosas }; \ 2300f0984d40SFabiano Rosas if (a->size == MO_16 && !dc_isar_feature(aa32_fp16_arith, s)) { \ 2301f0984d40SFabiano Rosas return false; \ 2302f0984d40SFabiano Rosas } \ 2303f0984d40SFabiano Rosas return do_2scalar_fp_vec(s, a, opfn[a->size]); \ 2304f0984d40SFabiano Rosas } 2305f0984d40SFabiano Rosas 2306f0984d40SFabiano Rosas DO_VMUL_F_2sc(VMUL, gvec_fmul_idx) 2307f0984d40SFabiano Rosas DO_VMUL_F_2sc(VMLA, gvec_fmla_nf_idx) 2308f0984d40SFabiano Rosas DO_VMUL_F_2sc(VMLS, gvec_fmls_nf_idx) 2309f0984d40SFabiano Rosas 2310f0984d40SFabiano Rosas WRAP_ENV_FN(gen_VQDMULH_16, gen_helper_neon_qdmulh_s16) 2311f0984d40SFabiano Rosas WRAP_ENV_FN(gen_VQDMULH_32, gen_helper_neon_qdmulh_s32) 2312f0984d40SFabiano Rosas WRAP_ENV_FN(gen_VQRDMULH_16, gen_helper_neon_qrdmulh_s16) 2313f0984d40SFabiano Rosas WRAP_ENV_FN(gen_VQRDMULH_32, gen_helper_neon_qrdmulh_s32) 2314f0984d40SFabiano Rosas 2315f0984d40SFabiano Rosas static bool trans_VQDMULH_2sc(DisasContext *s, arg_2scalar *a) 2316f0984d40SFabiano Rosas { 2317f0984d40SFabiano Rosas static NeonGenTwoOpFn * const opfn[] = { 2318f0984d40SFabiano Rosas NULL, 2319f0984d40SFabiano Rosas gen_VQDMULH_16, 2320f0984d40SFabiano Rosas gen_VQDMULH_32, 2321f0984d40SFabiano Rosas NULL, 2322f0984d40SFabiano Rosas }; 2323f0984d40SFabiano Rosas 2324f0984d40SFabiano Rosas return do_2scalar(s, a, opfn[a->size], NULL); 2325f0984d40SFabiano Rosas } 2326f0984d40SFabiano Rosas 2327f0984d40SFabiano Rosas static bool trans_VQRDMULH_2sc(DisasContext *s, arg_2scalar *a) 2328f0984d40SFabiano Rosas { 2329f0984d40SFabiano Rosas static NeonGenTwoOpFn * const opfn[] = { 2330f0984d40SFabiano Rosas NULL, 2331f0984d40SFabiano Rosas gen_VQRDMULH_16, 2332f0984d40SFabiano Rosas gen_VQRDMULH_32, 2333f0984d40SFabiano Rosas NULL, 2334f0984d40SFabiano Rosas }; 2335f0984d40SFabiano Rosas 2336f0984d40SFabiano Rosas return do_2scalar(s, a, opfn[a->size], NULL); 2337f0984d40SFabiano Rosas } 2338f0984d40SFabiano Rosas 2339f0984d40SFabiano Rosas static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a, 2340f0984d40SFabiano Rosas NeonGenThreeOpEnvFn *opfn) 2341f0984d40SFabiano Rosas { 2342f0984d40SFabiano Rosas /* 2343f0984d40SFabiano Rosas * VQRDMLAH/VQRDMLSH: this is like do_2scalar, but the opfn 2344f0984d40SFabiano Rosas * performs a kind of fused op-then-accumulate using a helper 2345f0984d40SFabiano Rosas * function that takes all of rd, rn and the scalar at once. 2346f0984d40SFabiano Rosas */ 2347f0984d40SFabiano Rosas TCGv_i32 scalar, rn, rd; 2348f0984d40SFabiano Rosas int pass; 2349f0984d40SFabiano Rosas 2350f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 2351f0984d40SFabiano Rosas return false; 2352f0984d40SFabiano Rosas } 2353f0984d40SFabiano Rosas 2354f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_rdm, s)) { 2355f0984d40SFabiano Rosas return false; 2356f0984d40SFabiano Rosas } 2357f0984d40SFabiano Rosas 2358f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 2359f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 2360f0984d40SFabiano Rosas ((a->vd | a->vn | a->vm) & 0x10)) { 2361f0984d40SFabiano Rosas return false; 2362f0984d40SFabiano Rosas } 2363f0984d40SFabiano Rosas 2364f0984d40SFabiano Rosas if (!opfn) { 2365f0984d40SFabiano Rosas /* Bad size (including size == 3, which is a different insn group) */ 2366f0984d40SFabiano Rosas return false; 2367f0984d40SFabiano Rosas } 2368f0984d40SFabiano Rosas 2369f0984d40SFabiano Rosas if (a->q && ((a->vd | a->vn) & 1)) { 2370f0984d40SFabiano Rosas return false; 2371f0984d40SFabiano Rosas } 2372f0984d40SFabiano Rosas 2373f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 2374f0984d40SFabiano Rosas return true; 2375f0984d40SFabiano Rosas } 2376f0984d40SFabiano Rosas 2377f0984d40SFabiano Rosas scalar = neon_get_scalar(a->size, a->vm); 2378f0984d40SFabiano Rosas rn = tcg_temp_new_i32(); 2379f0984d40SFabiano Rosas rd = tcg_temp_new_i32(); 2380f0984d40SFabiano Rosas 2381f0984d40SFabiano Rosas for (pass = 0; pass < (a->q ? 4 : 2); pass++) { 2382f0984d40SFabiano Rosas read_neon_element32(rn, a->vn, pass, MO_32); 2383f0984d40SFabiano Rosas read_neon_element32(rd, a->vd, pass, MO_32); 2384ad75a51eSRichard Henderson opfn(rd, tcg_env, rn, scalar, rd); 2385f0984d40SFabiano Rosas write_neon_element32(rd, a->vd, pass, MO_32); 2386f0984d40SFabiano Rosas } 2387f0984d40SFabiano Rosas return true; 2388f0984d40SFabiano Rosas } 2389f0984d40SFabiano Rosas 2390f0984d40SFabiano Rosas static bool trans_VQRDMLAH_2sc(DisasContext *s, arg_2scalar *a) 2391f0984d40SFabiano Rosas { 2392f0984d40SFabiano Rosas static NeonGenThreeOpEnvFn *opfn[] = { 2393f0984d40SFabiano Rosas NULL, 2394f0984d40SFabiano Rosas gen_helper_neon_qrdmlah_s16, 2395f0984d40SFabiano Rosas gen_helper_neon_qrdmlah_s32, 2396f0984d40SFabiano Rosas NULL, 2397f0984d40SFabiano Rosas }; 2398f0984d40SFabiano Rosas return do_vqrdmlah_2sc(s, a, opfn[a->size]); 2399f0984d40SFabiano Rosas } 2400f0984d40SFabiano Rosas 2401f0984d40SFabiano Rosas static bool trans_VQRDMLSH_2sc(DisasContext *s, arg_2scalar *a) 2402f0984d40SFabiano Rosas { 2403f0984d40SFabiano Rosas static NeonGenThreeOpEnvFn *opfn[] = { 2404f0984d40SFabiano Rosas NULL, 2405f0984d40SFabiano Rosas gen_helper_neon_qrdmlsh_s16, 2406f0984d40SFabiano Rosas gen_helper_neon_qrdmlsh_s32, 2407f0984d40SFabiano Rosas NULL, 2408f0984d40SFabiano Rosas }; 2409f0984d40SFabiano Rosas return do_vqrdmlah_2sc(s, a, opfn[a->size]); 2410f0984d40SFabiano Rosas } 2411f0984d40SFabiano Rosas 2412f0984d40SFabiano Rosas static bool do_2scalar_long(DisasContext *s, arg_2scalar *a, 2413f0984d40SFabiano Rosas NeonGenTwoOpWidenFn *opfn, 2414f0984d40SFabiano Rosas NeonGenTwo64OpFn *accfn) 2415f0984d40SFabiano Rosas { 2416f0984d40SFabiano Rosas /* 2417f0984d40SFabiano Rosas * Two registers and a scalar, long operations: perform an 2418f0984d40SFabiano Rosas * operation on the input elements and the scalar which produces 2419f0984d40SFabiano Rosas * a double-width result, and then possibly perform an accumulation 2420f0984d40SFabiano Rosas * operation of that result into the destination. 2421f0984d40SFabiano Rosas */ 2422f0984d40SFabiano Rosas TCGv_i32 scalar, rn; 2423f0984d40SFabiano Rosas TCGv_i64 rn0_64, rn1_64; 2424f0984d40SFabiano Rosas 2425f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 2426f0984d40SFabiano Rosas return false; 2427f0984d40SFabiano Rosas } 2428f0984d40SFabiano Rosas 2429f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 2430f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 2431f0984d40SFabiano Rosas ((a->vd | a->vn | a->vm) & 0x10)) { 2432f0984d40SFabiano Rosas return false; 2433f0984d40SFabiano Rosas } 2434f0984d40SFabiano Rosas 2435f0984d40SFabiano Rosas if (!opfn) { 2436f0984d40SFabiano Rosas /* Bad size (including size == 3, which is a different insn group) */ 2437f0984d40SFabiano Rosas return false; 2438f0984d40SFabiano Rosas } 2439f0984d40SFabiano Rosas 2440f0984d40SFabiano Rosas if (a->vd & 1) { 2441f0984d40SFabiano Rosas return false; 2442f0984d40SFabiano Rosas } 2443f0984d40SFabiano Rosas 2444f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 2445f0984d40SFabiano Rosas return true; 2446f0984d40SFabiano Rosas } 2447f0984d40SFabiano Rosas 2448f0984d40SFabiano Rosas scalar = neon_get_scalar(a->size, a->vm); 2449f0984d40SFabiano Rosas 2450f0984d40SFabiano Rosas /* Load all inputs before writing any outputs, in case of overlap */ 2451f0984d40SFabiano Rosas rn = tcg_temp_new_i32(); 2452f0984d40SFabiano Rosas read_neon_element32(rn, a->vn, 0, MO_32); 2453f0984d40SFabiano Rosas rn0_64 = tcg_temp_new_i64(); 2454f0984d40SFabiano Rosas opfn(rn0_64, rn, scalar); 2455f0984d40SFabiano Rosas 2456f0984d40SFabiano Rosas read_neon_element32(rn, a->vn, 1, MO_32); 2457f0984d40SFabiano Rosas rn1_64 = tcg_temp_new_i64(); 2458f0984d40SFabiano Rosas opfn(rn1_64, rn, scalar); 2459f0984d40SFabiano Rosas 2460f0984d40SFabiano Rosas if (accfn) { 2461f0984d40SFabiano Rosas TCGv_i64 t64 = tcg_temp_new_i64(); 2462f0984d40SFabiano Rosas read_neon_element64(t64, a->vd, 0, MO_64); 2463f0984d40SFabiano Rosas accfn(rn0_64, t64, rn0_64); 2464f0984d40SFabiano Rosas read_neon_element64(t64, a->vd, 1, MO_64); 2465f0984d40SFabiano Rosas accfn(rn1_64, t64, rn1_64); 2466f0984d40SFabiano Rosas } 2467f0984d40SFabiano Rosas 2468f0984d40SFabiano Rosas write_neon_element64(rn0_64, a->vd, 0, MO_64); 2469f0984d40SFabiano Rosas write_neon_element64(rn1_64, a->vd, 1, MO_64); 2470f0984d40SFabiano Rosas return true; 2471f0984d40SFabiano Rosas } 2472f0984d40SFabiano Rosas 2473f0984d40SFabiano Rosas static bool trans_VMULL_S_2sc(DisasContext *s, arg_2scalar *a) 2474f0984d40SFabiano Rosas { 2475f0984d40SFabiano Rosas static NeonGenTwoOpWidenFn * const opfn[] = { 2476f0984d40SFabiano Rosas NULL, 2477f0984d40SFabiano Rosas gen_helper_neon_mull_s16, 2478f0984d40SFabiano Rosas gen_mull_s32, 2479f0984d40SFabiano Rosas NULL, 2480f0984d40SFabiano Rosas }; 2481f0984d40SFabiano Rosas 2482f0984d40SFabiano Rosas return do_2scalar_long(s, a, opfn[a->size], NULL); 2483f0984d40SFabiano Rosas } 2484f0984d40SFabiano Rosas 2485f0984d40SFabiano Rosas static bool trans_VMULL_U_2sc(DisasContext *s, arg_2scalar *a) 2486f0984d40SFabiano Rosas { 2487f0984d40SFabiano Rosas static NeonGenTwoOpWidenFn * const opfn[] = { 2488f0984d40SFabiano Rosas NULL, 2489f0984d40SFabiano Rosas gen_helper_neon_mull_u16, 2490f0984d40SFabiano Rosas gen_mull_u32, 2491f0984d40SFabiano Rosas NULL, 2492f0984d40SFabiano Rosas }; 2493f0984d40SFabiano Rosas 2494f0984d40SFabiano Rosas return do_2scalar_long(s, a, opfn[a->size], NULL); 2495f0984d40SFabiano Rosas } 2496f0984d40SFabiano Rosas 2497f0984d40SFabiano Rosas #define DO_VMLAL_2SC(INSN, MULL, ACC) \ 2498f0984d40SFabiano Rosas static bool trans_##INSN##_2sc(DisasContext *s, arg_2scalar *a) \ 2499f0984d40SFabiano Rosas { \ 2500f0984d40SFabiano Rosas static NeonGenTwoOpWidenFn * const opfn[] = { \ 2501f0984d40SFabiano Rosas NULL, \ 2502f0984d40SFabiano Rosas gen_helper_neon_##MULL##16, \ 2503f0984d40SFabiano Rosas gen_##MULL##32, \ 2504f0984d40SFabiano Rosas NULL, \ 2505f0984d40SFabiano Rosas }; \ 2506f0984d40SFabiano Rosas static NeonGenTwo64OpFn * const accfn[] = { \ 2507f0984d40SFabiano Rosas NULL, \ 2508f0984d40SFabiano Rosas gen_helper_neon_##ACC##l_u32, \ 2509f0984d40SFabiano Rosas tcg_gen_##ACC##_i64, \ 2510f0984d40SFabiano Rosas NULL, \ 2511f0984d40SFabiano Rosas }; \ 2512f0984d40SFabiano Rosas return do_2scalar_long(s, a, opfn[a->size], accfn[a->size]); \ 2513f0984d40SFabiano Rosas } 2514f0984d40SFabiano Rosas 2515f0984d40SFabiano Rosas DO_VMLAL_2SC(VMLAL_S, mull_s, add) 2516f0984d40SFabiano Rosas DO_VMLAL_2SC(VMLAL_U, mull_u, add) 2517f0984d40SFabiano Rosas DO_VMLAL_2SC(VMLSL_S, mull_s, sub) 2518f0984d40SFabiano Rosas DO_VMLAL_2SC(VMLSL_U, mull_u, sub) 2519f0984d40SFabiano Rosas 2520f0984d40SFabiano Rosas static bool trans_VQDMULL_2sc(DisasContext *s, arg_2scalar *a) 2521f0984d40SFabiano Rosas { 2522f0984d40SFabiano Rosas static NeonGenTwoOpWidenFn * const opfn[] = { 2523f0984d40SFabiano Rosas NULL, 2524f0984d40SFabiano Rosas gen_VQDMULL_16, 2525f0984d40SFabiano Rosas gen_VQDMULL_32, 2526f0984d40SFabiano Rosas NULL, 2527f0984d40SFabiano Rosas }; 2528f0984d40SFabiano Rosas 2529f0984d40SFabiano Rosas return do_2scalar_long(s, a, opfn[a->size], NULL); 2530f0984d40SFabiano Rosas } 2531f0984d40SFabiano Rosas 2532f0984d40SFabiano Rosas static bool trans_VQDMLAL_2sc(DisasContext *s, arg_2scalar *a) 2533f0984d40SFabiano Rosas { 2534f0984d40SFabiano Rosas static NeonGenTwoOpWidenFn * const opfn[] = { 2535f0984d40SFabiano Rosas NULL, 2536f0984d40SFabiano Rosas gen_VQDMULL_16, 2537f0984d40SFabiano Rosas gen_VQDMULL_32, 2538f0984d40SFabiano Rosas NULL, 2539f0984d40SFabiano Rosas }; 2540f0984d40SFabiano Rosas static NeonGenTwo64OpFn * const accfn[] = { 2541f0984d40SFabiano Rosas NULL, 2542f0984d40SFabiano Rosas gen_VQDMLAL_acc_16, 2543f0984d40SFabiano Rosas gen_VQDMLAL_acc_32, 2544f0984d40SFabiano Rosas NULL, 2545f0984d40SFabiano Rosas }; 2546f0984d40SFabiano Rosas 2547f0984d40SFabiano Rosas return do_2scalar_long(s, a, opfn[a->size], accfn[a->size]); 2548f0984d40SFabiano Rosas } 2549f0984d40SFabiano Rosas 2550f0984d40SFabiano Rosas static bool trans_VQDMLSL_2sc(DisasContext *s, arg_2scalar *a) 2551f0984d40SFabiano Rosas { 2552f0984d40SFabiano Rosas static NeonGenTwoOpWidenFn * const opfn[] = { 2553f0984d40SFabiano Rosas NULL, 2554f0984d40SFabiano Rosas gen_VQDMULL_16, 2555f0984d40SFabiano Rosas gen_VQDMULL_32, 2556f0984d40SFabiano Rosas NULL, 2557f0984d40SFabiano Rosas }; 2558f0984d40SFabiano Rosas static NeonGenTwo64OpFn * const accfn[] = { 2559f0984d40SFabiano Rosas NULL, 2560f0984d40SFabiano Rosas gen_VQDMLSL_acc_16, 2561f0984d40SFabiano Rosas gen_VQDMLSL_acc_32, 2562f0984d40SFabiano Rosas NULL, 2563f0984d40SFabiano Rosas }; 2564f0984d40SFabiano Rosas 2565f0984d40SFabiano Rosas return do_2scalar_long(s, a, opfn[a->size], accfn[a->size]); 2566f0984d40SFabiano Rosas } 2567f0984d40SFabiano Rosas 2568f0984d40SFabiano Rosas static bool trans_VEXT(DisasContext *s, arg_VEXT *a) 2569f0984d40SFabiano Rosas { 2570f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 2571f0984d40SFabiano Rosas return false; 2572f0984d40SFabiano Rosas } 2573f0984d40SFabiano Rosas 2574f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 2575f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 2576f0984d40SFabiano Rosas ((a->vd | a->vn | a->vm) & 0x10)) { 2577f0984d40SFabiano Rosas return false; 2578f0984d40SFabiano Rosas } 2579f0984d40SFabiano Rosas 2580f0984d40SFabiano Rosas if ((a->vn | a->vm | a->vd) & a->q) { 2581f0984d40SFabiano Rosas return false; 2582f0984d40SFabiano Rosas } 2583f0984d40SFabiano Rosas 2584f0984d40SFabiano Rosas if (a->imm > 7 && !a->q) { 2585f0984d40SFabiano Rosas return false; 2586f0984d40SFabiano Rosas } 2587f0984d40SFabiano Rosas 2588f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 2589f0984d40SFabiano Rosas return true; 2590f0984d40SFabiano Rosas } 2591f0984d40SFabiano Rosas 2592f0984d40SFabiano Rosas if (!a->q) { 2593f0984d40SFabiano Rosas /* Extract 64 bits from <Vm:Vn> */ 2594f0984d40SFabiano Rosas TCGv_i64 left, right, dest; 2595f0984d40SFabiano Rosas 2596f0984d40SFabiano Rosas left = tcg_temp_new_i64(); 2597f0984d40SFabiano Rosas right = tcg_temp_new_i64(); 2598f0984d40SFabiano Rosas dest = tcg_temp_new_i64(); 2599f0984d40SFabiano Rosas 2600f0984d40SFabiano Rosas read_neon_element64(right, a->vn, 0, MO_64); 2601f0984d40SFabiano Rosas read_neon_element64(left, a->vm, 0, MO_64); 2602f0984d40SFabiano Rosas tcg_gen_extract2_i64(dest, right, left, a->imm * 8); 2603f0984d40SFabiano Rosas write_neon_element64(dest, a->vd, 0, MO_64); 2604f0984d40SFabiano Rosas } else { 2605f0984d40SFabiano Rosas /* Extract 128 bits from <Vm+1:Vm:Vn+1:Vn> */ 2606f0984d40SFabiano Rosas TCGv_i64 left, middle, right, destleft, destright; 2607f0984d40SFabiano Rosas 2608f0984d40SFabiano Rosas left = tcg_temp_new_i64(); 2609f0984d40SFabiano Rosas middle = tcg_temp_new_i64(); 2610f0984d40SFabiano Rosas right = tcg_temp_new_i64(); 2611f0984d40SFabiano Rosas destleft = tcg_temp_new_i64(); 2612f0984d40SFabiano Rosas destright = tcg_temp_new_i64(); 2613f0984d40SFabiano Rosas 2614f0984d40SFabiano Rosas if (a->imm < 8) { 2615f0984d40SFabiano Rosas read_neon_element64(right, a->vn, 0, MO_64); 2616f0984d40SFabiano Rosas read_neon_element64(middle, a->vn, 1, MO_64); 2617f0984d40SFabiano Rosas tcg_gen_extract2_i64(destright, right, middle, a->imm * 8); 2618f0984d40SFabiano Rosas read_neon_element64(left, a->vm, 0, MO_64); 2619f0984d40SFabiano Rosas tcg_gen_extract2_i64(destleft, middle, left, a->imm * 8); 2620f0984d40SFabiano Rosas } else { 2621f0984d40SFabiano Rosas read_neon_element64(right, a->vn, 1, MO_64); 2622f0984d40SFabiano Rosas read_neon_element64(middle, a->vm, 0, MO_64); 2623f0984d40SFabiano Rosas tcg_gen_extract2_i64(destright, right, middle, (a->imm - 8) * 8); 2624f0984d40SFabiano Rosas read_neon_element64(left, a->vm, 1, MO_64); 2625f0984d40SFabiano Rosas tcg_gen_extract2_i64(destleft, middle, left, (a->imm - 8) * 8); 2626f0984d40SFabiano Rosas } 2627f0984d40SFabiano Rosas 2628f0984d40SFabiano Rosas write_neon_element64(destright, a->vd, 0, MO_64); 2629f0984d40SFabiano Rosas write_neon_element64(destleft, a->vd, 1, MO_64); 2630f0984d40SFabiano Rosas } 2631f0984d40SFabiano Rosas return true; 2632f0984d40SFabiano Rosas } 2633f0984d40SFabiano Rosas 2634f0984d40SFabiano Rosas static bool trans_VTBL(DisasContext *s, arg_VTBL *a) 2635f0984d40SFabiano Rosas { 2636f0984d40SFabiano Rosas TCGv_i64 val, def; 2637f0984d40SFabiano Rosas TCGv_i32 desc; 2638f0984d40SFabiano Rosas 2639f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 2640f0984d40SFabiano Rosas return false; 2641f0984d40SFabiano Rosas } 2642f0984d40SFabiano Rosas 2643f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 2644f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 2645f0984d40SFabiano Rosas ((a->vd | a->vn | a->vm) & 0x10)) { 2646f0984d40SFabiano Rosas return false; 2647f0984d40SFabiano Rosas } 2648f0984d40SFabiano Rosas 2649f0984d40SFabiano Rosas if ((a->vn + a->len + 1) > 32) { 2650f0984d40SFabiano Rosas /* 2651f0984d40SFabiano Rosas * This is UNPREDICTABLE; we choose to UNDEF to avoid the 2652f0984d40SFabiano Rosas * helper function running off the end of the register file. 2653f0984d40SFabiano Rosas */ 2654f0984d40SFabiano Rosas return false; 2655f0984d40SFabiano Rosas } 2656f0984d40SFabiano Rosas 2657f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 2658f0984d40SFabiano Rosas return true; 2659f0984d40SFabiano Rosas } 2660f0984d40SFabiano Rosas 2661f0984d40SFabiano Rosas desc = tcg_constant_i32((a->vn << 2) | a->len); 2662f0984d40SFabiano Rosas def = tcg_temp_new_i64(); 2663f0984d40SFabiano Rosas if (a->op) { 2664f0984d40SFabiano Rosas read_neon_element64(def, a->vd, 0, MO_64); 2665f0984d40SFabiano Rosas } else { 2666f0984d40SFabiano Rosas tcg_gen_movi_i64(def, 0); 2667f0984d40SFabiano Rosas } 2668f0984d40SFabiano Rosas val = tcg_temp_new_i64(); 2669f0984d40SFabiano Rosas read_neon_element64(val, a->vm, 0, MO_64); 2670f0984d40SFabiano Rosas 2671ad75a51eSRichard Henderson gen_helper_neon_tbl(val, tcg_env, desc, val, def); 2672f0984d40SFabiano Rosas write_neon_element64(val, a->vd, 0, MO_64); 2673f0984d40SFabiano Rosas return true; 2674f0984d40SFabiano Rosas } 2675f0984d40SFabiano Rosas 2676f0984d40SFabiano Rosas static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a) 2677f0984d40SFabiano Rosas { 2678f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 2679f0984d40SFabiano Rosas return false; 2680f0984d40SFabiano Rosas } 2681f0984d40SFabiano Rosas 2682f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 2683f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 2684f0984d40SFabiano Rosas ((a->vd | a->vm) & 0x10)) { 2685f0984d40SFabiano Rosas return false; 2686f0984d40SFabiano Rosas } 2687f0984d40SFabiano Rosas 2688f0984d40SFabiano Rosas if (a->vd & a->q) { 2689f0984d40SFabiano Rosas return false; 2690f0984d40SFabiano Rosas } 2691f0984d40SFabiano Rosas 2692f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 2693f0984d40SFabiano Rosas return true; 2694f0984d40SFabiano Rosas } 2695f0984d40SFabiano Rosas 2696f0984d40SFabiano Rosas tcg_gen_gvec_dup_mem(a->size, neon_full_reg_offset(a->vd), 2697f0984d40SFabiano Rosas neon_element_offset(a->vm, a->index, a->size), 2698f0984d40SFabiano Rosas a->q ? 16 : 8, a->q ? 16 : 8); 2699f0984d40SFabiano Rosas return true; 2700f0984d40SFabiano Rosas } 2701f0984d40SFabiano Rosas 2702f0984d40SFabiano Rosas static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) 2703f0984d40SFabiano Rosas { 2704f0984d40SFabiano Rosas int pass, half; 2705f0984d40SFabiano Rosas TCGv_i32 tmp[2]; 2706f0984d40SFabiano Rosas 2707f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 2708f0984d40SFabiano Rosas return false; 2709f0984d40SFabiano Rosas } 2710f0984d40SFabiano Rosas 2711f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 2712f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 2713f0984d40SFabiano Rosas ((a->vd | a->vm) & 0x10)) { 2714f0984d40SFabiano Rosas return false; 2715f0984d40SFabiano Rosas } 2716f0984d40SFabiano Rosas 2717f0984d40SFabiano Rosas if ((a->vd | a->vm) & a->q) { 2718f0984d40SFabiano Rosas return false; 2719f0984d40SFabiano Rosas } 2720f0984d40SFabiano Rosas 2721f0984d40SFabiano Rosas if (a->size == 3) { 2722f0984d40SFabiano Rosas return false; 2723f0984d40SFabiano Rosas } 2724f0984d40SFabiano Rosas 2725f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 2726f0984d40SFabiano Rosas return true; 2727f0984d40SFabiano Rosas } 2728f0984d40SFabiano Rosas 2729f0984d40SFabiano Rosas tmp[0] = tcg_temp_new_i32(); 2730f0984d40SFabiano Rosas tmp[1] = tcg_temp_new_i32(); 2731f0984d40SFabiano Rosas 2732f0984d40SFabiano Rosas for (pass = 0; pass < (a->q ? 2 : 1); pass++) { 2733f0984d40SFabiano Rosas for (half = 0; half < 2; half++) { 2734f0984d40SFabiano Rosas read_neon_element32(tmp[half], a->vm, pass * 2 + half, MO_32); 2735f0984d40SFabiano Rosas switch (a->size) { 2736f0984d40SFabiano Rosas case 0: 2737f0984d40SFabiano Rosas tcg_gen_bswap32_i32(tmp[half], tmp[half]); 2738f0984d40SFabiano Rosas break; 2739f0984d40SFabiano Rosas case 1: 2740f0984d40SFabiano Rosas gen_swap_half(tmp[half], tmp[half]); 2741f0984d40SFabiano Rosas break; 2742f0984d40SFabiano Rosas case 2: 2743f0984d40SFabiano Rosas break; 2744f0984d40SFabiano Rosas default: 2745f0984d40SFabiano Rosas g_assert_not_reached(); 2746f0984d40SFabiano Rosas } 2747f0984d40SFabiano Rosas } 2748f0984d40SFabiano Rosas write_neon_element32(tmp[1], a->vd, pass * 2, MO_32); 2749f0984d40SFabiano Rosas write_neon_element32(tmp[0], a->vd, pass * 2 + 1, MO_32); 2750f0984d40SFabiano Rosas } 2751f0984d40SFabiano Rosas return true; 2752f0984d40SFabiano Rosas } 2753f0984d40SFabiano Rosas 2754f0984d40SFabiano Rosas static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a, 2755f0984d40SFabiano Rosas NeonGenWidenFn *widenfn, 2756f0984d40SFabiano Rosas NeonGenTwo64OpFn *opfn, 2757f0984d40SFabiano Rosas NeonGenTwo64OpFn *accfn) 2758f0984d40SFabiano Rosas { 2759f0984d40SFabiano Rosas /* 2760f0984d40SFabiano Rosas * Pairwise long operations: widen both halves of the pair, 2761f0984d40SFabiano Rosas * combine the pairs with the opfn, and then possibly accumulate 2762f0984d40SFabiano Rosas * into the destination with the accfn. 2763f0984d40SFabiano Rosas */ 2764f0984d40SFabiano Rosas int pass; 2765f0984d40SFabiano Rosas 2766f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 2767f0984d40SFabiano Rosas return false; 2768f0984d40SFabiano Rosas } 2769f0984d40SFabiano Rosas 2770f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 2771f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 2772f0984d40SFabiano Rosas ((a->vd | a->vm) & 0x10)) { 2773f0984d40SFabiano Rosas return false; 2774f0984d40SFabiano Rosas } 2775f0984d40SFabiano Rosas 2776f0984d40SFabiano Rosas if ((a->vd | a->vm) & a->q) { 2777f0984d40SFabiano Rosas return false; 2778f0984d40SFabiano Rosas } 2779f0984d40SFabiano Rosas 2780f0984d40SFabiano Rosas if (!widenfn) { 2781f0984d40SFabiano Rosas return false; 2782f0984d40SFabiano Rosas } 2783f0984d40SFabiano Rosas 2784f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 2785f0984d40SFabiano Rosas return true; 2786f0984d40SFabiano Rosas } 2787f0984d40SFabiano Rosas 2788f0984d40SFabiano Rosas for (pass = 0; pass < a->q + 1; pass++) { 2789f0984d40SFabiano Rosas TCGv_i32 tmp; 2790f0984d40SFabiano Rosas TCGv_i64 rm0_64, rm1_64, rd_64; 2791f0984d40SFabiano Rosas 2792f0984d40SFabiano Rosas rm0_64 = tcg_temp_new_i64(); 2793f0984d40SFabiano Rosas rm1_64 = tcg_temp_new_i64(); 2794f0984d40SFabiano Rosas rd_64 = tcg_temp_new_i64(); 2795f0984d40SFabiano Rosas 2796f0984d40SFabiano Rosas tmp = tcg_temp_new_i32(); 2797f0984d40SFabiano Rosas read_neon_element32(tmp, a->vm, pass * 2, MO_32); 2798f0984d40SFabiano Rosas widenfn(rm0_64, tmp); 2799f0984d40SFabiano Rosas read_neon_element32(tmp, a->vm, pass * 2 + 1, MO_32); 2800f0984d40SFabiano Rosas widenfn(rm1_64, tmp); 2801f0984d40SFabiano Rosas 2802f0984d40SFabiano Rosas opfn(rd_64, rm0_64, rm1_64); 2803f0984d40SFabiano Rosas 2804f0984d40SFabiano Rosas if (accfn) { 2805f0984d40SFabiano Rosas TCGv_i64 tmp64 = tcg_temp_new_i64(); 2806f0984d40SFabiano Rosas read_neon_element64(tmp64, a->vd, pass, MO_64); 2807f0984d40SFabiano Rosas accfn(rd_64, tmp64, rd_64); 2808f0984d40SFabiano Rosas } 2809f0984d40SFabiano Rosas write_neon_element64(rd_64, a->vd, pass, MO_64); 2810f0984d40SFabiano Rosas } 2811f0984d40SFabiano Rosas return true; 2812f0984d40SFabiano Rosas } 2813f0984d40SFabiano Rosas 2814f0984d40SFabiano Rosas static bool trans_VPADDL_S(DisasContext *s, arg_2misc *a) 2815f0984d40SFabiano Rosas { 2816f0984d40SFabiano Rosas static NeonGenWidenFn * const widenfn[] = { 2817f0984d40SFabiano Rosas gen_helper_neon_widen_s8, 2818f0984d40SFabiano Rosas gen_helper_neon_widen_s16, 2819f0984d40SFabiano Rosas tcg_gen_ext_i32_i64, 2820f0984d40SFabiano Rosas NULL, 2821f0984d40SFabiano Rosas }; 2822f0984d40SFabiano Rosas static NeonGenTwo64OpFn * const opfn[] = { 2823f0984d40SFabiano Rosas gen_helper_neon_paddl_u16, 2824f0984d40SFabiano Rosas gen_helper_neon_paddl_u32, 2825f0984d40SFabiano Rosas tcg_gen_add_i64, 2826f0984d40SFabiano Rosas NULL, 2827f0984d40SFabiano Rosas }; 2828f0984d40SFabiano Rosas 2829f0984d40SFabiano Rosas return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], NULL); 2830f0984d40SFabiano Rosas } 2831f0984d40SFabiano Rosas 2832f0984d40SFabiano Rosas static bool trans_VPADDL_U(DisasContext *s, arg_2misc *a) 2833f0984d40SFabiano Rosas { 2834f0984d40SFabiano Rosas static NeonGenWidenFn * const widenfn[] = { 2835f0984d40SFabiano Rosas gen_helper_neon_widen_u8, 2836f0984d40SFabiano Rosas gen_helper_neon_widen_u16, 2837f0984d40SFabiano Rosas tcg_gen_extu_i32_i64, 2838f0984d40SFabiano Rosas NULL, 2839f0984d40SFabiano Rosas }; 2840f0984d40SFabiano Rosas static NeonGenTwo64OpFn * const opfn[] = { 2841f0984d40SFabiano Rosas gen_helper_neon_paddl_u16, 2842f0984d40SFabiano Rosas gen_helper_neon_paddl_u32, 2843f0984d40SFabiano Rosas tcg_gen_add_i64, 2844f0984d40SFabiano Rosas NULL, 2845f0984d40SFabiano Rosas }; 2846f0984d40SFabiano Rosas 2847f0984d40SFabiano Rosas return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], NULL); 2848f0984d40SFabiano Rosas } 2849f0984d40SFabiano Rosas 2850f0984d40SFabiano Rosas static bool trans_VPADAL_S(DisasContext *s, arg_2misc *a) 2851f0984d40SFabiano Rosas { 2852f0984d40SFabiano Rosas static NeonGenWidenFn * const widenfn[] = { 2853f0984d40SFabiano Rosas gen_helper_neon_widen_s8, 2854f0984d40SFabiano Rosas gen_helper_neon_widen_s16, 2855f0984d40SFabiano Rosas tcg_gen_ext_i32_i64, 2856f0984d40SFabiano Rosas NULL, 2857f0984d40SFabiano Rosas }; 2858f0984d40SFabiano Rosas static NeonGenTwo64OpFn * const opfn[] = { 2859f0984d40SFabiano Rosas gen_helper_neon_paddl_u16, 2860f0984d40SFabiano Rosas gen_helper_neon_paddl_u32, 2861f0984d40SFabiano Rosas tcg_gen_add_i64, 2862f0984d40SFabiano Rosas NULL, 2863f0984d40SFabiano Rosas }; 2864f0984d40SFabiano Rosas static NeonGenTwo64OpFn * const accfn[] = { 2865f0984d40SFabiano Rosas gen_helper_neon_addl_u16, 2866f0984d40SFabiano Rosas gen_helper_neon_addl_u32, 2867f0984d40SFabiano Rosas tcg_gen_add_i64, 2868f0984d40SFabiano Rosas NULL, 2869f0984d40SFabiano Rosas }; 2870f0984d40SFabiano Rosas 2871f0984d40SFabiano Rosas return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], 2872f0984d40SFabiano Rosas accfn[a->size]); 2873f0984d40SFabiano Rosas } 2874f0984d40SFabiano Rosas 2875f0984d40SFabiano Rosas static bool trans_VPADAL_U(DisasContext *s, arg_2misc *a) 2876f0984d40SFabiano Rosas { 2877f0984d40SFabiano Rosas static NeonGenWidenFn * const widenfn[] = { 2878f0984d40SFabiano Rosas gen_helper_neon_widen_u8, 2879f0984d40SFabiano Rosas gen_helper_neon_widen_u16, 2880f0984d40SFabiano Rosas tcg_gen_extu_i32_i64, 2881f0984d40SFabiano Rosas NULL, 2882f0984d40SFabiano Rosas }; 2883f0984d40SFabiano Rosas static NeonGenTwo64OpFn * const opfn[] = { 2884f0984d40SFabiano Rosas gen_helper_neon_paddl_u16, 2885f0984d40SFabiano Rosas gen_helper_neon_paddl_u32, 2886f0984d40SFabiano Rosas tcg_gen_add_i64, 2887f0984d40SFabiano Rosas NULL, 2888f0984d40SFabiano Rosas }; 2889f0984d40SFabiano Rosas static NeonGenTwo64OpFn * const accfn[] = { 2890f0984d40SFabiano Rosas gen_helper_neon_addl_u16, 2891f0984d40SFabiano Rosas gen_helper_neon_addl_u32, 2892f0984d40SFabiano Rosas tcg_gen_add_i64, 2893f0984d40SFabiano Rosas NULL, 2894f0984d40SFabiano Rosas }; 2895f0984d40SFabiano Rosas 2896f0984d40SFabiano Rosas return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], 2897f0984d40SFabiano Rosas accfn[a->size]); 2898f0984d40SFabiano Rosas } 2899f0984d40SFabiano Rosas 2900f0984d40SFabiano Rosas typedef void ZipFn(TCGv_ptr, TCGv_ptr); 2901f0984d40SFabiano Rosas 2902f0984d40SFabiano Rosas static bool do_zip_uzp(DisasContext *s, arg_2misc *a, 2903f0984d40SFabiano Rosas ZipFn *fn) 2904f0984d40SFabiano Rosas { 2905f0984d40SFabiano Rosas TCGv_ptr pd, pm; 2906f0984d40SFabiano Rosas 2907f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 2908f0984d40SFabiano Rosas return false; 2909f0984d40SFabiano Rosas } 2910f0984d40SFabiano Rosas 2911f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 2912f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 2913f0984d40SFabiano Rosas ((a->vd | a->vm) & 0x10)) { 2914f0984d40SFabiano Rosas return false; 2915f0984d40SFabiano Rosas } 2916f0984d40SFabiano Rosas 2917f0984d40SFabiano Rosas if ((a->vd | a->vm) & a->q) { 2918f0984d40SFabiano Rosas return false; 2919f0984d40SFabiano Rosas } 2920f0984d40SFabiano Rosas 2921f0984d40SFabiano Rosas if (!fn) { 2922f0984d40SFabiano Rosas /* Bad size or size/q combination */ 2923f0984d40SFabiano Rosas return false; 2924f0984d40SFabiano Rosas } 2925f0984d40SFabiano Rosas 2926f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 2927f0984d40SFabiano Rosas return true; 2928f0984d40SFabiano Rosas } 2929f0984d40SFabiano Rosas 2930f0984d40SFabiano Rosas pd = vfp_reg_ptr(true, a->vd); 2931f0984d40SFabiano Rosas pm = vfp_reg_ptr(true, a->vm); 2932f0984d40SFabiano Rosas fn(pd, pm); 2933f0984d40SFabiano Rosas return true; 2934f0984d40SFabiano Rosas } 2935f0984d40SFabiano Rosas 2936f0984d40SFabiano Rosas static bool trans_VUZP(DisasContext *s, arg_2misc *a) 2937f0984d40SFabiano Rosas { 2938f0984d40SFabiano Rosas static ZipFn * const fn[2][4] = { 2939f0984d40SFabiano Rosas { 2940f0984d40SFabiano Rosas gen_helper_neon_unzip8, 2941f0984d40SFabiano Rosas gen_helper_neon_unzip16, 2942f0984d40SFabiano Rosas NULL, 2943f0984d40SFabiano Rosas NULL, 2944f0984d40SFabiano Rosas }, { 2945f0984d40SFabiano Rosas gen_helper_neon_qunzip8, 2946f0984d40SFabiano Rosas gen_helper_neon_qunzip16, 2947f0984d40SFabiano Rosas gen_helper_neon_qunzip32, 2948f0984d40SFabiano Rosas NULL, 2949f0984d40SFabiano Rosas } 2950f0984d40SFabiano Rosas }; 2951f0984d40SFabiano Rosas return do_zip_uzp(s, a, fn[a->q][a->size]); 2952f0984d40SFabiano Rosas } 2953f0984d40SFabiano Rosas 2954f0984d40SFabiano Rosas static bool trans_VZIP(DisasContext *s, arg_2misc *a) 2955f0984d40SFabiano Rosas { 2956f0984d40SFabiano Rosas static ZipFn * const fn[2][4] = { 2957f0984d40SFabiano Rosas { 2958f0984d40SFabiano Rosas gen_helper_neon_zip8, 2959f0984d40SFabiano Rosas gen_helper_neon_zip16, 2960f0984d40SFabiano Rosas NULL, 2961f0984d40SFabiano Rosas NULL, 2962f0984d40SFabiano Rosas }, { 2963f0984d40SFabiano Rosas gen_helper_neon_qzip8, 2964f0984d40SFabiano Rosas gen_helper_neon_qzip16, 2965f0984d40SFabiano Rosas gen_helper_neon_qzip32, 2966f0984d40SFabiano Rosas NULL, 2967f0984d40SFabiano Rosas } 2968f0984d40SFabiano Rosas }; 2969f0984d40SFabiano Rosas return do_zip_uzp(s, a, fn[a->q][a->size]); 2970f0984d40SFabiano Rosas } 2971f0984d40SFabiano Rosas 2972f0984d40SFabiano Rosas static bool do_vmovn(DisasContext *s, arg_2misc *a, 2973f0984d40SFabiano Rosas NeonGenNarrowEnvFn *narrowfn) 2974f0984d40SFabiano Rosas { 2975f0984d40SFabiano Rosas TCGv_i64 rm; 2976f0984d40SFabiano Rosas TCGv_i32 rd0, rd1; 2977f0984d40SFabiano Rosas 2978f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 2979f0984d40SFabiano Rosas return false; 2980f0984d40SFabiano Rosas } 2981f0984d40SFabiano Rosas 2982f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 2983f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 2984f0984d40SFabiano Rosas ((a->vd | a->vm) & 0x10)) { 2985f0984d40SFabiano Rosas return false; 2986f0984d40SFabiano Rosas } 2987f0984d40SFabiano Rosas 2988f0984d40SFabiano Rosas if (a->vm & 1) { 2989f0984d40SFabiano Rosas return false; 2990f0984d40SFabiano Rosas } 2991f0984d40SFabiano Rosas 2992f0984d40SFabiano Rosas if (!narrowfn) { 2993f0984d40SFabiano Rosas return false; 2994f0984d40SFabiano Rosas } 2995f0984d40SFabiano Rosas 2996f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 2997f0984d40SFabiano Rosas return true; 2998f0984d40SFabiano Rosas } 2999f0984d40SFabiano Rosas 3000f0984d40SFabiano Rosas rm = tcg_temp_new_i64(); 3001f0984d40SFabiano Rosas rd0 = tcg_temp_new_i32(); 3002f0984d40SFabiano Rosas rd1 = tcg_temp_new_i32(); 3003f0984d40SFabiano Rosas 3004f0984d40SFabiano Rosas read_neon_element64(rm, a->vm, 0, MO_64); 3005ad75a51eSRichard Henderson narrowfn(rd0, tcg_env, rm); 3006f0984d40SFabiano Rosas read_neon_element64(rm, a->vm, 1, MO_64); 3007ad75a51eSRichard Henderson narrowfn(rd1, tcg_env, rm); 3008f0984d40SFabiano Rosas write_neon_element32(rd0, a->vd, 0, MO_32); 3009f0984d40SFabiano Rosas write_neon_element32(rd1, a->vd, 1, MO_32); 3010f0984d40SFabiano Rosas return true; 3011f0984d40SFabiano Rosas } 3012f0984d40SFabiano Rosas 3013f0984d40SFabiano Rosas #define DO_VMOVN(INSN, FUNC) \ 3014f0984d40SFabiano Rosas static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ 3015f0984d40SFabiano Rosas { \ 3016f0984d40SFabiano Rosas static NeonGenNarrowEnvFn * const narrowfn[] = { \ 3017f0984d40SFabiano Rosas FUNC##8, \ 3018f0984d40SFabiano Rosas FUNC##16, \ 3019f0984d40SFabiano Rosas FUNC##32, \ 3020f0984d40SFabiano Rosas NULL, \ 3021f0984d40SFabiano Rosas }; \ 3022f0984d40SFabiano Rosas return do_vmovn(s, a, narrowfn[a->size]); \ 3023f0984d40SFabiano Rosas } 3024f0984d40SFabiano Rosas 3025f0984d40SFabiano Rosas DO_VMOVN(VMOVN, gen_neon_narrow_u) 3026f0984d40SFabiano Rosas DO_VMOVN(VQMOVUN, gen_helper_neon_unarrow_sat) 3027f0984d40SFabiano Rosas DO_VMOVN(VQMOVN_S, gen_helper_neon_narrow_sat_s) 3028f0984d40SFabiano Rosas DO_VMOVN(VQMOVN_U, gen_helper_neon_narrow_sat_u) 3029f0984d40SFabiano Rosas 3030f0984d40SFabiano Rosas static bool trans_VSHLL(DisasContext *s, arg_2misc *a) 3031f0984d40SFabiano Rosas { 3032f0984d40SFabiano Rosas TCGv_i32 rm0, rm1; 3033f0984d40SFabiano Rosas TCGv_i64 rd; 3034f0984d40SFabiano Rosas static NeonGenWidenFn * const widenfns[] = { 3035f0984d40SFabiano Rosas gen_helper_neon_widen_u8, 3036f0984d40SFabiano Rosas gen_helper_neon_widen_u16, 3037f0984d40SFabiano Rosas tcg_gen_extu_i32_i64, 3038f0984d40SFabiano Rosas NULL, 3039f0984d40SFabiano Rosas }; 3040f0984d40SFabiano Rosas NeonGenWidenFn *widenfn = widenfns[a->size]; 3041f0984d40SFabiano Rosas 3042f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 3043f0984d40SFabiano Rosas return false; 3044f0984d40SFabiano Rosas } 3045f0984d40SFabiano Rosas 3046f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 3047f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 3048f0984d40SFabiano Rosas ((a->vd | a->vm) & 0x10)) { 3049f0984d40SFabiano Rosas return false; 3050f0984d40SFabiano Rosas } 3051f0984d40SFabiano Rosas 3052f0984d40SFabiano Rosas if (a->vd & 1) { 3053f0984d40SFabiano Rosas return false; 3054f0984d40SFabiano Rosas } 3055f0984d40SFabiano Rosas 3056f0984d40SFabiano Rosas if (!widenfn) { 3057f0984d40SFabiano Rosas return false; 3058f0984d40SFabiano Rosas } 3059f0984d40SFabiano Rosas 3060f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 3061f0984d40SFabiano Rosas return true; 3062f0984d40SFabiano Rosas } 3063f0984d40SFabiano Rosas 3064f0984d40SFabiano Rosas rd = tcg_temp_new_i64(); 3065f0984d40SFabiano Rosas rm0 = tcg_temp_new_i32(); 3066f0984d40SFabiano Rosas rm1 = tcg_temp_new_i32(); 3067f0984d40SFabiano Rosas 3068f0984d40SFabiano Rosas read_neon_element32(rm0, a->vm, 0, MO_32); 3069f0984d40SFabiano Rosas read_neon_element32(rm1, a->vm, 1, MO_32); 3070f0984d40SFabiano Rosas 3071f0984d40SFabiano Rosas widenfn(rd, rm0); 3072f0984d40SFabiano Rosas tcg_gen_shli_i64(rd, rd, 8 << a->size); 3073f0984d40SFabiano Rosas write_neon_element64(rd, a->vd, 0, MO_64); 3074f0984d40SFabiano Rosas widenfn(rd, rm1); 3075f0984d40SFabiano Rosas tcg_gen_shli_i64(rd, rd, 8 << a->size); 3076f0984d40SFabiano Rosas write_neon_element64(rd, a->vd, 1, MO_64); 3077f0984d40SFabiano Rosas return true; 3078f0984d40SFabiano Rosas } 3079f0984d40SFabiano Rosas 3080f0984d40SFabiano Rosas static bool trans_VCVT_B16_F32(DisasContext *s, arg_2misc *a) 3081f0984d40SFabiano Rosas { 3082f0984d40SFabiano Rosas TCGv_ptr fpst; 3083f0984d40SFabiano Rosas TCGv_i64 tmp; 3084f0984d40SFabiano Rosas TCGv_i32 dst0, dst1; 3085f0984d40SFabiano Rosas 3086f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_bf16, s)) { 3087f0984d40SFabiano Rosas return false; 3088f0984d40SFabiano Rosas } 3089f0984d40SFabiano Rosas 3090f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 3091f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 3092f0984d40SFabiano Rosas ((a->vd | a->vm) & 0x10)) { 3093f0984d40SFabiano Rosas return false; 3094f0984d40SFabiano Rosas } 3095f0984d40SFabiano Rosas 3096f0984d40SFabiano Rosas if ((a->vm & 1) || (a->size != 1)) { 3097f0984d40SFabiano Rosas return false; 3098f0984d40SFabiano Rosas } 3099f0984d40SFabiano Rosas 3100f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 3101f0984d40SFabiano Rosas return true; 3102f0984d40SFabiano Rosas } 3103f0984d40SFabiano Rosas 3104f0984d40SFabiano Rosas fpst = fpstatus_ptr(FPST_STD); 3105f0984d40SFabiano Rosas tmp = tcg_temp_new_i64(); 3106f0984d40SFabiano Rosas dst0 = tcg_temp_new_i32(); 3107f0984d40SFabiano Rosas dst1 = tcg_temp_new_i32(); 3108f0984d40SFabiano Rosas 3109f0984d40SFabiano Rosas read_neon_element64(tmp, a->vm, 0, MO_64); 3110f0984d40SFabiano Rosas gen_helper_bfcvt_pair(dst0, tmp, fpst); 3111f0984d40SFabiano Rosas 3112f0984d40SFabiano Rosas read_neon_element64(tmp, a->vm, 1, MO_64); 3113f0984d40SFabiano Rosas gen_helper_bfcvt_pair(dst1, tmp, fpst); 3114f0984d40SFabiano Rosas 3115f0984d40SFabiano Rosas write_neon_element32(dst0, a->vd, 0, MO_32); 3116f0984d40SFabiano Rosas write_neon_element32(dst1, a->vd, 1, MO_32); 3117f0984d40SFabiano Rosas return true; 3118f0984d40SFabiano Rosas } 3119f0984d40SFabiano Rosas 3120f0984d40SFabiano Rosas static bool trans_VCVT_F16_F32(DisasContext *s, arg_2misc *a) 3121f0984d40SFabiano Rosas { 3122f0984d40SFabiano Rosas TCGv_ptr fpst; 3123f0984d40SFabiano Rosas TCGv_i32 ahp, tmp, tmp2, tmp3; 3124f0984d40SFabiano Rosas 3125f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON) || 3126f0984d40SFabiano Rosas !dc_isar_feature(aa32_fp16_spconv, s)) { 3127f0984d40SFabiano Rosas return false; 3128f0984d40SFabiano Rosas } 3129f0984d40SFabiano Rosas 3130f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 3131f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 3132f0984d40SFabiano Rosas ((a->vd | a->vm) & 0x10)) { 3133f0984d40SFabiano Rosas return false; 3134f0984d40SFabiano Rosas } 3135f0984d40SFabiano Rosas 3136f0984d40SFabiano Rosas if ((a->vm & 1) || (a->size != 1)) { 3137f0984d40SFabiano Rosas return false; 3138f0984d40SFabiano Rosas } 3139f0984d40SFabiano Rosas 3140f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 3141f0984d40SFabiano Rosas return true; 3142f0984d40SFabiano Rosas } 3143f0984d40SFabiano Rosas 3144f0984d40SFabiano Rosas fpst = fpstatus_ptr(FPST_STD); 3145f0984d40SFabiano Rosas ahp = get_ahp_flag(); 3146f0984d40SFabiano Rosas tmp = tcg_temp_new_i32(); 3147f0984d40SFabiano Rosas read_neon_element32(tmp, a->vm, 0, MO_32); 3148f0984d40SFabiano Rosas gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); 3149f0984d40SFabiano Rosas tmp2 = tcg_temp_new_i32(); 3150f0984d40SFabiano Rosas read_neon_element32(tmp2, a->vm, 1, MO_32); 3151f0984d40SFabiano Rosas gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp); 3152f0984d40SFabiano Rosas tcg_gen_shli_i32(tmp2, tmp2, 16); 3153f0984d40SFabiano Rosas tcg_gen_or_i32(tmp2, tmp2, tmp); 3154f0984d40SFabiano Rosas read_neon_element32(tmp, a->vm, 2, MO_32); 3155f0984d40SFabiano Rosas gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); 3156f0984d40SFabiano Rosas tmp3 = tcg_temp_new_i32(); 3157f0984d40SFabiano Rosas read_neon_element32(tmp3, a->vm, 3, MO_32); 3158f0984d40SFabiano Rosas write_neon_element32(tmp2, a->vd, 0, MO_32); 3159f0984d40SFabiano Rosas gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp); 3160f0984d40SFabiano Rosas tcg_gen_shli_i32(tmp3, tmp3, 16); 3161f0984d40SFabiano Rosas tcg_gen_or_i32(tmp3, tmp3, tmp); 3162f0984d40SFabiano Rosas write_neon_element32(tmp3, a->vd, 1, MO_32); 3163f0984d40SFabiano Rosas return true; 3164f0984d40SFabiano Rosas } 3165f0984d40SFabiano Rosas 3166f0984d40SFabiano Rosas static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a) 3167f0984d40SFabiano Rosas { 3168f0984d40SFabiano Rosas TCGv_ptr fpst; 3169f0984d40SFabiano Rosas TCGv_i32 ahp, tmp, tmp2, tmp3; 3170f0984d40SFabiano Rosas 3171f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON) || 3172f0984d40SFabiano Rosas !dc_isar_feature(aa32_fp16_spconv, s)) { 3173f0984d40SFabiano Rosas return false; 3174f0984d40SFabiano Rosas } 3175f0984d40SFabiano Rosas 3176f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 3177f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 3178f0984d40SFabiano Rosas ((a->vd | a->vm) & 0x10)) { 3179f0984d40SFabiano Rosas return false; 3180f0984d40SFabiano Rosas } 3181f0984d40SFabiano Rosas 3182f0984d40SFabiano Rosas if ((a->vd & 1) || (a->size != 1)) { 3183f0984d40SFabiano Rosas return false; 3184f0984d40SFabiano Rosas } 3185f0984d40SFabiano Rosas 3186f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 3187f0984d40SFabiano Rosas return true; 3188f0984d40SFabiano Rosas } 3189f0984d40SFabiano Rosas 3190f0984d40SFabiano Rosas fpst = fpstatus_ptr(FPST_STD); 3191f0984d40SFabiano Rosas ahp = get_ahp_flag(); 3192f0984d40SFabiano Rosas tmp3 = tcg_temp_new_i32(); 3193f0984d40SFabiano Rosas tmp2 = tcg_temp_new_i32(); 3194f0984d40SFabiano Rosas tmp = tcg_temp_new_i32(); 3195f0984d40SFabiano Rosas read_neon_element32(tmp, a->vm, 0, MO_32); 3196f0984d40SFabiano Rosas read_neon_element32(tmp2, a->vm, 1, MO_32); 3197f0984d40SFabiano Rosas tcg_gen_ext16u_i32(tmp3, tmp); 3198f0984d40SFabiano Rosas gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); 3199f0984d40SFabiano Rosas write_neon_element32(tmp3, a->vd, 0, MO_32); 3200f0984d40SFabiano Rosas tcg_gen_shri_i32(tmp, tmp, 16); 3201f0984d40SFabiano Rosas gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp); 3202f0984d40SFabiano Rosas write_neon_element32(tmp, a->vd, 1, MO_32); 3203f0984d40SFabiano Rosas tcg_gen_ext16u_i32(tmp3, tmp2); 3204f0984d40SFabiano Rosas gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); 3205f0984d40SFabiano Rosas write_neon_element32(tmp3, a->vd, 2, MO_32); 3206f0984d40SFabiano Rosas tcg_gen_shri_i32(tmp2, tmp2, 16); 3207f0984d40SFabiano Rosas gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp); 3208f0984d40SFabiano Rosas write_neon_element32(tmp2, a->vd, 3, MO_32); 3209f0984d40SFabiano Rosas return true; 3210f0984d40SFabiano Rosas } 3211f0984d40SFabiano Rosas 3212f0984d40SFabiano Rosas static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn) 3213f0984d40SFabiano Rosas { 3214f0984d40SFabiano Rosas int vec_size = a->q ? 16 : 8; 3215f0984d40SFabiano Rosas int rd_ofs = neon_full_reg_offset(a->vd); 3216f0984d40SFabiano Rosas int rm_ofs = neon_full_reg_offset(a->vm); 3217f0984d40SFabiano Rosas 3218f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 3219f0984d40SFabiano Rosas return false; 3220f0984d40SFabiano Rosas } 3221f0984d40SFabiano Rosas 3222f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 3223f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 3224f0984d40SFabiano Rosas ((a->vd | a->vm) & 0x10)) { 3225f0984d40SFabiano Rosas return false; 3226f0984d40SFabiano Rosas } 3227f0984d40SFabiano Rosas 3228f0984d40SFabiano Rosas if (a->size == 3) { 3229f0984d40SFabiano Rosas return false; 3230f0984d40SFabiano Rosas } 3231f0984d40SFabiano Rosas 3232f0984d40SFabiano Rosas if ((a->vd | a->vm) & a->q) { 3233f0984d40SFabiano Rosas return false; 3234f0984d40SFabiano Rosas } 3235f0984d40SFabiano Rosas 3236f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 3237f0984d40SFabiano Rosas return true; 3238f0984d40SFabiano Rosas } 3239f0984d40SFabiano Rosas 3240f0984d40SFabiano Rosas fn(a->size, rd_ofs, rm_ofs, vec_size, vec_size); 3241f0984d40SFabiano Rosas 3242f0984d40SFabiano Rosas return true; 3243f0984d40SFabiano Rosas } 3244f0984d40SFabiano Rosas 3245f0984d40SFabiano Rosas #define DO_2MISC_VEC(INSN, FN) \ 3246f0984d40SFabiano Rosas static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ 3247f0984d40SFabiano Rosas { \ 3248f0984d40SFabiano Rosas return do_2misc_vec(s, a, FN); \ 3249f0984d40SFabiano Rosas } 3250f0984d40SFabiano Rosas 3251f0984d40SFabiano Rosas DO_2MISC_VEC(VNEG, tcg_gen_gvec_neg) 3252f0984d40SFabiano Rosas DO_2MISC_VEC(VABS, tcg_gen_gvec_abs) 3253f0984d40SFabiano Rosas DO_2MISC_VEC(VCEQ0, gen_gvec_ceq0) 3254f0984d40SFabiano Rosas DO_2MISC_VEC(VCGT0, gen_gvec_cgt0) 3255f0984d40SFabiano Rosas DO_2MISC_VEC(VCLE0, gen_gvec_cle0) 3256f0984d40SFabiano Rosas DO_2MISC_VEC(VCGE0, gen_gvec_cge0) 3257f0984d40SFabiano Rosas DO_2MISC_VEC(VCLT0, gen_gvec_clt0) 3258f0984d40SFabiano Rosas 3259f0984d40SFabiano Rosas static bool trans_VMVN(DisasContext *s, arg_2misc *a) 3260f0984d40SFabiano Rosas { 3261f0984d40SFabiano Rosas if (a->size != 0) { 3262f0984d40SFabiano Rosas return false; 3263f0984d40SFabiano Rosas } 3264f0984d40SFabiano Rosas return do_2misc_vec(s, a, tcg_gen_gvec_not); 3265f0984d40SFabiano Rosas } 3266f0984d40SFabiano Rosas 3267f0984d40SFabiano Rosas #define WRAP_2M_3_OOL_FN(WRAPNAME, FUNC, DATA) \ 3268f0984d40SFabiano Rosas static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \ 3269f0984d40SFabiano Rosas uint32_t rm_ofs, uint32_t oprsz, \ 3270f0984d40SFabiano Rosas uint32_t maxsz) \ 3271f0984d40SFabiano Rosas { \ 3272f0984d40SFabiano Rosas tcg_gen_gvec_3_ool(rd_ofs, rd_ofs, rm_ofs, oprsz, maxsz, \ 3273f0984d40SFabiano Rosas DATA, FUNC); \ 3274f0984d40SFabiano Rosas } 3275f0984d40SFabiano Rosas 3276f0984d40SFabiano Rosas #define WRAP_2M_2_OOL_FN(WRAPNAME, FUNC, DATA) \ 3277f0984d40SFabiano Rosas static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \ 3278f0984d40SFabiano Rosas uint32_t rm_ofs, uint32_t oprsz, \ 3279f0984d40SFabiano Rosas uint32_t maxsz) \ 3280f0984d40SFabiano Rosas { \ 3281f0984d40SFabiano Rosas tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, oprsz, maxsz, DATA, FUNC); \ 3282f0984d40SFabiano Rosas } 3283f0984d40SFabiano Rosas 3284f0984d40SFabiano Rosas WRAP_2M_3_OOL_FN(gen_AESE, gen_helper_crypto_aese, 0) 32850f23908cSRichard Henderson WRAP_2M_3_OOL_FN(gen_AESD, gen_helper_crypto_aesd, 0) 3286f0984d40SFabiano Rosas WRAP_2M_2_OOL_FN(gen_AESMC, gen_helper_crypto_aesmc, 0) 32870f23908cSRichard Henderson WRAP_2M_2_OOL_FN(gen_AESIMC, gen_helper_crypto_aesimc, 0) 3288f0984d40SFabiano Rosas WRAP_2M_2_OOL_FN(gen_SHA1H, gen_helper_crypto_sha1h, 0) 3289f0984d40SFabiano Rosas WRAP_2M_2_OOL_FN(gen_SHA1SU1, gen_helper_crypto_sha1su1, 0) 3290f0984d40SFabiano Rosas WRAP_2M_2_OOL_FN(gen_SHA256SU0, gen_helper_crypto_sha256su0, 0) 3291f0984d40SFabiano Rosas 3292f0984d40SFabiano Rosas #define DO_2M_CRYPTO(INSN, FEATURE, SIZE) \ 3293f0984d40SFabiano Rosas static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ 3294f0984d40SFabiano Rosas { \ 3295f0984d40SFabiano Rosas if (!dc_isar_feature(FEATURE, s) || a->size != SIZE) { \ 3296f0984d40SFabiano Rosas return false; \ 3297f0984d40SFabiano Rosas } \ 3298f0984d40SFabiano Rosas return do_2misc_vec(s, a, gen_##INSN); \ 3299f0984d40SFabiano Rosas } 3300f0984d40SFabiano Rosas 3301f0984d40SFabiano Rosas DO_2M_CRYPTO(AESE, aa32_aes, 0) 3302f0984d40SFabiano Rosas DO_2M_CRYPTO(AESD, aa32_aes, 0) 3303f0984d40SFabiano Rosas DO_2M_CRYPTO(AESMC, aa32_aes, 0) 3304f0984d40SFabiano Rosas DO_2M_CRYPTO(AESIMC, aa32_aes, 0) 3305f0984d40SFabiano Rosas DO_2M_CRYPTO(SHA1H, aa32_sha1, 2) 3306f0984d40SFabiano Rosas DO_2M_CRYPTO(SHA1SU1, aa32_sha1, 2) 3307f0984d40SFabiano Rosas DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2) 3308f0984d40SFabiano Rosas 3309f0984d40SFabiano Rosas static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn) 3310f0984d40SFabiano Rosas { 3311f0984d40SFabiano Rosas TCGv_i32 tmp; 3312f0984d40SFabiano Rosas int pass; 3313f0984d40SFabiano Rosas 3314f0984d40SFabiano Rosas /* Handle a 2-reg-misc operation by iterating 32 bits at a time */ 3315f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 3316f0984d40SFabiano Rosas return false; 3317f0984d40SFabiano Rosas } 3318f0984d40SFabiano Rosas 3319f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 3320f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 3321f0984d40SFabiano Rosas ((a->vd | a->vm) & 0x10)) { 3322f0984d40SFabiano Rosas return false; 3323f0984d40SFabiano Rosas } 3324f0984d40SFabiano Rosas 3325f0984d40SFabiano Rosas if (!fn) { 3326f0984d40SFabiano Rosas return false; 3327f0984d40SFabiano Rosas } 3328f0984d40SFabiano Rosas 3329f0984d40SFabiano Rosas if ((a->vd | a->vm) & a->q) { 3330f0984d40SFabiano Rosas return false; 3331f0984d40SFabiano Rosas } 3332f0984d40SFabiano Rosas 3333f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 3334f0984d40SFabiano Rosas return true; 3335f0984d40SFabiano Rosas } 3336f0984d40SFabiano Rosas 3337f0984d40SFabiano Rosas tmp = tcg_temp_new_i32(); 3338f0984d40SFabiano Rosas for (pass = 0; pass < (a->q ? 4 : 2); pass++) { 3339f0984d40SFabiano Rosas read_neon_element32(tmp, a->vm, pass, MO_32); 3340f0984d40SFabiano Rosas fn(tmp, tmp); 3341f0984d40SFabiano Rosas write_neon_element32(tmp, a->vd, pass, MO_32); 3342f0984d40SFabiano Rosas } 3343f0984d40SFabiano Rosas return true; 3344f0984d40SFabiano Rosas } 3345f0984d40SFabiano Rosas 3346f0984d40SFabiano Rosas static bool trans_VREV32(DisasContext *s, arg_2misc *a) 3347f0984d40SFabiano Rosas { 3348f0984d40SFabiano Rosas static NeonGenOneOpFn * const fn[] = { 3349f0984d40SFabiano Rosas tcg_gen_bswap32_i32, 3350f0984d40SFabiano Rosas gen_swap_half, 3351f0984d40SFabiano Rosas NULL, 3352f0984d40SFabiano Rosas NULL, 3353f0984d40SFabiano Rosas }; 3354f0984d40SFabiano Rosas return do_2misc(s, a, fn[a->size]); 3355f0984d40SFabiano Rosas } 3356f0984d40SFabiano Rosas 3357f0984d40SFabiano Rosas static bool trans_VREV16(DisasContext *s, arg_2misc *a) 3358f0984d40SFabiano Rosas { 3359f0984d40SFabiano Rosas if (a->size != 0) { 3360f0984d40SFabiano Rosas return false; 3361f0984d40SFabiano Rosas } 3362f0984d40SFabiano Rosas return do_2misc(s, a, gen_rev16); 3363f0984d40SFabiano Rosas } 3364f0984d40SFabiano Rosas 3365f0984d40SFabiano Rosas static bool trans_VCLS(DisasContext *s, arg_2misc *a) 3366f0984d40SFabiano Rosas { 3367f0984d40SFabiano Rosas static NeonGenOneOpFn * const fn[] = { 3368f0984d40SFabiano Rosas gen_helper_neon_cls_s8, 3369f0984d40SFabiano Rosas gen_helper_neon_cls_s16, 3370f0984d40SFabiano Rosas gen_helper_neon_cls_s32, 3371f0984d40SFabiano Rosas NULL, 3372f0984d40SFabiano Rosas }; 3373f0984d40SFabiano Rosas return do_2misc(s, a, fn[a->size]); 3374f0984d40SFabiano Rosas } 3375f0984d40SFabiano Rosas 3376f0984d40SFabiano Rosas static void do_VCLZ_32(TCGv_i32 rd, TCGv_i32 rm) 3377f0984d40SFabiano Rosas { 3378f0984d40SFabiano Rosas tcg_gen_clzi_i32(rd, rm, 32); 3379f0984d40SFabiano Rosas } 3380f0984d40SFabiano Rosas 3381f0984d40SFabiano Rosas static bool trans_VCLZ(DisasContext *s, arg_2misc *a) 3382f0984d40SFabiano Rosas { 3383f0984d40SFabiano Rosas static NeonGenOneOpFn * const fn[] = { 3384f0984d40SFabiano Rosas gen_helper_neon_clz_u8, 3385f0984d40SFabiano Rosas gen_helper_neon_clz_u16, 3386f0984d40SFabiano Rosas do_VCLZ_32, 3387f0984d40SFabiano Rosas NULL, 3388f0984d40SFabiano Rosas }; 3389f0984d40SFabiano Rosas return do_2misc(s, a, fn[a->size]); 3390f0984d40SFabiano Rosas } 3391f0984d40SFabiano Rosas 3392f0984d40SFabiano Rosas static bool trans_VCNT(DisasContext *s, arg_2misc *a) 3393f0984d40SFabiano Rosas { 3394f0984d40SFabiano Rosas if (a->size != 0) { 3395f0984d40SFabiano Rosas return false; 3396f0984d40SFabiano Rosas } 3397f0984d40SFabiano Rosas return do_2misc(s, a, gen_helper_neon_cnt_u8); 3398f0984d40SFabiano Rosas } 3399f0984d40SFabiano Rosas 3400f0984d40SFabiano Rosas static void gen_VABS_F(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 3401f0984d40SFabiano Rosas uint32_t oprsz, uint32_t maxsz) 3402f0984d40SFabiano Rosas { 3403f0984d40SFabiano Rosas tcg_gen_gvec_andi(vece, rd_ofs, rm_ofs, 3404f0984d40SFabiano Rosas vece == MO_16 ? 0x7fff : 0x7fffffff, 3405f0984d40SFabiano Rosas oprsz, maxsz); 3406f0984d40SFabiano Rosas } 3407f0984d40SFabiano Rosas 3408f0984d40SFabiano Rosas static bool trans_VABS_F(DisasContext *s, arg_2misc *a) 3409f0984d40SFabiano Rosas { 3410f0984d40SFabiano Rosas if (a->size == MO_16) { 3411f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_fp16_arith, s)) { 3412f0984d40SFabiano Rosas return false; 3413f0984d40SFabiano Rosas } 3414f0984d40SFabiano Rosas } else if (a->size != MO_32) { 3415f0984d40SFabiano Rosas return false; 3416f0984d40SFabiano Rosas } 3417f0984d40SFabiano Rosas return do_2misc_vec(s, a, gen_VABS_F); 3418f0984d40SFabiano Rosas } 3419f0984d40SFabiano Rosas 3420f0984d40SFabiano Rosas static void gen_VNEG_F(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 3421f0984d40SFabiano Rosas uint32_t oprsz, uint32_t maxsz) 3422f0984d40SFabiano Rosas { 3423f0984d40SFabiano Rosas tcg_gen_gvec_xori(vece, rd_ofs, rm_ofs, 3424f0984d40SFabiano Rosas vece == MO_16 ? 0x8000 : 0x80000000, 3425f0984d40SFabiano Rosas oprsz, maxsz); 3426f0984d40SFabiano Rosas } 3427f0984d40SFabiano Rosas 3428f0984d40SFabiano Rosas static bool trans_VNEG_F(DisasContext *s, arg_2misc *a) 3429f0984d40SFabiano Rosas { 3430f0984d40SFabiano Rosas if (a->size == MO_16) { 3431f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_fp16_arith, s)) { 3432f0984d40SFabiano Rosas return false; 3433f0984d40SFabiano Rosas } 3434f0984d40SFabiano Rosas } else if (a->size != MO_32) { 3435f0984d40SFabiano Rosas return false; 3436f0984d40SFabiano Rosas } 3437f0984d40SFabiano Rosas return do_2misc_vec(s, a, gen_VNEG_F); 3438f0984d40SFabiano Rosas } 3439f0984d40SFabiano Rosas 3440f0984d40SFabiano Rosas static bool trans_VRECPE(DisasContext *s, arg_2misc *a) 3441f0984d40SFabiano Rosas { 3442f0984d40SFabiano Rosas if (a->size != 2) { 3443f0984d40SFabiano Rosas return false; 3444f0984d40SFabiano Rosas } 3445f0984d40SFabiano Rosas return do_2misc(s, a, gen_helper_recpe_u32); 3446f0984d40SFabiano Rosas } 3447f0984d40SFabiano Rosas 3448f0984d40SFabiano Rosas static bool trans_VRSQRTE(DisasContext *s, arg_2misc *a) 3449f0984d40SFabiano Rosas { 3450f0984d40SFabiano Rosas if (a->size != 2) { 3451f0984d40SFabiano Rosas return false; 3452f0984d40SFabiano Rosas } 3453f0984d40SFabiano Rosas return do_2misc(s, a, gen_helper_rsqrte_u32); 3454f0984d40SFabiano Rosas } 3455f0984d40SFabiano Rosas 3456f0984d40SFabiano Rosas #define WRAP_1OP_ENV_FN(WRAPNAME, FUNC) \ 3457f0984d40SFabiano Rosas static void WRAPNAME(TCGv_i32 d, TCGv_i32 m) \ 3458f0984d40SFabiano Rosas { \ 3459ad75a51eSRichard Henderson FUNC(d, tcg_env, m); \ 3460f0984d40SFabiano Rosas } 3461f0984d40SFabiano Rosas 3462f0984d40SFabiano Rosas WRAP_1OP_ENV_FN(gen_VQABS_s8, gen_helper_neon_qabs_s8) 3463f0984d40SFabiano Rosas WRAP_1OP_ENV_FN(gen_VQABS_s16, gen_helper_neon_qabs_s16) 3464f0984d40SFabiano Rosas WRAP_1OP_ENV_FN(gen_VQABS_s32, gen_helper_neon_qabs_s32) 3465f0984d40SFabiano Rosas WRAP_1OP_ENV_FN(gen_VQNEG_s8, gen_helper_neon_qneg_s8) 3466f0984d40SFabiano Rosas WRAP_1OP_ENV_FN(gen_VQNEG_s16, gen_helper_neon_qneg_s16) 3467f0984d40SFabiano Rosas WRAP_1OP_ENV_FN(gen_VQNEG_s32, gen_helper_neon_qneg_s32) 3468f0984d40SFabiano Rosas 3469f0984d40SFabiano Rosas static bool trans_VQABS(DisasContext *s, arg_2misc *a) 3470f0984d40SFabiano Rosas { 3471f0984d40SFabiano Rosas static NeonGenOneOpFn * const fn[] = { 3472f0984d40SFabiano Rosas gen_VQABS_s8, 3473f0984d40SFabiano Rosas gen_VQABS_s16, 3474f0984d40SFabiano Rosas gen_VQABS_s32, 3475f0984d40SFabiano Rosas NULL, 3476f0984d40SFabiano Rosas }; 3477f0984d40SFabiano Rosas return do_2misc(s, a, fn[a->size]); 3478f0984d40SFabiano Rosas } 3479f0984d40SFabiano Rosas 3480f0984d40SFabiano Rosas static bool trans_VQNEG(DisasContext *s, arg_2misc *a) 3481f0984d40SFabiano Rosas { 3482f0984d40SFabiano Rosas static NeonGenOneOpFn * const fn[] = { 3483f0984d40SFabiano Rosas gen_VQNEG_s8, 3484f0984d40SFabiano Rosas gen_VQNEG_s16, 3485f0984d40SFabiano Rosas gen_VQNEG_s32, 3486f0984d40SFabiano Rosas NULL, 3487f0984d40SFabiano Rosas }; 3488f0984d40SFabiano Rosas return do_2misc(s, a, fn[a->size]); 3489f0984d40SFabiano Rosas } 3490f0984d40SFabiano Rosas 3491f0984d40SFabiano Rosas #define DO_2MISC_FP_VEC(INSN, HFUNC, SFUNC) \ 3492f0984d40SFabiano Rosas static void gen_##INSN(unsigned vece, uint32_t rd_ofs, \ 3493f0984d40SFabiano Rosas uint32_t rm_ofs, \ 3494f0984d40SFabiano Rosas uint32_t oprsz, uint32_t maxsz) \ 3495f0984d40SFabiano Rosas { \ 3496f0984d40SFabiano Rosas static gen_helper_gvec_2_ptr * const fns[4] = { \ 3497f0984d40SFabiano Rosas NULL, HFUNC, SFUNC, NULL, \ 3498f0984d40SFabiano Rosas }; \ 3499f0984d40SFabiano Rosas TCGv_ptr fpst; \ 3500f0984d40SFabiano Rosas fpst = fpstatus_ptr(vece == MO_16 ? FPST_STD_F16 : FPST_STD); \ 3501f0984d40SFabiano Rosas tcg_gen_gvec_2_ptr(rd_ofs, rm_ofs, fpst, oprsz, maxsz, 0, \ 3502f0984d40SFabiano Rosas fns[vece]); \ 3503f0984d40SFabiano Rosas } \ 3504f0984d40SFabiano Rosas static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ 3505f0984d40SFabiano Rosas { \ 3506f0984d40SFabiano Rosas if (a->size == MO_16) { \ 3507f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_fp16_arith, s)) { \ 3508f0984d40SFabiano Rosas return false; \ 3509f0984d40SFabiano Rosas } \ 3510f0984d40SFabiano Rosas } else if (a->size != MO_32) { \ 3511f0984d40SFabiano Rosas return false; \ 3512f0984d40SFabiano Rosas } \ 3513f0984d40SFabiano Rosas return do_2misc_vec(s, a, gen_##INSN); \ 3514f0984d40SFabiano Rosas } 3515f0984d40SFabiano Rosas 3516f0984d40SFabiano Rosas DO_2MISC_FP_VEC(VRECPE_F, gen_helper_gvec_frecpe_h, gen_helper_gvec_frecpe_s) 3517f0984d40SFabiano Rosas DO_2MISC_FP_VEC(VRSQRTE_F, gen_helper_gvec_frsqrte_h, gen_helper_gvec_frsqrte_s) 3518f0984d40SFabiano Rosas DO_2MISC_FP_VEC(VCGT0_F, gen_helper_gvec_fcgt0_h, gen_helper_gvec_fcgt0_s) 3519f0984d40SFabiano Rosas DO_2MISC_FP_VEC(VCGE0_F, gen_helper_gvec_fcge0_h, gen_helper_gvec_fcge0_s) 3520f0984d40SFabiano Rosas DO_2MISC_FP_VEC(VCEQ0_F, gen_helper_gvec_fceq0_h, gen_helper_gvec_fceq0_s) 3521f0984d40SFabiano Rosas DO_2MISC_FP_VEC(VCLT0_F, gen_helper_gvec_fclt0_h, gen_helper_gvec_fclt0_s) 3522f0984d40SFabiano Rosas DO_2MISC_FP_VEC(VCLE0_F, gen_helper_gvec_fcle0_h, gen_helper_gvec_fcle0_s) 3523f0984d40SFabiano Rosas DO_2MISC_FP_VEC(VCVT_FS, gen_helper_gvec_sstoh, gen_helper_gvec_sitos) 3524f0984d40SFabiano Rosas DO_2MISC_FP_VEC(VCVT_FU, gen_helper_gvec_ustoh, gen_helper_gvec_uitos) 3525f0984d40SFabiano Rosas DO_2MISC_FP_VEC(VCVT_SF, gen_helper_gvec_tosszh, gen_helper_gvec_tosizs) 3526f0984d40SFabiano Rosas DO_2MISC_FP_VEC(VCVT_UF, gen_helper_gvec_touszh, gen_helper_gvec_touizs) 3527f0984d40SFabiano Rosas 3528f0984d40SFabiano Rosas DO_2MISC_FP_VEC(VRINTX_impl, gen_helper_gvec_vrintx_h, gen_helper_gvec_vrintx_s) 3529f0984d40SFabiano Rosas 3530f0984d40SFabiano Rosas static bool trans_VRINTX(DisasContext *s, arg_2misc *a) 3531f0984d40SFabiano Rosas { 3532f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_V8)) { 3533f0984d40SFabiano Rosas return false; 3534f0984d40SFabiano Rosas } 3535f0984d40SFabiano Rosas return trans_VRINTX_impl(s, a); 3536f0984d40SFabiano Rosas } 3537f0984d40SFabiano Rosas 3538f0984d40SFabiano Rosas #define DO_VEC_RMODE(INSN, RMODE, OP) \ 3539f0984d40SFabiano Rosas static void gen_##INSN(unsigned vece, uint32_t rd_ofs, \ 3540f0984d40SFabiano Rosas uint32_t rm_ofs, \ 3541f0984d40SFabiano Rosas uint32_t oprsz, uint32_t maxsz) \ 3542f0984d40SFabiano Rosas { \ 3543f0984d40SFabiano Rosas static gen_helper_gvec_2_ptr * const fns[4] = { \ 3544f0984d40SFabiano Rosas NULL, \ 3545f0984d40SFabiano Rosas gen_helper_gvec_##OP##h, \ 3546f0984d40SFabiano Rosas gen_helper_gvec_##OP##s, \ 3547f0984d40SFabiano Rosas NULL, \ 3548f0984d40SFabiano Rosas }; \ 3549f0984d40SFabiano Rosas TCGv_ptr fpst; \ 3550f0984d40SFabiano Rosas fpst = fpstatus_ptr(vece == 1 ? FPST_STD_F16 : FPST_STD); \ 3551f0984d40SFabiano Rosas tcg_gen_gvec_2_ptr(rd_ofs, rm_ofs, fpst, oprsz, maxsz, \ 3552f0984d40SFabiano Rosas arm_rmode_to_sf(RMODE), fns[vece]); \ 3553f0984d40SFabiano Rosas } \ 3554f0984d40SFabiano Rosas static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ 3555f0984d40SFabiano Rosas { \ 3556f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_V8)) { \ 3557f0984d40SFabiano Rosas return false; \ 3558f0984d40SFabiano Rosas } \ 3559f0984d40SFabiano Rosas if (a->size == MO_16) { \ 3560f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_fp16_arith, s)) { \ 3561f0984d40SFabiano Rosas return false; \ 3562f0984d40SFabiano Rosas } \ 3563f0984d40SFabiano Rosas } else if (a->size != MO_32) { \ 3564f0984d40SFabiano Rosas return false; \ 3565f0984d40SFabiano Rosas } \ 3566f0984d40SFabiano Rosas return do_2misc_vec(s, a, gen_##INSN); \ 3567f0984d40SFabiano Rosas } 3568f0984d40SFabiano Rosas 3569f0984d40SFabiano Rosas DO_VEC_RMODE(VCVTAU, FPROUNDING_TIEAWAY, vcvt_rm_u) 3570f0984d40SFabiano Rosas DO_VEC_RMODE(VCVTAS, FPROUNDING_TIEAWAY, vcvt_rm_s) 3571f0984d40SFabiano Rosas DO_VEC_RMODE(VCVTNU, FPROUNDING_TIEEVEN, vcvt_rm_u) 3572f0984d40SFabiano Rosas DO_VEC_RMODE(VCVTNS, FPROUNDING_TIEEVEN, vcvt_rm_s) 3573f0984d40SFabiano Rosas DO_VEC_RMODE(VCVTPU, FPROUNDING_POSINF, vcvt_rm_u) 3574f0984d40SFabiano Rosas DO_VEC_RMODE(VCVTPS, FPROUNDING_POSINF, vcvt_rm_s) 3575f0984d40SFabiano Rosas DO_VEC_RMODE(VCVTMU, FPROUNDING_NEGINF, vcvt_rm_u) 3576f0984d40SFabiano Rosas DO_VEC_RMODE(VCVTMS, FPROUNDING_NEGINF, vcvt_rm_s) 3577f0984d40SFabiano Rosas 3578f0984d40SFabiano Rosas DO_VEC_RMODE(VRINTN, FPROUNDING_TIEEVEN, vrint_rm_) 3579f0984d40SFabiano Rosas DO_VEC_RMODE(VRINTA, FPROUNDING_TIEAWAY, vrint_rm_) 3580f0984d40SFabiano Rosas DO_VEC_RMODE(VRINTZ, FPROUNDING_ZERO, vrint_rm_) 3581f0984d40SFabiano Rosas DO_VEC_RMODE(VRINTM, FPROUNDING_NEGINF, vrint_rm_) 3582f0984d40SFabiano Rosas DO_VEC_RMODE(VRINTP, FPROUNDING_POSINF, vrint_rm_) 3583f0984d40SFabiano Rosas 3584f0984d40SFabiano Rosas static bool trans_VSWP(DisasContext *s, arg_2misc *a) 3585f0984d40SFabiano Rosas { 3586f0984d40SFabiano Rosas TCGv_i64 rm, rd; 3587f0984d40SFabiano Rosas int pass; 3588f0984d40SFabiano Rosas 3589f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 3590f0984d40SFabiano Rosas return false; 3591f0984d40SFabiano Rosas } 3592f0984d40SFabiano Rosas 3593f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 3594f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 3595f0984d40SFabiano Rosas ((a->vd | a->vm) & 0x10)) { 3596f0984d40SFabiano Rosas return false; 3597f0984d40SFabiano Rosas } 3598f0984d40SFabiano Rosas 3599f0984d40SFabiano Rosas if (a->size != 0) { 3600f0984d40SFabiano Rosas return false; 3601f0984d40SFabiano Rosas } 3602f0984d40SFabiano Rosas 3603f0984d40SFabiano Rosas if ((a->vd | a->vm) & a->q) { 3604f0984d40SFabiano Rosas return false; 3605f0984d40SFabiano Rosas } 3606f0984d40SFabiano Rosas 3607f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 3608f0984d40SFabiano Rosas return true; 3609f0984d40SFabiano Rosas } 3610f0984d40SFabiano Rosas 3611f0984d40SFabiano Rosas rm = tcg_temp_new_i64(); 3612f0984d40SFabiano Rosas rd = tcg_temp_new_i64(); 3613f0984d40SFabiano Rosas for (pass = 0; pass < (a->q ? 2 : 1); pass++) { 3614f0984d40SFabiano Rosas read_neon_element64(rm, a->vm, pass, MO_64); 3615f0984d40SFabiano Rosas read_neon_element64(rd, a->vd, pass, MO_64); 3616f0984d40SFabiano Rosas write_neon_element64(rm, a->vd, pass, MO_64); 3617f0984d40SFabiano Rosas write_neon_element64(rd, a->vm, pass, MO_64); 3618f0984d40SFabiano Rosas } 3619f0984d40SFabiano Rosas return true; 3620f0984d40SFabiano Rosas } 362124f4531dSRichard Henderson 3622f0984d40SFabiano Rosas static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1) 3623f0984d40SFabiano Rosas { 3624f0984d40SFabiano Rosas TCGv_i32 rd, tmp; 3625f0984d40SFabiano Rosas 3626f0984d40SFabiano Rosas rd = tcg_temp_new_i32(); 3627f0984d40SFabiano Rosas tmp = tcg_temp_new_i32(); 3628f0984d40SFabiano Rosas 3629f0984d40SFabiano Rosas tcg_gen_shli_i32(rd, t0, 8); 3630f0984d40SFabiano Rosas tcg_gen_andi_i32(rd, rd, 0xff00ff00); 3631f0984d40SFabiano Rosas tcg_gen_andi_i32(tmp, t1, 0x00ff00ff); 3632f0984d40SFabiano Rosas tcg_gen_or_i32(rd, rd, tmp); 3633f0984d40SFabiano Rosas 3634f0984d40SFabiano Rosas tcg_gen_shri_i32(t1, t1, 8); 3635f0984d40SFabiano Rosas tcg_gen_andi_i32(t1, t1, 0x00ff00ff); 3636f0984d40SFabiano Rosas tcg_gen_andi_i32(tmp, t0, 0xff00ff00); 3637f0984d40SFabiano Rosas tcg_gen_or_i32(t1, t1, tmp); 3638f0984d40SFabiano Rosas tcg_gen_mov_i32(t0, rd); 3639f0984d40SFabiano Rosas } 3640f0984d40SFabiano Rosas 3641f0984d40SFabiano Rosas static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1) 3642f0984d40SFabiano Rosas { 3643f0984d40SFabiano Rosas TCGv_i32 rd, tmp; 3644f0984d40SFabiano Rosas 3645f0984d40SFabiano Rosas rd = tcg_temp_new_i32(); 3646f0984d40SFabiano Rosas tmp = tcg_temp_new_i32(); 3647f0984d40SFabiano Rosas 3648f0984d40SFabiano Rosas tcg_gen_shli_i32(rd, t0, 16); 3649f0984d40SFabiano Rosas tcg_gen_andi_i32(tmp, t1, 0xffff); 3650f0984d40SFabiano Rosas tcg_gen_or_i32(rd, rd, tmp); 3651f0984d40SFabiano Rosas tcg_gen_shri_i32(t1, t1, 16); 3652f0984d40SFabiano Rosas tcg_gen_andi_i32(tmp, t0, 0xffff0000); 3653f0984d40SFabiano Rosas tcg_gen_or_i32(t1, t1, tmp); 3654f0984d40SFabiano Rosas tcg_gen_mov_i32(t0, rd); 3655f0984d40SFabiano Rosas } 3656f0984d40SFabiano Rosas 3657f0984d40SFabiano Rosas static bool trans_VTRN(DisasContext *s, arg_2misc *a) 3658f0984d40SFabiano Rosas { 3659f0984d40SFabiano Rosas TCGv_i32 tmp, tmp2; 3660f0984d40SFabiano Rosas int pass; 3661f0984d40SFabiano Rosas 3662f0984d40SFabiano Rosas if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { 3663f0984d40SFabiano Rosas return false; 3664f0984d40SFabiano Rosas } 3665f0984d40SFabiano Rosas 3666f0984d40SFabiano Rosas /* UNDEF accesses to D16-D31 if they don't exist. */ 3667f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_simd_r32, s) && 3668f0984d40SFabiano Rosas ((a->vd | a->vm) & 0x10)) { 3669f0984d40SFabiano Rosas return false; 3670f0984d40SFabiano Rosas } 3671f0984d40SFabiano Rosas 3672f0984d40SFabiano Rosas if ((a->vd | a->vm) & a->q) { 3673f0984d40SFabiano Rosas return false; 3674f0984d40SFabiano Rosas } 3675f0984d40SFabiano Rosas 3676f0984d40SFabiano Rosas if (a->size == 3) { 3677f0984d40SFabiano Rosas return false; 3678f0984d40SFabiano Rosas } 3679f0984d40SFabiano Rosas 3680f0984d40SFabiano Rosas if (!vfp_access_check(s)) { 3681f0984d40SFabiano Rosas return true; 3682f0984d40SFabiano Rosas } 3683f0984d40SFabiano Rosas 3684f0984d40SFabiano Rosas tmp = tcg_temp_new_i32(); 3685f0984d40SFabiano Rosas tmp2 = tcg_temp_new_i32(); 3686f0984d40SFabiano Rosas if (a->size == MO_32) { 3687f0984d40SFabiano Rosas for (pass = 0; pass < (a->q ? 4 : 2); pass += 2) { 3688f0984d40SFabiano Rosas read_neon_element32(tmp, a->vm, pass, MO_32); 3689f0984d40SFabiano Rosas read_neon_element32(tmp2, a->vd, pass + 1, MO_32); 3690f0984d40SFabiano Rosas write_neon_element32(tmp2, a->vm, pass, MO_32); 3691f0984d40SFabiano Rosas write_neon_element32(tmp, a->vd, pass + 1, MO_32); 3692f0984d40SFabiano Rosas } 3693f0984d40SFabiano Rosas } else { 3694f0984d40SFabiano Rosas for (pass = 0; pass < (a->q ? 4 : 2); pass++) { 3695f0984d40SFabiano Rosas read_neon_element32(tmp, a->vm, pass, MO_32); 3696f0984d40SFabiano Rosas read_neon_element32(tmp2, a->vd, pass, MO_32); 3697f0984d40SFabiano Rosas if (a->size == MO_8) { 3698f0984d40SFabiano Rosas gen_neon_trn_u8(tmp, tmp2); 3699f0984d40SFabiano Rosas } else { 3700f0984d40SFabiano Rosas gen_neon_trn_u16(tmp, tmp2); 3701f0984d40SFabiano Rosas } 3702f0984d40SFabiano Rosas write_neon_element32(tmp2, a->vm, pass, MO_32); 3703f0984d40SFabiano Rosas write_neon_element32(tmp, a->vd, pass, MO_32); 3704f0984d40SFabiano Rosas } 3705f0984d40SFabiano Rosas } 3706f0984d40SFabiano Rosas return true; 3707f0984d40SFabiano Rosas } 3708f0984d40SFabiano Rosas 3709f0984d40SFabiano Rosas static bool trans_VSMMLA(DisasContext *s, arg_VSMMLA *a) 3710f0984d40SFabiano Rosas { 3711f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_i8mm, s)) { 3712f0984d40SFabiano Rosas return false; 3713f0984d40SFabiano Rosas } 3714f0984d40SFabiano Rosas return do_neon_ddda(s, 7, a->vd, a->vn, a->vm, 0, 3715f0984d40SFabiano Rosas gen_helper_gvec_smmla_b); 3716f0984d40SFabiano Rosas } 3717f0984d40SFabiano Rosas 3718f0984d40SFabiano Rosas static bool trans_VUMMLA(DisasContext *s, arg_VUMMLA *a) 3719f0984d40SFabiano Rosas { 3720f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_i8mm, s)) { 3721f0984d40SFabiano Rosas return false; 3722f0984d40SFabiano Rosas } 3723f0984d40SFabiano Rosas return do_neon_ddda(s, 7, a->vd, a->vn, a->vm, 0, 3724f0984d40SFabiano Rosas gen_helper_gvec_ummla_b); 3725f0984d40SFabiano Rosas } 3726f0984d40SFabiano Rosas 3727f0984d40SFabiano Rosas static bool trans_VUSMMLA(DisasContext *s, arg_VUSMMLA *a) 3728f0984d40SFabiano Rosas { 3729f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_i8mm, s)) { 3730f0984d40SFabiano Rosas return false; 3731f0984d40SFabiano Rosas } 3732f0984d40SFabiano Rosas return do_neon_ddda(s, 7, a->vd, a->vn, a->vm, 0, 3733f0984d40SFabiano Rosas gen_helper_gvec_usmmla_b); 3734f0984d40SFabiano Rosas } 3735f0984d40SFabiano Rosas 3736f0984d40SFabiano Rosas static bool trans_VMMLA_b16(DisasContext *s, arg_VMMLA_b16 *a) 3737f0984d40SFabiano Rosas { 3738f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_bf16, s)) { 3739f0984d40SFabiano Rosas return false; 3740f0984d40SFabiano Rosas } 3741f0984d40SFabiano Rosas return do_neon_ddda(s, 7, a->vd, a->vn, a->vm, 0, 3742f0984d40SFabiano Rosas gen_helper_gvec_bfmmla); 3743f0984d40SFabiano Rosas } 3744f0984d40SFabiano Rosas 3745f0984d40SFabiano Rosas static bool trans_VFMA_b16(DisasContext *s, arg_VFMA_b16 *a) 3746f0984d40SFabiano Rosas { 3747f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_bf16, s)) { 3748f0984d40SFabiano Rosas return false; 3749f0984d40SFabiano Rosas } 3750f0984d40SFabiano Rosas return do_neon_ddda_fpst(s, 7, a->vd, a->vn, a->vm, a->q, FPST_STD, 3751f0984d40SFabiano Rosas gen_helper_gvec_bfmlal); 3752f0984d40SFabiano Rosas } 3753f0984d40SFabiano Rosas 3754f0984d40SFabiano Rosas static bool trans_VFMA_b16_scal(DisasContext *s, arg_VFMA_b16_scal *a) 3755f0984d40SFabiano Rosas { 3756f0984d40SFabiano Rosas if (!dc_isar_feature(aa32_bf16, s)) { 3757f0984d40SFabiano Rosas return false; 3758f0984d40SFabiano Rosas } 3759f0984d40SFabiano Rosas return do_neon_ddda_fpst(s, 6, a->vd, a->vn, a->vm, 3760f0984d40SFabiano Rosas (a->index << 1) | a->q, FPST_STD, 3761f0984d40SFabiano Rosas gen_helper_gvec_bfmlal_idx); 3762f0984d40SFabiano Rosas } 3763