1*f0984d40SFabiano Rosas# AArch64 SME allowed instruction decoding 2*f0984d40SFabiano Rosas# 3*f0984d40SFabiano Rosas# Copyright (c) 2022 Linaro, Ltd 4*f0984d40SFabiano Rosas# 5*f0984d40SFabiano Rosas# This library is free software; you can redistribute it and/or 6*f0984d40SFabiano Rosas# modify it under the terms of the GNU Lesser General Public 7*f0984d40SFabiano Rosas# License as published by the Free Software Foundation; either 8*f0984d40SFabiano Rosas# version 2.1 of the License, or (at your option) any later version. 9*f0984d40SFabiano Rosas# 10*f0984d40SFabiano Rosas# This library is distributed in the hope that it will be useful, 11*f0984d40SFabiano Rosas# but WITHOUT ANY WARRANTY; without even the implied warranty of 12*f0984d40SFabiano Rosas# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13*f0984d40SFabiano Rosas# Lesser General Public License for more details. 14*f0984d40SFabiano Rosas# 15*f0984d40SFabiano Rosas# You should have received a copy of the GNU Lesser General Public 16*f0984d40SFabiano Rosas# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17*f0984d40SFabiano Rosas 18*f0984d40SFabiano Rosas# 19*f0984d40SFabiano Rosas# This file is processed by scripts/decodetree.py 20*f0984d40SFabiano Rosas# 21*f0984d40SFabiano Rosas 22*f0984d40SFabiano Rosas# These patterns are taken from Appendix E1.1 of DDI0616 A.a, 23*f0984d40SFabiano Rosas# Arm Architecture Reference Manual Supplement, 24*f0984d40SFabiano Rosas# The Scalable Matrix Extension (SME), for Armv9-A 25*f0984d40SFabiano Rosas 26*f0984d40SFabiano Rosas{ 27*f0984d40SFabiano Rosas [ 28*f0984d40SFabiano Rosas OK 0-00 1110 0000 0001 0010 11-- ---- ---- # SMOV W|Xd,Vn.B[0] 29*f0984d40SFabiano Rosas OK 0-00 1110 0000 0010 0010 11-- ---- ---- # SMOV W|Xd,Vn.H[0] 30*f0984d40SFabiano Rosas OK 0100 1110 0000 0100 0010 11-- ---- ---- # SMOV Xd,Vn.S[0] 31*f0984d40SFabiano Rosas OK 0000 1110 0000 0001 0011 11-- ---- ---- # UMOV Wd,Vn.B[0] 32*f0984d40SFabiano Rosas OK 0000 1110 0000 0010 0011 11-- ---- ---- # UMOV Wd,Vn.H[0] 33*f0984d40SFabiano Rosas OK 0000 1110 0000 0100 0011 11-- ---- ---- # UMOV Wd,Vn.S[0] 34*f0984d40SFabiano Rosas OK 0100 1110 0000 1000 0011 11-- ---- ---- # UMOV Xd,Vn.D[0] 35*f0984d40SFabiano Rosas ] 36*f0984d40SFabiano Rosas FAIL 0--0 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD vector operations 37*f0984d40SFabiano Rosas} 38*f0984d40SFabiano Rosas 39*f0984d40SFabiano Rosas{ 40*f0984d40SFabiano Rosas [ 41*f0984d40SFabiano Rosas OK 0101 1110 --1- ---- 11-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (scalar) 42*f0984d40SFabiano Rosas OK 0101 1110 -10- ---- 00-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (scalar, FP16) 43*f0984d40SFabiano Rosas OK 01-1 1110 1-10 0001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX (scalar) 44*f0984d40SFabiano Rosas OK 01-1 1110 1111 1001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX (scalar, FP16) 45*f0984d40SFabiano Rosas ] 46*f0984d40SFabiano Rosas FAIL 01-1 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD single-element operations 47*f0984d40SFabiano Rosas} 48*f0984d40SFabiano Rosas 49*f0984d40SFabiano RosasFAIL 0-00 110- ---- ---- ---- ---- ---- ---- # Advanced SIMD structure load/store 50*f0984d40SFabiano RosasFAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography extensions 51*f0984d40SFabiano RosasFAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS 52*f0984d40SFabiano Rosas 53*f0984d40SFabiano Rosas# These are the "avoidance of doubt" final table of Illegal Advanced SIMD instructions 54*f0984d40SFabiano Rosas# We don't actually need to include these, as the default is OK. 55*f0984d40SFabiano Rosas# -001 111- ---- ---- ---- ---- ---- ---- # Scalar floating-point operations 56*f0984d40SFabiano Rosas# --10 110- ---- ---- ---- ---- ---- ---- # Load/store pair of FP registers 57*f0984d40SFabiano Rosas# --01 1100 ---- ---- ---- ---- ---- ---- # Load FP register (PC-relative literal) 58*f0984d40SFabiano Rosas# --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register (unscaled imm) 59*f0984d40SFabiano Rosas# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) 60*f0984d40SFabiano Rosas# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) 61