1gen = [ 2 decodetree.process('sve.decode', extra_args: '--decode=disas_sve'), 3 decodetree.process('sme.decode', extra_args: '--decode=disas_sme'), 4 decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'), 5 decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'), 6 decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'), 7 decodetree.process('vfp.decode', extra_args: '--decode=disas_vfp'), 8 decodetree.process('vfp-uncond.decode', extra_args: '--decode=disas_vfp_uncond'), 9 decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'), 10 decodetree.process('mve.decode', extra_args: '--decode=disas_mve'), 11 decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'), 12 decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'), 13 decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'), 14 decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']), 15] 16 17arm_ss = ss.source_set() 18arm_ss.add(gen) 19arm_ss.add(files( 20 'cpu.c', 21 'crypto_helper.c', 22 'debug_helper.c', 23 'gdbstub.c', 24 'helper.c', 25 'iwmmxt_helper.c', 26 'm_helper.c', 27 'mve_helper.c', 28 'neon_helper.c', 29 'op_helper.c', 30 'tlb_helper.c', 31 'translate.c', 32 'translate-m-nocp.c', 33 'translate-mve.c', 34 'translate-neon.c', 35 'translate-vfp.c', 36 'vec_helper.c', 37 'vfp_helper.c', 38 'cpu_tcg.c', 39)) 40arm_ss.add(zlib) 41 42arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c')) 43 44arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 45 'cpu64.c', 46 'gdbstub64.c', 47 'helper-a64.c', 48 'mte_helper.c', 49 'pauth_helper.c', 50 'sve_helper.c', 51 'sme_helper.c', 52 'translate-a64.c', 53 'translate-sve.c', 54 'translate-sme.c', 55)) 56 57arm_softmmu_ss = ss.source_set() 58arm_softmmu_ss.add(files( 59 'arch_dump.c', 60 'arm-powerctl.c', 61 'machine.c', 62 'monitor.c', 63 'psci.c', 64 'ptw.c', 65)) 66 67subdir('hvf') 68 69target_arch += {'arm': arm_ss} 70target_softmmu_arch += {'arm': arm_softmmu_ss} 71