1 /* 2 * QEMU Hypervisor.framework support for Apple Silicon 3 4 * Copyright 2020 Alexander Graf <agraf@csgraf.de> 5 * Copyright 2020 Google LLC 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or later. 8 * See the COPYING file in the top-level directory. 9 * 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/error-report.h" 14 15 #include "sysemu/runstate.h" 16 #include "sysemu/hvf.h" 17 #include "sysemu/hvf_int.h" 18 #include "sysemu/hw_accel.h" 19 #include "hvf_arm.h" 20 #include "cpregs.h" 21 22 #include <mach/mach_time.h> 23 24 #include "exec/address-spaces.h" 25 #include "hw/irq.h" 26 #include "qemu/main-loop.h" 27 #include "sysemu/cpus.h" 28 #include "arm-powerctl.h" 29 #include "target/arm/cpu.h" 30 #include "target/arm/internals.h" 31 #include "target/arm/multiprocessing.h" 32 #include "trace/trace-target_arm_hvf.h" 33 #include "migration/vmstate.h" 34 35 #include "exec/gdbstub.h" 36 37 #define MDSCR_EL1_SS_SHIFT 0 38 #define MDSCR_EL1_MDE_SHIFT 15 39 40 static const uint16_t dbgbcr_regs[] = { 41 HV_SYS_REG_DBGBCR0_EL1, 42 HV_SYS_REG_DBGBCR1_EL1, 43 HV_SYS_REG_DBGBCR2_EL1, 44 HV_SYS_REG_DBGBCR3_EL1, 45 HV_SYS_REG_DBGBCR4_EL1, 46 HV_SYS_REG_DBGBCR5_EL1, 47 HV_SYS_REG_DBGBCR6_EL1, 48 HV_SYS_REG_DBGBCR7_EL1, 49 HV_SYS_REG_DBGBCR8_EL1, 50 HV_SYS_REG_DBGBCR9_EL1, 51 HV_SYS_REG_DBGBCR10_EL1, 52 HV_SYS_REG_DBGBCR11_EL1, 53 HV_SYS_REG_DBGBCR12_EL1, 54 HV_SYS_REG_DBGBCR13_EL1, 55 HV_SYS_REG_DBGBCR14_EL1, 56 HV_SYS_REG_DBGBCR15_EL1, 57 }; 58 59 static const uint16_t dbgbvr_regs[] = { 60 HV_SYS_REG_DBGBVR0_EL1, 61 HV_SYS_REG_DBGBVR1_EL1, 62 HV_SYS_REG_DBGBVR2_EL1, 63 HV_SYS_REG_DBGBVR3_EL1, 64 HV_SYS_REG_DBGBVR4_EL1, 65 HV_SYS_REG_DBGBVR5_EL1, 66 HV_SYS_REG_DBGBVR6_EL1, 67 HV_SYS_REG_DBGBVR7_EL1, 68 HV_SYS_REG_DBGBVR8_EL1, 69 HV_SYS_REG_DBGBVR9_EL1, 70 HV_SYS_REG_DBGBVR10_EL1, 71 HV_SYS_REG_DBGBVR11_EL1, 72 HV_SYS_REG_DBGBVR12_EL1, 73 HV_SYS_REG_DBGBVR13_EL1, 74 HV_SYS_REG_DBGBVR14_EL1, 75 HV_SYS_REG_DBGBVR15_EL1, 76 }; 77 78 static const uint16_t dbgwcr_regs[] = { 79 HV_SYS_REG_DBGWCR0_EL1, 80 HV_SYS_REG_DBGWCR1_EL1, 81 HV_SYS_REG_DBGWCR2_EL1, 82 HV_SYS_REG_DBGWCR3_EL1, 83 HV_SYS_REG_DBGWCR4_EL1, 84 HV_SYS_REG_DBGWCR5_EL1, 85 HV_SYS_REG_DBGWCR6_EL1, 86 HV_SYS_REG_DBGWCR7_EL1, 87 HV_SYS_REG_DBGWCR8_EL1, 88 HV_SYS_REG_DBGWCR9_EL1, 89 HV_SYS_REG_DBGWCR10_EL1, 90 HV_SYS_REG_DBGWCR11_EL1, 91 HV_SYS_REG_DBGWCR12_EL1, 92 HV_SYS_REG_DBGWCR13_EL1, 93 HV_SYS_REG_DBGWCR14_EL1, 94 HV_SYS_REG_DBGWCR15_EL1, 95 }; 96 97 static const uint16_t dbgwvr_regs[] = { 98 HV_SYS_REG_DBGWVR0_EL1, 99 HV_SYS_REG_DBGWVR1_EL1, 100 HV_SYS_REG_DBGWVR2_EL1, 101 HV_SYS_REG_DBGWVR3_EL1, 102 HV_SYS_REG_DBGWVR4_EL1, 103 HV_SYS_REG_DBGWVR5_EL1, 104 HV_SYS_REG_DBGWVR6_EL1, 105 HV_SYS_REG_DBGWVR7_EL1, 106 HV_SYS_REG_DBGWVR8_EL1, 107 HV_SYS_REG_DBGWVR9_EL1, 108 HV_SYS_REG_DBGWVR10_EL1, 109 HV_SYS_REG_DBGWVR11_EL1, 110 HV_SYS_REG_DBGWVR12_EL1, 111 HV_SYS_REG_DBGWVR13_EL1, 112 HV_SYS_REG_DBGWVR14_EL1, 113 HV_SYS_REG_DBGWVR15_EL1, 114 }; 115 116 static inline int hvf_arm_num_brps(hv_vcpu_config_t config) 117 { 118 uint64_t val; 119 hv_return_t ret; 120 ret = hv_vcpu_config_get_feature_reg(config, HV_FEATURE_REG_ID_AA64DFR0_EL1, 121 &val); 122 assert_hvf_ok(ret); 123 return FIELD_EX64(val, ID_AA64DFR0, BRPS) + 1; 124 } 125 126 static inline int hvf_arm_num_wrps(hv_vcpu_config_t config) 127 { 128 uint64_t val; 129 hv_return_t ret; 130 ret = hv_vcpu_config_get_feature_reg(config, HV_FEATURE_REG_ID_AA64DFR0_EL1, 131 &val); 132 assert_hvf_ok(ret); 133 return FIELD_EX64(val, ID_AA64DFR0, WRPS) + 1; 134 } 135 136 void hvf_arm_init_debug(void) 137 { 138 hv_vcpu_config_t config; 139 config = hv_vcpu_config_create(); 140 141 max_hw_bps = hvf_arm_num_brps(config); 142 hw_breakpoints = 143 g_array_sized_new(true, true, sizeof(HWBreakpoint), max_hw_bps); 144 145 max_hw_wps = hvf_arm_num_wrps(config); 146 hw_watchpoints = 147 g_array_sized_new(true, true, sizeof(HWWatchpoint), max_hw_wps); 148 } 149 150 #define HVF_SYSREG(crn, crm, op0, op1, op2) \ 151 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) 152 #define PL1_WRITE_MASK 0x4 153 154 #define SYSREG_OP0_SHIFT 20 155 #define SYSREG_OP0_MASK 0x3 156 #define SYSREG_OP0(sysreg) ((sysreg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK) 157 #define SYSREG_OP1_SHIFT 14 158 #define SYSREG_OP1_MASK 0x7 159 #define SYSREG_OP1(sysreg) ((sysreg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK) 160 #define SYSREG_CRN_SHIFT 10 161 #define SYSREG_CRN_MASK 0xf 162 #define SYSREG_CRN(sysreg) ((sysreg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK) 163 #define SYSREG_CRM_SHIFT 1 164 #define SYSREG_CRM_MASK 0xf 165 #define SYSREG_CRM(sysreg) ((sysreg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK) 166 #define SYSREG_OP2_SHIFT 17 167 #define SYSREG_OP2_MASK 0x7 168 #define SYSREG_OP2(sysreg) ((sysreg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK) 169 170 #define SYSREG(op0, op1, crn, crm, op2) \ 171 ((op0 << SYSREG_OP0_SHIFT) | \ 172 (op1 << SYSREG_OP1_SHIFT) | \ 173 (crn << SYSREG_CRN_SHIFT) | \ 174 (crm << SYSREG_CRM_SHIFT) | \ 175 (op2 << SYSREG_OP2_SHIFT)) 176 #define SYSREG_MASK \ 177 SYSREG(SYSREG_OP0_MASK, \ 178 SYSREG_OP1_MASK, \ 179 SYSREG_CRN_MASK, \ 180 SYSREG_CRM_MASK, \ 181 SYSREG_OP2_MASK) 182 #define SYSREG_OSLAR_EL1 SYSREG(2, 0, 1, 0, 4) 183 #define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4) 184 #define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4) 185 #define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1) 186 #define SYSREG_PMCR_EL0 SYSREG(3, 3, 9, 12, 0) 187 #define SYSREG_PMUSERENR_EL0 SYSREG(3, 3, 9, 14, 0) 188 #define SYSREG_PMCNTENSET_EL0 SYSREG(3, 3, 9, 12, 1) 189 #define SYSREG_PMCNTENCLR_EL0 SYSREG(3, 3, 9, 12, 2) 190 #define SYSREG_PMINTENCLR_EL1 SYSREG(3, 0, 9, 14, 2) 191 #define SYSREG_PMOVSCLR_EL0 SYSREG(3, 3, 9, 12, 3) 192 #define SYSREG_PMSWINC_EL0 SYSREG(3, 3, 9, 12, 4) 193 #define SYSREG_PMSELR_EL0 SYSREG(3, 3, 9, 12, 5) 194 #define SYSREG_PMCEID0_EL0 SYSREG(3, 3, 9, 12, 6) 195 #define SYSREG_PMCEID1_EL0 SYSREG(3, 3, 9, 12, 7) 196 #define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0) 197 #define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7) 198 199 #define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 12, 8, 4) 200 #define SYSREG_ICC_AP0R1_EL1 SYSREG(3, 0, 12, 8, 5) 201 #define SYSREG_ICC_AP0R2_EL1 SYSREG(3, 0, 12, 8, 6) 202 #define SYSREG_ICC_AP0R3_EL1 SYSREG(3, 0, 12, 8, 7) 203 #define SYSREG_ICC_AP1R0_EL1 SYSREG(3, 0, 12, 9, 0) 204 #define SYSREG_ICC_AP1R1_EL1 SYSREG(3, 0, 12, 9, 1) 205 #define SYSREG_ICC_AP1R2_EL1 SYSREG(3, 0, 12, 9, 2) 206 #define SYSREG_ICC_AP1R3_EL1 SYSREG(3, 0, 12, 9, 3) 207 #define SYSREG_ICC_ASGI1R_EL1 SYSREG(3, 0, 12, 11, 6) 208 #define SYSREG_ICC_BPR0_EL1 SYSREG(3, 0, 12, 8, 3) 209 #define SYSREG_ICC_BPR1_EL1 SYSREG(3, 0, 12, 12, 3) 210 #define SYSREG_ICC_CTLR_EL1 SYSREG(3, 0, 12, 12, 4) 211 #define SYSREG_ICC_DIR_EL1 SYSREG(3, 0, 12, 11, 1) 212 #define SYSREG_ICC_EOIR0_EL1 SYSREG(3, 0, 12, 8, 1) 213 #define SYSREG_ICC_EOIR1_EL1 SYSREG(3, 0, 12, 12, 1) 214 #define SYSREG_ICC_HPPIR0_EL1 SYSREG(3, 0, 12, 8, 2) 215 #define SYSREG_ICC_HPPIR1_EL1 SYSREG(3, 0, 12, 12, 2) 216 #define SYSREG_ICC_IAR0_EL1 SYSREG(3, 0, 12, 8, 0) 217 #define SYSREG_ICC_IAR1_EL1 SYSREG(3, 0, 12, 12, 0) 218 #define SYSREG_ICC_IGRPEN0_EL1 SYSREG(3, 0, 12, 12, 6) 219 #define SYSREG_ICC_IGRPEN1_EL1 SYSREG(3, 0, 12, 12, 7) 220 #define SYSREG_ICC_PMR_EL1 SYSREG(3, 0, 4, 6, 0) 221 #define SYSREG_ICC_RPR_EL1 SYSREG(3, 0, 12, 11, 3) 222 #define SYSREG_ICC_SGI0R_EL1 SYSREG(3, 0, 12, 11, 7) 223 #define SYSREG_ICC_SGI1R_EL1 SYSREG(3, 0, 12, 11, 5) 224 #define SYSREG_ICC_SRE_EL1 SYSREG(3, 0, 12, 12, 5) 225 226 #define SYSREG_MDSCR_EL1 SYSREG(2, 0, 0, 2, 2) 227 #define SYSREG_DBGBVR0_EL1 SYSREG(2, 0, 0, 0, 4) 228 #define SYSREG_DBGBCR0_EL1 SYSREG(2, 0, 0, 0, 5) 229 #define SYSREG_DBGWVR0_EL1 SYSREG(2, 0, 0, 0, 6) 230 #define SYSREG_DBGWCR0_EL1 SYSREG(2, 0, 0, 0, 7) 231 #define SYSREG_DBGBVR1_EL1 SYSREG(2, 0, 0, 1, 4) 232 #define SYSREG_DBGBCR1_EL1 SYSREG(2, 0, 0, 1, 5) 233 #define SYSREG_DBGWVR1_EL1 SYSREG(2, 0, 0, 1, 6) 234 #define SYSREG_DBGWCR1_EL1 SYSREG(2, 0, 0, 1, 7) 235 #define SYSREG_DBGBVR2_EL1 SYSREG(2, 0, 0, 2, 4) 236 #define SYSREG_DBGBCR2_EL1 SYSREG(2, 0, 0, 2, 5) 237 #define SYSREG_DBGWVR2_EL1 SYSREG(2, 0, 0, 2, 6) 238 #define SYSREG_DBGWCR2_EL1 SYSREG(2, 0, 0, 2, 7) 239 #define SYSREG_DBGBVR3_EL1 SYSREG(2, 0, 0, 3, 4) 240 #define SYSREG_DBGBCR3_EL1 SYSREG(2, 0, 0, 3, 5) 241 #define SYSREG_DBGWVR3_EL1 SYSREG(2, 0, 0, 3, 6) 242 #define SYSREG_DBGWCR3_EL1 SYSREG(2, 0, 0, 3, 7) 243 #define SYSREG_DBGBVR4_EL1 SYSREG(2, 0, 0, 4, 4) 244 #define SYSREG_DBGBCR4_EL1 SYSREG(2, 0, 0, 4, 5) 245 #define SYSREG_DBGWVR4_EL1 SYSREG(2, 0, 0, 4, 6) 246 #define SYSREG_DBGWCR4_EL1 SYSREG(2, 0, 0, 4, 7) 247 #define SYSREG_DBGBVR5_EL1 SYSREG(2, 0, 0, 5, 4) 248 #define SYSREG_DBGBCR5_EL1 SYSREG(2, 0, 0, 5, 5) 249 #define SYSREG_DBGWVR5_EL1 SYSREG(2, 0, 0, 5, 6) 250 #define SYSREG_DBGWCR5_EL1 SYSREG(2, 0, 0, 5, 7) 251 #define SYSREG_DBGBVR6_EL1 SYSREG(2, 0, 0, 6, 4) 252 #define SYSREG_DBGBCR6_EL1 SYSREG(2, 0, 0, 6, 5) 253 #define SYSREG_DBGWVR6_EL1 SYSREG(2, 0, 0, 6, 6) 254 #define SYSREG_DBGWCR6_EL1 SYSREG(2, 0, 0, 6, 7) 255 #define SYSREG_DBGBVR7_EL1 SYSREG(2, 0, 0, 7, 4) 256 #define SYSREG_DBGBCR7_EL1 SYSREG(2, 0, 0, 7, 5) 257 #define SYSREG_DBGWVR7_EL1 SYSREG(2, 0, 0, 7, 6) 258 #define SYSREG_DBGWCR7_EL1 SYSREG(2, 0, 0, 7, 7) 259 #define SYSREG_DBGBVR8_EL1 SYSREG(2, 0, 0, 8, 4) 260 #define SYSREG_DBGBCR8_EL1 SYSREG(2, 0, 0, 8, 5) 261 #define SYSREG_DBGWVR8_EL1 SYSREG(2, 0, 0, 8, 6) 262 #define SYSREG_DBGWCR8_EL1 SYSREG(2, 0, 0, 8, 7) 263 #define SYSREG_DBGBVR9_EL1 SYSREG(2, 0, 0, 9, 4) 264 #define SYSREG_DBGBCR9_EL1 SYSREG(2, 0, 0, 9, 5) 265 #define SYSREG_DBGWVR9_EL1 SYSREG(2, 0, 0, 9, 6) 266 #define SYSREG_DBGWCR9_EL1 SYSREG(2, 0, 0, 9, 7) 267 #define SYSREG_DBGBVR10_EL1 SYSREG(2, 0, 0, 10, 4) 268 #define SYSREG_DBGBCR10_EL1 SYSREG(2, 0, 0, 10, 5) 269 #define SYSREG_DBGWVR10_EL1 SYSREG(2, 0, 0, 10, 6) 270 #define SYSREG_DBGWCR10_EL1 SYSREG(2, 0, 0, 10, 7) 271 #define SYSREG_DBGBVR11_EL1 SYSREG(2, 0, 0, 11, 4) 272 #define SYSREG_DBGBCR11_EL1 SYSREG(2, 0, 0, 11, 5) 273 #define SYSREG_DBGWVR11_EL1 SYSREG(2, 0, 0, 11, 6) 274 #define SYSREG_DBGWCR11_EL1 SYSREG(2, 0, 0, 11, 7) 275 #define SYSREG_DBGBVR12_EL1 SYSREG(2, 0, 0, 12, 4) 276 #define SYSREG_DBGBCR12_EL1 SYSREG(2, 0, 0, 12, 5) 277 #define SYSREG_DBGWVR12_EL1 SYSREG(2, 0, 0, 12, 6) 278 #define SYSREG_DBGWCR12_EL1 SYSREG(2, 0, 0, 12, 7) 279 #define SYSREG_DBGBVR13_EL1 SYSREG(2, 0, 0, 13, 4) 280 #define SYSREG_DBGBCR13_EL1 SYSREG(2, 0, 0, 13, 5) 281 #define SYSREG_DBGWVR13_EL1 SYSREG(2, 0, 0, 13, 6) 282 #define SYSREG_DBGWCR13_EL1 SYSREG(2, 0, 0, 13, 7) 283 #define SYSREG_DBGBVR14_EL1 SYSREG(2, 0, 0, 14, 4) 284 #define SYSREG_DBGBCR14_EL1 SYSREG(2, 0, 0, 14, 5) 285 #define SYSREG_DBGWVR14_EL1 SYSREG(2, 0, 0, 14, 6) 286 #define SYSREG_DBGWCR14_EL1 SYSREG(2, 0, 0, 14, 7) 287 #define SYSREG_DBGBVR15_EL1 SYSREG(2, 0, 0, 15, 4) 288 #define SYSREG_DBGBCR15_EL1 SYSREG(2, 0, 0, 15, 5) 289 #define SYSREG_DBGWVR15_EL1 SYSREG(2, 0, 0, 15, 6) 290 #define SYSREG_DBGWCR15_EL1 SYSREG(2, 0, 0, 15, 7) 291 292 #define WFX_IS_WFE (1 << 0) 293 294 #define TMR_CTL_ENABLE (1 << 0) 295 #define TMR_CTL_IMASK (1 << 1) 296 #define TMR_CTL_ISTATUS (1 << 2) 297 298 static void hvf_wfi(CPUState *cpu); 299 300 typedef struct HVFVTimer { 301 /* Vtimer value during migration and paused state */ 302 uint64_t vtimer_val; 303 } HVFVTimer; 304 305 static HVFVTimer vtimer; 306 307 typedef struct ARMHostCPUFeatures { 308 ARMISARegisters isar; 309 uint64_t features; 310 uint64_t midr; 311 uint32_t reset_sctlr; 312 const char *dtb_compatible; 313 } ARMHostCPUFeatures; 314 315 static ARMHostCPUFeatures arm_host_cpu_features; 316 317 struct hvf_reg_match { 318 int reg; 319 uint64_t offset; 320 }; 321 322 static const struct hvf_reg_match hvf_reg_match[] = { 323 { HV_REG_X0, offsetof(CPUARMState, xregs[0]) }, 324 { HV_REG_X1, offsetof(CPUARMState, xregs[1]) }, 325 { HV_REG_X2, offsetof(CPUARMState, xregs[2]) }, 326 { HV_REG_X3, offsetof(CPUARMState, xregs[3]) }, 327 { HV_REG_X4, offsetof(CPUARMState, xregs[4]) }, 328 { HV_REG_X5, offsetof(CPUARMState, xregs[5]) }, 329 { HV_REG_X6, offsetof(CPUARMState, xregs[6]) }, 330 { HV_REG_X7, offsetof(CPUARMState, xregs[7]) }, 331 { HV_REG_X8, offsetof(CPUARMState, xregs[8]) }, 332 { HV_REG_X9, offsetof(CPUARMState, xregs[9]) }, 333 { HV_REG_X10, offsetof(CPUARMState, xregs[10]) }, 334 { HV_REG_X11, offsetof(CPUARMState, xregs[11]) }, 335 { HV_REG_X12, offsetof(CPUARMState, xregs[12]) }, 336 { HV_REG_X13, offsetof(CPUARMState, xregs[13]) }, 337 { HV_REG_X14, offsetof(CPUARMState, xregs[14]) }, 338 { HV_REG_X15, offsetof(CPUARMState, xregs[15]) }, 339 { HV_REG_X16, offsetof(CPUARMState, xregs[16]) }, 340 { HV_REG_X17, offsetof(CPUARMState, xregs[17]) }, 341 { HV_REG_X18, offsetof(CPUARMState, xregs[18]) }, 342 { HV_REG_X19, offsetof(CPUARMState, xregs[19]) }, 343 { HV_REG_X20, offsetof(CPUARMState, xregs[20]) }, 344 { HV_REG_X21, offsetof(CPUARMState, xregs[21]) }, 345 { HV_REG_X22, offsetof(CPUARMState, xregs[22]) }, 346 { HV_REG_X23, offsetof(CPUARMState, xregs[23]) }, 347 { HV_REG_X24, offsetof(CPUARMState, xregs[24]) }, 348 { HV_REG_X25, offsetof(CPUARMState, xregs[25]) }, 349 { HV_REG_X26, offsetof(CPUARMState, xregs[26]) }, 350 { HV_REG_X27, offsetof(CPUARMState, xregs[27]) }, 351 { HV_REG_X28, offsetof(CPUARMState, xregs[28]) }, 352 { HV_REG_X29, offsetof(CPUARMState, xregs[29]) }, 353 { HV_REG_X30, offsetof(CPUARMState, xregs[30]) }, 354 { HV_REG_PC, offsetof(CPUARMState, pc) }, 355 }; 356 357 static const struct hvf_reg_match hvf_fpreg_match[] = { 358 { HV_SIMD_FP_REG_Q0, offsetof(CPUARMState, vfp.zregs[0]) }, 359 { HV_SIMD_FP_REG_Q1, offsetof(CPUARMState, vfp.zregs[1]) }, 360 { HV_SIMD_FP_REG_Q2, offsetof(CPUARMState, vfp.zregs[2]) }, 361 { HV_SIMD_FP_REG_Q3, offsetof(CPUARMState, vfp.zregs[3]) }, 362 { HV_SIMD_FP_REG_Q4, offsetof(CPUARMState, vfp.zregs[4]) }, 363 { HV_SIMD_FP_REG_Q5, offsetof(CPUARMState, vfp.zregs[5]) }, 364 { HV_SIMD_FP_REG_Q6, offsetof(CPUARMState, vfp.zregs[6]) }, 365 { HV_SIMD_FP_REG_Q7, offsetof(CPUARMState, vfp.zregs[7]) }, 366 { HV_SIMD_FP_REG_Q8, offsetof(CPUARMState, vfp.zregs[8]) }, 367 { HV_SIMD_FP_REG_Q9, offsetof(CPUARMState, vfp.zregs[9]) }, 368 { HV_SIMD_FP_REG_Q10, offsetof(CPUARMState, vfp.zregs[10]) }, 369 { HV_SIMD_FP_REG_Q11, offsetof(CPUARMState, vfp.zregs[11]) }, 370 { HV_SIMD_FP_REG_Q12, offsetof(CPUARMState, vfp.zregs[12]) }, 371 { HV_SIMD_FP_REG_Q13, offsetof(CPUARMState, vfp.zregs[13]) }, 372 { HV_SIMD_FP_REG_Q14, offsetof(CPUARMState, vfp.zregs[14]) }, 373 { HV_SIMD_FP_REG_Q15, offsetof(CPUARMState, vfp.zregs[15]) }, 374 { HV_SIMD_FP_REG_Q16, offsetof(CPUARMState, vfp.zregs[16]) }, 375 { HV_SIMD_FP_REG_Q17, offsetof(CPUARMState, vfp.zregs[17]) }, 376 { HV_SIMD_FP_REG_Q18, offsetof(CPUARMState, vfp.zregs[18]) }, 377 { HV_SIMD_FP_REG_Q19, offsetof(CPUARMState, vfp.zregs[19]) }, 378 { HV_SIMD_FP_REG_Q20, offsetof(CPUARMState, vfp.zregs[20]) }, 379 { HV_SIMD_FP_REG_Q21, offsetof(CPUARMState, vfp.zregs[21]) }, 380 { HV_SIMD_FP_REG_Q22, offsetof(CPUARMState, vfp.zregs[22]) }, 381 { HV_SIMD_FP_REG_Q23, offsetof(CPUARMState, vfp.zregs[23]) }, 382 { HV_SIMD_FP_REG_Q24, offsetof(CPUARMState, vfp.zregs[24]) }, 383 { HV_SIMD_FP_REG_Q25, offsetof(CPUARMState, vfp.zregs[25]) }, 384 { HV_SIMD_FP_REG_Q26, offsetof(CPUARMState, vfp.zregs[26]) }, 385 { HV_SIMD_FP_REG_Q27, offsetof(CPUARMState, vfp.zregs[27]) }, 386 { HV_SIMD_FP_REG_Q28, offsetof(CPUARMState, vfp.zregs[28]) }, 387 { HV_SIMD_FP_REG_Q29, offsetof(CPUARMState, vfp.zregs[29]) }, 388 { HV_SIMD_FP_REG_Q30, offsetof(CPUARMState, vfp.zregs[30]) }, 389 { HV_SIMD_FP_REG_Q31, offsetof(CPUARMState, vfp.zregs[31]) }, 390 }; 391 392 struct hvf_sreg_match { 393 int reg; 394 uint32_t key; 395 uint32_t cp_idx; 396 }; 397 398 static struct hvf_sreg_match hvf_sreg_match[] = { 399 { HV_SYS_REG_DBGBVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 4) }, 400 { HV_SYS_REG_DBGBCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 5) }, 401 { HV_SYS_REG_DBGWVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 6) }, 402 { HV_SYS_REG_DBGWCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 7) }, 403 404 { HV_SYS_REG_DBGBVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 4) }, 405 { HV_SYS_REG_DBGBCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 5) }, 406 { HV_SYS_REG_DBGWVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 6) }, 407 { HV_SYS_REG_DBGWCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 7) }, 408 409 { HV_SYS_REG_DBGBVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 4) }, 410 { HV_SYS_REG_DBGBCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 5) }, 411 { HV_SYS_REG_DBGWVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 6) }, 412 { HV_SYS_REG_DBGWCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 7) }, 413 414 { HV_SYS_REG_DBGBVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 4) }, 415 { HV_SYS_REG_DBGBCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 5) }, 416 { HV_SYS_REG_DBGWVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 6) }, 417 { HV_SYS_REG_DBGWCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 7) }, 418 419 { HV_SYS_REG_DBGBVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 4) }, 420 { HV_SYS_REG_DBGBCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 5) }, 421 { HV_SYS_REG_DBGWVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 6) }, 422 { HV_SYS_REG_DBGWCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 7) }, 423 424 { HV_SYS_REG_DBGBVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 4) }, 425 { HV_SYS_REG_DBGBCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 5) }, 426 { HV_SYS_REG_DBGWVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 6) }, 427 { HV_SYS_REG_DBGWCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 7) }, 428 429 { HV_SYS_REG_DBGBVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 4) }, 430 { HV_SYS_REG_DBGBCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 5) }, 431 { HV_SYS_REG_DBGWVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 6) }, 432 { HV_SYS_REG_DBGWCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 7) }, 433 434 { HV_SYS_REG_DBGBVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 4) }, 435 { HV_SYS_REG_DBGBCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 5) }, 436 { HV_SYS_REG_DBGWVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 6) }, 437 { HV_SYS_REG_DBGWCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 7) }, 438 439 { HV_SYS_REG_DBGBVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 4) }, 440 { HV_SYS_REG_DBGBCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 5) }, 441 { HV_SYS_REG_DBGWVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 6) }, 442 { HV_SYS_REG_DBGWCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 7) }, 443 444 { HV_SYS_REG_DBGBVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 4) }, 445 { HV_SYS_REG_DBGBCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 5) }, 446 { HV_SYS_REG_DBGWVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 6) }, 447 { HV_SYS_REG_DBGWCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 7) }, 448 449 { HV_SYS_REG_DBGBVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 4) }, 450 { HV_SYS_REG_DBGBCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 5) }, 451 { HV_SYS_REG_DBGWVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 6) }, 452 { HV_SYS_REG_DBGWCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 7) }, 453 454 { HV_SYS_REG_DBGBVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 4) }, 455 { HV_SYS_REG_DBGBCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 5) }, 456 { HV_SYS_REG_DBGWVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 6) }, 457 { HV_SYS_REG_DBGWCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 7) }, 458 459 { HV_SYS_REG_DBGBVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 4) }, 460 { HV_SYS_REG_DBGBCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 5) }, 461 { HV_SYS_REG_DBGWVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 6) }, 462 { HV_SYS_REG_DBGWCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 7) }, 463 464 { HV_SYS_REG_DBGBVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 4) }, 465 { HV_SYS_REG_DBGBCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 5) }, 466 { HV_SYS_REG_DBGWVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 6) }, 467 { HV_SYS_REG_DBGWCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 7) }, 468 469 { HV_SYS_REG_DBGBVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 4) }, 470 { HV_SYS_REG_DBGBCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 5) }, 471 { HV_SYS_REG_DBGWVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 6) }, 472 { HV_SYS_REG_DBGWCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 7) }, 473 474 { HV_SYS_REG_DBGBVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 4) }, 475 { HV_SYS_REG_DBGBCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 5) }, 476 { HV_SYS_REG_DBGWVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 6) }, 477 { HV_SYS_REG_DBGWCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 7) }, 478 479 #ifdef SYNC_NO_RAW_REGS 480 /* 481 * The registers below are manually synced on init because they are 482 * marked as NO_RAW. We still list them to make number space sync easier. 483 */ 484 { HV_SYS_REG_MDCCINT_EL1, HVF_SYSREG(0, 2, 2, 0, 0) }, 485 { HV_SYS_REG_MIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 0) }, 486 { HV_SYS_REG_MPIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 5) }, 487 { HV_SYS_REG_ID_AA64PFR0_EL1, HVF_SYSREG(0, 4, 3, 0, 0) }, 488 #endif 489 { HV_SYS_REG_ID_AA64PFR1_EL1, HVF_SYSREG(0, 4, 3, 0, 2) }, 490 { HV_SYS_REG_ID_AA64DFR0_EL1, HVF_SYSREG(0, 5, 3, 0, 0) }, 491 { HV_SYS_REG_ID_AA64DFR1_EL1, HVF_SYSREG(0, 5, 3, 0, 1) }, 492 { HV_SYS_REG_ID_AA64ISAR0_EL1, HVF_SYSREG(0, 6, 3, 0, 0) }, 493 { HV_SYS_REG_ID_AA64ISAR1_EL1, HVF_SYSREG(0, 6, 3, 0, 1) }, 494 #ifdef SYNC_NO_MMFR0 495 /* We keep the hardware MMFR0 around. HW limits are there anyway */ 496 { HV_SYS_REG_ID_AA64MMFR0_EL1, HVF_SYSREG(0, 7, 3, 0, 0) }, 497 #endif 498 { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) }, 499 { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) }, 500 501 { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) }, 502 { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) }, 503 { HV_SYS_REG_CPACR_EL1, HVF_SYSREG(1, 0, 3, 0, 2) }, 504 { HV_SYS_REG_TTBR0_EL1, HVF_SYSREG(2, 0, 3, 0, 0) }, 505 { HV_SYS_REG_TTBR1_EL1, HVF_SYSREG(2, 0, 3, 0, 1) }, 506 { HV_SYS_REG_TCR_EL1, HVF_SYSREG(2, 0, 3, 0, 2) }, 507 508 { HV_SYS_REG_APIAKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 0) }, 509 { HV_SYS_REG_APIAKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 1) }, 510 { HV_SYS_REG_APIBKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 2) }, 511 { HV_SYS_REG_APIBKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 3) }, 512 { HV_SYS_REG_APDAKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 0) }, 513 { HV_SYS_REG_APDAKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 1) }, 514 { HV_SYS_REG_APDBKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 2) }, 515 { HV_SYS_REG_APDBKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 3) }, 516 { HV_SYS_REG_APGAKEYLO_EL1, HVF_SYSREG(2, 3, 3, 0, 0) }, 517 { HV_SYS_REG_APGAKEYHI_EL1, HVF_SYSREG(2, 3, 3, 0, 1) }, 518 519 { HV_SYS_REG_SPSR_EL1, HVF_SYSREG(4, 0, 3, 0, 0) }, 520 { HV_SYS_REG_ELR_EL1, HVF_SYSREG(4, 0, 3, 0, 1) }, 521 { HV_SYS_REG_SP_EL0, HVF_SYSREG(4, 1, 3, 0, 0) }, 522 { HV_SYS_REG_AFSR0_EL1, HVF_SYSREG(5, 1, 3, 0, 0) }, 523 { HV_SYS_REG_AFSR1_EL1, HVF_SYSREG(5, 1, 3, 0, 1) }, 524 { HV_SYS_REG_ESR_EL1, HVF_SYSREG(5, 2, 3, 0, 0) }, 525 { HV_SYS_REG_FAR_EL1, HVF_SYSREG(6, 0, 3, 0, 0) }, 526 { HV_SYS_REG_PAR_EL1, HVF_SYSREG(7, 4, 3, 0, 0) }, 527 { HV_SYS_REG_MAIR_EL1, HVF_SYSREG(10, 2, 3, 0, 0) }, 528 { HV_SYS_REG_AMAIR_EL1, HVF_SYSREG(10, 3, 3, 0, 0) }, 529 { HV_SYS_REG_VBAR_EL1, HVF_SYSREG(12, 0, 3, 0, 0) }, 530 { HV_SYS_REG_CONTEXTIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 1) }, 531 { HV_SYS_REG_TPIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 4) }, 532 { HV_SYS_REG_CNTKCTL_EL1, HVF_SYSREG(14, 1, 3, 0, 0) }, 533 { HV_SYS_REG_CSSELR_EL1, HVF_SYSREG(0, 0, 3, 2, 0) }, 534 { HV_SYS_REG_TPIDR_EL0, HVF_SYSREG(13, 0, 3, 3, 2) }, 535 { HV_SYS_REG_TPIDRRO_EL0, HVF_SYSREG(13, 0, 3, 3, 3) }, 536 { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) }, 537 { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) }, 538 { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) }, 539 }; 540 541 int hvf_get_registers(CPUState *cpu) 542 { 543 ARMCPU *arm_cpu = ARM_CPU(cpu); 544 CPUARMState *env = &arm_cpu->env; 545 hv_return_t ret; 546 uint64_t val; 547 hv_simd_fp_uchar16_t fpval; 548 int i; 549 550 for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) { 551 ret = hv_vcpu_get_reg(cpu->accel->fd, hvf_reg_match[i].reg, &val); 552 *(uint64_t *)((void *)env + hvf_reg_match[i].offset) = val; 553 assert_hvf_ok(ret); 554 } 555 556 for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { 557 ret = hv_vcpu_get_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i].reg, 558 &fpval); 559 memcpy((void *)env + hvf_fpreg_match[i].offset, &fpval, sizeof(fpval)); 560 assert_hvf_ok(ret); 561 } 562 563 val = 0; 564 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPCR, &val); 565 assert_hvf_ok(ret); 566 vfp_set_fpcr(env, val); 567 568 val = 0; 569 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPSR, &val); 570 assert_hvf_ok(ret); 571 vfp_set_fpsr(env, val); 572 573 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_CPSR, &val); 574 assert_hvf_ok(ret); 575 pstate_write(env, val); 576 577 for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { 578 if (hvf_sreg_match[i].cp_idx == -1) { 579 continue; 580 } 581 582 if (cpu->accel->guest_debug_enabled) { 583 /* Handle debug registers */ 584 switch (hvf_sreg_match[i].reg) { 585 case HV_SYS_REG_DBGBVR0_EL1: 586 case HV_SYS_REG_DBGBCR0_EL1: 587 case HV_SYS_REG_DBGWVR0_EL1: 588 case HV_SYS_REG_DBGWCR0_EL1: 589 case HV_SYS_REG_DBGBVR1_EL1: 590 case HV_SYS_REG_DBGBCR1_EL1: 591 case HV_SYS_REG_DBGWVR1_EL1: 592 case HV_SYS_REG_DBGWCR1_EL1: 593 case HV_SYS_REG_DBGBVR2_EL1: 594 case HV_SYS_REG_DBGBCR2_EL1: 595 case HV_SYS_REG_DBGWVR2_EL1: 596 case HV_SYS_REG_DBGWCR2_EL1: 597 case HV_SYS_REG_DBGBVR3_EL1: 598 case HV_SYS_REG_DBGBCR3_EL1: 599 case HV_SYS_REG_DBGWVR3_EL1: 600 case HV_SYS_REG_DBGWCR3_EL1: 601 case HV_SYS_REG_DBGBVR4_EL1: 602 case HV_SYS_REG_DBGBCR4_EL1: 603 case HV_SYS_REG_DBGWVR4_EL1: 604 case HV_SYS_REG_DBGWCR4_EL1: 605 case HV_SYS_REG_DBGBVR5_EL1: 606 case HV_SYS_REG_DBGBCR5_EL1: 607 case HV_SYS_REG_DBGWVR5_EL1: 608 case HV_SYS_REG_DBGWCR5_EL1: 609 case HV_SYS_REG_DBGBVR6_EL1: 610 case HV_SYS_REG_DBGBCR6_EL1: 611 case HV_SYS_REG_DBGWVR6_EL1: 612 case HV_SYS_REG_DBGWCR6_EL1: 613 case HV_SYS_REG_DBGBVR7_EL1: 614 case HV_SYS_REG_DBGBCR7_EL1: 615 case HV_SYS_REG_DBGWVR7_EL1: 616 case HV_SYS_REG_DBGWCR7_EL1: 617 case HV_SYS_REG_DBGBVR8_EL1: 618 case HV_SYS_REG_DBGBCR8_EL1: 619 case HV_SYS_REG_DBGWVR8_EL1: 620 case HV_SYS_REG_DBGWCR8_EL1: 621 case HV_SYS_REG_DBGBVR9_EL1: 622 case HV_SYS_REG_DBGBCR9_EL1: 623 case HV_SYS_REG_DBGWVR9_EL1: 624 case HV_SYS_REG_DBGWCR9_EL1: 625 case HV_SYS_REG_DBGBVR10_EL1: 626 case HV_SYS_REG_DBGBCR10_EL1: 627 case HV_SYS_REG_DBGWVR10_EL1: 628 case HV_SYS_REG_DBGWCR10_EL1: 629 case HV_SYS_REG_DBGBVR11_EL1: 630 case HV_SYS_REG_DBGBCR11_EL1: 631 case HV_SYS_REG_DBGWVR11_EL1: 632 case HV_SYS_REG_DBGWCR11_EL1: 633 case HV_SYS_REG_DBGBVR12_EL1: 634 case HV_SYS_REG_DBGBCR12_EL1: 635 case HV_SYS_REG_DBGWVR12_EL1: 636 case HV_SYS_REG_DBGWCR12_EL1: 637 case HV_SYS_REG_DBGBVR13_EL1: 638 case HV_SYS_REG_DBGBCR13_EL1: 639 case HV_SYS_REG_DBGWVR13_EL1: 640 case HV_SYS_REG_DBGWCR13_EL1: 641 case HV_SYS_REG_DBGBVR14_EL1: 642 case HV_SYS_REG_DBGBCR14_EL1: 643 case HV_SYS_REG_DBGWVR14_EL1: 644 case HV_SYS_REG_DBGWCR14_EL1: 645 case HV_SYS_REG_DBGBVR15_EL1: 646 case HV_SYS_REG_DBGBCR15_EL1: 647 case HV_SYS_REG_DBGWVR15_EL1: 648 case HV_SYS_REG_DBGWCR15_EL1: { 649 /* 650 * If the guest is being debugged, the vCPU's debug registers 651 * are holding the gdbstub's view of the registers (set in 652 * hvf_arch_update_guest_debug()). 653 * Since the environment is used to store only the guest's view 654 * of the registers, don't update it with the values from the 655 * vCPU but simply keep the values from the previous 656 * environment. 657 */ 658 const ARMCPRegInfo *ri; 659 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_sreg_match[i].key); 660 val = read_raw_cp_reg(env, ri); 661 662 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val; 663 continue; 664 } 665 } 666 } 667 668 ret = hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, &val); 669 assert_hvf_ok(ret); 670 671 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val; 672 } 673 assert(write_list_to_cpustate(arm_cpu)); 674 675 aarch64_restore_sp(env, arm_current_el(env)); 676 677 return 0; 678 } 679 680 int hvf_put_registers(CPUState *cpu) 681 { 682 ARMCPU *arm_cpu = ARM_CPU(cpu); 683 CPUARMState *env = &arm_cpu->env; 684 hv_return_t ret; 685 uint64_t val; 686 hv_simd_fp_uchar16_t fpval; 687 int i; 688 689 for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) { 690 val = *(uint64_t *)((void *)env + hvf_reg_match[i].offset); 691 ret = hv_vcpu_set_reg(cpu->accel->fd, hvf_reg_match[i].reg, val); 692 assert_hvf_ok(ret); 693 } 694 695 for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { 696 memcpy(&fpval, (void *)env + hvf_fpreg_match[i].offset, sizeof(fpval)); 697 ret = hv_vcpu_set_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i].reg, 698 fpval); 699 assert_hvf_ok(ret); 700 } 701 702 ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPCR, vfp_get_fpcr(env)); 703 assert_hvf_ok(ret); 704 705 ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPSR, vfp_get_fpsr(env)); 706 assert_hvf_ok(ret); 707 708 ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_CPSR, pstate_read(env)); 709 assert_hvf_ok(ret); 710 711 aarch64_save_sp(env, arm_current_el(env)); 712 713 assert(write_cpustate_to_list(arm_cpu, false)); 714 for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) { 715 if (hvf_sreg_match[i].cp_idx == -1) { 716 continue; 717 } 718 719 if (cpu->accel->guest_debug_enabled) { 720 /* Handle debug registers */ 721 switch (hvf_sreg_match[i].reg) { 722 case HV_SYS_REG_DBGBVR0_EL1: 723 case HV_SYS_REG_DBGBCR0_EL1: 724 case HV_SYS_REG_DBGWVR0_EL1: 725 case HV_SYS_REG_DBGWCR0_EL1: 726 case HV_SYS_REG_DBGBVR1_EL1: 727 case HV_SYS_REG_DBGBCR1_EL1: 728 case HV_SYS_REG_DBGWVR1_EL1: 729 case HV_SYS_REG_DBGWCR1_EL1: 730 case HV_SYS_REG_DBGBVR2_EL1: 731 case HV_SYS_REG_DBGBCR2_EL1: 732 case HV_SYS_REG_DBGWVR2_EL1: 733 case HV_SYS_REG_DBGWCR2_EL1: 734 case HV_SYS_REG_DBGBVR3_EL1: 735 case HV_SYS_REG_DBGBCR3_EL1: 736 case HV_SYS_REG_DBGWVR3_EL1: 737 case HV_SYS_REG_DBGWCR3_EL1: 738 case HV_SYS_REG_DBGBVR4_EL1: 739 case HV_SYS_REG_DBGBCR4_EL1: 740 case HV_SYS_REG_DBGWVR4_EL1: 741 case HV_SYS_REG_DBGWCR4_EL1: 742 case HV_SYS_REG_DBGBVR5_EL1: 743 case HV_SYS_REG_DBGBCR5_EL1: 744 case HV_SYS_REG_DBGWVR5_EL1: 745 case HV_SYS_REG_DBGWCR5_EL1: 746 case HV_SYS_REG_DBGBVR6_EL1: 747 case HV_SYS_REG_DBGBCR6_EL1: 748 case HV_SYS_REG_DBGWVR6_EL1: 749 case HV_SYS_REG_DBGWCR6_EL1: 750 case HV_SYS_REG_DBGBVR7_EL1: 751 case HV_SYS_REG_DBGBCR7_EL1: 752 case HV_SYS_REG_DBGWVR7_EL1: 753 case HV_SYS_REG_DBGWCR7_EL1: 754 case HV_SYS_REG_DBGBVR8_EL1: 755 case HV_SYS_REG_DBGBCR8_EL1: 756 case HV_SYS_REG_DBGWVR8_EL1: 757 case HV_SYS_REG_DBGWCR8_EL1: 758 case HV_SYS_REG_DBGBVR9_EL1: 759 case HV_SYS_REG_DBGBCR9_EL1: 760 case HV_SYS_REG_DBGWVR9_EL1: 761 case HV_SYS_REG_DBGWCR9_EL1: 762 case HV_SYS_REG_DBGBVR10_EL1: 763 case HV_SYS_REG_DBGBCR10_EL1: 764 case HV_SYS_REG_DBGWVR10_EL1: 765 case HV_SYS_REG_DBGWCR10_EL1: 766 case HV_SYS_REG_DBGBVR11_EL1: 767 case HV_SYS_REG_DBGBCR11_EL1: 768 case HV_SYS_REG_DBGWVR11_EL1: 769 case HV_SYS_REG_DBGWCR11_EL1: 770 case HV_SYS_REG_DBGBVR12_EL1: 771 case HV_SYS_REG_DBGBCR12_EL1: 772 case HV_SYS_REG_DBGWVR12_EL1: 773 case HV_SYS_REG_DBGWCR12_EL1: 774 case HV_SYS_REG_DBGBVR13_EL1: 775 case HV_SYS_REG_DBGBCR13_EL1: 776 case HV_SYS_REG_DBGWVR13_EL1: 777 case HV_SYS_REG_DBGWCR13_EL1: 778 case HV_SYS_REG_DBGBVR14_EL1: 779 case HV_SYS_REG_DBGBCR14_EL1: 780 case HV_SYS_REG_DBGWVR14_EL1: 781 case HV_SYS_REG_DBGWCR14_EL1: 782 case HV_SYS_REG_DBGBVR15_EL1: 783 case HV_SYS_REG_DBGBCR15_EL1: 784 case HV_SYS_REG_DBGWVR15_EL1: 785 case HV_SYS_REG_DBGWCR15_EL1: 786 /* 787 * If the guest is being debugged, the vCPU's debug registers 788 * are already holding the gdbstub's view of the registers (set 789 * in hvf_arch_update_guest_debug()). 790 */ 791 continue; 792 } 793 } 794 795 val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx]; 796 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, val); 797 assert_hvf_ok(ret); 798 } 799 800 ret = hv_vcpu_set_vtimer_offset(cpu->accel->fd, hvf_state->vtimer_offset); 801 assert_hvf_ok(ret); 802 803 return 0; 804 } 805 806 static void flush_cpu_state(CPUState *cpu) 807 { 808 if (cpu->vcpu_dirty) { 809 hvf_put_registers(cpu); 810 cpu->vcpu_dirty = false; 811 } 812 } 813 814 static void hvf_set_reg(CPUState *cpu, int rt, uint64_t val) 815 { 816 hv_return_t r; 817 818 flush_cpu_state(cpu); 819 820 if (rt < 31) { 821 r = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_X0 + rt, val); 822 assert_hvf_ok(r); 823 } 824 } 825 826 static uint64_t hvf_get_reg(CPUState *cpu, int rt) 827 { 828 uint64_t val = 0; 829 hv_return_t r; 830 831 flush_cpu_state(cpu); 832 833 if (rt < 31) { 834 r = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_X0 + rt, &val); 835 assert_hvf_ok(r); 836 } 837 838 return val; 839 } 840 841 static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) 842 { 843 ARMISARegisters host_isar = {}; 844 const struct isar_regs { 845 int reg; 846 uint64_t *val; 847 } regs[] = { 848 { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 }, 849 { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 }, 850 { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, 851 { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, 852 { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 }, 853 { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 }, 854 /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ 855 { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, 856 { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, 857 { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 }, 858 }; 859 hv_vcpu_t fd; 860 hv_return_t r = HV_SUCCESS; 861 hv_vcpu_exit_t *exit; 862 int i; 863 864 ahcf->dtb_compatible = "arm,arm-v8"; 865 ahcf->features = (1ULL << ARM_FEATURE_V8) | 866 (1ULL << ARM_FEATURE_NEON) | 867 (1ULL << ARM_FEATURE_AARCH64) | 868 (1ULL << ARM_FEATURE_PMU) | 869 (1ULL << ARM_FEATURE_GENERIC_TIMER); 870 871 /* We set up a small vcpu to extract host registers */ 872 873 if (hv_vcpu_create(&fd, &exit, NULL) != HV_SUCCESS) { 874 return false; 875 } 876 877 for (i = 0; i < ARRAY_SIZE(regs); i++) { 878 r |= hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val); 879 } 880 r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr); 881 r |= hv_vcpu_destroy(fd); 882 883 ahcf->isar = host_isar; 884 885 /* 886 * A scratch vCPU returns SCTLR 0, so let's fill our default with the M1 887 * boot SCTLR from https://github.com/AsahiLinux/m1n1/issues/97 888 */ 889 ahcf->reset_sctlr = 0x30100180; 890 /* 891 * SPAN is disabled by default when SCTLR.SPAN=1. To improve compatibility, 892 * let's disable it on boot and then allow guest software to turn it on by 893 * setting it to 0. 894 */ 895 ahcf->reset_sctlr |= 0x00800000; 896 897 /* Make sure we don't advertise AArch32 support for EL0/EL1 */ 898 if ((host_isar.id_aa64pfr0 & 0xff) != 0x11) { 899 return false; 900 } 901 902 return r == HV_SUCCESS; 903 } 904 905 void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) 906 { 907 if (!arm_host_cpu_features.dtb_compatible) { 908 if (!hvf_enabled() || 909 !hvf_arm_get_host_cpu_features(&arm_host_cpu_features)) { 910 /* 911 * We can't report this error yet, so flag that we need to 912 * in arm_cpu_realizefn(). 913 */ 914 cpu->host_cpu_probe_failed = true; 915 return; 916 } 917 } 918 919 cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; 920 cpu->isar = arm_host_cpu_features.isar; 921 cpu->env.features = arm_host_cpu_features.features; 922 cpu->midr = arm_host_cpu_features.midr; 923 cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr; 924 } 925 926 void hvf_arch_vcpu_destroy(CPUState *cpu) 927 { 928 } 929 930 int hvf_arch_init_vcpu(CPUState *cpu) 931 { 932 ARMCPU *arm_cpu = ARM_CPU(cpu); 933 CPUARMState *env = &arm_cpu->env; 934 uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_match); 935 uint32_t sregs_cnt = 0; 936 uint64_t pfr; 937 hv_return_t ret; 938 int i; 939 940 env->aarch64 = true; 941 asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz)); 942 943 /* Allocate enough space for our sysreg sync */ 944 arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes, 945 sregs_match_len); 946 arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values, 947 sregs_match_len); 948 arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t, 949 arm_cpu->cpreg_vmstate_indexes, 950 sregs_match_len); 951 arm_cpu->cpreg_vmstate_values = g_renew(uint64_t, 952 arm_cpu->cpreg_vmstate_values, 953 sregs_match_len); 954 955 memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t)); 956 957 /* Populate cp list for all known sysregs */ 958 for (i = 0; i < sregs_match_len; i++) { 959 const ARMCPRegInfo *ri; 960 uint32_t key = hvf_sreg_match[i].key; 961 962 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key); 963 if (ri) { 964 assert(!(ri->type & ARM_CP_NO_RAW)); 965 hvf_sreg_match[i].cp_idx = sregs_cnt; 966 arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key); 967 } else { 968 hvf_sreg_match[i].cp_idx = -1; 969 } 970 } 971 arm_cpu->cpreg_array_len = sregs_cnt; 972 arm_cpu->cpreg_vmstate_array_len = sregs_cnt; 973 974 assert(write_cpustate_to_list(arm_cpu, false)); 975 976 /* Set CP_NO_RAW system registers on init */ 977 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MIDR_EL1, 978 arm_cpu->midr); 979 assert_hvf_ok(ret); 980 981 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MPIDR_EL1, 982 arm_cpu->mp_affinity); 983 assert_hvf_ok(ret); 984 985 ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr); 986 assert_hvf_ok(ret); 987 pfr |= env->gicv3state ? (1 << 24) : 0; 988 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr); 989 assert_hvf_ok(ret); 990 991 /* We're limited to underlying hardware caps, override internal versions */ 992 ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL1, 993 &arm_cpu->isar.id_aa64mmfr0); 994 assert_hvf_ok(ret); 995 996 return 0; 997 } 998 999 void hvf_kick_vcpu_thread(CPUState *cpu) 1000 { 1001 cpus_kick_thread(cpu); 1002 hv_vcpus_exit(&cpu->accel->fd, 1); 1003 } 1004 1005 static void hvf_raise_exception(CPUState *cpu, uint32_t excp, 1006 uint32_t syndrome) 1007 { 1008 ARMCPU *arm_cpu = ARM_CPU(cpu); 1009 CPUARMState *env = &arm_cpu->env; 1010 1011 cpu->exception_index = excp; 1012 env->exception.target_el = 1; 1013 env->exception.syndrome = syndrome; 1014 1015 arm_cpu_do_interrupt(cpu); 1016 } 1017 1018 static void hvf_psci_cpu_off(ARMCPU *arm_cpu) 1019 { 1020 int32_t ret = arm_set_cpu_off(arm_cpu_mp_affinity(arm_cpu)); 1021 assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS); 1022 } 1023 1024 /* 1025 * Handle a PSCI call. 1026 * 1027 * Returns 0 on success 1028 * -1 when the PSCI call is unknown, 1029 */ 1030 static bool hvf_handle_psci_call(CPUState *cpu) 1031 { 1032 ARMCPU *arm_cpu = ARM_CPU(cpu); 1033 CPUARMState *env = &arm_cpu->env; 1034 uint64_t param[4] = { 1035 env->xregs[0], 1036 env->xregs[1], 1037 env->xregs[2], 1038 env->xregs[3] 1039 }; 1040 uint64_t context_id, mpidr; 1041 bool target_aarch64 = true; 1042 CPUState *target_cpu_state; 1043 ARMCPU *target_cpu; 1044 target_ulong entry; 1045 int target_el = 1; 1046 int32_t ret = 0; 1047 1048 trace_hvf_psci_call(param[0], param[1], param[2], param[3], 1049 arm_cpu_mp_affinity(arm_cpu)); 1050 1051 switch (param[0]) { 1052 case QEMU_PSCI_0_2_FN_PSCI_VERSION: 1053 ret = QEMU_PSCI_VERSION_1_1; 1054 break; 1055 case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: 1056 ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */ 1057 break; 1058 case QEMU_PSCI_0_2_FN_AFFINITY_INFO: 1059 case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: 1060 mpidr = param[1]; 1061 1062 switch (param[2]) { 1063 case 0: 1064 target_cpu_state = arm_get_cpu_by_id(mpidr); 1065 if (!target_cpu_state) { 1066 ret = QEMU_PSCI_RET_INVALID_PARAMS; 1067 break; 1068 } 1069 target_cpu = ARM_CPU(target_cpu_state); 1070 1071 ret = target_cpu->power_state; 1072 break; 1073 default: 1074 /* Everything above affinity level 0 is always on. */ 1075 ret = 0; 1076 } 1077 break; 1078 case QEMU_PSCI_0_2_FN_SYSTEM_RESET: 1079 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 1080 /* 1081 * QEMU reset and shutdown are async requests, but PSCI 1082 * mandates that we never return from the reset/shutdown 1083 * call, so power the CPU off now so it doesn't execute 1084 * anything further. 1085 */ 1086 hvf_psci_cpu_off(arm_cpu); 1087 break; 1088 case QEMU_PSCI_0_2_FN_SYSTEM_OFF: 1089 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 1090 hvf_psci_cpu_off(arm_cpu); 1091 break; 1092 case QEMU_PSCI_0_1_FN_CPU_ON: 1093 case QEMU_PSCI_0_2_FN_CPU_ON: 1094 case QEMU_PSCI_0_2_FN64_CPU_ON: 1095 mpidr = param[1]; 1096 entry = param[2]; 1097 context_id = param[3]; 1098 ret = arm_set_cpu_on(mpidr, entry, context_id, 1099 target_el, target_aarch64); 1100 break; 1101 case QEMU_PSCI_0_1_FN_CPU_OFF: 1102 case QEMU_PSCI_0_2_FN_CPU_OFF: 1103 hvf_psci_cpu_off(arm_cpu); 1104 break; 1105 case QEMU_PSCI_0_1_FN_CPU_SUSPEND: 1106 case QEMU_PSCI_0_2_FN_CPU_SUSPEND: 1107 case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: 1108 /* Affinity levels are not supported in QEMU */ 1109 if (param[1] & 0xfffe0000) { 1110 ret = QEMU_PSCI_RET_INVALID_PARAMS; 1111 break; 1112 } 1113 /* Powerdown is not supported, we always go into WFI */ 1114 env->xregs[0] = 0; 1115 hvf_wfi(cpu); 1116 break; 1117 case QEMU_PSCI_0_1_FN_MIGRATE: 1118 case QEMU_PSCI_0_2_FN_MIGRATE: 1119 ret = QEMU_PSCI_RET_NOT_SUPPORTED; 1120 break; 1121 case QEMU_PSCI_1_0_FN_PSCI_FEATURES: 1122 switch (param[1]) { 1123 case QEMU_PSCI_0_2_FN_PSCI_VERSION: 1124 case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: 1125 case QEMU_PSCI_0_2_FN_AFFINITY_INFO: 1126 case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: 1127 case QEMU_PSCI_0_2_FN_SYSTEM_RESET: 1128 case QEMU_PSCI_0_2_FN_SYSTEM_OFF: 1129 case QEMU_PSCI_0_1_FN_CPU_ON: 1130 case QEMU_PSCI_0_2_FN_CPU_ON: 1131 case QEMU_PSCI_0_2_FN64_CPU_ON: 1132 case QEMU_PSCI_0_1_FN_CPU_OFF: 1133 case QEMU_PSCI_0_2_FN_CPU_OFF: 1134 case QEMU_PSCI_0_1_FN_CPU_SUSPEND: 1135 case QEMU_PSCI_0_2_FN_CPU_SUSPEND: 1136 case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: 1137 case QEMU_PSCI_1_0_FN_PSCI_FEATURES: 1138 ret = 0; 1139 break; 1140 case QEMU_PSCI_0_1_FN_MIGRATE: 1141 case QEMU_PSCI_0_2_FN_MIGRATE: 1142 default: 1143 ret = QEMU_PSCI_RET_NOT_SUPPORTED; 1144 } 1145 break; 1146 default: 1147 return false; 1148 } 1149 1150 env->xregs[0] = ret; 1151 return true; 1152 } 1153 1154 static bool is_id_sysreg(uint32_t reg) 1155 { 1156 return SYSREG_OP0(reg) == 3 && 1157 SYSREG_OP1(reg) == 0 && 1158 SYSREG_CRN(reg) == 0 && 1159 SYSREG_CRM(reg) >= 1 && 1160 SYSREG_CRM(reg) < 8; 1161 } 1162 1163 static uint32_t hvf_reg2cp_reg(uint32_t reg) 1164 { 1165 return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, 1166 (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, 1167 (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK, 1168 (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK, 1169 (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK, 1170 (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK); 1171 } 1172 1173 static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val) 1174 { 1175 ARMCPU *arm_cpu = ARM_CPU(cpu); 1176 CPUARMState *env = &arm_cpu->env; 1177 const ARMCPRegInfo *ri; 1178 1179 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); 1180 if (ri) { 1181 if (ri->accessfn) { 1182 if (ri->accessfn(env, ri, true) != CP_ACCESS_OK) { 1183 return false; 1184 } 1185 } 1186 if (ri->type & ARM_CP_CONST) { 1187 *val = ri->resetvalue; 1188 } else if (ri->readfn) { 1189 *val = ri->readfn(env, ri); 1190 } else { 1191 *val = CPREG_FIELD64(env, ri); 1192 } 1193 trace_hvf_vgic_read(ri->name, *val); 1194 return true; 1195 } 1196 1197 return false; 1198 } 1199 1200 static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) 1201 { 1202 ARMCPU *arm_cpu = ARM_CPU(cpu); 1203 CPUARMState *env = &arm_cpu->env; 1204 uint64_t val = 0; 1205 1206 switch (reg) { 1207 case SYSREG_CNTPCT_EL0: 1208 val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 1209 gt_cntfrq_period_ns(arm_cpu); 1210 break; 1211 case SYSREG_PMCR_EL0: 1212 val = env->cp15.c9_pmcr; 1213 break; 1214 case SYSREG_PMCCNTR_EL0: 1215 pmu_op_start(env); 1216 val = env->cp15.c15_ccnt; 1217 pmu_op_finish(env); 1218 break; 1219 case SYSREG_PMCNTENCLR_EL0: 1220 val = env->cp15.c9_pmcnten; 1221 break; 1222 case SYSREG_PMOVSCLR_EL0: 1223 val = env->cp15.c9_pmovsr; 1224 break; 1225 case SYSREG_PMSELR_EL0: 1226 val = env->cp15.c9_pmselr; 1227 break; 1228 case SYSREG_PMINTENCLR_EL1: 1229 val = env->cp15.c9_pminten; 1230 break; 1231 case SYSREG_PMCCFILTR_EL0: 1232 val = env->cp15.pmccfiltr_el0; 1233 break; 1234 case SYSREG_PMCNTENSET_EL0: 1235 val = env->cp15.c9_pmcnten; 1236 break; 1237 case SYSREG_PMUSERENR_EL0: 1238 val = env->cp15.c9_pmuserenr; 1239 break; 1240 case SYSREG_PMCEID0_EL0: 1241 case SYSREG_PMCEID1_EL0: 1242 /* We can't really count anything yet, declare all events invalid */ 1243 val = 0; 1244 break; 1245 case SYSREG_OSLSR_EL1: 1246 val = env->cp15.oslsr_el1; 1247 break; 1248 case SYSREG_OSDLR_EL1: 1249 /* Dummy register */ 1250 break; 1251 case SYSREG_ICC_AP0R0_EL1: 1252 case SYSREG_ICC_AP0R1_EL1: 1253 case SYSREG_ICC_AP0R2_EL1: 1254 case SYSREG_ICC_AP0R3_EL1: 1255 case SYSREG_ICC_AP1R0_EL1: 1256 case SYSREG_ICC_AP1R1_EL1: 1257 case SYSREG_ICC_AP1R2_EL1: 1258 case SYSREG_ICC_AP1R3_EL1: 1259 case SYSREG_ICC_ASGI1R_EL1: 1260 case SYSREG_ICC_BPR0_EL1: 1261 case SYSREG_ICC_BPR1_EL1: 1262 case SYSREG_ICC_DIR_EL1: 1263 case SYSREG_ICC_EOIR0_EL1: 1264 case SYSREG_ICC_EOIR1_EL1: 1265 case SYSREG_ICC_HPPIR0_EL1: 1266 case SYSREG_ICC_HPPIR1_EL1: 1267 case SYSREG_ICC_IAR0_EL1: 1268 case SYSREG_ICC_IAR1_EL1: 1269 case SYSREG_ICC_IGRPEN0_EL1: 1270 case SYSREG_ICC_IGRPEN1_EL1: 1271 case SYSREG_ICC_PMR_EL1: 1272 case SYSREG_ICC_SGI0R_EL1: 1273 case SYSREG_ICC_SGI1R_EL1: 1274 case SYSREG_ICC_SRE_EL1: 1275 case SYSREG_ICC_CTLR_EL1: 1276 /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */ 1277 if (!hvf_sysreg_read_cp(cpu, reg, &val)) { 1278 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1279 } 1280 break; 1281 case SYSREG_DBGBVR0_EL1: 1282 case SYSREG_DBGBVR1_EL1: 1283 case SYSREG_DBGBVR2_EL1: 1284 case SYSREG_DBGBVR3_EL1: 1285 case SYSREG_DBGBVR4_EL1: 1286 case SYSREG_DBGBVR5_EL1: 1287 case SYSREG_DBGBVR6_EL1: 1288 case SYSREG_DBGBVR7_EL1: 1289 case SYSREG_DBGBVR8_EL1: 1290 case SYSREG_DBGBVR9_EL1: 1291 case SYSREG_DBGBVR10_EL1: 1292 case SYSREG_DBGBVR11_EL1: 1293 case SYSREG_DBGBVR12_EL1: 1294 case SYSREG_DBGBVR13_EL1: 1295 case SYSREG_DBGBVR14_EL1: 1296 case SYSREG_DBGBVR15_EL1: 1297 val = env->cp15.dbgbvr[SYSREG_CRM(reg)]; 1298 break; 1299 case SYSREG_DBGBCR0_EL1: 1300 case SYSREG_DBGBCR1_EL1: 1301 case SYSREG_DBGBCR2_EL1: 1302 case SYSREG_DBGBCR3_EL1: 1303 case SYSREG_DBGBCR4_EL1: 1304 case SYSREG_DBGBCR5_EL1: 1305 case SYSREG_DBGBCR6_EL1: 1306 case SYSREG_DBGBCR7_EL1: 1307 case SYSREG_DBGBCR8_EL1: 1308 case SYSREG_DBGBCR9_EL1: 1309 case SYSREG_DBGBCR10_EL1: 1310 case SYSREG_DBGBCR11_EL1: 1311 case SYSREG_DBGBCR12_EL1: 1312 case SYSREG_DBGBCR13_EL1: 1313 case SYSREG_DBGBCR14_EL1: 1314 case SYSREG_DBGBCR15_EL1: 1315 val = env->cp15.dbgbcr[SYSREG_CRM(reg)]; 1316 break; 1317 case SYSREG_DBGWVR0_EL1: 1318 case SYSREG_DBGWVR1_EL1: 1319 case SYSREG_DBGWVR2_EL1: 1320 case SYSREG_DBGWVR3_EL1: 1321 case SYSREG_DBGWVR4_EL1: 1322 case SYSREG_DBGWVR5_EL1: 1323 case SYSREG_DBGWVR6_EL1: 1324 case SYSREG_DBGWVR7_EL1: 1325 case SYSREG_DBGWVR8_EL1: 1326 case SYSREG_DBGWVR9_EL1: 1327 case SYSREG_DBGWVR10_EL1: 1328 case SYSREG_DBGWVR11_EL1: 1329 case SYSREG_DBGWVR12_EL1: 1330 case SYSREG_DBGWVR13_EL1: 1331 case SYSREG_DBGWVR14_EL1: 1332 case SYSREG_DBGWVR15_EL1: 1333 val = env->cp15.dbgwvr[SYSREG_CRM(reg)]; 1334 break; 1335 case SYSREG_DBGWCR0_EL1: 1336 case SYSREG_DBGWCR1_EL1: 1337 case SYSREG_DBGWCR2_EL1: 1338 case SYSREG_DBGWCR3_EL1: 1339 case SYSREG_DBGWCR4_EL1: 1340 case SYSREG_DBGWCR5_EL1: 1341 case SYSREG_DBGWCR6_EL1: 1342 case SYSREG_DBGWCR7_EL1: 1343 case SYSREG_DBGWCR8_EL1: 1344 case SYSREG_DBGWCR9_EL1: 1345 case SYSREG_DBGWCR10_EL1: 1346 case SYSREG_DBGWCR11_EL1: 1347 case SYSREG_DBGWCR12_EL1: 1348 case SYSREG_DBGWCR13_EL1: 1349 case SYSREG_DBGWCR14_EL1: 1350 case SYSREG_DBGWCR15_EL1: 1351 val = env->cp15.dbgwcr[SYSREG_CRM(reg)]; 1352 break; 1353 default: 1354 if (is_id_sysreg(reg)) { 1355 /* ID system registers read as RES0 */ 1356 val = 0; 1357 break; 1358 } 1359 cpu_synchronize_state(cpu); 1360 trace_hvf_unhandled_sysreg_read(env->pc, reg, 1361 SYSREG_OP0(reg), 1362 SYSREG_OP1(reg), 1363 SYSREG_CRN(reg), 1364 SYSREG_CRM(reg), 1365 SYSREG_OP2(reg)); 1366 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1367 return 1; 1368 } 1369 1370 trace_hvf_sysreg_read(reg, 1371 SYSREG_OP0(reg), 1372 SYSREG_OP1(reg), 1373 SYSREG_CRN(reg), 1374 SYSREG_CRM(reg), 1375 SYSREG_OP2(reg), 1376 val); 1377 hvf_set_reg(cpu, rt, val); 1378 1379 return 0; 1380 } 1381 1382 static void pmu_update_irq(CPUARMState *env) 1383 { 1384 ARMCPU *cpu = env_archcpu(env); 1385 qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && 1386 (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); 1387 } 1388 1389 static bool pmu_event_supported(uint16_t number) 1390 { 1391 return false; 1392 } 1393 1394 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using 1395 * the current EL, security state, and register configuration. 1396 */ 1397 static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) 1398 { 1399 uint64_t filter; 1400 bool enabled, filtered = true; 1401 int el = arm_current_el(env); 1402 1403 enabled = (env->cp15.c9_pmcr & PMCRE) && 1404 (env->cp15.c9_pmcnten & (1 << counter)); 1405 1406 if (counter == 31) { 1407 filter = env->cp15.pmccfiltr_el0; 1408 } else { 1409 filter = env->cp15.c14_pmevtyper[counter]; 1410 } 1411 1412 if (el == 0) { 1413 filtered = filter & PMXEVTYPER_U; 1414 } else if (el == 1) { 1415 filtered = filter & PMXEVTYPER_P; 1416 } 1417 1418 if (counter != 31) { 1419 /* 1420 * If not checking PMCCNTR, ensure the counter is setup to an event we 1421 * support 1422 */ 1423 uint16_t event = filter & PMXEVTYPER_EVTCOUNT; 1424 if (!pmu_event_supported(event)) { 1425 return false; 1426 } 1427 } 1428 1429 return enabled && !filtered; 1430 } 1431 1432 static void pmswinc_write(CPUARMState *env, uint64_t value) 1433 { 1434 unsigned int i; 1435 for (i = 0; i < pmu_num_counters(env); i++) { 1436 /* Increment a counter's count iff: */ 1437 if ((value & (1 << i)) && /* counter's bit is set */ 1438 /* counter is enabled and not filtered */ 1439 pmu_counter_enabled(env, i) && 1440 /* counter is SW_INCR */ 1441 (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { 1442 /* 1443 * Detect if this write causes an overflow since we can't predict 1444 * PMSWINC overflows like we can for other events 1445 */ 1446 uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; 1447 1448 if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { 1449 env->cp15.c9_pmovsr |= (1 << i); 1450 pmu_update_irq(env); 1451 } 1452 1453 env->cp15.c14_pmevcntr[i] = new_pmswinc; 1454 } 1455 } 1456 } 1457 1458 static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val) 1459 { 1460 ARMCPU *arm_cpu = ARM_CPU(cpu); 1461 CPUARMState *env = &arm_cpu->env; 1462 const ARMCPRegInfo *ri; 1463 1464 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); 1465 1466 if (ri) { 1467 if (ri->accessfn) { 1468 if (ri->accessfn(env, ri, false) != CP_ACCESS_OK) { 1469 return false; 1470 } 1471 } 1472 if (ri->writefn) { 1473 ri->writefn(env, ri, val); 1474 } else { 1475 CPREG_FIELD64(env, ri) = val; 1476 } 1477 1478 trace_hvf_vgic_write(ri->name, val); 1479 return true; 1480 } 1481 1482 return false; 1483 } 1484 1485 static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) 1486 { 1487 ARMCPU *arm_cpu = ARM_CPU(cpu); 1488 CPUARMState *env = &arm_cpu->env; 1489 1490 trace_hvf_sysreg_write(reg, 1491 SYSREG_OP0(reg), 1492 SYSREG_OP1(reg), 1493 SYSREG_CRN(reg), 1494 SYSREG_CRM(reg), 1495 SYSREG_OP2(reg), 1496 val); 1497 1498 switch (reg) { 1499 case SYSREG_PMCCNTR_EL0: 1500 pmu_op_start(env); 1501 env->cp15.c15_ccnt = val; 1502 pmu_op_finish(env); 1503 break; 1504 case SYSREG_PMCR_EL0: 1505 pmu_op_start(env); 1506 1507 if (val & PMCRC) { 1508 /* The counter has been reset */ 1509 env->cp15.c15_ccnt = 0; 1510 } 1511 1512 if (val & PMCRP) { 1513 unsigned int i; 1514 for (i = 0; i < pmu_num_counters(env); i++) { 1515 env->cp15.c14_pmevcntr[i] = 0; 1516 } 1517 } 1518 1519 env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; 1520 env->cp15.c9_pmcr |= (val & PMCR_WRITABLE_MASK); 1521 1522 pmu_op_finish(env); 1523 break; 1524 case SYSREG_PMUSERENR_EL0: 1525 env->cp15.c9_pmuserenr = val & 0xf; 1526 break; 1527 case SYSREG_PMCNTENSET_EL0: 1528 env->cp15.c9_pmcnten |= (val & pmu_counter_mask(env)); 1529 break; 1530 case SYSREG_PMCNTENCLR_EL0: 1531 env->cp15.c9_pmcnten &= ~(val & pmu_counter_mask(env)); 1532 break; 1533 case SYSREG_PMINTENCLR_EL1: 1534 pmu_op_start(env); 1535 env->cp15.c9_pminten |= val; 1536 pmu_op_finish(env); 1537 break; 1538 case SYSREG_PMOVSCLR_EL0: 1539 pmu_op_start(env); 1540 env->cp15.c9_pmovsr &= ~val; 1541 pmu_op_finish(env); 1542 break; 1543 case SYSREG_PMSWINC_EL0: 1544 pmu_op_start(env); 1545 pmswinc_write(env, val); 1546 pmu_op_finish(env); 1547 break; 1548 case SYSREG_PMSELR_EL0: 1549 env->cp15.c9_pmselr = val & 0x1f; 1550 break; 1551 case SYSREG_PMCCFILTR_EL0: 1552 pmu_op_start(env); 1553 env->cp15.pmccfiltr_el0 = val & PMCCFILTR_EL0; 1554 pmu_op_finish(env); 1555 break; 1556 case SYSREG_OSLAR_EL1: 1557 env->cp15.oslsr_el1 = val & 1; 1558 break; 1559 case SYSREG_OSDLR_EL1: 1560 /* Dummy register */ 1561 break; 1562 case SYSREG_ICC_AP0R0_EL1: 1563 case SYSREG_ICC_AP0R1_EL1: 1564 case SYSREG_ICC_AP0R2_EL1: 1565 case SYSREG_ICC_AP0R3_EL1: 1566 case SYSREG_ICC_AP1R0_EL1: 1567 case SYSREG_ICC_AP1R1_EL1: 1568 case SYSREG_ICC_AP1R2_EL1: 1569 case SYSREG_ICC_AP1R3_EL1: 1570 case SYSREG_ICC_ASGI1R_EL1: 1571 case SYSREG_ICC_BPR0_EL1: 1572 case SYSREG_ICC_BPR1_EL1: 1573 case SYSREG_ICC_CTLR_EL1: 1574 case SYSREG_ICC_DIR_EL1: 1575 case SYSREG_ICC_EOIR0_EL1: 1576 case SYSREG_ICC_EOIR1_EL1: 1577 case SYSREG_ICC_HPPIR0_EL1: 1578 case SYSREG_ICC_HPPIR1_EL1: 1579 case SYSREG_ICC_IAR0_EL1: 1580 case SYSREG_ICC_IAR1_EL1: 1581 case SYSREG_ICC_IGRPEN0_EL1: 1582 case SYSREG_ICC_IGRPEN1_EL1: 1583 case SYSREG_ICC_PMR_EL1: 1584 case SYSREG_ICC_SGI0R_EL1: 1585 case SYSREG_ICC_SGI1R_EL1: 1586 case SYSREG_ICC_SRE_EL1: 1587 /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */ 1588 if (!hvf_sysreg_write_cp(cpu, reg, val)) { 1589 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1590 } 1591 break; 1592 case SYSREG_MDSCR_EL1: 1593 env->cp15.mdscr_el1 = val; 1594 break; 1595 case SYSREG_DBGBVR0_EL1: 1596 case SYSREG_DBGBVR1_EL1: 1597 case SYSREG_DBGBVR2_EL1: 1598 case SYSREG_DBGBVR3_EL1: 1599 case SYSREG_DBGBVR4_EL1: 1600 case SYSREG_DBGBVR5_EL1: 1601 case SYSREG_DBGBVR6_EL1: 1602 case SYSREG_DBGBVR7_EL1: 1603 case SYSREG_DBGBVR8_EL1: 1604 case SYSREG_DBGBVR9_EL1: 1605 case SYSREG_DBGBVR10_EL1: 1606 case SYSREG_DBGBVR11_EL1: 1607 case SYSREG_DBGBVR12_EL1: 1608 case SYSREG_DBGBVR13_EL1: 1609 case SYSREG_DBGBVR14_EL1: 1610 case SYSREG_DBGBVR15_EL1: 1611 env->cp15.dbgbvr[SYSREG_CRM(reg)] = val; 1612 break; 1613 case SYSREG_DBGBCR0_EL1: 1614 case SYSREG_DBGBCR1_EL1: 1615 case SYSREG_DBGBCR2_EL1: 1616 case SYSREG_DBGBCR3_EL1: 1617 case SYSREG_DBGBCR4_EL1: 1618 case SYSREG_DBGBCR5_EL1: 1619 case SYSREG_DBGBCR6_EL1: 1620 case SYSREG_DBGBCR7_EL1: 1621 case SYSREG_DBGBCR8_EL1: 1622 case SYSREG_DBGBCR9_EL1: 1623 case SYSREG_DBGBCR10_EL1: 1624 case SYSREG_DBGBCR11_EL1: 1625 case SYSREG_DBGBCR12_EL1: 1626 case SYSREG_DBGBCR13_EL1: 1627 case SYSREG_DBGBCR14_EL1: 1628 case SYSREG_DBGBCR15_EL1: 1629 env->cp15.dbgbcr[SYSREG_CRM(reg)] = val; 1630 break; 1631 case SYSREG_DBGWVR0_EL1: 1632 case SYSREG_DBGWVR1_EL1: 1633 case SYSREG_DBGWVR2_EL1: 1634 case SYSREG_DBGWVR3_EL1: 1635 case SYSREG_DBGWVR4_EL1: 1636 case SYSREG_DBGWVR5_EL1: 1637 case SYSREG_DBGWVR6_EL1: 1638 case SYSREG_DBGWVR7_EL1: 1639 case SYSREG_DBGWVR8_EL1: 1640 case SYSREG_DBGWVR9_EL1: 1641 case SYSREG_DBGWVR10_EL1: 1642 case SYSREG_DBGWVR11_EL1: 1643 case SYSREG_DBGWVR12_EL1: 1644 case SYSREG_DBGWVR13_EL1: 1645 case SYSREG_DBGWVR14_EL1: 1646 case SYSREG_DBGWVR15_EL1: 1647 env->cp15.dbgwvr[SYSREG_CRM(reg)] = val; 1648 break; 1649 case SYSREG_DBGWCR0_EL1: 1650 case SYSREG_DBGWCR1_EL1: 1651 case SYSREG_DBGWCR2_EL1: 1652 case SYSREG_DBGWCR3_EL1: 1653 case SYSREG_DBGWCR4_EL1: 1654 case SYSREG_DBGWCR5_EL1: 1655 case SYSREG_DBGWCR6_EL1: 1656 case SYSREG_DBGWCR7_EL1: 1657 case SYSREG_DBGWCR8_EL1: 1658 case SYSREG_DBGWCR9_EL1: 1659 case SYSREG_DBGWCR10_EL1: 1660 case SYSREG_DBGWCR11_EL1: 1661 case SYSREG_DBGWCR12_EL1: 1662 case SYSREG_DBGWCR13_EL1: 1663 case SYSREG_DBGWCR14_EL1: 1664 case SYSREG_DBGWCR15_EL1: 1665 env->cp15.dbgwcr[SYSREG_CRM(reg)] = val; 1666 break; 1667 default: 1668 cpu_synchronize_state(cpu); 1669 trace_hvf_unhandled_sysreg_write(env->pc, reg, 1670 SYSREG_OP0(reg), 1671 SYSREG_OP1(reg), 1672 SYSREG_CRN(reg), 1673 SYSREG_CRM(reg), 1674 SYSREG_OP2(reg)); 1675 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1676 return 1; 1677 } 1678 1679 return 0; 1680 } 1681 1682 static int hvf_inject_interrupts(CPUState *cpu) 1683 { 1684 if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) { 1685 trace_hvf_inject_fiq(); 1686 hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_FIQ, 1687 true); 1688 } 1689 1690 if (cpu->interrupt_request & CPU_INTERRUPT_HARD) { 1691 trace_hvf_inject_irq(); 1692 hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_IRQ, 1693 true); 1694 } 1695 1696 return 0; 1697 } 1698 1699 static uint64_t hvf_vtimer_val_raw(void) 1700 { 1701 /* 1702 * mach_absolute_time() returns the vtimer value without the VM 1703 * offset that we define. Add our own offset on top. 1704 */ 1705 return mach_absolute_time() - hvf_state->vtimer_offset; 1706 } 1707 1708 static uint64_t hvf_vtimer_val(void) 1709 { 1710 if (!runstate_is_running()) { 1711 /* VM is paused, the vtimer value is in vtimer.vtimer_val */ 1712 return vtimer.vtimer_val; 1713 } 1714 1715 return hvf_vtimer_val_raw(); 1716 } 1717 1718 static void hvf_wait_for_ipi(CPUState *cpu, struct timespec *ts) 1719 { 1720 /* 1721 * Use pselect to sleep so that other threads can IPI us while we're 1722 * sleeping. 1723 */ 1724 qatomic_set_mb(&cpu->thread_kicked, false); 1725 bql_unlock(); 1726 pselect(0, 0, 0, 0, ts, &cpu->accel->unblock_ipi_mask); 1727 bql_lock(); 1728 } 1729 1730 static void hvf_wfi(CPUState *cpu) 1731 { 1732 ARMCPU *arm_cpu = ARM_CPU(cpu); 1733 struct timespec ts; 1734 hv_return_t r; 1735 uint64_t ctl; 1736 uint64_t cval; 1737 int64_t ticks_to_sleep; 1738 uint64_t seconds; 1739 uint64_t nanos; 1740 uint32_t cntfrq; 1741 1742 if (cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ)) { 1743 /* Interrupt pending, no need to wait */ 1744 return; 1745 } 1746 1747 r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); 1748 assert_hvf_ok(r); 1749 1750 if (!(ctl & 1) || (ctl & 2)) { 1751 /* Timer disabled or masked, just wait for an IPI. */ 1752 hvf_wait_for_ipi(cpu, NULL); 1753 return; 1754 } 1755 1756 r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CVAL_EL0, &cval); 1757 assert_hvf_ok(r); 1758 1759 ticks_to_sleep = cval - hvf_vtimer_val(); 1760 if (ticks_to_sleep < 0) { 1761 return; 1762 } 1763 1764 cntfrq = gt_cntfrq_period_ns(arm_cpu); 1765 seconds = muldiv64(ticks_to_sleep, cntfrq, NANOSECONDS_PER_SECOND); 1766 ticks_to_sleep -= muldiv64(seconds, NANOSECONDS_PER_SECOND, cntfrq); 1767 nanos = ticks_to_sleep * cntfrq; 1768 1769 /* 1770 * Don't sleep for less than the time a context switch would take, 1771 * so that we can satisfy fast timer requests on the same CPU. 1772 * Measurements on M1 show the sweet spot to be ~2ms. 1773 */ 1774 if (!seconds && nanos < (2 * SCALE_MS)) { 1775 return; 1776 } 1777 1778 ts = (struct timespec) { seconds, nanos }; 1779 hvf_wait_for_ipi(cpu, &ts); 1780 } 1781 1782 static void hvf_sync_vtimer(CPUState *cpu) 1783 { 1784 ARMCPU *arm_cpu = ARM_CPU(cpu); 1785 hv_return_t r; 1786 uint64_t ctl; 1787 bool irq_state; 1788 1789 if (!cpu->accel->vtimer_masked) { 1790 /* We will get notified on vtimer changes by hvf, nothing to do */ 1791 return; 1792 } 1793 1794 r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); 1795 assert_hvf_ok(r); 1796 1797 irq_state = (ctl & (TMR_CTL_ENABLE | TMR_CTL_IMASK | TMR_CTL_ISTATUS)) == 1798 (TMR_CTL_ENABLE | TMR_CTL_ISTATUS); 1799 qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], irq_state); 1800 1801 if (!irq_state) { 1802 /* Timer no longer asserting, we can unmask it */ 1803 hv_vcpu_set_vtimer_mask(cpu->accel->fd, false); 1804 cpu->accel->vtimer_masked = false; 1805 } 1806 } 1807 1808 int hvf_vcpu_exec(CPUState *cpu) 1809 { 1810 ARMCPU *arm_cpu = ARM_CPU(cpu); 1811 CPUARMState *env = &arm_cpu->env; 1812 int ret; 1813 hv_vcpu_exit_t *hvf_exit = cpu->accel->exit; 1814 hv_return_t r; 1815 bool advance_pc = false; 1816 1817 if (!(cpu->singlestep_enabled & SSTEP_NOIRQ) && 1818 hvf_inject_interrupts(cpu)) { 1819 return EXCP_INTERRUPT; 1820 } 1821 1822 if (cpu->halted) { 1823 return EXCP_HLT; 1824 } 1825 1826 flush_cpu_state(cpu); 1827 1828 bql_unlock(); 1829 assert_hvf_ok(hv_vcpu_run(cpu->accel->fd)); 1830 1831 /* handle VMEXIT */ 1832 uint64_t exit_reason = hvf_exit->reason; 1833 uint64_t syndrome = hvf_exit->exception.syndrome; 1834 uint32_t ec = syn_get_ec(syndrome); 1835 1836 ret = 0; 1837 bql_lock(); 1838 switch (exit_reason) { 1839 case HV_EXIT_REASON_EXCEPTION: 1840 /* This is the main one, handle below. */ 1841 break; 1842 case HV_EXIT_REASON_VTIMER_ACTIVATED: 1843 qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1); 1844 cpu->accel->vtimer_masked = true; 1845 return 0; 1846 case HV_EXIT_REASON_CANCELED: 1847 /* we got kicked, no exit to process */ 1848 return 0; 1849 default: 1850 g_assert_not_reached(); 1851 } 1852 1853 hvf_sync_vtimer(cpu); 1854 1855 switch (ec) { 1856 case EC_SOFTWARESTEP: { 1857 ret = EXCP_DEBUG; 1858 1859 if (!cpu->singlestep_enabled) { 1860 error_report("EC_SOFTWARESTEP but single-stepping not enabled"); 1861 } 1862 break; 1863 } 1864 case EC_AA64_BKPT: { 1865 ret = EXCP_DEBUG; 1866 1867 cpu_synchronize_state(cpu); 1868 1869 if (!hvf_find_sw_breakpoint(cpu, env->pc)) { 1870 /* Re-inject into the guest */ 1871 ret = 0; 1872 hvf_raise_exception(cpu, EXCP_BKPT, syn_aa64_bkpt(0)); 1873 } 1874 break; 1875 } 1876 case EC_BREAKPOINT: { 1877 ret = EXCP_DEBUG; 1878 1879 cpu_synchronize_state(cpu); 1880 1881 if (!find_hw_breakpoint(cpu, env->pc)) { 1882 error_report("EC_BREAKPOINT but unknown hw breakpoint"); 1883 } 1884 break; 1885 } 1886 case EC_WATCHPOINT: { 1887 ret = EXCP_DEBUG; 1888 1889 cpu_synchronize_state(cpu); 1890 1891 CPUWatchpoint *wp = 1892 find_hw_watchpoint(cpu, hvf_exit->exception.virtual_address); 1893 if (!wp) { 1894 error_report("EXCP_DEBUG but unknown hw watchpoint"); 1895 } 1896 cpu->watchpoint_hit = wp; 1897 break; 1898 } 1899 case EC_DATAABORT: { 1900 bool isv = syndrome & ARM_EL_ISV; 1901 bool iswrite = (syndrome >> 6) & 1; 1902 bool s1ptw = (syndrome >> 7) & 1; 1903 uint32_t sas = (syndrome >> 22) & 3; 1904 uint32_t len = 1 << sas; 1905 uint32_t srt = (syndrome >> 16) & 0x1f; 1906 uint32_t cm = (syndrome >> 8) & 0x1; 1907 uint64_t val = 0; 1908 1909 trace_hvf_data_abort(env->pc, hvf_exit->exception.virtual_address, 1910 hvf_exit->exception.physical_address, isv, 1911 iswrite, s1ptw, len, srt); 1912 1913 if (cm) { 1914 /* We don't cache MMIO regions */ 1915 advance_pc = true; 1916 break; 1917 } 1918 1919 assert(isv); 1920 1921 if (iswrite) { 1922 val = hvf_get_reg(cpu, srt); 1923 address_space_write(&address_space_memory, 1924 hvf_exit->exception.physical_address, 1925 MEMTXATTRS_UNSPECIFIED, &val, len); 1926 } else { 1927 address_space_read(&address_space_memory, 1928 hvf_exit->exception.physical_address, 1929 MEMTXATTRS_UNSPECIFIED, &val, len); 1930 hvf_set_reg(cpu, srt, val); 1931 } 1932 1933 advance_pc = true; 1934 break; 1935 } 1936 case EC_SYSTEMREGISTERTRAP: { 1937 bool isread = (syndrome >> 0) & 1; 1938 uint32_t rt = (syndrome >> 5) & 0x1f; 1939 uint32_t reg = syndrome & SYSREG_MASK; 1940 uint64_t val; 1941 int sysreg_ret = 0; 1942 1943 if (isread) { 1944 sysreg_ret = hvf_sysreg_read(cpu, reg, rt); 1945 } else { 1946 val = hvf_get_reg(cpu, rt); 1947 sysreg_ret = hvf_sysreg_write(cpu, reg, val); 1948 } 1949 1950 advance_pc = !sysreg_ret; 1951 break; 1952 } 1953 case EC_WFX_TRAP: 1954 advance_pc = true; 1955 if (!(syndrome & WFX_IS_WFE)) { 1956 hvf_wfi(cpu); 1957 } 1958 break; 1959 case EC_AA64_HVC: 1960 cpu_synchronize_state(cpu); 1961 if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_HVC) { 1962 if (!hvf_handle_psci_call(cpu)) { 1963 trace_hvf_unknown_hvc(env->xregs[0]); 1964 /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ 1965 env->xregs[0] = -1; 1966 } 1967 } else { 1968 trace_hvf_unknown_hvc(env->xregs[0]); 1969 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1970 } 1971 break; 1972 case EC_AA64_SMC: 1973 cpu_synchronize_state(cpu); 1974 if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_SMC) { 1975 advance_pc = true; 1976 1977 if (!hvf_handle_psci_call(cpu)) { 1978 trace_hvf_unknown_smc(env->xregs[0]); 1979 /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */ 1980 env->xregs[0] = -1; 1981 } 1982 } else { 1983 trace_hvf_unknown_smc(env->xregs[0]); 1984 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); 1985 } 1986 break; 1987 default: 1988 cpu_synchronize_state(cpu); 1989 trace_hvf_exit(syndrome, ec, env->pc); 1990 error_report("0x%llx: unhandled exception ec=0x%x", env->pc, ec); 1991 } 1992 1993 if (advance_pc) { 1994 uint64_t pc; 1995 1996 flush_cpu_state(cpu); 1997 1998 r = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_PC, &pc); 1999 assert_hvf_ok(r); 2000 pc += 4; 2001 r = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_PC, pc); 2002 assert_hvf_ok(r); 2003 2004 /* Handle single-stepping over instructions which trigger a VM exit */ 2005 if (cpu->singlestep_enabled) { 2006 ret = EXCP_DEBUG; 2007 } 2008 } 2009 2010 return ret; 2011 } 2012 2013 static const VMStateDescription vmstate_hvf_vtimer = { 2014 .name = "hvf-vtimer", 2015 .version_id = 1, 2016 .minimum_version_id = 1, 2017 .fields = (const VMStateField[]) { 2018 VMSTATE_UINT64(vtimer_val, HVFVTimer), 2019 VMSTATE_END_OF_LIST() 2020 }, 2021 }; 2022 2023 static void hvf_vm_state_change(void *opaque, bool running, RunState state) 2024 { 2025 HVFVTimer *s = opaque; 2026 2027 if (running) { 2028 /* Update vtimer offset on all CPUs */ 2029 hvf_state->vtimer_offset = mach_absolute_time() - s->vtimer_val; 2030 cpu_synchronize_all_states(); 2031 } else { 2032 /* Remember vtimer value on every pause */ 2033 s->vtimer_val = hvf_vtimer_val_raw(); 2034 } 2035 } 2036 2037 int hvf_arch_init(void) 2038 { 2039 hvf_state->vtimer_offset = mach_absolute_time(); 2040 vmstate_register(NULL, 0, &vmstate_hvf_vtimer, &vtimer); 2041 qemu_add_vm_change_state_handler(hvf_vm_state_change, &vtimer); 2042 2043 hvf_arm_init_debug(); 2044 2045 return 0; 2046 } 2047 2048 static const uint32_t brk_insn = 0xd4200000; 2049 2050 int hvf_arch_insert_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) 2051 { 2052 if (cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) || 2053 cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { 2054 return -EINVAL; 2055 } 2056 return 0; 2057 } 2058 2059 int hvf_arch_remove_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) 2060 { 2061 static uint32_t brk; 2062 2063 if (cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&brk, 4, 0) || 2064 brk != brk_insn || 2065 cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { 2066 return -EINVAL; 2067 } 2068 return 0; 2069 } 2070 2071 int hvf_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) 2072 { 2073 switch (type) { 2074 case GDB_BREAKPOINT_HW: 2075 return insert_hw_breakpoint(addr); 2076 case GDB_WATCHPOINT_READ: 2077 case GDB_WATCHPOINT_WRITE: 2078 case GDB_WATCHPOINT_ACCESS: 2079 return insert_hw_watchpoint(addr, len, type); 2080 default: 2081 return -ENOSYS; 2082 } 2083 } 2084 2085 int hvf_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) 2086 { 2087 switch (type) { 2088 case GDB_BREAKPOINT_HW: 2089 return delete_hw_breakpoint(addr); 2090 case GDB_WATCHPOINT_READ: 2091 case GDB_WATCHPOINT_WRITE: 2092 case GDB_WATCHPOINT_ACCESS: 2093 return delete_hw_watchpoint(addr, len, type); 2094 default: 2095 return -ENOSYS; 2096 } 2097 } 2098 2099 void hvf_arch_remove_all_hw_breakpoints(void) 2100 { 2101 if (cur_hw_wps > 0) { 2102 g_array_remove_range(hw_watchpoints, 0, cur_hw_wps); 2103 } 2104 if (cur_hw_bps > 0) { 2105 g_array_remove_range(hw_breakpoints, 0, cur_hw_bps); 2106 } 2107 } 2108 2109 /* 2110 * Update the vCPU with the gdbstub's view of debug registers. This view 2111 * consists of all hardware breakpoints and watchpoints inserted so far while 2112 * debugging the guest. 2113 */ 2114 static void hvf_put_gdbstub_debug_registers(CPUState *cpu) 2115 { 2116 hv_return_t r = HV_SUCCESS; 2117 int i; 2118 2119 for (i = 0; i < cur_hw_bps; i++) { 2120 HWBreakpoint *bp = get_hw_bp(i); 2121 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], bp->bcr); 2122 assert_hvf_ok(r); 2123 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], bp->bvr); 2124 assert_hvf_ok(r); 2125 } 2126 for (i = cur_hw_bps; i < max_hw_bps; i++) { 2127 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], 0); 2128 assert_hvf_ok(r); 2129 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], 0); 2130 assert_hvf_ok(r); 2131 } 2132 2133 for (i = 0; i < cur_hw_wps; i++) { 2134 HWWatchpoint *wp = get_hw_wp(i); 2135 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], wp->wcr); 2136 assert_hvf_ok(r); 2137 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], wp->wvr); 2138 assert_hvf_ok(r); 2139 } 2140 for (i = cur_hw_wps; i < max_hw_wps; i++) { 2141 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], 0); 2142 assert_hvf_ok(r); 2143 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], 0); 2144 assert_hvf_ok(r); 2145 } 2146 } 2147 2148 /* 2149 * Update the vCPU with the guest's view of debug registers. This view is kept 2150 * in the environment at all times. 2151 */ 2152 static void hvf_put_guest_debug_registers(CPUState *cpu) 2153 { 2154 ARMCPU *arm_cpu = ARM_CPU(cpu); 2155 CPUARMState *env = &arm_cpu->env; 2156 hv_return_t r = HV_SUCCESS; 2157 int i; 2158 2159 for (i = 0; i < max_hw_bps; i++) { 2160 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], 2161 env->cp15.dbgbcr[i]); 2162 assert_hvf_ok(r); 2163 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], 2164 env->cp15.dbgbvr[i]); 2165 assert_hvf_ok(r); 2166 } 2167 2168 for (i = 0; i < max_hw_wps; i++) { 2169 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], 2170 env->cp15.dbgwcr[i]); 2171 assert_hvf_ok(r); 2172 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], 2173 env->cp15.dbgwvr[i]); 2174 assert_hvf_ok(r); 2175 } 2176 } 2177 2178 static inline bool hvf_arm_hw_debug_active(CPUState *cpu) 2179 { 2180 return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); 2181 } 2182 2183 static void hvf_arch_set_traps(void) 2184 { 2185 CPUState *cpu; 2186 bool should_enable_traps = false; 2187 hv_return_t r = HV_SUCCESS; 2188 2189 /* Check whether guest debugging is enabled for at least one vCPU; if it 2190 * is, enable exiting the guest on all vCPUs */ 2191 CPU_FOREACH(cpu) { 2192 should_enable_traps |= cpu->accel->guest_debug_enabled; 2193 } 2194 CPU_FOREACH(cpu) { 2195 /* Set whether debug exceptions exit the guest */ 2196 r = hv_vcpu_set_trap_debug_exceptions(cpu->accel->fd, 2197 should_enable_traps); 2198 assert_hvf_ok(r); 2199 2200 /* Set whether accesses to debug registers exit the guest */ 2201 r = hv_vcpu_set_trap_debug_reg_accesses(cpu->accel->fd, 2202 should_enable_traps); 2203 assert_hvf_ok(r); 2204 } 2205 } 2206 2207 void hvf_arch_update_guest_debug(CPUState *cpu) 2208 { 2209 ARMCPU *arm_cpu = ARM_CPU(cpu); 2210 CPUARMState *env = &arm_cpu->env; 2211 2212 /* Check whether guest debugging is enabled */ 2213 cpu->accel->guest_debug_enabled = cpu->singlestep_enabled || 2214 hvf_sw_breakpoints_active(cpu) || 2215 hvf_arm_hw_debug_active(cpu); 2216 2217 /* Update debug registers */ 2218 if (cpu->accel->guest_debug_enabled) { 2219 hvf_put_gdbstub_debug_registers(cpu); 2220 } else { 2221 hvf_put_guest_debug_registers(cpu); 2222 } 2223 2224 cpu_synchronize_state(cpu); 2225 2226 /* Enable/disable single-stepping */ 2227 if (cpu->singlestep_enabled) { 2228 env->cp15.mdscr_el1 = 2229 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 1); 2230 pstate_write(env, pstate_read(env) | PSTATE_SS); 2231 } else { 2232 env->cp15.mdscr_el1 = 2233 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 0); 2234 } 2235 2236 /* Enable/disable Breakpoint exceptions */ 2237 if (hvf_arm_hw_debug_active(cpu)) { 2238 env->cp15.mdscr_el1 = 2239 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 1); 2240 } else { 2241 env->cp15.mdscr_el1 = 2242 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 0); 2243 } 2244 2245 hvf_arch_set_traps(); 2246 } 2247 2248 inline bool hvf_arch_supports_guest_debug(void) 2249 { 2250 return true; 2251 } 2252