1*f4f318b4SPhilippe Mathieu-Daudé /* 2*f4f318b4SPhilippe Mathieu-Daudé * ARM generic timer definitions for Arm A-class CPU 3*f4f318b4SPhilippe Mathieu-Daudé * 4*f4f318b4SPhilippe Mathieu-Daudé * Copyright (c) 2003 Fabrice Bellard 5*f4f318b4SPhilippe Mathieu-Daudé * 6*f4f318b4SPhilippe Mathieu-Daudé * SPDX-License-Identifier: LGPL-2.1-or-later 7*f4f318b4SPhilippe Mathieu-Daudé */ 8*f4f318b4SPhilippe Mathieu-Daudé 9*f4f318b4SPhilippe Mathieu-Daudé #ifndef TARGET_ARM_GTIMER_H 10*f4f318b4SPhilippe Mathieu-Daudé #define TARGET_ARM_GTIMER_H 11*f4f318b4SPhilippe Mathieu-Daudé 12*f4f318b4SPhilippe Mathieu-Daudé enum { 13*f4f318b4SPhilippe Mathieu-Daudé GTIMER_PHYS = 0, 14*f4f318b4SPhilippe Mathieu-Daudé GTIMER_VIRT = 1, 15*f4f318b4SPhilippe Mathieu-Daudé GTIMER_HYP = 2, 16*f4f318b4SPhilippe Mathieu-Daudé GTIMER_SEC = 3, 17*f4f318b4SPhilippe Mathieu-Daudé GTIMER_HYPVIRT = 4, 18*f4f318b4SPhilippe Mathieu-Daudé #define NUM_GTIMERS 5 19*f4f318b4SPhilippe Mathieu-Daudé }; 20*f4f318b4SPhilippe Mathieu-Daudé 21*f4f318b4SPhilippe Mathieu-Daudé #endif 22