1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "qapi/qapi-types-common.h" 29 30 /* ARM processors have a weak memory model */ 31 #define TCG_GUEST_DEFAULT_MO (0) 32 33 #ifdef TARGET_AARCH64 34 #define KVM_HAVE_MCE_INJECTION 1 35 #endif 36 37 #define EXCP_UDEF 1 /* undefined instruction */ 38 #define EXCP_SWI 2 /* software interrupt */ 39 #define EXCP_PREFETCH_ABORT 3 40 #define EXCP_DATA_ABORT 4 41 #define EXCP_IRQ 5 42 #define EXCP_FIQ 6 43 #define EXCP_BKPT 7 44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 46 #define EXCP_HVC 11 /* HyperVisor Call */ 47 #define EXCP_HYP_TRAP 12 48 #define EXCP_SMC 13 /* Secure Monitor Call */ 49 #define EXCP_VIRQ 14 50 #define EXCP_VFIQ 15 51 #define EXCP_SEMIHOST 16 /* semihosting call */ 52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 59 #define EXCP_VSERR 24 60 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ 61 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 62 63 #define ARMV7M_EXCP_RESET 1 64 #define ARMV7M_EXCP_NMI 2 65 #define ARMV7M_EXCP_HARD 3 66 #define ARMV7M_EXCP_MEM 4 67 #define ARMV7M_EXCP_BUS 5 68 #define ARMV7M_EXCP_USAGE 6 69 #define ARMV7M_EXCP_SECURE 7 70 #define ARMV7M_EXCP_SVC 11 71 #define ARMV7M_EXCP_DEBUG 12 72 #define ARMV7M_EXCP_PENDSV 14 73 #define ARMV7M_EXCP_SYSTICK 15 74 75 /* For M profile, some registers are banked secure vs non-secure; 76 * these are represented as a 2-element array where the first element 77 * is the non-secure copy and the second is the secure copy. 78 * When the CPU does not have implement the security extension then 79 * only the first element is used. 80 * This means that the copy for the current security state can be 81 * accessed via env->registerfield[env->v7m.secure] (whether the security 82 * extension is implemented or not). 83 */ 84 enum { 85 M_REG_NS = 0, 86 M_REG_S = 1, 87 M_REG_NUM_BANKS = 2, 88 }; 89 90 /* ARM-specific interrupt pending bits. */ 91 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 92 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 93 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 94 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 95 96 /* The usual mapping for an AArch64 system register to its AArch32 97 * counterpart is for the 32 bit world to have access to the lower 98 * half only (with writes leaving the upper half untouched). It's 99 * therefore useful to be able to pass TCG the offset of the least 100 * significant half of a uint64_t struct member. 101 */ 102 #if HOST_BIG_ENDIAN 103 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 104 #define offsetofhigh32(S, M) offsetof(S, M) 105 #else 106 #define offsetoflow32(S, M) offsetof(S, M) 107 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 108 #endif 109 110 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 111 #define ARM_CPU_IRQ 0 112 #define ARM_CPU_FIQ 1 113 #define ARM_CPU_VIRQ 2 114 #define ARM_CPU_VFIQ 3 115 116 /* ARM-specific extra insn start words: 117 * 1: Conditional execution bits 118 * 2: Partial exception syndrome for data aborts 119 */ 120 #define TARGET_INSN_START_EXTRA_WORDS 2 121 122 /* The 2nd extra word holding syndrome info for data aborts does not use 123 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 124 * help the sleb128 encoder do a better job. 125 * When restoring the CPU state, we shift it back up. 126 */ 127 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 128 #define ARM_INSN_START_WORD2_SHIFT 14 129 130 /* We currently assume float and double are IEEE single and double 131 precision respectively. 132 Doing runtime conversions is tricky because VFP registers may contain 133 integer values (eg. as the result of a FTOSI instruction). 134 s<2n> maps to the least significant half of d<n> 135 s<2n+1> maps to the most significant half of d<n> 136 */ 137 138 /** 139 * DynamicGDBXMLInfo: 140 * @desc: Contains the XML descriptions. 141 * @num: Number of the registers in this XML seen by GDB. 142 * @data: A union with data specific to the set of registers 143 * @cpregs_keys: Array that contains the corresponding Key of 144 * a given cpreg with the same order of the cpreg 145 * in the XML description. 146 */ 147 typedef struct DynamicGDBXMLInfo { 148 char *desc; 149 int num; 150 union { 151 struct { 152 uint32_t *keys; 153 } cpregs; 154 } data; 155 } DynamicGDBXMLInfo; 156 157 /* CPU state for each instance of a generic timer (in cp15 c14) */ 158 typedef struct ARMGenericTimer { 159 uint64_t cval; /* Timer CompareValue register */ 160 uint64_t ctl; /* Timer Control register */ 161 } ARMGenericTimer; 162 163 #define GTIMER_PHYS 0 164 #define GTIMER_VIRT 1 165 #define GTIMER_HYP 2 166 #define GTIMER_SEC 3 167 #define GTIMER_HYPVIRT 4 168 #define NUM_GTIMERS 5 169 170 #define VTCR_NSW (1u << 29) 171 #define VTCR_NSA (1u << 30) 172 #define VSTCR_SW VTCR_NSW 173 #define VSTCR_SA VTCR_NSA 174 175 /* Define a maximum sized vector register. 176 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 177 * For 64-bit, this is a 2048-bit SVE register. 178 * 179 * Note that the mapping between S, D, and Q views of the register bank 180 * differs between AArch64 and AArch32. 181 * In AArch32: 182 * Qn = regs[n].d[1]:regs[n].d[0] 183 * Dn = regs[n / 2].d[n & 1] 184 * Sn = regs[n / 4].d[n % 4 / 2], 185 * bits 31..0 for even n, and bits 63..32 for odd n 186 * (and regs[16] to regs[31] are inaccessible) 187 * In AArch64: 188 * Zn = regs[n].d[*] 189 * Qn = regs[n].d[1]:regs[n].d[0] 190 * Dn = regs[n].d[0] 191 * Sn = regs[n].d[0] bits 31..0 192 * Hn = regs[n].d[0] bits 15..0 193 * 194 * This corresponds to the architecturally defined mapping between 195 * the two execution states, and means we do not need to explicitly 196 * map these registers when changing states. 197 * 198 * Align the data for use with TCG host vector operations. 199 */ 200 201 #ifdef TARGET_AARCH64 202 # define ARM_MAX_VQ 16 203 #else 204 # define ARM_MAX_VQ 1 205 #endif 206 207 typedef struct ARMVectorReg { 208 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 209 } ARMVectorReg; 210 211 #ifdef TARGET_AARCH64 212 /* In AArch32 mode, predicate registers do not exist at all. */ 213 typedef struct ARMPredicateReg { 214 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 215 } ARMPredicateReg; 216 217 /* In AArch32 mode, PAC keys do not exist at all. */ 218 typedef struct ARMPACKey { 219 uint64_t lo, hi; 220 } ARMPACKey; 221 #endif 222 223 /* See the commentary above the TBFLAG field definitions. */ 224 typedef struct CPUARMTBFlags { 225 uint32_t flags; 226 target_ulong flags2; 227 } CPUARMTBFlags; 228 229 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 230 231 typedef struct NVICState NVICState; 232 233 typedef struct CPUArchState { 234 /* Regs for current mode. */ 235 uint32_t regs[16]; 236 237 /* 32/64 switch only happens when taking and returning from 238 * exceptions so the overlap semantics are taken care of then 239 * instead of having a complicated union. 240 */ 241 /* Regs for A64 mode. */ 242 uint64_t xregs[32]; 243 uint64_t pc; 244 /* PSTATE isn't an architectural register for ARMv8. However, it is 245 * convenient for us to assemble the underlying state into a 32 bit format 246 * identical to the architectural format used for the SPSR. (This is also 247 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 248 * 'pstate' register are.) Of the PSTATE bits: 249 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 250 * semantics as for AArch32, as described in the comments on each field) 251 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 252 * DAIF (exception masks) are kept in env->daif 253 * BTYPE is kept in env->btype 254 * SM and ZA are kept in env->svcr 255 * all other bits are stored in their correct places in env->pstate 256 */ 257 uint32_t pstate; 258 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 259 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 260 261 /* Cached TBFLAGS state. See below for which bits are included. */ 262 CPUARMTBFlags hflags; 263 264 /* Frequently accessed CPSR bits are stored separately for efficiency. 265 This contains all the other bits. Use cpsr_{read,write} to access 266 the whole CPSR. */ 267 uint32_t uncached_cpsr; 268 uint32_t spsr; 269 270 /* Banked registers. */ 271 uint64_t banked_spsr[8]; 272 uint32_t banked_r13[8]; 273 uint32_t banked_r14[8]; 274 275 /* These hold r8-r12. */ 276 uint32_t usr_regs[5]; 277 uint32_t fiq_regs[5]; 278 279 /* cpsr flag cache for faster execution */ 280 uint32_t CF; /* 0 or 1 */ 281 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 282 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 283 uint32_t ZF; /* Z set if zero. */ 284 uint32_t QF; /* 0 or 1 */ 285 uint32_t GE; /* cpsr[19:16] */ 286 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 287 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 288 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 289 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 290 291 uint64_t elr_el[4]; /* AArch64 exception link regs */ 292 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 293 294 /* System control coprocessor (cp15) */ 295 struct { 296 uint32_t c0_cpuid; 297 union { /* Cache size selection */ 298 struct { 299 uint64_t _unused_csselr0; 300 uint64_t csselr_ns; 301 uint64_t _unused_csselr1; 302 uint64_t csselr_s; 303 }; 304 uint64_t csselr_el[4]; 305 }; 306 union { /* System control register. */ 307 struct { 308 uint64_t _unused_sctlr; 309 uint64_t sctlr_ns; 310 uint64_t hsctlr; 311 uint64_t sctlr_s; 312 }; 313 uint64_t sctlr_el[4]; 314 }; 315 uint64_t vsctlr; /* Virtualization System control register. */ 316 uint64_t cpacr_el1; /* Architectural feature access control register */ 317 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 318 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 319 uint64_t sder; /* Secure debug enable register. */ 320 uint32_t nsacr; /* Non-secure access control register. */ 321 union { /* MMU translation table base 0. */ 322 struct { 323 uint64_t _unused_ttbr0_0; 324 uint64_t ttbr0_ns; 325 uint64_t _unused_ttbr0_1; 326 uint64_t ttbr0_s; 327 }; 328 uint64_t ttbr0_el[4]; 329 }; 330 union { /* MMU translation table base 1. */ 331 struct { 332 uint64_t _unused_ttbr1_0; 333 uint64_t ttbr1_ns; 334 uint64_t _unused_ttbr1_1; 335 uint64_t ttbr1_s; 336 }; 337 uint64_t ttbr1_el[4]; 338 }; 339 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 340 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 341 /* MMU translation table base control. */ 342 uint64_t tcr_el[4]; 343 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 344 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 345 uint32_t c2_data; /* MPU data cacheable bits. */ 346 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 347 union { /* MMU domain access control register 348 * MPU write buffer control. 349 */ 350 struct { 351 uint64_t dacr_ns; 352 uint64_t dacr_s; 353 }; 354 struct { 355 uint64_t dacr32_el2; 356 }; 357 }; 358 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 359 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 360 uint64_t hcr_el2; /* Hypervisor configuration register */ 361 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 362 uint64_t scr_el3; /* Secure configuration register. */ 363 union { /* Fault status registers. */ 364 struct { 365 uint64_t ifsr_ns; 366 uint64_t ifsr_s; 367 }; 368 struct { 369 uint64_t ifsr32_el2; 370 }; 371 }; 372 union { 373 struct { 374 uint64_t _unused_dfsr; 375 uint64_t dfsr_ns; 376 uint64_t hsr; 377 uint64_t dfsr_s; 378 }; 379 uint64_t esr_el[4]; 380 }; 381 uint32_t c6_region[8]; /* MPU base/size registers. */ 382 union { /* Fault address registers. */ 383 struct { 384 uint64_t _unused_far0; 385 #if HOST_BIG_ENDIAN 386 uint32_t ifar_ns; 387 uint32_t dfar_ns; 388 uint32_t ifar_s; 389 uint32_t dfar_s; 390 #else 391 uint32_t dfar_ns; 392 uint32_t ifar_ns; 393 uint32_t dfar_s; 394 uint32_t ifar_s; 395 #endif 396 uint64_t _unused_far3; 397 }; 398 uint64_t far_el[4]; 399 }; 400 uint64_t hpfar_el2; 401 uint64_t hstr_el2; 402 union { /* Translation result. */ 403 struct { 404 uint64_t _unused_par_0; 405 uint64_t par_ns; 406 uint64_t _unused_par_1; 407 uint64_t par_s; 408 }; 409 uint64_t par_el[4]; 410 }; 411 412 uint32_t c9_insn; /* Cache lockdown registers. */ 413 uint32_t c9_data; 414 uint64_t c9_pmcr; /* performance monitor control register */ 415 uint64_t c9_pmcnten; /* perf monitor counter enables */ 416 uint64_t c9_pmovsr; /* perf monitor overflow status */ 417 uint64_t c9_pmuserenr; /* perf monitor user enable */ 418 uint64_t c9_pmselr; /* perf monitor counter selection register */ 419 uint64_t c9_pminten; /* perf monitor interrupt enables */ 420 union { /* Memory attribute redirection */ 421 struct { 422 #if HOST_BIG_ENDIAN 423 uint64_t _unused_mair_0; 424 uint32_t mair1_ns; 425 uint32_t mair0_ns; 426 uint64_t _unused_mair_1; 427 uint32_t mair1_s; 428 uint32_t mair0_s; 429 #else 430 uint64_t _unused_mair_0; 431 uint32_t mair0_ns; 432 uint32_t mair1_ns; 433 uint64_t _unused_mair_1; 434 uint32_t mair0_s; 435 uint32_t mair1_s; 436 #endif 437 }; 438 uint64_t mair_el[4]; 439 }; 440 union { /* vector base address register */ 441 struct { 442 uint64_t _unused_vbar; 443 uint64_t vbar_ns; 444 uint64_t hvbar; 445 uint64_t vbar_s; 446 }; 447 uint64_t vbar_el[4]; 448 }; 449 uint32_t mvbar; /* (monitor) vector base address register */ 450 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 451 struct { /* FCSE PID. */ 452 uint32_t fcseidr_ns; 453 uint32_t fcseidr_s; 454 }; 455 union { /* Context ID. */ 456 struct { 457 uint64_t _unused_contextidr_0; 458 uint64_t contextidr_ns; 459 uint64_t _unused_contextidr_1; 460 uint64_t contextidr_s; 461 }; 462 uint64_t contextidr_el[4]; 463 }; 464 union { /* User RW Thread register. */ 465 struct { 466 uint64_t tpidrurw_ns; 467 uint64_t tpidrprw_ns; 468 uint64_t htpidr; 469 uint64_t _tpidr_el3; 470 }; 471 uint64_t tpidr_el[4]; 472 }; 473 uint64_t tpidr2_el0; 474 /* The secure banks of these registers don't map anywhere */ 475 uint64_t tpidrurw_s; 476 uint64_t tpidrprw_s; 477 uint64_t tpidruro_s; 478 479 union { /* User RO Thread register. */ 480 uint64_t tpidruro_ns; 481 uint64_t tpidrro_el[1]; 482 }; 483 uint64_t c14_cntfrq; /* Counter Frequency register */ 484 uint64_t c14_cntkctl; /* Timer Control register */ 485 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 486 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 487 ARMGenericTimer c14_timer[NUM_GTIMERS]; 488 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 489 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 490 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 491 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 492 uint32_t c15_threadid; /* TI debugger thread-ID. */ 493 uint32_t c15_config_base_address; /* SCU base address. */ 494 uint32_t c15_diagnostic; /* diagnostic register */ 495 uint32_t c15_power_diagnostic; 496 uint32_t c15_power_control; /* power control */ 497 uint64_t dbgbvr[16]; /* breakpoint value registers */ 498 uint64_t dbgbcr[16]; /* breakpoint control registers */ 499 uint64_t dbgwvr[16]; /* watchpoint value registers */ 500 uint64_t dbgwcr[16]; /* watchpoint control registers */ 501 uint64_t dbgclaim; /* DBGCLAIM bits */ 502 uint64_t mdscr_el1; 503 uint64_t oslsr_el1; /* OS Lock Status */ 504 uint64_t osdlr_el1; /* OS DoubleLock status */ 505 uint64_t mdcr_el2; 506 uint64_t mdcr_el3; 507 /* Stores the architectural value of the counter *the last time it was 508 * updated* by pmccntr_op_start. Accesses should always be surrounded 509 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 510 * architecturally-correct value is being read/set. 511 */ 512 uint64_t c15_ccnt; 513 /* Stores the delta between the architectural value and the underlying 514 * cycle count during normal operation. It is used to update c15_ccnt 515 * to be the correct architectural value before accesses. During 516 * accesses, c15_ccnt_delta contains the underlying count being used 517 * for the access, after which it reverts to the delta value in 518 * pmccntr_op_finish. 519 */ 520 uint64_t c15_ccnt_delta; 521 uint64_t c14_pmevcntr[31]; 522 uint64_t c14_pmevcntr_delta[31]; 523 uint64_t c14_pmevtyper[31]; 524 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 525 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 526 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 527 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 528 uint64_t gcr_el1; 529 uint64_t rgsr_el1; 530 531 /* Minimal RAS registers */ 532 uint64_t disr_el1; 533 uint64_t vdisr_el2; 534 uint64_t vsesr_el2; 535 536 /* 537 * Fine-Grained Trap registers. We store these as arrays so the 538 * access checking code doesn't have to manually select 539 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. 540 * FEAT_FGT2 will add more elements to these arrays. 541 */ 542 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ 543 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ 544 uint64_t fgt_exec[1]; /* HFGITR */ 545 546 /* RME registers */ 547 uint64_t gpccr_el3; 548 uint64_t gptbr_el3; 549 uint64_t mfar_el3; 550 } cp15; 551 552 struct { 553 /* M profile has up to 4 stack pointers: 554 * a Main Stack Pointer and a Process Stack Pointer for each 555 * of the Secure and Non-Secure states. (If the CPU doesn't support 556 * the security extension then it has only two SPs.) 557 * In QEMU we always store the currently active SP in regs[13], 558 * and the non-active SP for the current security state in 559 * v7m.other_sp. The stack pointers for the inactive security state 560 * are stored in other_ss_msp and other_ss_psp. 561 * switch_v7m_security_state() is responsible for rearranging them 562 * when we change security state. 563 */ 564 uint32_t other_sp; 565 uint32_t other_ss_msp; 566 uint32_t other_ss_psp; 567 uint32_t vecbase[M_REG_NUM_BANKS]; 568 uint32_t basepri[M_REG_NUM_BANKS]; 569 uint32_t control[M_REG_NUM_BANKS]; 570 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 571 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 572 uint32_t hfsr; /* HardFault Status */ 573 uint32_t dfsr; /* Debug Fault Status Register */ 574 uint32_t sfsr; /* Secure Fault Status Register */ 575 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 576 uint32_t bfar; /* BusFault Address */ 577 uint32_t sfar; /* Secure Fault Address Register */ 578 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 579 int exception; 580 uint32_t primask[M_REG_NUM_BANKS]; 581 uint32_t faultmask[M_REG_NUM_BANKS]; 582 uint32_t aircr; /* only holds r/w state if security extn implemented */ 583 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 584 uint32_t csselr[M_REG_NUM_BANKS]; 585 uint32_t scr[M_REG_NUM_BANKS]; 586 uint32_t msplim[M_REG_NUM_BANKS]; 587 uint32_t psplim[M_REG_NUM_BANKS]; 588 uint32_t fpcar[M_REG_NUM_BANKS]; 589 uint32_t fpccr[M_REG_NUM_BANKS]; 590 uint32_t fpdscr[M_REG_NUM_BANKS]; 591 uint32_t cpacr[M_REG_NUM_BANKS]; 592 uint32_t nsacr; 593 uint32_t ltpsize; 594 uint32_t vpr; 595 } v7m; 596 597 /* Information associated with an exception about to be taken: 598 * code which raises an exception must set cs->exception_index and 599 * the relevant parts of this structure; the cpu_do_interrupt function 600 * will then set the guest-visible registers as part of the exception 601 * entry process. 602 */ 603 struct { 604 uint32_t syndrome; /* AArch64 format syndrome register */ 605 uint32_t fsr; /* AArch32 format fault status register info */ 606 uint64_t vaddress; /* virtual addr associated with exception, if any */ 607 uint32_t target_el; /* EL the exception should be targeted for */ 608 /* If we implement EL2 we will also need to store information 609 * about the intermediate physical address for stage 2 faults. 610 */ 611 } exception; 612 613 /* Information associated with an SError */ 614 struct { 615 uint8_t pending; 616 uint8_t has_esr; 617 uint64_t esr; 618 } serror; 619 620 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 621 622 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 623 uint32_t irq_line_state; 624 625 /* Thumb-2 EE state. */ 626 uint32_t teecr; 627 uint32_t teehbr; 628 629 /* VFP coprocessor state. */ 630 struct { 631 ARMVectorReg zregs[32]; 632 633 #ifdef TARGET_AARCH64 634 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 635 #define FFR_PRED_NUM 16 636 ARMPredicateReg pregs[17]; 637 /* Scratch space for aa64 sve predicate temporary. */ 638 ARMPredicateReg preg_tmp; 639 #endif 640 641 /* We store these fpcsr fields separately for convenience. */ 642 uint32_t qc[4] QEMU_ALIGNED(16); 643 int vec_len; 644 int vec_stride; 645 646 uint32_t xregs[16]; 647 648 /* Scratch space for aa32 neon expansion. */ 649 uint32_t scratch[8]; 650 651 /* There are a number of distinct float control structures: 652 * 653 * fp_status: is the "normal" fp status. 654 * fp_status_fp16: used for half-precision calculations 655 * standard_fp_status : the ARM "Standard FPSCR Value" 656 * standard_fp_status_fp16 : used for half-precision 657 * calculations with the ARM "Standard FPSCR Value" 658 * 659 * Half-precision operations are governed by a separate 660 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 661 * status structure to control this. 662 * 663 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 664 * round-to-nearest and is used by any operations (generally 665 * Neon) which the architecture defines as controlled by the 666 * standard FPSCR value rather than the FPSCR. 667 * 668 * The "standard FPSCR but for fp16 ops" is needed because 669 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 670 * using a fixed value for it. 671 * 672 * To avoid having to transfer exception bits around, we simply 673 * say that the FPSCR cumulative exception flags are the logical 674 * OR of the flags in the four fp statuses. This relies on the 675 * only thing which needs to read the exception flags being 676 * an explicit FPSCR read. 677 */ 678 float_status fp_status; 679 float_status fp_status_f16; 680 float_status standard_fp_status; 681 float_status standard_fp_status_f16; 682 683 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 684 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 685 } vfp; 686 687 uint64_t exclusive_addr; 688 uint64_t exclusive_val; 689 /* 690 * Contains the 'val' for the second 64-bit register of LDXP, which comes 691 * from the higher address, not the high part of a complete 128-bit value. 692 * In some ways it might be more convenient to record the exclusive value 693 * as the low and high halves of a 128 bit data value, but the current 694 * semantics of these fields are baked into the migration format. 695 */ 696 uint64_t exclusive_high; 697 698 /* iwMMXt coprocessor state. */ 699 struct { 700 uint64_t regs[16]; 701 uint64_t val; 702 703 uint32_t cregs[16]; 704 } iwmmxt; 705 706 #ifdef TARGET_AARCH64 707 struct { 708 ARMPACKey apia; 709 ARMPACKey apib; 710 ARMPACKey apda; 711 ARMPACKey apdb; 712 ARMPACKey apga; 713 } keys; 714 715 uint64_t scxtnum_el[4]; 716 717 /* 718 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 719 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 720 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 721 * When SVL is less than the architectural maximum, the accessible 722 * storage is restricted, such that if the SVL is X bytes the guest can 723 * see only the bottom X elements of zarray[], and only the least 724 * significant X bytes of each element of the array. (In other words, 725 * the observable part is always square.) 726 * 727 * The ZA storage can also be considered as a set of square tiles of 728 * elements of different sizes. The mapping from tiles to the ZA array 729 * is architecturally defined, such that for tiles of elements of esz 730 * bytes, the Nth row (or "horizontal slice") of tile T is in 731 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 732 * in the ZA storage, because its rows are striped through the ZA array. 733 * 734 * Because this is so large, keep this toward the end of the reset area, 735 * to keep the offsets into the rest of the structure smaller. 736 */ 737 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 738 #endif 739 740 struct CPUBreakpoint *cpu_breakpoint[16]; 741 struct CPUWatchpoint *cpu_watchpoint[16]; 742 743 /* Optional fault info across tlb lookup. */ 744 ARMMMUFaultInfo *tlb_fi; 745 746 /* Fields up to this point are cleared by a CPU reset */ 747 struct {} end_reset_fields; 748 749 /* Fields after this point are preserved across CPU reset. */ 750 751 /* Internal CPU feature flags. */ 752 uint64_t features; 753 754 /* PMSAv7 MPU */ 755 struct { 756 uint32_t *drbar; 757 uint32_t *drsr; 758 uint32_t *dracr; 759 uint32_t rnr[M_REG_NUM_BANKS]; 760 } pmsav7; 761 762 /* PMSAv8 MPU */ 763 struct { 764 /* The PMSAv8 implementation also shares some PMSAv7 config 765 * and state: 766 * pmsav7.rnr (region number register) 767 * pmsav7_dregion (number of configured regions) 768 */ 769 uint32_t *rbar[M_REG_NUM_BANKS]; 770 uint32_t *rlar[M_REG_NUM_BANKS]; 771 uint32_t *hprbar; 772 uint32_t *hprlar; 773 uint32_t mair0[M_REG_NUM_BANKS]; 774 uint32_t mair1[M_REG_NUM_BANKS]; 775 uint32_t hprselr; 776 } pmsav8; 777 778 /* v8M SAU */ 779 struct { 780 uint32_t *rbar; 781 uint32_t *rlar; 782 uint32_t rnr; 783 uint32_t ctrl; 784 } sau; 785 786 #if !defined(CONFIG_USER_ONLY) 787 NVICState *nvic; 788 const struct arm_boot_info *boot_info; 789 /* Store GICv3CPUState to access from this struct */ 790 void *gicv3state; 791 #else /* CONFIG_USER_ONLY */ 792 /* For usermode syscall translation. */ 793 bool eabi; 794 #endif /* CONFIG_USER_ONLY */ 795 796 #ifdef TARGET_TAGGED_ADDRESSES 797 /* Linux syscall tagged address support */ 798 bool tagged_addr_enable; 799 #endif 800 } CPUARMState; 801 802 static inline void set_feature(CPUARMState *env, int feature) 803 { 804 env->features |= 1ULL << feature; 805 } 806 807 static inline void unset_feature(CPUARMState *env, int feature) 808 { 809 env->features &= ~(1ULL << feature); 810 } 811 812 /** 813 * ARMELChangeHookFn: 814 * type of a function which can be registered via arm_register_el_change_hook() 815 * to get callbacks when the CPU changes its exception level or mode. 816 */ 817 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 818 typedef struct ARMELChangeHook ARMELChangeHook; 819 struct ARMELChangeHook { 820 ARMELChangeHookFn *hook; 821 void *opaque; 822 QLIST_ENTRY(ARMELChangeHook) node; 823 }; 824 825 /* These values map onto the return values for 826 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 827 typedef enum ARMPSCIState { 828 PSCI_ON = 0, 829 PSCI_OFF = 1, 830 PSCI_ON_PENDING = 2 831 } ARMPSCIState; 832 833 typedef struct ARMISARegisters ARMISARegisters; 834 835 /* 836 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 837 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 838 * 839 * While processing properties during initialization, corresponding init bits 840 * are set for bits in sve_vq_map that have been set by properties. 841 * 842 * Bits set in supported represent valid vector lengths for the CPU type. 843 */ 844 typedef struct { 845 uint32_t map, init, supported; 846 } ARMVQMap; 847 848 /** 849 * ARMCPU: 850 * @env: #CPUARMState 851 * 852 * An ARM CPU core. 853 */ 854 struct ArchCPU { 855 CPUState parent_obj; 856 857 CPUARMState env; 858 859 /* Coprocessor information */ 860 GHashTable *cp_regs; 861 /* For marshalling (mostly coprocessor) register state between the 862 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 863 * we use these arrays. 864 */ 865 /* List of register indexes managed via these arrays; (full KVM style 866 * 64 bit indexes, not CPRegInfo 32 bit indexes) 867 */ 868 uint64_t *cpreg_indexes; 869 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 870 uint64_t *cpreg_values; 871 /* Length of the indexes, values, reset_values arrays */ 872 int32_t cpreg_array_len; 873 /* These are used only for migration: incoming data arrives in 874 * these fields and is sanity checked in post_load before copying 875 * to the working data structures above. 876 */ 877 uint64_t *cpreg_vmstate_indexes; 878 uint64_t *cpreg_vmstate_values; 879 int32_t cpreg_vmstate_array_len; 880 881 DynamicGDBXMLInfo dyn_sysreg_xml; 882 DynamicGDBXMLInfo dyn_svereg_xml; 883 DynamicGDBXMLInfo dyn_m_systemreg_xml; 884 DynamicGDBXMLInfo dyn_m_secextreg_xml; 885 886 /* Timers used by the generic (architected) timer */ 887 QEMUTimer *gt_timer[NUM_GTIMERS]; 888 /* 889 * Timer used by the PMU. Its state is restored after migration by 890 * pmu_op_finish() - it does not need other handling during migration 891 */ 892 QEMUTimer *pmu_timer; 893 /* GPIO outputs for generic timer */ 894 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 895 /* GPIO output for GICv3 maintenance interrupt signal */ 896 qemu_irq gicv3_maintenance_interrupt; 897 /* GPIO output for the PMU interrupt */ 898 qemu_irq pmu_interrupt; 899 900 /* MemoryRegion to use for secure physical accesses */ 901 MemoryRegion *secure_memory; 902 903 /* MemoryRegion to use for allocation tag accesses */ 904 MemoryRegion *tag_memory; 905 MemoryRegion *secure_tag_memory; 906 907 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 908 Object *idau; 909 910 /* 'compatible' string for this CPU for Linux device trees */ 911 const char *dtb_compatible; 912 913 /* PSCI version for this CPU 914 * Bits[31:16] = Major Version 915 * Bits[15:0] = Minor Version 916 */ 917 uint32_t psci_version; 918 919 /* Current power state, access guarded by BQL */ 920 ARMPSCIState power_state; 921 922 /* CPU has virtualization extension */ 923 bool has_el2; 924 /* CPU has security extension */ 925 bool has_el3; 926 /* CPU has PMU (Performance Monitor Unit) */ 927 bool has_pmu; 928 /* CPU has VFP */ 929 bool has_vfp; 930 /* CPU has 32 VFP registers */ 931 bool has_vfp_d32; 932 /* CPU has Neon */ 933 bool has_neon; 934 /* CPU has M-profile DSP extension */ 935 bool has_dsp; 936 937 /* CPU has memory protection unit */ 938 bool has_mpu; 939 /* PMSAv7 MPU number of supported regions */ 940 uint32_t pmsav7_dregion; 941 /* PMSAv8 MPU number of supported hyp regions */ 942 uint32_t pmsav8r_hdregion; 943 /* v8M SAU number of supported regions */ 944 uint32_t sau_sregion; 945 946 /* PSCI conduit used to invoke PSCI methods 947 * 0 - disabled, 1 - smc, 2 - hvc 948 */ 949 uint32_t psci_conduit; 950 951 /* For v8M, initial value of the Secure VTOR */ 952 uint32_t init_svtor; 953 /* For v8M, initial value of the Non-secure VTOR */ 954 uint32_t init_nsvtor; 955 956 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 957 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 958 */ 959 uint32_t kvm_target; 960 961 #ifdef CONFIG_KVM 962 /* KVM init features for this CPU */ 963 uint32_t kvm_init_features[7]; 964 965 /* KVM CPU state */ 966 967 /* KVM virtual time adjustment */ 968 bool kvm_adjvtime; 969 bool kvm_vtime_dirty; 970 uint64_t kvm_vtime; 971 972 /* KVM steal time */ 973 OnOffAuto kvm_steal_time; 974 #endif /* CONFIG_KVM */ 975 976 /* Uniprocessor system with MP extensions */ 977 bool mp_is_up; 978 979 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 980 * and the probe failed (so we need to report the error in realize) 981 */ 982 bool host_cpu_probe_failed; 983 984 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 985 * register. 986 */ 987 int32_t core_count; 988 989 /* The instance init functions for implementation-specific subclasses 990 * set these fields to specify the implementation-dependent values of 991 * various constant registers and reset values of non-constant 992 * registers. 993 * Some of these might become QOM properties eventually. 994 * Field names match the official register names as defined in the 995 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 996 * is used for reset values of non-constant registers; no reset_ 997 * prefix means a constant register. 998 * Some of these registers are split out into a substructure that 999 * is shared with the translators to control the ISA. 1000 * 1001 * Note that if you add an ID register to the ARMISARegisters struct 1002 * you need to also update the 32-bit and 64-bit versions of the 1003 * kvm_arm_get_host_cpu_features() function to correctly populate the 1004 * field by reading the value from the KVM vCPU. 1005 */ 1006 struct ARMISARegisters { 1007 uint32_t id_isar0; 1008 uint32_t id_isar1; 1009 uint32_t id_isar2; 1010 uint32_t id_isar3; 1011 uint32_t id_isar4; 1012 uint32_t id_isar5; 1013 uint32_t id_isar6; 1014 uint32_t id_mmfr0; 1015 uint32_t id_mmfr1; 1016 uint32_t id_mmfr2; 1017 uint32_t id_mmfr3; 1018 uint32_t id_mmfr4; 1019 uint32_t id_mmfr5; 1020 uint32_t id_pfr0; 1021 uint32_t id_pfr1; 1022 uint32_t id_pfr2; 1023 uint32_t mvfr0; 1024 uint32_t mvfr1; 1025 uint32_t mvfr2; 1026 uint32_t id_dfr0; 1027 uint32_t id_dfr1; 1028 uint32_t dbgdidr; 1029 uint32_t dbgdevid; 1030 uint32_t dbgdevid1; 1031 uint64_t id_aa64isar0; 1032 uint64_t id_aa64isar1; 1033 uint64_t id_aa64isar2; 1034 uint64_t id_aa64pfr0; 1035 uint64_t id_aa64pfr1; 1036 uint64_t id_aa64mmfr0; 1037 uint64_t id_aa64mmfr1; 1038 uint64_t id_aa64mmfr2; 1039 uint64_t id_aa64dfr0; 1040 uint64_t id_aa64dfr1; 1041 uint64_t id_aa64zfr0; 1042 uint64_t id_aa64smfr0; 1043 uint64_t reset_pmcr_el0; 1044 } isar; 1045 uint64_t midr; 1046 uint32_t revidr; 1047 uint32_t reset_fpsid; 1048 uint64_t ctr; 1049 uint32_t reset_sctlr; 1050 uint64_t pmceid0; 1051 uint64_t pmceid1; 1052 uint32_t id_afr0; 1053 uint64_t id_aa64afr0; 1054 uint64_t id_aa64afr1; 1055 uint64_t clidr; 1056 uint64_t mp_affinity; /* MP ID without feature bits */ 1057 /* The elements of this array are the CCSIDR values for each cache, 1058 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1059 */ 1060 uint64_t ccsidr[16]; 1061 uint64_t reset_cbar; 1062 uint32_t reset_auxcr; 1063 bool reset_hivecs; 1064 uint8_t reset_l0gptsz; 1065 1066 /* 1067 * Intermediate values used during property parsing. 1068 * Once finalized, the values should be read from ID_AA64*. 1069 */ 1070 bool prop_pauth; 1071 bool prop_pauth_impdef; 1072 bool prop_pauth_qarma3; 1073 bool prop_lpa2; 1074 1075 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1076 uint8_t dcz_blocksize; 1077 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ 1078 uint8_t gm_blocksize; 1079 1080 uint64_t rvbar_prop; /* Property/input signals. */ 1081 1082 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1083 int gic_num_lrs; /* number of list registers */ 1084 int gic_vpribits; /* number of virtual priority bits */ 1085 int gic_vprebits; /* number of virtual preemption bits */ 1086 int gic_pribits; /* number of physical priority bits */ 1087 1088 /* Whether the cfgend input is high (i.e. this CPU should reset into 1089 * big-endian mode). This setting isn't used directly: instead it modifies 1090 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1091 * architecture version. 1092 */ 1093 bool cfgend; 1094 1095 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1096 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1097 1098 int32_t node_id; /* NUMA node this CPU belongs to */ 1099 1100 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1101 uint8_t device_irq_level; 1102 1103 /* Used to set the maximum vector length the cpu will support. */ 1104 uint32_t sve_max_vq; 1105 1106 #ifdef CONFIG_USER_ONLY 1107 /* Used to set the default vector length at process start. */ 1108 uint32_t sve_default_vq; 1109 uint32_t sme_default_vq; 1110 #endif 1111 1112 ARMVQMap sve_vq; 1113 ARMVQMap sme_vq; 1114 1115 /* Generic timer counter frequency, in Hz */ 1116 uint64_t gt_cntfrq_hz; 1117 }; 1118 1119 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1120 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); 1121 1122 void arm_cpu_post_init(Object *obj); 1123 1124 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1125 1126 #ifndef CONFIG_USER_ONLY 1127 extern const VMStateDescription vmstate_arm_cpu; 1128 1129 void arm_cpu_do_interrupt(CPUState *cpu); 1130 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1131 1132 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1133 MemTxAttrs *attrs); 1134 #endif /* !CONFIG_USER_ONLY */ 1135 1136 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1137 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1138 1139 /* Returns the dynamically generated XML for the gdb stub. 1140 * Returns a pointer to the XML contents for the specified XML file or NULL 1141 * if the XML name doesn't match the predefined one. 1142 */ 1143 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1144 1145 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1146 int cpuid, DumpState *s); 1147 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1148 int cpuid, DumpState *s); 1149 1150 /** 1151 * arm_emulate_firmware_reset: Emulate firmware CPU reset handling 1152 * @cpu: CPU (which must have been freshly reset) 1153 * @target_el: exception level to put the CPU into 1154 * @secure: whether to put the CPU in secure state 1155 * 1156 * When QEMU is directly running a guest kernel at a lower level than 1157 * EL3 it implicitly emulates some aspects of the guest firmware. 1158 * This includes that on reset we need to configure the parts of the 1159 * CPU corresponding to EL3 so that the real guest code can run at its 1160 * lower exception level. This function does that post-reset CPU setup, 1161 * for when we do direct boot of a guest kernel, and for when we 1162 * emulate PSCI and similar firmware interfaces starting a CPU at a 1163 * lower exception level. 1164 * 1165 * @target_el must be an EL implemented by the CPU between 1 and 3. 1166 * We do not support dropping into a Secure EL other than 3. 1167 * 1168 * It is the responsibility of the caller to call arm_rebuild_hflags(). 1169 */ 1170 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el); 1171 1172 #ifdef TARGET_AARCH64 1173 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1174 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1175 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1176 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1177 int new_el, bool el0_a64); 1178 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1179 1180 /* 1181 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1182 * The byte at offset i from the start of the in-memory representation contains 1183 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1184 * lowest offsets are stored in the lowest memory addresses, then that nearly 1185 * matches QEMU's representation, which is to use an array of host-endian 1186 * uint64_t's, where the lower offsets are at the lower indices. To complete 1187 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1188 */ 1189 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1190 { 1191 #if HOST_BIG_ENDIAN 1192 int i; 1193 1194 for (i = 0; i < nr; ++i) { 1195 dst[i] = bswap64(src[i]); 1196 } 1197 1198 return dst; 1199 #else 1200 return src; 1201 #endif 1202 } 1203 1204 #else 1205 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1206 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1207 int n, bool a) 1208 { } 1209 #endif 1210 1211 void aarch64_sync_32_to_64(CPUARMState *env); 1212 void aarch64_sync_64_to_32(CPUARMState *env); 1213 1214 int fp_exception_el(CPUARMState *env, int cur_el); 1215 int sve_exception_el(CPUARMState *env, int cur_el); 1216 int sme_exception_el(CPUARMState *env, int cur_el); 1217 1218 /** 1219 * sve_vqm1_for_el_sm: 1220 * @env: CPUARMState 1221 * @el: exception level 1222 * @sm: streaming mode 1223 * 1224 * Compute the current vector length for @el & @sm, in units of 1225 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1226 * If @sm, compute for SVL, otherwise NVL. 1227 */ 1228 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1229 1230 /* Likewise, but using @sm = PSTATE.SM. */ 1231 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1232 1233 static inline bool is_a64(CPUARMState *env) 1234 { 1235 return env->aarch64; 1236 } 1237 1238 /** 1239 * pmu_op_start/finish 1240 * @env: CPUARMState 1241 * 1242 * Convert all PMU counters between their delta form (the typical mode when 1243 * they are enabled) and the guest-visible values. These two calls must 1244 * surround any action which might affect the counters. 1245 */ 1246 void pmu_op_start(CPUARMState *env); 1247 void pmu_op_finish(CPUARMState *env); 1248 1249 /* 1250 * Called when a PMU counter is due to overflow 1251 */ 1252 void arm_pmu_timer_cb(void *opaque); 1253 1254 /** 1255 * Functions to register as EL change hooks for PMU mode filtering 1256 */ 1257 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1258 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1259 1260 /* 1261 * pmu_init 1262 * @cpu: ARMCPU 1263 * 1264 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1265 * for the current configuration 1266 */ 1267 void pmu_init(ARMCPU *cpu); 1268 1269 /* SCTLR bit meanings. Several bits have been reused in newer 1270 * versions of the architecture; in that case we define constants 1271 * for both old and new bit meanings. Code which tests against those 1272 * bits should probably check or otherwise arrange that the CPU 1273 * is the architectural version it expects. 1274 */ 1275 #define SCTLR_M (1U << 0) 1276 #define SCTLR_A (1U << 1) 1277 #define SCTLR_C (1U << 2) 1278 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1279 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1280 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1281 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1282 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1283 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1284 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1285 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1286 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1287 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */ 1288 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1289 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1290 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1291 #define SCTLR_SED (1U << 8) /* v8 onward */ 1292 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1293 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1294 #define SCTLR_F (1U << 10) /* up to v6 */ 1295 #define SCTLR_SW (1U << 10) /* v7 */ 1296 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1297 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1298 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1299 #define SCTLR_I (1U << 12) 1300 #define SCTLR_V (1U << 13) /* AArch32 only */ 1301 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1302 #define SCTLR_RR (1U << 14) /* up to v7 */ 1303 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1304 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1305 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1306 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1307 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1308 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1309 #define SCTLR_BR (1U << 17) /* PMSA only */ 1310 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1311 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1312 #define SCTLR_WXN (1U << 19) 1313 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1314 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1315 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1316 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1317 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1318 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1319 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1320 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1321 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1322 #define SCTLR_VE (1U << 24) /* up to v7 */ 1323 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1324 #define SCTLR_EE (1U << 25) 1325 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1326 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1327 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1328 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1329 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1330 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1331 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1332 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1333 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1334 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1335 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1336 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1337 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */ 1338 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1339 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1340 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1341 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1342 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1343 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1344 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1345 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1346 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1347 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1348 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1349 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1350 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1351 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1352 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1353 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1354 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1355 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1356 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1357 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1358 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1359 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1360 1361 /* Bit definitions for CPACR (AArch32 only) */ 1362 FIELD(CPACR, CP10, 20, 2) 1363 FIELD(CPACR, CP11, 22, 2) 1364 FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ 1365 FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ 1366 FIELD(CPACR, ASEDIS, 31, 1) 1367 1368 /* Bit definitions for CPACR_EL1 (AArch64 only) */ 1369 FIELD(CPACR_EL1, ZEN, 16, 2) 1370 FIELD(CPACR_EL1, FPEN, 20, 2) 1371 FIELD(CPACR_EL1, SMEN, 24, 2) 1372 FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ 1373 1374 /* Bit definitions for HCPTR (AArch32 only) */ 1375 FIELD(HCPTR, TCP10, 10, 1) 1376 FIELD(HCPTR, TCP11, 11, 1) 1377 FIELD(HCPTR, TASE, 15, 1) 1378 FIELD(HCPTR, TTA, 20, 1) 1379 FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ 1380 FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ 1381 1382 /* Bit definitions for CPTR_EL2 (AArch64 only) */ 1383 FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ 1384 FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ 1385 FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ 1386 FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ 1387 FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ 1388 FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ 1389 FIELD(CPTR_EL2, TTA, 28, 1) 1390 FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ 1391 FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ 1392 1393 /* Bit definitions for CPTR_EL3 (AArch64 only) */ 1394 FIELD(CPTR_EL3, EZ, 8, 1) 1395 FIELD(CPTR_EL3, TFP, 10, 1) 1396 FIELD(CPTR_EL3, ESM, 12, 1) 1397 FIELD(CPTR_EL3, TTA, 20, 1) 1398 FIELD(CPTR_EL3, TAM, 30, 1) 1399 FIELD(CPTR_EL3, TCPAC, 31, 1) 1400 1401 #define MDCR_MTPME (1U << 28) 1402 #define MDCR_TDCC (1U << 27) 1403 #define MDCR_HLP (1U << 26) /* MDCR_EL2 */ 1404 #define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ 1405 #define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ 1406 #define MDCR_EPMAD (1U << 21) 1407 #define MDCR_EDAD (1U << 20) 1408 #define MDCR_TTRF (1U << 19) 1409 #define MDCR_STE (1U << 18) /* MDCR_EL3 */ 1410 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1411 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1412 #define MDCR_SDD (1U << 16) 1413 #define MDCR_SPD (3U << 14) 1414 #define MDCR_TDRA (1U << 11) 1415 #define MDCR_TDOSA (1U << 10) 1416 #define MDCR_TDA (1U << 9) 1417 #define MDCR_TDE (1U << 8) 1418 #define MDCR_HPME (1U << 7) 1419 #define MDCR_TPM (1U << 6) 1420 #define MDCR_TPMCR (1U << 5) 1421 #define MDCR_HPMN (0x1fU) 1422 1423 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1424 #define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \ 1425 MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \ 1426 MDCR_STE | MDCR_SPME | MDCR_SPD) 1427 1428 #define CPSR_M (0x1fU) 1429 #define CPSR_T (1U << 5) 1430 #define CPSR_F (1U << 6) 1431 #define CPSR_I (1U << 7) 1432 #define CPSR_A (1U << 8) 1433 #define CPSR_E (1U << 9) 1434 #define CPSR_IT_2_7 (0xfc00U) 1435 #define CPSR_GE (0xfU << 16) 1436 #define CPSR_IL (1U << 20) 1437 #define CPSR_DIT (1U << 21) 1438 #define CPSR_PAN (1U << 22) 1439 #define CPSR_SSBS (1U << 23) 1440 #define CPSR_J (1U << 24) 1441 #define CPSR_IT_0_1 (3U << 25) 1442 #define CPSR_Q (1U << 27) 1443 #define CPSR_V (1U << 28) 1444 #define CPSR_C (1U << 29) 1445 #define CPSR_Z (1U << 30) 1446 #define CPSR_N (1U << 31) 1447 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1448 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1449 1450 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1451 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1452 | CPSR_NZCV) 1453 /* Bits writable in user mode. */ 1454 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1455 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1456 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1457 1458 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1459 #define XPSR_EXCP 0x1ffU 1460 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1461 #define XPSR_IT_2_7 CPSR_IT_2_7 1462 #define XPSR_GE CPSR_GE 1463 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1464 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1465 #define XPSR_IT_0_1 CPSR_IT_0_1 1466 #define XPSR_Q CPSR_Q 1467 #define XPSR_V CPSR_V 1468 #define XPSR_C CPSR_C 1469 #define XPSR_Z CPSR_Z 1470 #define XPSR_N CPSR_N 1471 #define XPSR_NZCV CPSR_NZCV 1472 #define XPSR_IT CPSR_IT 1473 1474 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1475 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1476 #define TTBCR_PD0 (1U << 4) 1477 #define TTBCR_PD1 (1U << 5) 1478 #define TTBCR_EPD0 (1U << 7) 1479 #define TTBCR_IRGN0 (3U << 8) 1480 #define TTBCR_ORGN0 (3U << 10) 1481 #define TTBCR_SH0 (3U << 12) 1482 #define TTBCR_T1SZ (3U << 16) 1483 #define TTBCR_A1 (1U << 22) 1484 #define TTBCR_EPD1 (1U << 23) 1485 #define TTBCR_IRGN1 (3U << 24) 1486 #define TTBCR_ORGN1 (3U << 26) 1487 #define TTBCR_SH1 (1U << 28) 1488 #define TTBCR_EAE (1U << 31) 1489 1490 FIELD(VTCR, T0SZ, 0, 6) 1491 FIELD(VTCR, SL0, 6, 2) 1492 FIELD(VTCR, IRGN0, 8, 2) 1493 FIELD(VTCR, ORGN0, 10, 2) 1494 FIELD(VTCR, SH0, 12, 2) 1495 FIELD(VTCR, TG0, 14, 2) 1496 FIELD(VTCR, PS, 16, 3) 1497 FIELD(VTCR, VS, 19, 1) 1498 FIELD(VTCR, HA, 21, 1) 1499 FIELD(VTCR, HD, 22, 1) 1500 FIELD(VTCR, HWU59, 25, 1) 1501 FIELD(VTCR, HWU60, 26, 1) 1502 FIELD(VTCR, HWU61, 27, 1) 1503 FIELD(VTCR, HWU62, 28, 1) 1504 FIELD(VTCR, NSW, 29, 1) 1505 FIELD(VTCR, NSA, 30, 1) 1506 FIELD(VTCR, DS, 32, 1) 1507 FIELD(VTCR, SL2, 33, 1) 1508 1509 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1510 * Only these are valid when in AArch64 mode; in 1511 * AArch32 mode SPSRs are basically CPSR-format. 1512 */ 1513 #define PSTATE_SP (1U) 1514 #define PSTATE_M (0xFU) 1515 #define PSTATE_nRW (1U << 4) 1516 #define PSTATE_F (1U << 6) 1517 #define PSTATE_I (1U << 7) 1518 #define PSTATE_A (1U << 8) 1519 #define PSTATE_D (1U << 9) 1520 #define PSTATE_BTYPE (3U << 10) 1521 #define PSTATE_SSBS (1U << 12) 1522 #define PSTATE_IL (1U << 20) 1523 #define PSTATE_SS (1U << 21) 1524 #define PSTATE_PAN (1U << 22) 1525 #define PSTATE_UAO (1U << 23) 1526 #define PSTATE_DIT (1U << 24) 1527 #define PSTATE_TCO (1U << 25) 1528 #define PSTATE_V (1U << 28) 1529 #define PSTATE_C (1U << 29) 1530 #define PSTATE_Z (1U << 30) 1531 #define PSTATE_N (1U << 31) 1532 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1533 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1534 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1535 /* Mode values for AArch64 */ 1536 #define PSTATE_MODE_EL3h 13 1537 #define PSTATE_MODE_EL3t 12 1538 #define PSTATE_MODE_EL2h 9 1539 #define PSTATE_MODE_EL2t 8 1540 #define PSTATE_MODE_EL1h 5 1541 #define PSTATE_MODE_EL1t 4 1542 #define PSTATE_MODE_EL0t 0 1543 1544 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1545 FIELD(SVCR, SM, 0, 1) 1546 FIELD(SVCR, ZA, 1, 1) 1547 1548 /* Fields for SMCR_ELx. */ 1549 FIELD(SMCR, LEN, 0, 4) 1550 FIELD(SMCR, FA64, 31, 1) 1551 1552 /* Write a new value to v7m.exception, thus transitioning into or out 1553 * of Handler mode; this may result in a change of active stack pointer. 1554 */ 1555 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1556 1557 /* Map EL and handler into a PSTATE_MODE. */ 1558 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1559 { 1560 return (el << 2) | handler; 1561 } 1562 1563 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1564 * interprocessing, so we don't attempt to sync with the cpsr state used by 1565 * the 32 bit decoder. 1566 */ 1567 static inline uint32_t pstate_read(CPUARMState *env) 1568 { 1569 int ZF; 1570 1571 ZF = (env->ZF == 0); 1572 return (env->NF & 0x80000000) | (ZF << 30) 1573 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1574 | env->pstate | env->daif | (env->btype << 10); 1575 } 1576 1577 static inline void pstate_write(CPUARMState *env, uint32_t val) 1578 { 1579 env->ZF = (~val) & PSTATE_Z; 1580 env->NF = val; 1581 env->CF = (val >> 29) & 1; 1582 env->VF = (val << 3) & 0x80000000; 1583 env->daif = val & PSTATE_DAIF; 1584 env->btype = (val >> 10) & 3; 1585 env->pstate = val & ~CACHED_PSTATE_BITS; 1586 } 1587 1588 /* Return the current CPSR value. */ 1589 uint32_t cpsr_read(CPUARMState *env); 1590 1591 typedef enum CPSRWriteType { 1592 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1593 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1594 CPSRWriteRaw = 2, 1595 /* trust values, no reg bank switch, no hflags rebuild */ 1596 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1597 } CPSRWriteType; 1598 1599 /* 1600 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1601 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1602 * correspond to TB flags bits cached in the hflags, unless @write_type 1603 * is CPSRWriteRaw. 1604 */ 1605 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1606 CPSRWriteType write_type); 1607 1608 /* Return the current xPSR value. */ 1609 static inline uint32_t xpsr_read(CPUARMState *env) 1610 { 1611 int ZF; 1612 ZF = (env->ZF == 0); 1613 return (env->NF & 0x80000000) | (ZF << 30) 1614 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1615 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1616 | ((env->condexec_bits & 0xfc) << 8) 1617 | (env->GE << 16) 1618 | env->v7m.exception; 1619 } 1620 1621 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1622 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1623 { 1624 if (mask & XPSR_NZCV) { 1625 env->ZF = (~val) & XPSR_Z; 1626 env->NF = val; 1627 env->CF = (val >> 29) & 1; 1628 env->VF = (val << 3) & 0x80000000; 1629 } 1630 if (mask & XPSR_Q) { 1631 env->QF = ((val & XPSR_Q) != 0); 1632 } 1633 if (mask & XPSR_GE) { 1634 env->GE = (val & XPSR_GE) >> 16; 1635 } 1636 #ifndef CONFIG_USER_ONLY 1637 if (mask & XPSR_T) { 1638 env->thumb = ((val & XPSR_T) != 0); 1639 } 1640 if (mask & XPSR_IT_0_1) { 1641 env->condexec_bits &= ~3; 1642 env->condexec_bits |= (val >> 25) & 3; 1643 } 1644 if (mask & XPSR_IT_2_7) { 1645 env->condexec_bits &= 3; 1646 env->condexec_bits |= (val >> 8) & 0xfc; 1647 } 1648 if (mask & XPSR_EXCP) { 1649 /* Note that this only happens on exception exit */ 1650 write_v7m_exception(env, val & XPSR_EXCP); 1651 } 1652 #endif 1653 } 1654 1655 #define HCR_VM (1ULL << 0) 1656 #define HCR_SWIO (1ULL << 1) 1657 #define HCR_PTW (1ULL << 2) 1658 #define HCR_FMO (1ULL << 3) 1659 #define HCR_IMO (1ULL << 4) 1660 #define HCR_AMO (1ULL << 5) 1661 #define HCR_VF (1ULL << 6) 1662 #define HCR_VI (1ULL << 7) 1663 #define HCR_VSE (1ULL << 8) 1664 #define HCR_FB (1ULL << 9) 1665 #define HCR_BSU_MASK (3ULL << 10) 1666 #define HCR_DC (1ULL << 12) 1667 #define HCR_TWI (1ULL << 13) 1668 #define HCR_TWE (1ULL << 14) 1669 #define HCR_TID0 (1ULL << 15) 1670 #define HCR_TID1 (1ULL << 16) 1671 #define HCR_TID2 (1ULL << 17) 1672 #define HCR_TID3 (1ULL << 18) 1673 #define HCR_TSC (1ULL << 19) 1674 #define HCR_TIDCP (1ULL << 20) 1675 #define HCR_TACR (1ULL << 21) 1676 #define HCR_TSW (1ULL << 22) 1677 #define HCR_TPCP (1ULL << 23) 1678 #define HCR_TPU (1ULL << 24) 1679 #define HCR_TTLB (1ULL << 25) 1680 #define HCR_TVM (1ULL << 26) 1681 #define HCR_TGE (1ULL << 27) 1682 #define HCR_TDZ (1ULL << 28) 1683 #define HCR_HCD (1ULL << 29) 1684 #define HCR_TRVM (1ULL << 30) 1685 #define HCR_RW (1ULL << 31) 1686 #define HCR_CD (1ULL << 32) 1687 #define HCR_ID (1ULL << 33) 1688 #define HCR_E2H (1ULL << 34) 1689 #define HCR_TLOR (1ULL << 35) 1690 #define HCR_TERR (1ULL << 36) 1691 #define HCR_TEA (1ULL << 37) 1692 #define HCR_MIOCNCE (1ULL << 38) 1693 #define HCR_TME (1ULL << 39) 1694 #define HCR_APK (1ULL << 40) 1695 #define HCR_API (1ULL << 41) 1696 #define HCR_NV (1ULL << 42) 1697 #define HCR_NV1 (1ULL << 43) 1698 #define HCR_AT (1ULL << 44) 1699 #define HCR_NV2 (1ULL << 45) 1700 #define HCR_FWB (1ULL << 46) 1701 #define HCR_FIEN (1ULL << 47) 1702 #define HCR_GPF (1ULL << 48) 1703 #define HCR_TID4 (1ULL << 49) 1704 #define HCR_TICAB (1ULL << 50) 1705 #define HCR_AMVOFFEN (1ULL << 51) 1706 #define HCR_TOCU (1ULL << 52) 1707 #define HCR_ENSCXT (1ULL << 53) 1708 #define HCR_TTLBIS (1ULL << 54) 1709 #define HCR_TTLBOS (1ULL << 55) 1710 #define HCR_ATA (1ULL << 56) 1711 #define HCR_DCT (1ULL << 57) 1712 #define HCR_TID5 (1ULL << 58) 1713 #define HCR_TWEDEN (1ULL << 59) 1714 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1715 1716 #define HCRX_ENAS0 (1ULL << 0) 1717 #define HCRX_ENALS (1ULL << 1) 1718 #define HCRX_ENASR (1ULL << 2) 1719 #define HCRX_FNXS (1ULL << 3) 1720 #define HCRX_FGTNXS (1ULL << 4) 1721 #define HCRX_SMPME (1ULL << 5) 1722 #define HCRX_TALLINT (1ULL << 6) 1723 #define HCRX_VINMI (1ULL << 7) 1724 #define HCRX_VFNMI (1ULL << 8) 1725 #define HCRX_CMOW (1ULL << 9) 1726 #define HCRX_MCE2 (1ULL << 10) 1727 #define HCRX_MSCEN (1ULL << 11) 1728 1729 #define HPFAR_NS (1ULL << 63) 1730 1731 #define SCR_NS (1ULL << 0) 1732 #define SCR_IRQ (1ULL << 1) 1733 #define SCR_FIQ (1ULL << 2) 1734 #define SCR_EA (1ULL << 3) 1735 #define SCR_FW (1ULL << 4) 1736 #define SCR_AW (1ULL << 5) 1737 #define SCR_NET (1ULL << 6) 1738 #define SCR_SMD (1ULL << 7) 1739 #define SCR_HCE (1ULL << 8) 1740 #define SCR_SIF (1ULL << 9) 1741 #define SCR_RW (1ULL << 10) 1742 #define SCR_ST (1ULL << 11) 1743 #define SCR_TWI (1ULL << 12) 1744 #define SCR_TWE (1ULL << 13) 1745 #define SCR_TLOR (1ULL << 14) 1746 #define SCR_TERR (1ULL << 15) 1747 #define SCR_APK (1ULL << 16) 1748 #define SCR_API (1ULL << 17) 1749 #define SCR_EEL2 (1ULL << 18) 1750 #define SCR_EASE (1ULL << 19) 1751 #define SCR_NMEA (1ULL << 20) 1752 #define SCR_FIEN (1ULL << 21) 1753 #define SCR_ENSCXT (1ULL << 25) 1754 #define SCR_ATA (1ULL << 26) 1755 #define SCR_FGTEN (1ULL << 27) 1756 #define SCR_ECVEN (1ULL << 28) 1757 #define SCR_TWEDEN (1ULL << 29) 1758 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1759 #define SCR_TME (1ULL << 34) 1760 #define SCR_AMVOFFEN (1ULL << 35) 1761 #define SCR_ENAS0 (1ULL << 36) 1762 #define SCR_ADEN (1ULL << 37) 1763 #define SCR_HXEN (1ULL << 38) 1764 #define SCR_TRNDR (1ULL << 40) 1765 #define SCR_ENTP2 (1ULL << 41) 1766 #define SCR_GPF (1ULL << 48) 1767 #define SCR_NSE (1ULL << 62) 1768 1769 #define HSTR_TTEE (1 << 16) 1770 #define HSTR_TJDBX (1 << 17) 1771 1772 #define CNTHCTL_CNTVMASK (1 << 18) 1773 #define CNTHCTL_CNTPMASK (1 << 19) 1774 1775 /* Return the current FPSCR value. */ 1776 uint32_t vfp_get_fpscr(CPUARMState *env); 1777 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1778 1779 /* FPCR, Floating Point Control Register 1780 * FPSR, Floating Poiht Status Register 1781 * 1782 * For A64 the FPSCR is split into two logically distinct registers, 1783 * FPCR and FPSR. However since they still use non-overlapping bits 1784 * we store the underlying state in fpscr and just mask on read/write. 1785 */ 1786 #define FPSR_MASK 0xf800009f 1787 #define FPCR_MASK 0x07ff9f00 1788 1789 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1790 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1791 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1792 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1793 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1794 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1795 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1796 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1797 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1798 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1799 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1800 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1801 #define FPCR_V (1 << 28) /* FP overflow flag */ 1802 #define FPCR_C (1 << 29) /* FP carry flag */ 1803 #define FPCR_Z (1 << 30) /* FP zero flag */ 1804 #define FPCR_N (1 << 31) /* FP negative flag */ 1805 1806 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1807 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1808 #define FPCR_LTPSIZE_LENGTH 3 1809 1810 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1811 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1812 1813 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1814 { 1815 return vfp_get_fpscr(env) & FPSR_MASK; 1816 } 1817 1818 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1819 { 1820 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1821 vfp_set_fpscr(env, new_fpscr); 1822 } 1823 1824 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1825 { 1826 return vfp_get_fpscr(env) & FPCR_MASK; 1827 } 1828 1829 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1830 { 1831 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1832 vfp_set_fpscr(env, new_fpscr); 1833 } 1834 1835 enum arm_cpu_mode { 1836 ARM_CPU_MODE_USR = 0x10, 1837 ARM_CPU_MODE_FIQ = 0x11, 1838 ARM_CPU_MODE_IRQ = 0x12, 1839 ARM_CPU_MODE_SVC = 0x13, 1840 ARM_CPU_MODE_MON = 0x16, 1841 ARM_CPU_MODE_ABT = 0x17, 1842 ARM_CPU_MODE_HYP = 0x1a, 1843 ARM_CPU_MODE_UND = 0x1b, 1844 ARM_CPU_MODE_SYS = 0x1f 1845 }; 1846 1847 /* VFP system registers. */ 1848 #define ARM_VFP_FPSID 0 1849 #define ARM_VFP_FPSCR 1 1850 #define ARM_VFP_MVFR2 5 1851 #define ARM_VFP_MVFR1 6 1852 #define ARM_VFP_MVFR0 7 1853 #define ARM_VFP_FPEXC 8 1854 #define ARM_VFP_FPINST 9 1855 #define ARM_VFP_FPINST2 10 1856 /* These ones are M-profile only */ 1857 #define ARM_VFP_FPSCR_NZCVQC 2 1858 #define ARM_VFP_VPR 12 1859 #define ARM_VFP_P0 13 1860 #define ARM_VFP_FPCXT_NS 14 1861 #define ARM_VFP_FPCXT_S 15 1862 1863 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1864 #define QEMU_VFP_FPSCR_NZCV 0xffff 1865 1866 /* iwMMXt coprocessor control registers. */ 1867 #define ARM_IWMMXT_wCID 0 1868 #define ARM_IWMMXT_wCon 1 1869 #define ARM_IWMMXT_wCSSF 2 1870 #define ARM_IWMMXT_wCASF 3 1871 #define ARM_IWMMXT_wCGR0 8 1872 #define ARM_IWMMXT_wCGR1 9 1873 #define ARM_IWMMXT_wCGR2 10 1874 #define ARM_IWMMXT_wCGR3 11 1875 1876 /* V7M CCR bits */ 1877 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1878 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1879 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1880 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1881 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1882 FIELD(V7M_CCR, STKALIGN, 9, 1) 1883 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1884 FIELD(V7M_CCR, DC, 16, 1) 1885 FIELD(V7M_CCR, IC, 17, 1) 1886 FIELD(V7M_CCR, BP, 18, 1) 1887 FIELD(V7M_CCR, LOB, 19, 1) 1888 FIELD(V7M_CCR, TRD, 20, 1) 1889 1890 /* V7M SCR bits */ 1891 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1892 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1893 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1894 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1895 1896 /* V7M AIRCR bits */ 1897 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1898 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1899 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1900 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1901 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1902 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1903 FIELD(V7M_AIRCR, PRIS, 14, 1) 1904 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1905 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1906 1907 /* V7M CFSR bits for MMFSR */ 1908 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1909 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1910 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1911 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1912 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1913 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1914 1915 /* V7M CFSR bits for BFSR */ 1916 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1917 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1918 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1919 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1920 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1921 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1922 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1923 1924 /* V7M CFSR bits for UFSR */ 1925 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1926 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1927 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1928 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1929 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1930 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1931 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1932 1933 /* V7M CFSR bit masks covering all of the subregister bits */ 1934 FIELD(V7M_CFSR, MMFSR, 0, 8) 1935 FIELD(V7M_CFSR, BFSR, 8, 8) 1936 FIELD(V7M_CFSR, UFSR, 16, 16) 1937 1938 /* V7M HFSR bits */ 1939 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1940 FIELD(V7M_HFSR, FORCED, 30, 1) 1941 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1942 1943 /* V7M DFSR bits */ 1944 FIELD(V7M_DFSR, HALTED, 0, 1) 1945 FIELD(V7M_DFSR, BKPT, 1, 1) 1946 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1947 FIELD(V7M_DFSR, VCATCH, 3, 1) 1948 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1949 1950 /* V7M SFSR bits */ 1951 FIELD(V7M_SFSR, INVEP, 0, 1) 1952 FIELD(V7M_SFSR, INVIS, 1, 1) 1953 FIELD(V7M_SFSR, INVER, 2, 1) 1954 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1955 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1956 FIELD(V7M_SFSR, LSPERR, 5, 1) 1957 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1958 FIELD(V7M_SFSR, LSERR, 7, 1) 1959 1960 /* v7M MPU_CTRL bits */ 1961 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1962 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1963 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1964 1965 /* v7M CLIDR bits */ 1966 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1967 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1968 FIELD(V7M_CLIDR, LOC, 24, 3) 1969 FIELD(V7M_CLIDR, LOUU, 27, 3) 1970 FIELD(V7M_CLIDR, ICB, 30, 2) 1971 1972 FIELD(V7M_CSSELR, IND, 0, 1) 1973 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1974 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1975 * define a mask for this and check that it doesn't permit running off 1976 * the end of the array. 1977 */ 1978 FIELD(V7M_CSSELR, INDEX, 0, 4) 1979 1980 /* v7M FPCCR bits */ 1981 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1982 FIELD(V7M_FPCCR, USER, 1, 1) 1983 FIELD(V7M_FPCCR, S, 2, 1) 1984 FIELD(V7M_FPCCR, THREAD, 3, 1) 1985 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1986 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1987 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1988 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1989 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1990 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1991 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1992 FIELD(V7M_FPCCR, RES0, 11, 15) 1993 FIELD(V7M_FPCCR, TS, 26, 1) 1994 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1995 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1996 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1997 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1998 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1999 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 2000 #define R_V7M_FPCCR_BANKED_MASK \ 2001 (R_V7M_FPCCR_LSPACT_MASK | \ 2002 R_V7M_FPCCR_USER_MASK | \ 2003 R_V7M_FPCCR_THREAD_MASK | \ 2004 R_V7M_FPCCR_MMRDY_MASK | \ 2005 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 2006 R_V7M_FPCCR_UFRDY_MASK | \ 2007 R_V7M_FPCCR_ASPEN_MASK) 2008 2009 /* v7M VPR bits */ 2010 FIELD(V7M_VPR, P0, 0, 16) 2011 FIELD(V7M_VPR, MASK01, 16, 4) 2012 FIELD(V7M_VPR, MASK23, 20, 4) 2013 2014 /* 2015 * System register ID fields. 2016 */ 2017 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 2018 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 2019 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 2020 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 2021 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 2022 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 2023 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 2024 FIELD(CLIDR_EL1, LOUIS, 21, 3) 2025 FIELD(CLIDR_EL1, LOC, 24, 3) 2026 FIELD(CLIDR_EL1, LOUU, 27, 3) 2027 FIELD(CLIDR_EL1, ICB, 30, 3) 2028 2029 /* When FEAT_CCIDX is implemented */ 2030 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 2031 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 2032 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 2033 2034 /* When FEAT_CCIDX is not implemented */ 2035 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 2036 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 2037 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 2038 2039 FIELD(CTR_EL0, IMINLINE, 0, 4) 2040 FIELD(CTR_EL0, L1IP, 14, 2) 2041 FIELD(CTR_EL0, DMINLINE, 16, 4) 2042 FIELD(CTR_EL0, ERG, 20, 4) 2043 FIELD(CTR_EL0, CWG, 24, 4) 2044 FIELD(CTR_EL0, IDC, 28, 1) 2045 FIELD(CTR_EL0, DIC, 29, 1) 2046 FIELD(CTR_EL0, TMINLINE, 32, 6) 2047 2048 FIELD(MIDR_EL1, REVISION, 0, 4) 2049 FIELD(MIDR_EL1, PARTNUM, 4, 12) 2050 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 2051 FIELD(MIDR_EL1, VARIANT, 20, 4) 2052 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 2053 2054 FIELD(ID_ISAR0, SWAP, 0, 4) 2055 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 2056 FIELD(ID_ISAR0, BITFIELD, 8, 4) 2057 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 2058 FIELD(ID_ISAR0, COPROC, 16, 4) 2059 FIELD(ID_ISAR0, DEBUG, 20, 4) 2060 FIELD(ID_ISAR0, DIVIDE, 24, 4) 2061 2062 FIELD(ID_ISAR1, ENDIAN, 0, 4) 2063 FIELD(ID_ISAR1, EXCEPT, 4, 4) 2064 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 2065 FIELD(ID_ISAR1, EXTEND, 12, 4) 2066 FIELD(ID_ISAR1, IFTHEN, 16, 4) 2067 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 2068 FIELD(ID_ISAR1, INTERWORK, 24, 4) 2069 FIELD(ID_ISAR1, JAZELLE, 28, 4) 2070 2071 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 2072 FIELD(ID_ISAR2, MEMHINT, 4, 4) 2073 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 2074 FIELD(ID_ISAR2, MULT, 12, 4) 2075 FIELD(ID_ISAR2, MULTS, 16, 4) 2076 FIELD(ID_ISAR2, MULTU, 20, 4) 2077 FIELD(ID_ISAR2, PSR_AR, 24, 4) 2078 FIELD(ID_ISAR2, REVERSAL, 28, 4) 2079 2080 FIELD(ID_ISAR3, SATURATE, 0, 4) 2081 FIELD(ID_ISAR3, SIMD, 4, 4) 2082 FIELD(ID_ISAR3, SVC, 8, 4) 2083 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 2084 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 2085 FIELD(ID_ISAR3, T32COPY, 20, 4) 2086 FIELD(ID_ISAR3, TRUENOP, 24, 4) 2087 FIELD(ID_ISAR3, T32EE, 28, 4) 2088 2089 FIELD(ID_ISAR4, UNPRIV, 0, 4) 2090 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 2091 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 2092 FIELD(ID_ISAR4, SMC, 12, 4) 2093 FIELD(ID_ISAR4, BARRIER, 16, 4) 2094 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 2095 FIELD(ID_ISAR4, PSR_M, 24, 4) 2096 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 2097 2098 FIELD(ID_ISAR5, SEVL, 0, 4) 2099 FIELD(ID_ISAR5, AES, 4, 4) 2100 FIELD(ID_ISAR5, SHA1, 8, 4) 2101 FIELD(ID_ISAR5, SHA2, 12, 4) 2102 FIELD(ID_ISAR5, CRC32, 16, 4) 2103 FIELD(ID_ISAR5, RDM, 24, 4) 2104 FIELD(ID_ISAR5, VCMA, 28, 4) 2105 2106 FIELD(ID_ISAR6, JSCVT, 0, 4) 2107 FIELD(ID_ISAR6, DP, 4, 4) 2108 FIELD(ID_ISAR6, FHM, 8, 4) 2109 FIELD(ID_ISAR6, SB, 12, 4) 2110 FIELD(ID_ISAR6, SPECRES, 16, 4) 2111 FIELD(ID_ISAR6, BF16, 20, 4) 2112 FIELD(ID_ISAR6, I8MM, 24, 4) 2113 2114 FIELD(ID_MMFR0, VMSA, 0, 4) 2115 FIELD(ID_MMFR0, PMSA, 4, 4) 2116 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2117 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2118 FIELD(ID_MMFR0, TCM, 16, 4) 2119 FIELD(ID_MMFR0, AUXREG, 20, 4) 2120 FIELD(ID_MMFR0, FCSE, 24, 4) 2121 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2122 2123 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2124 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2125 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2126 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2127 FIELD(ID_MMFR1, L1HVD, 16, 4) 2128 FIELD(ID_MMFR1, L1UNI, 20, 4) 2129 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2130 FIELD(ID_MMFR1, BPRED, 28, 4) 2131 2132 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2133 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2134 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2135 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2136 FIELD(ID_MMFR2, UNITLB, 16, 4) 2137 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2138 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2139 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2140 2141 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2142 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2143 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2144 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2145 FIELD(ID_MMFR3, PAN, 16, 4) 2146 FIELD(ID_MMFR3, COHWALK, 20, 4) 2147 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2148 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2149 2150 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2151 FIELD(ID_MMFR4, AC2, 4, 4) 2152 FIELD(ID_MMFR4, XNX, 8, 4) 2153 FIELD(ID_MMFR4, CNP, 12, 4) 2154 FIELD(ID_MMFR4, HPDS, 16, 4) 2155 FIELD(ID_MMFR4, LSM, 20, 4) 2156 FIELD(ID_MMFR4, CCIDX, 24, 4) 2157 FIELD(ID_MMFR4, EVT, 28, 4) 2158 2159 FIELD(ID_MMFR5, ETS, 0, 4) 2160 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2161 2162 FIELD(ID_PFR0, STATE0, 0, 4) 2163 FIELD(ID_PFR0, STATE1, 4, 4) 2164 FIELD(ID_PFR0, STATE2, 8, 4) 2165 FIELD(ID_PFR0, STATE3, 12, 4) 2166 FIELD(ID_PFR0, CSV2, 16, 4) 2167 FIELD(ID_PFR0, AMU, 20, 4) 2168 FIELD(ID_PFR0, DIT, 24, 4) 2169 FIELD(ID_PFR0, RAS, 28, 4) 2170 2171 FIELD(ID_PFR1, PROGMOD, 0, 4) 2172 FIELD(ID_PFR1, SECURITY, 4, 4) 2173 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2174 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2175 FIELD(ID_PFR1, GENTIMER, 16, 4) 2176 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2177 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2178 FIELD(ID_PFR1, GIC, 28, 4) 2179 2180 FIELD(ID_PFR2, CSV3, 0, 4) 2181 FIELD(ID_PFR2, SSBS, 4, 4) 2182 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2183 2184 FIELD(ID_AA64ISAR0, AES, 4, 4) 2185 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2186 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2187 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2188 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2189 FIELD(ID_AA64ISAR0, TME, 24, 4) 2190 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2191 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2192 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2193 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2194 FIELD(ID_AA64ISAR0, DP, 44, 4) 2195 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2196 FIELD(ID_AA64ISAR0, TS, 52, 4) 2197 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2198 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2199 2200 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2201 FIELD(ID_AA64ISAR1, APA, 4, 4) 2202 FIELD(ID_AA64ISAR1, API, 8, 4) 2203 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2204 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2205 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2206 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2207 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2208 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2209 FIELD(ID_AA64ISAR1, SB, 36, 4) 2210 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2211 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2212 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2213 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2214 FIELD(ID_AA64ISAR1, XS, 56, 4) 2215 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2216 2217 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2218 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2219 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2220 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2221 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2222 FIELD(ID_AA64ISAR2, BC, 20, 4) 2223 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2224 FIELD(ID_AA64ISAR2, CLRBHB, 28, 4) 2225 FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4) 2226 FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4) 2227 FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4) 2228 FIELD(ID_AA64ISAR2, RPRFM, 48, 4) 2229 FIELD(ID_AA64ISAR2, CSSC, 52, 4) 2230 FIELD(ID_AA64ISAR2, ATS1A, 60, 4) 2231 2232 FIELD(ID_AA64PFR0, EL0, 0, 4) 2233 FIELD(ID_AA64PFR0, EL1, 4, 4) 2234 FIELD(ID_AA64PFR0, EL2, 8, 4) 2235 FIELD(ID_AA64PFR0, EL3, 12, 4) 2236 FIELD(ID_AA64PFR0, FP, 16, 4) 2237 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2238 FIELD(ID_AA64PFR0, GIC, 24, 4) 2239 FIELD(ID_AA64PFR0, RAS, 28, 4) 2240 FIELD(ID_AA64PFR0, SVE, 32, 4) 2241 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2242 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2243 FIELD(ID_AA64PFR0, AMU, 44, 4) 2244 FIELD(ID_AA64PFR0, DIT, 48, 4) 2245 FIELD(ID_AA64PFR0, RME, 52, 4) 2246 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2247 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2248 2249 FIELD(ID_AA64PFR1, BT, 0, 4) 2250 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2251 FIELD(ID_AA64PFR1, MTE, 8, 4) 2252 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2253 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2254 FIELD(ID_AA64PFR1, SME, 24, 4) 2255 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2256 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2257 FIELD(ID_AA64PFR1, NMI, 36, 4) 2258 FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4) 2259 FIELD(ID_AA64PFR1, GCS, 44, 4) 2260 FIELD(ID_AA64PFR1, THE, 48, 4) 2261 FIELD(ID_AA64PFR1, MTEX, 52, 4) 2262 FIELD(ID_AA64PFR1, DF2, 56, 4) 2263 FIELD(ID_AA64PFR1, PFAR, 60, 4) 2264 2265 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2266 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2267 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2268 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2269 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2270 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2271 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2272 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2273 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2274 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2275 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2276 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2277 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2278 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2279 2280 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2281 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2282 FIELD(ID_AA64MMFR1, VH, 8, 4) 2283 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2284 FIELD(ID_AA64MMFR1, LO, 16, 4) 2285 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2286 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2287 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2288 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2289 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2290 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2291 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2292 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2293 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2294 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2295 FIELD(ID_AA64MMFR1, ECBHB, 60, 4) 2296 2297 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2298 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2299 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2300 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2301 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2302 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2303 FIELD(ID_AA64MMFR2, NV, 24, 4) 2304 FIELD(ID_AA64MMFR2, ST, 28, 4) 2305 FIELD(ID_AA64MMFR2, AT, 32, 4) 2306 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2307 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2308 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2309 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2310 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2311 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2312 2313 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2314 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2315 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2316 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2317 FIELD(ID_AA64DFR0, PMSS, 16, 4) 2318 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2319 FIELD(ID_AA64DFR0, SEBEP, 24, 4) 2320 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2321 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2322 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2323 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2324 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2325 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2326 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2327 FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4) 2328 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2329 2330 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2331 FIELD(ID_AA64ZFR0, AES, 4, 4) 2332 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2333 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2334 FIELD(ID_AA64ZFR0, B16B16, 24, 4) 2335 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2336 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2337 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2338 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2339 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2340 2341 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2342 FIELD(ID_AA64SMFR0, BI32I32, 33, 1) 2343 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2344 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2345 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2346 FIELD(ID_AA64SMFR0, F16F16, 42, 1) 2347 FIELD(ID_AA64SMFR0, B16B16, 43, 1) 2348 FIELD(ID_AA64SMFR0, I16I32, 44, 4) 2349 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2350 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2351 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2352 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2353 2354 FIELD(ID_DFR0, COPDBG, 0, 4) 2355 FIELD(ID_DFR0, COPSDBG, 4, 4) 2356 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2357 FIELD(ID_DFR0, COPTRC, 12, 4) 2358 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2359 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2360 FIELD(ID_DFR0, PERFMON, 24, 4) 2361 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2362 2363 FIELD(ID_DFR1, MTPMU, 0, 4) 2364 FIELD(ID_DFR1, HPMN0, 4, 4) 2365 2366 FIELD(DBGDIDR, SE_IMP, 12, 1) 2367 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2368 FIELD(DBGDIDR, VERSION, 16, 4) 2369 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2370 FIELD(DBGDIDR, BRPS, 24, 4) 2371 FIELD(DBGDIDR, WRPS, 28, 4) 2372 2373 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2374 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2375 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2376 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2377 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2378 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2379 FIELD(DBGDEVID, AUXREGS, 24, 4) 2380 FIELD(DBGDEVID, CIDMASK, 28, 4) 2381 2382 FIELD(MVFR0, SIMDREG, 0, 4) 2383 FIELD(MVFR0, FPSP, 4, 4) 2384 FIELD(MVFR0, FPDP, 8, 4) 2385 FIELD(MVFR0, FPTRAP, 12, 4) 2386 FIELD(MVFR0, FPDIVIDE, 16, 4) 2387 FIELD(MVFR0, FPSQRT, 20, 4) 2388 FIELD(MVFR0, FPSHVEC, 24, 4) 2389 FIELD(MVFR0, FPROUND, 28, 4) 2390 2391 FIELD(MVFR1, FPFTZ, 0, 4) 2392 FIELD(MVFR1, FPDNAN, 4, 4) 2393 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2394 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2395 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2396 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2397 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2398 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2399 FIELD(MVFR1, FPHP, 24, 4) 2400 FIELD(MVFR1, SIMDFMAC, 28, 4) 2401 2402 FIELD(MVFR2, SIMDMISC, 0, 4) 2403 FIELD(MVFR2, FPMISC, 4, 4) 2404 2405 FIELD(GPCCR, PPS, 0, 3) 2406 FIELD(GPCCR, IRGN, 8, 2) 2407 FIELD(GPCCR, ORGN, 10, 2) 2408 FIELD(GPCCR, SH, 12, 2) 2409 FIELD(GPCCR, PGS, 14, 2) 2410 FIELD(GPCCR, GPC, 16, 1) 2411 FIELD(GPCCR, GPCP, 17, 1) 2412 FIELD(GPCCR, L0GPTSZ, 20, 4) 2413 2414 FIELD(MFAR, FPA, 12, 40) 2415 FIELD(MFAR, NSE, 62, 1) 2416 FIELD(MFAR, NS, 63, 1) 2417 2418 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2419 2420 /* If adding a feature bit which corresponds to a Linux ELF 2421 * HWCAP bit, remember to update the feature-bit-to-hwcap 2422 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2423 */ 2424 enum arm_features { 2425 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2426 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2427 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2428 ARM_FEATURE_V6, 2429 ARM_FEATURE_V6K, 2430 ARM_FEATURE_V7, 2431 ARM_FEATURE_THUMB2, 2432 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2433 ARM_FEATURE_NEON, 2434 ARM_FEATURE_M, /* Microcontroller profile. */ 2435 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2436 ARM_FEATURE_THUMB2EE, 2437 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2438 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2439 ARM_FEATURE_V4T, 2440 ARM_FEATURE_V5, 2441 ARM_FEATURE_STRONGARM, 2442 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2443 ARM_FEATURE_GENERIC_TIMER, 2444 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2445 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2446 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2447 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2448 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2449 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2450 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2451 ARM_FEATURE_V8, 2452 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2453 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2454 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2455 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2456 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2457 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2458 ARM_FEATURE_PMU, /* has PMU support */ 2459 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2460 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2461 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2462 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2463 }; 2464 2465 static inline int arm_feature(CPUARMState *env, int feature) 2466 { 2467 return (env->features & (1ULL << feature)) != 0; 2468 } 2469 2470 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2471 2472 /* 2473 * ARM v9 security states. 2474 * The ordering of the enumeration corresponds to the low 2 bits 2475 * of the GPI value, and (except for Root) the concat of NSE:NS. 2476 */ 2477 2478 typedef enum ARMSecuritySpace { 2479 ARMSS_Secure = 0, 2480 ARMSS_NonSecure = 1, 2481 ARMSS_Root = 2, 2482 ARMSS_Realm = 3, 2483 } ARMSecuritySpace; 2484 2485 /* Return true if @space is secure, in the pre-v9 sense. */ 2486 static inline bool arm_space_is_secure(ARMSecuritySpace space) 2487 { 2488 return space == ARMSS_Secure || space == ARMSS_Root; 2489 } 2490 2491 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ 2492 static inline ARMSecuritySpace arm_secure_to_space(bool secure) 2493 { 2494 return secure ? ARMSS_Secure : ARMSS_NonSecure; 2495 } 2496 2497 #if !defined(CONFIG_USER_ONLY) 2498 /** 2499 * arm_security_space_below_el3: 2500 * @env: cpu context 2501 * 2502 * Return the security space of exception levels below EL3, following 2503 * an exception return to those levels. Unlike arm_security_space, 2504 * this doesn't care about the current EL. 2505 */ 2506 ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); 2507 2508 /** 2509 * arm_is_secure_below_el3: 2510 * @env: cpu context 2511 * 2512 * Return true if exception levels below EL3 are in secure state, 2513 * or would be following an exception return to those levels. 2514 */ 2515 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2516 { 2517 ARMSecuritySpace ss = arm_security_space_below_el3(env); 2518 return ss == ARMSS_Secure; 2519 } 2520 2521 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2522 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2523 { 2524 assert(!arm_feature(env, ARM_FEATURE_M)); 2525 if (arm_feature(env, ARM_FEATURE_EL3)) { 2526 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2527 /* CPU currently in AArch64 state and EL3 */ 2528 return true; 2529 } else if (!is_a64(env) && 2530 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2531 /* CPU currently in AArch32 state and monitor mode */ 2532 return true; 2533 } 2534 } 2535 return false; 2536 } 2537 2538 /** 2539 * arm_security_space: 2540 * @env: cpu context 2541 * 2542 * Return the current security space of the cpu. 2543 */ 2544 ARMSecuritySpace arm_security_space(CPUARMState *env); 2545 2546 /** 2547 * arm_is_secure: 2548 * @env: cpu context 2549 * 2550 * Return true if the processor is in secure state. 2551 */ 2552 static inline bool arm_is_secure(CPUARMState *env) 2553 { 2554 return arm_space_is_secure(arm_security_space(env)); 2555 } 2556 2557 /* 2558 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2559 * This corresponds to the pseudocode EL2Enabled(). 2560 */ 2561 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2562 ARMSecuritySpace space) 2563 { 2564 assert(space != ARMSS_Root); 2565 return arm_feature(env, ARM_FEATURE_EL2) 2566 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); 2567 } 2568 2569 static inline bool arm_is_el2_enabled(CPUARMState *env) 2570 { 2571 return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env)); 2572 } 2573 2574 #else 2575 static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) 2576 { 2577 return ARMSS_NonSecure; 2578 } 2579 2580 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2581 { 2582 return false; 2583 } 2584 2585 static inline ARMSecuritySpace arm_security_space(CPUARMState *env) 2586 { 2587 return ARMSS_NonSecure; 2588 } 2589 2590 static inline bool arm_is_secure(CPUARMState *env) 2591 { 2592 return false; 2593 } 2594 2595 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2596 ARMSecuritySpace space) 2597 { 2598 return false; 2599 } 2600 2601 static inline bool arm_is_el2_enabled(CPUARMState *env) 2602 { 2603 return false; 2604 } 2605 #endif 2606 2607 /** 2608 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2609 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2610 * "for all purposes other than a direct read or write access of HCR_EL2." 2611 * Not included here is HCR_RW. 2612 */ 2613 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); 2614 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2615 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2616 2617 /* Return true if the specified exception level is running in AArch64 state. */ 2618 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2619 { 2620 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2621 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2622 */ 2623 assert(el >= 1 && el <= 3); 2624 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2625 2626 /* The highest exception level is always at the maximum supported 2627 * register width, and then lower levels have a register width controlled 2628 * by bits in the SCR or HCR registers. 2629 */ 2630 if (el == 3) { 2631 return aa64; 2632 } 2633 2634 if (arm_feature(env, ARM_FEATURE_EL3) && 2635 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2636 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2637 } 2638 2639 if (el == 2) { 2640 return aa64; 2641 } 2642 2643 if (arm_is_el2_enabled(env)) { 2644 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2645 } 2646 2647 return aa64; 2648 } 2649 2650 /* Function for determining whether guest cp register reads and writes should 2651 * access the secure or non-secure bank of a cp register. When EL3 is 2652 * operating in AArch32 state, the NS-bit determines whether the secure 2653 * instance of a cp register should be used. When EL3 is AArch64 (or if 2654 * it doesn't exist at all) then there is no register banking, and all 2655 * accesses are to the non-secure version. 2656 */ 2657 static inline bool access_secure_reg(CPUARMState *env) 2658 { 2659 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2660 !arm_el_is_aa64(env, 3) && 2661 !(env->cp15.scr_el3 & SCR_NS)); 2662 2663 return ret; 2664 } 2665 2666 /* Macros for accessing a specified CP register bank */ 2667 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2668 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2669 2670 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2671 do { \ 2672 if (_secure) { \ 2673 (_env)->cp15._regname##_s = (_val); \ 2674 } else { \ 2675 (_env)->cp15._regname##_ns = (_val); \ 2676 } \ 2677 } while (0) 2678 2679 /* Macros for automatically accessing a specific CP register bank depending on 2680 * the current secure state of the system. These macros are not intended for 2681 * supporting instruction translation reads/writes as these are dependent 2682 * solely on the SCR.NS bit and not the mode. 2683 */ 2684 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2685 A32_BANKED_REG_GET((_env), _regname, \ 2686 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2687 2688 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2689 A32_BANKED_REG_SET((_env), _regname, \ 2690 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2691 (_val)) 2692 2693 void arm_cpu_list(void); 2694 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2695 uint32_t cur_el, bool secure); 2696 2697 /* Return the highest implemented Exception Level */ 2698 static inline int arm_highest_el(CPUARMState *env) 2699 { 2700 if (arm_feature(env, ARM_FEATURE_EL3)) { 2701 return 3; 2702 } 2703 if (arm_feature(env, ARM_FEATURE_EL2)) { 2704 return 2; 2705 } 2706 return 1; 2707 } 2708 2709 /* Return true if a v7M CPU is in Handler mode */ 2710 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2711 { 2712 return env->v7m.exception != 0; 2713 } 2714 2715 /* Return the current Exception Level (as per ARMv8; note that this differs 2716 * from the ARMv7 Privilege Level). 2717 */ 2718 static inline int arm_current_el(CPUARMState *env) 2719 { 2720 if (arm_feature(env, ARM_FEATURE_M)) { 2721 return arm_v7m_is_handler_mode(env) || 2722 !(env->v7m.control[env->v7m.secure] & 1); 2723 } 2724 2725 if (is_a64(env)) { 2726 return extract32(env->pstate, 2, 2); 2727 } 2728 2729 switch (env->uncached_cpsr & 0x1f) { 2730 case ARM_CPU_MODE_USR: 2731 return 0; 2732 case ARM_CPU_MODE_HYP: 2733 return 2; 2734 case ARM_CPU_MODE_MON: 2735 return 3; 2736 default: 2737 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2738 /* If EL3 is 32-bit then all secure privileged modes run in 2739 * EL3 2740 */ 2741 return 3; 2742 } 2743 2744 return 1; 2745 } 2746 } 2747 2748 /** 2749 * write_list_to_cpustate 2750 * @cpu: ARMCPU 2751 * 2752 * For each register listed in the ARMCPU cpreg_indexes list, write 2753 * its value from the cpreg_values list into the ARMCPUState structure. 2754 * This updates TCG's working data structures from KVM data or 2755 * from incoming migration state. 2756 * 2757 * Returns: true if all register values were updated correctly, 2758 * false if some register was unknown or could not be written. 2759 * Note that we do not stop early on failure -- we will attempt 2760 * writing all registers in the list. 2761 */ 2762 bool write_list_to_cpustate(ARMCPU *cpu); 2763 2764 /** 2765 * write_cpustate_to_list: 2766 * @cpu: ARMCPU 2767 * @kvm_sync: true if this is for syncing back to KVM 2768 * 2769 * For each register listed in the ARMCPU cpreg_indexes list, write 2770 * its value from the ARMCPUState structure into the cpreg_values list. 2771 * This is used to copy info from TCG's working data structures into 2772 * KVM or for outbound migration. 2773 * 2774 * @kvm_sync is true if we are doing this in order to sync the 2775 * register state back to KVM. In this case we will only update 2776 * values in the list if the previous list->cpustate sync actually 2777 * successfully wrote the CPU state. Otherwise we will keep the value 2778 * that is in the list. 2779 * 2780 * Returns: true if all register values were read correctly, 2781 * false if some register was unknown or could not be read. 2782 * Note that we do not stop early on failure -- we will attempt 2783 * reading all registers in the list. 2784 */ 2785 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2786 2787 #define ARM_CPUID_TI915T 0x54029152 2788 #define ARM_CPUID_TI925T 0x54029252 2789 2790 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2791 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2792 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2793 2794 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2795 2796 #define cpu_list arm_cpu_list 2797 2798 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2799 * 2800 * If EL3 is 64-bit: 2801 * + NonSecure EL1 & 0 stage 1 2802 * + NonSecure EL1 & 0 stage 2 2803 * + NonSecure EL2 2804 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2805 * + Secure EL1 & 0 2806 * + Secure EL3 2807 * If EL3 is 32-bit: 2808 * + NonSecure PL1 & 0 stage 1 2809 * + NonSecure PL1 & 0 stage 2 2810 * + NonSecure PL2 2811 * + Secure PL0 2812 * + Secure PL1 2813 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2814 * 2815 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2816 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2817 * because they may differ in access permissions even if the VA->PA map is 2818 * the same 2819 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2820 * translation, which means that we have one mmu_idx that deals with two 2821 * concatenated translation regimes [this sort of combined s1+2 TLB is 2822 * architecturally permitted] 2823 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2824 * handling via the TLB. The only way to do a stage 1 translation without 2825 * the immediate stage 2 translation is via the ATS or AT system insns, 2826 * which can be slow-pathed and always do a page table walk. 2827 * The only use of stage 2 translations is either as part of an s1+2 2828 * lookup or when loading the descriptors during a stage 1 page table walk, 2829 * and in both those cases we don't use the TLB. 2830 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2831 * translation regimes, because they map reasonably well to each other 2832 * and they can't both be active at the same time. 2833 * 5. we want to be able to use the TLB for accesses done as part of a 2834 * stage1 page table walk, rather than having to walk the stage2 page 2835 * table over and over. 2836 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2837 * Never (PAN) bit within PSTATE. 2838 * 7. we fold together the secure and non-secure regimes for A-profile, 2839 * because there are no banked system registers for aarch64, so the 2840 * process of switching between secure and non-secure is 2841 * already heavyweight. 2842 * 2843 * This gives us the following list of cases: 2844 * 2845 * EL0 EL1&0 stage 1+2 (aka NS PL0) 2846 * EL1 EL1&0 stage 1+2 (aka NS PL1) 2847 * EL1 EL1&0 stage 1+2 +PAN 2848 * EL0 EL2&0 2849 * EL2 EL2&0 2850 * EL2 EL2&0 +PAN 2851 * EL2 (aka NS PL2) 2852 * EL3 (aka S PL1) 2853 * Physical (NS & S) 2854 * Stage2 (NS & S) 2855 * 2856 * for a total of 12 different mmu_idx. 2857 * 2858 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2859 * as A profile. They only need to distinguish EL0 and EL1 (and 2860 * EL2 if we ever model a Cortex-R52). 2861 * 2862 * M profile CPUs are rather different as they do not have a true MMU. 2863 * They have the following different MMU indexes: 2864 * User 2865 * Privileged 2866 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2867 * Privileged, execution priority negative (ditto) 2868 * If the CPU supports the v8M Security Extension then there are also: 2869 * Secure User 2870 * Secure Privileged 2871 * Secure User, execution priority negative 2872 * Secure Privileged, execution priority negative 2873 * 2874 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2875 * are not quite the same -- different CPU types (most notably M profile 2876 * vs A/R profile) would like to use MMU indexes with different semantics, 2877 * but since we don't ever need to use all of those in a single CPU we 2878 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2879 * modes + total number of M profile MMU modes". The lower bits of 2880 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2881 * the same for any particular CPU. 2882 * Variables of type ARMMUIdx are always full values, and the core 2883 * index values are in variables of type 'int'. 2884 * 2885 * Our enumeration includes at the end some entries which are not "true" 2886 * mmu_idx values in that they don't have corresponding TLBs and are only 2887 * valid for doing slow path page table walks. 2888 * 2889 * The constant names here are patterned after the general style of the names 2890 * of the AT/ATS operations. 2891 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2892 * For M profile we arrange them to have a bit for priv, a bit for negpri 2893 * and a bit for secure. 2894 */ 2895 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2896 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2897 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2898 2899 /* Meanings of the bits for M profile mmu idx values */ 2900 #define ARM_MMU_IDX_M_PRIV 0x1 2901 #define ARM_MMU_IDX_M_NEGPRI 0x2 2902 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2903 2904 #define ARM_MMU_IDX_TYPE_MASK \ 2905 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2906 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2907 2908 typedef enum ARMMMUIdx { 2909 /* 2910 * A-profile. 2911 */ 2912 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2913 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2914 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2915 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2916 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2917 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2918 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2919 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2920 2921 /* 2922 * Used for second stage of an S12 page table walk, or for descriptor 2923 * loads during first stage of an S1 page table walk. Note that both 2924 * are in use simultaneously for SecureEL2: the security state for 2925 * the S2 ptw is selected by the NS bit from the S1 ptw. 2926 */ 2927 ARMMMUIdx_Stage2_S = 8 | ARM_MMU_IDX_A, 2928 ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A, 2929 2930 /* TLBs with 1-1 mapping to the physical address spaces. */ 2931 ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, 2932 ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, 2933 ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A, 2934 ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A, 2935 2936 /* 2937 * These are not allocated TLBs and are used only for AT system 2938 * instructions or for the first stage of an S12 page table walk. 2939 */ 2940 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2941 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2942 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2943 2944 /* 2945 * M-profile. 2946 */ 2947 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2948 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2949 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2950 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2951 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2952 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2953 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2954 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2955 } ARMMMUIdx; 2956 2957 /* 2958 * Bit macros for the core-mmu-index values for each index, 2959 * for use when calling tlb_flush_by_mmuidx() and friends. 2960 */ 2961 #define TO_CORE_BIT(NAME) \ 2962 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2963 2964 typedef enum ARMMMUIdxBit { 2965 TO_CORE_BIT(E10_0), 2966 TO_CORE_BIT(E20_0), 2967 TO_CORE_BIT(E10_1), 2968 TO_CORE_BIT(E10_1_PAN), 2969 TO_CORE_BIT(E2), 2970 TO_CORE_BIT(E20_2), 2971 TO_CORE_BIT(E20_2_PAN), 2972 TO_CORE_BIT(E3), 2973 TO_CORE_BIT(Stage2), 2974 TO_CORE_BIT(Stage2_S), 2975 2976 TO_CORE_BIT(MUser), 2977 TO_CORE_BIT(MPriv), 2978 TO_CORE_BIT(MUserNegPri), 2979 TO_CORE_BIT(MPrivNegPri), 2980 TO_CORE_BIT(MSUser), 2981 TO_CORE_BIT(MSPriv), 2982 TO_CORE_BIT(MSUserNegPri), 2983 TO_CORE_BIT(MSPrivNegPri), 2984 } ARMMMUIdxBit; 2985 2986 #undef TO_CORE_BIT 2987 2988 #define MMU_USER_IDX 0 2989 2990 /* Indexes used when registering address spaces with cpu_address_space_init */ 2991 typedef enum ARMASIdx { 2992 ARMASIdx_NS = 0, 2993 ARMASIdx_S = 1, 2994 ARMASIdx_TagNS = 2, 2995 ARMASIdx_TagS = 3, 2996 } ARMASIdx; 2997 2998 static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) 2999 { 3000 /* Assert the relative order of the physical mmu indexes. */ 3001 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0); 3002 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure); 3003 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root); 3004 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm); 3005 3006 return ARMMMUIdx_Phys_S + space; 3007 } 3008 3009 static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) 3010 { 3011 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); 3012 return idx - ARMMMUIdx_Phys_S; 3013 } 3014 3015 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 3016 { 3017 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 3018 * CSSELR is RAZ/WI. 3019 */ 3020 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 3021 } 3022 3023 static inline bool arm_sctlr_b(CPUARMState *env) 3024 { 3025 return 3026 /* We need not implement SCTLR.ITD in user-mode emulation, so 3027 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3028 * This lets people run BE32 binaries with "-cpu any". 3029 */ 3030 #ifndef CONFIG_USER_ONLY 3031 !arm_feature(env, ARM_FEATURE_V7) && 3032 #endif 3033 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3034 } 3035 3036 uint64_t arm_sctlr(CPUARMState *env, int el); 3037 3038 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3039 bool sctlr_b) 3040 { 3041 #ifdef CONFIG_USER_ONLY 3042 /* 3043 * In system mode, BE32 is modelled in line with the 3044 * architecture (as word-invariant big-endianness), where loads 3045 * and stores are done little endian but from addresses which 3046 * are adjusted by XORing with the appropriate constant. So the 3047 * endianness to use for the raw data access is not affected by 3048 * SCTLR.B. 3049 * In user mode, however, we model BE32 as byte-invariant 3050 * big-endianness (because user-only code cannot tell the 3051 * difference), and so we need to use a data access endianness 3052 * that depends on SCTLR.B. 3053 */ 3054 if (sctlr_b) { 3055 return true; 3056 } 3057 #endif 3058 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3059 return env->uncached_cpsr & CPSR_E; 3060 } 3061 3062 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3063 { 3064 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3065 } 3066 3067 /* Return true if the processor is in big-endian mode. */ 3068 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3069 { 3070 if (!is_a64(env)) { 3071 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3072 } else { 3073 int cur_el = arm_current_el(env); 3074 uint64_t sctlr = arm_sctlr(env, cur_el); 3075 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3076 } 3077 } 3078 3079 #include "exec/cpu-all.h" 3080 3081 /* 3082 * We have more than 32-bits worth of state per TB, so we split the data 3083 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3084 * We collect these two parts in CPUARMTBFlags where they are named 3085 * flags and flags2 respectively. 3086 * 3087 * The flags that are shared between all execution modes, TBFLAG_ANY, 3088 * are stored in flags. The flags that are specific to a given mode 3089 * are stores in flags2. Since cs_base is sized on the configured 3090 * address size, flags2 always has 64-bits for A64, and a minimum of 3091 * 32-bits for A32 and M32. 3092 * 3093 * The bits for 32-bit A-profile and M-profile partially overlap: 3094 * 3095 * 31 23 11 10 0 3096 * +-------------+----------+----------------+ 3097 * | | | TBFLAG_A32 | 3098 * | TBFLAG_AM32 | +-----+----------+ 3099 * | | |TBFLAG_M32| 3100 * +-------------+----------------+----------+ 3101 * 31 23 6 5 0 3102 * 3103 * Unless otherwise noted, these bits are cached in env->hflags. 3104 */ 3105 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3106 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3107 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3108 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3109 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3110 /* Target EL if we take a floating-point-disabled exception */ 3111 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3112 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3113 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 3114 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3115 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) 3116 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) 3117 3118 /* 3119 * Bit usage when in AArch32 state, both A- and M-profile. 3120 */ 3121 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3122 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3123 3124 /* 3125 * Bit usage when in AArch32 state, for A-profile only. 3126 */ 3127 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3128 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3129 /* 3130 * We store the bottom two bits of the CPAR as TB flags and handle 3131 * checks on the other bits at runtime. This shares the same bits as 3132 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3133 * Not cached, because VECLEN+VECSTRIDE are not cached. 3134 */ 3135 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3136 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3137 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3138 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3139 /* 3140 * Indicates whether cp register reads and writes by guest code should access 3141 * the secure or nonsecure bank of banked registers; note that this is not 3142 * the same thing as the current security state of the processor! 3143 */ 3144 FIELD(TBFLAG_A32, NS, 10, 1) 3145 /* 3146 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3147 * This requires an SME trap from AArch32 mode when using NEON. 3148 */ 3149 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3150 3151 /* 3152 * Bit usage when in AArch32 state, for M-profile only. 3153 */ 3154 /* Handler (ie not Thread) mode */ 3155 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3156 /* Whether we should generate stack-limit checks */ 3157 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3158 /* Set if FPCCR.LSPACT is set */ 3159 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3160 /* Set if we must create a new FP context */ 3161 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3162 /* Set if FPCCR.S does not match current security state */ 3163 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3164 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3165 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3166 /* Set if in secure mode */ 3167 FIELD(TBFLAG_M32, SECURE, 6, 1) 3168 3169 /* 3170 * Bit usage when in AArch64 state 3171 */ 3172 FIELD(TBFLAG_A64, TBII, 0, 2) 3173 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3174 /* The current vector length, either NVL or SVL. */ 3175 FIELD(TBFLAG_A64, VL, 4, 4) 3176 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3177 FIELD(TBFLAG_A64, BT, 9, 1) 3178 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3179 FIELD(TBFLAG_A64, TBID, 12, 2) 3180 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3181 FIELD(TBFLAG_A64, ATA, 15, 1) 3182 FIELD(TBFLAG_A64, TCMA, 16, 2) 3183 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3184 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3185 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3186 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3187 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3188 FIELD(TBFLAG_A64, SVL, 24, 4) 3189 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3190 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3191 FIELD(TBFLAG_A64, FGT_ERET, 29, 1) 3192 FIELD(TBFLAG_A64, NAA, 30, 1) 3193 FIELD(TBFLAG_A64, ATA0, 31, 1) 3194 3195 /* 3196 * Helpers for using the above. 3197 */ 3198 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3199 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3200 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3201 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3202 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3203 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3204 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3205 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3206 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3207 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3208 3209 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3210 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) 3211 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3212 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3213 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3214 3215 /** 3216 * cpu_mmu_index: 3217 * @env: The cpu environment 3218 * @ifetch: True for code access, false for data access. 3219 * 3220 * Return the core mmu index for the current translation regime. 3221 * This function is used by generic TCG code paths. 3222 */ 3223 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3224 { 3225 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3226 } 3227 3228 /** 3229 * sve_vq 3230 * @env: the cpu context 3231 * 3232 * Return the VL cached within env->hflags, in units of quadwords. 3233 */ 3234 static inline int sve_vq(CPUARMState *env) 3235 { 3236 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3237 } 3238 3239 /** 3240 * sme_vq 3241 * @env: the cpu context 3242 * 3243 * Return the SVL cached within env->hflags, in units of quadwords. 3244 */ 3245 static inline int sme_vq(CPUARMState *env) 3246 { 3247 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3248 } 3249 3250 static inline bool bswap_code(bool sctlr_b) 3251 { 3252 #ifdef CONFIG_USER_ONLY 3253 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3254 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3255 * would also end up as a mixed-endian mode with BE code, LE data. 3256 */ 3257 return TARGET_BIG_ENDIAN ^ sctlr_b; 3258 #else 3259 /* All code access in ARM is little endian, and there are no loaders 3260 * doing swaps that need to be reversed 3261 */ 3262 return 0; 3263 #endif 3264 } 3265 3266 #ifdef CONFIG_USER_ONLY 3267 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3268 { 3269 return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env); 3270 } 3271 #endif 3272 3273 void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, 3274 uint64_t *cs_base, uint32_t *flags); 3275 3276 enum { 3277 QEMU_PSCI_CONDUIT_DISABLED = 0, 3278 QEMU_PSCI_CONDUIT_SMC = 1, 3279 QEMU_PSCI_CONDUIT_HVC = 2, 3280 }; 3281 3282 #ifndef CONFIG_USER_ONLY 3283 /* Return the address space index to use for a memory access */ 3284 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3285 { 3286 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3287 } 3288 3289 /* Return the AddressSpace to use for a memory access 3290 * (which depends on whether the access is S or NS, and whether 3291 * the board gave us a separate AddressSpace for S accesses). 3292 */ 3293 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3294 { 3295 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3296 } 3297 #endif 3298 3299 /** 3300 * arm_register_pre_el_change_hook: 3301 * Register a hook function which will be called immediately before this 3302 * CPU changes exception level or mode. The hook function will be 3303 * passed a pointer to the ARMCPU and the opaque data pointer passed 3304 * to this function when the hook was registered. 3305 * 3306 * Note that if a pre-change hook is called, any registered post-change hooks 3307 * are guaranteed to subsequently be called. 3308 */ 3309 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3310 void *opaque); 3311 /** 3312 * arm_register_el_change_hook: 3313 * Register a hook function which will be called immediately after this 3314 * CPU changes exception level or mode. The hook function will be 3315 * passed a pointer to the ARMCPU and the opaque data pointer passed 3316 * to this function when the hook was registered. 3317 * 3318 * Note that any registered hooks registered here are guaranteed to be called 3319 * if pre-change hooks have been. 3320 */ 3321 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3322 *opaque); 3323 3324 /** 3325 * arm_rebuild_hflags: 3326 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3327 */ 3328 void arm_rebuild_hflags(CPUARMState *env); 3329 3330 /** 3331 * aa32_vfp_dreg: 3332 * Return a pointer to the Dn register within env in 32-bit mode. 3333 */ 3334 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3335 { 3336 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3337 } 3338 3339 /** 3340 * aa32_vfp_qreg: 3341 * Return a pointer to the Qn register within env in 32-bit mode. 3342 */ 3343 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3344 { 3345 return &env->vfp.zregs[regno].d[0]; 3346 } 3347 3348 /** 3349 * aa64_vfp_qreg: 3350 * Return a pointer to the Qn register within env in 64-bit mode. 3351 */ 3352 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3353 { 3354 return &env->vfp.zregs[regno].d[0]; 3355 } 3356 3357 /* Shared between translate-sve.c and sve_helper.c. */ 3358 extern const uint64_t pred_esz_masks[5]; 3359 3360 /* 3361 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3362 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3363 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3364 */ 3365 #define PAGE_BTI PAGE_TARGET_1 3366 #define PAGE_MTE PAGE_TARGET_2 3367 #define PAGE_TARGET_STICKY PAGE_MTE 3368 3369 /* We associate one allocation tag per 16 bytes, the minimum. */ 3370 #define LOG2_TAG_GRANULE 4 3371 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3372 3373 #ifdef CONFIG_USER_ONLY 3374 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) 3375 #endif 3376 3377 #ifdef TARGET_TAGGED_ADDRESSES 3378 /** 3379 * cpu_untagged_addr: 3380 * @cs: CPU context 3381 * @x: tagged address 3382 * 3383 * Remove any address tag from @x. This is explicitly related to the 3384 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3385 * 3386 * There should be a better place to put this, but we need this in 3387 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3388 */ 3389 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3390 { 3391 ARMCPU *cpu = ARM_CPU(cs); 3392 if (cpu->env.tagged_addr_enable) { 3393 /* 3394 * TBI is enabled for userspace but not kernelspace addresses. 3395 * Only clear the tag if bit 55 is clear. 3396 */ 3397 x &= sextract64(x, 0, 56); 3398 } 3399 return x; 3400 } 3401 #endif 3402 3403 #endif 3404