1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "cpu.h" 30 #ifdef CONFIG_TCG 31 #include "hw/core/tcg-cpu-ops.h" 32 #endif /* CONFIG_TCG */ 33 #include "internals.h" 34 #include "exec/exec-all.h" 35 #include "hw/qdev-properties.h" 36 #if !defined(CONFIG_USER_ONLY) 37 #include "hw/loader.h" 38 #include "hw/boards.h" 39 #ifdef CONFIG_TCG 40 #include "hw/intc/armv7m_nvic.h" 41 #endif /* CONFIG_TCG */ 42 #endif /* !CONFIG_USER_ONLY */ 43 #include "sysemu/tcg.h" 44 #include "sysemu/qtest.h" 45 #include "sysemu/hw_accel.h" 46 #include "kvm_arm.h" 47 #include "disas/capstone.h" 48 #include "fpu/softfloat.h" 49 #include "cpregs.h" 50 51 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 52 { 53 ARMCPU *cpu = ARM_CPU(cs); 54 CPUARMState *env = &cpu->env; 55 56 if (is_a64(env)) { 57 env->pc = value; 58 env->thumb = false; 59 } else { 60 env->regs[15] = value & ~1; 61 env->thumb = value & 1; 62 } 63 } 64 65 static vaddr arm_cpu_get_pc(CPUState *cs) 66 { 67 ARMCPU *cpu = ARM_CPU(cs); 68 CPUARMState *env = &cpu->env; 69 70 if (is_a64(env)) { 71 return env->pc; 72 } else { 73 return env->regs[15]; 74 } 75 } 76 77 #ifdef CONFIG_TCG 78 void arm_cpu_synchronize_from_tb(CPUState *cs, 79 const TranslationBlock *tb) 80 { 81 /* The program counter is always up to date with CF_PCREL. */ 82 if (!(tb_cflags(tb) & CF_PCREL)) { 83 CPUARMState *env = cpu_env(cs); 84 /* 85 * It's OK to look at env for the current mode here, because it's 86 * never possible for an AArch64 TB to chain to an AArch32 TB. 87 */ 88 if (is_a64(env)) { 89 env->pc = tb->pc; 90 } else { 91 env->regs[15] = tb->pc; 92 } 93 } 94 } 95 96 void arm_restore_state_to_opc(CPUState *cs, 97 const TranslationBlock *tb, 98 const uint64_t *data) 99 { 100 CPUARMState *env = cpu_env(cs); 101 102 if (is_a64(env)) { 103 if (tb_cflags(tb) & CF_PCREL) { 104 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 105 } else { 106 env->pc = data[0]; 107 } 108 env->condexec_bits = 0; 109 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 110 } else { 111 if (tb_cflags(tb) & CF_PCREL) { 112 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; 113 } else { 114 env->regs[15] = data[0]; 115 } 116 env->condexec_bits = data[1]; 117 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; 118 } 119 } 120 #endif /* CONFIG_TCG */ 121 122 static bool arm_cpu_has_work(CPUState *cs) 123 { 124 ARMCPU *cpu = ARM_CPU(cs); 125 126 return (cpu->power_state != PSCI_OFF) 127 && cs->interrupt_request & 128 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 129 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 130 | CPU_INTERRUPT_EXITTB); 131 } 132 133 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 134 void *opaque) 135 { 136 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 137 138 entry->hook = hook; 139 entry->opaque = opaque; 140 141 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 142 } 143 144 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 145 void *opaque) 146 { 147 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 148 149 entry->hook = hook; 150 entry->opaque = opaque; 151 152 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 153 } 154 155 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 156 { 157 /* Reset a single ARMCPRegInfo register */ 158 ARMCPRegInfo *ri = value; 159 ARMCPU *cpu = opaque; 160 161 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 162 return; 163 } 164 165 if (ri->resetfn) { 166 ri->resetfn(&cpu->env, ri); 167 return; 168 } 169 170 /* A zero offset is never possible as it would be regs[0] 171 * so we use it to indicate that reset is being handled elsewhere. 172 * This is basically only used for fields in non-core coprocessors 173 * (like the pxa2xx ones). 174 */ 175 if (!ri->fieldoffset) { 176 return; 177 } 178 179 if (cpreg_field_is_64bit(ri)) { 180 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 181 } else { 182 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 183 } 184 } 185 186 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 187 { 188 /* Purely an assertion check: we've already done reset once, 189 * so now check that running the reset for the cpreg doesn't 190 * change its value. This traps bugs where two different cpregs 191 * both try to reset the same state field but to different values. 192 */ 193 ARMCPRegInfo *ri = value; 194 ARMCPU *cpu = opaque; 195 uint64_t oldvalue, newvalue; 196 197 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 198 return; 199 } 200 201 oldvalue = read_raw_cp_reg(&cpu->env, ri); 202 cp_reg_reset(key, value, opaque); 203 newvalue = read_raw_cp_reg(&cpu->env, ri); 204 assert(oldvalue == newvalue); 205 } 206 207 static void arm_cpu_reset_hold(Object *obj) 208 { 209 CPUState *s = CPU(obj); 210 ARMCPU *cpu = ARM_CPU(s); 211 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 212 CPUARMState *env = &cpu->env; 213 214 if (acc->parent_phases.hold) { 215 acc->parent_phases.hold(obj); 216 } 217 218 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 219 220 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 221 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 222 223 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 224 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 225 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 226 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 227 228 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 229 230 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 231 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 232 } 233 234 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 235 /* 64 bit CPUs always start in 64 bit mode */ 236 env->aarch64 = true; 237 #if defined(CONFIG_USER_ONLY) 238 env->pstate = PSTATE_MODE_EL0t; 239 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 240 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 241 /* Enable all PAC keys. */ 242 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 243 SCTLR_EnDA | SCTLR_EnDB); 244 /* Trap on btype=3 for PACIxSP. */ 245 env->cp15.sctlr_el[1] |= SCTLR_BT0; 246 /* Trap on implementation defined registers. */ 247 if (cpu_isar_feature(aa64_tidcp1, cpu)) { 248 env->cp15.sctlr_el[1] |= SCTLR_TIDCP; 249 } 250 /* and to the FP/Neon instructions */ 251 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 252 CPACR_EL1, FPEN, 3); 253 /* and to the SVE instructions, with default vector length */ 254 if (cpu_isar_feature(aa64_sve, cpu)) { 255 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 256 CPACR_EL1, ZEN, 3); 257 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 258 } 259 /* and for SME instructions, with default vector length, and TPIDR2 */ 260 if (cpu_isar_feature(aa64_sme, cpu)) { 261 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; 262 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 263 CPACR_EL1, SMEN, 3); 264 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; 265 if (cpu_isar_feature(aa64_sme_fa64, cpu)) { 266 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], 267 SMCR, FA64, 1); 268 } 269 } 270 /* 271 * Enable 48-bit address space (TODO: take reserved_va into account). 272 * Enable TBI0 but not TBI1. 273 * Note that this must match useronly_clean_ptr. 274 */ 275 env->cp15.tcr_el[1] = 5 | (1ULL << 37); 276 277 /* Enable MTE */ 278 if (cpu_isar_feature(aa64_mte, cpu)) { 279 /* Enable tag access, but leave TCF0 as No Effect (0). */ 280 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 281 /* 282 * Exclude all tags, so that tag 0 is always used. 283 * This corresponds to Linux current->thread.gcr_incl = 0. 284 * 285 * Set RRND, so that helper_irg() will generate a seed later. 286 * Here in cpu_reset(), the crypto subsystem has not yet been 287 * initialized. 288 */ 289 env->cp15.gcr_el1 = 0x1ffff; 290 } 291 /* 292 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 293 * This is not yet exposed from the Linux kernel in any way. 294 */ 295 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 296 /* Disable access to Debug Communication Channel (DCC). */ 297 env->cp15.mdscr_el1 |= 1 << 12; 298 #else 299 /* Reset into the highest available EL */ 300 if (arm_feature(env, ARM_FEATURE_EL3)) { 301 env->pstate = PSTATE_MODE_EL3h; 302 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 303 env->pstate = PSTATE_MODE_EL2h; 304 } else { 305 env->pstate = PSTATE_MODE_EL1h; 306 } 307 308 /* Sample rvbar at reset. */ 309 env->cp15.rvbar = cpu->rvbar_prop; 310 env->pc = env->cp15.rvbar; 311 #endif 312 } else { 313 #if defined(CONFIG_USER_ONLY) 314 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 315 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 316 CPACR, CP10, 3); 317 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 318 CPACR, CP11, 3); 319 #endif 320 if (arm_feature(env, ARM_FEATURE_V8)) { 321 env->cp15.rvbar = cpu->rvbar_prop; 322 env->regs[15] = cpu->rvbar_prop; 323 } 324 } 325 326 #if defined(CONFIG_USER_ONLY) 327 env->uncached_cpsr = ARM_CPU_MODE_USR; 328 /* For user mode we must enable access to coprocessors */ 329 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 330 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 331 env->cp15.c15_cpar = 3; 332 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 333 env->cp15.c15_cpar = 1; 334 } 335 #else 336 337 /* 338 * If the highest available EL is EL2, AArch32 will start in Hyp 339 * mode; otherwise it starts in SVC. Note that if we start in 340 * AArch64 then these values in the uncached_cpsr will be ignored. 341 */ 342 if (arm_feature(env, ARM_FEATURE_EL2) && 343 !arm_feature(env, ARM_FEATURE_EL3)) { 344 env->uncached_cpsr = ARM_CPU_MODE_HYP; 345 } else { 346 env->uncached_cpsr = ARM_CPU_MODE_SVC; 347 } 348 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 349 350 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 351 * executing as AArch32 then check if highvecs are enabled and 352 * adjust the PC accordingly. 353 */ 354 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 355 env->regs[15] = 0xFFFF0000; 356 } 357 358 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 359 #endif 360 361 if (arm_feature(env, ARM_FEATURE_M)) { 362 #ifndef CONFIG_USER_ONLY 363 uint32_t initial_msp; /* Loaded from 0x0 */ 364 uint32_t initial_pc; /* Loaded from 0x4 */ 365 uint8_t *rom; 366 uint32_t vecbase; 367 #endif 368 369 if (cpu_isar_feature(aa32_lob, cpu)) { 370 /* 371 * LTPSIZE is constant 4 if MVE not implemented, and resets 372 * to an UNKNOWN value if MVE is implemented. We choose to 373 * always reset to 4. 374 */ 375 env->v7m.ltpsize = 4; 376 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 377 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 378 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 379 } 380 381 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 382 env->v7m.secure = true; 383 } else { 384 /* This bit resets to 0 if security is supported, but 1 if 385 * it is not. The bit is not present in v7M, but we set it 386 * here so we can avoid having to make checks on it conditional 387 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 388 */ 389 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 390 /* 391 * Set NSACR to indicate "NS access permitted to everything"; 392 * this avoids having to have all the tests of it being 393 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 394 * v8.1M the guest-visible value of NSACR in a CPU without the 395 * Security Extension is 0xcff. 396 */ 397 env->v7m.nsacr = 0xcff; 398 } 399 400 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 401 * that it resets to 1, so QEMU always does that rather than making 402 * it dependent on CPU model. In v8M it is RES1. 403 */ 404 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 405 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 406 if (arm_feature(env, ARM_FEATURE_V8)) { 407 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 408 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 409 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 410 } 411 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 412 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 413 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 414 } 415 416 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 417 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 418 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 419 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 420 } 421 422 #ifndef CONFIG_USER_ONLY 423 /* Unlike A/R profile, M profile defines the reset LR value */ 424 env->regs[14] = 0xffffffff; 425 426 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 427 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 428 429 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 430 vecbase = env->v7m.vecbase[env->v7m.secure]; 431 rom = rom_ptr_for_as(s->as, vecbase, 8); 432 if (rom) { 433 /* Address zero is covered by ROM which hasn't yet been 434 * copied into physical memory. 435 */ 436 initial_msp = ldl_p(rom); 437 initial_pc = ldl_p(rom + 4); 438 } else { 439 /* Address zero not covered by a ROM blob, or the ROM blob 440 * is in non-modifiable memory and this is a second reset after 441 * it got copied into memory. In the latter case, rom_ptr 442 * will return a NULL pointer and we should use ldl_phys instead. 443 */ 444 initial_msp = ldl_phys(s->as, vecbase); 445 initial_pc = ldl_phys(s->as, vecbase + 4); 446 } 447 448 qemu_log_mask(CPU_LOG_INT, 449 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 450 initial_msp, initial_pc); 451 452 env->regs[13] = initial_msp & 0xFFFFFFFC; 453 env->regs[15] = initial_pc & ~1; 454 env->thumb = initial_pc & 1; 455 #else 456 /* 457 * For user mode we run non-secure and with access to the FPU. 458 * The FPU context is active (ie does not need further setup) 459 * and is owned by non-secure. 460 */ 461 env->v7m.secure = false; 462 env->v7m.nsacr = 0xcff; 463 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 464 env->v7m.fpccr[M_REG_S] &= 465 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 466 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 467 #endif 468 } 469 470 /* M profile requires that reset clears the exclusive monitor; 471 * A profile does not, but clearing it makes more sense than having it 472 * set with an exclusive access on address zero. 473 */ 474 arm_clear_exclusive(env); 475 476 if (arm_feature(env, ARM_FEATURE_PMSA)) { 477 if (cpu->pmsav7_dregion > 0) { 478 if (arm_feature(env, ARM_FEATURE_V8)) { 479 memset(env->pmsav8.rbar[M_REG_NS], 0, 480 sizeof(*env->pmsav8.rbar[M_REG_NS]) 481 * cpu->pmsav7_dregion); 482 memset(env->pmsav8.rlar[M_REG_NS], 0, 483 sizeof(*env->pmsav8.rlar[M_REG_NS]) 484 * cpu->pmsav7_dregion); 485 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 486 memset(env->pmsav8.rbar[M_REG_S], 0, 487 sizeof(*env->pmsav8.rbar[M_REG_S]) 488 * cpu->pmsav7_dregion); 489 memset(env->pmsav8.rlar[M_REG_S], 0, 490 sizeof(*env->pmsav8.rlar[M_REG_S]) 491 * cpu->pmsav7_dregion); 492 } 493 } else if (arm_feature(env, ARM_FEATURE_V7)) { 494 memset(env->pmsav7.drbar, 0, 495 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 496 memset(env->pmsav7.drsr, 0, 497 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 498 memset(env->pmsav7.dracr, 0, 499 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 500 } 501 } 502 503 if (cpu->pmsav8r_hdregion > 0) { 504 memset(env->pmsav8.hprbar, 0, 505 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion); 506 memset(env->pmsav8.hprlar, 0, 507 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion); 508 } 509 510 env->pmsav7.rnr[M_REG_NS] = 0; 511 env->pmsav7.rnr[M_REG_S] = 0; 512 env->pmsav8.mair0[M_REG_NS] = 0; 513 env->pmsav8.mair0[M_REG_S] = 0; 514 env->pmsav8.mair1[M_REG_NS] = 0; 515 env->pmsav8.mair1[M_REG_S] = 0; 516 } 517 518 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 519 if (cpu->sau_sregion > 0) { 520 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 521 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 522 } 523 env->sau.rnr = 0; 524 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 525 * the Cortex-M33 does. 526 */ 527 env->sau.ctrl = 0; 528 } 529 530 set_flush_to_zero(1, &env->vfp.standard_fp_status); 531 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 532 set_default_nan_mode(1, &env->vfp.standard_fp_status); 533 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 534 set_float_detect_tininess(float_tininess_before_rounding, 535 &env->vfp.fp_status); 536 set_float_detect_tininess(float_tininess_before_rounding, 537 &env->vfp.standard_fp_status); 538 set_float_detect_tininess(float_tininess_before_rounding, 539 &env->vfp.fp_status_f16); 540 set_float_detect_tininess(float_tininess_before_rounding, 541 &env->vfp.standard_fp_status_f16); 542 #ifndef CONFIG_USER_ONLY 543 if (kvm_enabled()) { 544 kvm_arm_reset_vcpu(cpu); 545 } 546 #endif 547 548 if (tcg_enabled()) { 549 hw_breakpoint_update_all(cpu); 550 hw_watchpoint_update_all(cpu); 551 552 arm_rebuild_hflags(env); 553 } 554 } 555 556 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el) 557 { 558 ARMCPU *cpu = ARM_CPU(cpustate); 559 CPUARMState *env = &cpu->env; 560 bool have_el3 = arm_feature(env, ARM_FEATURE_EL3); 561 bool have_el2 = arm_feature(env, ARM_FEATURE_EL2); 562 563 /* 564 * Check we have the EL we're aiming for. If that is the 565 * highest implemented EL, then cpu_reset has already done 566 * all the work. 567 */ 568 switch (target_el) { 569 case 3: 570 assert(have_el3); 571 return; 572 case 2: 573 assert(have_el2); 574 if (!have_el3) { 575 return; 576 } 577 break; 578 case 1: 579 if (!have_el3 && !have_el2) { 580 return; 581 } 582 break; 583 default: 584 g_assert_not_reached(); 585 } 586 587 if (have_el3) { 588 /* 589 * Set the EL3 state so code can run at EL2. This should match 590 * the requirements set by Linux in its booting spec. 591 */ 592 if (env->aarch64) { 593 env->cp15.scr_el3 |= SCR_RW; 594 if (cpu_isar_feature(aa64_pauth, cpu)) { 595 env->cp15.scr_el3 |= SCR_API | SCR_APK; 596 } 597 if (cpu_isar_feature(aa64_mte, cpu)) { 598 env->cp15.scr_el3 |= SCR_ATA; 599 } 600 if (cpu_isar_feature(aa64_sve, cpu)) { 601 env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK; 602 env->vfp.zcr_el[3] = 0xf; 603 } 604 if (cpu_isar_feature(aa64_sme, cpu)) { 605 env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK; 606 env->cp15.scr_el3 |= SCR_ENTP2; 607 env->vfp.smcr_el[3] = 0xf; 608 } 609 if (cpu_isar_feature(aa64_hcx, cpu)) { 610 env->cp15.scr_el3 |= SCR_HXEN; 611 } 612 if (cpu_isar_feature(aa64_fgt, cpu)) { 613 env->cp15.scr_el3 |= SCR_FGTEN; 614 } 615 } 616 617 if (target_el == 2) { 618 /* If the guest is at EL2 then Linux expects the HVC insn to work */ 619 env->cp15.scr_el3 |= SCR_HCE; 620 } 621 622 /* Put CPU into non-secure state */ 623 env->cp15.scr_el3 |= SCR_NS; 624 /* Set NSACR.{CP11,CP10} so NS can access the FPU */ 625 env->cp15.nsacr |= 3 << 10; 626 } 627 628 if (have_el2 && target_el < 2) { 629 /* Set EL2 state so code can run at EL1. */ 630 if (env->aarch64) { 631 env->cp15.hcr_el2 |= HCR_RW; 632 } 633 } 634 635 /* Set the CPU to the desired state */ 636 if (env->aarch64) { 637 env->pstate = aarch64_pstate_mode(target_el, true); 638 } else { 639 static const uint32_t mode_for_el[] = { 640 0, 641 ARM_CPU_MODE_SVC, 642 ARM_CPU_MODE_HYP, 643 ARM_CPU_MODE_SVC, 644 }; 645 646 cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw); 647 } 648 } 649 650 651 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 652 653 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 654 unsigned int target_el, 655 unsigned int cur_el, bool secure, 656 uint64_t hcr_el2) 657 { 658 CPUARMState *env = cpu_env(cs); 659 bool pstate_unmasked; 660 bool unmasked = false; 661 662 /* 663 * Don't take exceptions if they target a lower EL. 664 * This check should catch any exceptions that would not be taken 665 * but left pending. 666 */ 667 if (cur_el > target_el) { 668 return false; 669 } 670 671 switch (excp_idx) { 672 case EXCP_FIQ: 673 pstate_unmasked = !(env->daif & PSTATE_F); 674 break; 675 676 case EXCP_IRQ: 677 pstate_unmasked = !(env->daif & PSTATE_I); 678 break; 679 680 case EXCP_VFIQ: 681 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 682 /* VFIQs are only taken when hypervized. */ 683 return false; 684 } 685 return !(env->daif & PSTATE_F); 686 case EXCP_VIRQ: 687 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 688 /* VIRQs are only taken when hypervized. */ 689 return false; 690 } 691 return !(env->daif & PSTATE_I); 692 case EXCP_VSERR: 693 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 694 /* VIRQs are only taken when hypervized. */ 695 return false; 696 } 697 return !(env->daif & PSTATE_A); 698 default: 699 g_assert_not_reached(); 700 } 701 702 /* 703 * Use the target EL, current execution state and SCR/HCR settings to 704 * determine whether the corresponding CPSR bit is used to mask the 705 * interrupt. 706 */ 707 if ((target_el > cur_el) && (target_el != 1)) { 708 /* Exceptions targeting a higher EL may not be maskable */ 709 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 710 switch (target_el) { 711 case 2: 712 /* 713 * According to ARM DDI 0487H.a, an interrupt can be masked 714 * when HCR_E2H and HCR_TGE are both set regardless of the 715 * current Security state. Note that we need to revisit this 716 * part again once we need to support NMI. 717 */ 718 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 719 unmasked = true; 720 } 721 break; 722 case 3: 723 /* Interrupt cannot be masked when the target EL is 3 */ 724 unmasked = true; 725 break; 726 default: 727 g_assert_not_reached(); 728 } 729 } else { 730 /* 731 * The old 32-bit-only environment has a more complicated 732 * masking setup. HCR and SCR bits not only affect interrupt 733 * routing but also change the behaviour of masking. 734 */ 735 bool hcr, scr; 736 737 switch (excp_idx) { 738 case EXCP_FIQ: 739 /* 740 * If FIQs are routed to EL3 or EL2 then there are cases where 741 * we override the CPSR.F in determining if the exception is 742 * masked or not. If neither of these are set then we fall back 743 * to the CPSR.F setting otherwise we further assess the state 744 * below. 745 */ 746 hcr = hcr_el2 & HCR_FMO; 747 scr = (env->cp15.scr_el3 & SCR_FIQ); 748 749 /* 750 * When EL3 is 32-bit, the SCR.FW bit controls whether the 751 * CPSR.F bit masks FIQ interrupts when taken in non-secure 752 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 753 * when non-secure but only when FIQs are only routed to EL3. 754 */ 755 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 756 break; 757 case EXCP_IRQ: 758 /* 759 * When EL3 execution state is 32-bit, if HCR.IMO is set then 760 * we may override the CPSR.I masking when in non-secure state. 761 * The SCR.IRQ setting has already been taken into consideration 762 * when setting the target EL, so it does not have a further 763 * affect here. 764 */ 765 hcr = hcr_el2 & HCR_IMO; 766 scr = false; 767 break; 768 default: 769 g_assert_not_reached(); 770 } 771 772 if ((scr || hcr) && !secure) { 773 unmasked = true; 774 } 775 } 776 } 777 778 /* 779 * The PSTATE bits only mask the interrupt if we have not overridden the 780 * ability above. 781 */ 782 return unmasked || pstate_unmasked; 783 } 784 785 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 786 { 787 CPUClass *cc = CPU_GET_CLASS(cs); 788 CPUARMState *env = cpu_env(cs); 789 uint32_t cur_el = arm_current_el(env); 790 bool secure = arm_is_secure(env); 791 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 792 uint32_t target_el; 793 uint32_t excp_idx; 794 795 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 796 797 if (interrupt_request & CPU_INTERRUPT_FIQ) { 798 excp_idx = EXCP_FIQ; 799 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 800 if (arm_excp_unmasked(cs, excp_idx, target_el, 801 cur_el, secure, hcr_el2)) { 802 goto found; 803 } 804 } 805 if (interrupt_request & CPU_INTERRUPT_HARD) { 806 excp_idx = EXCP_IRQ; 807 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 808 if (arm_excp_unmasked(cs, excp_idx, target_el, 809 cur_el, secure, hcr_el2)) { 810 goto found; 811 } 812 } 813 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 814 excp_idx = EXCP_VIRQ; 815 target_el = 1; 816 if (arm_excp_unmasked(cs, excp_idx, target_el, 817 cur_el, secure, hcr_el2)) { 818 goto found; 819 } 820 } 821 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 822 excp_idx = EXCP_VFIQ; 823 target_el = 1; 824 if (arm_excp_unmasked(cs, excp_idx, target_el, 825 cur_el, secure, hcr_el2)) { 826 goto found; 827 } 828 } 829 if (interrupt_request & CPU_INTERRUPT_VSERR) { 830 excp_idx = EXCP_VSERR; 831 target_el = 1; 832 if (arm_excp_unmasked(cs, excp_idx, target_el, 833 cur_el, secure, hcr_el2)) { 834 /* Taking a virtual abort clears HCR_EL2.VSE */ 835 env->cp15.hcr_el2 &= ~HCR_VSE; 836 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 837 goto found; 838 } 839 } 840 return false; 841 842 found: 843 cs->exception_index = excp_idx; 844 env->exception.target_el = target_el; 845 cc->tcg_ops->do_interrupt(cs); 846 return true; 847 } 848 849 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ 850 851 void arm_cpu_update_virq(ARMCPU *cpu) 852 { 853 /* 854 * Update the interrupt level for VIRQ, which is the logical OR of 855 * the HCR_EL2.VI bit and the input line level from the GIC. 856 */ 857 CPUARMState *env = &cpu->env; 858 CPUState *cs = CPU(cpu); 859 860 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 861 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 862 863 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 864 if (new_state) { 865 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 866 } else { 867 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 868 } 869 } 870 } 871 872 void arm_cpu_update_vfiq(ARMCPU *cpu) 873 { 874 /* 875 * Update the interrupt level for VFIQ, which is the logical OR of 876 * the HCR_EL2.VF bit and the input line level from the GIC. 877 */ 878 CPUARMState *env = &cpu->env; 879 CPUState *cs = CPU(cpu); 880 881 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 882 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 883 884 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 885 if (new_state) { 886 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 887 } else { 888 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 889 } 890 } 891 } 892 893 void arm_cpu_update_vserr(ARMCPU *cpu) 894 { 895 /* 896 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 897 */ 898 CPUARMState *env = &cpu->env; 899 CPUState *cs = CPU(cpu); 900 901 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 902 903 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 904 if (new_state) { 905 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 906 } else { 907 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 908 } 909 } 910 } 911 912 #ifndef CONFIG_USER_ONLY 913 static void arm_cpu_set_irq(void *opaque, int irq, int level) 914 { 915 ARMCPU *cpu = opaque; 916 CPUARMState *env = &cpu->env; 917 CPUState *cs = CPU(cpu); 918 static const int mask[] = { 919 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 920 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 921 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 922 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 923 }; 924 925 if (!arm_feature(env, ARM_FEATURE_EL2) && 926 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 927 /* 928 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 929 * have EL2 support we don't care. (Unless the guest is doing something 930 * silly this will only be calls saying "level is still 0".) 931 */ 932 return; 933 } 934 935 if (level) { 936 env->irq_line_state |= mask[irq]; 937 } else { 938 env->irq_line_state &= ~mask[irq]; 939 } 940 941 switch (irq) { 942 case ARM_CPU_VIRQ: 943 arm_cpu_update_virq(cpu); 944 break; 945 case ARM_CPU_VFIQ: 946 arm_cpu_update_vfiq(cpu); 947 break; 948 case ARM_CPU_IRQ: 949 case ARM_CPU_FIQ: 950 if (level) { 951 cpu_interrupt(cs, mask[irq]); 952 } else { 953 cpu_reset_interrupt(cs, mask[irq]); 954 } 955 break; 956 default: 957 g_assert_not_reached(); 958 } 959 } 960 961 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 962 { 963 #ifdef CONFIG_KVM 964 ARMCPU *cpu = opaque; 965 CPUARMState *env = &cpu->env; 966 CPUState *cs = CPU(cpu); 967 uint32_t linestate_bit; 968 int irq_id; 969 970 switch (irq) { 971 case ARM_CPU_IRQ: 972 irq_id = KVM_ARM_IRQ_CPU_IRQ; 973 linestate_bit = CPU_INTERRUPT_HARD; 974 break; 975 case ARM_CPU_FIQ: 976 irq_id = KVM_ARM_IRQ_CPU_FIQ; 977 linestate_bit = CPU_INTERRUPT_FIQ; 978 break; 979 default: 980 g_assert_not_reached(); 981 } 982 983 if (level) { 984 env->irq_line_state |= linestate_bit; 985 } else { 986 env->irq_line_state &= ~linestate_bit; 987 } 988 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 989 #endif 990 } 991 992 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 993 { 994 ARMCPU *cpu = ARM_CPU(cs); 995 CPUARMState *env = &cpu->env; 996 997 cpu_synchronize_state(cs); 998 return arm_cpu_data_is_big_endian(env); 999 } 1000 1001 #endif 1002 1003 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 1004 { 1005 ARMCPU *ac = ARM_CPU(cpu); 1006 CPUARMState *env = &ac->env; 1007 bool sctlr_b; 1008 1009 if (is_a64(env)) { 1010 info->cap_arch = CS_ARCH_ARM64; 1011 info->cap_insn_unit = 4; 1012 info->cap_insn_split = 4; 1013 } else { 1014 int cap_mode; 1015 if (env->thumb) { 1016 info->cap_insn_unit = 2; 1017 info->cap_insn_split = 4; 1018 cap_mode = CS_MODE_THUMB; 1019 } else { 1020 info->cap_insn_unit = 4; 1021 info->cap_insn_split = 4; 1022 cap_mode = CS_MODE_ARM; 1023 } 1024 if (arm_feature(env, ARM_FEATURE_V8)) { 1025 cap_mode |= CS_MODE_V8; 1026 } 1027 if (arm_feature(env, ARM_FEATURE_M)) { 1028 cap_mode |= CS_MODE_MCLASS; 1029 } 1030 info->cap_arch = CS_ARCH_ARM; 1031 info->cap_mode = cap_mode; 1032 } 1033 1034 sctlr_b = arm_sctlr_b(env); 1035 if (bswap_code(sctlr_b)) { 1036 #if TARGET_BIG_ENDIAN 1037 info->endian = BFD_ENDIAN_LITTLE; 1038 #else 1039 info->endian = BFD_ENDIAN_BIG; 1040 #endif 1041 } 1042 info->flags &= ~INSN_ARM_BE32; 1043 #ifndef CONFIG_USER_ONLY 1044 if (sctlr_b) { 1045 info->flags |= INSN_ARM_BE32; 1046 } 1047 #endif 1048 } 1049 1050 #ifdef TARGET_AARCH64 1051 1052 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1053 { 1054 ARMCPU *cpu = ARM_CPU(cs); 1055 CPUARMState *env = &cpu->env; 1056 uint32_t psr = pstate_read(env); 1057 int i, j; 1058 int el = arm_current_el(env); 1059 const char *ns_status; 1060 bool sve; 1061 1062 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 1063 for (i = 0; i < 32; i++) { 1064 if (i == 31) { 1065 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 1066 } else { 1067 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 1068 (i + 2) % 3 ? " " : "\n"); 1069 } 1070 } 1071 1072 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 1073 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1074 } else { 1075 ns_status = ""; 1076 } 1077 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 1078 psr, 1079 psr & PSTATE_N ? 'N' : '-', 1080 psr & PSTATE_Z ? 'Z' : '-', 1081 psr & PSTATE_C ? 'C' : '-', 1082 psr & PSTATE_V ? 'V' : '-', 1083 ns_status, 1084 el, 1085 psr & PSTATE_SP ? 'h' : 't'); 1086 1087 if (cpu_isar_feature(aa64_sme, cpu)) { 1088 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", 1089 env->svcr, 1090 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), 1091 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); 1092 } 1093 if (cpu_isar_feature(aa64_bti, cpu)) { 1094 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 1095 } 1096 if (!(flags & CPU_DUMP_FPU)) { 1097 qemu_fprintf(f, "\n"); 1098 return; 1099 } 1100 if (fp_exception_el(env, el) != 0) { 1101 qemu_fprintf(f, " FPU disabled\n"); 1102 return; 1103 } 1104 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 1105 vfp_get_fpcr(env), vfp_get_fpsr(env)); 1106 1107 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { 1108 sve = sme_exception_el(env, el) == 0; 1109 } else if (cpu_isar_feature(aa64_sve, cpu)) { 1110 sve = sve_exception_el(env, el) == 0; 1111 } else { 1112 sve = false; 1113 } 1114 1115 if (sve) { 1116 int zcr_len = sve_vqm1_for_el(env, el); 1117 1118 for (i = 0; i <= FFR_PRED_NUM; i++) { 1119 bool eol; 1120 if (i == FFR_PRED_NUM) { 1121 qemu_fprintf(f, "FFR="); 1122 /* It's last, so end the line. */ 1123 eol = true; 1124 } else { 1125 qemu_fprintf(f, "P%02d=", i); 1126 switch (zcr_len) { 1127 case 0: 1128 eol = i % 8 == 7; 1129 break; 1130 case 1: 1131 eol = i % 6 == 5; 1132 break; 1133 case 2: 1134 case 3: 1135 eol = i % 3 == 2; 1136 break; 1137 default: 1138 /* More than one quadword per predicate. */ 1139 eol = true; 1140 break; 1141 } 1142 } 1143 for (j = zcr_len / 4; j >= 0; j--) { 1144 int digits; 1145 if (j * 4 + 4 <= zcr_len + 1) { 1146 digits = 16; 1147 } else { 1148 digits = (zcr_len % 4 + 1) * 4; 1149 } 1150 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 1151 env->vfp.pregs[i].p[j], 1152 j ? ":" : eol ? "\n" : " "); 1153 } 1154 } 1155 1156 if (zcr_len == 0) { 1157 /* 1158 * With vl=16, there are only 37 columns per register, 1159 * so output two registers per line. 1160 */ 1161 for (i = 0; i < 32; i++) { 1162 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1163 i, env->vfp.zregs[i].d[1], 1164 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 1165 } 1166 } else { 1167 for (i = 0; i < 32; i++) { 1168 qemu_fprintf(f, "Z%02d=", i); 1169 for (j = zcr_len; j >= 0; j--) { 1170 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 1171 env->vfp.zregs[i].d[j * 2 + 1], 1172 env->vfp.zregs[i].d[j * 2 + 0], 1173 j ? ":" : "\n"); 1174 } 1175 } 1176 } 1177 } else { 1178 for (i = 0; i < 32; i++) { 1179 uint64_t *q = aa64_vfp_qreg(env, i); 1180 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1181 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1182 } 1183 } 1184 1185 if (cpu_isar_feature(aa64_sme, cpu) && 1186 FIELD_EX64(env->svcr, SVCR, ZA) && 1187 sme_exception_el(env, el) == 0) { 1188 int zcr_len = sve_vqm1_for_el_sm(env, el, true); 1189 int svl = (zcr_len + 1) * 16; 1190 int svl_lg10 = svl < 100 ? 2 : 3; 1191 1192 for (i = 0; i < svl; i++) { 1193 qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i); 1194 for (j = zcr_len; j >= 0; --j) { 1195 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c", 1196 env->zarray[i].d[2 * j + 1], 1197 env->zarray[i].d[2 * j], 1198 j ? ':' : '\n'); 1199 } 1200 } 1201 } 1202 } 1203 1204 #else 1205 1206 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1207 { 1208 g_assert_not_reached(); 1209 } 1210 1211 #endif 1212 1213 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1214 { 1215 ARMCPU *cpu = ARM_CPU(cs); 1216 CPUARMState *env = &cpu->env; 1217 int i; 1218 1219 if (is_a64(env)) { 1220 aarch64_cpu_dump_state(cs, f, flags); 1221 return; 1222 } 1223 1224 for (i = 0; i < 16; i++) { 1225 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1226 if ((i % 4) == 3) { 1227 qemu_fprintf(f, "\n"); 1228 } else { 1229 qemu_fprintf(f, " "); 1230 } 1231 } 1232 1233 if (arm_feature(env, ARM_FEATURE_M)) { 1234 uint32_t xpsr = xpsr_read(env); 1235 const char *mode; 1236 const char *ns_status = ""; 1237 1238 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1239 ns_status = env->v7m.secure ? "S " : "NS "; 1240 } 1241 1242 if (xpsr & XPSR_EXCP) { 1243 mode = "handler"; 1244 } else { 1245 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1246 mode = "unpriv-thread"; 1247 } else { 1248 mode = "priv-thread"; 1249 } 1250 } 1251 1252 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1253 xpsr, 1254 xpsr & XPSR_N ? 'N' : '-', 1255 xpsr & XPSR_Z ? 'Z' : '-', 1256 xpsr & XPSR_C ? 'C' : '-', 1257 xpsr & XPSR_V ? 'V' : '-', 1258 xpsr & XPSR_T ? 'T' : 'A', 1259 ns_status, 1260 mode); 1261 } else { 1262 uint32_t psr = cpsr_read(env); 1263 const char *ns_status = ""; 1264 1265 if (arm_feature(env, ARM_FEATURE_EL3) && 1266 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1267 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1268 } 1269 1270 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1271 psr, 1272 psr & CPSR_N ? 'N' : '-', 1273 psr & CPSR_Z ? 'Z' : '-', 1274 psr & CPSR_C ? 'C' : '-', 1275 psr & CPSR_V ? 'V' : '-', 1276 psr & CPSR_T ? 'T' : 'A', 1277 ns_status, 1278 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1279 } 1280 1281 if (flags & CPU_DUMP_FPU) { 1282 int numvfpregs = 0; 1283 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1284 numvfpregs = 32; 1285 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1286 numvfpregs = 16; 1287 } 1288 for (i = 0; i < numvfpregs; i++) { 1289 uint64_t v = *aa32_vfp_dreg(env, i); 1290 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1291 i * 2, (uint32_t)v, 1292 i * 2 + 1, (uint32_t)(v >> 32), 1293 i, v); 1294 } 1295 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1296 if (cpu_isar_feature(aa32_mve, cpu)) { 1297 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1298 } 1299 } 1300 } 1301 1302 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1303 { 1304 uint32_t Aff1 = idx / clustersz; 1305 uint32_t Aff0 = idx % clustersz; 1306 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1307 } 1308 1309 static void arm_cpu_initfn(Object *obj) 1310 { 1311 ARMCPU *cpu = ARM_CPU(obj); 1312 1313 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1314 NULL, g_free); 1315 1316 QLIST_INIT(&cpu->pre_el_change_hooks); 1317 QLIST_INIT(&cpu->el_change_hooks); 1318 1319 #ifdef CONFIG_USER_ONLY 1320 # ifdef TARGET_AARCH64 1321 /* 1322 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. 1323 * These values were chosen to fit within the default signal frame. 1324 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, 1325 * and our corresponding cpu property. 1326 */ 1327 cpu->sve_default_vq = 4; 1328 cpu->sme_default_vq = 2; 1329 # endif 1330 #else 1331 /* Our inbound IRQ and FIQ lines */ 1332 if (kvm_enabled()) { 1333 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1334 * the same interface as non-KVM CPUs. 1335 */ 1336 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1337 } else { 1338 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1339 } 1340 1341 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1342 ARRAY_SIZE(cpu->gt_timer_outputs)); 1343 1344 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1345 "gicv3-maintenance-interrupt", 1); 1346 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1347 "pmu-interrupt", 1); 1348 #endif 1349 1350 /* DTB consumers generally don't in fact care what the 'compatible' 1351 * string is, so always provide some string and trust that a hypothetical 1352 * picky DTB consumer will also provide a helpful error message. 1353 */ 1354 cpu->dtb_compatible = "qemu,unknown"; 1355 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1356 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1357 1358 if (tcg_enabled() || hvf_enabled()) { 1359 /* TCG and HVF implement PSCI 1.1 */ 1360 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1361 } 1362 } 1363 1364 static Property arm_cpu_gt_cntfrq_property = 1365 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1366 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1367 1368 static Property arm_cpu_reset_cbar_property = 1369 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1370 1371 static Property arm_cpu_reset_hivecs_property = 1372 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1373 1374 #ifndef CONFIG_USER_ONLY 1375 static Property arm_cpu_has_el2_property = 1376 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1377 1378 static Property arm_cpu_has_el3_property = 1379 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1380 #endif 1381 1382 static Property arm_cpu_cfgend_property = 1383 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1384 1385 static Property arm_cpu_has_vfp_property = 1386 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1387 1388 static Property arm_cpu_has_vfp_d32_property = 1389 DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true); 1390 1391 static Property arm_cpu_has_neon_property = 1392 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1393 1394 static Property arm_cpu_has_dsp_property = 1395 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1396 1397 static Property arm_cpu_has_mpu_property = 1398 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1399 1400 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1401 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1402 * the right value for that particular CPU type, and we don't want 1403 * to override that with an incorrect constant value. 1404 */ 1405 static Property arm_cpu_pmsav7_dregion_property = 1406 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1407 pmsav7_dregion, 1408 qdev_prop_uint32, uint32_t); 1409 1410 static bool arm_get_pmu(Object *obj, Error **errp) 1411 { 1412 ARMCPU *cpu = ARM_CPU(obj); 1413 1414 return cpu->has_pmu; 1415 } 1416 1417 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1418 { 1419 ARMCPU *cpu = ARM_CPU(obj); 1420 1421 if (value) { 1422 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1423 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1424 return; 1425 } 1426 set_feature(&cpu->env, ARM_FEATURE_PMU); 1427 } else { 1428 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1429 } 1430 cpu->has_pmu = value; 1431 } 1432 1433 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1434 { 1435 /* 1436 * The exact approach to calculating guest ticks is: 1437 * 1438 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1439 * NANOSECONDS_PER_SECOND); 1440 * 1441 * We don't do that. Rather we intentionally use integer division 1442 * truncation below and in the caller for the conversion of host monotonic 1443 * time to guest ticks to provide the exact inverse for the semantics of 1444 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1445 * it loses precision when representing frequencies where 1446 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1447 * provide an exact inverse leads to scheduling timers with negative 1448 * periods, which in turn leads to sticky behaviour in the guest. 1449 * 1450 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1451 * cannot become zero. 1452 */ 1453 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1454 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1455 } 1456 1457 static void arm_cpu_propagate_feature_implications(ARMCPU *cpu) 1458 { 1459 CPUARMState *env = &cpu->env; 1460 bool no_aa32 = false; 1461 1462 /* 1463 * Some features automatically imply others: set the feature 1464 * bits explicitly for these cases. 1465 */ 1466 1467 if (arm_feature(env, ARM_FEATURE_M)) { 1468 set_feature(env, ARM_FEATURE_PMSA); 1469 } 1470 1471 if (arm_feature(env, ARM_FEATURE_V8)) { 1472 if (arm_feature(env, ARM_FEATURE_M)) { 1473 set_feature(env, ARM_FEATURE_V7); 1474 } else { 1475 set_feature(env, ARM_FEATURE_V7VE); 1476 } 1477 } 1478 1479 /* 1480 * There exist AArch64 cpus without AArch32 support. When KVM 1481 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1482 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1483 * As a general principle, we also do not make ID register 1484 * consistency checks anywhere unless using TCG, because only 1485 * for TCG would a consistency-check failure be a QEMU bug. 1486 */ 1487 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1488 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1489 } 1490 1491 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1492 /* 1493 * v7 Virtualization Extensions. In real hardware this implies 1494 * EL2 and also the presence of the Security Extensions. 1495 * For QEMU, for backwards-compatibility we implement some 1496 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1497 * include the various other features that V7VE implies. 1498 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1499 * Security Extensions is ARM_FEATURE_EL3. 1500 */ 1501 assert(!tcg_enabled() || no_aa32 || 1502 cpu_isar_feature(aa32_arm_div, cpu)); 1503 set_feature(env, ARM_FEATURE_LPAE); 1504 set_feature(env, ARM_FEATURE_V7); 1505 } 1506 if (arm_feature(env, ARM_FEATURE_V7)) { 1507 set_feature(env, ARM_FEATURE_VAPA); 1508 set_feature(env, ARM_FEATURE_THUMB2); 1509 set_feature(env, ARM_FEATURE_MPIDR); 1510 if (!arm_feature(env, ARM_FEATURE_M)) { 1511 set_feature(env, ARM_FEATURE_V6K); 1512 } else { 1513 set_feature(env, ARM_FEATURE_V6); 1514 } 1515 1516 /* 1517 * Always define VBAR for V7 CPUs even if it doesn't exist in 1518 * non-EL3 configs. This is needed by some legacy boards. 1519 */ 1520 set_feature(env, ARM_FEATURE_VBAR); 1521 } 1522 if (arm_feature(env, ARM_FEATURE_V6K)) { 1523 set_feature(env, ARM_FEATURE_V6); 1524 set_feature(env, ARM_FEATURE_MVFR); 1525 } 1526 if (arm_feature(env, ARM_FEATURE_V6)) { 1527 set_feature(env, ARM_FEATURE_V5); 1528 if (!arm_feature(env, ARM_FEATURE_M)) { 1529 assert(!tcg_enabled() || no_aa32 || 1530 cpu_isar_feature(aa32_jazelle, cpu)); 1531 set_feature(env, ARM_FEATURE_AUXCR); 1532 } 1533 } 1534 if (arm_feature(env, ARM_FEATURE_V5)) { 1535 set_feature(env, ARM_FEATURE_V4T); 1536 } 1537 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1538 set_feature(env, ARM_FEATURE_V7MP); 1539 } 1540 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1541 set_feature(env, ARM_FEATURE_CBAR); 1542 } 1543 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1544 !arm_feature(env, ARM_FEATURE_M)) { 1545 set_feature(env, ARM_FEATURE_THUMB_DSP); 1546 } 1547 } 1548 1549 void arm_cpu_post_init(Object *obj) 1550 { 1551 ARMCPU *cpu = ARM_CPU(obj); 1552 1553 /* 1554 * Some features imply others. Figure this out now, because we 1555 * are going to look at the feature bits in deciding which 1556 * properties to add. 1557 */ 1558 arm_cpu_propagate_feature_implications(cpu); 1559 1560 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1561 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1562 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1563 } 1564 1565 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1566 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1567 } 1568 1569 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { 1570 object_property_add_uint64_ptr(obj, "rvbar", 1571 &cpu->rvbar_prop, 1572 OBJ_PROP_FLAG_READWRITE); 1573 } 1574 1575 #ifndef CONFIG_USER_ONLY 1576 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1577 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1578 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1579 */ 1580 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1581 1582 object_property_add_link(obj, "secure-memory", 1583 TYPE_MEMORY_REGION, 1584 (Object **)&cpu->secure_memory, 1585 qdev_prop_allow_set_link_before_realize, 1586 OBJ_PROP_LINK_STRONG); 1587 } 1588 1589 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1590 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1591 } 1592 #endif 1593 1594 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1595 cpu->has_pmu = true; 1596 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1597 } 1598 1599 /* 1600 * Allow user to turn off VFP and Neon support, but only for TCG -- 1601 * KVM does not currently allow us to lie to the guest about its 1602 * ID/feature registers, so the guest always sees what the host has. 1603 */ 1604 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1605 if (cpu_isar_feature(aa64_fp_simd, cpu)) { 1606 cpu->has_vfp = true; 1607 cpu->has_vfp_d32 = true; 1608 if (tcg_enabled() || qtest_enabled()) { 1609 qdev_property_add_static(DEVICE(obj), 1610 &arm_cpu_has_vfp_property); 1611 } 1612 } 1613 } else if (cpu_isar_feature(aa32_vfp, cpu)) { 1614 cpu->has_vfp = true; 1615 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1616 cpu->has_vfp_d32 = true; 1617 /* 1618 * The permitted values of the SIMDReg bits [3:0] on 1619 * Armv8-A are either 0b0000 and 0b0010. On such CPUs, 1620 * make sure that has_vfp_d32 can not be set to false. 1621 */ 1622 if ((tcg_enabled() || qtest_enabled()) 1623 && !(arm_feature(&cpu->env, ARM_FEATURE_V8) 1624 && !arm_feature(&cpu->env, ARM_FEATURE_M))) { 1625 qdev_property_add_static(DEVICE(obj), 1626 &arm_cpu_has_vfp_d32_property); 1627 } 1628 } 1629 } 1630 1631 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1632 cpu->has_neon = true; 1633 if (!kvm_enabled()) { 1634 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1635 } 1636 } 1637 1638 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1639 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1640 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1641 } 1642 1643 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1644 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1645 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1646 qdev_property_add_static(DEVICE(obj), 1647 &arm_cpu_pmsav7_dregion_property); 1648 } 1649 } 1650 1651 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1652 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1653 qdev_prop_allow_set_link_before_realize, 1654 OBJ_PROP_LINK_STRONG); 1655 /* 1656 * M profile: initial value of the Secure VTOR. We can't just use 1657 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1658 * the property to be set after realize. 1659 */ 1660 object_property_add_uint32_ptr(obj, "init-svtor", 1661 &cpu->init_svtor, 1662 OBJ_PROP_FLAG_READWRITE); 1663 } 1664 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1665 /* 1666 * Initial value of the NS VTOR (for cores without the Security 1667 * extension, this is the only VTOR) 1668 */ 1669 object_property_add_uint32_ptr(obj, "init-nsvtor", 1670 &cpu->init_nsvtor, 1671 OBJ_PROP_FLAG_READWRITE); 1672 } 1673 1674 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1675 object_property_add_uint32_ptr(obj, "psci-conduit", 1676 &cpu->psci_conduit, 1677 OBJ_PROP_FLAG_READWRITE); 1678 1679 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1680 1681 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1682 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1683 } 1684 1685 if (kvm_enabled()) { 1686 kvm_arm_add_vcpu_properties(obj); 1687 } 1688 1689 #ifndef CONFIG_USER_ONLY 1690 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1691 cpu_isar_feature(aa64_mte, cpu)) { 1692 object_property_add_link(obj, "tag-memory", 1693 TYPE_MEMORY_REGION, 1694 (Object **)&cpu->tag_memory, 1695 qdev_prop_allow_set_link_before_realize, 1696 OBJ_PROP_LINK_STRONG); 1697 1698 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1699 object_property_add_link(obj, "secure-tag-memory", 1700 TYPE_MEMORY_REGION, 1701 (Object **)&cpu->secure_tag_memory, 1702 qdev_prop_allow_set_link_before_realize, 1703 OBJ_PROP_LINK_STRONG); 1704 } 1705 } 1706 #endif 1707 } 1708 1709 static void arm_cpu_finalizefn(Object *obj) 1710 { 1711 ARMCPU *cpu = ARM_CPU(obj); 1712 ARMELChangeHook *hook, *next; 1713 1714 g_hash_table_destroy(cpu->cp_regs); 1715 1716 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1717 QLIST_REMOVE(hook, node); 1718 g_free(hook); 1719 } 1720 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1721 QLIST_REMOVE(hook, node); 1722 g_free(hook); 1723 } 1724 #ifndef CONFIG_USER_ONLY 1725 if (cpu->pmu_timer) { 1726 timer_free(cpu->pmu_timer); 1727 } 1728 #endif 1729 } 1730 1731 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1732 { 1733 Error *local_err = NULL; 1734 1735 #ifdef TARGET_AARCH64 1736 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1737 arm_cpu_sve_finalize(cpu, &local_err); 1738 if (local_err != NULL) { 1739 error_propagate(errp, local_err); 1740 return; 1741 } 1742 1743 arm_cpu_sme_finalize(cpu, &local_err); 1744 if (local_err != NULL) { 1745 error_propagate(errp, local_err); 1746 return; 1747 } 1748 1749 arm_cpu_pauth_finalize(cpu, &local_err); 1750 if (local_err != NULL) { 1751 error_propagate(errp, local_err); 1752 return; 1753 } 1754 1755 arm_cpu_lpa2_finalize(cpu, &local_err); 1756 if (local_err != NULL) { 1757 error_propagate(errp, local_err); 1758 return; 1759 } 1760 } 1761 #endif 1762 1763 if (kvm_enabled()) { 1764 kvm_arm_steal_time_finalize(cpu, &local_err); 1765 if (local_err != NULL) { 1766 error_propagate(errp, local_err); 1767 return; 1768 } 1769 } 1770 } 1771 1772 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1773 { 1774 CPUState *cs = CPU(dev); 1775 ARMCPU *cpu = ARM_CPU(dev); 1776 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1777 CPUARMState *env = &cpu->env; 1778 int pagebits; 1779 Error *local_err = NULL; 1780 1781 /* Use pc-relative instructions in system-mode */ 1782 #ifndef CONFIG_USER_ONLY 1783 cs->tcg_cflags |= CF_PCREL; 1784 #endif 1785 1786 /* If we needed to query the host kernel for the CPU features 1787 * then it's possible that might have failed in the initfn, but 1788 * this is the first point where we can report it. 1789 */ 1790 if (cpu->host_cpu_probe_failed) { 1791 if (!kvm_enabled() && !hvf_enabled()) { 1792 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1793 } else { 1794 error_setg(errp, "Failed to retrieve host CPU features"); 1795 } 1796 return; 1797 } 1798 1799 #ifndef CONFIG_USER_ONLY 1800 /* The NVIC and M-profile CPU are two halves of a single piece of 1801 * hardware; trying to use one without the other is a command line 1802 * error and will result in segfaults if not caught here. 1803 */ 1804 if (arm_feature(env, ARM_FEATURE_M)) { 1805 if (!env->nvic) { 1806 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1807 return; 1808 } 1809 } else { 1810 if (env->nvic) { 1811 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1812 return; 1813 } 1814 } 1815 1816 if (!tcg_enabled() && !qtest_enabled()) { 1817 /* 1818 * We assume that no accelerator except TCG (and the "not really an 1819 * accelerator" qtest) can handle these features, because Arm hardware 1820 * virtualization can't virtualize them. 1821 * 1822 * Catch all the cases which might cause us to create more than one 1823 * address space for the CPU (otherwise we will assert() later in 1824 * cpu_address_space_init()). 1825 */ 1826 if (arm_feature(env, ARM_FEATURE_M)) { 1827 error_setg(errp, 1828 "Cannot enable %s when using an M-profile guest CPU", 1829 current_accel_name()); 1830 return; 1831 } 1832 if (cpu->has_el3) { 1833 error_setg(errp, 1834 "Cannot enable %s when guest CPU has EL3 enabled", 1835 current_accel_name()); 1836 return; 1837 } 1838 if (cpu->tag_memory) { 1839 error_setg(errp, 1840 "Cannot enable %s when guest CPUs has MTE enabled", 1841 current_accel_name()); 1842 return; 1843 } 1844 } 1845 1846 { 1847 uint64_t scale; 1848 1849 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1850 if (!cpu->gt_cntfrq_hz) { 1851 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1852 cpu->gt_cntfrq_hz); 1853 return; 1854 } 1855 scale = gt_cntfrq_period_ns(cpu); 1856 } else { 1857 scale = GTIMER_SCALE; 1858 } 1859 1860 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1861 arm_gt_ptimer_cb, cpu); 1862 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1863 arm_gt_vtimer_cb, cpu); 1864 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1865 arm_gt_htimer_cb, cpu); 1866 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1867 arm_gt_stimer_cb, cpu); 1868 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1869 arm_gt_hvtimer_cb, cpu); 1870 } 1871 #endif 1872 1873 cpu_exec_realizefn(cs, &local_err); 1874 if (local_err != NULL) { 1875 error_propagate(errp, local_err); 1876 return; 1877 } 1878 1879 arm_cpu_finalize_features(cpu, &local_err); 1880 if (local_err != NULL) { 1881 error_propagate(errp, local_err); 1882 return; 1883 } 1884 1885 #ifdef CONFIG_USER_ONLY 1886 /* 1887 * User mode relies on IC IVAU instructions to catch modification of 1888 * dual-mapped code. 1889 * 1890 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses 1891 * IC IVAU even if the emulated processor does not normally require it. 1892 */ 1893 cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0); 1894 #endif 1895 1896 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1897 cpu->has_vfp != cpu->has_neon) { 1898 /* 1899 * This is an architectural requirement for AArch64; AArch32 is 1900 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1901 */ 1902 error_setg(errp, 1903 "AArch64 CPUs must have both VFP and Neon or neither"); 1904 return; 1905 } 1906 1907 if (cpu->has_vfp_d32 != cpu->has_neon) { 1908 error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither"); 1909 return; 1910 } 1911 1912 if (!cpu->has_vfp_d32) { 1913 uint32_t u; 1914 1915 u = cpu->isar.mvfr0; 1916 u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */ 1917 cpu->isar.mvfr0 = u; 1918 } 1919 1920 if (!cpu->has_vfp) { 1921 uint64_t t; 1922 uint32_t u; 1923 1924 t = cpu->isar.id_aa64isar1; 1925 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1926 cpu->isar.id_aa64isar1 = t; 1927 1928 t = cpu->isar.id_aa64pfr0; 1929 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1930 cpu->isar.id_aa64pfr0 = t; 1931 1932 u = cpu->isar.id_isar6; 1933 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1934 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1935 cpu->isar.id_isar6 = u; 1936 1937 u = cpu->isar.mvfr0; 1938 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1939 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1940 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1941 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1942 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1943 if (!arm_feature(env, ARM_FEATURE_M)) { 1944 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1945 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1946 } 1947 cpu->isar.mvfr0 = u; 1948 1949 u = cpu->isar.mvfr1; 1950 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1951 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1952 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1953 if (arm_feature(env, ARM_FEATURE_M)) { 1954 u = FIELD_DP32(u, MVFR1, FP16, 0); 1955 } 1956 cpu->isar.mvfr1 = u; 1957 1958 u = cpu->isar.mvfr2; 1959 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1960 cpu->isar.mvfr2 = u; 1961 } 1962 1963 if (!cpu->has_neon) { 1964 uint64_t t; 1965 uint32_t u; 1966 1967 unset_feature(env, ARM_FEATURE_NEON); 1968 1969 t = cpu->isar.id_aa64isar0; 1970 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 1971 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 1972 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 1973 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 1974 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 1975 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 1976 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1977 cpu->isar.id_aa64isar0 = t; 1978 1979 t = cpu->isar.id_aa64isar1; 1980 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1981 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 1982 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1983 cpu->isar.id_aa64isar1 = t; 1984 1985 t = cpu->isar.id_aa64pfr0; 1986 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1987 cpu->isar.id_aa64pfr0 = t; 1988 1989 u = cpu->isar.id_isar5; 1990 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 1991 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 1992 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 1993 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1994 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1995 cpu->isar.id_isar5 = u; 1996 1997 u = cpu->isar.id_isar6; 1998 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1999 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 2000 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 2001 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 2002 cpu->isar.id_isar6 = u; 2003 2004 if (!arm_feature(env, ARM_FEATURE_M)) { 2005 u = cpu->isar.mvfr1; 2006 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 2007 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 2008 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 2009 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 2010 cpu->isar.mvfr1 = u; 2011 2012 u = cpu->isar.mvfr2; 2013 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 2014 cpu->isar.mvfr2 = u; 2015 } 2016 } 2017 2018 if (!cpu->has_neon && !cpu->has_vfp) { 2019 uint64_t t; 2020 uint32_t u; 2021 2022 t = cpu->isar.id_aa64isar0; 2023 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 2024 cpu->isar.id_aa64isar0 = t; 2025 2026 t = cpu->isar.id_aa64isar1; 2027 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 2028 cpu->isar.id_aa64isar1 = t; 2029 2030 u = cpu->isar.mvfr0; 2031 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 2032 cpu->isar.mvfr0 = u; 2033 2034 /* Despite the name, this field covers both VFP and Neon */ 2035 u = cpu->isar.mvfr1; 2036 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 2037 cpu->isar.mvfr1 = u; 2038 } 2039 2040 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 2041 uint32_t u; 2042 2043 unset_feature(env, ARM_FEATURE_THUMB_DSP); 2044 2045 u = cpu->isar.id_isar1; 2046 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 2047 cpu->isar.id_isar1 = u; 2048 2049 u = cpu->isar.id_isar2; 2050 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 2051 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 2052 cpu->isar.id_isar2 = u; 2053 2054 u = cpu->isar.id_isar3; 2055 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 2056 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 2057 cpu->isar.id_isar3 = u; 2058 } 2059 2060 2061 /* 2062 * We rely on no XScale CPU having VFP so we can use the same bits in the 2063 * TB flags field for VECSTRIDE and XSCALE_CPAR. 2064 */ 2065 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 2066 !cpu_isar_feature(aa32_vfp_simd, cpu) || 2067 !arm_feature(env, ARM_FEATURE_XSCALE)); 2068 2069 if (arm_feature(env, ARM_FEATURE_V7) && 2070 !arm_feature(env, ARM_FEATURE_M) && 2071 !arm_feature(env, ARM_FEATURE_PMSA)) { 2072 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 2073 * can use 4K pages. 2074 */ 2075 pagebits = 12; 2076 } else { 2077 /* For CPUs which might have tiny 1K pages, or which have an 2078 * MPU and might have small region sizes, stick with 1K pages. 2079 */ 2080 pagebits = 10; 2081 } 2082 if (!set_preferred_target_page_bits(pagebits)) { 2083 /* This can only ever happen for hotplugging a CPU, or if 2084 * the board code incorrectly creates a CPU which it has 2085 * promised via minimum_page_size that it will not. 2086 */ 2087 error_setg(errp, "This CPU requires a smaller page size than the " 2088 "system is using"); 2089 return; 2090 } 2091 2092 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 2093 * We don't support setting cluster ID ([16..23]) (known as Aff2 2094 * in later ARM ARM versions), or any of the higher affinity level fields, 2095 * so these bits always RAZ. 2096 */ 2097 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 2098 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 2099 ARM_DEFAULT_CPUS_PER_CLUSTER); 2100 } 2101 2102 if (cpu->reset_hivecs) { 2103 cpu->reset_sctlr |= (1 << 13); 2104 } 2105 2106 if (cpu->cfgend) { 2107 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 2108 cpu->reset_sctlr |= SCTLR_EE; 2109 } else { 2110 cpu->reset_sctlr |= SCTLR_B; 2111 } 2112 } 2113 2114 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 2115 /* If the has_el3 CPU property is disabled then we need to disable the 2116 * feature. 2117 */ 2118 unset_feature(env, ARM_FEATURE_EL3); 2119 2120 /* 2121 * Disable the security extension feature bits in the processor 2122 * feature registers as well. 2123 */ 2124 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); 2125 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); 2126 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2127 ID_AA64PFR0, EL3, 0); 2128 2129 /* Disable the realm management extension, which requires EL3. */ 2130 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2131 ID_AA64PFR0, RME, 0); 2132 } 2133 2134 if (!cpu->has_el2) { 2135 unset_feature(env, ARM_FEATURE_EL2); 2136 } 2137 2138 if (!cpu->has_pmu) { 2139 unset_feature(env, ARM_FEATURE_PMU); 2140 } 2141 if (arm_feature(env, ARM_FEATURE_PMU)) { 2142 pmu_init(cpu); 2143 2144 if (!kvm_enabled()) { 2145 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 2146 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 2147 } 2148 2149 #ifndef CONFIG_USER_ONLY 2150 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 2151 cpu); 2152 #endif 2153 } else { 2154 cpu->isar.id_aa64dfr0 = 2155 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 2156 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 2157 cpu->pmceid0 = 0; 2158 cpu->pmceid1 = 0; 2159 } 2160 2161 if (!arm_feature(env, ARM_FEATURE_EL2)) { 2162 /* 2163 * Disable the hypervisor feature bits in the processor feature 2164 * registers if we don't have EL2. 2165 */ 2166 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 2167 ID_AA64PFR0, EL2, 0); 2168 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, 2169 ID_PFR1, VIRTUALIZATION, 0); 2170 } 2171 2172 if (cpu_isar_feature(aa64_mte, cpu)) { 2173 /* 2174 * The architectural range of GM blocksize is 2-6, however qemu 2175 * doesn't support blocksize of 2 (see HELPER(ldgm)). 2176 */ 2177 if (tcg_enabled()) { 2178 assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6); 2179 } 2180 2181 #ifndef CONFIG_USER_ONLY 2182 /* 2183 * If we do not have tag-memory provided by the machine, 2184 * reduce MTE support to instructions enabled at EL0. 2185 * This matches Cortex-A710 BROADCASTMTE input being LOW. 2186 */ 2187 if (cpu->tag_memory == NULL) { 2188 cpu->isar.id_aa64pfr1 = 2189 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); 2190 } 2191 #endif 2192 } 2193 2194 if (tcg_enabled()) { 2195 /* 2196 * Don't report some architectural features in the ID registers 2197 * where TCG does not yet implement it (not even a minimal 2198 * stub version). This avoids guests falling over when they 2199 * try to access the non-existent system registers for them. 2200 */ 2201 /* FEAT_SPE (Statistical Profiling Extension) */ 2202 cpu->isar.id_aa64dfr0 = 2203 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); 2204 /* FEAT_TRBE (Trace Buffer Extension) */ 2205 cpu->isar.id_aa64dfr0 = 2206 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); 2207 /* FEAT_TRF (Self-hosted Trace Extension) */ 2208 cpu->isar.id_aa64dfr0 = 2209 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); 2210 cpu->isar.id_dfr0 = 2211 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); 2212 /* Trace Macrocell system register access */ 2213 cpu->isar.id_aa64dfr0 = 2214 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0); 2215 cpu->isar.id_dfr0 = 2216 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); 2217 /* Memory mapped trace */ 2218 cpu->isar.id_dfr0 = 2219 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); 2220 /* FEAT_AMU (Activity Monitors Extension) */ 2221 cpu->isar.id_aa64pfr0 = 2222 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0); 2223 cpu->isar.id_pfr0 = 2224 FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); 2225 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ 2226 cpu->isar.id_aa64pfr0 = 2227 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); 2228 /* FEAT_NV (Nested Virtualization) */ 2229 cpu->isar.id_aa64mmfr2 = 2230 FIELD_DP64(cpu->isar.id_aa64mmfr2, ID_AA64MMFR2, NV, 0); 2231 } 2232 2233 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 2234 * to false or by setting pmsav7-dregion to 0. 2235 */ 2236 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) { 2237 cpu->has_mpu = false; 2238 cpu->pmsav7_dregion = 0; 2239 cpu->pmsav8r_hdregion = 0; 2240 } 2241 2242 if (arm_feature(env, ARM_FEATURE_PMSA) && 2243 arm_feature(env, ARM_FEATURE_V7)) { 2244 uint32_t nr = cpu->pmsav7_dregion; 2245 2246 if (nr > 0xff) { 2247 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 2248 return; 2249 } 2250 2251 if (nr) { 2252 if (arm_feature(env, ARM_FEATURE_V8)) { 2253 /* PMSAv8 */ 2254 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 2255 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 2256 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2257 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 2258 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 2259 } 2260 } else { 2261 env->pmsav7.drbar = g_new0(uint32_t, nr); 2262 env->pmsav7.drsr = g_new0(uint32_t, nr); 2263 env->pmsav7.dracr = g_new0(uint32_t, nr); 2264 } 2265 } 2266 2267 if (cpu->pmsav8r_hdregion > 0xff) { 2268 error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32, 2269 cpu->pmsav8r_hdregion); 2270 return; 2271 } 2272 2273 if (cpu->pmsav8r_hdregion) { 2274 env->pmsav8.hprbar = g_new0(uint32_t, 2275 cpu->pmsav8r_hdregion); 2276 env->pmsav8.hprlar = g_new0(uint32_t, 2277 cpu->pmsav8r_hdregion); 2278 } 2279 } 2280 2281 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 2282 uint32_t nr = cpu->sau_sregion; 2283 2284 if (nr > 0xff) { 2285 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 2286 return; 2287 } 2288 2289 if (nr) { 2290 env->sau.rbar = g_new0(uint32_t, nr); 2291 env->sau.rlar = g_new0(uint32_t, nr); 2292 } 2293 } 2294 2295 if (arm_feature(env, ARM_FEATURE_EL3)) { 2296 set_feature(env, ARM_FEATURE_VBAR); 2297 } 2298 2299 #ifndef CONFIG_USER_ONLY 2300 if (tcg_enabled() && cpu_isar_feature(aa64_rme, cpu)) { 2301 arm_register_el_change_hook(cpu, >_rme_post_el_change, 0); 2302 } 2303 #endif 2304 2305 register_cp_regs_for_features(cpu); 2306 arm_cpu_register_gdb_regs_for_features(cpu); 2307 2308 init_cpreg_list(cpu); 2309 2310 #ifndef CONFIG_USER_ONLY 2311 MachineState *ms = MACHINE(qdev_get_machine()); 2312 unsigned int smp_cpus = ms->smp.cpus; 2313 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 2314 2315 /* 2316 * We must set cs->num_ases to the final value before 2317 * the first call to cpu_address_space_init. 2318 */ 2319 if (cpu->tag_memory != NULL) { 2320 cs->num_ases = 3 + has_secure; 2321 } else { 2322 cs->num_ases = 1 + has_secure; 2323 } 2324 2325 if (has_secure) { 2326 if (!cpu->secure_memory) { 2327 cpu->secure_memory = cs->memory; 2328 } 2329 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 2330 cpu->secure_memory); 2331 } 2332 2333 if (cpu->tag_memory != NULL) { 2334 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 2335 cpu->tag_memory); 2336 if (has_secure) { 2337 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 2338 cpu->secure_tag_memory); 2339 } 2340 } 2341 2342 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 2343 2344 /* No core_count specified, default to smp_cpus. */ 2345 if (cpu->core_count == -1) { 2346 cpu->core_count = smp_cpus; 2347 } 2348 #endif 2349 2350 if (tcg_enabled()) { 2351 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2352 2353 /* 2354 * We only support DCZ blocklen that fits on one page. 2355 * 2356 * Architectually this is always true. However TARGET_PAGE_SIZE 2357 * is variable and, for compatibility with -machine virt-2.7, 2358 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2359 * But even then, while the largest architectural DCZ blocklen 2360 * is 2KiB, no cpu actually uses such a large blocklen. 2361 */ 2362 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2363 2364 /* 2365 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2366 * both nibbles of each byte storing tag data may be written at once. 2367 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2368 */ 2369 if (cpu_isar_feature(aa64_mte, cpu)) { 2370 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2371 } 2372 } 2373 2374 qemu_init_vcpu(cs); 2375 cpu_reset(cs); 2376 2377 acc->parent_realize(dev, errp); 2378 } 2379 2380 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2381 { 2382 ObjectClass *oc; 2383 char *typename; 2384 char **cpuname; 2385 const char *cpunamestr; 2386 2387 cpuname = g_strsplit(cpu_model, ",", 1); 2388 cpunamestr = cpuname[0]; 2389 #ifdef CONFIG_USER_ONLY 2390 /* For backwards compatibility usermode emulation allows "-cpu any", 2391 * which has the same semantics as "-cpu max". 2392 */ 2393 if (!strcmp(cpunamestr, "any")) { 2394 cpunamestr = "max"; 2395 } 2396 #endif 2397 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2398 oc = object_class_by_name(typename); 2399 g_strfreev(cpuname); 2400 g_free(typename); 2401 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 2402 object_class_is_abstract(oc)) { 2403 return NULL; 2404 } 2405 return oc; 2406 } 2407 2408 static Property arm_cpu_properties[] = { 2409 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2410 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2411 mp_affinity, ARM64_AFFINITY_INVALID), 2412 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2413 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2414 DEFINE_PROP_END_OF_LIST() 2415 }; 2416 2417 static const gchar *arm_gdb_arch_name(CPUState *cs) 2418 { 2419 ARMCPU *cpu = ARM_CPU(cs); 2420 CPUARMState *env = &cpu->env; 2421 2422 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2423 return "iwmmxt"; 2424 } 2425 return "arm"; 2426 } 2427 2428 #ifndef CONFIG_USER_ONLY 2429 #include "hw/core/sysemu-cpu-ops.h" 2430 2431 static const struct SysemuCPUOps arm_sysemu_ops = { 2432 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2433 .asidx_from_attrs = arm_asidx_from_attrs, 2434 .write_elf32_note = arm_cpu_write_elf32_note, 2435 .write_elf64_note = arm_cpu_write_elf64_note, 2436 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2437 .legacy_vmsd = &vmstate_arm_cpu, 2438 }; 2439 #endif 2440 2441 #ifdef CONFIG_TCG 2442 static const struct TCGCPUOps arm_tcg_ops = { 2443 .initialize = arm_translate_init, 2444 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2445 .debug_excp_handler = arm_debug_excp_handler, 2446 .restore_state_to_opc = arm_restore_state_to_opc, 2447 2448 #ifdef CONFIG_USER_ONLY 2449 .record_sigsegv = arm_cpu_record_sigsegv, 2450 .record_sigbus = arm_cpu_record_sigbus, 2451 #else 2452 .tlb_fill = arm_cpu_tlb_fill, 2453 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2454 .do_interrupt = arm_cpu_do_interrupt, 2455 .do_transaction_failed = arm_cpu_do_transaction_failed, 2456 .do_unaligned_access = arm_cpu_do_unaligned_access, 2457 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2458 .debug_check_watchpoint = arm_debug_check_watchpoint, 2459 .debug_check_breakpoint = arm_debug_check_breakpoint, 2460 #endif /* !CONFIG_USER_ONLY */ 2461 }; 2462 #endif /* CONFIG_TCG */ 2463 2464 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2465 { 2466 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2467 CPUClass *cc = CPU_CLASS(acc); 2468 DeviceClass *dc = DEVICE_CLASS(oc); 2469 ResettableClass *rc = RESETTABLE_CLASS(oc); 2470 2471 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2472 &acc->parent_realize); 2473 2474 device_class_set_props(dc, arm_cpu_properties); 2475 2476 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, 2477 &acc->parent_phases); 2478 2479 cc->class_by_name = arm_cpu_class_by_name; 2480 cc->has_work = arm_cpu_has_work; 2481 cc->dump_state = arm_cpu_dump_state; 2482 cc->set_pc = arm_cpu_set_pc; 2483 cc->get_pc = arm_cpu_get_pc; 2484 cc->gdb_read_register = arm_cpu_gdb_read_register; 2485 cc->gdb_write_register = arm_cpu_gdb_write_register; 2486 #ifndef CONFIG_USER_ONLY 2487 cc->sysemu_ops = &arm_sysemu_ops; 2488 #endif 2489 cc->gdb_num_core_regs = 26; 2490 cc->gdb_arch_name = arm_gdb_arch_name; 2491 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2492 cc->gdb_stop_before_watchpoint = true; 2493 cc->disas_set_info = arm_disas_set_info; 2494 2495 #ifdef CONFIG_TCG 2496 cc->tcg_ops = &arm_tcg_ops; 2497 #endif /* CONFIG_TCG */ 2498 } 2499 2500 static void arm_cpu_instance_init(Object *obj) 2501 { 2502 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2503 2504 acc->info->initfn(obj); 2505 arm_cpu_post_init(obj); 2506 } 2507 2508 static void cpu_register_class_init(ObjectClass *oc, void *data) 2509 { 2510 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2511 CPUClass *cc = CPU_CLASS(acc); 2512 2513 acc->info = data; 2514 cc->gdb_core_xml_file = "arm-core.xml"; 2515 } 2516 2517 void arm_cpu_register(const ARMCPUInfo *info) 2518 { 2519 TypeInfo type_info = { 2520 .parent = TYPE_ARM_CPU, 2521 .instance_init = arm_cpu_instance_init, 2522 .class_init = info->class_init ?: cpu_register_class_init, 2523 .class_data = (void *)info, 2524 }; 2525 2526 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2527 type_register(&type_info); 2528 g_free((void *)type_info.name); 2529 } 2530 2531 static const TypeInfo arm_cpu_type_info = { 2532 .name = TYPE_ARM_CPU, 2533 .parent = TYPE_CPU, 2534 .instance_size = sizeof(ARMCPU), 2535 .instance_align = __alignof__(ARMCPU), 2536 .instance_init = arm_cpu_initfn, 2537 .instance_finalize = arm_cpu_finalizefn, 2538 .abstract = true, 2539 .class_size = sizeof(ARMCPUClass), 2540 .class_init = arm_cpu_class_init, 2541 }; 2542 2543 static void arm_cpu_register_types(void) 2544 { 2545 type_register_static(&arm_cpu_type_info); 2546 } 2547 2548 type_init(arm_cpu_register_types) 2549