1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "target/arm/idau.h" 23 #include "qemu/error-report.h" 24 #include "qapi/error.h" 25 #include "cpu.h" 26 #include "internals.h" 27 #include "qemu-common.h" 28 #include "exec/exec-all.h" 29 #include "hw/qdev-properties.h" 30 #if !defined(CONFIG_USER_ONLY) 31 #include "hw/loader.h" 32 #endif 33 #include "hw/arm/arm.h" 34 #include "sysemu/sysemu.h" 35 #include "sysemu/hw_accel.h" 36 #include "kvm_arm.h" 37 #include "disas/capstone.h" 38 #include "fpu/softfloat.h" 39 40 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 41 { 42 ARMCPU *cpu = ARM_CPU(cs); 43 44 cpu->env.regs[15] = value; 45 } 46 47 static bool arm_cpu_has_work(CPUState *cs) 48 { 49 ARMCPU *cpu = ARM_CPU(cs); 50 51 return (cpu->power_state != PSCI_OFF) 52 && cs->interrupt_request & 53 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 54 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 55 | CPU_INTERRUPT_EXITTB); 56 } 57 58 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 59 void *opaque) 60 { 61 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 62 63 entry->hook = hook; 64 entry->opaque = opaque; 65 66 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 67 } 68 69 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 70 { 71 /* Reset a single ARMCPRegInfo register */ 72 ARMCPRegInfo *ri = value; 73 ARMCPU *cpu = opaque; 74 75 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 76 return; 77 } 78 79 if (ri->resetfn) { 80 ri->resetfn(&cpu->env, ri); 81 return; 82 } 83 84 /* A zero offset is never possible as it would be regs[0] 85 * so we use it to indicate that reset is being handled elsewhere. 86 * This is basically only used for fields in non-core coprocessors 87 * (like the pxa2xx ones). 88 */ 89 if (!ri->fieldoffset) { 90 return; 91 } 92 93 if (cpreg_field_is_64bit(ri)) { 94 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 95 } else { 96 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 97 } 98 } 99 100 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 101 { 102 /* Purely an assertion check: we've already done reset once, 103 * so now check that running the reset for the cpreg doesn't 104 * change its value. This traps bugs where two different cpregs 105 * both try to reset the same state field but to different values. 106 */ 107 ARMCPRegInfo *ri = value; 108 ARMCPU *cpu = opaque; 109 uint64_t oldvalue, newvalue; 110 111 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 112 return; 113 } 114 115 oldvalue = read_raw_cp_reg(&cpu->env, ri); 116 cp_reg_reset(key, value, opaque); 117 newvalue = read_raw_cp_reg(&cpu->env, ri); 118 assert(oldvalue == newvalue); 119 } 120 121 /* CPUClass::reset() */ 122 static void arm_cpu_reset(CPUState *s) 123 { 124 ARMCPU *cpu = ARM_CPU(s); 125 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 126 CPUARMState *env = &cpu->env; 127 128 acc->parent_reset(s); 129 130 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 131 132 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 133 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 134 135 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 136 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 137 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 138 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 139 140 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 141 s->halted = cpu->start_powered_off; 142 143 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 144 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 145 } 146 147 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 148 /* 64 bit CPUs always start in 64 bit mode */ 149 env->aarch64 = 1; 150 #if defined(CONFIG_USER_ONLY) 151 env->pstate = PSTATE_MODE_EL0t; 152 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 153 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 154 /* and to the FP/Neon instructions */ 155 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 156 #else 157 /* Reset into the highest available EL */ 158 if (arm_feature(env, ARM_FEATURE_EL3)) { 159 env->pstate = PSTATE_MODE_EL3h; 160 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 161 env->pstate = PSTATE_MODE_EL2h; 162 } else { 163 env->pstate = PSTATE_MODE_EL1h; 164 } 165 env->pc = cpu->rvbar; 166 #endif 167 } else { 168 #if defined(CONFIG_USER_ONLY) 169 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 170 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 171 #endif 172 } 173 174 #if defined(CONFIG_USER_ONLY) 175 env->uncached_cpsr = ARM_CPU_MODE_USR; 176 /* For user mode we must enable access to coprocessors */ 177 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 178 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 179 env->cp15.c15_cpar = 3; 180 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 181 env->cp15.c15_cpar = 1; 182 } 183 #else 184 /* SVC mode with interrupts disabled. */ 185 env->uncached_cpsr = ARM_CPU_MODE_SVC; 186 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 187 188 if (arm_feature(env, ARM_FEATURE_M)) { 189 uint32_t initial_msp; /* Loaded from 0x0 */ 190 uint32_t initial_pc; /* Loaded from 0x4 */ 191 uint8_t *rom; 192 uint32_t vecbase; 193 194 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 195 env->v7m.secure = true; 196 } else { 197 /* This bit resets to 0 if security is supported, but 1 if 198 * it is not. The bit is not present in v7M, but we set it 199 * here so we can avoid having to make checks on it conditional 200 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 201 */ 202 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 203 } 204 205 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 206 * that it resets to 1, so QEMU always does that rather than making 207 * it dependent on CPU model. In v8M it is RES1. 208 */ 209 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 210 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 211 if (arm_feature(env, ARM_FEATURE_V8)) { 212 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 213 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 214 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 215 } 216 217 /* Unlike A/R profile, M profile defines the reset LR value */ 218 env->regs[14] = 0xffffffff; 219 220 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 221 222 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 223 vecbase = env->v7m.vecbase[env->v7m.secure]; 224 rom = rom_ptr(vecbase); 225 if (rom) { 226 /* Address zero is covered by ROM which hasn't yet been 227 * copied into physical memory. 228 */ 229 initial_msp = ldl_p(rom); 230 initial_pc = ldl_p(rom + 4); 231 } else { 232 /* Address zero not covered by a ROM blob, or the ROM blob 233 * is in non-modifiable memory and this is a second reset after 234 * it got copied into memory. In the latter case, rom_ptr 235 * will return a NULL pointer and we should use ldl_phys instead. 236 */ 237 initial_msp = ldl_phys(s->as, vecbase); 238 initial_pc = ldl_phys(s->as, vecbase + 4); 239 } 240 241 env->regs[13] = initial_msp & 0xFFFFFFFC; 242 env->regs[15] = initial_pc & ~1; 243 env->thumb = initial_pc & 1; 244 } 245 246 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 247 * executing as AArch32 then check if highvecs are enabled and 248 * adjust the PC accordingly. 249 */ 250 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 251 env->regs[15] = 0xFFFF0000; 252 } 253 254 /* M profile requires that reset clears the exclusive monitor; 255 * A profile does not, but clearing it makes more sense than having it 256 * set with an exclusive access on address zero. 257 */ 258 arm_clear_exclusive(env); 259 260 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 261 #endif 262 263 if (arm_feature(env, ARM_FEATURE_PMSA)) { 264 if (cpu->pmsav7_dregion > 0) { 265 if (arm_feature(env, ARM_FEATURE_V8)) { 266 memset(env->pmsav8.rbar[M_REG_NS], 0, 267 sizeof(*env->pmsav8.rbar[M_REG_NS]) 268 * cpu->pmsav7_dregion); 269 memset(env->pmsav8.rlar[M_REG_NS], 0, 270 sizeof(*env->pmsav8.rlar[M_REG_NS]) 271 * cpu->pmsav7_dregion); 272 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 273 memset(env->pmsav8.rbar[M_REG_S], 0, 274 sizeof(*env->pmsav8.rbar[M_REG_S]) 275 * cpu->pmsav7_dregion); 276 memset(env->pmsav8.rlar[M_REG_S], 0, 277 sizeof(*env->pmsav8.rlar[M_REG_S]) 278 * cpu->pmsav7_dregion); 279 } 280 } else if (arm_feature(env, ARM_FEATURE_V7)) { 281 memset(env->pmsav7.drbar, 0, 282 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 283 memset(env->pmsav7.drsr, 0, 284 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 285 memset(env->pmsav7.dracr, 0, 286 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 287 } 288 } 289 env->pmsav7.rnr[M_REG_NS] = 0; 290 env->pmsav7.rnr[M_REG_S] = 0; 291 env->pmsav8.mair0[M_REG_NS] = 0; 292 env->pmsav8.mair0[M_REG_S] = 0; 293 env->pmsav8.mair1[M_REG_NS] = 0; 294 env->pmsav8.mair1[M_REG_S] = 0; 295 } 296 297 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 298 if (cpu->sau_sregion > 0) { 299 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 300 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 301 } 302 env->sau.rnr = 0; 303 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 304 * the Cortex-M33 does. 305 */ 306 env->sau.ctrl = 0; 307 } 308 309 set_flush_to_zero(1, &env->vfp.standard_fp_status); 310 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 311 set_default_nan_mode(1, &env->vfp.standard_fp_status); 312 set_float_detect_tininess(float_tininess_before_rounding, 313 &env->vfp.fp_status); 314 set_float_detect_tininess(float_tininess_before_rounding, 315 &env->vfp.standard_fp_status); 316 #ifndef CONFIG_USER_ONLY 317 if (kvm_enabled()) { 318 kvm_arm_reset_vcpu(cpu); 319 } 320 #endif 321 322 hw_breakpoint_update_all(cpu); 323 hw_watchpoint_update_all(cpu); 324 } 325 326 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 327 { 328 CPUClass *cc = CPU_GET_CLASS(cs); 329 CPUARMState *env = cs->env_ptr; 330 uint32_t cur_el = arm_current_el(env); 331 bool secure = arm_is_secure(env); 332 uint32_t target_el; 333 uint32_t excp_idx; 334 bool ret = false; 335 336 if (interrupt_request & CPU_INTERRUPT_FIQ) { 337 excp_idx = EXCP_FIQ; 338 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 339 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 340 cs->exception_index = excp_idx; 341 env->exception.target_el = target_el; 342 cc->do_interrupt(cs); 343 ret = true; 344 } 345 } 346 if (interrupt_request & CPU_INTERRUPT_HARD) { 347 excp_idx = EXCP_IRQ; 348 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 349 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 350 cs->exception_index = excp_idx; 351 env->exception.target_el = target_el; 352 cc->do_interrupt(cs); 353 ret = true; 354 } 355 } 356 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 357 excp_idx = EXCP_VIRQ; 358 target_el = 1; 359 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 360 cs->exception_index = excp_idx; 361 env->exception.target_el = target_el; 362 cc->do_interrupt(cs); 363 ret = true; 364 } 365 } 366 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 367 excp_idx = EXCP_VFIQ; 368 target_el = 1; 369 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 370 cs->exception_index = excp_idx; 371 env->exception.target_el = target_el; 372 cc->do_interrupt(cs); 373 ret = true; 374 } 375 } 376 377 return ret; 378 } 379 380 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 381 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 382 { 383 CPUClass *cc = CPU_GET_CLASS(cs); 384 ARMCPU *cpu = ARM_CPU(cs); 385 CPUARMState *env = &cpu->env; 386 bool ret = false; 387 388 /* ARMv7-M interrupt masking works differently than -A or -R. 389 * There is no FIQ/IRQ distinction. Instead of I and F bits 390 * masking FIQ and IRQ interrupts, an exception is taken only 391 * if it is higher priority than the current execution priority 392 * (which depends on state like BASEPRI, FAULTMASK and the 393 * currently active exception). 394 */ 395 if (interrupt_request & CPU_INTERRUPT_HARD 396 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 397 cs->exception_index = EXCP_IRQ; 398 cc->do_interrupt(cs); 399 ret = true; 400 } 401 return ret; 402 } 403 #endif 404 405 #ifndef CONFIG_USER_ONLY 406 static void arm_cpu_set_irq(void *opaque, int irq, int level) 407 { 408 ARMCPU *cpu = opaque; 409 CPUARMState *env = &cpu->env; 410 CPUState *cs = CPU(cpu); 411 static const int mask[] = { 412 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 413 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 414 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 415 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 416 }; 417 418 switch (irq) { 419 case ARM_CPU_VIRQ: 420 case ARM_CPU_VFIQ: 421 assert(arm_feature(env, ARM_FEATURE_EL2)); 422 /* fall through */ 423 case ARM_CPU_IRQ: 424 case ARM_CPU_FIQ: 425 if (level) { 426 cpu_interrupt(cs, mask[irq]); 427 } else { 428 cpu_reset_interrupt(cs, mask[irq]); 429 } 430 break; 431 default: 432 g_assert_not_reached(); 433 } 434 } 435 436 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 437 { 438 #ifdef CONFIG_KVM 439 ARMCPU *cpu = opaque; 440 CPUState *cs = CPU(cpu); 441 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 442 443 switch (irq) { 444 case ARM_CPU_IRQ: 445 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 446 break; 447 case ARM_CPU_FIQ: 448 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 449 break; 450 default: 451 g_assert_not_reached(); 452 } 453 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 454 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 455 #endif 456 } 457 458 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 459 { 460 ARMCPU *cpu = ARM_CPU(cs); 461 CPUARMState *env = &cpu->env; 462 463 cpu_synchronize_state(cs); 464 return arm_cpu_data_is_big_endian(env); 465 } 466 467 #endif 468 469 static inline void set_feature(CPUARMState *env, int feature) 470 { 471 env->features |= 1ULL << feature; 472 } 473 474 static inline void unset_feature(CPUARMState *env, int feature) 475 { 476 env->features &= ~(1ULL << feature); 477 } 478 479 static int 480 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 481 { 482 return print_insn_arm(pc | 1, info); 483 } 484 485 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 486 { 487 ARMCPU *ac = ARM_CPU(cpu); 488 CPUARMState *env = &ac->env; 489 bool sctlr_b; 490 491 if (is_a64(env)) { 492 /* We might not be compiled with the A64 disassembler 493 * because it needs a C++ compiler. Leave print_insn 494 * unset in this case to use the caller default behaviour. 495 */ 496 #if defined(CONFIG_ARM_A64_DIS) 497 info->print_insn = print_insn_arm_a64; 498 #endif 499 info->cap_arch = CS_ARCH_ARM64; 500 info->cap_insn_unit = 4; 501 info->cap_insn_split = 4; 502 } else { 503 int cap_mode; 504 if (env->thumb) { 505 info->print_insn = print_insn_thumb1; 506 info->cap_insn_unit = 2; 507 info->cap_insn_split = 4; 508 cap_mode = CS_MODE_THUMB; 509 } else { 510 info->print_insn = print_insn_arm; 511 info->cap_insn_unit = 4; 512 info->cap_insn_split = 4; 513 cap_mode = CS_MODE_ARM; 514 } 515 if (arm_feature(env, ARM_FEATURE_V8)) { 516 cap_mode |= CS_MODE_V8; 517 } 518 if (arm_feature(env, ARM_FEATURE_M)) { 519 cap_mode |= CS_MODE_MCLASS; 520 } 521 info->cap_arch = CS_ARCH_ARM; 522 info->cap_mode = cap_mode; 523 } 524 525 sctlr_b = arm_sctlr_b(env); 526 if (bswap_code(sctlr_b)) { 527 #ifdef TARGET_WORDS_BIGENDIAN 528 info->endian = BFD_ENDIAN_LITTLE; 529 #else 530 info->endian = BFD_ENDIAN_BIG; 531 #endif 532 } 533 info->flags &= ~INSN_ARM_BE32; 534 #ifndef CONFIG_USER_ONLY 535 if (sctlr_b) { 536 info->flags |= INSN_ARM_BE32; 537 } 538 #endif 539 } 540 541 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 542 { 543 uint32_t Aff1 = idx / clustersz; 544 uint32_t Aff0 = idx % clustersz; 545 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 546 } 547 548 static void arm_cpu_initfn(Object *obj) 549 { 550 CPUState *cs = CPU(obj); 551 ARMCPU *cpu = ARM_CPU(obj); 552 553 cs->env_ptr = &cpu->env; 554 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 555 g_free, g_free); 556 557 QLIST_INIT(&cpu->el_change_hooks); 558 559 #ifndef CONFIG_USER_ONLY 560 /* Our inbound IRQ and FIQ lines */ 561 if (kvm_enabled()) { 562 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 563 * the same interface as non-KVM CPUs. 564 */ 565 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 566 } else { 567 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 568 } 569 570 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 571 arm_gt_ptimer_cb, cpu); 572 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 573 arm_gt_vtimer_cb, cpu); 574 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 575 arm_gt_htimer_cb, cpu); 576 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 577 arm_gt_stimer_cb, cpu); 578 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 579 ARRAY_SIZE(cpu->gt_timer_outputs)); 580 581 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 582 "gicv3-maintenance-interrupt", 1); 583 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 584 "pmu-interrupt", 1); 585 #endif 586 587 /* DTB consumers generally don't in fact care what the 'compatible' 588 * string is, so always provide some string and trust that a hypothetical 589 * picky DTB consumer will also provide a helpful error message. 590 */ 591 cpu->dtb_compatible = "qemu,unknown"; 592 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 593 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 594 595 if (tcg_enabled()) { 596 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 597 } 598 } 599 600 static Property arm_cpu_reset_cbar_property = 601 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 602 603 static Property arm_cpu_reset_hivecs_property = 604 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 605 606 static Property arm_cpu_rvbar_property = 607 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 608 609 static Property arm_cpu_has_el2_property = 610 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 611 612 static Property arm_cpu_has_el3_property = 613 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 614 615 static Property arm_cpu_cfgend_property = 616 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 617 618 /* use property name "pmu" to match other archs and virt tools */ 619 static Property arm_cpu_has_pmu_property = 620 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 621 622 static Property arm_cpu_has_mpu_property = 623 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 624 625 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 626 * because the CPU initfn will have already set cpu->pmsav7_dregion to 627 * the right value for that particular CPU type, and we don't want 628 * to override that with an incorrect constant value. 629 */ 630 static Property arm_cpu_pmsav7_dregion_property = 631 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 632 pmsav7_dregion, 633 qdev_prop_uint32, uint32_t); 634 635 /* M profile: initial value of the Secure VTOR */ 636 static Property arm_cpu_initsvtor_property = 637 DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0); 638 639 static void arm_cpu_post_init(Object *obj) 640 { 641 ARMCPU *cpu = ARM_CPU(obj); 642 643 /* M profile implies PMSA. We have to do this here rather than 644 * in realize with the other feature-implication checks because 645 * we look at the PMSA bit to see if we should add some properties. 646 */ 647 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 648 set_feature(&cpu->env, ARM_FEATURE_PMSA); 649 } 650 651 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 652 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 653 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 654 &error_abort); 655 } 656 657 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 658 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 659 &error_abort); 660 } 661 662 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 663 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 664 &error_abort); 665 } 666 667 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 668 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 669 * prevent "has_el3" from existing on CPUs which cannot support EL3. 670 */ 671 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 672 &error_abort); 673 674 #ifndef CONFIG_USER_ONLY 675 object_property_add_link(obj, "secure-memory", 676 TYPE_MEMORY_REGION, 677 (Object **)&cpu->secure_memory, 678 qdev_prop_allow_set_link_before_realize, 679 OBJ_PROP_LINK_UNREF_ON_RELEASE, 680 &error_abort); 681 #endif 682 } 683 684 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 685 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 686 &error_abort); 687 } 688 689 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 690 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 691 &error_abort); 692 } 693 694 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 695 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 696 &error_abort); 697 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 698 qdev_property_add_static(DEVICE(obj), 699 &arm_cpu_pmsav7_dregion_property, 700 &error_abort); 701 } 702 } 703 704 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 705 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 706 qdev_prop_allow_set_link_before_realize, 707 OBJ_PROP_LINK_UNREF_ON_RELEASE, 708 &error_abort); 709 qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property, 710 &error_abort); 711 } 712 713 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 714 &error_abort); 715 } 716 717 static void arm_cpu_finalizefn(Object *obj) 718 { 719 ARMCPU *cpu = ARM_CPU(obj); 720 ARMELChangeHook *hook, *next; 721 722 g_hash_table_destroy(cpu->cp_regs); 723 724 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 725 QLIST_REMOVE(hook, node); 726 g_free(hook); 727 } 728 } 729 730 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 731 { 732 CPUState *cs = CPU(dev); 733 ARMCPU *cpu = ARM_CPU(dev); 734 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 735 CPUARMState *env = &cpu->env; 736 int pagebits; 737 Error *local_err = NULL; 738 739 /* If we needed to query the host kernel for the CPU features 740 * then it's possible that might have failed in the initfn, but 741 * this is the first point where we can report it. 742 */ 743 if (cpu->host_cpu_probe_failed) { 744 if (!kvm_enabled()) { 745 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 746 } else { 747 error_setg(errp, "Failed to retrieve host CPU features"); 748 } 749 return; 750 } 751 752 cpu_exec_realizefn(cs, &local_err); 753 if (local_err != NULL) { 754 error_propagate(errp, local_err); 755 return; 756 } 757 758 /* Some features automatically imply others: */ 759 if (arm_feature(env, ARM_FEATURE_V8)) { 760 set_feature(env, ARM_FEATURE_V7); 761 set_feature(env, ARM_FEATURE_ARM_DIV); 762 set_feature(env, ARM_FEATURE_LPAE); 763 } 764 if (arm_feature(env, ARM_FEATURE_V7)) { 765 set_feature(env, ARM_FEATURE_VAPA); 766 set_feature(env, ARM_FEATURE_THUMB2); 767 set_feature(env, ARM_FEATURE_MPIDR); 768 if (!arm_feature(env, ARM_FEATURE_M)) { 769 set_feature(env, ARM_FEATURE_V6K); 770 } else { 771 set_feature(env, ARM_FEATURE_V6); 772 } 773 774 /* Always define VBAR for V7 CPUs even if it doesn't exist in 775 * non-EL3 configs. This is needed by some legacy boards. 776 */ 777 set_feature(env, ARM_FEATURE_VBAR); 778 } 779 if (arm_feature(env, ARM_FEATURE_V6K)) { 780 set_feature(env, ARM_FEATURE_V6); 781 set_feature(env, ARM_FEATURE_MVFR); 782 } 783 if (arm_feature(env, ARM_FEATURE_V6)) { 784 set_feature(env, ARM_FEATURE_V5); 785 set_feature(env, ARM_FEATURE_JAZELLE); 786 if (!arm_feature(env, ARM_FEATURE_M)) { 787 set_feature(env, ARM_FEATURE_AUXCR); 788 } 789 } 790 if (arm_feature(env, ARM_FEATURE_V5)) { 791 set_feature(env, ARM_FEATURE_V4T); 792 } 793 if (arm_feature(env, ARM_FEATURE_M)) { 794 set_feature(env, ARM_FEATURE_THUMB_DIV); 795 } 796 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 797 set_feature(env, ARM_FEATURE_THUMB_DIV); 798 } 799 if (arm_feature(env, ARM_FEATURE_VFP4)) { 800 set_feature(env, ARM_FEATURE_VFP3); 801 set_feature(env, ARM_FEATURE_VFP_FP16); 802 } 803 if (arm_feature(env, ARM_FEATURE_VFP3)) { 804 set_feature(env, ARM_FEATURE_VFP); 805 } 806 if (arm_feature(env, ARM_FEATURE_LPAE)) { 807 set_feature(env, ARM_FEATURE_V7MP); 808 set_feature(env, ARM_FEATURE_PXN); 809 } 810 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 811 set_feature(env, ARM_FEATURE_CBAR); 812 } 813 if (arm_feature(env, ARM_FEATURE_THUMB2) && 814 !arm_feature(env, ARM_FEATURE_M)) { 815 set_feature(env, ARM_FEATURE_THUMB_DSP); 816 } 817 818 if (arm_feature(env, ARM_FEATURE_V7) && 819 !arm_feature(env, ARM_FEATURE_M) && 820 !arm_feature(env, ARM_FEATURE_PMSA)) { 821 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 822 * can use 4K pages. 823 */ 824 pagebits = 12; 825 } else { 826 /* For CPUs which might have tiny 1K pages, or which have an 827 * MPU and might have small region sizes, stick with 1K pages. 828 */ 829 pagebits = 10; 830 } 831 if (!set_preferred_target_page_bits(pagebits)) { 832 /* This can only ever happen for hotplugging a CPU, or if 833 * the board code incorrectly creates a CPU which it has 834 * promised via minimum_page_size that it will not. 835 */ 836 error_setg(errp, "This CPU requires a smaller page size than the " 837 "system is using"); 838 return; 839 } 840 841 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 842 * We don't support setting cluster ID ([16..23]) (known as Aff2 843 * in later ARM ARM versions), or any of the higher affinity level fields, 844 * so these bits always RAZ. 845 */ 846 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 847 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 848 ARM_DEFAULT_CPUS_PER_CLUSTER); 849 } 850 851 if (cpu->reset_hivecs) { 852 cpu->reset_sctlr |= (1 << 13); 853 } 854 855 if (cpu->cfgend) { 856 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 857 cpu->reset_sctlr |= SCTLR_EE; 858 } else { 859 cpu->reset_sctlr |= SCTLR_B; 860 } 861 } 862 863 if (!cpu->has_el3) { 864 /* If the has_el3 CPU property is disabled then we need to disable the 865 * feature. 866 */ 867 unset_feature(env, ARM_FEATURE_EL3); 868 869 /* Disable the security extension feature bits in the processor feature 870 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 871 */ 872 cpu->id_pfr1 &= ~0xf0; 873 cpu->id_aa64pfr0 &= ~0xf000; 874 } 875 876 if (!cpu->has_el2) { 877 unset_feature(env, ARM_FEATURE_EL2); 878 } 879 880 if (!cpu->has_pmu) { 881 unset_feature(env, ARM_FEATURE_PMU); 882 cpu->id_aa64dfr0 &= ~0xf00; 883 } 884 885 if (!arm_feature(env, ARM_FEATURE_EL2)) { 886 /* Disable the hypervisor feature bits in the processor feature 887 * registers if we don't have EL2. These are id_pfr1[15:12] and 888 * id_aa64pfr0_el1[11:8]. 889 */ 890 cpu->id_aa64pfr0 &= ~0xf00; 891 cpu->id_pfr1 &= ~0xf000; 892 } 893 894 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 895 * to false or by setting pmsav7-dregion to 0. 896 */ 897 if (!cpu->has_mpu) { 898 cpu->pmsav7_dregion = 0; 899 } 900 if (cpu->pmsav7_dregion == 0) { 901 cpu->has_mpu = false; 902 } 903 904 if (arm_feature(env, ARM_FEATURE_PMSA) && 905 arm_feature(env, ARM_FEATURE_V7)) { 906 uint32_t nr = cpu->pmsav7_dregion; 907 908 if (nr > 0xff) { 909 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 910 return; 911 } 912 913 if (nr) { 914 if (arm_feature(env, ARM_FEATURE_V8)) { 915 /* PMSAv8 */ 916 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 917 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 918 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 919 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 920 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 921 } 922 } else { 923 env->pmsav7.drbar = g_new0(uint32_t, nr); 924 env->pmsav7.drsr = g_new0(uint32_t, nr); 925 env->pmsav7.dracr = g_new0(uint32_t, nr); 926 } 927 } 928 } 929 930 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 931 uint32_t nr = cpu->sau_sregion; 932 933 if (nr > 0xff) { 934 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 935 return; 936 } 937 938 if (nr) { 939 env->sau.rbar = g_new0(uint32_t, nr); 940 env->sau.rlar = g_new0(uint32_t, nr); 941 } 942 } 943 944 if (arm_feature(env, ARM_FEATURE_EL3)) { 945 set_feature(env, ARM_FEATURE_VBAR); 946 } 947 948 register_cp_regs_for_features(cpu); 949 arm_cpu_register_gdb_regs_for_features(cpu); 950 951 init_cpreg_list(cpu); 952 953 #ifndef CONFIG_USER_ONLY 954 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 955 cs->num_ases = 2; 956 957 if (!cpu->secure_memory) { 958 cpu->secure_memory = cs->memory; 959 } 960 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 961 cpu->secure_memory); 962 } else { 963 cs->num_ases = 1; 964 } 965 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 966 967 /* No core_count specified, default to smp_cpus. */ 968 if (cpu->core_count == -1) { 969 cpu->core_count = smp_cpus; 970 } 971 #endif 972 973 qemu_init_vcpu(cs); 974 cpu_reset(cs); 975 976 acc->parent_realize(dev, errp); 977 } 978 979 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 980 { 981 ObjectClass *oc; 982 char *typename; 983 char **cpuname; 984 const char *cpunamestr; 985 986 cpuname = g_strsplit(cpu_model, ",", 1); 987 cpunamestr = cpuname[0]; 988 #ifdef CONFIG_USER_ONLY 989 /* For backwards compatibility usermode emulation allows "-cpu any", 990 * which has the same semantics as "-cpu max". 991 */ 992 if (!strcmp(cpunamestr, "any")) { 993 cpunamestr = "max"; 994 } 995 #endif 996 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 997 oc = object_class_by_name(typename); 998 g_strfreev(cpuname); 999 g_free(typename); 1000 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1001 object_class_is_abstract(oc)) { 1002 return NULL; 1003 } 1004 return oc; 1005 } 1006 1007 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1008 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1009 1010 static void arm926_initfn(Object *obj) 1011 { 1012 ARMCPU *cpu = ARM_CPU(obj); 1013 1014 cpu->dtb_compatible = "arm,arm926"; 1015 set_feature(&cpu->env, ARM_FEATURE_V5); 1016 set_feature(&cpu->env, ARM_FEATURE_VFP); 1017 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1018 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1019 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 1020 cpu->midr = 0x41069265; 1021 cpu->reset_fpsid = 0x41011090; 1022 cpu->ctr = 0x1dd20d2; 1023 cpu->reset_sctlr = 0x00090078; 1024 } 1025 1026 static void arm946_initfn(Object *obj) 1027 { 1028 ARMCPU *cpu = ARM_CPU(obj); 1029 1030 cpu->dtb_compatible = "arm,arm946"; 1031 set_feature(&cpu->env, ARM_FEATURE_V5); 1032 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1033 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1034 cpu->midr = 0x41059461; 1035 cpu->ctr = 0x0f004006; 1036 cpu->reset_sctlr = 0x00000078; 1037 } 1038 1039 static void arm1026_initfn(Object *obj) 1040 { 1041 ARMCPU *cpu = ARM_CPU(obj); 1042 1043 cpu->dtb_compatible = "arm,arm1026"; 1044 set_feature(&cpu->env, ARM_FEATURE_V5); 1045 set_feature(&cpu->env, ARM_FEATURE_VFP); 1046 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 1047 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1048 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1049 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 1050 cpu->midr = 0x4106a262; 1051 cpu->reset_fpsid = 0x410110a0; 1052 cpu->ctr = 0x1dd20d2; 1053 cpu->reset_sctlr = 0x00090078; 1054 cpu->reset_auxcr = 1; 1055 { 1056 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1057 ARMCPRegInfo ifar = { 1058 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1059 .access = PL1_RW, 1060 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1061 .resetvalue = 0 1062 }; 1063 define_one_arm_cp_reg(cpu, &ifar); 1064 } 1065 } 1066 1067 static void arm1136_r2_initfn(Object *obj) 1068 { 1069 ARMCPU *cpu = ARM_CPU(obj); 1070 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1071 * older core than plain "arm1136". In particular this does not 1072 * have the v6K features. 1073 * These ID register values are correct for 1136 but may be wrong 1074 * for 1136_r2 (in particular r0p2 does not actually implement most 1075 * of the ID registers). 1076 */ 1077 1078 cpu->dtb_compatible = "arm,arm1136"; 1079 set_feature(&cpu->env, ARM_FEATURE_V6); 1080 set_feature(&cpu->env, ARM_FEATURE_VFP); 1081 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1082 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1083 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1084 cpu->midr = 0x4107b362; 1085 cpu->reset_fpsid = 0x410120b4; 1086 cpu->mvfr0 = 0x11111111; 1087 cpu->mvfr1 = 0x00000000; 1088 cpu->ctr = 0x1dd20d2; 1089 cpu->reset_sctlr = 0x00050078; 1090 cpu->id_pfr0 = 0x111; 1091 cpu->id_pfr1 = 0x1; 1092 cpu->id_dfr0 = 0x2; 1093 cpu->id_afr0 = 0x3; 1094 cpu->id_mmfr0 = 0x01130003; 1095 cpu->id_mmfr1 = 0x10030302; 1096 cpu->id_mmfr2 = 0x01222110; 1097 cpu->id_isar0 = 0x00140011; 1098 cpu->id_isar1 = 0x12002111; 1099 cpu->id_isar2 = 0x11231111; 1100 cpu->id_isar3 = 0x01102131; 1101 cpu->id_isar4 = 0x141; 1102 cpu->reset_auxcr = 7; 1103 } 1104 1105 static void arm1136_initfn(Object *obj) 1106 { 1107 ARMCPU *cpu = ARM_CPU(obj); 1108 1109 cpu->dtb_compatible = "arm,arm1136"; 1110 set_feature(&cpu->env, ARM_FEATURE_V6K); 1111 set_feature(&cpu->env, ARM_FEATURE_V6); 1112 set_feature(&cpu->env, ARM_FEATURE_VFP); 1113 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1114 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1115 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1116 cpu->midr = 0x4117b363; 1117 cpu->reset_fpsid = 0x410120b4; 1118 cpu->mvfr0 = 0x11111111; 1119 cpu->mvfr1 = 0x00000000; 1120 cpu->ctr = 0x1dd20d2; 1121 cpu->reset_sctlr = 0x00050078; 1122 cpu->id_pfr0 = 0x111; 1123 cpu->id_pfr1 = 0x1; 1124 cpu->id_dfr0 = 0x2; 1125 cpu->id_afr0 = 0x3; 1126 cpu->id_mmfr0 = 0x01130003; 1127 cpu->id_mmfr1 = 0x10030302; 1128 cpu->id_mmfr2 = 0x01222110; 1129 cpu->id_isar0 = 0x00140011; 1130 cpu->id_isar1 = 0x12002111; 1131 cpu->id_isar2 = 0x11231111; 1132 cpu->id_isar3 = 0x01102131; 1133 cpu->id_isar4 = 0x141; 1134 cpu->reset_auxcr = 7; 1135 } 1136 1137 static void arm1176_initfn(Object *obj) 1138 { 1139 ARMCPU *cpu = ARM_CPU(obj); 1140 1141 cpu->dtb_compatible = "arm,arm1176"; 1142 set_feature(&cpu->env, ARM_FEATURE_V6K); 1143 set_feature(&cpu->env, ARM_FEATURE_VFP); 1144 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1145 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1146 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1147 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1148 set_feature(&cpu->env, ARM_FEATURE_EL3); 1149 cpu->midr = 0x410fb767; 1150 cpu->reset_fpsid = 0x410120b5; 1151 cpu->mvfr0 = 0x11111111; 1152 cpu->mvfr1 = 0x00000000; 1153 cpu->ctr = 0x1dd20d2; 1154 cpu->reset_sctlr = 0x00050078; 1155 cpu->id_pfr0 = 0x111; 1156 cpu->id_pfr1 = 0x11; 1157 cpu->id_dfr0 = 0x33; 1158 cpu->id_afr0 = 0; 1159 cpu->id_mmfr0 = 0x01130003; 1160 cpu->id_mmfr1 = 0x10030302; 1161 cpu->id_mmfr2 = 0x01222100; 1162 cpu->id_isar0 = 0x0140011; 1163 cpu->id_isar1 = 0x12002111; 1164 cpu->id_isar2 = 0x11231121; 1165 cpu->id_isar3 = 0x01102131; 1166 cpu->id_isar4 = 0x01141; 1167 cpu->reset_auxcr = 7; 1168 } 1169 1170 static void arm11mpcore_initfn(Object *obj) 1171 { 1172 ARMCPU *cpu = ARM_CPU(obj); 1173 1174 cpu->dtb_compatible = "arm,arm11mpcore"; 1175 set_feature(&cpu->env, ARM_FEATURE_V6K); 1176 set_feature(&cpu->env, ARM_FEATURE_VFP); 1177 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1178 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1179 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1180 cpu->midr = 0x410fb022; 1181 cpu->reset_fpsid = 0x410120b4; 1182 cpu->mvfr0 = 0x11111111; 1183 cpu->mvfr1 = 0x00000000; 1184 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1185 cpu->id_pfr0 = 0x111; 1186 cpu->id_pfr1 = 0x1; 1187 cpu->id_dfr0 = 0; 1188 cpu->id_afr0 = 0x2; 1189 cpu->id_mmfr0 = 0x01100103; 1190 cpu->id_mmfr1 = 0x10020302; 1191 cpu->id_mmfr2 = 0x01222000; 1192 cpu->id_isar0 = 0x00100011; 1193 cpu->id_isar1 = 0x12002111; 1194 cpu->id_isar2 = 0x11221011; 1195 cpu->id_isar3 = 0x01102131; 1196 cpu->id_isar4 = 0x141; 1197 cpu->reset_auxcr = 1; 1198 } 1199 1200 static void cortex_m3_initfn(Object *obj) 1201 { 1202 ARMCPU *cpu = ARM_CPU(obj); 1203 set_feature(&cpu->env, ARM_FEATURE_V7); 1204 set_feature(&cpu->env, ARM_FEATURE_M); 1205 cpu->midr = 0x410fc231; 1206 cpu->pmsav7_dregion = 8; 1207 cpu->id_pfr0 = 0x00000030; 1208 cpu->id_pfr1 = 0x00000200; 1209 cpu->id_dfr0 = 0x00100000; 1210 cpu->id_afr0 = 0x00000000; 1211 cpu->id_mmfr0 = 0x00000030; 1212 cpu->id_mmfr1 = 0x00000000; 1213 cpu->id_mmfr2 = 0x00000000; 1214 cpu->id_mmfr3 = 0x00000000; 1215 cpu->id_isar0 = 0x01141110; 1216 cpu->id_isar1 = 0x02111000; 1217 cpu->id_isar2 = 0x21112231; 1218 cpu->id_isar3 = 0x01111110; 1219 cpu->id_isar4 = 0x01310102; 1220 cpu->id_isar5 = 0x00000000; 1221 } 1222 1223 static void cortex_m4_initfn(Object *obj) 1224 { 1225 ARMCPU *cpu = ARM_CPU(obj); 1226 1227 set_feature(&cpu->env, ARM_FEATURE_V7); 1228 set_feature(&cpu->env, ARM_FEATURE_M); 1229 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1230 cpu->midr = 0x410fc240; /* r0p0 */ 1231 cpu->pmsav7_dregion = 8; 1232 cpu->id_pfr0 = 0x00000030; 1233 cpu->id_pfr1 = 0x00000200; 1234 cpu->id_dfr0 = 0x00100000; 1235 cpu->id_afr0 = 0x00000000; 1236 cpu->id_mmfr0 = 0x00000030; 1237 cpu->id_mmfr1 = 0x00000000; 1238 cpu->id_mmfr2 = 0x00000000; 1239 cpu->id_mmfr3 = 0x00000000; 1240 cpu->id_isar0 = 0x01141110; 1241 cpu->id_isar1 = 0x02111000; 1242 cpu->id_isar2 = 0x21112231; 1243 cpu->id_isar3 = 0x01111110; 1244 cpu->id_isar4 = 0x01310102; 1245 cpu->id_isar5 = 0x00000000; 1246 } 1247 1248 static void cortex_m33_initfn(Object *obj) 1249 { 1250 ARMCPU *cpu = ARM_CPU(obj); 1251 1252 set_feature(&cpu->env, ARM_FEATURE_V8); 1253 set_feature(&cpu->env, ARM_FEATURE_M); 1254 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 1255 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1256 cpu->midr = 0x410fd213; /* r0p3 */ 1257 cpu->pmsav7_dregion = 16; 1258 cpu->sau_sregion = 8; 1259 cpu->id_pfr0 = 0x00000030; 1260 cpu->id_pfr1 = 0x00000210; 1261 cpu->id_dfr0 = 0x00200000; 1262 cpu->id_afr0 = 0x00000000; 1263 cpu->id_mmfr0 = 0x00101F40; 1264 cpu->id_mmfr1 = 0x00000000; 1265 cpu->id_mmfr2 = 0x01000000; 1266 cpu->id_mmfr3 = 0x00000000; 1267 cpu->id_isar0 = 0x01101110; 1268 cpu->id_isar1 = 0x02212000; 1269 cpu->id_isar2 = 0x20232232; 1270 cpu->id_isar3 = 0x01111131; 1271 cpu->id_isar4 = 0x01310132; 1272 cpu->id_isar5 = 0x00000000; 1273 cpu->clidr = 0x00000000; 1274 cpu->ctr = 0x8000c000; 1275 } 1276 1277 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1278 { 1279 CPUClass *cc = CPU_CLASS(oc); 1280 1281 #ifndef CONFIG_USER_ONLY 1282 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1283 #endif 1284 1285 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1286 } 1287 1288 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1289 /* Dummy the TCM region regs for the moment */ 1290 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1291 .access = PL1_RW, .type = ARM_CP_CONST }, 1292 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1293 .access = PL1_RW, .type = ARM_CP_CONST }, 1294 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1295 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1296 REGINFO_SENTINEL 1297 }; 1298 1299 static void cortex_r5_initfn(Object *obj) 1300 { 1301 ARMCPU *cpu = ARM_CPU(obj); 1302 1303 set_feature(&cpu->env, ARM_FEATURE_V7); 1304 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1305 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1306 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1307 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1308 cpu->midr = 0x411fc153; /* r1p3 */ 1309 cpu->id_pfr0 = 0x0131; 1310 cpu->id_pfr1 = 0x001; 1311 cpu->id_dfr0 = 0x010400; 1312 cpu->id_afr0 = 0x0; 1313 cpu->id_mmfr0 = 0x0210030; 1314 cpu->id_mmfr1 = 0x00000000; 1315 cpu->id_mmfr2 = 0x01200000; 1316 cpu->id_mmfr3 = 0x0211; 1317 cpu->id_isar0 = 0x2101111; 1318 cpu->id_isar1 = 0x13112111; 1319 cpu->id_isar2 = 0x21232141; 1320 cpu->id_isar3 = 0x01112131; 1321 cpu->id_isar4 = 0x0010142; 1322 cpu->id_isar5 = 0x0; 1323 cpu->mp_is_up = true; 1324 cpu->pmsav7_dregion = 16; 1325 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1326 } 1327 1328 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1329 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1330 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1331 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1332 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1333 REGINFO_SENTINEL 1334 }; 1335 1336 static void cortex_a8_initfn(Object *obj) 1337 { 1338 ARMCPU *cpu = ARM_CPU(obj); 1339 1340 cpu->dtb_compatible = "arm,cortex-a8"; 1341 set_feature(&cpu->env, ARM_FEATURE_V7); 1342 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1343 set_feature(&cpu->env, ARM_FEATURE_NEON); 1344 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1345 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1346 set_feature(&cpu->env, ARM_FEATURE_EL3); 1347 cpu->midr = 0x410fc080; 1348 cpu->reset_fpsid = 0x410330c0; 1349 cpu->mvfr0 = 0x11110222; 1350 cpu->mvfr1 = 0x00011111; 1351 cpu->ctr = 0x82048004; 1352 cpu->reset_sctlr = 0x00c50078; 1353 cpu->id_pfr0 = 0x1031; 1354 cpu->id_pfr1 = 0x11; 1355 cpu->id_dfr0 = 0x400; 1356 cpu->id_afr0 = 0; 1357 cpu->id_mmfr0 = 0x31100003; 1358 cpu->id_mmfr1 = 0x20000000; 1359 cpu->id_mmfr2 = 0x01202000; 1360 cpu->id_mmfr3 = 0x11; 1361 cpu->id_isar0 = 0x00101111; 1362 cpu->id_isar1 = 0x12112111; 1363 cpu->id_isar2 = 0x21232031; 1364 cpu->id_isar3 = 0x11112131; 1365 cpu->id_isar4 = 0x00111142; 1366 cpu->dbgdidr = 0x15141000; 1367 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1368 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1369 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1370 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1371 cpu->reset_auxcr = 2; 1372 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1373 } 1374 1375 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1376 /* power_control should be set to maximum latency. Again, 1377 * default to 0 and set by private hook 1378 */ 1379 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1380 .access = PL1_RW, .resetvalue = 0, 1381 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1382 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1383 .access = PL1_RW, .resetvalue = 0, 1384 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1385 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1386 .access = PL1_RW, .resetvalue = 0, 1387 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1388 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1389 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1390 /* TLB lockdown control */ 1391 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1392 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1393 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1394 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1395 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1396 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1397 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1398 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1399 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1400 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1401 REGINFO_SENTINEL 1402 }; 1403 1404 static void cortex_a9_initfn(Object *obj) 1405 { 1406 ARMCPU *cpu = ARM_CPU(obj); 1407 1408 cpu->dtb_compatible = "arm,cortex-a9"; 1409 set_feature(&cpu->env, ARM_FEATURE_V7); 1410 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1411 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1412 set_feature(&cpu->env, ARM_FEATURE_NEON); 1413 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1414 set_feature(&cpu->env, ARM_FEATURE_EL3); 1415 /* Note that A9 supports the MP extensions even for 1416 * A9UP and single-core A9MP (which are both different 1417 * and valid configurations; we don't model A9UP). 1418 */ 1419 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1420 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1421 cpu->midr = 0x410fc090; 1422 cpu->reset_fpsid = 0x41033090; 1423 cpu->mvfr0 = 0x11110222; 1424 cpu->mvfr1 = 0x01111111; 1425 cpu->ctr = 0x80038003; 1426 cpu->reset_sctlr = 0x00c50078; 1427 cpu->id_pfr0 = 0x1031; 1428 cpu->id_pfr1 = 0x11; 1429 cpu->id_dfr0 = 0x000; 1430 cpu->id_afr0 = 0; 1431 cpu->id_mmfr0 = 0x00100103; 1432 cpu->id_mmfr1 = 0x20000000; 1433 cpu->id_mmfr2 = 0x01230000; 1434 cpu->id_mmfr3 = 0x00002111; 1435 cpu->id_isar0 = 0x00101111; 1436 cpu->id_isar1 = 0x13112111; 1437 cpu->id_isar2 = 0x21232041; 1438 cpu->id_isar3 = 0x11112131; 1439 cpu->id_isar4 = 0x00111142; 1440 cpu->dbgdidr = 0x35141000; 1441 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1442 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1443 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1444 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1445 } 1446 1447 #ifndef CONFIG_USER_ONLY 1448 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1449 { 1450 /* Linux wants the number of processors from here. 1451 * Might as well set the interrupt-controller bit too. 1452 */ 1453 return ((smp_cpus - 1) << 24) | (1 << 23); 1454 } 1455 #endif 1456 1457 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1458 #ifndef CONFIG_USER_ONLY 1459 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1460 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1461 .writefn = arm_cp_write_ignore, }, 1462 #endif 1463 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1464 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1465 REGINFO_SENTINEL 1466 }; 1467 1468 static void cortex_a7_initfn(Object *obj) 1469 { 1470 ARMCPU *cpu = ARM_CPU(obj); 1471 1472 cpu->dtb_compatible = "arm,cortex-a7"; 1473 set_feature(&cpu->env, ARM_FEATURE_V7); 1474 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1475 set_feature(&cpu->env, ARM_FEATURE_NEON); 1476 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1477 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1478 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1479 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1480 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1481 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1482 set_feature(&cpu->env, ARM_FEATURE_EL3); 1483 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1484 cpu->midr = 0x410fc075; 1485 cpu->reset_fpsid = 0x41023075; 1486 cpu->mvfr0 = 0x10110222; 1487 cpu->mvfr1 = 0x11111111; 1488 cpu->ctr = 0x84448003; 1489 cpu->reset_sctlr = 0x00c50078; 1490 cpu->id_pfr0 = 0x00001131; 1491 cpu->id_pfr1 = 0x00011011; 1492 cpu->id_dfr0 = 0x02010555; 1493 cpu->pmceid0 = 0x00000000; 1494 cpu->pmceid1 = 0x00000000; 1495 cpu->id_afr0 = 0x00000000; 1496 cpu->id_mmfr0 = 0x10101105; 1497 cpu->id_mmfr1 = 0x40000000; 1498 cpu->id_mmfr2 = 0x01240000; 1499 cpu->id_mmfr3 = 0x02102211; 1500 cpu->id_isar0 = 0x01101110; 1501 cpu->id_isar1 = 0x13112111; 1502 cpu->id_isar2 = 0x21232041; 1503 cpu->id_isar3 = 0x11112131; 1504 cpu->id_isar4 = 0x10011142; 1505 cpu->dbgdidr = 0x3515f005; 1506 cpu->clidr = 0x0a200023; 1507 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1508 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1509 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1510 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1511 } 1512 1513 static void cortex_a15_initfn(Object *obj) 1514 { 1515 ARMCPU *cpu = ARM_CPU(obj); 1516 1517 cpu->dtb_compatible = "arm,cortex-a15"; 1518 set_feature(&cpu->env, ARM_FEATURE_V7); 1519 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1520 set_feature(&cpu->env, ARM_FEATURE_NEON); 1521 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1522 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1523 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1524 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1525 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1526 set_feature(&cpu->env, ARM_FEATURE_LPAE); 1527 set_feature(&cpu->env, ARM_FEATURE_EL3); 1528 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1529 cpu->midr = 0x412fc0f1; 1530 cpu->reset_fpsid = 0x410430f0; 1531 cpu->mvfr0 = 0x10110222; 1532 cpu->mvfr1 = 0x11111111; 1533 cpu->ctr = 0x8444c004; 1534 cpu->reset_sctlr = 0x00c50078; 1535 cpu->id_pfr0 = 0x00001131; 1536 cpu->id_pfr1 = 0x00011011; 1537 cpu->id_dfr0 = 0x02010555; 1538 cpu->pmceid0 = 0x0000000; 1539 cpu->pmceid1 = 0x00000000; 1540 cpu->id_afr0 = 0x00000000; 1541 cpu->id_mmfr0 = 0x10201105; 1542 cpu->id_mmfr1 = 0x20000000; 1543 cpu->id_mmfr2 = 0x01240000; 1544 cpu->id_mmfr3 = 0x02102211; 1545 cpu->id_isar0 = 0x02101110; 1546 cpu->id_isar1 = 0x13112111; 1547 cpu->id_isar2 = 0x21232041; 1548 cpu->id_isar3 = 0x11112131; 1549 cpu->id_isar4 = 0x10011142; 1550 cpu->dbgdidr = 0x3515f021; 1551 cpu->clidr = 0x0a200023; 1552 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1553 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1554 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1555 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1556 } 1557 1558 static void ti925t_initfn(Object *obj) 1559 { 1560 ARMCPU *cpu = ARM_CPU(obj); 1561 set_feature(&cpu->env, ARM_FEATURE_V4T); 1562 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1563 cpu->midr = ARM_CPUID_TI925T; 1564 cpu->ctr = 0x5109149; 1565 cpu->reset_sctlr = 0x00000070; 1566 } 1567 1568 static void sa1100_initfn(Object *obj) 1569 { 1570 ARMCPU *cpu = ARM_CPU(obj); 1571 1572 cpu->dtb_compatible = "intel,sa1100"; 1573 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1574 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1575 cpu->midr = 0x4401A11B; 1576 cpu->reset_sctlr = 0x00000070; 1577 } 1578 1579 static void sa1110_initfn(Object *obj) 1580 { 1581 ARMCPU *cpu = ARM_CPU(obj); 1582 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1583 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1584 cpu->midr = 0x6901B119; 1585 cpu->reset_sctlr = 0x00000070; 1586 } 1587 1588 static void pxa250_initfn(Object *obj) 1589 { 1590 ARMCPU *cpu = ARM_CPU(obj); 1591 1592 cpu->dtb_compatible = "marvell,xscale"; 1593 set_feature(&cpu->env, ARM_FEATURE_V5); 1594 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1595 cpu->midr = 0x69052100; 1596 cpu->ctr = 0xd172172; 1597 cpu->reset_sctlr = 0x00000078; 1598 } 1599 1600 static void pxa255_initfn(Object *obj) 1601 { 1602 ARMCPU *cpu = ARM_CPU(obj); 1603 1604 cpu->dtb_compatible = "marvell,xscale"; 1605 set_feature(&cpu->env, ARM_FEATURE_V5); 1606 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1607 cpu->midr = 0x69052d00; 1608 cpu->ctr = 0xd172172; 1609 cpu->reset_sctlr = 0x00000078; 1610 } 1611 1612 static void pxa260_initfn(Object *obj) 1613 { 1614 ARMCPU *cpu = ARM_CPU(obj); 1615 1616 cpu->dtb_compatible = "marvell,xscale"; 1617 set_feature(&cpu->env, ARM_FEATURE_V5); 1618 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1619 cpu->midr = 0x69052903; 1620 cpu->ctr = 0xd172172; 1621 cpu->reset_sctlr = 0x00000078; 1622 } 1623 1624 static void pxa261_initfn(Object *obj) 1625 { 1626 ARMCPU *cpu = ARM_CPU(obj); 1627 1628 cpu->dtb_compatible = "marvell,xscale"; 1629 set_feature(&cpu->env, ARM_FEATURE_V5); 1630 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1631 cpu->midr = 0x69052d05; 1632 cpu->ctr = 0xd172172; 1633 cpu->reset_sctlr = 0x00000078; 1634 } 1635 1636 static void pxa262_initfn(Object *obj) 1637 { 1638 ARMCPU *cpu = ARM_CPU(obj); 1639 1640 cpu->dtb_compatible = "marvell,xscale"; 1641 set_feature(&cpu->env, ARM_FEATURE_V5); 1642 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1643 cpu->midr = 0x69052d06; 1644 cpu->ctr = 0xd172172; 1645 cpu->reset_sctlr = 0x00000078; 1646 } 1647 1648 static void pxa270a0_initfn(Object *obj) 1649 { 1650 ARMCPU *cpu = ARM_CPU(obj); 1651 1652 cpu->dtb_compatible = "marvell,xscale"; 1653 set_feature(&cpu->env, ARM_FEATURE_V5); 1654 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1655 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1656 cpu->midr = 0x69054110; 1657 cpu->ctr = 0xd172172; 1658 cpu->reset_sctlr = 0x00000078; 1659 } 1660 1661 static void pxa270a1_initfn(Object *obj) 1662 { 1663 ARMCPU *cpu = ARM_CPU(obj); 1664 1665 cpu->dtb_compatible = "marvell,xscale"; 1666 set_feature(&cpu->env, ARM_FEATURE_V5); 1667 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1668 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1669 cpu->midr = 0x69054111; 1670 cpu->ctr = 0xd172172; 1671 cpu->reset_sctlr = 0x00000078; 1672 } 1673 1674 static void pxa270b0_initfn(Object *obj) 1675 { 1676 ARMCPU *cpu = ARM_CPU(obj); 1677 1678 cpu->dtb_compatible = "marvell,xscale"; 1679 set_feature(&cpu->env, ARM_FEATURE_V5); 1680 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1681 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1682 cpu->midr = 0x69054112; 1683 cpu->ctr = 0xd172172; 1684 cpu->reset_sctlr = 0x00000078; 1685 } 1686 1687 static void pxa270b1_initfn(Object *obj) 1688 { 1689 ARMCPU *cpu = ARM_CPU(obj); 1690 1691 cpu->dtb_compatible = "marvell,xscale"; 1692 set_feature(&cpu->env, ARM_FEATURE_V5); 1693 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1694 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1695 cpu->midr = 0x69054113; 1696 cpu->ctr = 0xd172172; 1697 cpu->reset_sctlr = 0x00000078; 1698 } 1699 1700 static void pxa270c0_initfn(Object *obj) 1701 { 1702 ARMCPU *cpu = ARM_CPU(obj); 1703 1704 cpu->dtb_compatible = "marvell,xscale"; 1705 set_feature(&cpu->env, ARM_FEATURE_V5); 1706 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1707 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1708 cpu->midr = 0x69054114; 1709 cpu->ctr = 0xd172172; 1710 cpu->reset_sctlr = 0x00000078; 1711 } 1712 1713 static void pxa270c5_initfn(Object *obj) 1714 { 1715 ARMCPU *cpu = ARM_CPU(obj); 1716 1717 cpu->dtb_compatible = "marvell,xscale"; 1718 set_feature(&cpu->env, ARM_FEATURE_V5); 1719 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1720 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1721 cpu->midr = 0x69054117; 1722 cpu->ctr = 0xd172172; 1723 cpu->reset_sctlr = 0x00000078; 1724 } 1725 1726 #ifndef TARGET_AARCH64 1727 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 1728 * otherwise, a CPU with as many features enabled as our emulation supports. 1729 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 1730 * this only needs to handle 32 bits. 1731 */ 1732 static void arm_max_initfn(Object *obj) 1733 { 1734 ARMCPU *cpu = ARM_CPU(obj); 1735 1736 if (kvm_enabled()) { 1737 kvm_arm_set_cpu_features_from_host(cpu); 1738 } else { 1739 cortex_a15_initfn(obj); 1740 #ifdef CONFIG_USER_ONLY 1741 /* We don't set these in system emulation mode for the moment, 1742 * since we don't correctly set the ID registers to advertise them, 1743 */ 1744 set_feature(&cpu->env, ARM_FEATURE_V8); 1745 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1746 set_feature(&cpu->env, ARM_FEATURE_NEON); 1747 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1748 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1749 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1750 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1751 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1752 set_feature(&cpu->env, ARM_FEATURE_CRC); 1753 set_feature(&cpu->env, ARM_FEATURE_V8_RDM); 1754 set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); 1755 #endif 1756 } 1757 } 1758 #endif 1759 1760 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1761 1762 typedef struct ARMCPUInfo { 1763 const char *name; 1764 void (*initfn)(Object *obj); 1765 void (*class_init)(ObjectClass *oc, void *data); 1766 } ARMCPUInfo; 1767 1768 static const ARMCPUInfo arm_cpus[] = { 1769 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1770 { .name = "arm926", .initfn = arm926_initfn }, 1771 { .name = "arm946", .initfn = arm946_initfn }, 1772 { .name = "arm1026", .initfn = arm1026_initfn }, 1773 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1774 * older core than plain "arm1136". In particular this does not 1775 * have the v6K features. 1776 */ 1777 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1778 { .name = "arm1136", .initfn = arm1136_initfn }, 1779 { .name = "arm1176", .initfn = arm1176_initfn }, 1780 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1781 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1782 .class_init = arm_v7m_class_init }, 1783 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1784 .class_init = arm_v7m_class_init }, 1785 { .name = "cortex-m33", .initfn = cortex_m33_initfn, 1786 .class_init = arm_v7m_class_init }, 1787 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1788 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1789 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1790 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1791 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1792 { .name = "ti925t", .initfn = ti925t_initfn }, 1793 { .name = "sa1100", .initfn = sa1100_initfn }, 1794 { .name = "sa1110", .initfn = sa1110_initfn }, 1795 { .name = "pxa250", .initfn = pxa250_initfn }, 1796 { .name = "pxa255", .initfn = pxa255_initfn }, 1797 { .name = "pxa260", .initfn = pxa260_initfn }, 1798 { .name = "pxa261", .initfn = pxa261_initfn }, 1799 { .name = "pxa262", .initfn = pxa262_initfn }, 1800 /* "pxa270" is an alias for "pxa270-a0" */ 1801 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1802 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1803 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1804 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1805 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1806 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1807 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1808 #ifndef TARGET_AARCH64 1809 { .name = "max", .initfn = arm_max_initfn }, 1810 #endif 1811 #ifdef CONFIG_USER_ONLY 1812 { .name = "any", .initfn = arm_max_initfn }, 1813 #endif 1814 #endif 1815 { .name = NULL } 1816 }; 1817 1818 static Property arm_cpu_properties[] = { 1819 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1820 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1821 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1822 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1823 mp_affinity, ARM64_AFFINITY_INVALID), 1824 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1825 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 1826 DEFINE_PROP_END_OF_LIST() 1827 }; 1828 1829 #ifdef CONFIG_USER_ONLY 1830 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, 1831 int rw, int mmu_idx) 1832 { 1833 ARMCPU *cpu = ARM_CPU(cs); 1834 CPUARMState *env = &cpu->env; 1835 1836 env->exception.vaddress = address; 1837 if (rw == 2) { 1838 cs->exception_index = EXCP_PREFETCH_ABORT; 1839 } else { 1840 cs->exception_index = EXCP_DATA_ABORT; 1841 } 1842 return 1; 1843 } 1844 #endif 1845 1846 static gchar *arm_gdb_arch_name(CPUState *cs) 1847 { 1848 ARMCPU *cpu = ARM_CPU(cs); 1849 CPUARMState *env = &cpu->env; 1850 1851 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1852 return g_strdup("iwmmxt"); 1853 } 1854 return g_strdup("arm"); 1855 } 1856 1857 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1858 { 1859 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1860 CPUClass *cc = CPU_CLASS(acc); 1861 DeviceClass *dc = DEVICE_CLASS(oc); 1862 1863 device_class_set_parent_realize(dc, arm_cpu_realizefn, 1864 &acc->parent_realize); 1865 dc->props = arm_cpu_properties; 1866 1867 acc->parent_reset = cc->reset; 1868 cc->reset = arm_cpu_reset; 1869 1870 cc->class_by_name = arm_cpu_class_by_name; 1871 cc->has_work = arm_cpu_has_work; 1872 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1873 cc->dump_state = arm_cpu_dump_state; 1874 cc->set_pc = arm_cpu_set_pc; 1875 cc->gdb_read_register = arm_cpu_gdb_read_register; 1876 cc->gdb_write_register = arm_cpu_gdb_write_register; 1877 #ifdef CONFIG_USER_ONLY 1878 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1879 #else 1880 cc->do_interrupt = arm_cpu_do_interrupt; 1881 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1882 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 1883 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1884 cc->asidx_from_attrs = arm_asidx_from_attrs; 1885 cc->vmsd = &vmstate_arm_cpu; 1886 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1887 cc->write_elf64_note = arm_cpu_write_elf64_note; 1888 cc->write_elf32_note = arm_cpu_write_elf32_note; 1889 #endif 1890 cc->gdb_num_core_regs = 26; 1891 cc->gdb_core_xml_file = "arm-core.xml"; 1892 cc->gdb_arch_name = arm_gdb_arch_name; 1893 cc->gdb_stop_before_watchpoint = true; 1894 cc->debug_excp_handler = arm_debug_excp_handler; 1895 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1896 #if !defined(CONFIG_USER_ONLY) 1897 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 1898 #endif 1899 1900 cc->disas_set_info = arm_disas_set_info; 1901 #ifdef CONFIG_TCG 1902 cc->tcg_initialize = arm_translate_init; 1903 #endif 1904 } 1905 1906 #ifdef CONFIG_KVM 1907 static void arm_host_initfn(Object *obj) 1908 { 1909 ARMCPU *cpu = ARM_CPU(obj); 1910 1911 kvm_arm_set_cpu_features_from_host(cpu); 1912 } 1913 1914 static const TypeInfo host_arm_cpu_type_info = { 1915 .name = TYPE_ARM_HOST_CPU, 1916 #ifdef TARGET_AARCH64 1917 .parent = TYPE_AARCH64_CPU, 1918 #else 1919 .parent = TYPE_ARM_CPU, 1920 #endif 1921 .instance_init = arm_host_initfn, 1922 }; 1923 1924 #endif 1925 1926 static void cpu_register(const ARMCPUInfo *info) 1927 { 1928 TypeInfo type_info = { 1929 .parent = TYPE_ARM_CPU, 1930 .instance_size = sizeof(ARMCPU), 1931 .instance_init = info->initfn, 1932 .class_size = sizeof(ARMCPUClass), 1933 .class_init = info->class_init, 1934 }; 1935 1936 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 1937 type_register(&type_info); 1938 g_free((void *)type_info.name); 1939 } 1940 1941 static const TypeInfo arm_cpu_type_info = { 1942 .name = TYPE_ARM_CPU, 1943 .parent = TYPE_CPU, 1944 .instance_size = sizeof(ARMCPU), 1945 .instance_init = arm_cpu_initfn, 1946 .instance_post_init = arm_cpu_post_init, 1947 .instance_finalize = arm_cpu_finalizefn, 1948 .abstract = true, 1949 .class_size = sizeof(ARMCPUClass), 1950 .class_init = arm_cpu_class_init, 1951 }; 1952 1953 static const TypeInfo idau_interface_type_info = { 1954 .name = TYPE_IDAU_INTERFACE, 1955 .parent = TYPE_INTERFACE, 1956 .class_size = sizeof(IDAUInterfaceClass), 1957 }; 1958 1959 static void arm_cpu_register_types(void) 1960 { 1961 const ARMCPUInfo *info = arm_cpus; 1962 1963 type_register_static(&arm_cpu_type_info); 1964 type_register_static(&idau_interface_type_info); 1965 1966 while (info->name) { 1967 cpu_register(info); 1968 info++; 1969 } 1970 1971 #ifdef CONFIG_KVM 1972 type_register_static(&host_arm_cpu_type_info); 1973 #endif 1974 } 1975 1976 type_init(arm_cpu_register_types) 1977