1ba7651fbSMax Filippov #ifndef XTENSA_TARGET_SYSCALL_H 2ba7651fbSMax Filippov #define XTENSA_TARGET_SYSCALL_H 3ba7651fbSMax Filippov 4ba7651fbSMax Filippov #define UNAME_MACHINE "xtensa" 5ba7651fbSMax Filippov 6ba7651fbSMax Filippov #define UNAME_MINIMUM_RELEASE "3.19" 7ba7651fbSMax Filippov #define TARGET_CLONE_BACKWARDS 8ba7651fbSMax Filippov 9ba7651fbSMax Filippov #define MMAP_SHIFT TARGET_PAGE_BITS 10ba7651fbSMax Filippov 11ba7651fbSMax Filippov typedef uint32_t xtensa_reg_t; 12ba7651fbSMax Filippov typedef struct { 13ba7651fbSMax Filippov } xtregs_opt_t; /* TODO */ 14ba7651fbSMax Filippov 15ba7651fbSMax Filippov struct target_pt_regs { 16ba7651fbSMax Filippov xtensa_reg_t pc; /* 4 */ 17ba7651fbSMax Filippov xtensa_reg_t ps; /* 8 */ 18ba7651fbSMax Filippov xtensa_reg_t depc; /* 12 */ 19ba7651fbSMax Filippov xtensa_reg_t exccause; /* 16 */ 20ba7651fbSMax Filippov xtensa_reg_t excvaddr; /* 20 */ 21ba7651fbSMax Filippov xtensa_reg_t debugcause; /* 24 */ 22ba7651fbSMax Filippov xtensa_reg_t wmask; /* 28 */ 23ba7651fbSMax Filippov xtensa_reg_t lbeg; /* 32 */ 24ba7651fbSMax Filippov xtensa_reg_t lend; /* 36 */ 25ba7651fbSMax Filippov xtensa_reg_t lcount; /* 40 */ 26ba7651fbSMax Filippov xtensa_reg_t sar; /* 44 */ 27ba7651fbSMax Filippov xtensa_reg_t windowbase; /* 48 */ 28ba7651fbSMax Filippov xtensa_reg_t windowstart; /* 52 */ 29ba7651fbSMax Filippov xtensa_reg_t syscall; /* 56 */ 30ba7651fbSMax Filippov xtensa_reg_t icountlevel; /* 60 */ 31ba7651fbSMax Filippov xtensa_reg_t scompare1; /* 64 */ 32ba7651fbSMax Filippov xtensa_reg_t threadptr; /* 68 */ 33ba7651fbSMax Filippov 34ba7651fbSMax Filippov /* Additional configurable registers that are used by the compiler. */ 35ba7651fbSMax Filippov xtregs_opt_t xtregs_opt; 36ba7651fbSMax Filippov 37ba7651fbSMax Filippov /* Make sure the areg field is 16 bytes aligned. */ 38ba7651fbSMax Filippov int align[0] __attribute__ ((aligned(16))); 39ba7651fbSMax Filippov 40ba7651fbSMax Filippov /* current register frame. 41ba7651fbSMax Filippov * Note: The ESF for kernel exceptions ends after 16 registers! 42ba7651fbSMax Filippov */ 43ba7651fbSMax Filippov xtensa_reg_t areg[16]; 44ba7651fbSMax Filippov }; 45ba7651fbSMax Filippov 46*02e5d7d7SFilip Bozuta #define TARGET_MCL_CURRENT 1 47*02e5d7d7SFilip Bozuta #define TARGET_MCL_FUTURE 2 48*02e5d7d7SFilip Bozuta #define TARGET_MCL_ONFAULT 4 49ba7651fbSMax Filippov 50ba7651fbSMax Filippov #endif 51