105a24871SPaolo Bonzini /* 205a24871SPaolo Bonzini * host-signal.h: signal info dependent on the host architecture 305a24871SPaolo Bonzini * 405a24871SPaolo Bonzini * Copyright (c) 2003-2005 Fabrice Bellard 505a24871SPaolo Bonzini * Copyright (c) 2021 Linaro Limited 605a24871SPaolo Bonzini * 705a24871SPaolo Bonzini * This work is licensed under the terms of the GNU LGPL, version 2.1 or later. 805a24871SPaolo Bonzini * See the COPYING file in the top-level directory. 905a24871SPaolo Bonzini */ 1005a24871SPaolo Bonzini 1105a24871SPaolo Bonzini #ifndef MIPS_HOST_SIGNAL_H 1205a24871SPaolo Bonzini #define MIPS_HOST_SIGNAL_H 1305a24871SPaolo Bonzini 14*9940799bSRichard Henderson /* The third argument to a SA_SIGINFO handler is ucontext_t. */ 15*9940799bSRichard Henderson typedef ucontext_t host_sigcontext; 16*9940799bSRichard Henderson host_signal_pc(host_sigcontext * uc)17*9940799bSRichard Hendersonstatic inline uintptr_t host_signal_pc(host_sigcontext *uc) 1805a24871SPaolo Bonzini { 1905a24871SPaolo Bonzini return uc->uc_mcontext.pc; 2005a24871SPaolo Bonzini } 2105a24871SPaolo Bonzini host_signal_set_pc(host_sigcontext * uc,uintptr_t pc)22*9940799bSRichard Hendersonstatic inline void host_signal_set_pc(host_sigcontext *uc, uintptr_t pc) 2305a24871SPaolo Bonzini { 2405a24871SPaolo Bonzini uc->uc_mcontext.pc = pc; 2505a24871SPaolo Bonzini } 2605a24871SPaolo Bonzini host_signal_mask(host_sigcontext * uc)27*9940799bSRichard Hendersonstatic inline void *host_signal_mask(host_sigcontext *uc) 28c8c89a6aSRichard Henderson { 29c8c89a6aSRichard Henderson return &uc->uc_sigmask; 30c8c89a6aSRichard Henderson } 31c8c89a6aSRichard Henderson 3205a24871SPaolo Bonzini #if defined(__misp16) || defined(__mips_micromips) 3305a24871SPaolo Bonzini #error "Unsupported encoding" 3405a24871SPaolo Bonzini #endif 3505a24871SPaolo Bonzini host_signal_write(siginfo_t * info,host_sigcontext * uc)36*9940799bSRichard Hendersonstatic inline bool host_signal_write(siginfo_t *info, host_sigcontext *uc) 3705a24871SPaolo Bonzini { 3805a24871SPaolo Bonzini uint32_t insn = *(uint32_t *)host_signal_pc(uc); 3905a24871SPaolo Bonzini 4005a24871SPaolo Bonzini /* Detect all store instructions at program counter. */ 4105a24871SPaolo Bonzini switch ((insn >> 26) & 077) { 4205a24871SPaolo Bonzini case 050: /* SB */ 4305a24871SPaolo Bonzini case 051: /* SH */ 4405a24871SPaolo Bonzini case 052: /* SWL */ 4505a24871SPaolo Bonzini case 053: /* SW */ 4605a24871SPaolo Bonzini case 054: /* SDL */ 4705a24871SPaolo Bonzini case 055: /* SDR */ 4805a24871SPaolo Bonzini case 056: /* SWR */ 4905a24871SPaolo Bonzini case 070: /* SC */ 5005a24871SPaolo Bonzini case 071: /* SWC1 */ 5105a24871SPaolo Bonzini case 074: /* SCD */ 5205a24871SPaolo Bonzini case 075: /* SDC1 */ 5305a24871SPaolo Bonzini case 077: /* SD */ 5405a24871SPaolo Bonzini #if !defined(__mips_isa_rev) || __mips_isa_rev < 6 5505a24871SPaolo Bonzini case 072: /* SWC2 */ 5605a24871SPaolo Bonzini case 076: /* SDC2 */ 5705a24871SPaolo Bonzini #endif 5805a24871SPaolo Bonzini return true; 5905a24871SPaolo Bonzini case 023: /* COP1X */ 6005a24871SPaolo Bonzini /* 6105a24871SPaolo Bonzini * Required in all versions of MIPS64 since 6205a24871SPaolo Bonzini * MIPS64r1 and subsequent versions of MIPS32r2. 6305a24871SPaolo Bonzini */ 6405a24871SPaolo Bonzini switch (insn & 077) { 6505a24871SPaolo Bonzini case 010: /* SWXC1 */ 6605a24871SPaolo Bonzini case 011: /* SDXC1 */ 6705a24871SPaolo Bonzini case 015: /* SUXC1 */ 6805a24871SPaolo Bonzini return true; 6905a24871SPaolo Bonzini } 7005a24871SPaolo Bonzini break; 7105a24871SPaolo Bonzini } 7205a24871SPaolo Bonzini return false; 7305a24871SPaolo Bonzini } 7405a24871SPaolo Bonzini 7505a24871SPaolo Bonzini #endif 76