1*05a24871SPaolo Bonzini /* 2*05a24871SPaolo Bonzini * host-signal.h: signal info dependent on the host architecture 3*05a24871SPaolo Bonzini * 4*05a24871SPaolo Bonzini * Copyright (c) 2003-2005 Fabrice Bellard 5*05a24871SPaolo Bonzini * Copyright (c) 2021 Linaro Limited 6*05a24871SPaolo Bonzini * 7*05a24871SPaolo Bonzini * This work is licensed under the terms of the GNU LGPL, version 2.1 or later. 8*05a24871SPaolo Bonzini * See the COPYING file in the top-level directory. 9*05a24871SPaolo Bonzini */ 10*05a24871SPaolo Bonzini 11*05a24871SPaolo Bonzini #ifndef ARM_HOST_SIGNAL_H 12*05a24871SPaolo Bonzini #define ARM_HOST_SIGNAL_H 13*05a24871SPaolo Bonzini 14*05a24871SPaolo Bonzini static inline uintptr_t host_signal_pc(ucontext_t *uc) 15*05a24871SPaolo Bonzini { 16*05a24871SPaolo Bonzini return uc->uc_mcontext.arm_pc; 17*05a24871SPaolo Bonzini } 18*05a24871SPaolo Bonzini 19*05a24871SPaolo Bonzini static inline void host_signal_set_pc(ucontext_t *uc, uintptr_t pc) 20*05a24871SPaolo Bonzini { 21*05a24871SPaolo Bonzini uc->uc_mcontext.arm_pc = pc; 22*05a24871SPaolo Bonzini } 23*05a24871SPaolo Bonzini 24*05a24871SPaolo Bonzini static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) 25*05a24871SPaolo Bonzini { 26*05a24871SPaolo Bonzini /* 27*05a24871SPaolo Bonzini * In the FSR, bit 11 is WnR, assuming a v6 or 28*05a24871SPaolo Bonzini * later processor. On v5 we will always report 29*05a24871SPaolo Bonzini * this as a read, which will fail later. 30*05a24871SPaolo Bonzini */ 31*05a24871SPaolo Bonzini uint32_t fsr = uc->uc_mcontext.error_code; 32*05a24871SPaolo Bonzini return extract32(fsr, 11, 1); 33*05a24871SPaolo Bonzini } 34*05a24871SPaolo Bonzini 35*05a24871SPaolo Bonzini #endif 36