1 #ifndef AARCH64_TARGET_SYSCALL_H 2 #define AARCH64_TARGET_SYSCALL_H 3 4 struct target_pt_regs { 5 uint64_t regs[31]; 6 uint64_t sp; 7 uint64_t pc; 8 uint64_t pstate; 9 }; 10 11 #if defined(TARGET_WORDS_BIGENDIAN) 12 #define UNAME_MACHINE "aarch64_be" 13 #else 14 #define UNAME_MACHINE "aarch64" 15 #endif 16 #define UNAME_MINIMUM_RELEASE "3.8.0" 17 #define TARGET_CLONE_BACKWARDS 18 #define TARGET_MCL_CURRENT 1 19 #define TARGET_MCL_FUTURE 2 20 #define TARGET_MCL_ONFAULT 4 21 22 #define TARGET_PR_SVE_SET_VL 50 23 #define TARGET_PR_SVE_GET_VL 51 24 25 #define TARGET_PR_PAC_RESET_KEYS 54 26 # define TARGET_PR_PAC_APIAKEY (1 << 0) 27 # define TARGET_PR_PAC_APIBKEY (1 << 1) 28 # define TARGET_PR_PAC_APDAKEY (1 << 2) 29 # define TARGET_PR_PAC_APDBKEY (1 << 3) 30 # define TARGET_PR_PAC_APGAKEY (1 << 4) 31 32 #define TARGET_PR_SET_TAGGED_ADDR_CTRL 55 33 #define TARGET_PR_GET_TAGGED_ADDR_CTRL 56 34 # define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0) 35 /* MTE tag check fault modes */ 36 # define TARGET_PR_MTE_TCF_SHIFT 1 37 # define TARGET_PR_MTE_TCF_NONE (0UL << TARGET_PR_MTE_TCF_SHIFT) 38 # define TARGET_PR_MTE_TCF_SYNC (1UL << TARGET_PR_MTE_TCF_SHIFT) 39 # define TARGET_PR_MTE_TCF_ASYNC (2UL << TARGET_PR_MTE_TCF_SHIFT) 40 # define TARGET_PR_MTE_TCF_MASK (3UL << TARGET_PR_MTE_TCF_SHIFT) 41 /* MTE tag inclusion mask */ 42 # define TARGET_PR_MTE_TAG_SHIFT 3 43 # define TARGET_PR_MTE_TAG_MASK (0xffffUL << TARGET_PR_MTE_TAG_SHIFT) 44 45 #endif /* AARCH64_TARGET_SYSCALL_H */ 46