1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef TCG_H 26 #define TCG_H 27 28 #include "cpu.h" 29 #include "exec/memop.h" 30 #include "exec/memopidx.h" 31 #include "qemu/bitops.h" 32 #include "qemu/plugin.h" 33 #include "qemu/queue.h" 34 #include "tcg/tcg-mo.h" 35 #include "tcg-target-reg-bits.h" 36 #include "tcg-target.h" 37 #include "tcg/tcg-cond.h" 38 #include "tcg/debug-assert.h" 39 40 /* XXX: make safe guess about sizes */ 41 #define MAX_OP_PER_INSTR 266 42 43 #define MAX_CALL_IARGS 7 44 45 #define CPU_TEMP_BUF_NLONGS 128 46 #define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) 47 48 #if TCG_TARGET_REG_BITS == 32 49 typedef int32_t tcg_target_long; 50 typedef uint32_t tcg_target_ulong; 51 #define TCG_PRIlx PRIx32 52 #define TCG_PRIld PRId32 53 #elif TCG_TARGET_REG_BITS == 64 54 typedef int64_t tcg_target_long; 55 typedef uint64_t tcg_target_ulong; 56 #define TCG_PRIlx PRIx64 57 #define TCG_PRIld PRId64 58 #else 59 #error unsupported 60 #endif 61 62 #if TCG_TARGET_NB_REGS <= 32 63 typedef uint32_t TCGRegSet; 64 #elif TCG_TARGET_NB_REGS <= 64 65 typedef uint64_t TCGRegSet; 66 #else 67 #error unsupported 68 #endif 69 70 #if TCG_TARGET_REG_BITS == 32 71 /* Turn some undef macros into false macros. */ 72 #define TCG_TARGET_HAS_extrl_i64_i32 0 73 #define TCG_TARGET_HAS_extrh_i64_i32 0 74 #define TCG_TARGET_HAS_div_i64 0 75 #define TCG_TARGET_HAS_rem_i64 0 76 #define TCG_TARGET_HAS_div2_i64 0 77 #define TCG_TARGET_HAS_rot_i64 0 78 #define TCG_TARGET_HAS_ext8s_i64 0 79 #define TCG_TARGET_HAS_ext16s_i64 0 80 #define TCG_TARGET_HAS_ext32s_i64 0 81 #define TCG_TARGET_HAS_ext8u_i64 0 82 #define TCG_TARGET_HAS_ext16u_i64 0 83 #define TCG_TARGET_HAS_ext32u_i64 0 84 #define TCG_TARGET_HAS_bswap16_i64 0 85 #define TCG_TARGET_HAS_bswap32_i64 0 86 #define TCG_TARGET_HAS_bswap64_i64 0 87 #define TCG_TARGET_HAS_neg_i64 0 88 #define TCG_TARGET_HAS_not_i64 0 89 #define TCG_TARGET_HAS_andc_i64 0 90 #define TCG_TARGET_HAS_orc_i64 0 91 #define TCG_TARGET_HAS_eqv_i64 0 92 #define TCG_TARGET_HAS_nand_i64 0 93 #define TCG_TARGET_HAS_nor_i64 0 94 #define TCG_TARGET_HAS_clz_i64 0 95 #define TCG_TARGET_HAS_ctz_i64 0 96 #define TCG_TARGET_HAS_ctpop_i64 0 97 #define TCG_TARGET_HAS_deposit_i64 0 98 #define TCG_TARGET_HAS_extract_i64 0 99 #define TCG_TARGET_HAS_sextract_i64 0 100 #define TCG_TARGET_HAS_extract2_i64 0 101 #define TCG_TARGET_HAS_movcond_i64 0 102 #define TCG_TARGET_HAS_add2_i64 0 103 #define TCG_TARGET_HAS_sub2_i64 0 104 #define TCG_TARGET_HAS_mulu2_i64 0 105 #define TCG_TARGET_HAS_muls2_i64 0 106 #define TCG_TARGET_HAS_muluh_i64 0 107 #define TCG_TARGET_HAS_mulsh_i64 0 108 /* Turn some undef macros into true macros. */ 109 #define TCG_TARGET_HAS_add2_i32 1 110 #define TCG_TARGET_HAS_sub2_i32 1 111 #endif 112 113 #ifndef TCG_TARGET_deposit_i32_valid 114 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 115 #endif 116 #ifndef TCG_TARGET_deposit_i64_valid 117 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 118 #endif 119 #ifndef TCG_TARGET_extract_i32_valid 120 #define TCG_TARGET_extract_i32_valid(ofs, len) 1 121 #endif 122 #ifndef TCG_TARGET_extract_i64_valid 123 #define TCG_TARGET_extract_i64_valid(ofs, len) 1 124 #endif 125 126 /* Only one of DIV or DIV2 should be defined. */ 127 #if defined(TCG_TARGET_HAS_div_i32) 128 #define TCG_TARGET_HAS_div2_i32 0 129 #elif defined(TCG_TARGET_HAS_div2_i32) 130 #define TCG_TARGET_HAS_div_i32 0 131 #define TCG_TARGET_HAS_rem_i32 0 132 #endif 133 #if defined(TCG_TARGET_HAS_div_i64) 134 #define TCG_TARGET_HAS_div2_i64 0 135 #elif defined(TCG_TARGET_HAS_div2_i64) 136 #define TCG_TARGET_HAS_div_i64 0 137 #define TCG_TARGET_HAS_rem_i64 0 138 #endif 139 140 #if !defined(TCG_TARGET_HAS_v64) \ 141 && !defined(TCG_TARGET_HAS_v128) \ 142 && !defined(TCG_TARGET_HAS_v256) 143 #define TCG_TARGET_MAYBE_vec 0 144 #define TCG_TARGET_HAS_abs_vec 0 145 #define TCG_TARGET_HAS_neg_vec 0 146 #define TCG_TARGET_HAS_not_vec 0 147 #define TCG_TARGET_HAS_andc_vec 0 148 #define TCG_TARGET_HAS_orc_vec 0 149 #define TCG_TARGET_HAS_nand_vec 0 150 #define TCG_TARGET_HAS_nor_vec 0 151 #define TCG_TARGET_HAS_eqv_vec 0 152 #define TCG_TARGET_HAS_roti_vec 0 153 #define TCG_TARGET_HAS_rots_vec 0 154 #define TCG_TARGET_HAS_rotv_vec 0 155 #define TCG_TARGET_HAS_shi_vec 0 156 #define TCG_TARGET_HAS_shs_vec 0 157 #define TCG_TARGET_HAS_shv_vec 0 158 #define TCG_TARGET_HAS_mul_vec 0 159 #define TCG_TARGET_HAS_sat_vec 0 160 #define TCG_TARGET_HAS_minmax_vec 0 161 #define TCG_TARGET_HAS_bitsel_vec 0 162 #define TCG_TARGET_HAS_cmpsel_vec 0 163 #else 164 #define TCG_TARGET_MAYBE_vec 1 165 #endif 166 #ifndef TCG_TARGET_HAS_v64 167 #define TCG_TARGET_HAS_v64 0 168 #endif 169 #ifndef TCG_TARGET_HAS_v128 170 #define TCG_TARGET_HAS_v128 0 171 #endif 172 #ifndef TCG_TARGET_HAS_v256 173 #define TCG_TARGET_HAS_v256 0 174 #endif 175 176 #ifndef TARGET_INSN_START_EXTRA_WORDS 177 # define TARGET_INSN_START_WORDS 1 178 #else 179 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) 180 #endif 181 182 typedef enum TCGOpcode { 183 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, 184 #include "tcg/tcg-opc.h" 185 #undef DEF 186 NB_OPS, 187 } TCGOpcode; 188 189 #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) 190 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r))) 191 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) 192 193 #ifndef TCG_TARGET_INSN_UNIT_SIZE 194 # error "Missing TCG_TARGET_INSN_UNIT_SIZE" 195 #elif TCG_TARGET_INSN_UNIT_SIZE == 1 196 typedef uint8_t tcg_insn_unit; 197 #elif TCG_TARGET_INSN_UNIT_SIZE == 2 198 typedef uint16_t tcg_insn_unit; 199 #elif TCG_TARGET_INSN_UNIT_SIZE == 4 200 typedef uint32_t tcg_insn_unit; 201 #elif TCG_TARGET_INSN_UNIT_SIZE == 8 202 typedef uint64_t tcg_insn_unit; 203 #else 204 /* The port better have done this. */ 205 #endif 206 207 typedef struct TCGRelocation TCGRelocation; 208 struct TCGRelocation { 209 QSIMPLEQ_ENTRY(TCGRelocation) next; 210 tcg_insn_unit *ptr; 211 intptr_t addend; 212 int type; 213 }; 214 215 typedef struct TCGOp TCGOp; 216 typedef struct TCGLabelUse TCGLabelUse; 217 struct TCGLabelUse { 218 QSIMPLEQ_ENTRY(TCGLabelUse) next; 219 TCGOp *op; 220 }; 221 222 typedef struct TCGLabel TCGLabel; 223 struct TCGLabel { 224 bool present; 225 bool has_value; 226 uint16_t id; 227 union { 228 uintptr_t value; 229 const tcg_insn_unit *value_ptr; 230 } u; 231 QSIMPLEQ_HEAD(, TCGLabelUse) branches; 232 QSIMPLEQ_HEAD(, TCGRelocation) relocs; 233 QSIMPLEQ_ENTRY(TCGLabel) next; 234 }; 235 236 typedef struct TCGPool { 237 struct TCGPool *next; 238 int size; 239 uint8_t data[] __attribute__ ((aligned)); 240 } TCGPool; 241 242 #define TCG_POOL_CHUNK_SIZE 32768 243 244 #define TCG_MAX_TEMPS 512 245 #define TCG_MAX_INSNS 512 246 247 /* when the size of the arguments of a called function is smaller than 248 this value, they are statically allocated in the TB stack frame */ 249 #define TCG_STATIC_CALL_ARGS_SIZE 128 250 251 typedef enum TCGType { 252 TCG_TYPE_I32, 253 TCG_TYPE_I64, 254 TCG_TYPE_I128, 255 256 TCG_TYPE_V64, 257 TCG_TYPE_V128, 258 TCG_TYPE_V256, 259 260 /* Number of different types (integer not enum) */ 261 #define TCG_TYPE_COUNT (TCG_TYPE_V256 + 1) 262 263 /* An alias for the size of the host register. */ 264 #if TCG_TARGET_REG_BITS == 32 265 TCG_TYPE_REG = TCG_TYPE_I32, 266 #else 267 TCG_TYPE_REG = TCG_TYPE_I64, 268 #endif 269 270 /* An alias for the size of the native pointer. */ 271 #if UINTPTR_MAX == UINT32_MAX 272 TCG_TYPE_PTR = TCG_TYPE_I32, 273 #else 274 TCG_TYPE_PTR = TCG_TYPE_I64, 275 #endif 276 } TCGType; 277 278 /** 279 * tcg_type_size 280 * @t: type 281 * 282 * Return the size of the type in bytes. 283 */ 284 static inline int tcg_type_size(TCGType t) 285 { 286 unsigned i = t; 287 if (i >= TCG_TYPE_V64) { 288 tcg_debug_assert(i < TCG_TYPE_COUNT); 289 i -= TCG_TYPE_V64 - 1; 290 } 291 return 4 << i; 292 } 293 294 /** 295 * get_alignment_bits 296 * @memop: MemOp value 297 * 298 * Extract the alignment size from the memop. 299 */ 300 static inline unsigned get_alignment_bits(MemOp memop) 301 { 302 unsigned a = memop & MO_AMASK; 303 304 if (a == MO_UNALN) { 305 /* No alignment required. */ 306 a = 0; 307 } else if (a == MO_ALIGN) { 308 /* A natural alignment requirement. */ 309 a = memop & MO_SIZE; 310 } else { 311 /* A specific alignment requirement. */ 312 a = a >> MO_ASHIFT; 313 } 314 #if defined(CONFIG_SOFTMMU) 315 /* The requested alignment cannot overlap the TLB flags. */ 316 tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0); 317 #endif 318 return a; 319 } 320 321 typedef tcg_target_ulong TCGArg; 322 323 /* Define type and accessor macros for TCG variables. 324 325 TCG variables are the inputs and outputs of TCG ops, as described 326 in tcg/README. Target CPU front-end code uses these types to deal 327 with TCG variables as it emits TCG code via the tcg_gen_* functions. 328 They come in several flavours: 329 * TCGv_i32 : 32 bit integer type 330 * TCGv_i64 : 64 bit integer type 331 * TCGv_i128 : 128 bit integer type 332 * TCGv_ptr : a host pointer type 333 * TCGv_vec : a host vector type; the exact size is not exposed 334 to the CPU front-end code. 335 * TCGv : an integer type the same size as target_ulong 336 (an alias for either TCGv_i32 or TCGv_i64) 337 The compiler's type checking will complain if you mix them 338 up and pass the wrong sized TCGv to a function. 339 340 Users of tcg_gen_* don't need to know about any of the internal 341 details of these, and should treat them as opaque types. 342 You won't be able to look inside them in a debugger either. 343 344 Internal implementation details follow: 345 346 Note that there is no definition of the structs TCGv_i32_d etc anywhere. 347 This is deliberate, because the values we store in variables of type 348 TCGv_i32 are not really pointers-to-structures. They're just small 349 integers, but keeping them in pointer types like this means that the 350 compiler will complain if you accidentally pass a TCGv_i32 to a 351 function which takes a TCGv_i64, and so on. Only the internals of 352 TCG need to care about the actual contents of the types. */ 353 354 typedef struct TCGv_i32_d *TCGv_i32; 355 typedef struct TCGv_i64_d *TCGv_i64; 356 typedef struct TCGv_i128_d *TCGv_i128; 357 typedef struct TCGv_ptr_d *TCGv_ptr; 358 typedef struct TCGv_vec_d *TCGv_vec; 359 typedef TCGv_ptr TCGv_env; 360 361 /* call flags */ 362 /* Helper does not read globals (either directly or through an exception). It 363 implies TCG_CALL_NO_WRITE_GLOBALS. */ 364 #define TCG_CALL_NO_READ_GLOBALS 0x0001 365 /* Helper does not write globals */ 366 #define TCG_CALL_NO_WRITE_GLOBALS 0x0002 367 /* Helper can be safely suppressed if the return value is not used. */ 368 #define TCG_CALL_NO_SIDE_EFFECTS 0x0004 369 /* Helper is G_NORETURN. */ 370 #define TCG_CALL_NO_RETURN 0x0008 371 /* Helper is part of Plugins. */ 372 #define TCG_CALL_PLUGIN 0x0010 373 374 /* convenience version of most used call flags */ 375 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS 376 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS 377 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS 378 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) 379 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) 380 381 /* 382 * Flags for the bswap opcodes. 383 * If IZ, the input is zero-extended, otherwise unknown. 384 * If OZ or OS, the output is zero- or sign-extended respectively, 385 * otherwise the high bits are undefined. 386 */ 387 enum { 388 TCG_BSWAP_IZ = 1, 389 TCG_BSWAP_OZ = 2, 390 TCG_BSWAP_OS = 4, 391 }; 392 393 typedef enum TCGTempVal { 394 TEMP_VAL_DEAD, 395 TEMP_VAL_REG, 396 TEMP_VAL_MEM, 397 TEMP_VAL_CONST, 398 } TCGTempVal; 399 400 typedef enum TCGTempKind { 401 /* 402 * Temp is dead at the end of the extended basic block (EBB), 403 * the single-entry multiple-exit region that falls through 404 * conditional branches. 405 */ 406 TEMP_EBB, 407 /* Temp is live across the entire translation block, but dead at end. */ 408 TEMP_TB, 409 /* Temp is live across the entire translation block, and between them. */ 410 TEMP_GLOBAL, 411 /* Temp is in a fixed register. */ 412 TEMP_FIXED, 413 /* Temp is a fixed constant. */ 414 TEMP_CONST, 415 } TCGTempKind; 416 417 typedef struct TCGTemp { 418 TCGReg reg:8; 419 TCGTempVal val_type:8; 420 TCGType base_type:8; 421 TCGType type:8; 422 TCGTempKind kind:3; 423 unsigned int indirect_reg:1; 424 unsigned int indirect_base:1; 425 unsigned int mem_coherent:1; 426 unsigned int mem_allocated:1; 427 unsigned int temp_allocated:1; 428 unsigned int temp_subindex:1; 429 430 int64_t val; 431 struct TCGTemp *mem_base; 432 intptr_t mem_offset; 433 const char *name; 434 435 /* Pass-specific information that can be stored for a temporary. 436 One word worth of integer data, and one pointer to data 437 allocated separately. */ 438 uintptr_t state; 439 void *state_ptr; 440 } TCGTemp; 441 442 typedef struct TCGContext TCGContext; 443 444 typedef struct TCGTempSet { 445 unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; 446 } TCGTempSet; 447 448 /* 449 * With 1 128-bit output, a 32-bit host requires 4 output parameters, 450 * which leaves a maximum of 28 other slots. Which is enough for 7 451 * 128-bit operands. 452 */ 453 #define DEAD_ARG (1 << 4) 454 #define SYNC_ARG (1 << 0) 455 typedef uint32_t TCGLifeData; 456 457 struct TCGOp { 458 TCGOpcode opc : 8; 459 unsigned nargs : 8; 460 461 /* Parameters for this opcode. See below. */ 462 unsigned param1 : 8; 463 unsigned param2 : 8; 464 465 /* Lifetime data of the operands. */ 466 TCGLifeData life; 467 468 /* Next and previous opcodes. */ 469 QTAILQ_ENTRY(TCGOp) link; 470 471 /* Register preferences for the output(s). */ 472 TCGRegSet output_pref[2]; 473 474 /* Arguments for the opcode. */ 475 TCGArg args[]; 476 }; 477 478 #define TCGOP_CALLI(X) (X)->param1 479 #define TCGOP_CALLO(X) (X)->param2 480 481 #define TCGOP_VECL(X) (X)->param1 482 #define TCGOP_VECE(X) (X)->param2 483 484 /* Make sure operands fit in the bitfields above. */ 485 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); 486 487 static inline TCGRegSet output_pref(const TCGOp *op, unsigned i) 488 { 489 return i < ARRAY_SIZE(op->output_pref) ? op->output_pref[i] : 0; 490 } 491 492 typedef struct TCGProfile { 493 int64_t cpu_exec_time; 494 int64_t tb_count1; 495 int64_t tb_count; 496 int64_t op_count; /* total insn count */ 497 int op_count_max; /* max insn per TB */ 498 int temp_count_max; 499 int64_t temp_count; 500 int64_t del_op_count; 501 int64_t code_in_len; 502 int64_t code_out_len; 503 int64_t search_out_len; 504 int64_t interm_time; 505 int64_t code_time; 506 int64_t la_time; 507 int64_t opt_time; 508 int64_t restore_count; 509 int64_t restore_time; 510 int64_t table_op_count[NB_OPS]; 511 } TCGProfile; 512 513 struct TCGContext { 514 uint8_t *pool_cur, *pool_end; 515 TCGPool *pool_first, *pool_current, *pool_first_large; 516 int nb_labels; 517 int nb_globals; 518 int nb_temps; 519 int nb_indirects; 520 int nb_ops; 521 TCGType addr_type; /* TCG_TYPE_I32 or TCG_TYPE_I64 */ 522 523 #ifdef CONFIG_SOFTMMU 524 int tlb_fast_offset; 525 int page_mask; 526 uint8_t page_bits; 527 uint8_t tlb_dyn_max_bits; 528 #endif 529 530 TCGRegSet reserved_regs; 531 intptr_t current_frame_offset; 532 intptr_t frame_start; 533 intptr_t frame_end; 534 TCGTemp *frame_temp; 535 536 TranslationBlock *gen_tb; /* tb for which code is being generated */ 537 tcg_insn_unit *code_buf; /* pointer for start of tb */ 538 tcg_insn_unit *code_ptr; /* pointer for running end of tb */ 539 540 #ifdef CONFIG_PROFILER 541 TCGProfile prof; 542 #endif 543 544 #ifdef CONFIG_DEBUG_TCG 545 int goto_tb_issue_mask; 546 const TCGOpcode *vecop_list; 547 #endif 548 549 /* Code generation. Note that we specifically do not use tcg_insn_unit 550 here, because there's too much arithmetic throughout that relies 551 on addition and subtraction working on bytes. Rely on the GCC 552 extension that allows arithmetic on void*. */ 553 void *code_gen_buffer; 554 size_t code_gen_buffer_size; 555 void *code_gen_ptr; 556 void *data_gen_ptr; 557 558 /* Threshold to flush the translated code buffer. */ 559 void *code_gen_highwater; 560 561 /* Track which vCPU triggers events */ 562 CPUState *cpu; /* *_trans */ 563 564 /* These structures are private to tcg-target.c.inc. */ 565 #ifdef TCG_TARGET_NEED_LDST_LABELS 566 QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; 567 #endif 568 #ifdef TCG_TARGET_NEED_POOL_LABELS 569 struct TCGLabelPoolData *pool_labels; 570 #endif 571 572 TCGLabel *exitreq_label; 573 574 #ifdef CONFIG_PLUGIN 575 /* 576 * We keep one plugin_tb struct per TCGContext. Note that on every TB 577 * translation we clear but do not free its contents; this way we 578 * avoid a lot of malloc/free churn, since after a few TB's it's 579 * unlikely that we'll need to allocate either more instructions or more 580 * space for instructions (for variable-instruction-length ISAs). 581 */ 582 struct qemu_plugin_tb *plugin_tb; 583 584 /* descriptor of the instruction being translated */ 585 struct qemu_plugin_insn *plugin_insn; 586 #endif 587 588 GHashTable *const_table[TCG_TYPE_COUNT]; 589 TCGTempSet free_temps[TCG_TYPE_COUNT]; 590 TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ 591 592 QTAILQ_HEAD(, TCGOp) ops, free_ops; 593 QSIMPLEQ_HEAD(, TCGLabel) labels; 594 595 /* Tells which temporary holds a given register. 596 It does not take into account fixed registers */ 597 TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; 598 599 uint16_t gen_insn_end_off[TCG_MAX_INSNS]; 600 uint64_t gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; 601 602 /* Exit to translator on overflow. */ 603 sigjmp_buf jmp_trans; 604 }; 605 606 static inline bool temp_readonly(TCGTemp *ts) 607 { 608 return ts->kind >= TEMP_FIXED; 609 } 610 611 extern __thread TCGContext *tcg_ctx; 612 extern const void *tcg_code_gen_epilogue; 613 extern uintptr_t tcg_splitwx_diff; 614 extern TCGv_env cpu_env; 615 616 bool in_code_gen_buffer(const void *p); 617 618 #ifdef CONFIG_DEBUG_TCG 619 const void *tcg_splitwx_to_rx(void *rw); 620 void *tcg_splitwx_to_rw(const void *rx); 621 #else 622 static inline const void *tcg_splitwx_to_rx(void *rw) 623 { 624 return rw ? rw + tcg_splitwx_diff : NULL; 625 } 626 627 static inline void *tcg_splitwx_to_rw(const void *rx) 628 { 629 return rx ? (void *)rx - tcg_splitwx_diff : NULL; 630 } 631 #endif 632 633 static inline size_t temp_idx(TCGTemp *ts) 634 { 635 ptrdiff_t n = ts - tcg_ctx->temps; 636 tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps); 637 return n; 638 } 639 640 static inline TCGArg temp_arg(TCGTemp *ts) 641 { 642 return (uintptr_t)ts; 643 } 644 645 static inline TCGTemp *arg_temp(TCGArg a) 646 { 647 return (TCGTemp *)(uintptr_t)a; 648 } 649 650 /* Using the offset of a temporary, relative to TCGContext, rather than 651 its index means that we don't use 0. That leaves offset 0 free for 652 a NULL representation without having to leave index 0 unused. */ 653 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) 654 { 655 uintptr_t o = (uintptr_t)v; 656 TCGTemp *t = (void *)tcg_ctx + o; 657 tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o); 658 return t; 659 } 660 661 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) 662 { 663 return tcgv_i32_temp((TCGv_i32)v); 664 } 665 666 static inline TCGTemp *tcgv_i128_temp(TCGv_i128 v) 667 { 668 return tcgv_i32_temp((TCGv_i32)v); 669 } 670 671 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) 672 { 673 return tcgv_i32_temp((TCGv_i32)v); 674 } 675 676 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v) 677 { 678 return tcgv_i32_temp((TCGv_i32)v); 679 } 680 681 static inline TCGArg tcgv_i32_arg(TCGv_i32 v) 682 { 683 return temp_arg(tcgv_i32_temp(v)); 684 } 685 686 static inline TCGArg tcgv_i64_arg(TCGv_i64 v) 687 { 688 return temp_arg(tcgv_i64_temp(v)); 689 } 690 691 static inline TCGArg tcgv_i128_arg(TCGv_i128 v) 692 { 693 return temp_arg(tcgv_i128_temp(v)); 694 } 695 696 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) 697 { 698 return temp_arg(tcgv_ptr_temp(v)); 699 } 700 701 static inline TCGArg tcgv_vec_arg(TCGv_vec v) 702 { 703 return temp_arg(tcgv_vec_temp(v)); 704 } 705 706 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) 707 { 708 (void)temp_idx(t); /* trigger embedded assert */ 709 return (TCGv_i32)((void *)t - (void *)tcg_ctx); 710 } 711 712 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) 713 { 714 return (TCGv_i64)temp_tcgv_i32(t); 715 } 716 717 static inline TCGv_i128 temp_tcgv_i128(TCGTemp *t) 718 { 719 return (TCGv_i128)temp_tcgv_i32(t); 720 } 721 722 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) 723 { 724 return (TCGv_ptr)temp_tcgv_i32(t); 725 } 726 727 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) 728 { 729 return (TCGv_vec)temp_tcgv_i32(t); 730 } 731 732 static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) 733 { 734 return op->args[arg]; 735 } 736 737 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) 738 { 739 op->args[arg] = v; 740 } 741 742 static inline uint64_t tcg_get_insn_start_param(TCGOp *op, int arg) 743 { 744 if (TCG_TARGET_REG_BITS == 64) { 745 return tcg_get_insn_param(op, arg); 746 } else { 747 return deposit64(tcg_get_insn_param(op, arg * 2), 32, 32, 748 tcg_get_insn_param(op, arg * 2 + 1)); 749 } 750 } 751 752 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, uint64_t v) 753 { 754 if (TCG_TARGET_REG_BITS == 64) { 755 tcg_set_insn_param(op, arg, v); 756 } else { 757 tcg_set_insn_param(op, arg * 2, v); 758 tcg_set_insn_param(op, arg * 2 + 1, v >> 32); 759 } 760 } 761 762 /* The last op that was emitted. */ 763 static inline TCGOp *tcg_last_op(void) 764 { 765 return QTAILQ_LAST(&tcg_ctx->ops); 766 } 767 768 /* Test for whether to terminate the TB for using too many opcodes. */ 769 static inline bool tcg_op_buf_full(void) 770 { 771 /* This is not a hard limit, it merely stops translation when 772 * we have produced "enough" opcodes. We want to limit TB size 773 * such that a RISC host can reasonably use a 16-bit signed 774 * branch within the TB. We also need to be mindful of the 775 * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[] 776 * and TCGContext.gen_insn_end_off[]. 777 */ 778 return tcg_ctx->nb_ops >= 4000; 779 } 780 781 /* pool based memory allocation */ 782 783 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */ 784 void *tcg_malloc_internal(TCGContext *s, int size); 785 void tcg_pool_reset(TCGContext *s); 786 TranslationBlock *tcg_tb_alloc(TCGContext *s); 787 788 void tcg_region_reset_all(void); 789 790 size_t tcg_code_size(void); 791 size_t tcg_code_capacity(void); 792 793 void tcg_tb_insert(TranslationBlock *tb); 794 void tcg_tb_remove(TranslationBlock *tb); 795 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr); 796 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data); 797 size_t tcg_nb_tbs(void); 798 799 /* user-mode: Called with mmap_lock held. */ 800 static inline void *tcg_malloc(int size) 801 { 802 TCGContext *s = tcg_ctx; 803 uint8_t *ptr, *ptr_end; 804 805 /* ??? This is a weak placeholder for minimum malloc alignment. */ 806 size = QEMU_ALIGN_UP(size, 8); 807 808 ptr = s->pool_cur; 809 ptr_end = ptr + size; 810 if (unlikely(ptr_end > s->pool_end)) { 811 return tcg_malloc_internal(tcg_ctx, size); 812 } else { 813 s->pool_cur = ptr_end; 814 return ptr; 815 } 816 } 817 818 void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus); 819 void tcg_register_thread(void); 820 void tcg_prologue_init(TCGContext *s); 821 void tcg_func_start(TCGContext *s); 822 823 int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start); 824 825 void tb_target_set_jmp_target(const TranslationBlock *, int, 826 uintptr_t, uintptr_t); 827 828 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); 829 830 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, 831 intptr_t, const char *); 832 TCGTemp *tcg_temp_new_internal(TCGType, TCGTempKind); 833 TCGv_vec tcg_temp_new_vec(TCGType type); 834 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); 835 836 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, 837 const char *name) 838 { 839 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name); 840 return temp_tcgv_i32(t); 841 } 842 843 static inline TCGv_i32 tcg_temp_new_i32(void) 844 { 845 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_TB); 846 return temp_tcgv_i32(t); 847 } 848 849 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, 850 const char *name) 851 { 852 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name); 853 return temp_tcgv_i64(t); 854 } 855 856 static inline TCGv_i64 tcg_temp_new_i64(void) 857 { 858 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_TB); 859 return temp_tcgv_i64(t); 860 } 861 862 static inline TCGv_i128 tcg_temp_new_i128(void) 863 { 864 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_TB); 865 return temp_tcgv_i128(t); 866 } 867 868 static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, 869 const char *name) 870 { 871 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name); 872 return temp_tcgv_ptr(t); 873 } 874 875 static inline TCGv_ptr tcg_temp_new_ptr(void) 876 { 877 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_TB); 878 return temp_tcgv_ptr(t); 879 } 880 881 int64_t tcg_cpu_exec_time(void); 882 void tcg_dump_info(GString *buf); 883 void tcg_dump_op_count(GString *buf); 884 885 #define TCG_CT_CONST 1 /* any constant of register size */ 886 887 typedef struct TCGArgConstraint { 888 unsigned ct : 16; 889 unsigned alias_index : 4; 890 unsigned sort_index : 4; 891 unsigned pair_index : 4; 892 unsigned pair : 2; /* 0: none, 1: first, 2: second, 3: second alias */ 893 bool oalias : 1; 894 bool ialias : 1; 895 bool newreg : 1; 896 TCGRegSet regs; 897 } TCGArgConstraint; 898 899 #define TCG_MAX_OP_ARGS 16 900 901 /* Bits for TCGOpDef->flags, 8 bits available, all used. */ 902 enum { 903 /* Instruction exits the translation block. */ 904 TCG_OPF_BB_EXIT = 0x01, 905 /* Instruction defines the end of a basic block. */ 906 TCG_OPF_BB_END = 0x02, 907 /* Instruction clobbers call registers and potentially update globals. */ 908 TCG_OPF_CALL_CLOBBER = 0x04, 909 /* Instruction has side effects: it cannot be removed if its outputs 910 are not used, and might trigger exceptions. */ 911 TCG_OPF_SIDE_EFFECTS = 0x08, 912 /* Instruction operands are 64-bits (otherwise 32-bits). */ 913 TCG_OPF_64BIT = 0x10, 914 /* Instruction is optional and not implemented by the host, or insn 915 is generic and should not be implemened by the host. */ 916 TCG_OPF_NOT_PRESENT = 0x20, 917 /* Instruction operands are vectors. */ 918 TCG_OPF_VECTOR = 0x40, 919 /* Instruction is a conditional branch. */ 920 TCG_OPF_COND_BRANCH = 0x80 921 }; 922 923 typedef struct TCGOpDef { 924 const char *name; 925 uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; 926 uint8_t flags; 927 TCGArgConstraint *args_ct; 928 } TCGOpDef; 929 930 extern TCGOpDef tcg_op_defs[]; 931 extern const size_t tcg_op_defs_max; 932 933 typedef struct TCGTargetOpDef { 934 TCGOpcode op; 935 const char *args_ct_str[TCG_MAX_OP_ARGS]; 936 } TCGTargetOpDef; 937 938 bool tcg_op_supported(TCGOpcode op); 939 940 void tcg_gen_callN(TCGHelperInfo *, TCGTemp *ret, int nargs, TCGTemp **args); 941 942 TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs); 943 void tcg_op_remove(TCGContext *s, TCGOp *op); 944 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, 945 TCGOpcode opc, unsigned nargs); 946 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, 947 TCGOpcode opc, unsigned nargs); 948 949 /** 950 * tcg_remove_ops_after: 951 * @op: target operation 952 * 953 * Discard any opcodes emitted since @op. Expected usage is to save 954 * a starting point with tcg_last_op(), speculatively emit opcodes, 955 * then decide whether or not to keep those opcodes after the fact. 956 */ 957 void tcg_remove_ops_after(TCGOp *op); 958 959 void tcg_optimize(TCGContext *s); 960 961 /* 962 * Locate or create a read-only temporary that is a constant. 963 * This kind of temporary need not be freed, but for convenience 964 * will be silently ignored by tcg_temp_free_*. 965 */ 966 TCGTemp *tcg_constant_internal(TCGType type, int64_t val); 967 968 static inline TCGv_i32 tcg_constant_i32(int32_t val) 969 { 970 return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); 971 } 972 973 static inline TCGv_i64 tcg_constant_i64(int64_t val) 974 { 975 return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); 976 } 977 978 TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); 979 TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); 980 981 #if UINTPTR_MAX == UINT32_MAX 982 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x))) 983 #else 984 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x))) 985 #endif 986 987 TCGLabel *gen_new_label(void); 988 989 /** 990 * label_arg 991 * @l: label 992 * 993 * Encode a label for storage in the TCG opcode stream. 994 */ 995 996 static inline TCGArg label_arg(TCGLabel *l) 997 { 998 return (uintptr_t)l; 999 } 1000 1001 /** 1002 * arg_label 1003 * @i: value 1004 * 1005 * The opposite of label_arg. Retrieve a label from the 1006 * encoding of the TCG opcode stream. 1007 */ 1008 1009 static inline TCGLabel *arg_label(TCGArg i) 1010 { 1011 return (TCGLabel *)(uintptr_t)i; 1012 } 1013 1014 /** 1015 * tcg_ptr_byte_diff 1016 * @a, @b: addresses to be differenced 1017 * 1018 * There are many places within the TCG backends where we need a byte 1019 * difference between two pointers. While this can be accomplished 1020 * with local casting, it's easy to get wrong -- especially if one is 1021 * concerned with the signedness of the result. 1022 * 1023 * This version relies on GCC's void pointer arithmetic to get the 1024 * correct result. 1025 */ 1026 1027 static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) 1028 { 1029 return a - b; 1030 } 1031 1032 /** 1033 * tcg_pcrel_diff 1034 * @s: the tcg context 1035 * @target: address of the target 1036 * 1037 * Produce a pc-relative difference, from the current code_ptr 1038 * to the destination address. 1039 */ 1040 1041 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) 1042 { 1043 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); 1044 } 1045 1046 /** 1047 * tcg_tbrel_diff 1048 * @s: the tcg context 1049 * @target: address of the target 1050 * 1051 * Produce a difference, from the beginning of the current TB code 1052 * to the destination address. 1053 */ 1054 static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, const void *target) 1055 { 1056 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_buf)); 1057 } 1058 1059 /** 1060 * tcg_current_code_size 1061 * @s: the tcg context 1062 * 1063 * Compute the current code size within the translation block. 1064 * This is used to fill in qemu's data structures for goto_tb. 1065 */ 1066 1067 static inline size_t tcg_current_code_size(TCGContext *s) 1068 { 1069 return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); 1070 } 1071 1072 /** 1073 * tcg_qemu_tb_exec: 1074 * @env: pointer to CPUArchState for the CPU 1075 * @tb_ptr: address of generated code for the TB to execute 1076 * 1077 * Start executing code from a given translation block. 1078 * Where translation blocks have been linked, execution 1079 * may proceed from the given TB into successive ones. 1080 * Control eventually returns only when some action is needed 1081 * from the top-level loop: either control must pass to a TB 1082 * which has not yet been directly linked, or an asynchronous 1083 * event such as an interrupt needs handling. 1084 * 1085 * Return: The return value is the value passed to the corresponding 1086 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute. 1087 * The value is either zero or a 4-byte aligned pointer to that TB combined 1088 * with additional information in its two least significant bits. The 1089 * additional information is encoded as follows: 1090 * 0, 1: the link between this TB and the next is via the specified 1091 * TB index (0 or 1). That is, we left the TB via (the equivalent 1092 * of) "goto_tb <index>". The main loop uses this to determine 1093 * how to link the TB just executed to the next. 1094 * 2: we are using instruction counting code generation, and we 1095 * did not start executing this TB because the instruction counter 1096 * would hit zero midway through it. In this case the pointer 1097 * returned is the TB we were about to execute, and the caller must 1098 * arrange to execute the remaining count of instructions. 1099 * 3: we stopped because the CPU's exit_request flag was set 1100 * (usually meaning that there is an interrupt that needs to be 1101 * handled). The pointer returned is the TB we were about to execute 1102 * when we noticed the pending exit request. 1103 * 1104 * If the bottom two bits indicate an exit-via-index then the CPU 1105 * state is correctly synchronised and ready for execution of the next 1106 * TB (and in particular the guest PC is the address to execute next). 1107 * Otherwise, we gave up on execution of this TB before it started, and 1108 * the caller must fix up the CPU state by calling the CPU's 1109 * synchronize_from_tb() method with the TB pointer we return (falling 1110 * back to calling the CPU's set_pc method with tb->pb if no 1111 * synchronize_from_tb() method exists). 1112 * 1113 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec 1114 * to this default (which just calls the prologue.code emitted by 1115 * tcg_target_qemu_prologue()). 1116 */ 1117 #define TB_EXIT_MASK 3 1118 #define TB_EXIT_IDX0 0 1119 #define TB_EXIT_IDX1 1 1120 #define TB_EXIT_IDXMAX 1 1121 #define TB_EXIT_REQUESTED 3 1122 1123 #ifdef CONFIG_TCG_INTERPRETER 1124 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); 1125 #else 1126 typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); 1127 extern tcg_prologue_fn *tcg_qemu_tb_exec; 1128 #endif 1129 1130 void tcg_register_jit(const void *buf, size_t buf_size); 1131 1132 #if TCG_TARGET_MAYBE_vec 1133 /* Return zero if the tuple (opc, type, vece) is unsupportable; 1134 return > 0 if it is directly supportable; 1135 return < 0 if we must call tcg_expand_vec_op. */ 1136 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned); 1137 #else 1138 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) 1139 { 1140 return 0; 1141 } 1142 #endif 1143 1144 /* Expand the tuple (opc, type, vece) on the given arguments. */ 1145 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...); 1146 1147 /* Replicate a constant C accoring to the log2 of the element size. */ 1148 uint64_t dup_const(unsigned vece, uint64_t c); 1149 1150 #define dup_const(VECE, C) \ 1151 (__builtin_constant_p(VECE) \ 1152 ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \ 1153 : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \ 1154 : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \ 1155 : (VECE) == MO_64 ? (uint64_t)(C) \ 1156 : (qemu_build_not_reached_always(), 0)) \ 1157 : dup_const(VECE, C)) 1158 1159 #ifdef CONFIG_DEBUG_TCG 1160 void tcg_assert_listed_vecop(TCGOpcode); 1161 #else 1162 static inline void tcg_assert_listed_vecop(TCGOpcode op) { } 1163 #endif 1164 1165 static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n) 1166 { 1167 #ifdef CONFIG_DEBUG_TCG 1168 const TCGOpcode *o = tcg_ctx->vecop_list; 1169 tcg_ctx->vecop_list = n; 1170 return o; 1171 #else 1172 return NULL; 1173 #endif 1174 } 1175 1176 bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned); 1177 1178 #endif /* TCG_H */ 1179