1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef TCG_H 26 #define TCG_H 27 28 #include "cpu.h" 29 #include "exec/memop.h" 30 #include "exec/memopidx.h" 31 #include "qemu/bitops.h" 32 #include "qemu/plugin.h" 33 #include "qemu/queue.h" 34 #include "tcg/tcg-mo.h" 35 #include "tcg-target-reg-bits.h" 36 #include "tcg-target.h" 37 #include "tcg/tcg-cond.h" 38 #include "tcg/debug-assert.h" 39 40 /* XXX: make safe guess about sizes */ 41 #define MAX_OP_PER_INSTR 266 42 43 #define MAX_CALL_IARGS 7 44 45 #define CPU_TEMP_BUF_NLONGS 128 46 #define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) 47 48 #if TCG_TARGET_REG_BITS == 32 49 typedef int32_t tcg_target_long; 50 typedef uint32_t tcg_target_ulong; 51 #define TCG_PRIlx PRIx32 52 #define TCG_PRIld PRId32 53 #elif TCG_TARGET_REG_BITS == 64 54 typedef int64_t tcg_target_long; 55 typedef uint64_t tcg_target_ulong; 56 #define TCG_PRIlx PRIx64 57 #define TCG_PRIld PRId64 58 #else 59 #error unsupported 60 #endif 61 62 /* Oversized TCG guests make things like MTTCG hard 63 * as we can't use atomics for cputlb updates. 64 */ 65 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS 66 #define TCG_OVERSIZED_GUEST 1 67 #else 68 #define TCG_OVERSIZED_GUEST 0 69 #endif 70 71 #if TCG_TARGET_NB_REGS <= 32 72 typedef uint32_t TCGRegSet; 73 #elif TCG_TARGET_NB_REGS <= 64 74 typedef uint64_t TCGRegSet; 75 #else 76 #error unsupported 77 #endif 78 79 #if TCG_TARGET_REG_BITS == 32 80 /* Turn some undef macros into false macros. */ 81 #define TCG_TARGET_HAS_extrl_i64_i32 0 82 #define TCG_TARGET_HAS_extrh_i64_i32 0 83 #define TCG_TARGET_HAS_div_i64 0 84 #define TCG_TARGET_HAS_rem_i64 0 85 #define TCG_TARGET_HAS_div2_i64 0 86 #define TCG_TARGET_HAS_rot_i64 0 87 #define TCG_TARGET_HAS_ext8s_i64 0 88 #define TCG_TARGET_HAS_ext16s_i64 0 89 #define TCG_TARGET_HAS_ext32s_i64 0 90 #define TCG_TARGET_HAS_ext8u_i64 0 91 #define TCG_TARGET_HAS_ext16u_i64 0 92 #define TCG_TARGET_HAS_ext32u_i64 0 93 #define TCG_TARGET_HAS_bswap16_i64 0 94 #define TCG_TARGET_HAS_bswap32_i64 0 95 #define TCG_TARGET_HAS_bswap64_i64 0 96 #define TCG_TARGET_HAS_neg_i64 0 97 #define TCG_TARGET_HAS_not_i64 0 98 #define TCG_TARGET_HAS_andc_i64 0 99 #define TCG_TARGET_HAS_orc_i64 0 100 #define TCG_TARGET_HAS_eqv_i64 0 101 #define TCG_TARGET_HAS_nand_i64 0 102 #define TCG_TARGET_HAS_nor_i64 0 103 #define TCG_TARGET_HAS_clz_i64 0 104 #define TCG_TARGET_HAS_ctz_i64 0 105 #define TCG_TARGET_HAS_ctpop_i64 0 106 #define TCG_TARGET_HAS_deposit_i64 0 107 #define TCG_TARGET_HAS_extract_i64 0 108 #define TCG_TARGET_HAS_sextract_i64 0 109 #define TCG_TARGET_HAS_extract2_i64 0 110 #define TCG_TARGET_HAS_movcond_i64 0 111 #define TCG_TARGET_HAS_add2_i64 0 112 #define TCG_TARGET_HAS_sub2_i64 0 113 #define TCG_TARGET_HAS_mulu2_i64 0 114 #define TCG_TARGET_HAS_muls2_i64 0 115 #define TCG_TARGET_HAS_muluh_i64 0 116 #define TCG_TARGET_HAS_mulsh_i64 0 117 /* Turn some undef macros into true macros. */ 118 #define TCG_TARGET_HAS_add2_i32 1 119 #define TCG_TARGET_HAS_sub2_i32 1 120 #endif 121 122 #ifndef TCG_TARGET_deposit_i32_valid 123 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 124 #endif 125 #ifndef TCG_TARGET_deposit_i64_valid 126 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 127 #endif 128 #ifndef TCG_TARGET_extract_i32_valid 129 #define TCG_TARGET_extract_i32_valid(ofs, len) 1 130 #endif 131 #ifndef TCG_TARGET_extract_i64_valid 132 #define TCG_TARGET_extract_i64_valid(ofs, len) 1 133 #endif 134 135 /* Only one of DIV or DIV2 should be defined. */ 136 #if defined(TCG_TARGET_HAS_div_i32) 137 #define TCG_TARGET_HAS_div2_i32 0 138 #elif defined(TCG_TARGET_HAS_div2_i32) 139 #define TCG_TARGET_HAS_div_i32 0 140 #define TCG_TARGET_HAS_rem_i32 0 141 #endif 142 #if defined(TCG_TARGET_HAS_div_i64) 143 #define TCG_TARGET_HAS_div2_i64 0 144 #elif defined(TCG_TARGET_HAS_div2_i64) 145 #define TCG_TARGET_HAS_div_i64 0 146 #define TCG_TARGET_HAS_rem_i64 0 147 #endif 148 149 #if !defined(TCG_TARGET_HAS_v64) \ 150 && !defined(TCG_TARGET_HAS_v128) \ 151 && !defined(TCG_TARGET_HAS_v256) 152 #define TCG_TARGET_MAYBE_vec 0 153 #define TCG_TARGET_HAS_abs_vec 0 154 #define TCG_TARGET_HAS_neg_vec 0 155 #define TCG_TARGET_HAS_not_vec 0 156 #define TCG_TARGET_HAS_andc_vec 0 157 #define TCG_TARGET_HAS_orc_vec 0 158 #define TCG_TARGET_HAS_nand_vec 0 159 #define TCG_TARGET_HAS_nor_vec 0 160 #define TCG_TARGET_HAS_eqv_vec 0 161 #define TCG_TARGET_HAS_roti_vec 0 162 #define TCG_TARGET_HAS_rots_vec 0 163 #define TCG_TARGET_HAS_rotv_vec 0 164 #define TCG_TARGET_HAS_shi_vec 0 165 #define TCG_TARGET_HAS_shs_vec 0 166 #define TCG_TARGET_HAS_shv_vec 0 167 #define TCG_TARGET_HAS_mul_vec 0 168 #define TCG_TARGET_HAS_sat_vec 0 169 #define TCG_TARGET_HAS_minmax_vec 0 170 #define TCG_TARGET_HAS_bitsel_vec 0 171 #define TCG_TARGET_HAS_cmpsel_vec 0 172 #else 173 #define TCG_TARGET_MAYBE_vec 1 174 #endif 175 #ifndef TCG_TARGET_HAS_v64 176 #define TCG_TARGET_HAS_v64 0 177 #endif 178 #ifndef TCG_TARGET_HAS_v128 179 #define TCG_TARGET_HAS_v128 0 180 #endif 181 #ifndef TCG_TARGET_HAS_v256 182 #define TCG_TARGET_HAS_v256 0 183 #endif 184 185 #ifndef TARGET_INSN_START_EXTRA_WORDS 186 # define TARGET_INSN_START_WORDS 1 187 #else 188 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) 189 #endif 190 191 typedef enum TCGOpcode { 192 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, 193 #include "tcg/tcg-opc.h" 194 #undef DEF 195 NB_OPS, 196 } TCGOpcode; 197 198 #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) 199 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r))) 200 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) 201 202 #ifndef TCG_TARGET_INSN_UNIT_SIZE 203 # error "Missing TCG_TARGET_INSN_UNIT_SIZE" 204 #elif TCG_TARGET_INSN_UNIT_SIZE == 1 205 typedef uint8_t tcg_insn_unit; 206 #elif TCG_TARGET_INSN_UNIT_SIZE == 2 207 typedef uint16_t tcg_insn_unit; 208 #elif TCG_TARGET_INSN_UNIT_SIZE == 4 209 typedef uint32_t tcg_insn_unit; 210 #elif TCG_TARGET_INSN_UNIT_SIZE == 8 211 typedef uint64_t tcg_insn_unit; 212 #else 213 /* The port better have done this. */ 214 #endif 215 216 typedef struct TCGRelocation TCGRelocation; 217 struct TCGRelocation { 218 QSIMPLEQ_ENTRY(TCGRelocation) next; 219 tcg_insn_unit *ptr; 220 intptr_t addend; 221 int type; 222 }; 223 224 typedef struct TCGOp TCGOp; 225 typedef struct TCGLabelUse TCGLabelUse; 226 struct TCGLabelUse { 227 QSIMPLEQ_ENTRY(TCGLabelUse) next; 228 TCGOp *op; 229 }; 230 231 typedef struct TCGLabel TCGLabel; 232 struct TCGLabel { 233 bool present; 234 bool has_value; 235 uint16_t id; 236 union { 237 uintptr_t value; 238 const tcg_insn_unit *value_ptr; 239 } u; 240 QSIMPLEQ_HEAD(, TCGLabelUse) branches; 241 QSIMPLEQ_HEAD(, TCGRelocation) relocs; 242 QSIMPLEQ_ENTRY(TCGLabel) next; 243 }; 244 245 typedef struct TCGPool { 246 struct TCGPool *next; 247 int size; 248 uint8_t data[] __attribute__ ((aligned)); 249 } TCGPool; 250 251 #define TCG_POOL_CHUNK_SIZE 32768 252 253 #define TCG_MAX_TEMPS 512 254 #define TCG_MAX_INSNS 512 255 256 /* when the size of the arguments of a called function is smaller than 257 this value, they are statically allocated in the TB stack frame */ 258 #define TCG_STATIC_CALL_ARGS_SIZE 128 259 260 typedef enum TCGType { 261 TCG_TYPE_I32, 262 TCG_TYPE_I64, 263 TCG_TYPE_I128, 264 265 TCG_TYPE_V64, 266 TCG_TYPE_V128, 267 TCG_TYPE_V256, 268 269 /* Number of different types (integer not enum) */ 270 #define TCG_TYPE_COUNT (TCG_TYPE_V256 + 1) 271 272 /* An alias for the size of the host register. */ 273 #if TCG_TARGET_REG_BITS == 32 274 TCG_TYPE_REG = TCG_TYPE_I32, 275 #else 276 TCG_TYPE_REG = TCG_TYPE_I64, 277 #endif 278 279 /* An alias for the size of the native pointer. */ 280 #if UINTPTR_MAX == UINT32_MAX 281 TCG_TYPE_PTR = TCG_TYPE_I32, 282 #else 283 TCG_TYPE_PTR = TCG_TYPE_I64, 284 #endif 285 } TCGType; 286 287 /** 288 * tcg_type_size 289 * @t: type 290 * 291 * Return the size of the type in bytes. 292 */ 293 static inline int tcg_type_size(TCGType t) 294 { 295 unsigned i = t; 296 if (i >= TCG_TYPE_V64) { 297 tcg_debug_assert(i < TCG_TYPE_COUNT); 298 i -= TCG_TYPE_V64 - 1; 299 } 300 return 4 << i; 301 } 302 303 /** 304 * get_alignment_bits 305 * @memop: MemOp value 306 * 307 * Extract the alignment size from the memop. 308 */ 309 static inline unsigned get_alignment_bits(MemOp memop) 310 { 311 unsigned a = memop & MO_AMASK; 312 313 if (a == MO_UNALN) { 314 /* No alignment required. */ 315 a = 0; 316 } else if (a == MO_ALIGN) { 317 /* A natural alignment requirement. */ 318 a = memop & MO_SIZE; 319 } else { 320 /* A specific alignment requirement. */ 321 a = a >> MO_ASHIFT; 322 } 323 #if defined(CONFIG_SOFTMMU) 324 /* The requested alignment cannot overlap the TLB flags. */ 325 tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0); 326 #endif 327 return a; 328 } 329 330 typedef tcg_target_ulong TCGArg; 331 332 /* Define type and accessor macros for TCG variables. 333 334 TCG variables are the inputs and outputs of TCG ops, as described 335 in tcg/README. Target CPU front-end code uses these types to deal 336 with TCG variables as it emits TCG code via the tcg_gen_* functions. 337 They come in several flavours: 338 * TCGv_i32 : 32 bit integer type 339 * TCGv_i64 : 64 bit integer type 340 * TCGv_i128 : 128 bit integer type 341 * TCGv_ptr : a host pointer type 342 * TCGv_vec : a host vector type; the exact size is not exposed 343 to the CPU front-end code. 344 * TCGv : an integer type the same size as target_ulong 345 (an alias for either TCGv_i32 or TCGv_i64) 346 The compiler's type checking will complain if you mix them 347 up and pass the wrong sized TCGv to a function. 348 349 Users of tcg_gen_* don't need to know about any of the internal 350 details of these, and should treat them as opaque types. 351 You won't be able to look inside them in a debugger either. 352 353 Internal implementation details follow: 354 355 Note that there is no definition of the structs TCGv_i32_d etc anywhere. 356 This is deliberate, because the values we store in variables of type 357 TCGv_i32 are not really pointers-to-structures. They're just small 358 integers, but keeping them in pointer types like this means that the 359 compiler will complain if you accidentally pass a TCGv_i32 to a 360 function which takes a TCGv_i64, and so on. Only the internals of 361 TCG need to care about the actual contents of the types. */ 362 363 typedef struct TCGv_i32_d *TCGv_i32; 364 typedef struct TCGv_i64_d *TCGv_i64; 365 typedef struct TCGv_i128_d *TCGv_i128; 366 typedef struct TCGv_ptr_d *TCGv_ptr; 367 typedef struct TCGv_vec_d *TCGv_vec; 368 typedef TCGv_ptr TCGv_env; 369 #if TARGET_LONG_BITS == 32 370 #define TCGv TCGv_i32 371 #elif TARGET_LONG_BITS == 64 372 #define TCGv TCGv_i64 373 #else 374 #error Unhandled TARGET_LONG_BITS value 375 #endif 376 377 /* call flags */ 378 /* Helper does not read globals (either directly or through an exception). It 379 implies TCG_CALL_NO_WRITE_GLOBALS. */ 380 #define TCG_CALL_NO_READ_GLOBALS 0x0001 381 /* Helper does not write globals */ 382 #define TCG_CALL_NO_WRITE_GLOBALS 0x0002 383 /* Helper can be safely suppressed if the return value is not used. */ 384 #define TCG_CALL_NO_SIDE_EFFECTS 0x0004 385 /* Helper is G_NORETURN. */ 386 #define TCG_CALL_NO_RETURN 0x0008 387 /* Helper is part of Plugins. */ 388 #define TCG_CALL_PLUGIN 0x0010 389 390 /* convenience version of most used call flags */ 391 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS 392 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS 393 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS 394 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) 395 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) 396 397 /* 398 * Flags for the bswap opcodes. 399 * If IZ, the input is zero-extended, otherwise unknown. 400 * If OZ or OS, the output is zero- or sign-extended respectively, 401 * otherwise the high bits are undefined. 402 */ 403 enum { 404 TCG_BSWAP_IZ = 1, 405 TCG_BSWAP_OZ = 2, 406 TCG_BSWAP_OS = 4, 407 }; 408 409 typedef enum TCGTempVal { 410 TEMP_VAL_DEAD, 411 TEMP_VAL_REG, 412 TEMP_VAL_MEM, 413 TEMP_VAL_CONST, 414 } TCGTempVal; 415 416 typedef enum TCGTempKind { 417 /* 418 * Temp is dead at the end of the extended basic block (EBB), 419 * the single-entry multiple-exit region that falls through 420 * conditional branches. 421 */ 422 TEMP_EBB, 423 /* Temp is live across the entire translation block, but dead at end. */ 424 TEMP_TB, 425 /* Temp is live across the entire translation block, and between them. */ 426 TEMP_GLOBAL, 427 /* Temp is in a fixed register. */ 428 TEMP_FIXED, 429 /* Temp is a fixed constant. */ 430 TEMP_CONST, 431 } TCGTempKind; 432 433 typedef struct TCGTemp { 434 TCGReg reg:8; 435 TCGTempVal val_type:8; 436 TCGType base_type:8; 437 TCGType type:8; 438 TCGTempKind kind:3; 439 unsigned int indirect_reg:1; 440 unsigned int indirect_base:1; 441 unsigned int mem_coherent:1; 442 unsigned int mem_allocated:1; 443 unsigned int temp_allocated:1; 444 unsigned int temp_subindex:1; 445 446 int64_t val; 447 struct TCGTemp *mem_base; 448 intptr_t mem_offset; 449 const char *name; 450 451 /* Pass-specific information that can be stored for a temporary. 452 One word worth of integer data, and one pointer to data 453 allocated separately. */ 454 uintptr_t state; 455 void *state_ptr; 456 } TCGTemp; 457 458 typedef struct TCGContext TCGContext; 459 460 typedef struct TCGTempSet { 461 unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; 462 } TCGTempSet; 463 464 /* 465 * With 1 128-bit output, a 32-bit host requires 4 output parameters, 466 * which leaves a maximum of 28 other slots. Which is enough for 7 467 * 128-bit operands. 468 */ 469 #define DEAD_ARG (1 << 4) 470 #define SYNC_ARG (1 << 0) 471 typedef uint32_t TCGLifeData; 472 473 struct TCGOp { 474 TCGOpcode opc : 8; 475 unsigned nargs : 8; 476 477 /* Parameters for this opcode. See below. */ 478 unsigned param1 : 8; 479 unsigned param2 : 8; 480 481 /* Lifetime data of the operands. */ 482 TCGLifeData life; 483 484 /* Next and previous opcodes. */ 485 QTAILQ_ENTRY(TCGOp) link; 486 487 /* Register preferences for the output(s). */ 488 TCGRegSet output_pref[2]; 489 490 /* Arguments for the opcode. */ 491 TCGArg args[]; 492 }; 493 494 #define TCGOP_CALLI(X) (X)->param1 495 #define TCGOP_CALLO(X) (X)->param2 496 497 #define TCGOP_VECL(X) (X)->param1 498 #define TCGOP_VECE(X) (X)->param2 499 500 /* Make sure operands fit in the bitfields above. */ 501 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); 502 503 static inline TCGRegSet output_pref(const TCGOp *op, unsigned i) 504 { 505 return i < ARRAY_SIZE(op->output_pref) ? op->output_pref[i] : 0; 506 } 507 508 typedef struct TCGProfile { 509 int64_t cpu_exec_time; 510 int64_t tb_count1; 511 int64_t tb_count; 512 int64_t op_count; /* total insn count */ 513 int op_count_max; /* max insn per TB */ 514 int temp_count_max; 515 int64_t temp_count; 516 int64_t del_op_count; 517 int64_t code_in_len; 518 int64_t code_out_len; 519 int64_t search_out_len; 520 int64_t interm_time; 521 int64_t code_time; 522 int64_t la_time; 523 int64_t opt_time; 524 int64_t restore_count; 525 int64_t restore_time; 526 int64_t table_op_count[NB_OPS]; 527 } TCGProfile; 528 529 struct TCGContext { 530 uint8_t *pool_cur, *pool_end; 531 TCGPool *pool_first, *pool_current, *pool_first_large; 532 int nb_labels; 533 int nb_globals; 534 int nb_temps; 535 int nb_indirects; 536 int nb_ops; 537 TCGType addr_type; /* TCG_TYPE_I32 or TCG_TYPE_I64 */ 538 539 #ifdef CONFIG_SOFTMMU 540 int tlb_fast_offset; 541 int page_mask; 542 uint8_t page_bits; 543 uint8_t tlb_dyn_max_bits; 544 #endif 545 546 TCGRegSet reserved_regs; 547 intptr_t current_frame_offset; 548 intptr_t frame_start; 549 intptr_t frame_end; 550 TCGTemp *frame_temp; 551 552 TranslationBlock *gen_tb; /* tb for which code is being generated */ 553 tcg_insn_unit *code_buf; /* pointer for start of tb */ 554 tcg_insn_unit *code_ptr; /* pointer for running end of tb */ 555 556 #ifdef CONFIG_PROFILER 557 TCGProfile prof; 558 #endif 559 560 #ifdef CONFIG_DEBUG_TCG 561 int goto_tb_issue_mask; 562 const TCGOpcode *vecop_list; 563 #endif 564 565 /* Code generation. Note that we specifically do not use tcg_insn_unit 566 here, because there's too much arithmetic throughout that relies 567 on addition and subtraction working on bytes. Rely on the GCC 568 extension that allows arithmetic on void*. */ 569 void *code_gen_buffer; 570 size_t code_gen_buffer_size; 571 void *code_gen_ptr; 572 void *data_gen_ptr; 573 574 /* Threshold to flush the translated code buffer. */ 575 void *code_gen_highwater; 576 577 /* Track which vCPU triggers events */ 578 CPUState *cpu; /* *_trans */ 579 580 /* These structures are private to tcg-target.c.inc. */ 581 #ifdef TCG_TARGET_NEED_LDST_LABELS 582 QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; 583 #endif 584 #ifdef TCG_TARGET_NEED_POOL_LABELS 585 struct TCGLabelPoolData *pool_labels; 586 #endif 587 588 TCGLabel *exitreq_label; 589 590 #ifdef CONFIG_PLUGIN 591 /* 592 * We keep one plugin_tb struct per TCGContext. Note that on every TB 593 * translation we clear but do not free its contents; this way we 594 * avoid a lot of malloc/free churn, since after a few TB's it's 595 * unlikely that we'll need to allocate either more instructions or more 596 * space for instructions (for variable-instruction-length ISAs). 597 */ 598 struct qemu_plugin_tb *plugin_tb; 599 600 /* descriptor of the instruction being translated */ 601 struct qemu_plugin_insn *plugin_insn; 602 #endif 603 604 GHashTable *const_table[TCG_TYPE_COUNT]; 605 TCGTempSet free_temps[TCG_TYPE_COUNT]; 606 TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ 607 608 QTAILQ_HEAD(, TCGOp) ops, free_ops; 609 QSIMPLEQ_HEAD(, TCGLabel) labels; 610 611 /* Tells which temporary holds a given register. 612 It does not take into account fixed registers */ 613 TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; 614 615 uint16_t gen_insn_end_off[TCG_MAX_INSNS]; 616 uint64_t gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; 617 618 /* Exit to translator on overflow. */ 619 sigjmp_buf jmp_trans; 620 }; 621 622 static inline bool temp_readonly(TCGTemp *ts) 623 { 624 return ts->kind >= TEMP_FIXED; 625 } 626 627 extern __thread TCGContext *tcg_ctx; 628 extern const void *tcg_code_gen_epilogue; 629 extern uintptr_t tcg_splitwx_diff; 630 extern TCGv_env cpu_env; 631 632 bool in_code_gen_buffer(const void *p); 633 634 #ifdef CONFIG_DEBUG_TCG 635 const void *tcg_splitwx_to_rx(void *rw); 636 void *tcg_splitwx_to_rw(const void *rx); 637 #else 638 static inline const void *tcg_splitwx_to_rx(void *rw) 639 { 640 return rw ? rw + tcg_splitwx_diff : NULL; 641 } 642 643 static inline void *tcg_splitwx_to_rw(const void *rx) 644 { 645 return rx ? (void *)rx - tcg_splitwx_diff : NULL; 646 } 647 #endif 648 649 static inline size_t temp_idx(TCGTemp *ts) 650 { 651 ptrdiff_t n = ts - tcg_ctx->temps; 652 tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps); 653 return n; 654 } 655 656 static inline TCGArg temp_arg(TCGTemp *ts) 657 { 658 return (uintptr_t)ts; 659 } 660 661 static inline TCGTemp *arg_temp(TCGArg a) 662 { 663 return (TCGTemp *)(uintptr_t)a; 664 } 665 666 /* Using the offset of a temporary, relative to TCGContext, rather than 667 its index means that we don't use 0. That leaves offset 0 free for 668 a NULL representation without having to leave index 0 unused. */ 669 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) 670 { 671 uintptr_t o = (uintptr_t)v; 672 TCGTemp *t = (void *)tcg_ctx + o; 673 tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o); 674 return t; 675 } 676 677 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) 678 { 679 return tcgv_i32_temp((TCGv_i32)v); 680 } 681 682 static inline TCGTemp *tcgv_i128_temp(TCGv_i128 v) 683 { 684 return tcgv_i32_temp((TCGv_i32)v); 685 } 686 687 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) 688 { 689 return tcgv_i32_temp((TCGv_i32)v); 690 } 691 692 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v) 693 { 694 return tcgv_i32_temp((TCGv_i32)v); 695 } 696 697 static inline TCGArg tcgv_i32_arg(TCGv_i32 v) 698 { 699 return temp_arg(tcgv_i32_temp(v)); 700 } 701 702 static inline TCGArg tcgv_i64_arg(TCGv_i64 v) 703 { 704 return temp_arg(tcgv_i64_temp(v)); 705 } 706 707 static inline TCGArg tcgv_i128_arg(TCGv_i128 v) 708 { 709 return temp_arg(tcgv_i128_temp(v)); 710 } 711 712 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) 713 { 714 return temp_arg(tcgv_ptr_temp(v)); 715 } 716 717 static inline TCGArg tcgv_vec_arg(TCGv_vec v) 718 { 719 return temp_arg(tcgv_vec_temp(v)); 720 } 721 722 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) 723 { 724 (void)temp_idx(t); /* trigger embedded assert */ 725 return (TCGv_i32)((void *)t - (void *)tcg_ctx); 726 } 727 728 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) 729 { 730 return (TCGv_i64)temp_tcgv_i32(t); 731 } 732 733 static inline TCGv_i128 temp_tcgv_i128(TCGTemp *t) 734 { 735 return (TCGv_i128)temp_tcgv_i32(t); 736 } 737 738 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) 739 { 740 return (TCGv_ptr)temp_tcgv_i32(t); 741 } 742 743 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) 744 { 745 return (TCGv_vec)temp_tcgv_i32(t); 746 } 747 748 static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) 749 { 750 return op->args[arg]; 751 } 752 753 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) 754 { 755 op->args[arg] = v; 756 } 757 758 static inline uint64_t tcg_get_insn_start_param(TCGOp *op, int arg) 759 { 760 if (TCG_TARGET_REG_BITS == 64) { 761 return tcg_get_insn_param(op, arg); 762 } else { 763 return deposit64(tcg_get_insn_param(op, arg * 2), 32, 32, 764 tcg_get_insn_param(op, arg * 2 + 1)); 765 } 766 } 767 768 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, uint64_t v) 769 { 770 if (TCG_TARGET_REG_BITS == 64) { 771 tcg_set_insn_param(op, arg, v); 772 } else { 773 tcg_set_insn_param(op, arg * 2, v); 774 tcg_set_insn_param(op, arg * 2 + 1, v >> 32); 775 } 776 } 777 778 /* The last op that was emitted. */ 779 static inline TCGOp *tcg_last_op(void) 780 { 781 return QTAILQ_LAST(&tcg_ctx->ops); 782 } 783 784 /* Test for whether to terminate the TB for using too many opcodes. */ 785 static inline bool tcg_op_buf_full(void) 786 { 787 /* This is not a hard limit, it merely stops translation when 788 * we have produced "enough" opcodes. We want to limit TB size 789 * such that a RISC host can reasonably use a 16-bit signed 790 * branch within the TB. We also need to be mindful of the 791 * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[] 792 * and TCGContext.gen_insn_end_off[]. 793 */ 794 return tcg_ctx->nb_ops >= 4000; 795 } 796 797 /* pool based memory allocation */ 798 799 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */ 800 void *tcg_malloc_internal(TCGContext *s, int size); 801 void tcg_pool_reset(TCGContext *s); 802 TranslationBlock *tcg_tb_alloc(TCGContext *s); 803 804 void tcg_region_reset_all(void); 805 806 size_t tcg_code_size(void); 807 size_t tcg_code_capacity(void); 808 809 void tcg_tb_insert(TranslationBlock *tb); 810 void tcg_tb_remove(TranslationBlock *tb); 811 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr); 812 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data); 813 size_t tcg_nb_tbs(void); 814 815 /* user-mode: Called with mmap_lock held. */ 816 static inline void *tcg_malloc(int size) 817 { 818 TCGContext *s = tcg_ctx; 819 uint8_t *ptr, *ptr_end; 820 821 /* ??? This is a weak placeholder for minimum malloc alignment. */ 822 size = QEMU_ALIGN_UP(size, 8); 823 824 ptr = s->pool_cur; 825 ptr_end = ptr + size; 826 if (unlikely(ptr_end > s->pool_end)) { 827 return tcg_malloc_internal(tcg_ctx, size); 828 } else { 829 s->pool_cur = ptr_end; 830 return ptr; 831 } 832 } 833 834 void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus); 835 void tcg_register_thread(void); 836 void tcg_prologue_init(TCGContext *s); 837 void tcg_func_start(TCGContext *s); 838 839 int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start); 840 841 void tb_target_set_jmp_target(const TranslationBlock *, int, 842 uintptr_t, uintptr_t); 843 844 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); 845 846 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, 847 intptr_t, const char *); 848 TCGTemp *tcg_temp_new_internal(TCGType, TCGTempKind); 849 TCGv_vec tcg_temp_new_vec(TCGType type); 850 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); 851 852 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, 853 const char *name) 854 { 855 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name); 856 return temp_tcgv_i32(t); 857 } 858 859 static inline TCGv_i32 tcg_temp_new_i32(void) 860 { 861 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_TB); 862 return temp_tcgv_i32(t); 863 } 864 865 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, 866 const char *name) 867 { 868 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name); 869 return temp_tcgv_i64(t); 870 } 871 872 static inline TCGv_i64 tcg_temp_new_i64(void) 873 { 874 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_TB); 875 return temp_tcgv_i64(t); 876 } 877 878 static inline TCGv_i128 tcg_temp_new_i128(void) 879 { 880 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_TB); 881 return temp_tcgv_i128(t); 882 } 883 884 static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, 885 const char *name) 886 { 887 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name); 888 return temp_tcgv_ptr(t); 889 } 890 891 static inline TCGv_ptr tcg_temp_new_ptr(void) 892 { 893 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_TB); 894 return temp_tcgv_ptr(t); 895 } 896 897 int64_t tcg_cpu_exec_time(void); 898 void tcg_dump_info(GString *buf); 899 void tcg_dump_op_count(GString *buf); 900 901 #define TCG_CT_CONST 1 /* any constant of register size */ 902 903 typedef struct TCGArgConstraint { 904 unsigned ct : 16; 905 unsigned alias_index : 4; 906 unsigned sort_index : 4; 907 unsigned pair_index : 4; 908 unsigned pair : 2; /* 0: none, 1: first, 2: second, 3: second alias */ 909 bool oalias : 1; 910 bool ialias : 1; 911 bool newreg : 1; 912 TCGRegSet regs; 913 } TCGArgConstraint; 914 915 #define TCG_MAX_OP_ARGS 16 916 917 /* Bits for TCGOpDef->flags, 8 bits available, all used. */ 918 enum { 919 /* Instruction exits the translation block. */ 920 TCG_OPF_BB_EXIT = 0x01, 921 /* Instruction defines the end of a basic block. */ 922 TCG_OPF_BB_END = 0x02, 923 /* Instruction clobbers call registers and potentially update globals. */ 924 TCG_OPF_CALL_CLOBBER = 0x04, 925 /* Instruction has side effects: it cannot be removed if its outputs 926 are not used, and might trigger exceptions. */ 927 TCG_OPF_SIDE_EFFECTS = 0x08, 928 /* Instruction operands are 64-bits (otherwise 32-bits). */ 929 TCG_OPF_64BIT = 0x10, 930 /* Instruction is optional and not implemented by the host, or insn 931 is generic and should not be implemened by the host. */ 932 TCG_OPF_NOT_PRESENT = 0x20, 933 /* Instruction operands are vectors. */ 934 TCG_OPF_VECTOR = 0x40, 935 /* Instruction is a conditional branch. */ 936 TCG_OPF_COND_BRANCH = 0x80 937 }; 938 939 typedef struct TCGOpDef { 940 const char *name; 941 uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; 942 uint8_t flags; 943 TCGArgConstraint *args_ct; 944 } TCGOpDef; 945 946 extern TCGOpDef tcg_op_defs[]; 947 extern const size_t tcg_op_defs_max; 948 949 typedef struct TCGTargetOpDef { 950 TCGOpcode op; 951 const char *args_ct_str[TCG_MAX_OP_ARGS]; 952 } TCGTargetOpDef; 953 954 bool tcg_op_supported(TCGOpcode op); 955 956 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args); 957 958 TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs); 959 void tcg_op_remove(TCGContext *s, TCGOp *op); 960 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, 961 TCGOpcode opc, unsigned nargs); 962 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, 963 TCGOpcode opc, unsigned nargs); 964 965 /** 966 * tcg_remove_ops_after: 967 * @op: target operation 968 * 969 * Discard any opcodes emitted since @op. Expected usage is to save 970 * a starting point with tcg_last_op(), speculatively emit opcodes, 971 * then decide whether or not to keep those opcodes after the fact. 972 */ 973 void tcg_remove_ops_after(TCGOp *op); 974 975 void tcg_optimize(TCGContext *s); 976 977 /* 978 * Locate or create a read-only temporary that is a constant. 979 * This kind of temporary need not be freed, but for convenience 980 * will be silently ignored by tcg_temp_free_*. 981 */ 982 TCGTemp *tcg_constant_internal(TCGType type, int64_t val); 983 984 static inline TCGv_i32 tcg_constant_i32(int32_t val) 985 { 986 return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); 987 } 988 989 static inline TCGv_i64 tcg_constant_i64(int64_t val) 990 { 991 return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); 992 } 993 994 TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); 995 TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); 996 997 #if UINTPTR_MAX == UINT32_MAX 998 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x))) 999 #else 1000 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x))) 1001 #endif 1002 1003 TCGLabel *gen_new_label(void); 1004 1005 /** 1006 * label_arg 1007 * @l: label 1008 * 1009 * Encode a label for storage in the TCG opcode stream. 1010 */ 1011 1012 static inline TCGArg label_arg(TCGLabel *l) 1013 { 1014 return (uintptr_t)l; 1015 } 1016 1017 /** 1018 * arg_label 1019 * @i: value 1020 * 1021 * The opposite of label_arg. Retrieve a label from the 1022 * encoding of the TCG opcode stream. 1023 */ 1024 1025 static inline TCGLabel *arg_label(TCGArg i) 1026 { 1027 return (TCGLabel *)(uintptr_t)i; 1028 } 1029 1030 /** 1031 * tcg_ptr_byte_diff 1032 * @a, @b: addresses to be differenced 1033 * 1034 * There are many places within the TCG backends where we need a byte 1035 * difference between two pointers. While this can be accomplished 1036 * with local casting, it's easy to get wrong -- especially if one is 1037 * concerned with the signedness of the result. 1038 * 1039 * This version relies on GCC's void pointer arithmetic to get the 1040 * correct result. 1041 */ 1042 1043 static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) 1044 { 1045 return a - b; 1046 } 1047 1048 /** 1049 * tcg_pcrel_diff 1050 * @s: the tcg context 1051 * @target: address of the target 1052 * 1053 * Produce a pc-relative difference, from the current code_ptr 1054 * to the destination address. 1055 */ 1056 1057 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) 1058 { 1059 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); 1060 } 1061 1062 /** 1063 * tcg_tbrel_diff 1064 * @s: the tcg context 1065 * @target: address of the target 1066 * 1067 * Produce a difference, from the beginning of the current TB code 1068 * to the destination address. 1069 */ 1070 static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, const void *target) 1071 { 1072 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_buf)); 1073 } 1074 1075 /** 1076 * tcg_current_code_size 1077 * @s: the tcg context 1078 * 1079 * Compute the current code size within the translation block. 1080 * This is used to fill in qemu's data structures for goto_tb. 1081 */ 1082 1083 static inline size_t tcg_current_code_size(TCGContext *s) 1084 { 1085 return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); 1086 } 1087 1088 /** 1089 * tcg_qemu_tb_exec: 1090 * @env: pointer to CPUArchState for the CPU 1091 * @tb_ptr: address of generated code for the TB to execute 1092 * 1093 * Start executing code from a given translation block. 1094 * Where translation blocks have been linked, execution 1095 * may proceed from the given TB into successive ones. 1096 * Control eventually returns only when some action is needed 1097 * from the top-level loop: either control must pass to a TB 1098 * which has not yet been directly linked, or an asynchronous 1099 * event such as an interrupt needs handling. 1100 * 1101 * Return: The return value is the value passed to the corresponding 1102 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute. 1103 * The value is either zero or a 4-byte aligned pointer to that TB combined 1104 * with additional information in its two least significant bits. The 1105 * additional information is encoded as follows: 1106 * 0, 1: the link between this TB and the next is via the specified 1107 * TB index (0 or 1). That is, we left the TB via (the equivalent 1108 * of) "goto_tb <index>". The main loop uses this to determine 1109 * how to link the TB just executed to the next. 1110 * 2: we are using instruction counting code generation, and we 1111 * did not start executing this TB because the instruction counter 1112 * would hit zero midway through it. In this case the pointer 1113 * returned is the TB we were about to execute, and the caller must 1114 * arrange to execute the remaining count of instructions. 1115 * 3: we stopped because the CPU's exit_request flag was set 1116 * (usually meaning that there is an interrupt that needs to be 1117 * handled). The pointer returned is the TB we were about to execute 1118 * when we noticed the pending exit request. 1119 * 1120 * If the bottom two bits indicate an exit-via-index then the CPU 1121 * state is correctly synchronised and ready for execution of the next 1122 * TB (and in particular the guest PC is the address to execute next). 1123 * Otherwise, we gave up on execution of this TB before it started, and 1124 * the caller must fix up the CPU state by calling the CPU's 1125 * synchronize_from_tb() method with the TB pointer we return (falling 1126 * back to calling the CPU's set_pc method with tb->pb if no 1127 * synchronize_from_tb() method exists). 1128 * 1129 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec 1130 * to this default (which just calls the prologue.code emitted by 1131 * tcg_target_qemu_prologue()). 1132 */ 1133 #define TB_EXIT_MASK 3 1134 #define TB_EXIT_IDX0 0 1135 #define TB_EXIT_IDX1 1 1136 #define TB_EXIT_IDXMAX 1 1137 #define TB_EXIT_REQUESTED 3 1138 1139 #ifdef CONFIG_TCG_INTERPRETER 1140 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); 1141 #else 1142 typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); 1143 extern tcg_prologue_fn *tcg_qemu_tb_exec; 1144 #endif 1145 1146 void tcg_register_jit(const void *buf, size_t buf_size); 1147 1148 #if TCG_TARGET_MAYBE_vec 1149 /* Return zero if the tuple (opc, type, vece) is unsupportable; 1150 return > 0 if it is directly supportable; 1151 return < 0 if we must call tcg_expand_vec_op. */ 1152 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned); 1153 #else 1154 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) 1155 { 1156 return 0; 1157 } 1158 #endif 1159 1160 /* Expand the tuple (opc, type, vece) on the given arguments. */ 1161 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...); 1162 1163 /* Replicate a constant C accoring to the log2 of the element size. */ 1164 uint64_t dup_const(unsigned vece, uint64_t c); 1165 1166 #define dup_const(VECE, C) \ 1167 (__builtin_constant_p(VECE) \ 1168 ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \ 1169 : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \ 1170 : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \ 1171 : (VECE) == MO_64 ? (uint64_t)(C) \ 1172 : (qemu_build_not_reached_always(), 0)) \ 1173 : dup_const(VECE, C)) 1174 1175 #if TARGET_LONG_BITS == 64 1176 # define dup_const_tl dup_const 1177 #else 1178 # define dup_const_tl(VECE, C) \ 1179 (__builtin_constant_p(VECE) \ 1180 ? ( (VECE) == MO_8 ? 0x01010101ul * (uint8_t)(C) \ 1181 : (VECE) == MO_16 ? 0x00010001ul * (uint16_t)(C) \ 1182 : (VECE) == MO_32 ? 0x00000001ul * (uint32_t)(C) \ 1183 : (qemu_build_not_reached_always(), 0)) \ 1184 : (target_long)dup_const(VECE, C)) 1185 #endif 1186 1187 #ifdef CONFIG_DEBUG_TCG 1188 void tcg_assert_listed_vecop(TCGOpcode); 1189 #else 1190 static inline void tcg_assert_listed_vecop(TCGOpcode op) { } 1191 #endif 1192 1193 static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n) 1194 { 1195 #ifdef CONFIG_DEBUG_TCG 1196 const TCGOpcode *o = tcg_ctx->vecop_list; 1197 tcg_ctx->vecop_list = n; 1198 return o; 1199 #else 1200 return NULL; 1201 #endif 1202 } 1203 1204 bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned); 1205 1206 #endif /* TCG_H */ 1207