1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef TCG_H 26 #define TCG_H 27 28 #include "cpu.h" 29 #include "exec/memop.h" 30 #include "exec/memopidx.h" 31 #include "qemu/bitops.h" 32 #include "qemu/plugin.h" 33 #include "qemu/queue.h" 34 #include "tcg/tcg-mo.h" 35 #include "tcg-target.h" 36 #include "tcg/tcg-cond.h" 37 #include "tcg/debug-assert.h" 38 39 /* XXX: make safe guess about sizes */ 40 #define MAX_OP_PER_INSTR 266 41 42 #define MAX_CALL_IARGS 7 43 44 #define CPU_TEMP_BUF_NLONGS 128 45 #define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) 46 47 /* Default target word size to pointer size. */ 48 #ifndef TCG_TARGET_REG_BITS 49 # if UINTPTR_MAX == UINT32_MAX 50 # define TCG_TARGET_REG_BITS 32 51 # elif UINTPTR_MAX == UINT64_MAX 52 # define TCG_TARGET_REG_BITS 64 53 # else 54 # error Unknown pointer size for tcg target 55 # endif 56 #endif 57 58 #if TCG_TARGET_REG_BITS == 32 59 typedef int32_t tcg_target_long; 60 typedef uint32_t tcg_target_ulong; 61 #define TCG_PRIlx PRIx32 62 #define TCG_PRIld PRId32 63 #elif TCG_TARGET_REG_BITS == 64 64 typedef int64_t tcg_target_long; 65 typedef uint64_t tcg_target_ulong; 66 #define TCG_PRIlx PRIx64 67 #define TCG_PRIld PRId64 68 #else 69 #error unsupported 70 #endif 71 72 /* Oversized TCG guests make things like MTTCG hard 73 * as we can't use atomics for cputlb updates. 74 */ 75 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS 76 #define TCG_OVERSIZED_GUEST 1 77 #else 78 #define TCG_OVERSIZED_GUEST 0 79 #endif 80 81 #if TCG_TARGET_NB_REGS <= 32 82 typedef uint32_t TCGRegSet; 83 #elif TCG_TARGET_NB_REGS <= 64 84 typedef uint64_t TCGRegSet; 85 #else 86 #error unsupported 87 #endif 88 89 #if TCG_TARGET_REG_BITS == 32 90 /* Turn some undef macros into false macros. */ 91 #define TCG_TARGET_HAS_extrl_i64_i32 0 92 #define TCG_TARGET_HAS_extrh_i64_i32 0 93 #define TCG_TARGET_HAS_div_i64 0 94 #define TCG_TARGET_HAS_rem_i64 0 95 #define TCG_TARGET_HAS_div2_i64 0 96 #define TCG_TARGET_HAS_rot_i64 0 97 #define TCG_TARGET_HAS_ext8s_i64 0 98 #define TCG_TARGET_HAS_ext16s_i64 0 99 #define TCG_TARGET_HAS_ext32s_i64 0 100 #define TCG_TARGET_HAS_ext8u_i64 0 101 #define TCG_TARGET_HAS_ext16u_i64 0 102 #define TCG_TARGET_HAS_ext32u_i64 0 103 #define TCG_TARGET_HAS_bswap16_i64 0 104 #define TCG_TARGET_HAS_bswap32_i64 0 105 #define TCG_TARGET_HAS_bswap64_i64 0 106 #define TCG_TARGET_HAS_neg_i64 0 107 #define TCG_TARGET_HAS_not_i64 0 108 #define TCG_TARGET_HAS_andc_i64 0 109 #define TCG_TARGET_HAS_orc_i64 0 110 #define TCG_TARGET_HAS_eqv_i64 0 111 #define TCG_TARGET_HAS_nand_i64 0 112 #define TCG_TARGET_HAS_nor_i64 0 113 #define TCG_TARGET_HAS_clz_i64 0 114 #define TCG_TARGET_HAS_ctz_i64 0 115 #define TCG_TARGET_HAS_ctpop_i64 0 116 #define TCG_TARGET_HAS_deposit_i64 0 117 #define TCG_TARGET_HAS_extract_i64 0 118 #define TCG_TARGET_HAS_sextract_i64 0 119 #define TCG_TARGET_HAS_extract2_i64 0 120 #define TCG_TARGET_HAS_movcond_i64 0 121 #define TCG_TARGET_HAS_add2_i64 0 122 #define TCG_TARGET_HAS_sub2_i64 0 123 #define TCG_TARGET_HAS_mulu2_i64 0 124 #define TCG_TARGET_HAS_muls2_i64 0 125 #define TCG_TARGET_HAS_muluh_i64 0 126 #define TCG_TARGET_HAS_mulsh_i64 0 127 /* Turn some undef macros into true macros. */ 128 #define TCG_TARGET_HAS_add2_i32 1 129 #define TCG_TARGET_HAS_sub2_i32 1 130 #endif 131 132 #ifndef TCG_TARGET_deposit_i32_valid 133 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 134 #endif 135 #ifndef TCG_TARGET_deposit_i64_valid 136 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 137 #endif 138 #ifndef TCG_TARGET_extract_i32_valid 139 #define TCG_TARGET_extract_i32_valid(ofs, len) 1 140 #endif 141 #ifndef TCG_TARGET_extract_i64_valid 142 #define TCG_TARGET_extract_i64_valid(ofs, len) 1 143 #endif 144 145 /* Only one of DIV or DIV2 should be defined. */ 146 #if defined(TCG_TARGET_HAS_div_i32) 147 #define TCG_TARGET_HAS_div2_i32 0 148 #elif defined(TCG_TARGET_HAS_div2_i32) 149 #define TCG_TARGET_HAS_div_i32 0 150 #define TCG_TARGET_HAS_rem_i32 0 151 #endif 152 #if defined(TCG_TARGET_HAS_div_i64) 153 #define TCG_TARGET_HAS_div2_i64 0 154 #elif defined(TCG_TARGET_HAS_div2_i64) 155 #define TCG_TARGET_HAS_div_i64 0 156 #define TCG_TARGET_HAS_rem_i64 0 157 #endif 158 159 #if !defined(TCG_TARGET_HAS_v64) \ 160 && !defined(TCG_TARGET_HAS_v128) \ 161 && !defined(TCG_TARGET_HAS_v256) 162 #define TCG_TARGET_MAYBE_vec 0 163 #define TCG_TARGET_HAS_abs_vec 0 164 #define TCG_TARGET_HAS_neg_vec 0 165 #define TCG_TARGET_HAS_not_vec 0 166 #define TCG_TARGET_HAS_andc_vec 0 167 #define TCG_TARGET_HAS_orc_vec 0 168 #define TCG_TARGET_HAS_nand_vec 0 169 #define TCG_TARGET_HAS_nor_vec 0 170 #define TCG_TARGET_HAS_eqv_vec 0 171 #define TCG_TARGET_HAS_roti_vec 0 172 #define TCG_TARGET_HAS_rots_vec 0 173 #define TCG_TARGET_HAS_rotv_vec 0 174 #define TCG_TARGET_HAS_shi_vec 0 175 #define TCG_TARGET_HAS_shs_vec 0 176 #define TCG_TARGET_HAS_shv_vec 0 177 #define TCG_TARGET_HAS_mul_vec 0 178 #define TCG_TARGET_HAS_sat_vec 0 179 #define TCG_TARGET_HAS_minmax_vec 0 180 #define TCG_TARGET_HAS_bitsel_vec 0 181 #define TCG_TARGET_HAS_cmpsel_vec 0 182 #else 183 #define TCG_TARGET_MAYBE_vec 1 184 #endif 185 #ifndef TCG_TARGET_HAS_v64 186 #define TCG_TARGET_HAS_v64 0 187 #endif 188 #ifndef TCG_TARGET_HAS_v128 189 #define TCG_TARGET_HAS_v128 0 190 #endif 191 #ifndef TCG_TARGET_HAS_v256 192 #define TCG_TARGET_HAS_v256 0 193 #endif 194 195 #ifndef TARGET_INSN_START_EXTRA_WORDS 196 # define TARGET_INSN_START_WORDS 1 197 #else 198 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) 199 #endif 200 201 typedef enum TCGOpcode { 202 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, 203 #include "tcg/tcg-opc.h" 204 #undef DEF 205 NB_OPS, 206 } TCGOpcode; 207 208 #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) 209 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r))) 210 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) 211 212 #ifndef TCG_TARGET_INSN_UNIT_SIZE 213 # error "Missing TCG_TARGET_INSN_UNIT_SIZE" 214 #elif TCG_TARGET_INSN_UNIT_SIZE == 1 215 typedef uint8_t tcg_insn_unit; 216 #elif TCG_TARGET_INSN_UNIT_SIZE == 2 217 typedef uint16_t tcg_insn_unit; 218 #elif TCG_TARGET_INSN_UNIT_SIZE == 4 219 typedef uint32_t tcg_insn_unit; 220 #elif TCG_TARGET_INSN_UNIT_SIZE == 8 221 typedef uint64_t tcg_insn_unit; 222 #else 223 /* The port better have done this. */ 224 #endif 225 226 typedef struct TCGRelocation TCGRelocation; 227 struct TCGRelocation { 228 QSIMPLEQ_ENTRY(TCGRelocation) next; 229 tcg_insn_unit *ptr; 230 intptr_t addend; 231 int type; 232 }; 233 234 typedef struct TCGOp TCGOp; 235 typedef struct TCGLabelUse TCGLabelUse; 236 struct TCGLabelUse { 237 QSIMPLEQ_ENTRY(TCGLabelUse) next; 238 TCGOp *op; 239 }; 240 241 typedef struct TCGLabel TCGLabel; 242 struct TCGLabel { 243 bool present; 244 bool has_value; 245 uint16_t id; 246 union { 247 uintptr_t value; 248 const tcg_insn_unit *value_ptr; 249 } u; 250 QSIMPLEQ_HEAD(, TCGLabelUse) branches; 251 QSIMPLEQ_HEAD(, TCGRelocation) relocs; 252 QSIMPLEQ_ENTRY(TCGLabel) next; 253 }; 254 255 typedef struct TCGPool { 256 struct TCGPool *next; 257 int size; 258 uint8_t data[] __attribute__ ((aligned)); 259 } TCGPool; 260 261 #define TCG_POOL_CHUNK_SIZE 32768 262 263 #define TCG_MAX_TEMPS 512 264 #define TCG_MAX_INSNS 512 265 266 /* when the size of the arguments of a called function is smaller than 267 this value, they are statically allocated in the TB stack frame */ 268 #define TCG_STATIC_CALL_ARGS_SIZE 128 269 270 typedef enum TCGType { 271 TCG_TYPE_I32, 272 TCG_TYPE_I64, 273 TCG_TYPE_I128, 274 275 TCG_TYPE_V64, 276 TCG_TYPE_V128, 277 TCG_TYPE_V256, 278 279 /* Number of different types (integer not enum) */ 280 #define TCG_TYPE_COUNT (TCG_TYPE_V256 + 1) 281 282 /* An alias for the size of the host register. */ 283 #if TCG_TARGET_REG_BITS == 32 284 TCG_TYPE_REG = TCG_TYPE_I32, 285 #else 286 TCG_TYPE_REG = TCG_TYPE_I64, 287 #endif 288 289 /* An alias for the size of the native pointer. */ 290 #if UINTPTR_MAX == UINT32_MAX 291 TCG_TYPE_PTR = TCG_TYPE_I32, 292 #else 293 TCG_TYPE_PTR = TCG_TYPE_I64, 294 #endif 295 } TCGType; 296 297 /** 298 * tcg_type_size 299 * @t: type 300 * 301 * Return the size of the type in bytes. 302 */ 303 static inline int tcg_type_size(TCGType t) 304 { 305 unsigned i = t; 306 if (i >= TCG_TYPE_V64) { 307 tcg_debug_assert(i < TCG_TYPE_COUNT); 308 i -= TCG_TYPE_V64 - 1; 309 } 310 return 4 << i; 311 } 312 313 /** 314 * get_alignment_bits 315 * @memop: MemOp value 316 * 317 * Extract the alignment size from the memop. 318 */ 319 static inline unsigned get_alignment_bits(MemOp memop) 320 { 321 unsigned a = memop & MO_AMASK; 322 323 if (a == MO_UNALN) { 324 /* No alignment required. */ 325 a = 0; 326 } else if (a == MO_ALIGN) { 327 /* A natural alignment requirement. */ 328 a = memop & MO_SIZE; 329 } else { 330 /* A specific alignment requirement. */ 331 a = a >> MO_ASHIFT; 332 } 333 #if defined(CONFIG_SOFTMMU) 334 /* The requested alignment cannot overlap the TLB flags. */ 335 tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0); 336 #endif 337 return a; 338 } 339 340 typedef tcg_target_ulong TCGArg; 341 342 /* Define type and accessor macros for TCG variables. 343 344 TCG variables are the inputs and outputs of TCG ops, as described 345 in tcg/README. Target CPU front-end code uses these types to deal 346 with TCG variables as it emits TCG code via the tcg_gen_* functions. 347 They come in several flavours: 348 * TCGv_i32 : 32 bit integer type 349 * TCGv_i64 : 64 bit integer type 350 * TCGv_i128 : 128 bit integer type 351 * TCGv_ptr : a host pointer type 352 * TCGv_vec : a host vector type; the exact size is not exposed 353 to the CPU front-end code. 354 * TCGv : an integer type the same size as target_ulong 355 (an alias for either TCGv_i32 or TCGv_i64) 356 The compiler's type checking will complain if you mix them 357 up and pass the wrong sized TCGv to a function. 358 359 Users of tcg_gen_* don't need to know about any of the internal 360 details of these, and should treat them as opaque types. 361 You won't be able to look inside them in a debugger either. 362 363 Internal implementation details follow: 364 365 Note that there is no definition of the structs TCGv_i32_d etc anywhere. 366 This is deliberate, because the values we store in variables of type 367 TCGv_i32 are not really pointers-to-structures. They're just small 368 integers, but keeping them in pointer types like this means that the 369 compiler will complain if you accidentally pass a TCGv_i32 to a 370 function which takes a TCGv_i64, and so on. Only the internals of 371 TCG need to care about the actual contents of the types. */ 372 373 typedef struct TCGv_i32_d *TCGv_i32; 374 typedef struct TCGv_i64_d *TCGv_i64; 375 typedef struct TCGv_i128_d *TCGv_i128; 376 typedef struct TCGv_ptr_d *TCGv_ptr; 377 typedef struct TCGv_vec_d *TCGv_vec; 378 typedef TCGv_ptr TCGv_env; 379 #if TARGET_LONG_BITS == 32 380 #define TCGv TCGv_i32 381 #elif TARGET_LONG_BITS == 64 382 #define TCGv TCGv_i64 383 #else 384 #error Unhandled TARGET_LONG_BITS value 385 #endif 386 387 /* call flags */ 388 /* Helper does not read globals (either directly or through an exception). It 389 implies TCG_CALL_NO_WRITE_GLOBALS. */ 390 #define TCG_CALL_NO_READ_GLOBALS 0x0001 391 /* Helper does not write globals */ 392 #define TCG_CALL_NO_WRITE_GLOBALS 0x0002 393 /* Helper can be safely suppressed if the return value is not used. */ 394 #define TCG_CALL_NO_SIDE_EFFECTS 0x0004 395 /* Helper is G_NORETURN. */ 396 #define TCG_CALL_NO_RETURN 0x0008 397 /* Helper is part of Plugins. */ 398 #define TCG_CALL_PLUGIN 0x0010 399 400 /* convenience version of most used call flags */ 401 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS 402 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS 403 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS 404 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) 405 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) 406 407 /* 408 * Flags for the bswap opcodes. 409 * If IZ, the input is zero-extended, otherwise unknown. 410 * If OZ or OS, the output is zero- or sign-extended respectively, 411 * otherwise the high bits are undefined. 412 */ 413 enum { 414 TCG_BSWAP_IZ = 1, 415 TCG_BSWAP_OZ = 2, 416 TCG_BSWAP_OS = 4, 417 }; 418 419 typedef enum TCGTempVal { 420 TEMP_VAL_DEAD, 421 TEMP_VAL_REG, 422 TEMP_VAL_MEM, 423 TEMP_VAL_CONST, 424 } TCGTempVal; 425 426 typedef enum TCGTempKind { 427 /* 428 * Temp is dead at the end of the extended basic block (EBB), 429 * the single-entry multiple-exit region that falls through 430 * conditional branches. 431 */ 432 TEMP_EBB, 433 /* Temp is live across the entire translation block, but dead at end. */ 434 TEMP_TB, 435 /* Temp is live across the entire translation block, and between them. */ 436 TEMP_GLOBAL, 437 /* Temp is in a fixed register. */ 438 TEMP_FIXED, 439 /* Temp is a fixed constant. */ 440 TEMP_CONST, 441 } TCGTempKind; 442 443 typedef struct TCGTemp { 444 TCGReg reg:8; 445 TCGTempVal val_type:8; 446 TCGType base_type:8; 447 TCGType type:8; 448 TCGTempKind kind:3; 449 unsigned int indirect_reg:1; 450 unsigned int indirect_base:1; 451 unsigned int mem_coherent:1; 452 unsigned int mem_allocated:1; 453 unsigned int temp_allocated:1; 454 unsigned int temp_subindex:1; 455 456 int64_t val; 457 struct TCGTemp *mem_base; 458 intptr_t mem_offset; 459 const char *name; 460 461 /* Pass-specific information that can be stored for a temporary. 462 One word worth of integer data, and one pointer to data 463 allocated separately. */ 464 uintptr_t state; 465 void *state_ptr; 466 } TCGTemp; 467 468 typedef struct TCGContext TCGContext; 469 470 typedef struct TCGTempSet { 471 unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; 472 } TCGTempSet; 473 474 /* 475 * With 1 128-bit output, a 32-bit host requires 4 output parameters, 476 * which leaves a maximum of 28 other slots. Which is enough for 7 477 * 128-bit operands. 478 */ 479 #define DEAD_ARG (1 << 4) 480 #define SYNC_ARG (1 << 0) 481 typedef uint32_t TCGLifeData; 482 483 struct TCGOp { 484 TCGOpcode opc : 8; 485 unsigned nargs : 8; 486 487 /* Parameters for this opcode. See below. */ 488 unsigned param1 : 8; 489 unsigned param2 : 8; 490 491 /* Lifetime data of the operands. */ 492 TCGLifeData life; 493 494 /* Next and previous opcodes. */ 495 QTAILQ_ENTRY(TCGOp) link; 496 497 /* Register preferences for the output(s). */ 498 TCGRegSet output_pref[2]; 499 500 /* Arguments for the opcode. */ 501 TCGArg args[]; 502 }; 503 504 #define TCGOP_CALLI(X) (X)->param1 505 #define TCGOP_CALLO(X) (X)->param2 506 507 #define TCGOP_VECL(X) (X)->param1 508 #define TCGOP_VECE(X) (X)->param2 509 510 /* Make sure operands fit in the bitfields above. */ 511 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); 512 513 static inline TCGRegSet output_pref(const TCGOp *op, unsigned i) 514 { 515 return i < ARRAY_SIZE(op->output_pref) ? op->output_pref[i] : 0; 516 } 517 518 typedef struct TCGProfile { 519 int64_t cpu_exec_time; 520 int64_t tb_count1; 521 int64_t tb_count; 522 int64_t op_count; /* total insn count */ 523 int op_count_max; /* max insn per TB */ 524 int temp_count_max; 525 int64_t temp_count; 526 int64_t del_op_count; 527 int64_t code_in_len; 528 int64_t code_out_len; 529 int64_t search_out_len; 530 int64_t interm_time; 531 int64_t code_time; 532 int64_t la_time; 533 int64_t opt_time; 534 int64_t restore_count; 535 int64_t restore_time; 536 int64_t table_op_count[NB_OPS]; 537 } TCGProfile; 538 539 struct TCGContext { 540 uint8_t *pool_cur, *pool_end; 541 TCGPool *pool_first, *pool_current, *pool_first_large; 542 int nb_labels; 543 int nb_globals; 544 int nb_temps; 545 int nb_indirects; 546 int nb_ops; 547 TCGType addr_type; /* TCG_TYPE_I32 or TCG_TYPE_I64 */ 548 549 #ifdef CONFIG_SOFTMMU 550 int page_mask; 551 uint8_t page_bits; 552 uint8_t tlb_dyn_max_bits; 553 #endif 554 555 TCGRegSet reserved_regs; 556 intptr_t current_frame_offset; 557 intptr_t frame_start; 558 intptr_t frame_end; 559 TCGTemp *frame_temp; 560 561 TranslationBlock *gen_tb; /* tb for which code is being generated */ 562 tcg_insn_unit *code_buf; /* pointer for start of tb */ 563 tcg_insn_unit *code_ptr; /* pointer for running end of tb */ 564 565 #ifdef CONFIG_PROFILER 566 TCGProfile prof; 567 #endif 568 569 #ifdef CONFIG_DEBUG_TCG 570 int goto_tb_issue_mask; 571 const TCGOpcode *vecop_list; 572 #endif 573 574 /* Code generation. Note that we specifically do not use tcg_insn_unit 575 here, because there's too much arithmetic throughout that relies 576 on addition and subtraction working on bytes. Rely on the GCC 577 extension that allows arithmetic on void*. */ 578 void *code_gen_buffer; 579 size_t code_gen_buffer_size; 580 void *code_gen_ptr; 581 void *data_gen_ptr; 582 583 /* Threshold to flush the translated code buffer. */ 584 void *code_gen_highwater; 585 586 /* Track which vCPU triggers events */ 587 CPUState *cpu; /* *_trans */ 588 589 /* These structures are private to tcg-target.c.inc. */ 590 #ifdef TCG_TARGET_NEED_LDST_LABELS 591 QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; 592 #endif 593 #ifdef TCG_TARGET_NEED_POOL_LABELS 594 struct TCGLabelPoolData *pool_labels; 595 #endif 596 597 TCGLabel *exitreq_label; 598 599 #ifdef CONFIG_PLUGIN 600 /* 601 * We keep one plugin_tb struct per TCGContext. Note that on every TB 602 * translation we clear but do not free its contents; this way we 603 * avoid a lot of malloc/free churn, since after a few TB's it's 604 * unlikely that we'll need to allocate either more instructions or more 605 * space for instructions (for variable-instruction-length ISAs). 606 */ 607 struct qemu_plugin_tb *plugin_tb; 608 609 /* descriptor of the instruction being translated */ 610 struct qemu_plugin_insn *plugin_insn; 611 #endif 612 613 GHashTable *const_table[TCG_TYPE_COUNT]; 614 TCGTempSet free_temps[TCG_TYPE_COUNT]; 615 TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ 616 617 QTAILQ_HEAD(, TCGOp) ops, free_ops; 618 QSIMPLEQ_HEAD(, TCGLabel) labels; 619 620 /* Tells which temporary holds a given register. 621 It does not take into account fixed registers */ 622 TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; 623 624 uint16_t gen_insn_end_off[TCG_MAX_INSNS]; 625 uint64_t gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; 626 627 /* Exit to translator on overflow. */ 628 sigjmp_buf jmp_trans; 629 }; 630 631 static inline bool temp_readonly(TCGTemp *ts) 632 { 633 return ts->kind >= TEMP_FIXED; 634 } 635 636 extern __thread TCGContext *tcg_ctx; 637 extern const void *tcg_code_gen_epilogue; 638 extern uintptr_t tcg_splitwx_diff; 639 extern TCGv_env cpu_env; 640 641 bool in_code_gen_buffer(const void *p); 642 643 #ifdef CONFIG_DEBUG_TCG 644 const void *tcg_splitwx_to_rx(void *rw); 645 void *tcg_splitwx_to_rw(const void *rx); 646 #else 647 static inline const void *tcg_splitwx_to_rx(void *rw) 648 { 649 return rw ? rw + tcg_splitwx_diff : NULL; 650 } 651 652 static inline void *tcg_splitwx_to_rw(const void *rx) 653 { 654 return rx ? (void *)rx - tcg_splitwx_diff : NULL; 655 } 656 #endif 657 658 static inline size_t temp_idx(TCGTemp *ts) 659 { 660 ptrdiff_t n = ts - tcg_ctx->temps; 661 tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps); 662 return n; 663 } 664 665 static inline TCGArg temp_arg(TCGTemp *ts) 666 { 667 return (uintptr_t)ts; 668 } 669 670 static inline TCGTemp *arg_temp(TCGArg a) 671 { 672 return (TCGTemp *)(uintptr_t)a; 673 } 674 675 /* Using the offset of a temporary, relative to TCGContext, rather than 676 its index means that we don't use 0. That leaves offset 0 free for 677 a NULL representation without having to leave index 0 unused. */ 678 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) 679 { 680 uintptr_t o = (uintptr_t)v; 681 TCGTemp *t = (void *)tcg_ctx + o; 682 tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o); 683 return t; 684 } 685 686 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) 687 { 688 return tcgv_i32_temp((TCGv_i32)v); 689 } 690 691 static inline TCGTemp *tcgv_i128_temp(TCGv_i128 v) 692 { 693 return tcgv_i32_temp((TCGv_i32)v); 694 } 695 696 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) 697 { 698 return tcgv_i32_temp((TCGv_i32)v); 699 } 700 701 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v) 702 { 703 return tcgv_i32_temp((TCGv_i32)v); 704 } 705 706 static inline TCGArg tcgv_i32_arg(TCGv_i32 v) 707 { 708 return temp_arg(tcgv_i32_temp(v)); 709 } 710 711 static inline TCGArg tcgv_i64_arg(TCGv_i64 v) 712 { 713 return temp_arg(tcgv_i64_temp(v)); 714 } 715 716 static inline TCGArg tcgv_i128_arg(TCGv_i128 v) 717 { 718 return temp_arg(tcgv_i128_temp(v)); 719 } 720 721 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) 722 { 723 return temp_arg(tcgv_ptr_temp(v)); 724 } 725 726 static inline TCGArg tcgv_vec_arg(TCGv_vec v) 727 { 728 return temp_arg(tcgv_vec_temp(v)); 729 } 730 731 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) 732 { 733 (void)temp_idx(t); /* trigger embedded assert */ 734 return (TCGv_i32)((void *)t - (void *)tcg_ctx); 735 } 736 737 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) 738 { 739 return (TCGv_i64)temp_tcgv_i32(t); 740 } 741 742 static inline TCGv_i128 temp_tcgv_i128(TCGTemp *t) 743 { 744 return (TCGv_i128)temp_tcgv_i32(t); 745 } 746 747 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) 748 { 749 return (TCGv_ptr)temp_tcgv_i32(t); 750 } 751 752 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) 753 { 754 return (TCGv_vec)temp_tcgv_i32(t); 755 } 756 757 static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) 758 { 759 return op->args[arg]; 760 } 761 762 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) 763 { 764 op->args[arg] = v; 765 } 766 767 static inline uint64_t tcg_get_insn_start_param(TCGOp *op, int arg) 768 { 769 if (TCG_TARGET_REG_BITS == 64) { 770 return tcg_get_insn_param(op, arg); 771 } else { 772 return deposit64(tcg_get_insn_param(op, arg * 2), 32, 32, 773 tcg_get_insn_param(op, arg * 2 + 1)); 774 } 775 } 776 777 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, uint64_t v) 778 { 779 if (TCG_TARGET_REG_BITS == 64) { 780 tcg_set_insn_param(op, arg, v); 781 } else { 782 tcg_set_insn_param(op, arg * 2, v); 783 tcg_set_insn_param(op, arg * 2 + 1, v >> 32); 784 } 785 } 786 787 /* The last op that was emitted. */ 788 static inline TCGOp *tcg_last_op(void) 789 { 790 return QTAILQ_LAST(&tcg_ctx->ops); 791 } 792 793 /* Test for whether to terminate the TB for using too many opcodes. */ 794 static inline bool tcg_op_buf_full(void) 795 { 796 /* This is not a hard limit, it merely stops translation when 797 * we have produced "enough" opcodes. We want to limit TB size 798 * such that a RISC host can reasonably use a 16-bit signed 799 * branch within the TB. We also need to be mindful of the 800 * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[] 801 * and TCGContext.gen_insn_end_off[]. 802 */ 803 return tcg_ctx->nb_ops >= 4000; 804 } 805 806 /* pool based memory allocation */ 807 808 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */ 809 void *tcg_malloc_internal(TCGContext *s, int size); 810 void tcg_pool_reset(TCGContext *s); 811 TranslationBlock *tcg_tb_alloc(TCGContext *s); 812 813 void tcg_region_reset_all(void); 814 815 size_t tcg_code_size(void); 816 size_t tcg_code_capacity(void); 817 818 void tcg_tb_insert(TranslationBlock *tb); 819 void tcg_tb_remove(TranslationBlock *tb); 820 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr); 821 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data); 822 size_t tcg_nb_tbs(void); 823 824 /* user-mode: Called with mmap_lock held. */ 825 static inline void *tcg_malloc(int size) 826 { 827 TCGContext *s = tcg_ctx; 828 uint8_t *ptr, *ptr_end; 829 830 /* ??? This is a weak placeholder for minimum malloc alignment. */ 831 size = QEMU_ALIGN_UP(size, 8); 832 833 ptr = s->pool_cur; 834 ptr_end = ptr + size; 835 if (unlikely(ptr_end > s->pool_end)) { 836 return tcg_malloc_internal(tcg_ctx, size); 837 } else { 838 s->pool_cur = ptr_end; 839 return ptr; 840 } 841 } 842 843 void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus); 844 void tcg_register_thread(void); 845 void tcg_prologue_init(TCGContext *s); 846 void tcg_func_start(TCGContext *s); 847 848 int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start); 849 850 void tb_target_set_jmp_target(const TranslationBlock *, int, 851 uintptr_t, uintptr_t); 852 853 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); 854 855 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, 856 intptr_t, const char *); 857 TCGTemp *tcg_temp_new_internal(TCGType, TCGTempKind); 858 TCGv_vec tcg_temp_new_vec(TCGType type); 859 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); 860 861 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, 862 const char *name) 863 { 864 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name); 865 return temp_tcgv_i32(t); 866 } 867 868 static inline TCGv_i32 tcg_temp_new_i32(void) 869 { 870 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_TB); 871 return temp_tcgv_i32(t); 872 } 873 874 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, 875 const char *name) 876 { 877 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name); 878 return temp_tcgv_i64(t); 879 } 880 881 static inline TCGv_i64 tcg_temp_new_i64(void) 882 { 883 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_TB); 884 return temp_tcgv_i64(t); 885 } 886 887 static inline TCGv_i128 tcg_temp_new_i128(void) 888 { 889 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_TB); 890 return temp_tcgv_i128(t); 891 } 892 893 static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, 894 const char *name) 895 { 896 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name); 897 return temp_tcgv_ptr(t); 898 } 899 900 static inline TCGv_ptr tcg_temp_new_ptr(void) 901 { 902 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_TB); 903 return temp_tcgv_ptr(t); 904 } 905 906 int64_t tcg_cpu_exec_time(void); 907 void tcg_dump_info(GString *buf); 908 void tcg_dump_op_count(GString *buf); 909 910 #define TCG_CT_CONST 1 /* any constant of register size */ 911 912 typedef struct TCGArgConstraint { 913 unsigned ct : 16; 914 unsigned alias_index : 4; 915 unsigned sort_index : 4; 916 unsigned pair_index : 4; 917 unsigned pair : 2; /* 0: none, 1: first, 2: second, 3: second alias */ 918 bool oalias : 1; 919 bool ialias : 1; 920 bool newreg : 1; 921 TCGRegSet regs; 922 } TCGArgConstraint; 923 924 #define TCG_MAX_OP_ARGS 16 925 926 /* Bits for TCGOpDef->flags, 8 bits available, all used. */ 927 enum { 928 /* Instruction exits the translation block. */ 929 TCG_OPF_BB_EXIT = 0x01, 930 /* Instruction defines the end of a basic block. */ 931 TCG_OPF_BB_END = 0x02, 932 /* Instruction clobbers call registers and potentially update globals. */ 933 TCG_OPF_CALL_CLOBBER = 0x04, 934 /* Instruction has side effects: it cannot be removed if its outputs 935 are not used, and might trigger exceptions. */ 936 TCG_OPF_SIDE_EFFECTS = 0x08, 937 /* Instruction operands are 64-bits (otherwise 32-bits). */ 938 TCG_OPF_64BIT = 0x10, 939 /* Instruction is optional and not implemented by the host, or insn 940 is generic and should not be implemened by the host. */ 941 TCG_OPF_NOT_PRESENT = 0x20, 942 /* Instruction operands are vectors. */ 943 TCG_OPF_VECTOR = 0x40, 944 /* Instruction is a conditional branch. */ 945 TCG_OPF_COND_BRANCH = 0x80 946 }; 947 948 typedef struct TCGOpDef { 949 const char *name; 950 uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; 951 uint8_t flags; 952 TCGArgConstraint *args_ct; 953 } TCGOpDef; 954 955 extern TCGOpDef tcg_op_defs[]; 956 extern const size_t tcg_op_defs_max; 957 958 typedef struct TCGTargetOpDef { 959 TCGOpcode op; 960 const char *args_ct_str[TCG_MAX_OP_ARGS]; 961 } TCGTargetOpDef; 962 963 bool tcg_op_supported(TCGOpcode op); 964 965 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args); 966 967 TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs); 968 void tcg_op_remove(TCGContext *s, TCGOp *op); 969 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, 970 TCGOpcode opc, unsigned nargs); 971 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, 972 TCGOpcode opc, unsigned nargs); 973 974 /** 975 * tcg_remove_ops_after: 976 * @op: target operation 977 * 978 * Discard any opcodes emitted since @op. Expected usage is to save 979 * a starting point with tcg_last_op(), speculatively emit opcodes, 980 * then decide whether or not to keep those opcodes after the fact. 981 */ 982 void tcg_remove_ops_after(TCGOp *op); 983 984 void tcg_optimize(TCGContext *s); 985 986 /* 987 * Locate or create a read-only temporary that is a constant. 988 * This kind of temporary need not be freed, but for convenience 989 * will be silently ignored by tcg_temp_free_*. 990 */ 991 TCGTemp *tcg_constant_internal(TCGType type, int64_t val); 992 993 static inline TCGv_i32 tcg_constant_i32(int32_t val) 994 { 995 return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); 996 } 997 998 static inline TCGv_i64 tcg_constant_i64(int64_t val) 999 { 1000 return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); 1001 } 1002 1003 TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); 1004 TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); 1005 1006 #if UINTPTR_MAX == UINT32_MAX 1007 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x))) 1008 #else 1009 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x))) 1010 #endif 1011 1012 TCGLabel *gen_new_label(void); 1013 1014 /** 1015 * label_arg 1016 * @l: label 1017 * 1018 * Encode a label for storage in the TCG opcode stream. 1019 */ 1020 1021 static inline TCGArg label_arg(TCGLabel *l) 1022 { 1023 return (uintptr_t)l; 1024 } 1025 1026 /** 1027 * arg_label 1028 * @i: value 1029 * 1030 * The opposite of label_arg. Retrieve a label from the 1031 * encoding of the TCG opcode stream. 1032 */ 1033 1034 static inline TCGLabel *arg_label(TCGArg i) 1035 { 1036 return (TCGLabel *)(uintptr_t)i; 1037 } 1038 1039 /** 1040 * tcg_ptr_byte_diff 1041 * @a, @b: addresses to be differenced 1042 * 1043 * There are many places within the TCG backends where we need a byte 1044 * difference between two pointers. While this can be accomplished 1045 * with local casting, it's easy to get wrong -- especially if one is 1046 * concerned with the signedness of the result. 1047 * 1048 * This version relies on GCC's void pointer arithmetic to get the 1049 * correct result. 1050 */ 1051 1052 static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) 1053 { 1054 return a - b; 1055 } 1056 1057 /** 1058 * tcg_pcrel_diff 1059 * @s: the tcg context 1060 * @target: address of the target 1061 * 1062 * Produce a pc-relative difference, from the current code_ptr 1063 * to the destination address. 1064 */ 1065 1066 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) 1067 { 1068 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); 1069 } 1070 1071 /** 1072 * tcg_tbrel_diff 1073 * @s: the tcg context 1074 * @target: address of the target 1075 * 1076 * Produce a difference, from the beginning of the current TB code 1077 * to the destination address. 1078 */ 1079 static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, const void *target) 1080 { 1081 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_buf)); 1082 } 1083 1084 /** 1085 * tcg_current_code_size 1086 * @s: the tcg context 1087 * 1088 * Compute the current code size within the translation block. 1089 * This is used to fill in qemu's data structures for goto_tb. 1090 */ 1091 1092 static inline size_t tcg_current_code_size(TCGContext *s) 1093 { 1094 return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); 1095 } 1096 1097 /** 1098 * tcg_qemu_tb_exec: 1099 * @env: pointer to CPUArchState for the CPU 1100 * @tb_ptr: address of generated code for the TB to execute 1101 * 1102 * Start executing code from a given translation block. 1103 * Where translation blocks have been linked, execution 1104 * may proceed from the given TB into successive ones. 1105 * Control eventually returns only when some action is needed 1106 * from the top-level loop: either control must pass to a TB 1107 * which has not yet been directly linked, or an asynchronous 1108 * event such as an interrupt needs handling. 1109 * 1110 * Return: The return value is the value passed to the corresponding 1111 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute. 1112 * The value is either zero or a 4-byte aligned pointer to that TB combined 1113 * with additional information in its two least significant bits. The 1114 * additional information is encoded as follows: 1115 * 0, 1: the link between this TB and the next is via the specified 1116 * TB index (0 or 1). That is, we left the TB via (the equivalent 1117 * of) "goto_tb <index>". The main loop uses this to determine 1118 * how to link the TB just executed to the next. 1119 * 2: we are using instruction counting code generation, and we 1120 * did not start executing this TB because the instruction counter 1121 * would hit zero midway through it. In this case the pointer 1122 * returned is the TB we were about to execute, and the caller must 1123 * arrange to execute the remaining count of instructions. 1124 * 3: we stopped because the CPU's exit_request flag was set 1125 * (usually meaning that there is an interrupt that needs to be 1126 * handled). The pointer returned is the TB we were about to execute 1127 * when we noticed the pending exit request. 1128 * 1129 * If the bottom two bits indicate an exit-via-index then the CPU 1130 * state is correctly synchronised and ready for execution of the next 1131 * TB (and in particular the guest PC is the address to execute next). 1132 * Otherwise, we gave up on execution of this TB before it started, and 1133 * the caller must fix up the CPU state by calling the CPU's 1134 * synchronize_from_tb() method with the TB pointer we return (falling 1135 * back to calling the CPU's set_pc method with tb->pb if no 1136 * synchronize_from_tb() method exists). 1137 * 1138 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec 1139 * to this default (which just calls the prologue.code emitted by 1140 * tcg_target_qemu_prologue()). 1141 */ 1142 #define TB_EXIT_MASK 3 1143 #define TB_EXIT_IDX0 0 1144 #define TB_EXIT_IDX1 1 1145 #define TB_EXIT_IDXMAX 1 1146 #define TB_EXIT_REQUESTED 3 1147 1148 #ifdef CONFIG_TCG_INTERPRETER 1149 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); 1150 #else 1151 typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); 1152 extern tcg_prologue_fn *tcg_qemu_tb_exec; 1153 #endif 1154 1155 void tcg_register_jit(const void *buf, size_t buf_size); 1156 1157 #if TCG_TARGET_MAYBE_vec 1158 /* Return zero if the tuple (opc, type, vece) is unsupportable; 1159 return > 0 if it is directly supportable; 1160 return < 0 if we must call tcg_expand_vec_op. */ 1161 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned); 1162 #else 1163 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) 1164 { 1165 return 0; 1166 } 1167 #endif 1168 1169 /* Expand the tuple (opc, type, vece) on the given arguments. */ 1170 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...); 1171 1172 /* Replicate a constant C accoring to the log2 of the element size. */ 1173 uint64_t dup_const(unsigned vece, uint64_t c); 1174 1175 #define dup_const(VECE, C) \ 1176 (__builtin_constant_p(VECE) \ 1177 ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \ 1178 : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \ 1179 : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \ 1180 : (VECE) == MO_64 ? (uint64_t)(C) \ 1181 : (qemu_build_not_reached_always(), 0)) \ 1182 : dup_const(VECE, C)) 1183 1184 #if TARGET_LONG_BITS == 64 1185 # define dup_const_tl dup_const 1186 #else 1187 # define dup_const_tl(VECE, C) \ 1188 (__builtin_constant_p(VECE) \ 1189 ? ( (VECE) == MO_8 ? 0x01010101ul * (uint8_t)(C) \ 1190 : (VECE) == MO_16 ? 0x00010001ul * (uint16_t)(C) \ 1191 : (VECE) == MO_32 ? 0x00000001ul * (uint32_t)(C) \ 1192 : (qemu_build_not_reached_always(), 0)) \ 1193 : (target_long)dup_const(VECE, C)) 1194 #endif 1195 1196 #ifdef CONFIG_DEBUG_TCG 1197 void tcg_assert_listed_vecop(TCGOpcode); 1198 #else 1199 static inline void tcg_assert_listed_vecop(TCGOpcode op) { } 1200 #endif 1201 1202 static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n) 1203 { 1204 #ifdef CONFIG_DEBUG_TCG 1205 const TCGOpcode *o = tcg_ctx->vecop_list; 1206 tcg_ctx->vecop_list = n; 1207 return o; 1208 #else 1209 return NULL; 1210 #endif 1211 } 1212 1213 bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned); 1214 1215 #endif /* TCG_H */ 1216