1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef TCG_H 26 #define TCG_H 27 28 #include "exec/memop.h" 29 #include "exec/memopidx.h" 30 #include "qemu/bitops.h" 31 #include "qemu/plugin.h" 32 #include "qemu/queue.h" 33 #include "tcg/tcg-mo.h" 34 #include "tcg-target-reg-bits.h" 35 #include "tcg-target.h" 36 #include "tcg/tcg-cond.h" 37 #include "tcg/debug-assert.h" 38 39 /* XXX: make safe guess about sizes */ 40 #define MAX_OP_PER_INSTR 266 41 42 #define MAX_CALL_IARGS 7 43 44 #define CPU_TEMP_BUF_NLONGS 128 45 #define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) 46 47 #if TCG_TARGET_REG_BITS == 32 48 typedef int32_t tcg_target_long; 49 typedef uint32_t tcg_target_ulong; 50 #define TCG_PRIlx PRIx32 51 #define TCG_PRIld PRId32 52 #elif TCG_TARGET_REG_BITS == 64 53 typedef int64_t tcg_target_long; 54 typedef uint64_t tcg_target_ulong; 55 #define TCG_PRIlx PRIx64 56 #define TCG_PRIld PRId64 57 #else 58 #error unsupported 59 #endif 60 61 #if TCG_TARGET_NB_REGS <= 32 62 typedef uint32_t TCGRegSet; 63 #elif TCG_TARGET_NB_REGS <= 64 64 typedef uint64_t TCGRegSet; 65 #else 66 #error unsupported 67 #endif 68 69 #if TCG_TARGET_REG_BITS == 32 70 /* Turn some undef macros into false macros. */ 71 #define TCG_TARGET_HAS_extr_i64_i32 0 72 #define TCG_TARGET_HAS_div_i64 0 73 #define TCG_TARGET_HAS_rem_i64 0 74 #define TCG_TARGET_HAS_div2_i64 0 75 #define TCG_TARGET_HAS_rot_i64 0 76 #define TCG_TARGET_HAS_ext8s_i64 0 77 #define TCG_TARGET_HAS_ext16s_i64 0 78 #define TCG_TARGET_HAS_ext32s_i64 0 79 #define TCG_TARGET_HAS_ext8u_i64 0 80 #define TCG_TARGET_HAS_ext16u_i64 0 81 #define TCG_TARGET_HAS_ext32u_i64 0 82 #define TCG_TARGET_HAS_bswap16_i64 0 83 #define TCG_TARGET_HAS_bswap32_i64 0 84 #define TCG_TARGET_HAS_bswap64_i64 0 85 #define TCG_TARGET_HAS_neg_i64 0 86 #define TCG_TARGET_HAS_not_i64 0 87 #define TCG_TARGET_HAS_andc_i64 0 88 #define TCG_TARGET_HAS_orc_i64 0 89 #define TCG_TARGET_HAS_eqv_i64 0 90 #define TCG_TARGET_HAS_nand_i64 0 91 #define TCG_TARGET_HAS_nor_i64 0 92 #define TCG_TARGET_HAS_clz_i64 0 93 #define TCG_TARGET_HAS_ctz_i64 0 94 #define TCG_TARGET_HAS_ctpop_i64 0 95 #define TCG_TARGET_HAS_deposit_i64 0 96 #define TCG_TARGET_HAS_extract_i64 0 97 #define TCG_TARGET_HAS_sextract_i64 0 98 #define TCG_TARGET_HAS_extract2_i64 0 99 #define TCG_TARGET_HAS_movcond_i64 0 100 #define TCG_TARGET_HAS_add2_i64 0 101 #define TCG_TARGET_HAS_sub2_i64 0 102 #define TCG_TARGET_HAS_mulu2_i64 0 103 #define TCG_TARGET_HAS_muls2_i64 0 104 #define TCG_TARGET_HAS_muluh_i64 0 105 #define TCG_TARGET_HAS_mulsh_i64 0 106 /* Turn some undef macros into true macros. */ 107 #define TCG_TARGET_HAS_add2_i32 1 108 #define TCG_TARGET_HAS_sub2_i32 1 109 #endif 110 111 #ifndef TCG_TARGET_deposit_i32_valid 112 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 113 #endif 114 #ifndef TCG_TARGET_deposit_i64_valid 115 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 116 #endif 117 #ifndef TCG_TARGET_extract_i32_valid 118 #define TCG_TARGET_extract_i32_valid(ofs, len) 1 119 #endif 120 #ifndef TCG_TARGET_extract_i64_valid 121 #define TCG_TARGET_extract_i64_valid(ofs, len) 1 122 #endif 123 124 /* Only one of DIV or DIV2 should be defined. */ 125 #if defined(TCG_TARGET_HAS_div_i32) 126 #define TCG_TARGET_HAS_div2_i32 0 127 #elif defined(TCG_TARGET_HAS_div2_i32) 128 #define TCG_TARGET_HAS_div_i32 0 129 #define TCG_TARGET_HAS_rem_i32 0 130 #endif 131 #if defined(TCG_TARGET_HAS_div_i64) 132 #define TCG_TARGET_HAS_div2_i64 0 133 #elif defined(TCG_TARGET_HAS_div2_i64) 134 #define TCG_TARGET_HAS_div_i64 0 135 #define TCG_TARGET_HAS_rem_i64 0 136 #endif 137 138 #if !defined(TCG_TARGET_HAS_v64) \ 139 && !defined(TCG_TARGET_HAS_v128) \ 140 && !defined(TCG_TARGET_HAS_v256) 141 #define TCG_TARGET_MAYBE_vec 0 142 #define TCG_TARGET_HAS_abs_vec 0 143 #define TCG_TARGET_HAS_neg_vec 0 144 #define TCG_TARGET_HAS_not_vec 0 145 #define TCG_TARGET_HAS_andc_vec 0 146 #define TCG_TARGET_HAS_orc_vec 0 147 #define TCG_TARGET_HAS_nand_vec 0 148 #define TCG_TARGET_HAS_nor_vec 0 149 #define TCG_TARGET_HAS_eqv_vec 0 150 #define TCG_TARGET_HAS_roti_vec 0 151 #define TCG_TARGET_HAS_rots_vec 0 152 #define TCG_TARGET_HAS_rotv_vec 0 153 #define TCG_TARGET_HAS_shi_vec 0 154 #define TCG_TARGET_HAS_shs_vec 0 155 #define TCG_TARGET_HAS_shv_vec 0 156 #define TCG_TARGET_HAS_mul_vec 0 157 #define TCG_TARGET_HAS_sat_vec 0 158 #define TCG_TARGET_HAS_minmax_vec 0 159 #define TCG_TARGET_HAS_bitsel_vec 0 160 #define TCG_TARGET_HAS_cmpsel_vec 0 161 #else 162 #define TCG_TARGET_MAYBE_vec 1 163 #endif 164 #ifndef TCG_TARGET_HAS_v64 165 #define TCG_TARGET_HAS_v64 0 166 #endif 167 #ifndef TCG_TARGET_HAS_v128 168 #define TCG_TARGET_HAS_v128 0 169 #endif 170 #ifndef TCG_TARGET_HAS_v256 171 #define TCG_TARGET_HAS_v256 0 172 #endif 173 174 typedef enum TCGOpcode { 175 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, 176 #include "tcg/tcg-opc.h" 177 #undef DEF 178 NB_OPS, 179 } TCGOpcode; 180 181 #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) 182 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r))) 183 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) 184 185 #ifndef TCG_TARGET_INSN_UNIT_SIZE 186 # error "Missing TCG_TARGET_INSN_UNIT_SIZE" 187 #elif TCG_TARGET_INSN_UNIT_SIZE == 1 188 typedef uint8_t tcg_insn_unit; 189 #elif TCG_TARGET_INSN_UNIT_SIZE == 2 190 typedef uint16_t tcg_insn_unit; 191 #elif TCG_TARGET_INSN_UNIT_SIZE == 4 192 typedef uint32_t tcg_insn_unit; 193 #elif TCG_TARGET_INSN_UNIT_SIZE == 8 194 typedef uint64_t tcg_insn_unit; 195 #else 196 /* The port better have done this. */ 197 #endif 198 199 typedef struct TCGRelocation TCGRelocation; 200 struct TCGRelocation { 201 QSIMPLEQ_ENTRY(TCGRelocation) next; 202 tcg_insn_unit *ptr; 203 intptr_t addend; 204 int type; 205 }; 206 207 typedef struct TCGOp TCGOp; 208 typedef struct TCGLabelUse TCGLabelUse; 209 struct TCGLabelUse { 210 QSIMPLEQ_ENTRY(TCGLabelUse) next; 211 TCGOp *op; 212 }; 213 214 typedef struct TCGLabel TCGLabel; 215 struct TCGLabel { 216 bool present; 217 bool has_value; 218 uint16_t id; 219 union { 220 uintptr_t value; 221 const tcg_insn_unit *value_ptr; 222 } u; 223 QSIMPLEQ_HEAD(, TCGLabelUse) branches; 224 QSIMPLEQ_HEAD(, TCGRelocation) relocs; 225 QSIMPLEQ_ENTRY(TCGLabel) next; 226 }; 227 228 typedef struct TCGPool { 229 struct TCGPool *next; 230 int size; 231 uint8_t data[] __attribute__ ((aligned)); 232 } TCGPool; 233 234 #define TCG_POOL_CHUNK_SIZE 32768 235 236 #define TCG_MAX_TEMPS 512 237 #define TCG_MAX_INSNS 512 238 239 /* when the size of the arguments of a called function is smaller than 240 this value, they are statically allocated in the TB stack frame */ 241 #define TCG_STATIC_CALL_ARGS_SIZE 128 242 243 typedef enum TCGType { 244 TCG_TYPE_I32, 245 TCG_TYPE_I64, 246 TCG_TYPE_I128, 247 248 TCG_TYPE_V64, 249 TCG_TYPE_V128, 250 TCG_TYPE_V256, 251 252 /* Number of different types (integer not enum) */ 253 #define TCG_TYPE_COUNT (TCG_TYPE_V256 + 1) 254 255 /* An alias for the size of the host register. */ 256 #if TCG_TARGET_REG_BITS == 32 257 TCG_TYPE_REG = TCG_TYPE_I32, 258 #else 259 TCG_TYPE_REG = TCG_TYPE_I64, 260 #endif 261 262 /* An alias for the size of the native pointer. */ 263 #if UINTPTR_MAX == UINT32_MAX 264 TCG_TYPE_PTR = TCG_TYPE_I32, 265 #else 266 TCG_TYPE_PTR = TCG_TYPE_I64, 267 #endif 268 } TCGType; 269 270 /** 271 * tcg_type_size 272 * @t: type 273 * 274 * Return the size of the type in bytes. 275 */ 276 static inline int tcg_type_size(TCGType t) 277 { 278 unsigned i = t; 279 if (i >= TCG_TYPE_V64) { 280 tcg_debug_assert(i < TCG_TYPE_COUNT); 281 i -= TCG_TYPE_V64 - 1; 282 } 283 return 4 << i; 284 } 285 286 /** 287 * get_alignment_bits 288 * @memop: MemOp value 289 * 290 * Extract the alignment size from the memop. 291 */ 292 static inline unsigned get_alignment_bits(MemOp memop) 293 { 294 unsigned a = memop & MO_AMASK; 295 296 if (a == MO_UNALN) { 297 /* No alignment required. */ 298 a = 0; 299 } else if (a == MO_ALIGN) { 300 /* A natural alignment requirement. */ 301 a = memop & MO_SIZE; 302 } else { 303 /* A specific alignment requirement. */ 304 a = a >> MO_ASHIFT; 305 } 306 return a; 307 } 308 309 typedef tcg_target_ulong TCGArg; 310 311 /* Define type and accessor macros for TCG variables. 312 313 TCG variables are the inputs and outputs of TCG ops, as described 314 in tcg/README. Target CPU front-end code uses these types to deal 315 with TCG variables as it emits TCG code via the tcg_gen_* functions. 316 They come in several flavours: 317 * TCGv_i32 : 32 bit integer type 318 * TCGv_i64 : 64 bit integer type 319 * TCGv_i128 : 128 bit integer type 320 * TCGv_ptr : a host pointer type 321 * TCGv_vec : a host vector type; the exact size is not exposed 322 to the CPU front-end code. 323 * TCGv : an integer type the same size as target_ulong 324 (an alias for either TCGv_i32 or TCGv_i64) 325 The compiler's type checking will complain if you mix them 326 up and pass the wrong sized TCGv to a function. 327 328 Users of tcg_gen_* don't need to know about any of the internal 329 details of these, and should treat them as opaque types. 330 You won't be able to look inside them in a debugger either. 331 332 Internal implementation details follow: 333 334 Note that there is no definition of the structs TCGv_i32_d etc anywhere. 335 This is deliberate, because the values we store in variables of type 336 TCGv_i32 are not really pointers-to-structures. They're just small 337 integers, but keeping them in pointer types like this means that the 338 compiler will complain if you accidentally pass a TCGv_i32 to a 339 function which takes a TCGv_i64, and so on. Only the internals of 340 TCG need to care about the actual contents of the types. */ 341 342 typedef struct TCGv_i32_d *TCGv_i32; 343 typedef struct TCGv_i64_d *TCGv_i64; 344 typedef struct TCGv_i128_d *TCGv_i128; 345 typedef struct TCGv_ptr_d *TCGv_ptr; 346 typedef struct TCGv_vec_d *TCGv_vec; 347 typedef TCGv_ptr TCGv_env; 348 349 /* call flags */ 350 /* Helper does not read globals (either directly or through an exception). It 351 implies TCG_CALL_NO_WRITE_GLOBALS. */ 352 #define TCG_CALL_NO_READ_GLOBALS 0x0001 353 /* Helper does not write globals */ 354 #define TCG_CALL_NO_WRITE_GLOBALS 0x0002 355 /* Helper can be safely suppressed if the return value is not used. */ 356 #define TCG_CALL_NO_SIDE_EFFECTS 0x0004 357 /* Helper is G_NORETURN. */ 358 #define TCG_CALL_NO_RETURN 0x0008 359 /* Helper is part of Plugins. */ 360 #define TCG_CALL_PLUGIN 0x0010 361 362 /* convenience version of most used call flags */ 363 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS 364 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS 365 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS 366 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) 367 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) 368 369 /* 370 * Flags for the bswap opcodes. 371 * If IZ, the input is zero-extended, otherwise unknown. 372 * If OZ or OS, the output is zero- or sign-extended respectively, 373 * otherwise the high bits are undefined. 374 */ 375 enum { 376 TCG_BSWAP_IZ = 1, 377 TCG_BSWAP_OZ = 2, 378 TCG_BSWAP_OS = 4, 379 }; 380 381 typedef enum TCGTempVal { 382 TEMP_VAL_DEAD, 383 TEMP_VAL_REG, 384 TEMP_VAL_MEM, 385 TEMP_VAL_CONST, 386 } TCGTempVal; 387 388 typedef enum TCGTempKind { 389 /* 390 * Temp is dead at the end of the extended basic block (EBB), 391 * the single-entry multiple-exit region that falls through 392 * conditional branches. 393 */ 394 TEMP_EBB, 395 /* Temp is live across the entire translation block, but dead at end. */ 396 TEMP_TB, 397 /* Temp is live across the entire translation block, and between them. */ 398 TEMP_GLOBAL, 399 /* Temp is in a fixed register. */ 400 TEMP_FIXED, 401 /* Temp is a fixed constant. */ 402 TEMP_CONST, 403 } TCGTempKind; 404 405 typedef struct TCGTemp { 406 TCGReg reg:8; 407 TCGTempVal val_type:8; 408 TCGType base_type:8; 409 TCGType type:8; 410 TCGTempKind kind:3; 411 unsigned int indirect_reg:1; 412 unsigned int indirect_base:1; 413 unsigned int mem_coherent:1; 414 unsigned int mem_allocated:1; 415 unsigned int temp_allocated:1; 416 unsigned int temp_subindex:1; 417 418 int64_t val; 419 struct TCGTemp *mem_base; 420 intptr_t mem_offset; 421 const char *name; 422 423 /* Pass-specific information that can be stored for a temporary. 424 One word worth of integer data, and one pointer to data 425 allocated separately. */ 426 uintptr_t state; 427 void *state_ptr; 428 } TCGTemp; 429 430 typedef struct TCGContext TCGContext; 431 432 typedef struct TCGTempSet { 433 unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; 434 } TCGTempSet; 435 436 /* 437 * With 1 128-bit output, a 32-bit host requires 4 output parameters, 438 * which leaves a maximum of 28 other slots. Which is enough for 7 439 * 128-bit operands. 440 */ 441 #define DEAD_ARG (1 << 4) 442 #define SYNC_ARG (1 << 0) 443 typedef uint32_t TCGLifeData; 444 445 struct TCGOp { 446 TCGOpcode opc : 8; 447 unsigned nargs : 8; 448 449 /* Parameters for this opcode. See below. */ 450 unsigned param1 : 8; 451 unsigned param2 : 8; 452 453 /* Lifetime data of the operands. */ 454 TCGLifeData life; 455 456 /* Next and previous opcodes. */ 457 QTAILQ_ENTRY(TCGOp) link; 458 459 /* Register preferences for the output(s). */ 460 TCGRegSet output_pref[2]; 461 462 /* Arguments for the opcode. */ 463 TCGArg args[]; 464 }; 465 466 #define TCGOP_CALLI(X) (X)->param1 467 #define TCGOP_CALLO(X) (X)->param2 468 469 #define TCGOP_VECL(X) (X)->param1 470 #define TCGOP_VECE(X) (X)->param2 471 472 /* Make sure operands fit in the bitfields above. */ 473 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); 474 475 static inline TCGRegSet output_pref(const TCGOp *op, unsigned i) 476 { 477 return i < ARRAY_SIZE(op->output_pref) ? op->output_pref[i] : 0; 478 } 479 480 struct TCGContext { 481 uint8_t *pool_cur, *pool_end; 482 TCGPool *pool_first, *pool_current, *pool_first_large; 483 int nb_labels; 484 int nb_globals; 485 int nb_temps; 486 int nb_indirects; 487 int nb_ops; 488 TCGType addr_type; /* TCG_TYPE_I32 or TCG_TYPE_I64 */ 489 490 #ifdef CONFIG_SOFTMMU 491 int tlb_fast_offset; 492 int page_mask; 493 uint8_t page_bits; 494 uint8_t tlb_dyn_max_bits; 495 #endif 496 uint8_t insn_start_words; 497 TCGBar guest_mo; 498 499 TCGRegSet reserved_regs; 500 intptr_t current_frame_offset; 501 intptr_t frame_start; 502 intptr_t frame_end; 503 TCGTemp *frame_temp; 504 505 TranslationBlock *gen_tb; /* tb for which code is being generated */ 506 tcg_insn_unit *code_buf; /* pointer for start of tb */ 507 tcg_insn_unit *code_ptr; /* pointer for running end of tb */ 508 509 #ifdef CONFIG_DEBUG_TCG 510 int goto_tb_issue_mask; 511 const TCGOpcode *vecop_list; 512 #endif 513 514 /* Code generation. Note that we specifically do not use tcg_insn_unit 515 here, because there's too much arithmetic throughout that relies 516 on addition and subtraction working on bytes. Rely on the GCC 517 extension that allows arithmetic on void*. */ 518 void *code_gen_buffer; 519 size_t code_gen_buffer_size; 520 void *code_gen_ptr; 521 void *data_gen_ptr; 522 523 /* Threshold to flush the translated code buffer. */ 524 void *code_gen_highwater; 525 526 /* Track which vCPU triggers events */ 527 CPUState *cpu; /* *_trans */ 528 529 /* These structures are private to tcg-target.c.inc. */ 530 #ifdef TCG_TARGET_NEED_LDST_LABELS 531 QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; 532 #endif 533 #ifdef TCG_TARGET_NEED_POOL_LABELS 534 struct TCGLabelPoolData *pool_labels; 535 #endif 536 537 TCGLabel *exitreq_label; 538 539 #ifdef CONFIG_PLUGIN 540 /* 541 * We keep one plugin_tb struct per TCGContext. Note that on every TB 542 * translation we clear but do not free its contents; this way we 543 * avoid a lot of malloc/free churn, since after a few TB's it's 544 * unlikely that we'll need to allocate either more instructions or more 545 * space for instructions (for variable-instruction-length ISAs). 546 */ 547 struct qemu_plugin_tb *plugin_tb; 548 549 /* descriptor of the instruction being translated */ 550 struct qemu_plugin_insn *plugin_insn; 551 #endif 552 553 GHashTable *const_table[TCG_TYPE_COUNT]; 554 TCGTempSet free_temps[TCG_TYPE_COUNT]; 555 TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ 556 557 QTAILQ_HEAD(, TCGOp) ops, free_ops; 558 QSIMPLEQ_HEAD(, TCGLabel) labels; 559 560 /* Tells which temporary holds a given register. 561 It does not take into account fixed registers */ 562 TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; 563 564 uint16_t gen_insn_end_off[TCG_MAX_INSNS]; 565 uint64_t *gen_insn_data; 566 567 /* Exit to translator on overflow. */ 568 sigjmp_buf jmp_trans; 569 }; 570 571 static inline bool temp_readonly(TCGTemp *ts) 572 { 573 return ts->kind >= TEMP_FIXED; 574 } 575 576 extern __thread TCGContext *tcg_ctx; 577 extern const void *tcg_code_gen_epilogue; 578 extern uintptr_t tcg_splitwx_diff; 579 extern TCGv_env cpu_env; 580 581 bool in_code_gen_buffer(const void *p); 582 583 #ifdef CONFIG_DEBUG_TCG 584 const void *tcg_splitwx_to_rx(void *rw); 585 void *tcg_splitwx_to_rw(const void *rx); 586 #else 587 static inline const void *tcg_splitwx_to_rx(void *rw) 588 { 589 return rw ? rw + tcg_splitwx_diff : NULL; 590 } 591 592 static inline void *tcg_splitwx_to_rw(const void *rx) 593 { 594 return rx ? (void *)rx - tcg_splitwx_diff : NULL; 595 } 596 #endif 597 598 static inline TCGArg temp_arg(TCGTemp *ts) 599 { 600 return (uintptr_t)ts; 601 } 602 603 static inline TCGTemp *arg_temp(TCGArg a) 604 { 605 return (TCGTemp *)(uintptr_t)a; 606 } 607 608 #ifdef CONFIG_DEBUG_TCG 609 size_t temp_idx(TCGTemp *ts); 610 TCGTemp *tcgv_i32_temp(TCGv_i32 v); 611 #else 612 static inline size_t temp_idx(TCGTemp *ts) 613 { 614 return ts - tcg_ctx->temps; 615 } 616 617 /* 618 * Using the offset of a temporary, relative to TCGContext, rather than 619 * its index means that we don't use 0. That leaves offset 0 free for 620 * a NULL representation without having to leave index 0 unused. 621 */ 622 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) 623 { 624 return (void *)tcg_ctx + (uintptr_t)v; 625 } 626 #endif 627 628 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) 629 { 630 return tcgv_i32_temp((TCGv_i32)v); 631 } 632 633 static inline TCGTemp *tcgv_i128_temp(TCGv_i128 v) 634 { 635 return tcgv_i32_temp((TCGv_i32)v); 636 } 637 638 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) 639 { 640 return tcgv_i32_temp((TCGv_i32)v); 641 } 642 643 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v) 644 { 645 return tcgv_i32_temp((TCGv_i32)v); 646 } 647 648 static inline TCGArg tcgv_i32_arg(TCGv_i32 v) 649 { 650 return temp_arg(tcgv_i32_temp(v)); 651 } 652 653 static inline TCGArg tcgv_i64_arg(TCGv_i64 v) 654 { 655 return temp_arg(tcgv_i64_temp(v)); 656 } 657 658 static inline TCGArg tcgv_i128_arg(TCGv_i128 v) 659 { 660 return temp_arg(tcgv_i128_temp(v)); 661 } 662 663 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) 664 { 665 return temp_arg(tcgv_ptr_temp(v)); 666 } 667 668 static inline TCGArg tcgv_vec_arg(TCGv_vec v) 669 { 670 return temp_arg(tcgv_vec_temp(v)); 671 } 672 673 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) 674 { 675 (void)temp_idx(t); /* trigger embedded assert */ 676 return (TCGv_i32)((void *)t - (void *)tcg_ctx); 677 } 678 679 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) 680 { 681 return (TCGv_i64)temp_tcgv_i32(t); 682 } 683 684 static inline TCGv_i128 temp_tcgv_i128(TCGTemp *t) 685 { 686 return (TCGv_i128)temp_tcgv_i32(t); 687 } 688 689 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) 690 { 691 return (TCGv_ptr)temp_tcgv_i32(t); 692 } 693 694 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) 695 { 696 return (TCGv_vec)temp_tcgv_i32(t); 697 } 698 699 static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) 700 { 701 return op->args[arg]; 702 } 703 704 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) 705 { 706 op->args[arg] = v; 707 } 708 709 static inline uint64_t tcg_get_insn_start_param(TCGOp *op, int arg) 710 { 711 if (TCG_TARGET_REG_BITS == 64) { 712 return tcg_get_insn_param(op, arg); 713 } else { 714 return deposit64(tcg_get_insn_param(op, arg * 2), 32, 32, 715 tcg_get_insn_param(op, arg * 2 + 1)); 716 } 717 } 718 719 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, uint64_t v) 720 { 721 if (TCG_TARGET_REG_BITS == 64) { 722 tcg_set_insn_param(op, arg, v); 723 } else { 724 tcg_set_insn_param(op, arg * 2, v); 725 tcg_set_insn_param(op, arg * 2 + 1, v >> 32); 726 } 727 } 728 729 /* The last op that was emitted. */ 730 static inline TCGOp *tcg_last_op(void) 731 { 732 return QTAILQ_LAST(&tcg_ctx->ops); 733 } 734 735 /* Test for whether to terminate the TB for using too many opcodes. */ 736 static inline bool tcg_op_buf_full(void) 737 { 738 /* This is not a hard limit, it merely stops translation when 739 * we have produced "enough" opcodes. We want to limit TB size 740 * such that a RISC host can reasonably use a 16-bit signed 741 * branch within the TB. We also need to be mindful of the 742 * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[] 743 * and TCGContext.gen_insn_end_off[]. 744 */ 745 return tcg_ctx->nb_ops >= 4000; 746 } 747 748 /* pool based memory allocation */ 749 750 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */ 751 void *tcg_malloc_internal(TCGContext *s, int size); 752 void tcg_pool_reset(TCGContext *s); 753 TranslationBlock *tcg_tb_alloc(TCGContext *s); 754 755 void tcg_region_reset_all(void); 756 757 size_t tcg_code_size(void); 758 size_t tcg_code_capacity(void); 759 760 void tcg_tb_insert(TranslationBlock *tb); 761 void tcg_tb_remove(TranslationBlock *tb); 762 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr); 763 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data); 764 size_t tcg_nb_tbs(void); 765 766 /* user-mode: Called with mmap_lock held. */ 767 static inline void *tcg_malloc(int size) 768 { 769 TCGContext *s = tcg_ctx; 770 uint8_t *ptr, *ptr_end; 771 772 /* ??? This is a weak placeholder for minimum malloc alignment. */ 773 size = QEMU_ALIGN_UP(size, 8); 774 775 ptr = s->pool_cur; 776 ptr_end = ptr + size; 777 if (unlikely(ptr_end > s->pool_end)) { 778 return tcg_malloc_internal(tcg_ctx, size); 779 } else { 780 s->pool_cur = ptr_end; 781 return ptr; 782 } 783 } 784 785 void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus); 786 void tcg_register_thread(void); 787 void tcg_prologue_init(TCGContext *s); 788 void tcg_func_start(TCGContext *s); 789 790 int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start); 791 792 void tb_target_set_jmp_target(const TranslationBlock *, int, 793 uintptr_t, uintptr_t); 794 795 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); 796 797 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, 798 intptr_t, const char *); 799 TCGTemp *tcg_temp_new_internal(TCGType, TCGTempKind); 800 TCGv_vec tcg_temp_new_vec(TCGType type); 801 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); 802 803 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, 804 const char *name) 805 { 806 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name); 807 return temp_tcgv_i32(t); 808 } 809 810 static inline TCGv_i32 tcg_temp_new_i32(void) 811 { 812 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_TB); 813 return temp_tcgv_i32(t); 814 } 815 816 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, 817 const char *name) 818 { 819 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name); 820 return temp_tcgv_i64(t); 821 } 822 823 static inline TCGv_i64 tcg_temp_new_i64(void) 824 { 825 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_TB); 826 return temp_tcgv_i64(t); 827 } 828 829 static inline TCGv_i128 tcg_temp_new_i128(void) 830 { 831 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_TB); 832 return temp_tcgv_i128(t); 833 } 834 835 static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, 836 const char *name) 837 { 838 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name); 839 return temp_tcgv_ptr(t); 840 } 841 842 static inline TCGv_ptr tcg_temp_new_ptr(void) 843 { 844 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_TB); 845 return temp_tcgv_ptr(t); 846 } 847 848 void tcg_dump_info(GString *buf); 849 void tcg_dump_op_count(GString *buf); 850 851 #define TCG_CT_CONST 1 /* any constant of register size */ 852 853 typedef struct TCGArgConstraint { 854 unsigned ct : 16; 855 unsigned alias_index : 4; 856 unsigned sort_index : 4; 857 unsigned pair_index : 4; 858 unsigned pair : 2; /* 0: none, 1: first, 2: second, 3: second alias */ 859 bool oalias : 1; 860 bool ialias : 1; 861 bool newreg : 1; 862 TCGRegSet regs; 863 } TCGArgConstraint; 864 865 #define TCG_MAX_OP_ARGS 16 866 867 /* Bits for TCGOpDef->flags, 8 bits available, all used. */ 868 enum { 869 /* Instruction exits the translation block. */ 870 TCG_OPF_BB_EXIT = 0x01, 871 /* Instruction defines the end of a basic block. */ 872 TCG_OPF_BB_END = 0x02, 873 /* Instruction clobbers call registers and potentially update globals. */ 874 TCG_OPF_CALL_CLOBBER = 0x04, 875 /* Instruction has side effects: it cannot be removed if its outputs 876 are not used, and might trigger exceptions. */ 877 TCG_OPF_SIDE_EFFECTS = 0x08, 878 /* Instruction operands are 64-bits (otherwise 32-bits). */ 879 TCG_OPF_64BIT = 0x10, 880 /* Instruction is optional and not implemented by the host, or insn 881 is generic and should not be implemened by the host. */ 882 TCG_OPF_NOT_PRESENT = 0x20, 883 /* Instruction operands are vectors. */ 884 TCG_OPF_VECTOR = 0x40, 885 /* Instruction is a conditional branch. */ 886 TCG_OPF_COND_BRANCH = 0x80 887 }; 888 889 typedef struct TCGOpDef { 890 const char *name; 891 uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; 892 uint8_t flags; 893 TCGArgConstraint *args_ct; 894 } TCGOpDef; 895 896 extern TCGOpDef tcg_op_defs[]; 897 extern const size_t tcg_op_defs_max; 898 899 typedef struct TCGTargetOpDef { 900 TCGOpcode op; 901 const char *args_ct_str[TCG_MAX_OP_ARGS]; 902 } TCGTargetOpDef; 903 904 bool tcg_op_supported(TCGOpcode op); 905 906 void tcg_gen_call0(TCGHelperInfo *, TCGTemp *ret); 907 void tcg_gen_call1(TCGHelperInfo *, TCGTemp *ret, TCGTemp *); 908 void tcg_gen_call2(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *); 909 void tcg_gen_call3(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, 910 TCGTemp *, TCGTemp *); 911 void tcg_gen_call4(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *, 912 TCGTemp *, TCGTemp *); 913 void tcg_gen_call5(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *, 914 TCGTemp *, TCGTemp *, TCGTemp *); 915 void tcg_gen_call6(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *, 916 TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *); 917 void tcg_gen_call7(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *, 918 TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *); 919 920 TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs); 921 void tcg_op_remove(TCGContext *s, TCGOp *op); 922 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, 923 TCGOpcode opc, unsigned nargs); 924 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, 925 TCGOpcode opc, unsigned nargs); 926 927 /** 928 * tcg_remove_ops_after: 929 * @op: target operation 930 * 931 * Discard any opcodes emitted since @op. Expected usage is to save 932 * a starting point with tcg_last_op(), speculatively emit opcodes, 933 * then decide whether or not to keep those opcodes after the fact. 934 */ 935 void tcg_remove_ops_after(TCGOp *op); 936 937 void tcg_optimize(TCGContext *s); 938 939 /* 940 * Locate or create a read-only temporary that is a constant. 941 * This kind of temporary need not be freed, but for convenience 942 * will be silently ignored by tcg_temp_free_*. 943 */ 944 TCGTemp *tcg_constant_internal(TCGType type, int64_t val); 945 946 static inline TCGv_i32 tcg_constant_i32(int32_t val) 947 { 948 return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); 949 } 950 951 static inline TCGv_i64 tcg_constant_i64(int64_t val) 952 { 953 return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); 954 } 955 956 TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); 957 TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); 958 959 #if UINTPTR_MAX == UINT32_MAX 960 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x))) 961 #else 962 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x))) 963 #endif 964 965 TCGLabel *gen_new_label(void); 966 967 /** 968 * label_arg 969 * @l: label 970 * 971 * Encode a label for storage in the TCG opcode stream. 972 */ 973 974 static inline TCGArg label_arg(TCGLabel *l) 975 { 976 return (uintptr_t)l; 977 } 978 979 /** 980 * arg_label 981 * @i: value 982 * 983 * The opposite of label_arg. Retrieve a label from the 984 * encoding of the TCG opcode stream. 985 */ 986 987 static inline TCGLabel *arg_label(TCGArg i) 988 { 989 return (TCGLabel *)(uintptr_t)i; 990 } 991 992 /** 993 * tcg_ptr_byte_diff 994 * @a, @b: addresses to be differenced 995 * 996 * There are many places within the TCG backends where we need a byte 997 * difference between two pointers. While this can be accomplished 998 * with local casting, it's easy to get wrong -- especially if one is 999 * concerned with the signedness of the result. 1000 * 1001 * This version relies on GCC's void pointer arithmetic to get the 1002 * correct result. 1003 */ 1004 1005 static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) 1006 { 1007 return a - b; 1008 } 1009 1010 /** 1011 * tcg_pcrel_diff 1012 * @s: the tcg context 1013 * @target: address of the target 1014 * 1015 * Produce a pc-relative difference, from the current code_ptr 1016 * to the destination address. 1017 */ 1018 1019 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) 1020 { 1021 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); 1022 } 1023 1024 /** 1025 * tcg_tbrel_diff 1026 * @s: the tcg context 1027 * @target: address of the target 1028 * 1029 * Produce a difference, from the beginning of the current TB code 1030 * to the destination address. 1031 */ 1032 static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, const void *target) 1033 { 1034 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_buf)); 1035 } 1036 1037 /** 1038 * tcg_current_code_size 1039 * @s: the tcg context 1040 * 1041 * Compute the current code size within the translation block. 1042 * This is used to fill in qemu's data structures for goto_tb. 1043 */ 1044 1045 static inline size_t tcg_current_code_size(TCGContext *s) 1046 { 1047 return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); 1048 } 1049 1050 /** 1051 * tcg_qemu_tb_exec: 1052 * @env: pointer to CPUArchState for the CPU 1053 * @tb_ptr: address of generated code for the TB to execute 1054 * 1055 * Start executing code from a given translation block. 1056 * Where translation blocks have been linked, execution 1057 * may proceed from the given TB into successive ones. 1058 * Control eventually returns only when some action is needed 1059 * from the top-level loop: either control must pass to a TB 1060 * which has not yet been directly linked, or an asynchronous 1061 * event such as an interrupt needs handling. 1062 * 1063 * Return: The return value is the value passed to the corresponding 1064 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute. 1065 * The value is either zero or a 4-byte aligned pointer to that TB combined 1066 * with additional information in its two least significant bits. The 1067 * additional information is encoded as follows: 1068 * 0, 1: the link between this TB and the next is via the specified 1069 * TB index (0 or 1). That is, we left the TB via (the equivalent 1070 * of) "goto_tb <index>". The main loop uses this to determine 1071 * how to link the TB just executed to the next. 1072 * 2: we are using instruction counting code generation, and we 1073 * did not start executing this TB because the instruction counter 1074 * would hit zero midway through it. In this case the pointer 1075 * returned is the TB we were about to execute, and the caller must 1076 * arrange to execute the remaining count of instructions. 1077 * 3: we stopped because the CPU's exit_request flag was set 1078 * (usually meaning that there is an interrupt that needs to be 1079 * handled). The pointer returned is the TB we were about to execute 1080 * when we noticed the pending exit request. 1081 * 1082 * If the bottom two bits indicate an exit-via-index then the CPU 1083 * state is correctly synchronised and ready for execution of the next 1084 * TB (and in particular the guest PC is the address to execute next). 1085 * Otherwise, we gave up on execution of this TB before it started, and 1086 * the caller must fix up the CPU state by calling the CPU's 1087 * synchronize_from_tb() method with the TB pointer we return (falling 1088 * back to calling the CPU's set_pc method with tb->pb if no 1089 * synchronize_from_tb() method exists). 1090 * 1091 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec 1092 * to this default (which just calls the prologue.code emitted by 1093 * tcg_target_qemu_prologue()). 1094 */ 1095 #define TB_EXIT_MASK 3 1096 #define TB_EXIT_IDX0 0 1097 #define TB_EXIT_IDX1 1 1098 #define TB_EXIT_IDXMAX 1 1099 #define TB_EXIT_REQUESTED 3 1100 1101 #ifdef CONFIG_TCG_INTERPRETER 1102 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); 1103 #else 1104 typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); 1105 extern tcg_prologue_fn *tcg_qemu_tb_exec; 1106 #endif 1107 1108 void tcg_register_jit(const void *buf, size_t buf_size); 1109 1110 #if TCG_TARGET_MAYBE_vec 1111 /* Return zero if the tuple (opc, type, vece) is unsupportable; 1112 return > 0 if it is directly supportable; 1113 return < 0 if we must call tcg_expand_vec_op. */ 1114 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned); 1115 #else 1116 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) 1117 { 1118 return 0; 1119 } 1120 #endif 1121 1122 /* Expand the tuple (opc, type, vece) on the given arguments. */ 1123 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...); 1124 1125 /* Replicate a constant C accoring to the log2 of the element size. */ 1126 uint64_t dup_const(unsigned vece, uint64_t c); 1127 1128 #define dup_const(VECE, C) \ 1129 (__builtin_constant_p(VECE) \ 1130 ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \ 1131 : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \ 1132 : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \ 1133 : (VECE) == MO_64 ? (uint64_t)(C) \ 1134 : (qemu_build_not_reached_always(), 0)) \ 1135 : dup_const(VECE, C)) 1136 1137 static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n) 1138 { 1139 #ifdef CONFIG_DEBUG_TCG 1140 const TCGOpcode *o = tcg_ctx->vecop_list; 1141 tcg_ctx->vecop_list = n; 1142 return o; 1143 #else 1144 return NULL; 1145 #endif 1146 } 1147 1148 bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned); 1149 1150 #endif /* TCG_H */ 1151