xref: /openbmc/qemu/include/sysemu/numa.h (revision 9b12dfa03a94d7f7a4b54eb67229a31e58193384)
1e35704baSEduardo Habkost #ifndef SYSEMU_NUMA_H
2e35704baSEduardo Habkost #define SYSEMU_NUMA_H
3e35704baSEduardo Habkost 
4e35704baSEduardo Habkost #include "qemu/bitmap.h"
5a44432b4SMarkus Armbruster #include "qapi/qapi-types-machine.h"
6a44432b4SMarkus Armbruster #include "exec/cpu-common.h"
7a44432b4SMarkus Armbruster 
8a44432b4SMarkus Armbruster struct CPUArchId;
9e35704baSEduardo Habkost 
10b58c5c2dSMarkus Armbruster #define MAX_NODES 128
11b58c5c2dSMarkus Armbruster #define NUMA_NODE_UNASSIGNED MAX_NODES
12b58c5c2dSMarkus Armbruster #define NUMA_DISTANCE_MIN         10
13b58c5c2dSMarkus Armbruster #define NUMA_DISTANCE_DEFAULT     20
14b58c5c2dSMarkus Armbruster #define NUMA_DISTANCE_MAX         254
15b58c5c2dSMarkus Armbruster #define NUMA_DISTANCE_UNREACHABLE 255
16b58c5c2dSMarkus Armbruster 
17*9b12dfa0SLiu Jingqi /* the value of AcpiHmatLBInfo flags */
18*9b12dfa0SLiu Jingqi enum {
19*9b12dfa0SLiu Jingqi     HMAT_LB_MEM_MEMORY           = 0,
20*9b12dfa0SLiu Jingqi     HMAT_LB_MEM_CACHE_1ST_LEVEL  = 1,
21*9b12dfa0SLiu Jingqi     HMAT_LB_MEM_CACHE_2ND_LEVEL  = 2,
22*9b12dfa0SLiu Jingqi     HMAT_LB_MEM_CACHE_3RD_LEVEL  = 3,
23*9b12dfa0SLiu Jingqi     HMAT_LB_LEVELS   /* must be the last entry */
24*9b12dfa0SLiu Jingqi };
25*9b12dfa0SLiu Jingqi 
26*9b12dfa0SLiu Jingqi /* the value of AcpiHmatLBInfo data type */
27*9b12dfa0SLiu Jingqi enum {
28*9b12dfa0SLiu Jingqi     HMAT_LB_DATA_ACCESS_LATENCY   = 0,
29*9b12dfa0SLiu Jingqi     HMAT_LB_DATA_READ_LATENCY     = 1,
30*9b12dfa0SLiu Jingqi     HMAT_LB_DATA_WRITE_LATENCY    = 2,
31*9b12dfa0SLiu Jingqi     HMAT_LB_DATA_ACCESS_BANDWIDTH = 3,
32*9b12dfa0SLiu Jingqi     HMAT_LB_DATA_READ_BANDWIDTH   = 4,
33*9b12dfa0SLiu Jingqi     HMAT_LB_DATA_WRITE_BANDWIDTH  = 5,
34*9b12dfa0SLiu Jingqi     HMAT_LB_TYPES   /* must be the last entry */
35*9b12dfa0SLiu Jingqi };
36*9b12dfa0SLiu Jingqi 
37*9b12dfa0SLiu Jingqi #define UINT16_BITS       16
38*9b12dfa0SLiu Jingqi 
39aec90730SEric Blake struct NodeInfo {
40e35704baSEduardo Habkost     uint64_t node_mem;
41e35704baSEduardo Habkost     struct HostMemoryBackend *node_memdev;
42e35704baSEduardo Habkost     bool present;
43244b3f44STao Xu     bool has_cpu;
44*9b12dfa0SLiu Jingqi     uint8_t lb_info_provided;
45244b3f44STao Xu     uint16_t initiator;
460f203430SHe Chen     uint8_t distance[MAX_NODES];
473bfe5716SLaurent Vivier };
48fa9ea81dSBharata B Rao 
4931959e82SVadim Galitsyn struct NumaNodeMem {
5031959e82SVadim Galitsyn     uint64_t node_mem;
5131959e82SVadim Galitsyn     uint64_t node_plugged_mem;
5231959e82SVadim Galitsyn };
5331959e82SVadim Galitsyn 
54*9b12dfa0SLiu Jingqi struct HMAT_LB_Data {
55*9b12dfa0SLiu Jingqi     uint8_t     initiator;
56*9b12dfa0SLiu Jingqi     uint8_t     target;
57*9b12dfa0SLiu Jingqi     uint64_t    data;
58*9b12dfa0SLiu Jingqi };
59*9b12dfa0SLiu Jingqi typedef struct HMAT_LB_Data HMAT_LB_Data;
60*9b12dfa0SLiu Jingqi 
61*9b12dfa0SLiu Jingqi struct HMAT_LB_Info {
62*9b12dfa0SLiu Jingqi     /* Indicates it's memory or the specified level memory side cache. */
63*9b12dfa0SLiu Jingqi     uint8_t     hierarchy;
64*9b12dfa0SLiu Jingqi 
65*9b12dfa0SLiu Jingqi     /* Present the type of data, access/read/write latency or bandwidth. */
66*9b12dfa0SLiu Jingqi     uint8_t     data_type;
67*9b12dfa0SLiu Jingqi 
68*9b12dfa0SLiu Jingqi     /* The range bitmap of bandwidth for calculating common base */
69*9b12dfa0SLiu Jingqi     uint64_t    range_bitmap;
70*9b12dfa0SLiu Jingqi 
71*9b12dfa0SLiu Jingqi     /* The common base unit for latencies or bandwidths */
72*9b12dfa0SLiu Jingqi     uint64_t    base;
73*9b12dfa0SLiu Jingqi 
74*9b12dfa0SLiu Jingqi     /* Array to store the latencies or bandwidths */
75*9b12dfa0SLiu Jingqi     GArray      *list;
76*9b12dfa0SLiu Jingqi };
77*9b12dfa0SLiu Jingqi typedef struct HMAT_LB_Info HMAT_LB_Info;
78*9b12dfa0SLiu Jingqi 
79aa570207STao Xu struct NumaState {
80aa570207STao Xu     /* Number of NUMA nodes */
81aa570207STao Xu     int num_nodes;
82aa570207STao Xu 
83118154b7STao Xu     /* Allow setting NUMA distance for different NUMA nodes */
84118154b7STao Xu     bool have_numa_distance;
857e721e7bSTao Xu 
86244b3f44STao Xu     /* Detect if HMAT support is enabled. */
87244b3f44STao Xu     bool hmat_enabled;
88244b3f44STao Xu 
897e721e7bSTao Xu     /* NUMA nodes information */
907e721e7bSTao Xu     NodeInfo nodes[MAX_NODES];
91*9b12dfa0SLiu Jingqi 
92*9b12dfa0SLiu Jingqi     /* NUMA nodes HMAT Locality Latency and Bandwidth Information */
93*9b12dfa0SLiu Jingqi     HMAT_LB_Info *hmat_lb[HMAT_LB_LEVELS][HMAT_LB_TYPES];
94aa570207STao Xu };
95aa570207STao Xu typedef struct NumaState NumaState;
96aa570207STao Xu 
9752924deaSMarkus Armbruster void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp);
98ea089eebSIgor Mammedov void parse_numa_opts(MachineState *ms);
99*9b12dfa0SLiu Jingqi void parse_numa_hmat_lb(NumaState *numa_state, NumaHmatLBOptions *node,
100*9b12dfa0SLiu Jingqi                         Error **errp);
1017a3099fcSIgor Mammedov void numa_complete_configuration(MachineState *ms);
102aa570207STao Xu void query_numa_node_mem(NumaNodeMem node_mem[], MachineState *ms);
103e35704baSEduardo Habkost extern QemuOptsList qemu_numa_opts;
1043bfe5716SLaurent Vivier void numa_legacy_auto_assign_ram(MachineClass *mc, NodeInfo *nodes,
1053bfe5716SLaurent Vivier                                  int nb_nodes, ram_addr_t size);
1063bfe5716SLaurent Vivier void numa_default_auto_assign_ram(MachineClass *mc, NodeInfo *nodes,
1073bfe5716SLaurent Vivier                                   int nb_nodes, ram_addr_t size);
108a44432b4SMarkus Armbruster void numa_cpu_pre_plug(const struct CPUArchId *slot, DeviceState *dev,
109a44432b4SMarkus Armbruster                        Error **errp);
110a44432b4SMarkus Armbruster 
111e35704baSEduardo Habkost #endif
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