1e35704baSEduardo Habkost #ifndef SYSEMU_NUMA_H 2e35704baSEduardo Habkost #define SYSEMU_NUMA_H 3e35704baSEduardo Habkost 4e35704baSEduardo Habkost #include "qemu/bitmap.h" 5a44432b4SMarkus Armbruster #include "qapi/qapi-types-machine.h" 6a44432b4SMarkus Armbruster #include "exec/cpu-common.h" 7a44432b4SMarkus Armbruster 8a44432b4SMarkus Armbruster struct CPUArchId; 9e35704baSEduardo Habkost 10b58c5c2dSMarkus Armbruster #define MAX_NODES 128 11b58c5c2dSMarkus Armbruster #define NUMA_NODE_UNASSIGNED MAX_NODES 12b58c5c2dSMarkus Armbruster #define NUMA_DISTANCE_MIN 10 13b58c5c2dSMarkus Armbruster #define NUMA_DISTANCE_DEFAULT 20 14b58c5c2dSMarkus Armbruster #define NUMA_DISTANCE_MAX 254 15b58c5c2dSMarkus Armbruster #define NUMA_DISTANCE_UNREACHABLE 255 16b58c5c2dSMarkus Armbruster 179b12dfa0SLiu Jingqi /* the value of AcpiHmatLBInfo flags */ 189b12dfa0SLiu Jingqi enum { 199b12dfa0SLiu Jingqi HMAT_LB_MEM_MEMORY = 0, 209b12dfa0SLiu Jingqi HMAT_LB_MEM_CACHE_1ST_LEVEL = 1, 219b12dfa0SLiu Jingqi HMAT_LB_MEM_CACHE_2ND_LEVEL = 2, 229b12dfa0SLiu Jingqi HMAT_LB_MEM_CACHE_3RD_LEVEL = 3, 239b12dfa0SLiu Jingqi HMAT_LB_LEVELS /* must be the last entry */ 249b12dfa0SLiu Jingqi }; 259b12dfa0SLiu Jingqi 269b12dfa0SLiu Jingqi /* the value of AcpiHmatLBInfo data type */ 279b12dfa0SLiu Jingqi enum { 289b12dfa0SLiu Jingqi HMAT_LB_DATA_ACCESS_LATENCY = 0, 299b12dfa0SLiu Jingqi HMAT_LB_DATA_READ_LATENCY = 1, 309b12dfa0SLiu Jingqi HMAT_LB_DATA_WRITE_LATENCY = 2, 319b12dfa0SLiu Jingqi HMAT_LB_DATA_ACCESS_BANDWIDTH = 3, 329b12dfa0SLiu Jingqi HMAT_LB_DATA_READ_BANDWIDTH = 4, 339b12dfa0SLiu Jingqi HMAT_LB_DATA_WRITE_BANDWIDTH = 5, 349b12dfa0SLiu Jingqi HMAT_LB_TYPES /* must be the last entry */ 359b12dfa0SLiu Jingqi }; 369b12dfa0SLiu Jingqi 379b12dfa0SLiu Jingqi #define UINT16_BITS 16 389b12dfa0SLiu Jingqi 39aec90730SEric Blake struct NodeInfo { 40e35704baSEduardo Habkost uint64_t node_mem; 41e35704baSEduardo Habkost struct HostMemoryBackend *node_memdev; 42e35704baSEduardo Habkost bool present; 43244b3f44STao Xu bool has_cpu; 44*0a5b5acdSAnkit Agrawal bool has_gi; 459b12dfa0SLiu Jingqi uint8_t lb_info_provided; 46244b3f44STao Xu uint16_t initiator; 470f203430SHe Chen uint8_t distance[MAX_NODES]; 483bfe5716SLaurent Vivier }; 49fa9ea81dSBharata B Rao 5031959e82SVadim Galitsyn struct NumaNodeMem { 5131959e82SVadim Galitsyn uint64_t node_mem; 5231959e82SVadim Galitsyn uint64_t node_plugged_mem; 5331959e82SVadim Galitsyn }; 5431959e82SVadim Galitsyn 559b12dfa0SLiu Jingqi struct HMAT_LB_Data { 569b12dfa0SLiu Jingqi uint8_t initiator; 579b12dfa0SLiu Jingqi uint8_t target; 589b12dfa0SLiu Jingqi uint64_t data; 599b12dfa0SLiu Jingqi }; 609b12dfa0SLiu Jingqi typedef struct HMAT_LB_Data HMAT_LB_Data; 619b12dfa0SLiu Jingqi 629b12dfa0SLiu Jingqi struct HMAT_LB_Info { 639b12dfa0SLiu Jingqi /* Indicates it's memory or the specified level memory side cache. */ 649b12dfa0SLiu Jingqi uint8_t hierarchy; 659b12dfa0SLiu Jingqi 669b12dfa0SLiu Jingqi /* Present the type of data, access/read/write latency or bandwidth. */ 679b12dfa0SLiu Jingqi uint8_t data_type; 689b12dfa0SLiu Jingqi 699b12dfa0SLiu Jingqi /* The range bitmap of bandwidth for calculating common base */ 709b12dfa0SLiu Jingqi uint64_t range_bitmap; 719b12dfa0SLiu Jingqi 729b12dfa0SLiu Jingqi /* The common base unit for latencies or bandwidths */ 739b12dfa0SLiu Jingqi uint64_t base; 749b12dfa0SLiu Jingqi 759b12dfa0SLiu Jingqi /* Array to store the latencies or bandwidths */ 769b12dfa0SLiu Jingqi GArray *list; 779b12dfa0SLiu Jingqi }; 789b12dfa0SLiu Jingqi typedef struct HMAT_LB_Info HMAT_LB_Info; 799b12dfa0SLiu Jingqi 80aa570207STao Xu struct NumaState { 81aa570207STao Xu /* Number of NUMA nodes */ 82aa570207STao Xu int num_nodes; 83aa570207STao Xu 84118154b7STao Xu /* Allow setting NUMA distance for different NUMA nodes */ 85118154b7STao Xu bool have_numa_distance; 867e721e7bSTao Xu 87244b3f44STao Xu /* Detect if HMAT support is enabled. */ 88244b3f44STao Xu bool hmat_enabled; 89244b3f44STao Xu 907e721e7bSTao Xu /* NUMA nodes information */ 917e721e7bSTao Xu NodeInfo nodes[MAX_NODES]; 929b12dfa0SLiu Jingqi 939b12dfa0SLiu Jingqi /* NUMA nodes HMAT Locality Latency and Bandwidth Information */ 949b12dfa0SLiu Jingqi HMAT_LB_Info *hmat_lb[HMAT_LB_LEVELS][HMAT_LB_TYPES]; 95c412a48dSLiu Jingqi 96c412a48dSLiu Jingqi /* Memory Side Cache Information Structure */ 97c412a48dSLiu Jingqi NumaHmatCacheOptions *hmat_cache[MAX_NODES][HMAT_LB_LEVELS]; 98aa570207STao Xu }; 99aa570207STao Xu typedef struct NumaState NumaState; 100aa570207STao Xu 10152924deaSMarkus Armbruster void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp); 102ea089eebSIgor Mammedov void parse_numa_opts(MachineState *ms); 1039b12dfa0SLiu Jingqi void parse_numa_hmat_lb(NumaState *numa_state, NumaHmatLBOptions *node, 1049b12dfa0SLiu Jingqi Error **errp); 105c412a48dSLiu Jingqi void parse_numa_hmat_cache(MachineState *ms, NumaHmatCacheOptions *node, 106c412a48dSLiu Jingqi Error **errp); 1077a3099fcSIgor Mammedov void numa_complete_configuration(MachineState *ms); 108aa570207STao Xu void query_numa_node_mem(NumaNodeMem node_mem[], MachineState *ms); 109e35704baSEduardo Habkost extern QemuOptsList qemu_numa_opts; 110a44432b4SMarkus Armbruster void numa_cpu_pre_plug(const struct CPUArchId *slot, DeviceState *dev, 111a44432b4SMarkus Armbruster Error **errp); 1126b61c2c5SIgor Mammedov bool numa_uses_legacy_mem(void); 113a44432b4SMarkus Armbruster 114e35704baSEduardo Habkost #endif 115