1f3eb7557SPeter Maydell /* 2f3eb7557SPeter Maydell * Luminary Micro Stellaris General Purpose Timer Module 3f3eb7557SPeter Maydell * 4f3eb7557SPeter Maydell * Copyright (c) 2006 CodeSourcery. 5f3eb7557SPeter Maydell * Written by Paul Brook 6f3eb7557SPeter Maydell * 7f3eb7557SPeter Maydell * This code is licensed under the GPL. 8f3eb7557SPeter Maydell */ 9f3eb7557SPeter Maydell 10f3eb7557SPeter Maydell #ifndef HW_TIMER_STELLARIS_GPTM_H 11f3eb7557SPeter Maydell #define HW_TIMER_STELLARIS_GPTM_H 12f3eb7557SPeter Maydell 13f3eb7557SPeter Maydell #include "qom/object.h" 14f3eb7557SPeter Maydell #include "hw/sysbus.h" 15f3eb7557SPeter Maydell #include "hw/irq.h" 16*d18fdd69SPeter Maydell #include "hw/clock.h" 17f3eb7557SPeter Maydell 18f3eb7557SPeter Maydell #define TYPE_STELLARIS_GPTM "stellaris-gptm" 19f3eb7557SPeter Maydell OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM) 20f3eb7557SPeter Maydell 21f3eb7557SPeter Maydell /* 22f3eb7557SPeter Maydell * QEMU interface: 23f3eb7557SPeter Maydell * + sysbus MMIO region 0: register bank 24f3eb7557SPeter Maydell * + sysbus IRQ 0: timer interrupt 25f3eb7557SPeter Maydell * + unnamed GPIO output 0: trigger output for the ADC 26*d18fdd69SPeter Maydell * + Clock input "clk": the 32-bit countdown timer runs at this speed 27f3eb7557SPeter Maydell */ 28f3eb7557SPeter Maydell struct gptm_state { 29f3eb7557SPeter Maydell SysBusDevice parent_obj; 30f3eb7557SPeter Maydell 31f3eb7557SPeter Maydell MemoryRegion iomem; 32f3eb7557SPeter Maydell uint32_t config; 33f3eb7557SPeter Maydell uint32_t mode[2]; 34f3eb7557SPeter Maydell uint32_t control; 35f3eb7557SPeter Maydell uint32_t state; 36f3eb7557SPeter Maydell uint32_t mask; 37f3eb7557SPeter Maydell uint32_t load[2]; 38f3eb7557SPeter Maydell uint32_t match[2]; 39f3eb7557SPeter Maydell uint32_t prescale[2]; 40f3eb7557SPeter Maydell uint32_t match_prescale[2]; 41f3eb7557SPeter Maydell uint32_t rtc; 42f3eb7557SPeter Maydell int64_t tick[2]; 43f3eb7557SPeter Maydell struct gptm_state *opaque[2]; 44f3eb7557SPeter Maydell QEMUTimer *timer[2]; 45f3eb7557SPeter Maydell /* The timers have an alternate output used to trigger the ADC. */ 46f3eb7557SPeter Maydell qemu_irq trigger; 47f3eb7557SPeter Maydell qemu_irq irq; 48*d18fdd69SPeter Maydell Clock *clk; 49f3eb7557SPeter Maydell }; 50f3eb7557SPeter Maydell 51f3eb7557SPeter Maydell #endif 52