1*7adca78eSYoshinori Sato /* 2*7adca78eSYoshinori Sato * Renesas 8bit timer Object 3*7adca78eSYoshinori Sato * 4*7adca78eSYoshinori Sato * Copyright (c) 2018 Yoshinori Sato 5*7adca78eSYoshinori Sato * 6*7adca78eSYoshinori Sato * SPDX-License-Identifier: GPL-2.0-or-later 7*7adca78eSYoshinori Sato */ 8*7adca78eSYoshinori Sato 9*7adca78eSYoshinori Sato #ifndef HW_TIMER_RENESAS_TMR_H 10*7adca78eSYoshinori Sato #define HW_TIMER_RENESAS_TMR_H 11*7adca78eSYoshinori Sato 12*7adca78eSYoshinori Sato #include "qemu/timer.h" 13*7adca78eSYoshinori Sato #include "hw/sysbus.h" 14*7adca78eSYoshinori Sato 15*7adca78eSYoshinori Sato #define TYPE_RENESAS_TMR "renesas-tmr" 16*7adca78eSYoshinori Sato #define RTMR(obj) OBJECT_CHECK(RTMRState, (obj), TYPE_RENESAS_TMR) 17*7adca78eSYoshinori Sato 18*7adca78eSYoshinori Sato enum timer_event { 19*7adca78eSYoshinori Sato cmia = 0, 20*7adca78eSYoshinori Sato cmib = 1, 21*7adca78eSYoshinori Sato ovi = 2, 22*7adca78eSYoshinori Sato none = 3, 23*7adca78eSYoshinori Sato TMR_NR_EVENTS = 4 24*7adca78eSYoshinori Sato }; 25*7adca78eSYoshinori Sato 26*7adca78eSYoshinori Sato enum { 27*7adca78eSYoshinori Sato TMR_CH = 2, 28*7adca78eSYoshinori Sato TMR_NR_IRQ = 3 * TMR_CH 29*7adca78eSYoshinori Sato }; 30*7adca78eSYoshinori Sato 31*7adca78eSYoshinori Sato typedef struct RTMRState { 32*7adca78eSYoshinori Sato /*< private >*/ 33*7adca78eSYoshinori Sato SysBusDevice parent_obj; 34*7adca78eSYoshinori Sato /*< public >*/ 35*7adca78eSYoshinori Sato 36*7adca78eSYoshinori Sato uint64_t input_freq; 37*7adca78eSYoshinori Sato MemoryRegion memory; 38*7adca78eSYoshinori Sato 39*7adca78eSYoshinori Sato int64_t tick; 40*7adca78eSYoshinori Sato uint8_t tcnt[TMR_CH]; 41*7adca78eSYoshinori Sato uint8_t tcora[TMR_CH]; 42*7adca78eSYoshinori Sato uint8_t tcorb[TMR_CH]; 43*7adca78eSYoshinori Sato uint8_t tcr[TMR_CH]; 44*7adca78eSYoshinori Sato uint8_t tccr[TMR_CH]; 45*7adca78eSYoshinori Sato uint8_t tcor[TMR_CH]; 46*7adca78eSYoshinori Sato uint8_t tcsr[TMR_CH]; 47*7adca78eSYoshinori Sato int64_t div_round[TMR_CH]; 48*7adca78eSYoshinori Sato uint8_t next[TMR_CH]; 49*7adca78eSYoshinori Sato qemu_irq cmia[TMR_CH]; 50*7adca78eSYoshinori Sato qemu_irq cmib[TMR_CH]; 51*7adca78eSYoshinori Sato qemu_irq ovi[TMR_CH]; 52*7adca78eSYoshinori Sato QEMUTimer timer[TMR_CH]; 53*7adca78eSYoshinori Sato } RTMRState; 54*7adca78eSYoshinori Sato 55*7adca78eSYoshinori Sato #endif 56