xref: /openbmc/qemu/include/hw/timer/cadence_ttc.h (revision 401d46789410e88e9e90d76a11f46e8e9f358d55)
1*09fc50cdSEdgar E. Iglesias /*
2*09fc50cdSEdgar E. Iglesias  * Xilinx Zynq cadence TTC model
3*09fc50cdSEdgar E. Iglesias  *
4*09fc50cdSEdgar E. Iglesias  * Copyright (c) 2011 Xilinx Inc.
5*09fc50cdSEdgar E. Iglesias  * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
6*09fc50cdSEdgar E. Iglesias  * Copyright (c) 2012 PetaLogix Pty Ltd.
7*09fc50cdSEdgar E. Iglesias  * Written By Haibing Ma
8*09fc50cdSEdgar E. Iglesias  *            M. Habib
9*09fc50cdSEdgar E. Iglesias  *
10*09fc50cdSEdgar E. Iglesias  * This program is free software; you can redistribute it and/or
11*09fc50cdSEdgar E. Iglesias  * modify it under the terms of the GNU General Public License
12*09fc50cdSEdgar E. Iglesias  * as published by the Free Software Foundation; either version
13*09fc50cdSEdgar E. Iglesias  * 2 of the License, or (at your option) any later version.
14*09fc50cdSEdgar E. Iglesias  *
15*09fc50cdSEdgar E. Iglesias  * You should have received a copy of the GNU General Public License along
16*09fc50cdSEdgar E. Iglesias  * with this program; if not, see <http://www.gnu.org/licenses/>.
17*09fc50cdSEdgar E. Iglesias  */
18*09fc50cdSEdgar E. Iglesias #ifndef HW_TIMER_CADENCE_TTC_H
19*09fc50cdSEdgar E. Iglesias #define HW_TIMER_CADENCE_TTC_H
20*09fc50cdSEdgar E. Iglesias 
21*09fc50cdSEdgar E. Iglesias #include "hw/sysbus.h"
22*09fc50cdSEdgar E. Iglesias #include "qemu/timer.h"
23*09fc50cdSEdgar E. Iglesias 
24*09fc50cdSEdgar E. Iglesias typedef struct {
25*09fc50cdSEdgar E. Iglesias     QEMUTimer *timer;
26*09fc50cdSEdgar E. Iglesias     int freq;
27*09fc50cdSEdgar E. Iglesias 
28*09fc50cdSEdgar E. Iglesias     uint32_t reg_clock;
29*09fc50cdSEdgar E. Iglesias     uint32_t reg_count;
30*09fc50cdSEdgar E. Iglesias     uint32_t reg_value;
31*09fc50cdSEdgar E. Iglesias     uint16_t reg_interval;
32*09fc50cdSEdgar E. Iglesias     uint16_t reg_match[3];
33*09fc50cdSEdgar E. Iglesias     uint32_t reg_intr;
34*09fc50cdSEdgar E. Iglesias     uint32_t reg_intr_en;
35*09fc50cdSEdgar E. Iglesias     uint32_t reg_event_ctrl;
36*09fc50cdSEdgar E. Iglesias     uint32_t reg_event;
37*09fc50cdSEdgar E. Iglesias 
38*09fc50cdSEdgar E. Iglesias     uint64_t cpu_time;
39*09fc50cdSEdgar E. Iglesias     unsigned int cpu_time_valid;
40*09fc50cdSEdgar E. Iglesias 
41*09fc50cdSEdgar E. Iglesias     qemu_irq irq;
42*09fc50cdSEdgar E. Iglesias } CadenceTimerState;
43*09fc50cdSEdgar E. Iglesias 
44*09fc50cdSEdgar E. Iglesias #define TYPE_CADENCE_TTC "cadence_ttc"
45*09fc50cdSEdgar E. Iglesias OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
46*09fc50cdSEdgar E. Iglesias 
47*09fc50cdSEdgar E. Iglesias struct CadenceTTCState {
48*09fc50cdSEdgar E. Iglesias     SysBusDevice parent_obj;
49*09fc50cdSEdgar E. Iglesias 
50*09fc50cdSEdgar E. Iglesias     MemoryRegion iomem;
51*09fc50cdSEdgar E. Iglesias     CadenceTimerState timer[3];
52*09fc50cdSEdgar E. Iglesias };
53*09fc50cdSEdgar E. Iglesias 
54*09fc50cdSEdgar E. Iglesias #endif
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