10694dabeSBin Meng /* 20694dabeSBin Meng * QEMU model of the SiFive SPI Controller 30694dabeSBin Meng * 40694dabeSBin Meng * Copyright (c) 2021 Wind River Systems, Inc. 50694dabeSBin Meng * 60694dabeSBin Meng * Author: 70694dabeSBin Meng * Bin Meng <bin.meng@windriver.com> 80694dabeSBin Meng * 90694dabeSBin Meng * This program is free software; you can redistribute it and/or modify it 100694dabeSBin Meng * under the terms and conditions of the GNU General Public License, 110694dabeSBin Meng * version 2 or later, as published by the Free Software Foundation. 120694dabeSBin Meng * 130694dabeSBin Meng * This program is distributed in the hope it will be useful, but WITHOUT 140694dabeSBin Meng * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 150694dabeSBin Meng * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 160694dabeSBin Meng * more details. 170694dabeSBin Meng * 180694dabeSBin Meng * You should have received a copy of the GNU General Public License along with 190694dabeSBin Meng * this program. If not, see <http://www.gnu.org/licenses/>. 200694dabeSBin Meng */ 210694dabeSBin Meng 220694dabeSBin Meng #ifndef HW_SIFIVE_SPI_H 230694dabeSBin Meng #define HW_SIFIVE_SPI_H 240694dabeSBin Meng 25*7a5951f6SMarkus Armbruster #include "qemu/fifo8.h" 26*7a5951f6SMarkus Armbruster #include "hw/sysbus.h" 27*7a5951f6SMarkus Armbruster 280694dabeSBin Meng #define SIFIVE_SPI_REG_NUM (0x78 / 4) 290694dabeSBin Meng 300694dabeSBin Meng #define TYPE_SIFIVE_SPI "sifive.spi" 310694dabeSBin Meng #define SIFIVE_SPI(obj) OBJECT_CHECK(SiFiveSPIState, (obj), TYPE_SIFIVE_SPI) 320694dabeSBin Meng 330694dabeSBin Meng typedef struct SiFiveSPIState { 340694dabeSBin Meng SysBusDevice parent_obj; 350694dabeSBin Meng 360694dabeSBin Meng MemoryRegion mmio; 370694dabeSBin Meng qemu_irq irq; 380694dabeSBin Meng 390694dabeSBin Meng uint32_t num_cs; 400694dabeSBin Meng qemu_irq *cs_lines; 410694dabeSBin Meng 420694dabeSBin Meng SSIBus *spi; 430694dabeSBin Meng 440694dabeSBin Meng Fifo8 tx_fifo; 450694dabeSBin Meng Fifo8 rx_fifo; 460694dabeSBin Meng 470694dabeSBin Meng uint32_t regs[SIFIVE_SPI_REG_NUM]; 480694dabeSBin Meng } SiFiveSPIState; 490694dabeSBin Meng 500694dabeSBin Meng #endif /* HW_SIFIVE_SPI_H */ 51