1*b821242cSHavard Skinnemoen /* 2*b821242cSHavard Skinnemoen * Nuvoton NPCM7xx Flash Interface Unit (FIU) 3*b821242cSHavard Skinnemoen * 4*b821242cSHavard Skinnemoen * Copyright 2020 Google LLC 5*b821242cSHavard Skinnemoen * 6*b821242cSHavard Skinnemoen * This program is free software; you can redistribute it and/or modify it 7*b821242cSHavard Skinnemoen * under the terms of the GNU General Public License as published by the 8*b821242cSHavard Skinnemoen * Free Software Foundation; either version 2 of the License, or 9*b821242cSHavard Skinnemoen * (at your option) any later version. 10*b821242cSHavard Skinnemoen * 11*b821242cSHavard Skinnemoen * This program is distributed in the hope that it will be useful, but WITHOUT 12*b821242cSHavard Skinnemoen * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13*b821242cSHavard Skinnemoen * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14*b821242cSHavard Skinnemoen * for more details. 15*b821242cSHavard Skinnemoen */ 16*b821242cSHavard Skinnemoen #ifndef NPCM7XX_FIU_H 17*b821242cSHavard Skinnemoen #define NPCM7XX_FIU_H 18*b821242cSHavard Skinnemoen 19*b821242cSHavard Skinnemoen #include "hw/ssi/ssi.h" 20*b821242cSHavard Skinnemoen #include "hw/sysbus.h" 21*b821242cSHavard Skinnemoen 22*b821242cSHavard Skinnemoen /* 23*b821242cSHavard Skinnemoen * Number of registers in our device state structure. Don't change this without 24*b821242cSHavard Skinnemoen * incrementing the version_id in the vmstate. 25*b821242cSHavard Skinnemoen */ 26*b821242cSHavard Skinnemoen #define NPCM7XX_FIU_NR_REGS (0x7c / sizeof(uint32_t)) 27*b821242cSHavard Skinnemoen 28*b821242cSHavard Skinnemoen typedef struct NPCM7xxFIUState NPCM7xxFIUState; 29*b821242cSHavard Skinnemoen 30*b821242cSHavard Skinnemoen /** 31*b821242cSHavard Skinnemoen * struct NPCM7xxFIUFlash - Per-chipselect flash controller state. 32*b821242cSHavard Skinnemoen * @direct_access: Memory region for direct flash access. 33*b821242cSHavard Skinnemoen * @fiu: Pointer to flash controller shared state. 34*b821242cSHavard Skinnemoen */ 35*b821242cSHavard Skinnemoen typedef struct NPCM7xxFIUFlash { 36*b821242cSHavard Skinnemoen MemoryRegion direct_access; 37*b821242cSHavard Skinnemoen NPCM7xxFIUState *fiu; 38*b821242cSHavard Skinnemoen } NPCM7xxFIUFlash; 39*b821242cSHavard Skinnemoen 40*b821242cSHavard Skinnemoen /** 41*b821242cSHavard Skinnemoen * NPCM7xxFIUState - Device state for one Flash Interface Unit. 42*b821242cSHavard Skinnemoen * @parent: System bus device. 43*b821242cSHavard Skinnemoen * @mmio: Memory region for register access. 44*b821242cSHavard Skinnemoen * @cs_count: Number of flash chips that may be connected to this module. 45*b821242cSHavard Skinnemoen * @active_cs: Currently active chip select, or -1 if no chip is selected. 46*b821242cSHavard Skinnemoen * @cs_lines: GPIO lines that may be wired to flash chips. 47*b821242cSHavard Skinnemoen * @flash: Array of @cs_count per-flash-chip state objects. 48*b821242cSHavard Skinnemoen * @spi: The SPI bus mastered by this controller. 49*b821242cSHavard Skinnemoen * @regs: Register contents. 50*b821242cSHavard Skinnemoen * 51*b821242cSHavard Skinnemoen * Each FIU has a shared bank of registers, and controls up to four chip 52*b821242cSHavard Skinnemoen * selects. Each chip select has a dedicated memory region which may be used to 53*b821242cSHavard Skinnemoen * read and write the flash connected to that chip select as if it were memory. 54*b821242cSHavard Skinnemoen */ 55*b821242cSHavard Skinnemoen struct NPCM7xxFIUState { 56*b821242cSHavard Skinnemoen SysBusDevice parent; 57*b821242cSHavard Skinnemoen 58*b821242cSHavard Skinnemoen MemoryRegion mmio; 59*b821242cSHavard Skinnemoen 60*b821242cSHavard Skinnemoen int32_t cs_count; 61*b821242cSHavard Skinnemoen int32_t active_cs; 62*b821242cSHavard Skinnemoen qemu_irq *cs_lines; 63*b821242cSHavard Skinnemoen NPCM7xxFIUFlash *flash; 64*b821242cSHavard Skinnemoen 65*b821242cSHavard Skinnemoen SSIBus *spi; 66*b821242cSHavard Skinnemoen 67*b821242cSHavard Skinnemoen uint32_t regs[NPCM7XX_FIU_NR_REGS]; 68*b821242cSHavard Skinnemoen }; 69*b821242cSHavard Skinnemoen 70*b821242cSHavard Skinnemoen #define TYPE_NPCM7XX_FIU "npcm7xx-fiu" 71*b821242cSHavard Skinnemoen #define NPCM7XX_FIU(obj) OBJECT_CHECK(NPCM7xxFIUState, (obj), TYPE_NPCM7XX_FIU) 72*b821242cSHavard Skinnemoen 73*b821242cSHavard Skinnemoen #endif /* NPCM7XX_FIU_H */ 74