1fff123b8SPhilippe Mathieu-Daudé /* 2fff123b8SPhilippe Mathieu-Daudé * QEMU PIIX South Bridge Emulation 3fff123b8SPhilippe Mathieu-Daudé * 4fff123b8SPhilippe Mathieu-Daudé * Copyright (c) 2006 Fabrice Bellard 5e29f2379SPhilippe Mathieu-Daudé * Copyright (c) 2018 Hervé Poussineau 6fff123b8SPhilippe Mathieu-Daudé * 7fff123b8SPhilippe Mathieu-Daudé * This work is licensed under the terms of the GNU GPL, version 2 or later. 8fff123b8SPhilippe Mathieu-Daudé * See the COPYING file in the top-level directory. 9fff123b8SPhilippe Mathieu-Daudé * 10fff123b8SPhilippe Mathieu-Daudé */ 11fff123b8SPhilippe Mathieu-Daudé 12fff123b8SPhilippe Mathieu-Daudé #ifndef HW_SOUTHBRIDGE_PIIX_H 13fff123b8SPhilippe Mathieu-Daudé #define HW_SOUTHBRIDGE_PIIX_H 14fff123b8SPhilippe Mathieu-Daudé 15edf5ca5dSMarkus Armbruster #include "hw/pci/pci_device.h" 160a15cf08SBernhard Beschow #include "hw/acpi/piix4.h" 17e47e5a5bSBernhard Beschow #include "hw/ide/pci.h" 18f0bc6bf7SBernhard Beschow #include "hw/rtc/mc146818rtc.h" 19*27af7e00SGuenter Roeck #include "hw/usb/hcd-uhci-pci.h" 20fff123b8SPhilippe Mathieu-Daudé 214b19de14SPhilippe Mathieu-Daudé /* PIRQRC[A:D]: PIRQx Route Control Registers */ 224b19de14SPhilippe Mathieu-Daudé #define PIIX_PIRQCA 0x60 234b19de14SPhilippe Mathieu-Daudé #define PIIX_PIRQCB 0x61 244b19de14SPhilippe Mathieu-Daudé #define PIIX_PIRQCC 0x62 254b19de14SPhilippe Mathieu-Daudé #define PIIX_PIRQCD 0x63 264b19de14SPhilippe Mathieu-Daudé 270063454aSPhilippe Mathieu-Daudé /* 280063454aSPhilippe Mathieu-Daudé * Reset Control Register: PCI-accessible ISA-Compatible Register at address 290063454aSPhilippe Mathieu-Daudé * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). 300063454aSPhilippe Mathieu-Daudé */ 310063454aSPhilippe Mathieu-Daudé #define PIIX_RCR_IOPORT 0xcf9 320063454aSPhilippe Mathieu-Daudé 3314a026ddSPhilippe Mathieu-Daudé #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ 3414a026ddSPhilippe Mathieu-Daudé 35db1015e9SEduardo Habkost struct PIIXState { 3614a026ddSPhilippe Mathieu-Daudé PCIDevice dev; 3714a026ddSPhilippe Mathieu-Daudé 3814a026ddSPhilippe Mathieu-Daudé /* 3914a026ddSPhilippe Mathieu-Daudé * bitmap to track pic levels. 4014a026ddSPhilippe Mathieu-Daudé * The pic level is the logical OR of all the PCI irqs mapped to it 4114a026ddSPhilippe Mathieu-Daudé * So one PIC level is tracked by PIIX_NUM_PIRQS bits. 4214a026ddSPhilippe Mathieu-Daudé * 4314a026ddSPhilippe Mathieu-Daudé * PIRQ is mapped to PIC pins, we track it by 4432f29b26SBernhard Beschow * PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with 4514a026ddSPhilippe Mathieu-Daudé * pic_irq * PIIX_NUM_PIRQS + pirq 4614a026ddSPhilippe Mathieu-Daudé */ 4732f29b26SBernhard Beschow #if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64 4814a026ddSPhilippe Mathieu-Daudé #error "unable to encode pic state in 64bit in pic_levels." 4914a026ddSPhilippe Mathieu-Daudé #endif 5014a026ddSPhilippe Mathieu-Daudé uint64_t pic_levels; 5114a026ddSPhilippe Mathieu-Daudé 5274bdcfb4SBernhard Beschow qemu_irq cpu_intr; 5340f70623SBernhard Beschow qemu_irq isa_irqs_in[ISA_NUM_IRQS]; 5414a026ddSPhilippe Mathieu-Daudé 5514a026ddSPhilippe Mathieu-Daudé /* This member isn't used. Just for save/load compatibility */ 5614a026ddSPhilippe Mathieu-Daudé int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; 5714a026ddSPhilippe Mathieu-Daudé 58f0bc6bf7SBernhard Beschow MC146818RtcState rtc; 59e47e5a5bSBernhard Beschow PCIIDEState ide; 60*27af7e00SGuenter Roeck UHCIPCIState uhci; 610a15cf08SBernhard Beschow PIIX4PMState pm; 620a15cf08SBernhard Beschow 630a15cf08SBernhard Beschow uint32_t smb_io_base; 64f0bc6bf7SBernhard Beschow 6514a026ddSPhilippe Mathieu-Daudé /* Reset Control Register contents */ 6614a026ddSPhilippe Mathieu-Daudé uint8_t rcr; 6714a026ddSPhilippe Mathieu-Daudé 6814a026ddSPhilippe Mathieu-Daudé /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ 6914a026ddSPhilippe Mathieu-Daudé MemoryRegion rcr_mem; 706fe4464cSBernhard Beschow 710a15cf08SBernhard Beschow bool has_acpi; 722d7630f5SBernhard Beschow bool has_pic; 73ac433035SBernhard Beschow bool has_pit; 746fe4464cSBernhard Beschow bool has_usb; 750a15cf08SBernhard Beschow bool smm_enabled; 76db1015e9SEduardo Habkost }; 7714a026ddSPhilippe Mathieu-Daudé 789769cfc3SBernhard Beschow #define TYPE_PIIX_PCI_DEVICE "pci-piix" 799769cfc3SBernhard Beschow OBJECT_DECLARE_SIMPLE_TYPE(PIIXState, PIIX_PCI_DEVICE) 80fe47ad3aSEduardo Habkost 813963e139SBernhard Beschow #define TYPE_PIIX3_DEVICE "PIIX3" 823963e139SBernhard Beschow #define TYPE_PIIX4_PCI_DEVICE "piix4-isa" 833963e139SBernhard Beschow 84fff123b8SPhilippe Mathieu-Daudé #endif 85