xref: /openbmc/qemu/include/hw/s390x/css.h (revision 99577c492fb2916165ed9bc215f058877f0a4106)
1bd3f16acSPaolo Bonzini /*
2bd3f16acSPaolo Bonzini  * Channel subsystem structures and definitions.
3bd3f16acSPaolo Bonzini  *
4bd3f16acSPaolo Bonzini  * Copyright 2012 IBM Corp.
5bd3f16acSPaolo Bonzini  * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
6bd3f16acSPaolo Bonzini  *
7bd3f16acSPaolo Bonzini  * This work is licensed under the terms of the GNU GPL, version 2 or (at
8bd3f16acSPaolo Bonzini  * your option) any later version. See the COPYING file in the top-level
9bd3f16acSPaolo Bonzini  * directory.
10bd3f16acSPaolo Bonzini  */
11bd3f16acSPaolo Bonzini 
12bd3f16acSPaolo Bonzini #ifndef CSS_H
13bd3f16acSPaolo Bonzini #define CSS_H
14bd3f16acSPaolo Bonzini 
152283f4d6SFei Li #include "cpu.h"
16bd3f16acSPaolo Bonzini #include "hw/s390x/adapter.h"
17bd3f16acSPaolo Bonzini #include "hw/s390x/s390_flic.h"
18bd3f16acSPaolo Bonzini #include "hw/s390x/ioinst.h"
19f16bbb9bSDavid Hildenbrand #include "sysemu/kvm.h"
20bd3f16acSPaolo Bonzini 
21bd3f16acSPaolo Bonzini /* Channel subsystem constants. */
22cf249935SSascha Silbe #define MAX_DEVNO 65535
23bd3f16acSPaolo Bonzini #define MAX_SCHID 65535
24bd3f16acSPaolo Bonzini #define MAX_SSID 3
25882b3b97SCornelia Huck #define MAX_CSSID 255
26bd3f16acSPaolo Bonzini #define MAX_CHPID 255
27bd3f16acSPaolo Bonzini 
28dde522bbSFei Li #define MAX_ISC 7
29dde522bbSFei Li 
30bd3f16acSPaolo Bonzini #define MAX_CIWS 62
31bd3f16acSPaolo Bonzini 
32cf249935SSascha Silbe #define VIRTUAL_CSSID 0xfe
336c15e9bfSJing Liu #define VIRTIO_CCW_CHPID 0   /* used by convention */
34cf249935SSascha Silbe 
35bd3f16acSPaolo Bonzini typedef struct CIW {
36bd3f16acSPaolo Bonzini     uint8_t type;
37bd3f16acSPaolo Bonzini     uint8_t command;
38bd3f16acSPaolo Bonzini     uint16_t count;
39bd3f16acSPaolo Bonzini } QEMU_PACKED CIW;
40bd3f16acSPaolo Bonzini 
41bd3f16acSPaolo Bonzini typedef struct SenseId {
42bd3f16acSPaolo Bonzini     /* common part */
43bd3f16acSPaolo Bonzini     uint8_t reserved;        /* always 0x'FF' */
44bd3f16acSPaolo Bonzini     uint16_t cu_type;        /* control unit type */
45bd3f16acSPaolo Bonzini     uint8_t cu_model;        /* control unit model */
46bd3f16acSPaolo Bonzini     uint16_t dev_type;       /* device type */
47bd3f16acSPaolo Bonzini     uint8_t dev_model;       /* device model */
48bd3f16acSPaolo Bonzini     uint8_t unused;          /* padding byte */
49bd3f16acSPaolo Bonzini     /* extended part */
50bd3f16acSPaolo Bonzini     CIW ciw[MAX_CIWS];       /* variable # of CIWs */
51bd3f16acSPaolo Bonzini } QEMU_PACKED SenseId;
52bd3f16acSPaolo Bonzini 
53bd3f16acSPaolo Bonzini /* Channel measurements, from linux/drivers/s390/cio/cmf.c. */
54bd3f16acSPaolo Bonzini typedef struct CMB {
55bd3f16acSPaolo Bonzini     uint16_t ssch_rsch_count;
56bd3f16acSPaolo Bonzini     uint16_t sample_count;
57bd3f16acSPaolo Bonzini     uint32_t device_connect_time;
58bd3f16acSPaolo Bonzini     uint32_t function_pending_time;
59bd3f16acSPaolo Bonzini     uint32_t device_disconnect_time;
60bd3f16acSPaolo Bonzini     uint32_t control_unit_queuing_time;
61bd3f16acSPaolo Bonzini     uint32_t device_active_only_time;
62bd3f16acSPaolo Bonzini     uint32_t reserved[2];
63bd3f16acSPaolo Bonzini } QEMU_PACKED CMB;
64bd3f16acSPaolo Bonzini 
65bd3f16acSPaolo Bonzini typedef struct CMBE {
66bd3f16acSPaolo Bonzini     uint32_t ssch_rsch_count;
67bd3f16acSPaolo Bonzini     uint32_t sample_count;
68bd3f16acSPaolo Bonzini     uint32_t device_connect_time;
69bd3f16acSPaolo Bonzini     uint32_t function_pending_time;
70bd3f16acSPaolo Bonzini     uint32_t device_disconnect_time;
71bd3f16acSPaolo Bonzini     uint32_t control_unit_queuing_time;
72bd3f16acSPaolo Bonzini     uint32_t device_active_only_time;
73bd3f16acSPaolo Bonzini     uint32_t device_busy_time;
74bd3f16acSPaolo Bonzini     uint32_t initial_command_response_time;
75bd3f16acSPaolo Bonzini     uint32_t reserved[7];
76bd3f16acSPaolo Bonzini } QEMU_PACKED CMBE;
77bd3f16acSPaolo Bonzini 
7857065a70SHalil Pasic typedef enum CcwDataStreamOp {
7957065a70SHalil Pasic     CDS_OP_R = 0, /* read, false when used as is_write */
8057065a70SHalil Pasic     CDS_OP_W = 1, /* write, true when used as is_write */
8157065a70SHalil Pasic     CDS_OP_A = 2  /* advance, should not be used as is_write */
8257065a70SHalil Pasic } CcwDataStreamOp;
8357065a70SHalil Pasic 
8457065a70SHalil Pasic /* normal usage is via SuchchDev.cds instead of instantiating */
8557065a70SHalil Pasic typedef struct CcwDataStream {
8657065a70SHalil Pasic #define CDS_F_IDA   0x01
8757065a70SHalil Pasic #define CDS_F_MIDA  0x02
8857065a70SHalil Pasic #define CDS_F_I2K   0x04
8957065a70SHalil Pasic #define CDS_F_C64   0x08
9062a2554eSHalil Pasic #define CDS_F_FMT   0x10 /* CCW format-1 */
9157065a70SHalil Pasic #define CDS_F_STREAM_BROKEN  0x80
9257065a70SHalil Pasic     uint8_t flags;
9357065a70SHalil Pasic     uint8_t at_idaw;
9457065a70SHalil Pasic     uint16_t at_byte;
9557065a70SHalil Pasic     uint16_t count;
9657065a70SHalil Pasic     uint32_t cda_orig;
9757065a70SHalil Pasic     int (*op_handler)(struct CcwDataStream *cds, void *buff, int len,
9857065a70SHalil Pasic                       CcwDataStreamOp op);
9957065a70SHalil Pasic     hwaddr cda;
10057065a70SHalil Pasic } CcwDataStream;
10157065a70SHalil Pasic 
102e443ef9fSHalil Pasic /*
103e443ef9fSHalil Pasic  * IO instructions conclude according to this. Currently we have only
104e443ef9fSHalil Pasic  * cc codes. Valid values are 0, 1, 2, 3 and the generic semantic for
105e443ef9fSHalil Pasic  * IO instructions is described briefly. For more details consult the PoP.
106e443ef9fSHalil Pasic  */
107e443ef9fSHalil Pasic typedef enum IOInstEnding {
108e443ef9fSHalil Pasic     /* produced expected result */
109e443ef9fSHalil Pasic     IOINST_CC_EXPECTED = 0,
110e443ef9fSHalil Pasic     /* status conditions were present or produced alternate result */
111e443ef9fSHalil Pasic     IOINST_CC_STATUS_PRESENT = 1,
112e443ef9fSHalil Pasic     /* inst. ineffective because busy with previously initiated function */
113e443ef9fSHalil Pasic     IOINST_CC_BUSY = 2,
114e443ef9fSHalil Pasic     /* inst. ineffective because not operational */
115e443ef9fSHalil Pasic     IOINST_CC_NOT_OPERATIONAL = 3
116e443ef9fSHalil Pasic } IOInstEnding;
117e443ef9fSHalil Pasic 
118bd3f16acSPaolo Bonzini typedef struct SubchDev SubchDev;
119bd3f16acSPaolo Bonzini struct SubchDev {
120bd3f16acSPaolo Bonzini     /* channel-subsystem related things: */
121bd3f16acSPaolo Bonzini     uint8_t cssid;
122bd3f16acSPaolo Bonzini     uint8_t ssid;
123bd3f16acSPaolo Bonzini     uint16_t schid;
124bd3f16acSPaolo Bonzini     uint16_t devno;
125bd3f16acSPaolo Bonzini     SCHIB curr_status;
126bd3f16acSPaolo Bonzini     uint8_t sense_data[32];
127bd3f16acSPaolo Bonzini     hwaddr channel_prog;
128bd3f16acSPaolo Bonzini     CCW1 last_cmd;
129bd3f16acSPaolo Bonzini     bool last_cmd_valid;
130bd3f16acSPaolo Bonzini     bool ccw_fmt_1;
131bd3f16acSPaolo Bonzini     bool thinint_active;
132bd3f16acSPaolo Bonzini     uint8_t ccw_no_data_cnt;
133517ff12cSHalil Pasic     uint16_t migrated_schid; /* used for missmatch detection */
134ff443fe6SHalil Pasic     ORB orb;
13557065a70SHalil Pasic     CcwDataStream cds;
136bd3f16acSPaolo Bonzini     /* transport-provided data: */
137bd3f16acSPaolo Bonzini     int (*ccw_cb) (SubchDev *, CCW1);
138bd3f16acSPaolo Bonzini     void (*disable_cb)(SubchDev *);
13966dc50f7SHalil Pasic     IOInstEnding (*do_subchannel_work) (SubchDev *);
140bd3f16acSPaolo Bonzini     SenseId id;
141bd3f16acSPaolo Bonzini     void *driver_data;
142bd3f16acSPaolo Bonzini };
143bd3f16acSPaolo Bonzini 
14466dc50f7SHalil Pasic static inline void sch_gen_unit_exception(SubchDev *sch)
14566dc50f7SHalil Pasic {
14666dc50f7SHalil Pasic     sch->curr_status.scsw.ctrl &= ~SCSW_ACTL_START_PEND;
14766dc50f7SHalil Pasic     sch->curr_status.scsw.ctrl |= SCSW_STCTL_PRIMARY |
14866dc50f7SHalil Pasic                                   SCSW_STCTL_SECONDARY |
14966dc50f7SHalil Pasic                                   SCSW_STCTL_ALERT |
15066dc50f7SHalil Pasic                                   SCSW_STCTL_STATUS_PEND;
15166dc50f7SHalil Pasic     sch->curr_status.scsw.cpa = sch->channel_prog + 8;
15266dc50f7SHalil Pasic     sch->curr_status.scsw.dstat =  SCSW_DSTAT_UNIT_EXCEP;
15366dc50f7SHalil Pasic }
15466dc50f7SHalil Pasic 
155517ff12cSHalil Pasic extern const VMStateDescription vmstate_subch_dev;
156517ff12cSHalil Pasic 
1578f3cf012SXiao Feng Ren /*
1588f3cf012SXiao Feng Ren  * Identify a device within the channel subsystem.
1598f3cf012SXiao Feng Ren  * Note that this can be used to identify either the subchannel or
1608f3cf012SXiao Feng Ren  * the attached I/O device, as there's always one I/O device per
1618f3cf012SXiao Feng Ren  * subchannel.
1628f3cf012SXiao Feng Ren  */
1638f3cf012SXiao Feng Ren typedef struct CssDevId {
1648f3cf012SXiao Feng Ren     uint8_t cssid;
1658f3cf012SXiao Feng Ren     uint8_t ssid;
1668f3cf012SXiao Feng Ren     uint16_t devid;
1678f3cf012SXiao Feng Ren     bool valid;
1688f3cf012SXiao Feng Ren } CssDevId;
1698f3cf012SXiao Feng Ren 
1701b6b7d10SFam Zheng extern const PropertyInfo css_devid_propinfo;
1718f3cf012SXiao Feng Ren 
1728f3cf012SXiao Feng Ren #define DEFINE_PROP_CSS_DEV_ID(_n, _s, _f) \
1738f3cf012SXiao Feng Ren     DEFINE_PROP(_n, _s, _f, css_devid_propinfo, CssDevId)
1748f3cf012SXiao Feng Ren 
175bd3f16acSPaolo Bonzini typedef struct IndAddr {
176bd3f16acSPaolo Bonzini     hwaddr addr;
177bd3f16acSPaolo Bonzini     uint64_t map;
178bd3f16acSPaolo Bonzini     unsigned long refcnt;
179517ff12cSHalil Pasic     int32_t len;
180bd3f16acSPaolo Bonzini     QTAILQ_ENTRY(IndAddr) sibling;
181bd3f16acSPaolo Bonzini } IndAddr;
182bd3f16acSPaolo Bonzini 
183517ff12cSHalil Pasic extern const VMStateDescription vmstate_ind_addr;
184517ff12cSHalil Pasic 
185517ff12cSHalil Pasic #define VMSTATE_PTR_TO_IND_ADDR(_f, _s)                                   \
186517ff12cSHalil Pasic     VMSTATE_STRUCT(_f, _s, 1, vmstate_ind_addr, IndAddr*)
187517ff12cSHalil Pasic 
188bd3f16acSPaolo Bonzini IndAddr *get_indicator(hwaddr ind_addr, int len);
189bd3f16acSPaolo Bonzini void release_indicator(AdapterInfo *adapter, IndAddr *indicator);
190bd3f16acSPaolo Bonzini int map_indicator(AdapterInfo *adapter, IndAddr *indicator);
191bd3f16acSPaolo Bonzini 
192bd3f16acSPaolo Bonzini typedef SubchDev *(*css_subch_cb_func)(uint8_t m, uint8_t cssid, uint8_t ssid,
193bd3f16acSPaolo Bonzini                                        uint16_t schid);
194bd3f16acSPaolo Bonzini int css_create_css_image(uint8_t cssid, bool default_image);
195bd3f16acSPaolo Bonzini bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno);
196bd3f16acSPaolo Bonzini void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid,
197bd3f16acSPaolo Bonzini                       uint16_t devno, SubchDev *sch);
198bd3f16acSPaolo Bonzini void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type);
1998f3cf012SXiao Feng Ren int css_sch_build_schib(SubchDev *sch, CssDevId *dev_id);
2006c15e9bfSJing Liu unsigned int css_find_free_chpid(uint8_t cssid);
201bd3f16acSPaolo Bonzini uint16_t css_build_subchannel_id(SubchDev *sch);
2028ca2b376SXiao Feng Ren void copy_scsw_to_guest(SCSW *dest, const SCSW *src);
2038ca2b376SXiao Feng Ren void css_inject_io_interrupt(SubchDev *sch);
204bd3f16acSPaolo Bonzini void css_reset(void);
205bd3f16acSPaolo Bonzini void css_reset_sch(SubchDev *sch);
2065c8d6f00SDong Jia Shi void css_queue_crw(uint8_t rsc, uint8_t erc, int solicited,
2075c8d6f00SDong Jia Shi                    int chain, uint16_t rsid);
208bd3f16acSPaolo Bonzini void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid,
209bd3f16acSPaolo Bonzini                            int hotplugged, int add);
210bd3f16acSPaolo Bonzini void css_generate_chp_crws(uint8_t cssid, uint8_t chpid);
211bd3f16acSPaolo Bonzini void css_generate_css_crws(uint8_t cssid);
212bd3f16acSPaolo Bonzini void css_clear_sei_pending(void);
21366dc50f7SHalil Pasic IOInstEnding s390_ccw_cmd_request(SubchDev *sch);
21466dc50f7SHalil Pasic IOInstEnding do_subchannel_work_virtual(SubchDev *sub);
21566dc50f7SHalil Pasic IOInstEnding do_subchannel_work_passthrough(SubchDev *sub);
216bd3f16acSPaolo Bonzini 
2175b00bef2SFei Li typedef enum {
2185b00bef2SFei Li     CSS_IO_ADAPTER_VIRTIO = 0,
2195b00bef2SFei Li     CSS_IO_ADAPTER_PCI = 1,
2205b00bef2SFei Li     CSS_IO_ADAPTER_TYPE_NUMS,
2215b00bef2SFei Li } CssIoAdapterType;
2225b00bef2SFei Li 
22325a08b8dSYi Min Zhao void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc);
2242283f4d6SFei Li int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode);
225dde522bbSFei Li uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc);
226dde522bbSFei Li void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable,
2271497c160SFei Li                               uint8_t flags, Error **errp);
2281497c160SFei Li 
2291497c160SFei Li #ifndef CONFIG_KVM
2301497c160SFei Li #define S390_ADAPTER_SUPPRESSIBLE 0x01
2311497c160SFei Li #else
2321497c160SFei Li #define S390_ADAPTER_SUPPRESSIBLE KVM_S390_ADAPTER_SUPPRESSIBLE
2331497c160SFei Li #endif
234bd3f16acSPaolo Bonzini 
235bd3f16acSPaolo Bonzini #ifndef CONFIG_USER_ONLY
236bd3f16acSPaolo Bonzini SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
237bd3f16acSPaolo Bonzini                          uint16_t schid);
238bd3f16acSPaolo Bonzini bool css_subch_visible(SubchDev *sch);
239bd3f16acSPaolo Bonzini void css_conditional_io_interrupt(SubchDev *sch);
240bd3f16acSPaolo Bonzini int css_do_stsch(SubchDev *sch, SCHIB *schib);
241bd3f16acSPaolo Bonzini bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
2426bb6f194SHalil Pasic IOInstEnding css_do_msch(SubchDev *sch, const SCHIB *schib);
24396376408SHalil Pasic IOInstEnding css_do_xsch(SubchDev *sch);
24477331442SHalil Pasic IOInstEnding css_do_csch(SubchDev *sch);
245ae9f1be3SHalil Pasic IOInstEnding css_do_hsch(SubchDev *sch);
24666dc50f7SHalil Pasic IOInstEnding css_do_ssch(SubchDev *sch, ORB *orb);
247bd3f16acSPaolo Bonzini int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len);
248bd3f16acSPaolo Bonzini void css_do_tsch_update_subch(SubchDev *sch);
249bd3f16acSPaolo Bonzini int css_do_stcrw(CRW *crw);
250bd3f16acSPaolo Bonzini void css_undo_stcrw(CRW *crw);
251bd3f16acSPaolo Bonzini int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
252bd3f16acSPaolo Bonzini                          int rfmt, void *buf);
253bd3f16acSPaolo Bonzini void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
254bd3f16acSPaolo Bonzini int css_enable_mcsse(void);
255bd3f16acSPaolo Bonzini int css_enable_mss(void);
25666dc50f7SHalil Pasic IOInstEnding css_do_rsch(SubchDev *sch);
257bd3f16acSPaolo Bonzini int css_do_rchp(uint8_t cssid, uint8_t chpid);
258bd3f16acSPaolo Bonzini bool css_present(uint8_t cssid);
259bd3f16acSPaolo Bonzini #endif
260bd3f16acSPaolo Bonzini 
2611b6b7d10SFam Zheng extern const PropertyInfo css_devid_ro_propinfo;
262c35fc6aaSDong Jia Shi 
263c35fc6aaSDong Jia Shi #define DEFINE_PROP_CSS_DEV_ID_RO(_n, _s, _f) \
264c35fc6aaSDong Jia Shi     DEFINE_PROP(_n, _s, _f, css_devid_ro_propinfo, CssDevId)
265c35fc6aaSDong Jia Shi 
266cf249935SSascha Silbe /**
267cf249935SSascha Silbe  * Create a subchannel for the given bus id.
268cf249935SSascha Silbe  *
269817d4a6bSDong Jia Shi  * If @p bus_id is valid, and @p squash_mcss is true, verify that it is
270817d4a6bSDong Jia Shi  * not already in use in the default css, and find a free devno from the
271817d4a6bSDong Jia Shi  * default css image for it.
272817d4a6bSDong Jia Shi  * If @p bus_id is valid, and @p squash_mcss is false, verify that it is
273817d4a6bSDong Jia Shi  * not already in use, and find a free devno for it.
274*99577c49SHalil Pasic  * If @p bus_id is not valid find a free subchannel id and device number
275*99577c49SHalil Pasic  * across all subchannel sets and all css images starting from the default
276*99577c49SHalil Pasic  * css image.
277817d4a6bSDong Jia Shi  *
278817d4a6bSDong Jia Shi  * If either of the former actions succeed, allocate a subchannel structure,
279817d4a6bSDong Jia Shi  * initialise it with the bus id, subchannel id and device number, register
280817d4a6bSDong Jia Shi  * it with the CSS and return it. Otherwise return NULL.
281cf249935SSascha Silbe  *
282cf249935SSascha Silbe  * The caller becomes owner of the returned subchannel structure and
283cf249935SSascha Silbe  * is responsible for unregistering and freeing it.
284cf249935SSascha Silbe  */
285*99577c49SHalil Pasic SubchDev *css_create_sch(CssDevId bus_id, bool squash_mcss, Error **errp);
286e996583eSHalil Pasic 
287e996583eSHalil Pasic /** Turn on css migration */
288e996583eSHalil Pasic void css_register_vmstate(void);
289e996583eSHalil Pasic 
29057065a70SHalil Pasic 
29157065a70SHalil Pasic void ccw_dstream_init(CcwDataStream *cds, CCW1 const *ccw, ORB const *orb);
29257065a70SHalil Pasic 
29357065a70SHalil Pasic static inline void ccw_dstream_rewind(CcwDataStream *cds)
29457065a70SHalil Pasic {
29557065a70SHalil Pasic     cds->at_byte = 0;
29657065a70SHalil Pasic     cds->at_idaw = 0;
29757065a70SHalil Pasic     cds->cda = cds->cda_orig;
29857065a70SHalil Pasic }
29957065a70SHalil Pasic 
30057065a70SHalil Pasic static inline bool ccw_dstream_good(CcwDataStream *cds)
30157065a70SHalil Pasic {
30257065a70SHalil Pasic     return !(cds->flags & CDS_F_STREAM_BROKEN);
30357065a70SHalil Pasic }
30457065a70SHalil Pasic 
30557065a70SHalil Pasic static inline uint16_t ccw_dstream_residual_count(CcwDataStream *cds)
30657065a70SHalil Pasic {
30757065a70SHalil Pasic     return cds->count - cds->at_byte;
30857065a70SHalil Pasic }
30957065a70SHalil Pasic 
31057065a70SHalil Pasic static inline uint16_t ccw_dstream_avail(CcwDataStream *cds)
31157065a70SHalil Pasic {
31257065a70SHalil Pasic     return ccw_dstream_good(cds) ? ccw_dstream_residual_count(cds) : 0;
31357065a70SHalil Pasic }
31457065a70SHalil Pasic 
31557065a70SHalil Pasic static inline int ccw_dstream_advance(CcwDataStream *cds, int len)
31657065a70SHalil Pasic {
31757065a70SHalil Pasic     return cds->op_handler(cds, NULL, len, CDS_OP_A);
31857065a70SHalil Pasic }
31957065a70SHalil Pasic 
32057065a70SHalil Pasic static inline int ccw_dstream_write_buf(CcwDataStream *cds, void *buff, int len)
32157065a70SHalil Pasic {
32257065a70SHalil Pasic     return cds->op_handler(cds, buff, len, CDS_OP_W);
32357065a70SHalil Pasic }
32457065a70SHalil Pasic 
32557065a70SHalil Pasic static inline int ccw_dstream_read_buf(CcwDataStream *cds, void *buff, int len)
32657065a70SHalil Pasic {
32757065a70SHalil Pasic     return cds->op_handler(cds, buff, len, CDS_OP_R);
32857065a70SHalil Pasic }
32957065a70SHalil Pasic 
33057065a70SHalil Pasic #define ccw_dstream_read(cds, v) ccw_dstream_read_buf((cds), &(v), sizeof(v))
33157065a70SHalil Pasic #define ccw_dstream_write(cds, v) ccw_dstream_write_buf((cds), &(v), sizeof(v))
33257065a70SHalil Pasic 
333bd3f16acSPaolo Bonzini #endif
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