1bd3f16acSPaolo Bonzini /* 2bd3f16acSPaolo Bonzini * Channel subsystem structures and definitions. 3bd3f16acSPaolo Bonzini * 4bd3f16acSPaolo Bonzini * Copyright 2012 IBM Corp. 5bd3f16acSPaolo Bonzini * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com> 6bd3f16acSPaolo Bonzini * 7bd3f16acSPaolo Bonzini * This work is licensed under the terms of the GNU GPL, version 2 or (at 8bd3f16acSPaolo Bonzini * your option) any later version. See the COPYING file in the top-level 9bd3f16acSPaolo Bonzini * directory. 10bd3f16acSPaolo Bonzini */ 11bd3f16acSPaolo Bonzini 12bd3f16acSPaolo Bonzini #ifndef CSS_H 13bd3f16acSPaolo Bonzini #define CSS_H 14bd3f16acSPaolo Bonzini 152283f4d6SFei Li #include "cpu.h" 16bd3f16acSPaolo Bonzini #include "hw/s390x/adapter.h" 17bd3f16acSPaolo Bonzini #include "hw/s390x/s390_flic.h" 18bd3f16acSPaolo Bonzini #include "hw/s390x/ioinst.h" 19f16bbb9bSDavid Hildenbrand #include "sysemu/kvm.h" 20bd3f16acSPaolo Bonzini 21bd3f16acSPaolo Bonzini /* Channel subsystem constants. */ 22cf249935SSascha Silbe #define MAX_DEVNO 65535 23bd3f16acSPaolo Bonzini #define MAX_SCHID 65535 24bd3f16acSPaolo Bonzini #define MAX_SSID 3 25882b3b97SCornelia Huck #define MAX_CSSID 255 26bd3f16acSPaolo Bonzini #define MAX_CHPID 255 27bd3f16acSPaolo Bonzini 28dde522bbSFei Li #define MAX_ISC 7 29dde522bbSFei Li 30bd3f16acSPaolo Bonzini #define MAX_CIWS 62 31bd3f16acSPaolo Bonzini 32cf249935SSascha Silbe #define VIRTUAL_CSSID 0xfe 336c15e9bfSJing Liu #define VIRTIO_CCW_CHPID 0 /* used by convention */ 34cf249935SSascha Silbe 35bd3f16acSPaolo Bonzini typedef struct CIW { 36bd3f16acSPaolo Bonzini uint8_t type; 37bd3f16acSPaolo Bonzini uint8_t command; 38bd3f16acSPaolo Bonzini uint16_t count; 39bd3f16acSPaolo Bonzini } QEMU_PACKED CIW; 40bd3f16acSPaolo Bonzini 41bd3f16acSPaolo Bonzini typedef struct SenseId { 42bd3f16acSPaolo Bonzini /* common part */ 43bd3f16acSPaolo Bonzini uint8_t reserved; /* always 0x'FF' */ 44bd3f16acSPaolo Bonzini uint16_t cu_type; /* control unit type */ 45bd3f16acSPaolo Bonzini uint8_t cu_model; /* control unit model */ 46bd3f16acSPaolo Bonzini uint16_t dev_type; /* device type */ 47bd3f16acSPaolo Bonzini uint8_t dev_model; /* device model */ 48bd3f16acSPaolo Bonzini uint8_t unused; /* padding byte */ 49bd3f16acSPaolo Bonzini /* extended part */ 50bd3f16acSPaolo Bonzini CIW ciw[MAX_CIWS]; /* variable # of CIWs */ 51bd3f16acSPaolo Bonzini } QEMU_PACKED SenseId; 52bd3f16acSPaolo Bonzini 53bd3f16acSPaolo Bonzini /* Channel measurements, from linux/drivers/s390/cio/cmf.c. */ 54bd3f16acSPaolo Bonzini typedef struct CMB { 55bd3f16acSPaolo Bonzini uint16_t ssch_rsch_count; 56bd3f16acSPaolo Bonzini uint16_t sample_count; 57bd3f16acSPaolo Bonzini uint32_t device_connect_time; 58bd3f16acSPaolo Bonzini uint32_t function_pending_time; 59bd3f16acSPaolo Bonzini uint32_t device_disconnect_time; 60bd3f16acSPaolo Bonzini uint32_t control_unit_queuing_time; 61bd3f16acSPaolo Bonzini uint32_t device_active_only_time; 62bd3f16acSPaolo Bonzini uint32_t reserved[2]; 63bd3f16acSPaolo Bonzini } QEMU_PACKED CMB; 64bd3f16acSPaolo Bonzini 65bd3f16acSPaolo Bonzini typedef struct CMBE { 66bd3f16acSPaolo Bonzini uint32_t ssch_rsch_count; 67bd3f16acSPaolo Bonzini uint32_t sample_count; 68bd3f16acSPaolo Bonzini uint32_t device_connect_time; 69bd3f16acSPaolo Bonzini uint32_t function_pending_time; 70bd3f16acSPaolo Bonzini uint32_t device_disconnect_time; 71bd3f16acSPaolo Bonzini uint32_t control_unit_queuing_time; 72bd3f16acSPaolo Bonzini uint32_t device_active_only_time; 73bd3f16acSPaolo Bonzini uint32_t device_busy_time; 74bd3f16acSPaolo Bonzini uint32_t initial_command_response_time; 75bd3f16acSPaolo Bonzini uint32_t reserved[7]; 76bd3f16acSPaolo Bonzini } QEMU_PACKED CMBE; 77bd3f16acSPaolo Bonzini 7857065a70SHalil Pasic typedef enum CcwDataStreamOp { 7957065a70SHalil Pasic CDS_OP_R = 0, /* read, false when used as is_write */ 8057065a70SHalil Pasic CDS_OP_W = 1, /* write, true when used as is_write */ 8157065a70SHalil Pasic CDS_OP_A = 2 /* advance, should not be used as is_write */ 8257065a70SHalil Pasic } CcwDataStreamOp; 8357065a70SHalil Pasic 8457065a70SHalil Pasic /* normal usage is via SuchchDev.cds instead of instantiating */ 8557065a70SHalil Pasic typedef struct CcwDataStream { 8657065a70SHalil Pasic #define CDS_F_IDA 0x01 8757065a70SHalil Pasic #define CDS_F_MIDA 0x02 8857065a70SHalil Pasic #define CDS_F_I2K 0x04 8957065a70SHalil Pasic #define CDS_F_C64 0x08 90*62a2554eSHalil Pasic #define CDS_F_FMT 0x10 /* CCW format-1 */ 9157065a70SHalil Pasic #define CDS_F_STREAM_BROKEN 0x80 9257065a70SHalil Pasic uint8_t flags; 9357065a70SHalil Pasic uint8_t at_idaw; 9457065a70SHalil Pasic uint16_t at_byte; 9557065a70SHalil Pasic uint16_t count; 9657065a70SHalil Pasic uint32_t cda_orig; 9757065a70SHalil Pasic int (*op_handler)(struct CcwDataStream *cds, void *buff, int len, 9857065a70SHalil Pasic CcwDataStreamOp op); 9957065a70SHalil Pasic hwaddr cda; 10057065a70SHalil Pasic } CcwDataStream; 10157065a70SHalil Pasic 102bd3f16acSPaolo Bonzini typedef struct SubchDev SubchDev; 103bd3f16acSPaolo Bonzini struct SubchDev { 104bd3f16acSPaolo Bonzini /* channel-subsystem related things: */ 105bd3f16acSPaolo Bonzini uint8_t cssid; 106bd3f16acSPaolo Bonzini uint8_t ssid; 107bd3f16acSPaolo Bonzini uint16_t schid; 108bd3f16acSPaolo Bonzini uint16_t devno; 109bd3f16acSPaolo Bonzini SCHIB curr_status; 110bd3f16acSPaolo Bonzini uint8_t sense_data[32]; 111bd3f16acSPaolo Bonzini hwaddr channel_prog; 112bd3f16acSPaolo Bonzini CCW1 last_cmd; 113bd3f16acSPaolo Bonzini bool last_cmd_valid; 114bd3f16acSPaolo Bonzini bool ccw_fmt_1; 115bd3f16acSPaolo Bonzini bool thinint_active; 116bd3f16acSPaolo Bonzini uint8_t ccw_no_data_cnt; 117517ff12cSHalil Pasic uint16_t migrated_schid; /* used for missmatch detection */ 118ff443fe6SHalil Pasic ORB orb; 11957065a70SHalil Pasic CcwDataStream cds; 120bd3f16acSPaolo Bonzini /* transport-provided data: */ 121bd3f16acSPaolo Bonzini int (*ccw_cb) (SubchDev *, CCW1); 122bd3f16acSPaolo Bonzini void (*disable_cb)(SubchDev *); 123b5f5a3afSHalil Pasic int (*do_subchannel_work) (SubchDev *); 124bd3f16acSPaolo Bonzini SenseId id; 125bd3f16acSPaolo Bonzini void *driver_data; 126bd3f16acSPaolo Bonzini }; 127bd3f16acSPaolo Bonzini 128517ff12cSHalil Pasic extern const VMStateDescription vmstate_subch_dev; 129517ff12cSHalil Pasic 1308f3cf012SXiao Feng Ren /* 1318f3cf012SXiao Feng Ren * Identify a device within the channel subsystem. 1328f3cf012SXiao Feng Ren * Note that this can be used to identify either the subchannel or 1338f3cf012SXiao Feng Ren * the attached I/O device, as there's always one I/O device per 1348f3cf012SXiao Feng Ren * subchannel. 1358f3cf012SXiao Feng Ren */ 1368f3cf012SXiao Feng Ren typedef struct CssDevId { 1378f3cf012SXiao Feng Ren uint8_t cssid; 1388f3cf012SXiao Feng Ren uint8_t ssid; 1398f3cf012SXiao Feng Ren uint16_t devid; 1408f3cf012SXiao Feng Ren bool valid; 1418f3cf012SXiao Feng Ren } CssDevId; 1428f3cf012SXiao Feng Ren 1431b6b7d10SFam Zheng extern const PropertyInfo css_devid_propinfo; 1448f3cf012SXiao Feng Ren 1458f3cf012SXiao Feng Ren #define DEFINE_PROP_CSS_DEV_ID(_n, _s, _f) \ 1468f3cf012SXiao Feng Ren DEFINE_PROP(_n, _s, _f, css_devid_propinfo, CssDevId) 1478f3cf012SXiao Feng Ren 148bd3f16acSPaolo Bonzini typedef struct IndAddr { 149bd3f16acSPaolo Bonzini hwaddr addr; 150bd3f16acSPaolo Bonzini uint64_t map; 151bd3f16acSPaolo Bonzini unsigned long refcnt; 152517ff12cSHalil Pasic int32_t len; 153bd3f16acSPaolo Bonzini QTAILQ_ENTRY(IndAddr) sibling; 154bd3f16acSPaolo Bonzini } IndAddr; 155bd3f16acSPaolo Bonzini 156517ff12cSHalil Pasic extern const VMStateDescription vmstate_ind_addr; 157517ff12cSHalil Pasic 158517ff12cSHalil Pasic #define VMSTATE_PTR_TO_IND_ADDR(_f, _s) \ 159517ff12cSHalil Pasic VMSTATE_STRUCT(_f, _s, 1, vmstate_ind_addr, IndAddr*) 160517ff12cSHalil Pasic 161bd3f16acSPaolo Bonzini IndAddr *get_indicator(hwaddr ind_addr, int len); 162bd3f16acSPaolo Bonzini void release_indicator(AdapterInfo *adapter, IndAddr *indicator); 163bd3f16acSPaolo Bonzini int map_indicator(AdapterInfo *adapter, IndAddr *indicator); 164bd3f16acSPaolo Bonzini 165bd3f16acSPaolo Bonzini typedef SubchDev *(*css_subch_cb_func)(uint8_t m, uint8_t cssid, uint8_t ssid, 166bd3f16acSPaolo Bonzini uint16_t schid); 167bd3f16acSPaolo Bonzini int css_create_css_image(uint8_t cssid, bool default_image); 168bd3f16acSPaolo Bonzini bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno); 169bd3f16acSPaolo Bonzini void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid, 170bd3f16acSPaolo Bonzini uint16_t devno, SubchDev *sch); 171bd3f16acSPaolo Bonzini void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type); 1728f3cf012SXiao Feng Ren int css_sch_build_schib(SubchDev *sch, CssDevId *dev_id); 1736c15e9bfSJing Liu unsigned int css_find_free_chpid(uint8_t cssid); 174bd3f16acSPaolo Bonzini uint16_t css_build_subchannel_id(SubchDev *sch); 1758ca2b376SXiao Feng Ren void copy_scsw_to_guest(SCSW *dest, const SCSW *src); 1768ca2b376SXiao Feng Ren void css_inject_io_interrupt(SubchDev *sch); 177bd3f16acSPaolo Bonzini void css_reset(void); 178bd3f16acSPaolo Bonzini void css_reset_sch(SubchDev *sch); 1795c8d6f00SDong Jia Shi void css_queue_crw(uint8_t rsc, uint8_t erc, int solicited, 1805c8d6f00SDong Jia Shi int chain, uint16_t rsid); 181bd3f16acSPaolo Bonzini void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid, 182bd3f16acSPaolo Bonzini int hotplugged, int add); 183bd3f16acSPaolo Bonzini void css_generate_chp_crws(uint8_t cssid, uint8_t chpid); 184bd3f16acSPaolo Bonzini void css_generate_css_crws(uint8_t cssid); 185bd3f16acSPaolo Bonzini void css_clear_sei_pending(void); 186bab482d7SXiao Feng Ren int s390_ccw_cmd_request(ORB *orb, SCSW *scsw, void *data); 187b5f5a3afSHalil Pasic int do_subchannel_work_virtual(SubchDev *sub); 188b5f5a3afSHalil Pasic int do_subchannel_work_passthrough(SubchDev *sub); 189bd3f16acSPaolo Bonzini 1905b00bef2SFei Li typedef enum { 1915b00bef2SFei Li CSS_IO_ADAPTER_VIRTIO = 0, 1925b00bef2SFei Li CSS_IO_ADAPTER_PCI = 1, 1935b00bef2SFei Li CSS_IO_ADAPTER_TYPE_NUMS, 1945b00bef2SFei Li } CssIoAdapterType; 1955b00bef2SFei Li 19625a08b8dSYi Min Zhao void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc); 1972283f4d6SFei Li int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode); 198dde522bbSFei Li uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc); 199dde522bbSFei Li void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable, 2001497c160SFei Li uint8_t flags, Error **errp); 2011497c160SFei Li 2021497c160SFei Li #ifndef CONFIG_KVM 2031497c160SFei Li #define S390_ADAPTER_SUPPRESSIBLE 0x01 2041497c160SFei Li #else 2051497c160SFei Li #define S390_ADAPTER_SUPPRESSIBLE KVM_S390_ADAPTER_SUPPRESSIBLE 2061497c160SFei Li #endif 207bd3f16acSPaolo Bonzini 208bd3f16acSPaolo Bonzini #ifndef CONFIG_USER_ONLY 209bd3f16acSPaolo Bonzini SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid, 210bd3f16acSPaolo Bonzini uint16_t schid); 211bd3f16acSPaolo Bonzini bool css_subch_visible(SubchDev *sch); 212bd3f16acSPaolo Bonzini void css_conditional_io_interrupt(SubchDev *sch); 213bd3f16acSPaolo Bonzini int css_do_stsch(SubchDev *sch, SCHIB *schib); 214bd3f16acSPaolo Bonzini bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid); 215bd3f16acSPaolo Bonzini int css_do_msch(SubchDev *sch, const SCHIB *schib); 216bd3f16acSPaolo Bonzini int css_do_xsch(SubchDev *sch); 217bd3f16acSPaolo Bonzini int css_do_csch(SubchDev *sch); 218bd3f16acSPaolo Bonzini int css_do_hsch(SubchDev *sch); 219bd3f16acSPaolo Bonzini int css_do_ssch(SubchDev *sch, ORB *orb); 220bd3f16acSPaolo Bonzini int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len); 221bd3f16acSPaolo Bonzini void css_do_tsch_update_subch(SubchDev *sch); 222bd3f16acSPaolo Bonzini int css_do_stcrw(CRW *crw); 223bd3f16acSPaolo Bonzini void css_undo_stcrw(CRW *crw); 224bd3f16acSPaolo Bonzini int css_do_tpi(IOIntCode *int_code, int lowcore); 225bd3f16acSPaolo Bonzini int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid, 226bd3f16acSPaolo Bonzini int rfmt, void *buf); 227bd3f16acSPaolo Bonzini void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo); 228bd3f16acSPaolo Bonzini int css_enable_mcsse(void); 229bd3f16acSPaolo Bonzini int css_enable_mss(void); 230bd3f16acSPaolo Bonzini int css_do_rsch(SubchDev *sch); 231bd3f16acSPaolo Bonzini int css_do_rchp(uint8_t cssid, uint8_t chpid); 232bd3f16acSPaolo Bonzini bool css_present(uint8_t cssid); 233bd3f16acSPaolo Bonzini #endif 234bd3f16acSPaolo Bonzini 2351b6b7d10SFam Zheng extern const PropertyInfo css_devid_ro_propinfo; 236c35fc6aaSDong Jia Shi 237c35fc6aaSDong Jia Shi #define DEFINE_PROP_CSS_DEV_ID_RO(_n, _s, _f) \ 238c35fc6aaSDong Jia Shi DEFINE_PROP(_n, _s, _f, css_devid_ro_propinfo, CssDevId) 239c35fc6aaSDong Jia Shi 240cf249935SSascha Silbe /** 241cf249935SSascha Silbe * Create a subchannel for the given bus id. 242cf249935SSascha Silbe * 243817d4a6bSDong Jia Shi * If @p bus_id is valid, and @p squash_mcss is true, verify that it is 244817d4a6bSDong Jia Shi * not already in use in the default css, and find a free devno from the 245817d4a6bSDong Jia Shi * default css image for it. 246817d4a6bSDong Jia Shi * If @p bus_id is valid, and @p squash_mcss is false, verify that it is 247817d4a6bSDong Jia Shi * not already in use, and find a free devno for it. 248817d4a6bSDong Jia Shi * If @p bus_id is not valid, and if either @p squash_mcss or @p is_virtual 249817d4a6bSDong Jia Shi * is true, find a free subchannel id and device number across all 250817d4a6bSDong Jia Shi * subchannel sets from the default css image. 251817d4a6bSDong Jia Shi * If @p bus_id is not valid, and if both @p squash_mcss and @p is_virtual 252817d4a6bSDong Jia Shi * are false, find a non-full css image and find a free subchannel id and 253817d4a6bSDong Jia Shi * device number across all subchannel sets from it. 254817d4a6bSDong Jia Shi * 255817d4a6bSDong Jia Shi * If either of the former actions succeed, allocate a subchannel structure, 256817d4a6bSDong Jia Shi * initialise it with the bus id, subchannel id and device number, register 257817d4a6bSDong Jia Shi * it with the CSS and return it. Otherwise return NULL. 258cf249935SSascha Silbe * 259cf249935SSascha Silbe * The caller becomes owner of the returned subchannel structure and 260cf249935SSascha Silbe * is responsible for unregistering and freeing it. 261cf249935SSascha Silbe */ 262817d4a6bSDong Jia Shi SubchDev *css_create_sch(CssDevId bus_id, bool is_virtual, bool squash_mcss, 263817d4a6bSDong Jia Shi Error **errp); 264e996583eSHalil Pasic 265e996583eSHalil Pasic /** Turn on css migration */ 266e996583eSHalil Pasic void css_register_vmstate(void); 267e996583eSHalil Pasic 26857065a70SHalil Pasic 26957065a70SHalil Pasic void ccw_dstream_init(CcwDataStream *cds, CCW1 const *ccw, ORB const *orb); 27057065a70SHalil Pasic 27157065a70SHalil Pasic static inline void ccw_dstream_rewind(CcwDataStream *cds) 27257065a70SHalil Pasic { 27357065a70SHalil Pasic cds->at_byte = 0; 27457065a70SHalil Pasic cds->at_idaw = 0; 27557065a70SHalil Pasic cds->cda = cds->cda_orig; 27657065a70SHalil Pasic } 27757065a70SHalil Pasic 27857065a70SHalil Pasic static inline bool ccw_dstream_good(CcwDataStream *cds) 27957065a70SHalil Pasic { 28057065a70SHalil Pasic return !(cds->flags & CDS_F_STREAM_BROKEN); 28157065a70SHalil Pasic } 28257065a70SHalil Pasic 28357065a70SHalil Pasic static inline uint16_t ccw_dstream_residual_count(CcwDataStream *cds) 28457065a70SHalil Pasic { 28557065a70SHalil Pasic return cds->count - cds->at_byte; 28657065a70SHalil Pasic } 28757065a70SHalil Pasic 28857065a70SHalil Pasic static inline uint16_t ccw_dstream_avail(CcwDataStream *cds) 28957065a70SHalil Pasic { 29057065a70SHalil Pasic return ccw_dstream_good(cds) ? ccw_dstream_residual_count(cds) : 0; 29157065a70SHalil Pasic } 29257065a70SHalil Pasic 29357065a70SHalil Pasic static inline int ccw_dstream_advance(CcwDataStream *cds, int len) 29457065a70SHalil Pasic { 29557065a70SHalil Pasic return cds->op_handler(cds, NULL, len, CDS_OP_A); 29657065a70SHalil Pasic } 29757065a70SHalil Pasic 29857065a70SHalil Pasic static inline int ccw_dstream_write_buf(CcwDataStream *cds, void *buff, int len) 29957065a70SHalil Pasic { 30057065a70SHalil Pasic return cds->op_handler(cds, buff, len, CDS_OP_W); 30157065a70SHalil Pasic } 30257065a70SHalil Pasic 30357065a70SHalil Pasic static inline int ccw_dstream_read_buf(CcwDataStream *cds, void *buff, int len) 30457065a70SHalil Pasic { 30557065a70SHalil Pasic return cds->op_handler(cds, buff, len, CDS_OP_R); 30657065a70SHalil Pasic } 30757065a70SHalil Pasic 30857065a70SHalil Pasic #define ccw_dstream_read(cds, v) ccw_dstream_read_buf((cds), &(v), sizeof(v)) 30957065a70SHalil Pasic #define ccw_dstream_write(cds, v) ccw_dstream_write_buf((cds), &(v), sizeof(v)) 31057065a70SHalil Pasic 311bd3f16acSPaolo Bonzini #endif 312