10d09e41aSPaolo Bonzini /* 20d09e41aSPaolo Bonzini * QEMU Common PCI Host bridge configuration data space access routines. 30d09e41aSPaolo Bonzini * 40d09e41aSPaolo Bonzini * Copyright (c) 2006 Fabrice Bellard 50d09e41aSPaolo Bonzini * 60d09e41aSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 70d09e41aSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 80d09e41aSPaolo Bonzini * in the Software without restriction, including without limitation the rights 90d09e41aSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 100d09e41aSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 110d09e41aSPaolo Bonzini * furnished to do so, subject to the following conditions: 120d09e41aSPaolo Bonzini * 130d09e41aSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 140d09e41aSPaolo Bonzini * all copies or substantial portions of the Software. 150d09e41aSPaolo Bonzini * 160d09e41aSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 170d09e41aSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 180d09e41aSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 190d09e41aSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 200d09e41aSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 210d09e41aSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 220d09e41aSPaolo Bonzini * THE SOFTWARE. 230d09e41aSPaolo Bonzini */ 240d09e41aSPaolo Bonzini 250d09e41aSPaolo Bonzini /* Worker routines for a PCI host controller that uses an {address,data} 260d09e41aSPaolo Bonzini register pair to access PCI configuration space. */ 270d09e41aSPaolo Bonzini 280d09e41aSPaolo Bonzini #ifndef PCI_HOST_H 290d09e41aSPaolo Bonzini #define PCI_HOST_H 300d09e41aSPaolo Bonzini 310d09e41aSPaolo Bonzini #include "hw/sysbus.h" 32*db1015e9SEduardo Habkost #include "qom/object.h" 330d09e41aSPaolo Bonzini 340d09e41aSPaolo Bonzini #define TYPE_PCI_HOST_BRIDGE "pci-host-bridge" 35*db1015e9SEduardo Habkost typedef struct PCIHostBridgeClass PCIHostBridgeClass; 360d09e41aSPaolo Bonzini #define PCI_HOST_BRIDGE(obj) \ 370d09e41aSPaolo Bonzini OBJECT_CHECK(PCIHostState, (obj), TYPE_PCI_HOST_BRIDGE) 38568f0690SDavid Gibson #define PCI_HOST_BRIDGE_CLASS(klass) \ 39568f0690SDavid Gibson OBJECT_CLASS_CHECK(PCIHostBridgeClass, (klass), TYPE_PCI_HOST_BRIDGE) 40568f0690SDavid Gibson #define PCI_HOST_BRIDGE_GET_CLASS(obj) \ 41568f0690SDavid Gibson OBJECT_GET_CLASS(PCIHostBridgeClass, (obj), TYPE_PCI_HOST_BRIDGE) 420d09e41aSPaolo Bonzini 430d09e41aSPaolo Bonzini struct PCIHostState { 440d09e41aSPaolo Bonzini SysBusDevice busdev; 450d09e41aSPaolo Bonzini 460d09e41aSPaolo Bonzini MemoryRegion conf_mem; 470d09e41aSPaolo Bonzini MemoryRegion data_mem; 480d09e41aSPaolo Bonzini MemoryRegion mmcfg; 490d09e41aSPaolo Bonzini uint32_t config_reg; 502ebc2121SHogan Wang bool mig_enabled; 510d09e41aSPaolo Bonzini PCIBus *bus; 527588e2b0SDavid Gibson 537588e2b0SDavid Gibson QLIST_ENTRY(PCIHostState) next; 540d09e41aSPaolo Bonzini }; 550d09e41aSPaolo Bonzini 56*db1015e9SEduardo Habkost struct PCIHostBridgeClass { 57568f0690SDavid Gibson SysBusDeviceClass parent_class; 58568f0690SDavid Gibson 59568f0690SDavid Gibson const char *(*root_bus_path)(PCIHostState *, PCIBus *); 60*db1015e9SEduardo Habkost }; 61568f0690SDavid Gibson 620d09e41aSPaolo Bonzini /* common internal helpers for PCI/PCIe hosts, cut off overflows */ 630d09e41aSPaolo Bonzini void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr, 640d09e41aSPaolo Bonzini uint32_t limit, uint32_t val, uint32_t len); 650d09e41aSPaolo Bonzini uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr, 660d09e41aSPaolo Bonzini uint32_t limit, uint32_t len); 670d09e41aSPaolo Bonzini 68f2a7e8f1SPhilippe Mathieu-Daudé void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, unsigned len); 69f2a7e8f1SPhilippe Mathieu-Daudé uint32_t pci_data_read(PCIBus *s, uint32_t addr, unsigned len); 700d09e41aSPaolo Bonzini 710d09e41aSPaolo Bonzini extern const MemoryRegionOps pci_host_conf_le_ops; 720d09e41aSPaolo Bonzini extern const MemoryRegionOps pci_host_conf_be_ops; 730d09e41aSPaolo Bonzini extern const MemoryRegionOps pci_host_data_le_ops; 740d09e41aSPaolo Bonzini extern const MemoryRegionOps pci_host_data_be_ops; 750d09e41aSPaolo Bonzini 760d09e41aSPaolo Bonzini #endif /* PCI_HOST_H */ 77