1*0d09e41aSPaolo Bonzini /* 2*0d09e41aSPaolo Bonzini * QEMU Common PCI Host bridge configuration data space access routines. 3*0d09e41aSPaolo Bonzini * 4*0d09e41aSPaolo Bonzini * Copyright (c) 2006 Fabrice Bellard 5*0d09e41aSPaolo Bonzini * 6*0d09e41aSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 7*0d09e41aSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 8*0d09e41aSPaolo Bonzini * in the Software without restriction, including without limitation the rights 9*0d09e41aSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10*0d09e41aSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 11*0d09e41aSPaolo Bonzini * furnished to do so, subject to the following conditions: 12*0d09e41aSPaolo Bonzini * 13*0d09e41aSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 14*0d09e41aSPaolo Bonzini * all copies or substantial portions of the Software. 15*0d09e41aSPaolo Bonzini * 16*0d09e41aSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17*0d09e41aSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18*0d09e41aSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19*0d09e41aSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20*0d09e41aSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21*0d09e41aSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22*0d09e41aSPaolo Bonzini * THE SOFTWARE. 23*0d09e41aSPaolo Bonzini */ 24*0d09e41aSPaolo Bonzini 25*0d09e41aSPaolo Bonzini /* Worker routines for a PCI host controller that uses an {address,data} 26*0d09e41aSPaolo Bonzini register pair to access PCI configuration space. */ 27*0d09e41aSPaolo Bonzini 28*0d09e41aSPaolo Bonzini #ifndef PCI_HOST_H 29*0d09e41aSPaolo Bonzini #define PCI_HOST_H 30*0d09e41aSPaolo Bonzini 31*0d09e41aSPaolo Bonzini #include "hw/sysbus.h" 32*0d09e41aSPaolo Bonzini 33*0d09e41aSPaolo Bonzini #define TYPE_PCI_HOST_BRIDGE "pci-host-bridge" 34*0d09e41aSPaolo Bonzini #define PCI_HOST_BRIDGE(obj) \ 35*0d09e41aSPaolo Bonzini OBJECT_CHECK(PCIHostState, (obj), TYPE_PCI_HOST_BRIDGE) 36*0d09e41aSPaolo Bonzini 37*0d09e41aSPaolo Bonzini struct PCIHostState { 38*0d09e41aSPaolo Bonzini SysBusDevice busdev; 39*0d09e41aSPaolo Bonzini 40*0d09e41aSPaolo Bonzini MemoryRegion conf_mem; 41*0d09e41aSPaolo Bonzini MemoryRegion data_mem; 42*0d09e41aSPaolo Bonzini MemoryRegion mmcfg; 43*0d09e41aSPaolo Bonzini uint32_t config_reg; 44*0d09e41aSPaolo Bonzini PCIBus *bus; 45*0d09e41aSPaolo Bonzini }; 46*0d09e41aSPaolo Bonzini 47*0d09e41aSPaolo Bonzini /* common internal helpers for PCI/PCIe hosts, cut off overflows */ 48*0d09e41aSPaolo Bonzini void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr, 49*0d09e41aSPaolo Bonzini uint32_t limit, uint32_t val, uint32_t len); 50*0d09e41aSPaolo Bonzini uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr, 51*0d09e41aSPaolo Bonzini uint32_t limit, uint32_t len); 52*0d09e41aSPaolo Bonzini 53*0d09e41aSPaolo Bonzini void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len); 54*0d09e41aSPaolo Bonzini uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len); 55*0d09e41aSPaolo Bonzini 56*0d09e41aSPaolo Bonzini extern const MemoryRegionOps pci_host_conf_le_ops; 57*0d09e41aSPaolo Bonzini extern const MemoryRegionOps pci_host_conf_be_ops; 58*0d09e41aSPaolo Bonzini extern const MemoryRegionOps pci_host_data_le_ops; 59*0d09e41aSPaolo Bonzini extern const MemoryRegionOps pci_host_data_be_ops; 60*0d09e41aSPaolo Bonzini 61*0d09e41aSPaolo Bonzini #endif /* PCI_HOST_H */ 62