198e5d7a2SVikram Garhwal /* 298e5d7a2SVikram Garhwal * QEMU model of the Xilinx ZynqMP CAN controller. 398e5d7a2SVikram Garhwal * 498e5d7a2SVikram Garhwal * Copyright (c) 2020 Xilinx Inc. 598e5d7a2SVikram Garhwal * 698e5d7a2SVikram Garhwal * Written-by: Vikram Garhwal<fnu.vikram@xilinx.com> 798e5d7a2SVikram Garhwal * 898e5d7a2SVikram Garhwal * Based on QEMU CAN Device emulation implemented by Jin Yang, Deniz Eren and 998e5d7a2SVikram Garhwal * Pavel Pisa. 1098e5d7a2SVikram Garhwal * 1198e5d7a2SVikram Garhwal * Permission is hereby granted, free of charge, to any person obtaining a copy 1298e5d7a2SVikram Garhwal * of this software and associated documentation files (the "Software"), to deal 1398e5d7a2SVikram Garhwal * in the Software without restriction, including without limitation the rights 1498e5d7a2SVikram Garhwal * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1598e5d7a2SVikram Garhwal * copies of the Software, and to permit persons to whom the Software is 1698e5d7a2SVikram Garhwal * furnished to do so, subject to the following conditions: 1798e5d7a2SVikram Garhwal * 1898e5d7a2SVikram Garhwal * The above copyright notice and this permission notice shall be included in 1998e5d7a2SVikram Garhwal * all copies or substantial portions of the Software. 2098e5d7a2SVikram Garhwal * 2198e5d7a2SVikram Garhwal * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 2298e5d7a2SVikram Garhwal * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2398e5d7a2SVikram Garhwal * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2498e5d7a2SVikram Garhwal * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2598e5d7a2SVikram Garhwal * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2698e5d7a2SVikram Garhwal * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2798e5d7a2SVikram Garhwal * THE SOFTWARE. 2898e5d7a2SVikram Garhwal */ 2998e5d7a2SVikram Garhwal 3098e5d7a2SVikram Garhwal #ifndef XLNX_ZYNQMP_CAN_H 3198e5d7a2SVikram Garhwal #define XLNX_ZYNQMP_CAN_H 3298e5d7a2SVikram Garhwal 33*7a5951f6SMarkus Armbruster #include "hw/sysbus.h" 3498e5d7a2SVikram Garhwal #include "hw/register.h" 3598e5d7a2SVikram Garhwal #include "net/can_emu.h" 3698e5d7a2SVikram Garhwal #include "net/can_host.h" 3798e5d7a2SVikram Garhwal #include "qemu/fifo32.h" 3898e5d7a2SVikram Garhwal #include "hw/ptimer.h" 3998e5d7a2SVikram Garhwal #include "hw/qdev-clock.h" 4098e5d7a2SVikram Garhwal 4198e5d7a2SVikram Garhwal #define TYPE_XLNX_ZYNQMP_CAN "xlnx.zynqmp-can" 4298e5d7a2SVikram Garhwal 4398e5d7a2SVikram Garhwal #define XLNX_ZYNQMP_CAN(obj) \ 4498e5d7a2SVikram Garhwal OBJECT_CHECK(XlnxZynqMPCANState, (obj), TYPE_XLNX_ZYNQMP_CAN) 4598e5d7a2SVikram Garhwal 4698e5d7a2SVikram Garhwal #define MAX_CAN_CTRLS 2 4798e5d7a2SVikram Garhwal #define XLNX_ZYNQMP_CAN_R_MAX (0x84 / 4) 4898e5d7a2SVikram Garhwal #define MAILBOX_CAPACITY 64 4998e5d7a2SVikram Garhwal #define CAN_TIMER_MAX 0XFFFFUL 5098e5d7a2SVikram Garhwal #define CAN_DEFAULT_CLOCK (24 * 1000 * 1000) 5198e5d7a2SVikram Garhwal 5298e5d7a2SVikram Garhwal /* Each CAN_FRAME will have 4 * 32bit size. */ 5398e5d7a2SVikram Garhwal #define CAN_FRAME_SIZE 4 5498e5d7a2SVikram Garhwal #define RXFIFO_SIZE (MAILBOX_CAPACITY * CAN_FRAME_SIZE) 5598e5d7a2SVikram Garhwal 5698e5d7a2SVikram Garhwal typedef struct XlnxZynqMPCANState { 5798e5d7a2SVikram Garhwal SysBusDevice parent_obj; 5898e5d7a2SVikram Garhwal MemoryRegion iomem; 5998e5d7a2SVikram Garhwal 6098e5d7a2SVikram Garhwal qemu_irq irq; 6198e5d7a2SVikram Garhwal 6298e5d7a2SVikram Garhwal CanBusClientState bus_client; 6398e5d7a2SVikram Garhwal CanBusState *canbus; 6498e5d7a2SVikram Garhwal 6598e5d7a2SVikram Garhwal struct { 6698e5d7a2SVikram Garhwal uint32_t ext_clk_freq; 6798e5d7a2SVikram Garhwal } cfg; 6898e5d7a2SVikram Garhwal 6998e5d7a2SVikram Garhwal RegisterInfo reg_info[XLNX_ZYNQMP_CAN_R_MAX]; 7098e5d7a2SVikram Garhwal uint32_t regs[XLNX_ZYNQMP_CAN_R_MAX]; 7198e5d7a2SVikram Garhwal 7298e5d7a2SVikram Garhwal Fifo32 rx_fifo; 7398e5d7a2SVikram Garhwal Fifo32 tx_fifo; 7498e5d7a2SVikram Garhwal Fifo32 txhpb_fifo; 7598e5d7a2SVikram Garhwal 7698e5d7a2SVikram Garhwal ptimer_state *can_timer; 7798e5d7a2SVikram Garhwal } XlnxZynqMPCANState; 7898e5d7a2SVikram Garhwal 7998e5d7a2SVikram Garhwal #endif 80